opcodes/ChangeLog

   1 2021-03-25  Alan Modra  <amodra@gmail.com>
   2
   3         PR 27647
   4         * ppc-opc.c (XLOCB_MASK): Delete.
   5         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
   6         XLBH_MASK.
   7         (powerpc_opcodes): Accept a BH field on all extended forms of
   8         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
   9
  10 2021-03-24  Jan Beulich  <jbeulich@suse.com>
  11
  12         * i386-gen.c (output_i386_opcode): Drop processing of
  13         opcode_length. Calculate length from base_opcode. Adjust prefix
  14         encoding determination.
  15         (process_i386_opcodes): Drop output of fake opcode_length.
  16         * i386-opc.h (struct insn_template): Drop opcode_length field.
  17         * i386-opc.tbl: Drop opcode length field from all templates.
  18         * i386-tbl.h: Re-generate.
  19
  20 2021-03-24  Jan Beulich  <jbeulich@suse.com>
  21
  22         * i386-gen.c (process_i386_opcode_modifier): Return void. New
  23         parameter "prefix". Drop local variable "regular_encoding".
  24         Record prefix setting / check for consistency.
  25         (output_i386_opcode): Parse opcode_length and base_opcode
  26         earlier. Derive prefix encoding. Drop no longer applicable
  27         consistency checking. Adjust process_i386_opcode_modifier()
  28         invocation.
  29         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
  30         invocation.
  31         * i386-tbl.h: Re-generate.
  32
  33 2021-03-24  Jan Beulich  <jbeulich@suse.com>
  34
  35         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
  36         check.
  37         * i386-opc.h (Prefix_*): Move #define-s.
  38         * i386-opc.tbl: Move pseudo prefix enumerator values to
  39         extension opcode field. Introduce pseudopfx template.
  40         * i386-tbl.h: Re-generate.
  41
  42 2021-03-23  Jan Beulich  <jbeulich@suse.com>
  43
  44         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
  45         comment.
  46         * i386-tbl.h: Re-generate.
  47
  48 2021-03-23  Jan Beulich  <jbeulich@suse.com>
  49
  50         * i386-opc.h (struct insn_template): Move cpu_flags field past
  51         opcode_modifier one.
  52         * i386-tbl.h: Re-generate.
  53
  54 2021-03-23  Jan Beulich  <jbeulich@suse.com>
  55
  56         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
  57         * i386-opc.h (OpcodeSpace): New enumerator.
  58         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
  59         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
  60         SPACE_XOP09, SPACE_XOP0A): ... respectively.
  61         (struct i386_opcode_modifier): New field opcodespace. Shrink
  62         opcodeprefix field.
  63         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
  64         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
  65         OpcodePrefix uses.
  66         * i386-tbl.h: Re-generate.
  67
  68 2021-03-22  Martin Liska  <mliska@suse.cz>
  69
  70         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
  71         * arc-dis.c (parse_option): Likewise.
  72         * arm-dis.c (parse_arm_disassembler_options): Likewise.
  73         * cris-dis.c (print_with_operands): Likewise.
  74         * h8300-dis.c (bfd_h8_disassemble): Likewise.
  75         * i386-dis.c (print_insn): Likewise.
  76         * ia64-gen.c (fetch_insn_class): Likewise.
  77         (parse_resource_users): Likewise.
  78         (in_iclass): Likewise.
  79         (lookup_specifier): Likewise.
  80         (insert_opcode_dependencies): Likewise.
  81         * mips-dis.c (parse_mips_ase_option): Likewise.
  82         (parse_mips_dis_option): Likewise.
  83         * s390-dis.c (disassemble_init_s390): Likewise.
  84         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
  85
  86 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
  87
  88         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
  89
  90 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  91
  92         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
  93         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
  94
  95 2021-03-12  Alan Modra  <amodra@gmail.com>
  96
  97         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
  98
  99 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 100
 101         * i386-dis.c (OP_XMM): Re-order checks.
 102
 103 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 104
 105         * i386-dis.c (putop): Drop need_vex check when also checking
 106         vex.evex.
 107         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 108         checking vex.b.
 109
 110 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 111
 112         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 113         checks. Move case label past broadcast check.
 114
 115 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 116
 117         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 118         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 119         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 120         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 121         EVEX_W_0F38C7_M_0_L_2): Delete.
 122         (REG_EVEX_0F38C7_M_0_L_2): New.
 123         (intel_operand_size): Handle VEX and EVEX the same for
 124         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 125         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 126         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 127         vex_vsib_q_w_d_mode uses.
 128         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 129         0F38A1, and 0F38A3 entries.
 130         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 131         entry.
 132         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 133         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 134         0F38A3 entries.
 135
 136 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 137
 138         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 139         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 140         MOD_VEX_0FXOP_09_12): Rename to ...
 141         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 142         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 143         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 144         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 145         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 146         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 147         (reg_table): Adjust comments.
 148         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 149         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 150         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 151         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 152         (vex_len_table): Adjust opcode 0A_12 entry.
 153         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 154         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 155         (rm_table): Move hreset entry.
 156
 157 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 158
 159         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 160         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 161         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 162         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 163         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 164         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 165         (get_valid_dis386): Also handle 512-bit vector length when
 166         vectoring into vex_len_table[].
 167         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 168         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 169         entries.
 170         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 171         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 172         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 173         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 174         entries.
 175
 176 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 177
 178         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 179         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 180         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 181         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 182         entries.
 183         * i386-dis-evex-len.h (evex_len_table): Likewise.
 184         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 185
 186 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 187
 188         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 189         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 190         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 191         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 192         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 193         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 194         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 195         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 196         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 197         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 198         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 199         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 200         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 201         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 202         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 203         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 204         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 205         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 206         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 207         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 208         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 209         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 210         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 211         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 212         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 213         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 214         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 215         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 216         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 217         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 218         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 219         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 220         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 221         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 222         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 223         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 224         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 225         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 226         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 227         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 228         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 229         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 230         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 231         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 232         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 233         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 234         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 235         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 236         EVEX_W_0F3A43_L_n): New.
 237         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 238         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 239         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 240         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 241         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 242         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 243         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 244         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 245         0F385B, 0F38C6, and 0F38C7 entries.
 246         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 247         0F38C6 and 0F38C7.
 248         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 249         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 250         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 251         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 252
 253 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 254
 255         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 256         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 257         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 258         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 259         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 260         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 261         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 262         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 263         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 264         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 265         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 266         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 267         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 268         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 269         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 270         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 271         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 272         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 273         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 274         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 275         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 276         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 277         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 278         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 279         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 280         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 281         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 282         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 283         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 284         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 285         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 286         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 287         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 288         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 289         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 290         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 291         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 292         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 293         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 294         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 295         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 296         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 297         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 298         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 299         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 300         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 301         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 302         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 303         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 304         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 305         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 306         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 307         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 308         VEX_W_0F99_P_2_LEN_0): Delete.
 309         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 310         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 311         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 312         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 313         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 314         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 315         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 316         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 317         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 318         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 319         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 320         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 321         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 322         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 323         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 324         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 325         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 326         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 327         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 328         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 329         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 330         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 331         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 332         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 333         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 334         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 335         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 336         (prefix_table): No longer link to vex_len_table[] for opcodes
 337         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 338         0F92, 0F93, 0F98, and 0F99.
 339         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 340         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 341         0F98, and 0F99.
 342         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 343         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 344         0F98, and 0F99.
 345         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 346         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 347         0F98, and 0F99.
 348         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 349         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 350         0F98, and 0F99.
 351
 352 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 353
 354         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 355         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 356         REG_VEX_0F73_M_0 respectively.
 357         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 358         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 359         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 360         MOD_VEX_0F73_REG_7): Delete.
 361         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 362         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 363         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 364         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 365         PREFIX_VEX_0F3AF0_L_0 respectively.
 366         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 367         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 368         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 369         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 370         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 371         VEX_LEN_0F38F7): New.
 372         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 373         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 374         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 375         0F38F3.
 376         (prefix_table): No longer link to vex_len_table[] for opcodes
 377         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 378         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 379         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 380         0F38F6, 0F38F7, and 0F3AF0.
 381         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 382         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 383         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 384         0F73.
 385
 386 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 387
 388         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 389         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 390         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 391         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 392         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 393         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 394         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 395         73.
 396         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 397         0F72, and 0F73.
 398         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 399         0F73.
 400
 401 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 402
 403         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 404         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 405         (reg_table): Don't link to mod_table[] where not needed. Add
 406         PREFIX_IGNORED to nop entries.
 407         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 408         (mod_table): Add nop entries next to prefetch ones. Drop
 409         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 410         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 411         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 412         PREFIX_OPCODE from endbr* entries.
 413         (get_valid_dis386): Also consider entry's name when zapping
 414         vindex.
 415         (print_insn): Handle PREFIX_IGNORED.
 416
 417 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 418
 419         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 420         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 421         element.
 422         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 423         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 424         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 425         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 426         (struct i386_opcode_modifier): Delete notrackprefixok,
 427         islockable, hleprefixok, and repprefixok fields. Add prefixok
 428         field.
 429         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 430         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 431         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 432         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 433         Replace HLEPrefixOk.
 434         * opcodes/i386-tbl.h: Re-generate.
 435
 436 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 437
 438         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 439         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 440         64-bit form.
 441         * opcodes/i386-tbl.h: Re-generate.
 442
 443 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 444
 445         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 446         for {} instead of {0}. Don't look for '0'.
 447         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 448         size specifiers.
 449
 450 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 451
 452         PR 27158
 453         * riscv-dis.c (print_insn_args): Updated encoding macros.
 454         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 455         (match_c_addi16sp): Updated encoding macros.
 456         (match_c_lui): Likewise.
 457         (match_c_lui_with_hint): Likewise.
 458         (match_c_addi4spn): Likewise.
 459         (match_c_slli): Likewise.
 460         (match_slli_as_c_slli): Likewise.
 461         (match_c_slli64): Likewise.
 462         (match_srxi_as_c_srxi): Likewise.
 463         (riscv_insn_types): Added .insn css/cl/cs.
 464
 465 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 466
 467         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 468         (default_priv_spec): Updated type to riscv_spec_class.
 469         (parse_riscv_dis_option): Updated.
 470         * riscv-opc.c: Moved stuff and make the file tidy.
 471
 472 2021-02-17  Alan Modra  <amodra@gmail.com>
 473
 474         * wasm32-dis.c: Include limits.h.
 475         (CHAR_BIT): Provide backup define.
 476         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 477         Correct signed overflow checking.
 478
 479 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 480
 481         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 482         * i386-tbl.h: Re-generate.
 483
 484 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 485
 486         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 487         Oword.
 488         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 489
 490 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 491
 492         * s390-mkopc.c (main): Accept arch14 as cpu string.
 493         * s390-opc.txt: Add new arch14 instructions.
 494
 495 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 496
 497         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 498         favour of LIBINTL.
 499         * configure: Regenerated.
 500
 501 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 502
 503         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 504         * tic54x-opc.c (regs): Rename to ...
 505         (tic54x_regs): ... this.
 506         (mmregs): Rename to ...
 507         (tic54x_mmregs): ... this.
 508         (condition_codes): Rename to ...
 509         (tic54x_condition_codes): ... this.
 510         (cc2_codes): Rename to ...
 511         (tic54x_cc2_codes): ... this.
 512         (cc3_codes): Rename to ...
 513         (tic54x_cc3_codes): ... this.
 514         (status_bits): Rename to ...
 515         (tic54x_status_bits): ... this.
 516         (misc_symbols): Rename to ...
 517         (tic54x_misc_symbols): ... this.
 518
 519 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 520
 521         * riscv-opc.c (MASK_RVB_IMM): Removed.
 522         (riscv_opcodes): Removed zb* instructions.
 523         (riscv_ext_version_table): Removed versions for zb*.
 524
 525 2021-01-26  Alan Modra  <amodra@gmail.com>
 526
 527         * i386-gen.c (parse_template): Ensure entire template_instance
 528         is initialised.
 529
 530 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 531
 532         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 533         (riscv_fpr_names_abi): Likewise.
 534         (riscv_opcodes): Likewise.
 535         (riscv_insn_types): Likewise.
 536
 537 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 538
 539         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 540
 541 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 542
 543         * riscv-dis.c: Comments tidy and improvement.
 544         * riscv-opc.c: Likewise.
 545
 546 2021-01-13  Alan Modra  <amodra@gmail.com>
 547
 548         * Makefile.in: Regenerate.
 549
 550 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 551
 552         PR binutils/26792
 553         * configure.ac: Use GNU_MAKE_JOBSERVER.
 554         * aclocal.m4: Regenerated.
 555         * configure: Likewise.
 556
 557 2021-01-12  Nick Clifton  <nickc@redhat.com>
 558
 559         * po/sr.po: Updated Serbian translation.
 560
 561 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 562
 563         PR ld/27173
 564         * configure: Regenerated.
 565
 566 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 567
 568         * aarch64-asm-2.c: Regenerate.
 569         * aarch64-dis-2.c: Likewise.
 570         * aarch64-opc-2.c: Likewise.
 571         * aarch64-opc.c (aarch64_print_operand):
 572         Delete handling of AARCH64_OPND_CSRE_CSR.
 573         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 574         (CSRE): Likewise.
 575         (_CSRE_INSN): Likewise.
 576         (aarch64_opcode_table): Delete csr.
 577
 578 2021-01-11  Nick Clifton  <nickc@redhat.com>
 579
 580         * po/de.po: Updated German translation.
 581         * po/fr.po: Updated French translation.
 582         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 583         * po/sv.po: Updated Swedish translation.
 584         * po/uk.po: Updated Ukranian translation.
 585
 586 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 587
 588         * configure: Regenerated.
 589
 590 2021-01-09  Nick Clifton  <nickc@redhat.com>
 591
 592         * configure: Regenerate.
 593         * po/opcodes.pot: Regenerate.
 594
 595 2021-01-09  Nick Clifton  <nickc@redhat.com>
 596
 597         * 2.36 release branch crated.
 598
 599 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 600
 601         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 602         (DW, (XRC_MASK): Define.
 603         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 604
 605 2021-01-09  Alan Modra  <amodra@gmail.com>
 606
 607         * configure: Regenerate.
 608
 609 2021-01-08  Nick Clifton  <nickc@redhat.com>
 610
 611         * po/sv.po: Updated Swedish translation.
 612
 613 2021-01-08  Nick Clifton  <nickc@redhat.com>
 614
 615         PR 27129
 616         * aarch64-dis.c (determine_disassembling_preference): Move call to
 617         aarch64_match_operands_constraint outside of the assertion.
 618         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 619         Replace with a return of FALSE.
 620
 621         PR 27139
 622         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 623         core system register.
 624
 625 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 626
 627         * configure: Regenerate.
 628
 629 2021-01-07  Nick Clifton  <nickc@redhat.com>
 630
 631         * po/fr.po: Updated French translation.
 632
 633 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 634
 635         * m68k-opc.c (chkl): Change minimum architecture requirement to
 636         m68020.
 637
 638 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 639
 640         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 641
 642 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 643             Jim Wilson  <jimw@sifive.com>
 644             Andrew Waterman  <andrew@sifive.com>
 645             Maxim Blinov  <maxim.blinov@embecosm.com>
 646             Kito Cheng  <kito.cheng@sifive.com>
 647             Nelson Chu  <nelson.chu@sifive.com>
 648
 649         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
 650         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 651
 652 2021-01-01  Alan Modra  <amodra@gmail.com>
 653
 654         Update year range in copyright notice of all files.
 655
 656 For older changes see ChangeLog-2020
 657 \f
 658 Copyright (C) 2021 Free Software Foundation, Inc.
 659
 660 Copying and distribution of this file, with or without modification,
 661 are permitted in any medium without royalty provided the copyright
 662 notice and this notice are preserved.
 663
 664 Local Variables:
 665 mode: change-log
 666 left-margin: 8
 667 fill-column: 74
 668 version-control: never
 669 End: