opcodes/ChangeLog

   1 2017-09-21  Sergio Durigan Junior  <sergiodj@redhat.com>
   2
   3         * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
   4
   5 2017-09-09  Kamil Rytarowski  <n54@gmx.com>
   6
   7         * nds32-asm.c: Rename __BIT() to N32_BIT().
   8         * nds32-asm.h: Likewise.
   9         * nds32-dis.c: Likewise.
  10
  11 2017-09-09  H.J. Lu  <hongjiu.lu@intel.com>
  12
  13         * i386-dis.c (last_active_prefix): Removed.
  14         (ckprefix): Don't set last_active_prefix.
  15         (NOTRACK_Fixup): Don't check last_active_prefix.
  16
  17 2017-08-31  Nick Clifton  <nickc@redhat.com>
  18
  19         * po/fr.po: Updated French translation.
  20
  21 2017-08-31  James Bowman  <james.bowman@ftdichip.com>
  22
  23         * ft32-dis.c (print_insn_ft32): Correct display of non-address
  24         fields.
  25
  26 2017-08-23  Alexander Fedotov <alexander.fedotov@nxp.com>
  27             Edmar Wienskoski <edmar.wienskoski@nxp.com>
  28
  29         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
  30         PPC_OPCODE_EFS2 flag to "e200z4" entry.
  31         New entries efs2 and spe2.
  32         Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
  33         (SPE2_OPCD_SEGS): New macro.
  34         (spe2_opcd_indices): New.
  35         (disassemble_init_powerpc): Handle SPE2 opcodes.
  36         (lookup_spe2): New function.
  37         (print_insn_powerpc): call lookup_spe2.
  38         * ppc-opc.c (insert_evuimm1_ex0): New function.
  39         (extract_evuimm1_ex0): Likewise.
  40         (insert_evuimm_lt8): Likewise.
  41         (extract_evuimm_lt8): Likewise.
  42         (insert_off_spe2): Likewise.
  43         (extract_off_spe2): Likewise.
  44         (insert_Ddd): Likewise.
  45         (extract_Ddd): Likewise.
  46         (DD): New operand.
  47         (EVUIMM_LT8): Likewise.
  48         (EVUIMM_LT16): Adjust.
  49         (MMMM): New operand.
  50         (EVUIMM_1): Likewise.
  51         (EVUIMM_1_EX0): Likewise.
  52         (EVUIMM_2): Adjust.
  53         (NNN): New operand.
  54         (VX_OFF_SPE2): Likewise.
  55         (BBB): Likewise.
  56         (DDD): Likewise.
  57         (VX_MASK_DDD): New mask.
  58         (HH): New operand.
  59         (VX_RA_CONST): New macro.
  60         (VX_RA_CONST_MASK): Likewise.
  61         (VX_RB_CONST): Likewise.
  62         (VX_RB_CONST_MASK): Likewise.
  63         (VX_OFF_SPE2_MASK): Likewise.
  64         (VX_SPE_CRFD): Likewise.
  65         (VX_SPE_CRFD_MASK VX): Likewise.
  66         (VX_SPE2_CLR): Likewise.
  67         (VX_SPE2_CLR_MASK): Likewise.
  68         (VX_SPE2_SPLATB): Likewise.
  69         (VX_SPE2_SPLATB_MASK): Likewise.
  70         (VX_SPE2_OCTET): Likewise.
  71         (VX_SPE2_OCTET_MASK): Likewise.
  72         (VX_SPE2_DDHH): Likewise.
  73         (VX_SPE2_DDHH_MASK): Likewise.
  74         (VX_SPE2_HH): Likewise.
  75         (VX_SPE2_HH_MASK): Likewise.
  76         (VX_SPE2_EVMAR): Likewise.
  77         (VX_SPE2_EVMAR_MASK): Likewise.
  78         (PPCSPE2): Likewise.
  79         (PPCEFS2): Likewise.
  80         (vle_opcodes): Add EFS2 and some missing SPE opcodes.
  81         (powerpc_macros): Map old SPE instructions have new names
  82         with the same opcodes. Add SPE2 instructions which just are
  83         mapped to SPE2.
  84         (spe2_opcodes): Add SPE2 opcodes.
  85
  86 2017-08-23  Alan Modra  <amodra@gmail.com>
  87
  88         * ppc-opc.c: Formatting and comment fixes.  Move insert and
  89         extract functions earlier, deleting forward declarations.
  90         (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
  91         RA_MASK.
  92
  93 2017-08-22  Palmer Dabbelt  <palmer@dabbelt.com>
  94
  95         * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
  96
  97 2017-08-21  Alexander Fedotov <alexander.fedotov@nxp.com>
  98             Edmar Wienskoski <edmar.wienskoski@nxp.com>
  99
 100         * ppc-opc.c (insert_evuimm2_ex0): New function.
 101         (extract_evuimm2_ex0): Likewise.
 102         (insert_evuimm4_ex0): Likewise.
 103         (extract_evuimm4_ex0): Likewise.
 104         (insert_evuimm8_ex0): Likewise.
 105         (extract_evuimm8_ex0): Likewise.
 106         (insert_evuimm_lt16): Likewise.
 107         (extract_evuimm_lt16): Likewise.
 108         (insert_rD_rS_even): Likewise.
 109         (extract_rD_rS_even): Likewise.
 110         (insert_off_lsp): Likewise.
 111         (extract_off_lsp): Likewise.
 112         (RD_EVEN): New operand.
 113         (RS_EVEN): Likewise.
 114         (RSQ): Adjust.
 115         (EVUIMM_LT16): New operand.
 116         (HTM_SI): Adjust.
 117         (EVUIMM_2_EX0): New operand.
 118         (EVUIMM_4): Adjust.
 119         (EVUIMM_4_EX0): New operand.
 120         (EVUIMM_8): Adjust.
 121         (EVUIMM_8_EX0): New operand.
 122         (WS): Adjust.
 123         (VX_OFF): New operand.
 124         (VX_LSP): New macro.
 125         (VX_LSP_MASK): Likewise.
 126         (VX_LSP_OFF_MASK): Likewise.
 127         (PPC_OPCODE_LSP): Likewise.
 128         (vle_opcodes): Add LSP opcodes.
 129         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
 130
 131 2017-08-09  Jiong Wang  <jiong.wang@arm.com>
 132
 133         * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
 134         register operands in CRC instructions.
 135         (print_insn_thumb32): Remove "<bitfield>S" support.  Updated the
 136         comments.
 137
 138 2017-08-07  H.J. Lu  <hongjiu.lu@intel.com>
 139
 140         * disassemble.c (disassembler): Mark big and mach with
 141         ATTRIBUTE_UNUSED.
 142
 143 2017-08-07  Maciej W. Rozycki  <macro@imgtec.com>
 144
 145         * disassemble.c (disassembler): Remove arch/mach/endian
 146         assertions.
 147
 148 2017-07-25  Nick Clifton  <nickc@redhat.com>
 149
 150         PR 21739
 151         * arc-opc.c (insert_rhv2): Use lower case first letter in error
 152         message.
 153         (insert_r0): Likewise.
 154         (insert_r1): Likewise.
 155         (insert_r2): Likewise.
 156         (insert_r3): Likewise.
 157         (insert_sp): Likewise.
 158         (insert_gp): Likewise.
 159         (insert_pcl): Likewise.
 160         (insert_blink): Likewise.
 161         (insert_ilink1): Likewise.
 162         (insert_ilink2): Likewise.
 163         (insert_ras): Likewise.
 164         (insert_rbs): Likewise.
 165         (insert_rcs): Likewise.
 166         (insert_simm3s): Likewise.
 167         (insert_rrange): Likewise.
 168         (insert_r13el): Likewise.
 169         (insert_fpel): Likewise.
 170         (insert_blinkel): Likewise.
 171         (insert_pclel): Likewise.
 172         (insert_nps_bitop_size_2b): Likewise.
 173         (insert_nps_imm_offset): Likewise.
 174         (insert_nps_imm_entry): Likewise.
 175         (insert_nps_size_16bit): Likewise.
 176         (insert_nps_##NAME##_pos): Likewise.
 177         (insert_nps_##NAME): Likewise.
 178         (insert_nps_bitop_ins_ext): Likewise.
 179         (insert_nps_##NAME): Likewise.
 180         (insert_nps_min_hofs): Likewise.
 181         (insert_nps_##NAME): Likewise.
 182         (insert_nps_rbdouble_64): Likewise.
 183         (insert_nps_misc_imm_offset): Likewise.
 184         * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
 185         option description.
 186
 187 2017-07-24  Laurent Desnogues  <laurent.desnogues@arm.com>
 188             Jiong Wang  <jiong.wang@arm.com>
 189
 190         * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
 191         correct the print.
 192         * aarch64-dis-2.c: Regenerated.
 193
 194 2017-07-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 195
 196         * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
 197         table.
 198
 199 2017-07-20  Nick Clifton  <nickc@redhat.com>
 200
 201         * po/de.po: Updated German translation.
 202
 203 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 204
 205         * arc-regs.h (sec_stat): New aux register.
 206         (aux_kernel_sp): Likewise.
 207         (aux_sec_u_sp): Likewise.
 208         (aux_sec_k_sp): Likewise.
 209         (sec_vecbase_build): Likewise.
 210         (nsc_table_top): Likewise.
 211         (nsc_table_base): Likewise.
 212         (ersec_stat): Likewise.
 213         (aux_sec_except): Likewise.
 214
 215 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 216
 217         * arc-opc.c (extract_uimm12_20): New function.
 218         (UIMM12_20): New operand.
 219         (SIMM3_5_S): Adjust.
 220         * arc-tbl.h (sjli): Add new instruction.
 221
 222 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 223             John Eric Martin  <John.Martin@emmicro-us.com>
 224
 225         * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
 226         (UIMM3_23): Adjust accordingly.
 227         * arc-regs.h: Add/correct jli_base register.
 228         * arc-tbl.h (jli_s): Likewise.
 229
 230 2017-07-18  Nick Clifton  <nickc@redhat.com>
 231
 232         PR 21775
 233         * aarch64-opc.c: Fix spelling typos.
 234         * i386-dis.c: Likewise.
 235
 236 2017-07-14  Ravi Bangoria  <ravi.bangoria@linux.vnet.ibm.com>
 237
 238         * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
 239         max_addr_offset and octets variables to size_t.
 240
 241 2017-07-12  Alan Modra  <amodra@gmail.com>
 242
 243         * po/da.po: Update from translationproject.org/latest/opcodes/.
 244         * po/de.po: Likewise.
 245         * po/es.po: Likewise.
 246         * po/fi.po: Likewise.
 247         * po/fr.po: Likewise.
 248         * po/id.po: Likewise.
 249         * po/it.po: Likewise.
 250         * po/nl.po: Likewise.
 251         * po/pt_BR.po: Likewise.
 252         * po/ro.po: Likewise.
 253         * po/sv.po: Likewise.
 254         * po/tr.po: Likewise.
 255         * po/uk.po: Likewise.
 256         * po/vi.po: Likewise.
 257         * po/zh_CN.po: Likewise.
 258
 259 2017-07-11  Yao Qi  <yao.qi@linaro.org>
 260             Alan Modra  <amodra@gmail.com>
 261
 262         * cgen.sh: Mark generated files read-only.
 263         * epiphany-asm.c: Regenerate.
 264         * epiphany-desc.c: Regenerate.
 265         * epiphany-desc.h: Regenerate.
 266         * epiphany-dis.c: Regenerate.
 267         * epiphany-ibld.c: Regenerate.
 268         * epiphany-opc.c: Regenerate.
 269         * epiphany-opc.h: Regenerate.
 270         * fr30-asm.c: Regenerate.
 271         * fr30-desc.c: Regenerate.
 272         * fr30-desc.h: Regenerate.
 273         * fr30-dis.c: Regenerate.
 274         * fr30-ibld.c: Regenerate.
 275         * fr30-opc.c: Regenerate.
 276         * fr30-opc.h: Regenerate.
 277         * frv-asm.c: Regenerate.
 278         * frv-desc.c: Regenerate.
 279         * frv-desc.h: Regenerate.
 280         * frv-dis.c: Regenerate.
 281         * frv-ibld.c: Regenerate.
 282         * frv-opc.c: Regenerate.
 283         * frv-opc.h: Regenerate.
 284         * ip2k-asm.c: Regenerate.
 285         * ip2k-desc.c: Regenerate.
 286         * ip2k-desc.h: Regenerate.
 287         * ip2k-dis.c: Regenerate.
 288         * ip2k-ibld.c: Regenerate.
 289         * ip2k-opc.c: Regenerate.
 290         * ip2k-opc.h: Regenerate.
 291         * iq2000-asm.c: Regenerate.
 292         * iq2000-desc.c: Regenerate.
 293         * iq2000-desc.h: Regenerate.
 294         * iq2000-dis.c: Regenerate.
 295         * iq2000-ibld.c: Regenerate.
 296         * iq2000-opc.c: Regenerate.
 297         * iq2000-opc.h: Regenerate.
 298         * lm32-asm.c: Regenerate.
 299         * lm32-desc.c: Regenerate.
 300         * lm32-desc.h: Regenerate.
 301         * lm32-dis.c: Regenerate.
 302         * lm32-ibld.c: Regenerate.
 303         * lm32-opc.c: Regenerate.
 304         * lm32-opc.h: Regenerate.
 305         * lm32-opinst.c: Regenerate.
 306         * m32c-asm.c: Regenerate.
 307         * m32c-desc.c: Regenerate.
 308         * m32c-desc.h: Regenerate.
 309         * m32c-dis.c: Regenerate.
 310         * m32c-ibld.c: Regenerate.
 311         * m32c-opc.c: Regenerate.
 312         * m32c-opc.h: Regenerate.
 313         * m32r-asm.c: Regenerate.
 314         * m32r-desc.c: Regenerate.
 315         * m32r-desc.h: Regenerate.
 316         * m32r-dis.c: Regenerate.
 317         * m32r-ibld.c: Regenerate.
 318         * m32r-opc.c: Regenerate.
 319         * m32r-opc.h: Regenerate.
 320         * m32r-opinst.c: Regenerate.
 321         * mep-asm.c: Regenerate.
 322         * mep-desc.c: Regenerate.
 323         * mep-desc.h: Regenerate.
 324         * mep-dis.c: Regenerate.
 325         * mep-ibld.c: Regenerate.
 326         * mep-opc.c: Regenerate.
 327         * mep-opc.h: Regenerate.
 328         * mt-asm.c: Regenerate.
 329         * mt-desc.c: Regenerate.
 330         * mt-desc.h: Regenerate.
 331         * mt-dis.c: Regenerate.
 332         * mt-ibld.c: Regenerate.
 333         * mt-opc.c: Regenerate.
 334         * mt-opc.h: Regenerate.
 335         * or1k-asm.c: Regenerate.
 336         * or1k-desc.c: Regenerate.
 337         * or1k-desc.h: Regenerate.
 338         * or1k-dis.c: Regenerate.
 339         * or1k-ibld.c: Regenerate.
 340         * or1k-opc.c: Regenerate.
 341         * or1k-opc.h: Regenerate.
 342         * or1k-opinst.c: Regenerate.
 343         * xc16x-asm.c: Regenerate.
 344         * xc16x-desc.c: Regenerate.
 345         * xc16x-desc.h: Regenerate.
 346         * xc16x-dis.c: Regenerate.
 347         * xc16x-ibld.c: Regenerate.
 348         * xc16x-opc.c: Regenerate.
 349         * xc16x-opc.h: Regenerate.
 350         * xstormy16-asm.c: Regenerate.
 351         * xstormy16-desc.c: Regenerate.
 352         * xstormy16-desc.h: Regenerate.
 353         * xstormy16-dis.c: Regenerate.
 354         * xstormy16-ibld.c: Regenerate.
 355         * xstormy16-opc.c: Regenerate.
 356         * xstormy16-opc.h: Regenerate.
 357
 358 2017-07-07  Alan Modra  <amodra@gmail.com>
 359
 360         * cgen-dis.in: Include disassemble.h, not dis-asm.h.
 361         * m32c-dis.c: Regenerate.
 362         * mep-dis.c: Regenerate.
 363
 364 2017-07-05  Borislav Petkov  <bp@suse.de>
 365
 366         * i386-dis.c: Enable ModRM.reg /6 aliases.
 367
 368 2017-07-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 369
 370         * opcodes/arm-dis.c: Support MVFR2 in disassembly
 371         with vmrs and vmsr.
 372
 373 2017-07-04  Tristan Gingold  <gingold@adacore.com>
 374
 375         * configure: Regenerate.
 376
 377 2017-07-03  Tristan Gingold  <gingold@adacore.com>
 378
 379         * po/opcodes.pot: Regenerate.
 380
 381 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 382
 383         * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
 384         entries to the MSA ASE instruction block.
 385
 386 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 387             Maciej W. Rozycki  <macro@imgtec.com>
 388
 389         * micromips-opc.c (XPA, XPAVZ): New macros.
 390         (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
 391         "mthgc0".
 392
 393 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 394             Maciej W. Rozycki  <macro@imgtec.com>
 395
 396         * micromips-opc.c (I36): New macro.
 397         (micromips_opcodes): Add "eretnc".
 398
 399 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 400             Andrew Bennett  <andrew.bennett@imgtec.com>
 401
 402         * mips-dis.c (mips_calculate_combination_ases): Handle the
 403         ASE_XPA_VIRT flag.
 404         (parse_mips_ase_option): New function.
 405         (parse_mips_dis_option): Factor out ASE option handling to the
 406         new function.  Call `mips_calculate_combination_ases'.
 407         * mips-opc.c (XPAVZ): New macro.
 408         (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
 409         "mfhgc0", "mthc0" and "mthgc0".
 410
 411 2017-06-29  Maciej W. Rozycki  <macro@imgtec.com>
 412
 413         * mips-dis.c (mips_calculate_combination_ases): New function.
 414         (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
 415         calculation to the new function.
 416         (set_default_mips_dis_options): Call the new function.
 417
 418 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 419
 420         * arc-dis.c (parse_disassembler_options): Use
 421         FOR_EACH_DISASSEMBLER_OPTION.
 422
 423 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 424
 425         * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
 426         disassembler option strings.
 427         (parse_cpu_option): Likewise.
 428
 429 2017-06-28  Tamar Christina  <tamar.christina@arm.com>
 430
 431         * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
 432         * aarch64-dis.c (aarch64_ext_reglane): Likewise.
 433         * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
 434         (aarch64_feature_dotprod, DOT_INSN): New.
 435         (udot, sdot): New.
 436         * aarch64-dis-2.c: Regenerated.
 437
 438 2017-06-28  Jiong Wang  <jiong.wang@arm.com>
 439
 440         * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
 441
 442 2017-06-28  Maciej W. Rozycki  <macro@imgtec.com>
 443             Matthew Fortune  <matthew.fortune@imgtec.com>
 444             Andrew Bennett  <andrew.bennett@imgtec.com>
 445
 446         * mips-formats.h (INT_BIAS): New macro.
 447         (INT_ADJ): Redefine in INT_BIAS terms.
 448         * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
 449         (mips_print_save_restore): New function.
 450         (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
 451         (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
 452         call.
 453         (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
 454         (print_mips16_insn_arg): Call `mips_print_save_restore' for
 455         OP_SAVE_RESTORE_LIST handling, factored out from here.
 456         * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
 457         (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
 458         (mips_builtin_opcodes): Add "restore" and "save" entries.
 459         * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
 460         (IAMR2): New macro.
 461         (mips16_opcodes): Add "copyw" and "ucopyw" entries.
 462
 463 2017-06-23  Andrew Waterman  <andrew@sifive.com>
 464
 465         * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
 466         alias; do not mark SLTI instruction as an alias.
 467
 468 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 469
 470         * i386-dis.c (RM_0FAE_REG_5): Removed.
 471         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 472         (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
 473         (PREFIX_MOD_3_0FAE_REG_5): Likewise.
 474         (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1.  Add
 475         PREFIX_MOD_3_0F01_REG_5_RM_0.
 476         (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5.  Add
 477         PREFIX_MOD_3_0FAE_REG_5.
 478         (mod_table): Update MOD_0FAE_REG_5.
 479         (rm_table): Update RM_0F01_REG_5.  Remove RM_0FAE_REG_5.
 480         * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
 481         * i386-tbl.h: Regenerated.
 482
 483 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 484
 485         * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
 486         * i386-opc.tbl: Likewise.
 487         * i386-tbl.h: Regenerated.
 488
 489 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 490
 491         * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
 492         and "jmp{&|}".
 493         (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
 494         prefix.
 495
 496 2017-06-19  Nick Clifton  <nickc@redhat.com>
 497
 498         PR binutils/21614
 499         * score-dis.c (score_opcodes): Add sentinel.
 500
 501 2017-06-16  Alan Modra  <amodra@gmail.com>
 502
 503         * rx-decode.c: Regenerate.
 504
 505 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
 506
 507         PR binutils/21594
 508         * i386-dis.c (OP_E_register): Check valid bnd register.
 509         (OP_G): Likewise.
 510
 511 2017-06-15  Nick Clifton  <nickc@redhat.com>
 512
 513         PR binutils/21595
 514         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
 515         range value.
 516
 517 2017-06-15  Nick Clifton  <nickc@redhat.com>
 518
 519         PR binutils/21588
 520         * rl78-decode.opc (OP_BUF_LEN): Define.
 521         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
 522         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
 523         array.
 524         * rl78-decode.c: Regenerate.
 525
 526 2017-06-15  Nick Clifton  <nickc@redhat.com>
 527
 528         PR binutils/21586
 529         * bfin-dis.c (gregs): Clip index to prevent overflow.
 530         (regs): Likewise.
 531         (regs_lo): Likewise.
 532         (regs_hi): Likewise.
 533
 534 2017-06-14  Nick Clifton  <nickc@redhat.com>
 535
 536         PR binutils/21576
 537         * score7-dis.c (score_opcodes): Add sentinel.
 538
 539 2017-06-14  Yao Qi  <yao.qi@linaro.org>
 540
 541         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
 542         * arm-dis.c: Likewise.
 543         * ia64-dis.c: Likewise.
 544         * mips-dis.c: Likewise.
 545         * spu-dis.c: Likewise.
 546         * disassemble.h (print_insn_aarch64): New declaration, moved from
 547         include/dis-asm.h.
 548         (print_insn_big_arm, print_insn_big_mips): Likewise.
 549         (print_insn_i386, print_insn_ia64): Likewise.
 550         (print_insn_little_arm, print_insn_little_mips): Likewise.
 551
 552 2017-06-14  Nick Clifton  <nickc@redhat.com>
 553
 554         PR binutils/21587
 555         * rx-decode.opc: Include libiberty.h
 556         (GET_SCALE): New macro - validates access to SCALE array.
 557         (GET_PSCALE): New macro - validates access to PSCALE array.
 558         (DIs, SIs, S2Is, rx_disp): Use new macros.
 559         * rx-decode.c: Regenerate.
 560
 561 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 562
 563         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
 564
 565 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
 566
 567         * arc-dis.c (enforced_isa_mask): Declare.
 568         (cpu_types): Likewise.
 569         (parse_cpu_option): New function.
 570         (parse_disassembler_options): Use it.
 571         (print_insn_arc): Use enforced_isa_mask.
 572         (print_arc_disassembler_options): Document new options.
 573
 574 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 575
 576         * alpha-dis.c: Include disassemble.h, don't include
 577         dis-asm.h.
 578         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
 579         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
 580         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
 581         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
 582         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
 583         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
 584         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
 585         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
 586         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
 587         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
 588         * moxie-dis.c, msp430-dis.c, mt-dis.c:
 589         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
 590         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
 591         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
 592         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
 593         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
 594         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
 595         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
 596         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
 597         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
 598         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
 599         * z80-dis.c, z8k-dis.c: Likewise.
 600         * disassemble.h: New file.
 601
 602 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 603
 604         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
 605         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
 606
 607 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 608
 609         * disassemble.c (disassembler): Add arguments a, big and mach.
 610         Use them.
 611
 612 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
 613
 614         * i386-dis.c (NOTRACK_Fixup): New.
 615         (NOTRACK): Likewise.
 616         (NOTRACK_PREFIX): Likewise.
 617         (last_active_prefix): Likewise.
 618         (reg_table): Use NOTRACK on indirect call and jmp.
 619         (ckprefix): Set last_active_prefix.
 620         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
 621         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
 622         * i386-opc.h (NoTrackPrefixOk): New.
 623         (i386_opcode_modifier): Add notrackprefixok.
 624         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
 625         Add notrack.
 626         * i386-tbl.h: Regenerated.
 627
 628 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 629
 630         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
 631         (X_IMM2): Define.
 632         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
 633         bfd_mach_sparc_v9m8.
 634         (print_insn_sparc): Handle new operand types.
 635         * sparc-opc.c (MASK_M8): Define.
 636         (v6): Add MASK_M8.
 637         (v6notlet): Likewise.
 638         (v7): Likewise.
 639         (v8): Likewise.
 640         (v9): Likewise.
 641         (v9a): Likewise.
 642         (v9b): Likewise.
 643         (v9c): Likewise.
 644         (v9d): Likewise.
 645         (v9e): Likewise.
 646         (v9v): Likewise.
 647         (v9m): Likewise.
 648         (v9andleon): Likewise.
 649         (m8): Define.
 650         (HWS_VM8): Define.
 651         (HWS2_VM8): Likewise.
 652         (sparc_opcode_archs): Add entry for "m8".
 653         (sparc_opcodes): Add OSA2017 and M8 instructions
 654         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
 655         fpx{ll,ra,rl}64x,
 656         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
 657         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
 658         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
 659         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
 660         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
 661         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
 662         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
 663         ASI_CORE_SELECT_COMMIT_NHT.
 664
 665 2017-05-18  Alan Modra  <amodra@gmail.com>
 666
 667         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
 668         * aarch64-dis.c: Likewise.
 669         * aarch64-gen.c: Likewise.
 670         * aarch64-opc.c: Likewise.
 671
 672 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 673             Matthew Fortune  <matthew.fortune@imgtec.com>
 674
 675         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
 676         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
 677         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
 678         (print_insn_arg) <OP_REG28>: Add handler.
 679         (validate_insn_args) <OP_REG28>: Handle.
 680         (print_mips16_insn_arg): Handle MIPS16 instructions that require
 681         32-bit encoding and 9-bit immediates.
 682         (print_insn_mips16): Handle MIPS16 instructions that require
 683         32-bit encoding and MFC0/MTC0 operand decoding.
 684         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
 685         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
 686         (RD_C0, WR_C0, E2, E2MT): New macros.
 687         (mips16_opcodes): Add entries for MIPS16e2 instructions:
 688         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
 689         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
 690         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
 691         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
 692         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
 693         instructions, "swl", "swr", "sync" and its "sync_acquire",
 694         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
 695         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
 696         regular/extended entries for original MIPS16 ISA revision
 697         instructions whose extended forms are subdecoded in the MIPS16e2
 698         ISA revision: "li", "sll" and "srl".
 699
 700 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 701
 702         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
 703         reference in CP0 move operand decoding.
 704
 705 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
 706
 707         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
 708         type to hexadecimal.
 709         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
 710
 711 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
 712
 713         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
 714         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
 715         "sync_rmb" and "sync_wmb" as aliases.
 716         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
 717         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
 718
 719 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
 720
 721         * arc-dis.c (parse_option): Update quarkse_em option..
 722         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
 723         QUARKSE1.
 724         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
 725
 726 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
 727
 728         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
 729
 730 2017-05-01  Michael Clark  <michaeljclark@mac.com>
 731
 732         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
 733         register.
 734
 735 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
 736
 737         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
 738         and branches and not synthetic data instructions.
 739
 740 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
 741
 742         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
 743
 744 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 745
 746         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
 747         * arc-opc.c (insert_r13el): New function.
 748         (R13_EL): Define.
 749         * arc-tbl.h: Add new enter/leave variants.
 750
 751 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 752
 753         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
 754
 755 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 756
 757         * mips-dis.c (print_mips_disassembler_options): Add
 758         `no-aliases'.
 759
 760 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 761
 762         * mips16-opc.c (AL): New macro.
 763         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
 764         of "ld" and "lw" as aliases.
 765
 766 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
 767
 768         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
 769         arguments.
 770
 771 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
 772             Alan Modra  <amodra@gmail.com>
 773
 774         * ppc-opc.c (ELEV): Define.
 775         (vle_opcodes): Add se_rfgi and e_sc.
 776         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
 777         for E200Z4.
 778
 779 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
 780
 781         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
 782
 783 2017-04-21  Nick Clifton  <nickc@redhat.com>
 784
 785         PR binutils/21380
 786         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
 787         LD3R and LD4R.
 788
 789 2017-04-13  Alan Modra  <amodra@gmail.com>
 790
 791         * epiphany-desc.c: Regenerate.
 792         * fr30-desc.c: Regenerate.
 793         * frv-desc.c: Regenerate.
 794         * ip2k-desc.c: Regenerate.
 795         * iq2000-desc.c: Regenerate.
 796         * lm32-desc.c: Regenerate.
 797         * m32c-desc.c: Regenerate.
 798         * m32r-desc.c: Regenerate.
 799         * mep-desc.c: Regenerate.
 800         * mt-desc.c: Regenerate.
 801         * or1k-desc.c: Regenerate.
 802         * xc16x-desc.c: Regenerate.
 803         * xstormy16-desc.c: Regenerate.
 804
 805 2017-04-11  Alan Modra  <amodra@gmail.com>
 806
 807         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
 808         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
 809         PPC_OPCODE_TMR for e6500.
 810         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
 811         (PPCVEC3): Define as PPC_OPCODE_POWER9.
 812         (PPCVSX2): Define as PPC_OPCODE_POWER8.
 813         (PPCVSX3): Define as PPC_OPCODE_POWER9.
 814         (PPCHTM): Define as PPC_OPCODE_POWER8.
 815         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
 816
 817 2017-04-10  Alan Modra  <amodra@gmail.com>
 818
 819         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
 820         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
 821         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
 822         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
 823
 824 2017-04-09  Pip Cet  <pipcet@gmail.com>
 825
 826         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
 827         appropriate floating-point precision directly.
 828
 829 2017-04-07  Alan Modra  <amodra@gmail.com>
 830
 831         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
 832         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
 833         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
 834         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
 835         vector instructions with E6500 not PPCVEC2.
 836
 837 2017-04-06  Pip Cet  <pipcet@gmail.com>
 838
 839         * Makefile.am: Add wasm32-dis.c.
 840         * configure.ac: Add wasm32-dis.c to wasm32 target.
 841         * disassemble.c: Add wasm32 disassembler code.
 842         * wasm32-dis.c: New file.
 843         * Makefile.in: Regenerate.
 844         * configure: Regenerate.
 845         * po/POTFILES.in: Regenerate.
 846         * po/opcodes.pot: Regenerate.
 847
 848 2017-04-05  Pedro Alves  <palves@redhat.com>
 849
 850         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
 851         * arm-dis.c (parse_arm_disassembler_options): Constify.
 852         * ppc-dis.c (powerpc_init_dialect): Constify local.
 853         * vax-dis.c (parse_disassembler_options): Constify.
 854
 855 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
 856
 857         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
 858         RISCV_GP_SYMBOL.
 859
 860 2017-03-30  Pip Cet  <pipcet@gmail.com>
 861
 862         * configure.ac: Add (empty) bfd_wasm32_arch target.
 863         * configure: Regenerate
 864         * po/opcodes.pot: Regenerate.
 865
 866 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
 867
 868         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
 869         OSA2015.
 870         * opcodes/sparc-opc.c (asi_table): New ASIs.
 871
 872 2017-03-29  Alan Modra  <amodra@gmail.com>
 873
 874         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
 875         "raw" option.
 876         (lookup_powerpc): Don't special case -1 dialect.  Handle
 877         PPC_OPCODE_RAW.
 878         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
 879         lookup_powerpc call, pass it on second.
 880
 881 2017-03-27  Alan Modra  <amodra@gmail.com>
 882
 883         PR 21303
 884         * ppc-dis.c (struct ppc_mopt): Comment.
 885         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
 886
 887 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
 888
 889         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
 890         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
 891         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
 892         (insert_nps_misc_imm_offset): New function.
 893         (extract_nps_misc imm_offset): New function.
 894         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
 895         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
 896
 897 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 898
 899         * s390-mkopc.c (main): Remove vx2 check.
 900         * s390-opc.txt: Remove vx2 instruction flags.
 901
 902 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
 903
 904         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
 905         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
 906         (insert_nps_imm_offset): New function.
 907         (extract_nps_imm_offset): New function.
 908         (insert_nps_imm_entry): New function.
 909         (extract_nps_imm_entry): New function.
 910
 911 2017-03-17  Alan Modra  <amodra@gmail.com>
 912
 913         PR 21248
 914         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
 915         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
 916         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
 917
 918 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 919
 920         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
 921         <c.andi>: Likewise.
 922         <c.addiw> Likewise.
 923
 924 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 925
 926         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
 927
 928 2017-03-13  Andrew Waterman  <andrew@sifive.com>
 929
 930         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
 931         <srl> Likewise.
 932         <srai> Likewise.
 933         <sra> Likewise.
 934
 935 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 936
 937         * i386-gen.c (opcode_modifiers): Replace S with Load.
 938         * i386-opc.h (S): Removed.
 939         (Load): New.
 940         (i386_opcode_modifier): Replace s with load.
 941         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
 942         and {evex}.  Replace S with Load.
 943         * i386-tbl.h: Regenerated.
 944
 945 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 946
 947         * i386-opc.tbl: Use CpuCET on rdsspq.
 948         * i386-tbl.h: Regenerated.
 949
 950 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 951
 952         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
 953         <vsx>: Do not use PPC_OPCODE_VSX3;
 954
 955 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 956
 957         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
 958
 959 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
 960
 961         * i386-dis.c (REG_0F1E_MOD_3): New enum.
 962         (MOD_0F1E_PREFIX_1): Likewise.
 963         (MOD_0F38F5_PREFIX_2): Likewise.
 964         (MOD_0F38F6_PREFIX_0): Likewise.
 965         (RM_0F1E_MOD_3_REG_7): Likewise.
 966         (PREFIX_MOD_0_0F01_REG_5): Likewise.
 967         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 968         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
 969         (PREFIX_0F1E): Likewise.
 970         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
 971         (PREFIX_0F38F5): Likewise.
 972         (dis386_twobyte): Use PREFIX_0F1E.
 973         (reg_table): Add REG_0F1E_MOD_3.
 974         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
 975         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
 976         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
 977         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
 978         (three_byte_table): Use PREFIX_0F38F5.
 979         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
 980         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
 981         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
 982         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
 983         PREFIX_MOD_3_0F01_REG_5_RM_2.
 984         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
 985         (cpu_flags): Add CpuCET.
 986         * i386-opc.h (CpuCET): New enum.
 987         (CpuUnused): Commented out.
 988         (i386_cpu_flags): Add cpucet.
 989         * i386-opc.tbl: Add Intel CET instructions.
 990         * i386-init.h: Regenerated.
 991         * i386-tbl.h: Likewise.
 992
 993 2017-03-06  Alan Modra  <amodra@gmail.com>
 994
 995         PR 21124
 996         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
 997         (extract_raq, extract_ras, extract_rbx): New functions.
 998         (powerpc_operands): Use opposite corresponding insert function.
 999         (Q_MASK): Define.
1000         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1001         register restriction.
1002
1003 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
1004
1005         * disassemble.c Include "safe-ctype.h".
1006         (disassemble_init_for_target): Handle s390 init.
1007         (remove_whitespace_and_extra_commas): New function.
1008         (disassembler_options_cmp): Likewise.
1009         * arm-dis.c: Include "libiberty.h".
1010         (NUM_ELEM): Delete.
1011         (regnames): Use long disassembler style names.
1012         Add force-thumb and no-force-thumb options.
1013         (NUM_ARM_REGNAMES): Rename from this...
1014         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
1015         (get_arm_regname_num_options): Delete.
1016         (set_arm_regname_option): Likewise.
1017         (get_arm_regnames): Likewise.
1018         (parse_disassembler_options): Likewise.
1019         (parse_arm_disassembler_option): Rename from this...
1020         (parse_arm_disassembler_options): ...to this.  Make static.
1021         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1022         (print_insn): Use parse_arm_disassembler_options.
1023         (disassembler_options_arm): New function.
1024         (print_arm_disassembler_options): Handle updated regnames.
1025         * ppc-dis.c: Include "libiberty.h".
1026         (ppc_opts): Add "32" and "64" entries.
1027         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1028         (powerpc_init_dialect): Add break to switch statement.
1029         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1030         (disassembler_options_powerpc): New function.
1031         (print_ppc_disassembler_options): Use ARRAY_SIZE.
1032         Remove printing of "32" and "64".
1033         * s390-dis.c: Include "libiberty.h".
1034         (init_flag): Remove unneeded variable.
1035         (struct s390_options_t): New structure type.
1036         (options): New structure.
1037         (init_disasm): Rename from this...
1038         (disassemble_init_s390): ...to this.  Add initializations for
1039         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
1040         (print_insn_s390): Delete call to init_disasm.
1041         (disassembler_options_s390): New function.
1042         (print_s390_disassembler_options): Print using information from
1043         struct 'options'.
1044         * po/opcodes.pot: Regenerate.
1045
1046 2017-02-28  Jan Beulich  <jbeulich@suse.com>
1047
1048         * i386-dis.c (PCMPESTR_Fixup): New.
1049         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1050         (prefix_table): Use PCMPESTR_Fixup.
1051         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1052         PCMPESTR_Fixup.
1053         (vex_w_table): Delete VPCMPESTR{I,M} entries.
1054         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1055         Split 64-bit and non-64-bit variants.
1056         * opcodes/i386-tbl.h: Re-generate.
1057
1058 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1059
1060         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1061         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1062         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1063         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1064         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1065         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1066         (OP_SVE_V_HSD): New macros.
1067         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1068         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1069         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1070         (aarch64_opcode_table): Add new SVE instructions.
1071         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1072         for rotation operands.  Add new SVE operands.
1073         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1074         (ins_sve_quad_index): Likewise.
1075         (ins_imm_rotate): Split into...
1076         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1077         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1078         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1079         functions.
1080         (aarch64_ins_sve_addr_ri_s4): New function.
1081         (aarch64_ins_sve_quad_index): Likewise.
1082         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1083         * aarch64-asm-2.c: Regenerate.
1084         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1085         (ext_sve_quad_index): Likewise.
1086         (ext_imm_rotate): Split into...
1087         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1088         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1089         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1090         functions.
1091         (aarch64_ext_sve_addr_ri_s4): New function.
1092         (aarch64_ext_sve_quad_index): Likewise.
1093         (aarch64_ext_sve_index): Allow quad indices.
1094         (do_misc_decoding): Likewise.
1095         * aarch64-dis-2.c: Regenerate.
1096         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1097         aarch64_field_kinds.
1098         (OPD_F_OD_MASK): Widen by one bit.
1099         (OPD_F_NO_ZR): Bump accordingly.
1100         (get_operand_field_width): New function.
1101         * aarch64-opc.c (fields): Add new SVE fields.
1102         (operand_general_constraint_met_p): Handle new SVE operands.
1103         (aarch64_print_operand): Likewise.
1104         * aarch64-opc-2.c: Regenerate.
1105
1106 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1107
1108         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1109         (aarch64_feature_compnum): ...this.
1110         (SIMD_V8_3): Replace with...
1111         (COMPNUM): ...this.
1112         (CNUM_INSN): New macro.
1113         (aarch64_opcode_table): Use it for the complex number instructions.
1114
1115 2017-02-24  Jan Beulich  <jbeulich@suse.com>
1116
1117         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1118
1119 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
1120
1121         Add support for associating SPARC ASIs with an architecture level.
1122         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1123         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1124         decoding of SPARC ASIs.
1125
1126 2017-02-23  Jan Beulich  <jbeulich@suse.com>
1127
1128         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1129         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1130
1131 2017-02-21  Jan Beulich  <jbeulich@suse.com>
1132
1133         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1134         1 (instead of to itself). Correct typo.
1135
1136 2017-02-14  Andrew Waterman  <andrew@sifive.com>
1137
1138         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1139         pseudoinstructions.
1140
1141 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
1142
1143         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1144         (aarch64_sys_reg_supported_p): Handle them.
1145
1146 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
1147
1148         * arc-opc.c (UIMM6_20R): Define.
1149         (SIMM12_20): Use above.
1150         (SIMM12_20R): Define.
1151         (SIMM3_5_S): Use above.
1152         (UIMM7_A32_11R_S): Define.
1153         (UIMM7_9_S): Use above.
1154         (UIMM3_13R_S): Define.
1155         (SIMM11_A32_7_S): Use above.
1156         (SIMM9_8R): Define.
1157         (UIMM10_A32_8_S): Use above.
1158         (UIMM8_8R_S): Define.
1159         (W6): Use above.
1160         (arc_relax_opcodes): Use all above defines.
1161
1162 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
1163
1164         * arc-regs.h: Distinguish some of the registers different on
1165         ARC700 and HS38 cpus.
1166
1167 2017-02-14  Alan Modra  <amodra@gmail.com>
1168
1169         PR 21118
1170         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1171         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
1172
1173 2017-02-11  Stafford Horne  <shorne@gmail.com>
1174             Alan Modra  <amodra@gmail.com>
1175
1176         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1177         Use insn_bytes_value and insn_int_value directly instead.  Don't
1178         free allocated memory until function exit.
1179
1180 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
1181
1182         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1183
1184 2017-02-03  Nick Clifton  <nickc@redhat.com>
1185
1186         PR 21096
1187         * aarch64-opc.c (print_register_list): Ensure that the register
1188         list index will fir into the tb buffer.
1189         (print_register_offset_address): Likewise.
1190         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1191
1192 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
1193
1194         PR 21056
1195         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1196         instructions when the previous fetch packet ends with a 32-bit
1197         instruction.
1198
1199 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
1200
1201         * pru-opc.c: Remove vague reference to a future GDB port.
1202
1203 2017-01-20  Nick Clifton  <nickc@redhat.com>
1204
1205         * po/ga.po: Updated Irish translation.
1206
1207 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1208
1209         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1210
1211 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1212
1213         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
1214         if FETCH_DATA returns 0.
1215         (m68k_scan_mask): Likewise.
1216         (print_insn_m68k): Update code to handle -1 return value.
1217
1218 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1219
1220         * m68k-dis.c (enum print_insn_arg_error): New.
1221         (NEXTBYTE): Replace -3 with
1222         PRINT_INSN_ARG_MEMORY_ERROR.
1223         (NEXTULONG): Likewise.
1224         (NEXTSINGLE): Likewise.
1225         (NEXTDOUBLE): Likewise.
1226         (NEXTDOUBLE): Likewise.
1227         (NEXTPACKED): Likewise.
1228         (FETCH_ARG): Likewise.
1229         (FETCH_DATA): Update comments.
1230         (print_insn_arg): Update comments. Replace magic numbers with
1231         enum.
1232         (match_insn_m68k): Likewise.
1233
1234 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1235
1236         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1237         * i386-dis-evex.h (evex_table): Updated.
1238         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1239         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1240         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1241         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1242         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1243         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1244         * i386-init.h: Regenerate.
1245         * i386-tbl.h: Ditto.
1246
1247 2017-01-12  Yao Qi  <yao.qi@linaro.org>
1248
1249         * msp430-dis.c (msp430_singleoperand): Return -1 if
1250         msp430dis_opcode_signed returns false.
1251         (msp430_doubleoperand): Likewise.
1252         (msp430_branchinstr): Return -1 if
1253         msp430dis_opcode_unsigned returns false.
1254         (msp430x_calla_instr): Likewise.
1255         (print_insn_msp430): Likewise.
1256
1257 2017-01-05  Nick Clifton  <nickc@redhat.com>
1258
1259         PR 20946
1260         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1261         could not be matched.
1262         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1263         NULL.
1264
1265 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1266
1267         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1268         (aarch64_opcode_table): Use RCPC_INSN.
1269
1270 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
1271
1272         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1273         extension.
1274         * riscv-opcodes/all-opcodes: Likewise.
1275
1276 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
1277
1278         * riscv-dis.c (print_insn_args): Add fall through comment.
1279
1280 2017-01-03  Nick Clifton  <nickc@redhat.com>
1281
1282         * po/sr.po: New Serbian translation.
1283         * configure.ac (ALL_LINGUAS): Add sr.
1284         * configure: Regenerate.
1285
1286 2017-01-02  Alan Modra  <amodra@gmail.com>
1287
1288         * epiphany-desc.h: Regenerate.
1289         * epiphany-opc.h: Regenerate.
1290         * fr30-desc.h: Regenerate.
1291         * fr30-opc.h: Regenerate.
1292         * frv-desc.h: Regenerate.
1293         * frv-opc.h: Regenerate.
1294         * ip2k-desc.h: Regenerate.
1295         * ip2k-opc.h: Regenerate.
1296         * iq2000-desc.h: Regenerate.
1297         * iq2000-opc.h: Regenerate.
1298         * lm32-desc.h: Regenerate.
1299         * lm32-opc.h: Regenerate.
1300         * m32c-desc.h: Regenerate.
1301         * m32c-opc.h: Regenerate.
1302         * m32r-desc.h: Regenerate.
1303         * m32r-opc.h: Regenerate.
1304         * mep-desc.h: Regenerate.
1305         * mep-opc.h: Regenerate.
1306         * mt-desc.h: Regenerate.
1307         * mt-opc.h: Regenerate.
1308         * or1k-desc.h: Regenerate.
1309         * or1k-opc.h: Regenerate.
1310         * xc16x-desc.h: Regenerate.
1311         * xc16x-opc.h: Regenerate.
1312         * xstormy16-desc.h: Regenerate.
1313         * xstormy16-opc.h: Regenerate.
1314
1315 2017-01-02  Alan Modra  <amodra@gmail.com>
1316
1317         Update year range in copyright notice of all files.
1318
1319 For older changes see ChangeLog-2016
1320 \f
1321 Copyright (C) 2017 Free Software Foundation, Inc.
1322
1323 Copying and distribution of this file, with or without modification,
1324 are permitted in any medium without royalty provided the copyright
1325 notice and this notice are preserved.
1326
1327 Local Variables:
1328 mode: change-log
1329 left-margin: 8
1330 fill-column: 74
1331 version-control: never
1332 End: