opcodes/ChangeLog

   1 2021-06-22  Alan Modra  <amodra@gmail.com>
   2
   3         * pj-dis.c (print_insn_pj): Don't print trailing tab.  Do
   4         print separator for pcrel insns.
   5
   6 2021-06-19  Alan Modra  <amodra@gmail.com>
   7
   8         * vax-dis.c (print_insn_vax): Avoid pointer overflow.
   9
  10 2021-06-19  Alan Modra  <amodra@gmail.com>
  11
  12         * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
  13         entire buffer.
  14
  15 2021-06-17  Alan Modra  <amodra@gmail.com>
  16
  17         * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
  18         in table.
  19
  20 2021-06-03  Alan Modra  <amodra@gmail.com>
  21
  22         PR 1202
  23         * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
  24         Use unsigned int for inst.
  25
  26 2021-06-02  Shahab Vahedi  <shahab@synopsys.com>
  27
  28         * arc-dis.c (arc_option_arg_t): New enumeration.
  29         (arc_options): New variable.
  30         (disassembler_options_arc): New function.
  31         (print_arc_disassembler_options): Reimplement in terms of
  32         "disassembler_options_arc".
  33
  34 2021-05-29  Alan Modra  <amodra@gmail.com>
  35
  36         * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
  37         Don't special case PPC_OPCODE_RAW.
  38         (lookup_prefix): Likewise.
  39         (lookup_vle, lookup_spe2): Similarly.  Add dialect parameter and..
  40         (print_insn_powerpc): ..update caller.
  41         * ppc-opc.c (EXT): Define.
  42         (powerpc_opcodes): Mark extended mnemonics with EXT.
  43         (prefix_opcodes, vle_opcodes): Likewise.
  44         (XISEL, XISEL_MASK): Add cr field and simplify.
  45         (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
  46         all isel variants to where the base mnemonic belongs.  Sort dstt,
  47         dststt and dssall.
  48
  49 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  50
  51         * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
  52         COP3 opcode instructions.
  53
  54 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  55
  56         * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
  57         "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
  58         "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
  59         "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
  60         "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
  61         "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
  62         "cop2", and "cop3" entries.
  63
  64 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  65
  66         * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
  67         entries and associated comments.
  68
  69 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  70
  71         * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
  72         of "c0".
  73
  74 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  75
  76         * mips-dis.c (mips_cp1_names_mips): New variable.
  77         (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
  78         for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
  79         "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
  80         "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
  81         "r12000", "r14000", "r16000", "mips5", "loongson2e", and
  82         "loongson2f".
  83
  84 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  85
  86         * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
  87         handling code over to...
  88         <OP_REG_CONTROL>: ... this new case.
  89         * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
  90         (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
  91         "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
  92         replacing the `G' operand code with `g'.  Update "cftc1" and
  93         "cftc2" entries replacing the `E' operand code with `y'.
  94         * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
  95         (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
  96         entries replacing the `G' operand code with `g'.
  97
  98 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  99
 100         * mips-dis.c (mips_cp0_names_r3900): New variable.
 101         (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
 102         for "r3900".
 103
 104 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 105
 106         * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
 107         and "mtthc2" to using the `G' rather than `g' operand code for
 108         the coprocessor control register referred.
 109
 110 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 111
 112         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
 113         entries with each other.
 114
 115 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
 116
 117         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
 118
 119 2021-05-25  Alan Modra  <amodra@gmail.com>
 120
 121         * cris-desc.c: Regenerate.
 122         * cris-desc.h: Regenerate.
 123         * cris-opc.h: Regenerate.
 124         * po/POTFILES.in: Regenerate.
 125
 126 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
 127
 128         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
 129         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
 130         (CGEN_CPUS): Add cris.
 131         (CRIS_DEPS): Define.
 132         (stamp-cris): New rule.
 133         * cgen.sh: Handle desc action.
 134         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
 135         * Makefile.in, configure: Regenerate.
 136
 137 2021-05-18  Job Noorman  <mtvec@pm.me>
 138
 139         PR 27814
 140         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
 141         the elf objects.
 142
 143 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
 144
 145         * arm-dis.c (mve_opcodes): Fix disassembly of
 146         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
 147         (is_mve_encoding_conflict): MVE vector loads should not match
 148         when P = W = 0.
 149         (is_mve_unpredictable): It's not unpredictable to use the same
 150         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
 151
 152 2021-05-11  Nick Clifton  <nickc@redhat.com>
 153
 154         PR 27840
 155         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
 156         the end of the code buffer.
 157
 158 2021-05-06  Stafford Horne  <shorne@gmail.com>
 159
 160         PR 21464
 161         * or1k-asm.c: Regenerate.
 162
 163 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
 164
 165         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
 166         info->insn_info_valid.
 167
 168 2021-04-26  Jan Beulich  <jbeulich@suse.com>
 169
 170         * i386-opc.tbl (lea): Add Optimize.
 171         * opcodes/i386-tbl.h: Re-generate.
 172
 173 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 174
 175         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
 176         of l32r fetch and display referenced literal value.
 177
 178 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 179
 180         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
 181         to 4 for literal disassembly.
 182
 183 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 184
 185         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
 186         for TLBI instruction.
 187
 188 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 189
 190         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
 191         DC instruction.
 192
 193 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 194
 195         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
 196         "qualifier".
 197         (convert_mov_to_movewide): Add initializer for "value".
 198
 199 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 200
 201         * aarch64-opc.c: Add RME system registers.
 202
 203 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 204
 205         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
 206         "addi d,CV,z" to "c.mv d,CV".
 207
 208 2021-04-12  Alan Modra  <amodra@gmail.com>
 209
 210         * configure.ac (--enable-checking): Add support.
 211         * config.in: Regenerate.
 212         * configure: Regenerate.
 213
 214 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 215
 216         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 217         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 218
 219 2021-04-09  Alan Modra  <amodra@gmail.com>
 220
 221         * ppc-dis.c (struct dis_private): Add "special".
 222         (POWERPC_DIALECT): Delete.  Replace uses with..
 223         (private_data): ..this.  New inline function.
 224         (disassemble_init_powerpc): Init "special" names.
 225         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 226         field of prefix instructions.
 227         (bsearch_reloc, print_got_plt): New functions.
 228         (print_insn_powerpc): For pcrel instructions, print target address
 229         and symbol if known, and decode plt and got loads too.
 230
 231 2021-04-08  Alan Modra  <amodra@gmail.com>
 232
 233         PR 27684
 234         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 235
 236 2021-04-08  Alan Modra  <amodra@gmail.com>
 237
 238         PR 27676
 239         * ppc-opc.c (DCBT_EO): Move earlier.
 240         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 241         (powerpc_operands): Add THCT and THDS entries.
 242         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 243
 244 2021-04-06  Alan Modra  <amodra@gmail.com>
 245
 246         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 247         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 248         symbol_at_address_func.
 249
 250 2021-04-05  Alan Modra  <amodra@gmail.com>
 251
 252         * configure.ac: Don't check for limits.h, string.h, strings.h or
 253         stdlib.h.
 254         (AC_ISC_POSIX): Don't invoke.
 255         * sysdep.h: Include stdlib.h and string.h unconditionally.
 256         * i386-opc.h: Include limits.h unconditionally.
 257         * wasm32-dis.c: Likewise.
 258         * cgen-opc.c: Don't include alloca-conf.h.
 259         * config.in: Regenerate.
 260         * configure: Regenerate.
 261
 262 2021-04-01  Martin Liska  <mliska@suse.cz>
 263
 264         * arm-dis.c (strneq): Remove strneq and use startswith.
 265         * cr16-dis.c (print_insn_cr16): Likewise.
 266         * score-dis.c (streq): Likewise.
 267         (strneq): Likewise.
 268         * score7-dis.c (strneq): Likewise.
 269
 270 2021-04-01  Alan Modra  <amodra@gmail.com>
 271
 272         PR 27675
 273         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 274
 275 2021-03-31  Alan Modra  <amodra@gmail.com>
 276
 277         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 278         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 279         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 280         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 281         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 282         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 283         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 284         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 285         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 286         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 287         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 288         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 289         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 290         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 291         and TRUE with true throughout.
 292
 293 2021-03-31  Alan Modra  <amodra@gmail.com>
 294
 295         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 296         * aarch64-dis.h: Likewise.
 297         * aarch64-opc.c: Likewise.
 298         * avr-dis.c: Likewise.
 299         * csky-dis.c: Likewise.
 300         * nds32-asm.c: Likewise.
 301         * nds32-dis.c: Likewise.
 302         * nfp-dis.c: Likewise.
 303         * riscv-dis.c: Likewise.
 304         * s12z-dis.c: Likewise.
 305         * wasm32-dis.c: Likewise.
 306
 307 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 308
 309         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 310         (i386_seg_prefixes): New.
 311         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 312         (i386_seg_prefixes): Declare.
 313
 314 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 315
 316         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 317
 318 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 319
 320         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 321         * i386-reg.tbl (st): Move down.
 322         (st(0)): Delete. Extend comment.
 323         * i386-tbl.h: Re-generate.
 324
 325 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 326
 327         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 328         (cmpsd): Move next to cmps.
 329         (movsd): Move next to movs.
 330         (cmpxchg16b): Move to separate section.
 331         (fisttp, fisttpll): Likewise.
 332         (monitor, mwait): Likewise.
 333         * i386-tbl.h: Re-generate.
 334
 335 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 336
 337         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 338         (vpsadbw): Add C.
 339         * i386-tbl.h: Re-generate.
 340
 341 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 342
 343         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 344         pclmul, gfni): New templates. Use them wherever possible. Move
 345         SSE4.1 pextrw into respective section.
 346         * i386-tbl.h: Re-generate.
 347
 348 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 349
 350         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 351         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 352         "length".
 353         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 354         Convert all of their uses to representation in opcode.
 355
 356 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 357
 358         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 359         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 360         value of None. Shrink operands to 3 bits.
 361
 362 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 363
 364         * i386-gen.c (process_i386_opcode_modifier): New parameter
 365         "space".
 366         (output_i386_opcode): New local variable "space". Adjust
 367         process_i386_opcode_modifier() invocation.
 368         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 369         invocation.
 370         * i386-tbl.h: Re-generate.
 371
 372 2021-03-29  Alan Modra  <amodra@gmail.com>
 373
 374         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 375         (fp_qualifier_p, get_data_pattern): Likewise.
 376         (aarch64_get_operand_modifier_from_value): Likewise.
 377         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 378         (operand_variant_qualifier_p): Likewise.
 379         (qualifier_value_in_range_constraint_p): Likewise.
 380         (aarch64_get_qualifier_esize): Likewise.
 381         (aarch64_get_qualifier_nelem): Likewise.
 382         (aarch64_get_qualifier_standard_value): Likewise.
 383         (get_lower_bound, get_upper_bound): Likewise.
 384         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 385         (aarch64_print_operand): Likewise.
 386         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 387         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 388         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 389         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 390         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 391         (print_insn_tic6x): Likewise.
 392
 393 2021-03-29  Alan Modra  <amodra@gmail.com>
 394
 395         * arc-dis.c (extract_operand_value): Correct NULL cast.
 396         * frv-opc.h: Regenerate.
 397
 398 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 399
 400         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 401         MMX form.
 402         * i386-tbl.h: Re-generate.
 403
 404 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 405
 406         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 407         immediate in br.n instruction.
 408
 409 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 410
 411         * i386-dis.c (XMGatherD, VexGatherD): New.
 412         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 413         (print_insn): Check masking for S/G insns.
 414         (OP_E_memory): New local variable check_gather. Extend mandatory
 415         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 416         Extend check for disallowed 16-bit addressing.
 417         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 418         if()s to switch(). Check register conflicts for (VEX-encoded)
 419         gathers. Drop no longer reachable cases.
 420         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 421         vgatherdp*.
 422
 423 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 424
 425         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 426         zeroing-masking without masking.
 427
 428 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 429
 430         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 431         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 432         single-operand forms as deprecated.
 433         * i386-tbl.h: Re-generate.
 434
 435 2021-03-25  Alan Modra  <amodra@gmail.com>
 436
 437         PR 27647
 438         * ppc-opc.c (XLOCB_MASK): Delete.
 439         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 440         XLBH_MASK.
 441         (powerpc_opcodes): Accept a BH field on all extended forms of
 442         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 443
 444 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 445
 446         * i386-gen.c (output_i386_opcode): Drop processing of
 447         opcode_length. Calculate length from base_opcode. Adjust prefix
 448         encoding determination.
 449         (process_i386_opcodes): Drop output of fake opcode_length.
 450         * i386-opc.h (struct insn_template): Drop opcode_length field.
 451         * i386-opc.tbl: Drop opcode length field from all templates.
 452         * i386-tbl.h: Re-generate.
 453
 454 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 455
 456         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 457         parameter "prefix". Drop local variable "regular_encoding".
 458         Record prefix setting / check for consistency.
 459         (output_i386_opcode): Parse opcode_length and base_opcode
 460         earlier. Derive prefix encoding. Drop no longer applicable
 461         consistency checking. Adjust process_i386_opcode_modifier()
 462         invocation.
 463         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 464         invocation.
 465         * i386-tbl.h: Re-generate.
 466
 467 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 468
 469         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 470         check.
 471         * i386-opc.h (Prefix_*): Move #define-s.
 472         * i386-opc.tbl: Move pseudo prefix enumerator values to
 473         extension opcode field. Introduce pseudopfx template.
 474         * i386-tbl.h: Re-generate.
 475
 476 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 477
 478         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 479         comment.
 480         * i386-tbl.h: Re-generate.
 481
 482 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 483
 484         * i386-opc.h (struct insn_template): Move cpu_flags field past
 485         opcode_modifier one.
 486         * i386-tbl.h: Re-generate.
 487
 488 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 489
 490         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 491         * i386-opc.h (OpcodeSpace): New enumerator.
 492         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 493         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 494         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 495         (struct i386_opcode_modifier): New field opcodespace. Shrink
 496         opcodeprefix field.
 497         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 498         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 499         OpcodePrefix uses.
 500         * i386-tbl.h: Re-generate.
 501
 502 2021-03-22  Martin Liska  <mliska@suse.cz>
 503
 504         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 505         * arc-dis.c (parse_option): Likewise.
 506         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 507         * cris-dis.c (print_with_operands): Likewise.
 508         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 509         * i386-dis.c (print_insn): Likewise.
 510         * ia64-gen.c (fetch_insn_class): Likewise.
 511         (parse_resource_users): Likewise.
 512         (in_iclass): Likewise.
 513         (lookup_specifier): Likewise.
 514         (insert_opcode_dependencies): Likewise.
 515         * mips-dis.c (parse_mips_ase_option): Likewise.
 516         (parse_mips_dis_option): Likewise.
 517         * s390-dis.c (disassemble_init_s390): Likewise.
 518         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 519
 520 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 521
 522         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 523
 524 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 525
 526         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 527         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 528
 529 2021-03-12  Alan Modra  <amodra@gmail.com>
 530
 531         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 532
 533 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 534
 535         * i386-dis.c (OP_XMM): Re-order checks.
 536
 537 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 538
 539         * i386-dis.c (putop): Drop need_vex check when also checking
 540         vex.evex.
 541         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 542         checking vex.b.
 543
 544 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 545
 546         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 547         checks. Move case label past broadcast check.
 548
 549 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 550
 551         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 552         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 553         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 554         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 555         EVEX_W_0F38C7_M_0_L_2): Delete.
 556         (REG_EVEX_0F38C7_M_0_L_2): New.
 557         (intel_operand_size): Handle VEX and EVEX the same for
 558         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 559         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 560         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 561         vex_vsib_q_w_d_mode uses.
 562         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 563         0F38A1, and 0F38A3 entries.
 564         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 565         entry.
 566         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 567         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 568         0F38A3 entries.
 569
 570 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 571
 572         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 573         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 574         MOD_VEX_0FXOP_09_12): Rename to ...
 575         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 576         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 577         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 578         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 579         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 580         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 581         (reg_table): Adjust comments.
 582         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 583         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 584         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 585         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 586         (vex_len_table): Adjust opcode 0A_12 entry.
 587         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 588         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 589         (rm_table): Move hreset entry.
 590
 591 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 592
 593         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 594         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 595         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 596         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 597         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 598         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 599         (get_valid_dis386): Also handle 512-bit vector length when
 600         vectoring into vex_len_table[].
 601         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 602         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 603         entries.
 604         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 605         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 606         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 607         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 608         entries.
 609
 610 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 611
 612         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 613         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 614         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 615         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 616         entries.
 617         * i386-dis-evex-len.h (evex_len_table): Likewise.
 618         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 619
 620 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 621
 622         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 623         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 624         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 625         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 626         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 627         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 628         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 629         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 630         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 631         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 632         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 633         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 634         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 635         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 636         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 637         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 638         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 639         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 640         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 641         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 642         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 643         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 644         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 645         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 646         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 647         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 648         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 649         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 650         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 651         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 652         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 653         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 654         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 655         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 656         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 657         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 658         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 659         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 660         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 661         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 662         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 663         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 664         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 665         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 666         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 667         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 668         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 669         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 670         EVEX_W_0F3A43_L_n): New.
 671         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 672         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 673         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 674         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 675         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 676         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 677         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 678         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 679         0F385B, 0F38C6, and 0F38C7 entries.
 680         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 681         0F38C6 and 0F38C7.
 682         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 683         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 684         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 685         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 686
 687 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 688
 689         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 690         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 691         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 692         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 693         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 694         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 695         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 696         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 697         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 698         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 699         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 700         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 701         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 702         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 703         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 704         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 705         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 706         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 707         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 708         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 709         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 710         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 711         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 712         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 713         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 714         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 715         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 716         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 717         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 718         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 719         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 720         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 721         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 722         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 723         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 724         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 725         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 726         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 727         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 728         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 729         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 730         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 731         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 732         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 733         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 734         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 735         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 736         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 737         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 738         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 739         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 740         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 741         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 742         VEX_W_0F99_P_2_LEN_0): Delete.
 743         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 744         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 745         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 746         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 747         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 748         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 749         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 750         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 751         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 752         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 753         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 754         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 755         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 756         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 757         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 758         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 759         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 760         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 761         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 762         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 763         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 764         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 765         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 766         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 767         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 768         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 769         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 770         (prefix_table): No longer link to vex_len_table[] for opcodes
 771         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 772         0F92, 0F93, 0F98, and 0F99.
 773         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 774         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 775         0F98, and 0F99.
 776         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 777         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 778         0F98, and 0F99.
 779         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 780         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 781         0F98, and 0F99.
 782         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 783         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 784         0F98, and 0F99.
 785
 786 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 787
 788         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 789         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 790         REG_VEX_0F73_M_0 respectively.
 791         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 792         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 793         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 794         MOD_VEX_0F73_REG_7): Delete.
 795         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 796         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 797         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 798         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 799         PREFIX_VEX_0F3AF0_L_0 respectively.
 800         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 801         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 802         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 803         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 804         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 805         VEX_LEN_0F38F7): New.
 806         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 807         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 808         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 809         0F38F3.
 810         (prefix_table): No longer link to vex_len_table[] for opcodes
 811         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 812         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 813         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 814         0F38F6, 0F38F7, and 0F3AF0.
 815         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 816         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 817         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 818         0F73.
 819
 820 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 821
 822         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 823         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 824         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 825         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 826         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 827         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 828         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 829         73.
 830         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 831         0F72, and 0F73.
 832         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 833         0F73.
 834
 835 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 836
 837         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 838         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 839         (reg_table): Don't link to mod_table[] where not needed. Add
 840         PREFIX_IGNORED to nop entries.
 841         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 842         (mod_table): Add nop entries next to prefetch ones. Drop
 843         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 844         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 845         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 846         PREFIX_OPCODE from endbr* entries.
 847         (get_valid_dis386): Also consider entry's name when zapping
 848         vindex.
 849         (print_insn): Handle PREFIX_IGNORED.
 850
 851 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 852
 853         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 854         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 855         element.
 856         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 857         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 858         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 859         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 860         (struct i386_opcode_modifier): Delete notrackprefixok,
 861         islockable, hleprefixok, and repprefixok fields. Add prefixok
 862         field.
 863         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 864         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 865         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 866         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 867         Replace HLEPrefixOk.
 868         * opcodes/i386-tbl.h: Re-generate.
 869
 870 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 871
 872         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 873         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 874         64-bit form.
 875         * opcodes/i386-tbl.h: Re-generate.
 876
 877 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 878
 879         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 880         for {} instead of {0}. Don't look for '0'.
 881         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 882         size specifiers.
 883
 884 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 885
 886         PR 27158
 887         * riscv-dis.c (print_insn_args): Updated encoding macros.
 888         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 889         (match_c_addi16sp): Updated encoding macros.
 890         (match_c_lui): Likewise.
 891         (match_c_lui_with_hint): Likewise.
 892         (match_c_addi4spn): Likewise.
 893         (match_c_slli): Likewise.
 894         (match_slli_as_c_slli): Likewise.
 895         (match_c_slli64): Likewise.
 896         (match_srxi_as_c_srxi): Likewise.
 897         (riscv_insn_types): Added .insn css/cl/cs.
 898
 899 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 900
 901         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 902         (default_priv_spec): Updated type to riscv_spec_class.
 903         (parse_riscv_dis_option): Updated.
 904         * riscv-opc.c: Moved stuff and make the file tidy.
 905
 906 2021-02-17  Alan Modra  <amodra@gmail.com>
 907
 908         * wasm32-dis.c: Include limits.h.
 909         (CHAR_BIT): Provide backup define.
 910         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 911         Correct signed overflow checking.
 912
 913 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 914
 915         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 916         * i386-tbl.h: Re-generate.
 917
 918 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 919
 920         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 921         Oword.
 922         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 923
 924 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 925
 926         * s390-mkopc.c (main): Accept arch14 as cpu string.
 927         * s390-opc.txt: Add new arch14 instructions.
 928
 929 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 930
 931         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 932         favour of LIBINTL.
 933         * configure: Regenerated.
 934
 935 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 936
 937         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 938         * tic54x-opc.c (regs): Rename to ...
 939         (tic54x_regs): ... this.
 940         (mmregs): Rename to ...
 941         (tic54x_mmregs): ... this.
 942         (condition_codes): Rename to ...
 943         (tic54x_condition_codes): ... this.
 944         (cc2_codes): Rename to ...
 945         (tic54x_cc2_codes): ... this.
 946         (cc3_codes): Rename to ...
 947         (tic54x_cc3_codes): ... this.
 948         (status_bits): Rename to ...
 949         (tic54x_status_bits): ... this.
 950         (misc_symbols): Rename to ...
 951         (tic54x_misc_symbols): ... this.
 952
 953 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 954
 955         * riscv-opc.c (MASK_RVB_IMM): Removed.
 956         (riscv_opcodes): Removed zb* instructions.
 957         (riscv_ext_version_table): Removed versions for zb*.
 958
 959 2021-01-26  Alan Modra  <amodra@gmail.com>
 960
 961         * i386-gen.c (parse_template): Ensure entire template_instance
 962         is initialised.
 963
 964 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 965
 966         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 967         (riscv_fpr_names_abi): Likewise.
 968         (riscv_opcodes): Likewise.
 969         (riscv_insn_types): Likewise.
 970
 971 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 972
 973         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 974
 975 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 976
 977         * riscv-dis.c: Comments tidy and improvement.
 978         * riscv-opc.c: Likewise.
 979
 980 2021-01-13  Alan Modra  <amodra@gmail.com>
 981
 982         * Makefile.in: Regenerate.
 983
 984 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 985
 986         PR binutils/26792
 987         * configure.ac: Use GNU_MAKE_JOBSERVER.
 988         * aclocal.m4: Regenerated.
 989         * configure: Likewise.
 990
 991 2021-01-12  Nick Clifton  <nickc@redhat.com>
 992
 993         * po/sr.po: Updated Serbian translation.
 994
 995 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 996
 997         PR ld/27173
 998         * configure: Regenerated.
 999
1000 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1001
1002         * aarch64-asm-2.c: Regenerate.
1003         * aarch64-dis-2.c: Likewise.
1004         * aarch64-opc-2.c: Likewise.
1005         * aarch64-opc.c (aarch64_print_operand):
1006         Delete handling of AARCH64_OPND_CSRE_CSR.
1007         * aarch64-tbl.h (aarch64_feature_csre): Delete.
1008         (CSRE): Likewise.
1009         (_CSRE_INSN): Likewise.
1010         (aarch64_opcode_table): Delete csr.
1011
1012 2021-01-11  Nick Clifton  <nickc@redhat.com>
1013
1014         * po/de.po: Updated German translation.
1015         * po/fr.po: Updated French translation.
1016         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1017         * po/sv.po: Updated Swedish translation.
1018         * po/uk.po: Updated Ukranian translation.
1019
1020 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
1021
1022         * configure: Regenerated.
1023
1024 2021-01-09  Nick Clifton  <nickc@redhat.com>
1025
1026         * configure: Regenerate.
1027         * po/opcodes.pot: Regenerate.
1028
1029 2021-01-09  Nick Clifton  <nickc@redhat.com>
1030
1031         * 2.36 release branch crated.
1032
1033 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
1034
1035         * ppc-opc.c (insert_dw, (extract_dw): New functions.
1036         (DW, (XRC_MASK): Define.
1037         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1038
1039 2021-01-09  Alan Modra  <amodra@gmail.com>
1040
1041         * configure: Regenerate.
1042
1043 2021-01-08  Nick Clifton  <nickc@redhat.com>
1044
1045         * po/sv.po: Updated Swedish translation.
1046
1047 2021-01-08  Nick Clifton  <nickc@redhat.com>
1048
1049         PR 27129
1050         * aarch64-dis.c (determine_disassembling_preference): Move call to
1051         aarch64_match_operands_constraint outside of the assertion.
1052         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1053         Replace with a return of FALSE.
1054
1055         PR 27139
1056         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1057         core system register.
1058
1059 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
1060
1061         * configure: Regenerate.
1062
1063 2021-01-07  Nick Clifton  <nickc@redhat.com>
1064
1065         * po/fr.po: Updated French translation.
1066
1067 2021-01-07  Fredrik Noring  <noring@nocrew.org>
1068
1069         * m68k-opc.c (chkl): Change minimum architecture requirement to
1070         m68020.
1071
1072 2021-01-07  Philipp Tomsich  <prt@gnu.org>
1073
1074         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1075
1076 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
1077             Jim Wilson  <jimw@sifive.com>
1078             Andrew Waterman  <andrew@sifive.com>
1079             Maxim Blinov  <maxim.blinov@embecosm.com>
1080             Kito Cheng  <kito.cheng@sifive.com>
1081             Nelson Chu  <nelson.chu@sifive.com>
1082
1083         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1084         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1085
1086 2021-01-01  Alan Modra  <amodra@gmail.com>
1087
1088         Update year range in copyright notice of all files.
1089
1090 For older changes see ChangeLog-2020
1091 \f
1092 Copyright (C) 2021 Free Software Foundation, Inc.
1093
1094 Copying and distribution of this file, with or without modification,
1095 are permitted in any medium without royalty provided the copyright
1096 notice and this notice are preserved.
1097
1098 Local Variables:
1099 mode: change-log
1100 left-margin: 8
1101 fill-column: 74
1102 version-control: never
1103 End: