opcodes/ChangeLog

   1 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
   2
   3         * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
   4         * micromips-opc.c (micromips_opcodes): Likewise.
   5         * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
   6         and "+T" handling.  Check for a "0" suffix when deciding whether to
   7         use coprocessor 0 names.  In that case, also check for ",H" selectors.
   8
   9 2013-07-05  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  10
  11         * s390-opc.c (J12_12, J24_24): New macros.
  12         (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
  13         (MASK_MII_UPI): Rename to MASK_MII_UPP.
  14         * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
  15
  16 2013-07-04  Alan Modra  <amodra@gmail.com>
  17
  18         * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
  19
  20 2013-06-26  Nick Clifton  <nickc@redhat.com>
  21
  22         * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
  23         field when checking for type 2 nop.
  24         * rx-decode.c: Regenerate.
  25
  26 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
  27
  28         * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
  29         and "movep" macros.
  30
  31 2013-06-24  Maciej W. Rozycki  <macro@codesourcery.com>
  32
  33         * mips-dis.c (is_mips16_plt_tail): New function.
  34         (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
  35         word.
  36         (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
  37
  38 2013-06-21  DJ Delorie  <dj@redhat.com>
  39
  40         * msp430-decode.opc: New.
  41         * msp430-decode.c: New/generated.
  42         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
  43         (MAINTAINER_CLEANFILES): Likewise.
  44         Add rule to build msp430-decode.c frommsp430decode.opc
  45         using the opc2c program.
  46         * Makefile.in: Regenerate.
  47         * configure.in: Add msp430-decode.lo to msp430 architecture files.
  48         * configure: Regenerate.
  49
  50 2013-06-20  Yufeng Zhang  <yufeng.zhang@arm.com>
  51
  52         * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
  53         (SYMTAB_AVAILABLE): Removed.
  54         (#include "elf/aarch64.h): Ditto.
  55
  56 2013-06-17  Catherine Moore  <clm@codesourcery.com>
  57             Maciej W. Rozycki  <macro@codesourcery.com>
  58             Chao-Ying Fu  <fu@mips.com>
  59
  60         * micromips-opc.c (EVA): Define.
  61         (TLBINV): Define.
  62         (micromips_opcodes): Add EVA opcodes.
  63         * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
  64         (print_insn_args): Handle EVA offsets.
  65         (print_insn_micromips): Likewise.
  66         * mips-opc.c (EVA): Define.
  67         (TLBINV): Define.
  68         (mips_builtin_opcodes): Add EVA opcodes.
  69
  70 2013-06-17  Alan Modra  <amodra@gmail.com>
  71
  72         * Makefile.am (mips-opc.lo): Add rules to create automatic
  73         dependency files.  Pass archdefs.
  74         (micromips-opc.lo, mips16-opc.lo): Likewise.
  75         * Makefile.in: Regenerate.
  76
  77 2013-06-14  DJ Delorie  <dj@redhat.com>
  78
  79         * rx-decode.opc (rx_decode_opcode): Bit operations on
  80         registers are 32-bit operations, not 8-bit operations.
  81         * rx-decode.c: Regenerate.
  82
  83 2013-06-13  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
  84
  85         * micromips-opc.c (IVIRT): New define.
  86         (IVIRT64): New define.
  87         (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
  88         tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
  89
  90         * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
  91         dmtgc0 to print cp0 names.
  92
  93 2013-06-09  Sandra Loosemore  <sandra@codesourcery.com>
  94
  95         * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
  96         argument.
  97
  98 2013-06-08  Catherine Moore  <clm@codesourcery.com>
  99             Richard Sandiford  <rdsandiford@googlemail.com>
 100
 101         * micromips-opc.c (D32, D33, MC): Update definitions.
 102         (micromips_opcodes):  Initialize ase field.
 103         * mips-dis.c (mips_arch_choice): Add ase field.
 104         (mips_arch_choices): Initialize ase field.
 105         (set_default_mips_dis_options): Declare and setup mips_ase.
 106         * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
 107         MT32, MC): Update definitions.
 108         (mips_builtin_opcodes): Initialize ase field.
 109
 110 2013-05-24  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 111
 112         * s390-opc.txt (flogr): Require a register pair destination.
 113
 114 2013-05-23  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 115
 116         * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
 117         instruction format.
 118
 119 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 120
 121         * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
 122
 123 2013-05-20  Peter Bergner <bergner@vnet.ibm.com>
 124
 125         * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
 126         * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
 127         XLS_MASK, PPCVSX2): New defines.
 128         (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
 129         fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
 130         mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
 131         mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
 132         mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
 133         vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
 134         vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
 135         vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
 136         vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
 137         vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
 138         vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
 139         vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
 140         vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
 141         vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
 142         xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
 143         xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
 144         xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
 145         xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
 146         <lxvx, stxvx>: New extended mnemonics.
 147
 148 2013-05-17  Alan Modra  <amodra@gmail.com>
 149
 150         * ia64-raw.tbl: Replace non-ASCII char.
 151         * ia64-waw.tbl: Likewise.
 152         * ia64-asmtab.c: Regenerate.
 153
 154 2013-05-15  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 155
 156         * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
 157         * i386-init.h: Regenerated.
 158
 159 2013-05-13  Yufeng Zhang  <yufeng.zhang@arm.com>
 160
 161         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
 162         * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
 163         check from [0, 255] to [-128, 255].
 164
 165 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 166
 167         * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
 168         Add INSN_VIRT and INSN_VIRT64 to mips64r2.
 169         (parse_mips_dis_option): Handle the virt option.
 170         (print_insn_args): Handle "+J".
 171         (print_mips_disassembler_options): Print out message about virt64.
 172         * mips-opc.c (IVIRT): New define.
 173         (IVIRT64): New define.
 174         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 175         tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
 176         Move rfe to the bottom as it conflicts with tlbgp.
 177
 178 2013-05-09  Alan Modra  <amodra@gmail.com>
 179
 180         * ppc-opc.c (extract_vlesi): Properly sign extend.
 181         (extract_vlensi): Likewise.  Comment reason for setting invalid.
 182
 183 2013-05-02  Nick Clifton  <nickc@redhat.com>
 184
 185         * msp430-dis.c: Add support for MSP430X instructions.
 186
 187 2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>
 188
 189         * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
 190         to "eccinj".
 191
 192 2013-04-17  Wei-chen Wang  <cole945@gmail.com>
 193
 194         PR binutils/15369
 195         * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
 196         of CGEN_CPU_ENDIAN.
 197         (hash_insns_list): Likewise.
 198
 199 2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
 200
 201         * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
 202         warning workaround.
 203
 204 2013-04-08  Jan Beulich <jbeulich@suse.com>
 205
 206         * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
 207         * i386-tbl.h: Re-generate.
 208
 209 2013-04-06  David S. Miller  <davem@davemloft.net>
 210
 211         * sparc-dis.c (compare_opcodes): When encountering multiple aliases
 212         of an opcode, prefer the one with F_PREFERRED set.
 213         * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
 214         lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
 215         ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
 216         mark existing mnenomics as aliases.  Add "cc" suffix to edge
 217         instructions generating condition codes, mark existing mnenomics
 218         as aliases.  Add "fp" prefix to VIS compare instructions, mark
 219         existing mnenomics as aliases.
 220
 221 2013-04-03  Nick Clifton  <nickc@redhat.com>
 222
 223         * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
 224         destination address by subtracting the operand from the current
 225         address.
 226         * v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
 227         a positive value in the insn.
 228         (extract_u16_loop): Do not negate the returned value.
 229         (D16_LOOP): Add V850_INVERSE_PCREL flag.
 230
 231         (ceilf.sw): Remove duplicate entry.
 232         (cvtf.hs): New entry.
 233         (cvtf.sh): Likewise.
 234         (fmaf.s): Likewise.
 235         (fmsf.s): Likewise.
 236         (fnmaf.s): Likewise.
 237         (fnmsf.s): Likewise.
 238         (maddf.s): Restrict to E3V5 architectures.
 239         (msubf.s): Likewise.
 240         (nmaddf.s): Likewise.
 241         (nmsubf.s): Likewise.
 242
 243 2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
 244
 245         * i386-dis.c (get_sib): Add the sizeflag argument.  Properly
 246         check address mode.
 247         (print_insn): Pass sizeflag to get_sib.
 248
 249 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 250
 251         PR binutils/15068
 252         * tic6x-dis.c: Add support for displaying 16-bit insns.
 253
 254 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 255
 256         PR gas/15095
 257         * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
 258         individual msb and lsb halves in src1 & src2 fields.  Discard the
 259         src1 (lsb) value and only use src2 (msb), discarding bit 0, to
 260         follow what Ti SDK does in that case as any value in the src1
 261         field yields the same output with SDK disassembler.
 262
 263 2013-03-12  Michael Eager <eager@eagercon.com>
 264
 265         * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
 266
 267 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 268
 269         * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
 270
 271 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 272
 273         * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
 274
 275 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 276
 277         * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
 278
 279 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 280
 281         * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
 282         (thumb32_opcodes): Likewise.
 283         (print_insn_thumb32): Handle 'S' control char.
 284
 285 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
 286
 287         * lm32-desc.c: Regenerate.
 288
 289 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 290
 291         * i386-reg.tbl (riz): Add RegRex64.
 292         * i386-tbl.h: Regenerated.
 293
 294 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 295
 296         * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
 297         (aarch64_feature_crc): New static.
 298         (CRC): New macro.
 299         (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
 300         crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
 301         * aarch64-asm-2.c: Re-generate.
 302         * aarch64-dis-2.c: Ditto.
 303         * aarch64-opc-2.c: Ditto.
 304
 305 2013-02-27  Alan Modra  <amodra@gmail.com>
 306
 307         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
 308         * rl78-decode.c: Regenerate.
 309
 310 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
 311
 312         * rl78-decode.opc: Fix encoding of DIVWU insn.
 313         * rl78-decode.c: Regenerate.
 314
 315 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 316
 317         PR gas/15159
 318         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
 319
 320         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
 321         (cpu_flags): Add CpuSMAP.
 322
 323         * i386-opc.h (CpuSMAP): New.
 324         (i386_cpu_flags): Add cpusmap.
 325
 326         * i386-opc.tbl: Add clac and stac.
 327
 328         * i386-init.h: Regenerated.
 329         * i386-tbl.h: Likewise.
 330
 331 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
 332
 333         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
 334         which also makes the disassembler output be in little
 335         endian like it should be.
 336
 337 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
 338
 339         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
 340         fields to NULL.
 341         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
 342
 343 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
 344
 345         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
 346         section disassembled.
 347
 348 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 349
 350         * arm-dis.c: Update strht pattern.
 351
 352 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
 353
 354         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
 355         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
 356         trunc.w.s macro for EE.
 357
 358 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 359             Andrew Jenner <andrew@codesourcery.com>
 360
 361         Based on patches from Altera Corporation.
 362
 363         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
 364         nios2-opc.c.
 365         * Makefile.in: Regenerated.
 366         * configure.in: Add case for bfd_nios2_arch.
 367         * configure: Regenerated.
 368         * disassemble.c (ARCH_nios2): Define.
 369         (disassembler): Add case for bfd_arch_nios2.
 370         * nios2-dis.c: New file.
 371         * nios2-opc.c: New file.
 372
 373 2013-02-04  Alan Modra  <amodra@gmail.com>
 374
 375         * po/POTFILES.in: Regenerate.
 376         * rl78-decode.c: Regenerate.
 377         * rx-decode.c: Regenerate.
 378
 379 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
 380
 381         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
 382         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
 383         * aarch64-asm.c (convert_xtl_to_shll): New function.
 384         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 385         calling convert_xtl_to_shll.
 386         * aarch64-dis.c (convert_shll_to_xtl): New function.
 387         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 388         calling convert_shll_to_xtl.
 389         * aarch64-gen.c: Update copyright year.
 390         * aarch64-asm-2.c: Re-generate.
 391         * aarch64-dis-2.c: Re-generate.
 392         * aarch64-opc-2.c: Re-generate.
 393
 394 2013-01-24  Nick Clifton  <nickc@redhat.com>
 395
 396         * v850-dis.c: Add support for e3v5 architecture.
 397         * v850-opc.c: Likewise.
 398
 399 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 400
 401         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
 402         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
 403         * aarch64-opc.c (operand_general_constraint_met_p): For
 404         AARCH64_MOD_LSL, move the range check on the shift amount before the
 405         alignment check; change to call set_sft_amount_out_of_range_error
 406         instead of set_imm_out_of_range_error.
 407         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
 408         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
 409         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
 410         SIMD_IMM_SFT.
 411
 412 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
 413
 414         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
 415
 416         * i386-init.h: Regenerated.
 417         * i386-tbl.h: Likewise.
 418
 419 2013-01-15  Nick Clifton  <nickc@redhat.com>
 420
 421         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
 422         values.
 423         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
 424
 425 2013-01-14  Will Newton <will.newton@imgtec.com>
 426
 427         * metag-dis.c (REG_WIDTH): Increase to 64.
 428
 429 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
 430
 431         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
 432         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
 433         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
 434         (SH6): Update.
 435         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
 436         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
 437         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
 438         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
 439
 440 2013-01-10  Will Newton <will.newton@imgtec.com>
 441
 442         * Makefile.am: Add Meta.
 443         * configure.in: Add Meta.
 444         * disassemble.c: Add Meta support.
 445         * metag-dis.c: New file.
 446         * Makefile.in: Regenerate.
 447         * configure: Regenerate.
 448
 449 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 450
 451         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
 452         (match_opcode): Rename to cr16_match_opcode.
 453
 454 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 455
 456         * mips-dis.c: Add names for CP0 registers of r5900.
 457         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
 458         instructions sq and lq.
 459         Add support for MIPS r5900 CPU.
 460         Add support for 128 bit MMI (Multimedia Instructions).
 461         Add support for EE instructions (Emotion Engine).
 462         Disable unsupported floating point instructions (64 bit and
 463         undefined compare operations).
 464         Enable instructions of MIPS ISA IV which are supported by r5900.
 465         Disable 64 bit co processor instructions.
 466         Disable 64 bit multiplication and division instructions.
 467         Disable instructions for co-processor 2 and 3, because these are
 468         not supported (preparation for later VU0 support (Vector Unit)).
 469         Disable cvt.w.s because this behaves like trunc.w.s and the
 470         correct execution can't be ensured on r5900.
 471         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
 472         will confuse less developers and compilers.
 473
 474 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 475
 476         * aarch64-opc.c (aarch64_print_operand): Change to print
 477         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
 478         in comment.
 479         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
 480         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
 481         OP_MOV_IMM_WIDE.
 482
 483 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 484
 485         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
 486         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
 487
 488 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
 489
 490         * i386-gen.c (process_copyright): Update copyright year to 2013.
 491
 492 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 493
 494         * cr16-dis.c (match_opcode,make_instruction): Remove static
 495         declaration.
 496         (dwordU,wordU): Moved typedefs to opcode/cr16.h
 497         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
 498
 499 For older changes see ChangeLog-2012
 500 \f
 501 Copyright (C) 2013 Free Software Foundation, Inc.
 502
 503 Copying and distribution of this file, with or without modification,
 504 are permitted in any medium without royalty provided the copyright
 505 notice and this notice are preserved.
 506
 507 Local Variables:
 508 mode: change-log
 509 left-margin: 8
 510 fill-column: 74
 511 version-control: never
 512 End: