opcodes/ChangeLog

   1 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
   2
   3         * mep-asm.c (macros): Mark static & const.
   4         (lookup_macro): Change return & m to const.
   5         (expand_macro): Change mac to const.
   6         (expand_string): Change pmacro to const.
   7
   8 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
   9
  10         * nds32-asm.c (operand_fields): Rename to ...
  11         (nds32_operand_fields): ... this.
  12         (keyword_gpr): Rename to ...
  13         (nds32_keyword_gpr): ... this.
  14         (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
  15         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
  16         keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
  17         keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
  18         keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
  19         Mark static.
  20         (keywords): Rename to ...
  21         (nds32_keywords): ... this.
  22         * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
  23         keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
  24
  25 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  26
  27         * z80-dis.c (opc_ed): Make const.
  28         (pref_ed): Make p const.
  29
  30 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  31
  32         * microblaze-dis.c (get_field_special): Make op const.
  33         (read_insn_microblaze): Make opr & op const.  Rename opcodes to
  34         microblaze_opcodes.
  35         (print_insn_microblaze): Make op & pop const.
  36         (get_insn_microblaze): Make op const.  Rename opcodes to
  37         microblaze_opcodes.
  38         (microblaze_get_target_address): Likewise.
  39         * microblaze-opc.h (struct op_code_struct): Make const.
  40         Rename opcodes to microblaze_opcodes.
  41
  42 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  43
  44         * aarch64-gen.c (aarch64_opcode_table): Add const.
  45         * aarch64-tbl.h (aarch64_opcode_table): Likewise.
  46
  47 2021-06-22  Andrew Burgess  <andrew.burgess@embecosm.com>
  48
  49         * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
  50         available.
  51
  52 2021-06-22  Alan Modra  <amodra@gmail.com>
  53
  54         * pj-dis.c (print_insn_pj): Don't print trailing tab.  Do
  55         print separator for pcrel insns.
  56
  57 2021-06-19  Alan Modra  <amodra@gmail.com>
  58
  59         * vax-dis.c (print_insn_vax): Avoid pointer overflow.
  60
  61 2021-06-19  Alan Modra  <amodra@gmail.com>
  62
  63         * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
  64         entire buffer.
  65
  66 2021-06-17  Alan Modra  <amodra@gmail.com>
  67
  68         * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
  69         in table.
  70
  71 2021-06-03  Alan Modra  <amodra@gmail.com>
  72
  73         PR 1202
  74         * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
  75         Use unsigned int for inst.
  76
  77 2021-06-02  Shahab Vahedi  <shahab@synopsys.com>
  78
  79         * arc-dis.c (arc_option_arg_t): New enumeration.
  80         (arc_options): New variable.
  81         (disassembler_options_arc): New function.
  82         (print_arc_disassembler_options): Reimplement in terms of
  83         "disassembler_options_arc".
  84
  85 2021-05-29  Alan Modra  <amodra@gmail.com>
  86
  87         * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
  88         Don't special case PPC_OPCODE_RAW.
  89         (lookup_prefix): Likewise.
  90         (lookup_vle, lookup_spe2): Similarly.  Add dialect parameter and..
  91         (print_insn_powerpc): ..update caller.
  92         * ppc-opc.c (EXT): Define.
  93         (powerpc_opcodes): Mark extended mnemonics with EXT.
  94         (prefix_opcodes, vle_opcodes): Likewise.
  95         (XISEL, XISEL_MASK): Add cr field and simplify.
  96         (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
  97         all isel variants to where the base mnemonic belongs.  Sort dstt,
  98         dststt and dssall.
  99
 100 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 101
 102         * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
 103         COP3 opcode instructions.
 104
 105 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 106
 107         * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
 108         "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
 109         "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
 110         "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
 111         "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
 112         "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
 113         "cop2", and "cop3" entries.
 114
 115 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 116
 117         * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
 118         entries and associated comments.
 119
 120 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 121
 122         * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
 123         of "c0".
 124
 125 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 126
 127         * mips-dis.c (mips_cp1_names_mips): New variable.
 128         (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
 129         for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
 130         "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
 131         "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
 132         "r12000", "r14000", "r16000", "mips5", "loongson2e", and
 133         "loongson2f".
 134
 135 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 136
 137         * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
 138         handling code over to...
 139         <OP_REG_CONTROL>: ... this new case.
 140         * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
 141         (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
 142         "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
 143         replacing the `G' operand code with `g'.  Update "cftc1" and
 144         "cftc2" entries replacing the `E' operand code with `y'.
 145         * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
 146         (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
 147         entries replacing the `G' operand code with `g'.
 148
 149 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 150
 151         * mips-dis.c (mips_cp0_names_r3900): New variable.
 152         (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
 153         for "r3900".
 154
 155 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 156
 157         * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
 158         and "mtthc2" to using the `G' rather than `g' operand code for
 159         the coprocessor control register referred.
 160
 161 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 162
 163         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
 164         entries with each other.
 165
 166 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
 167
 168         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
 169
 170 2021-05-25  Alan Modra  <amodra@gmail.com>
 171
 172         * cris-desc.c: Regenerate.
 173         * cris-desc.h: Regenerate.
 174         * cris-opc.h: Regenerate.
 175         * po/POTFILES.in: Regenerate.
 176
 177 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
 178
 179         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
 180         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
 181         (CGEN_CPUS): Add cris.
 182         (CRIS_DEPS): Define.
 183         (stamp-cris): New rule.
 184         * cgen.sh: Handle desc action.
 185         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
 186         * Makefile.in, configure: Regenerate.
 187
 188 2021-05-18  Job Noorman  <mtvec@pm.me>
 189
 190         PR 27814
 191         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
 192         the elf objects.
 193
 194 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
 195
 196         * arm-dis.c (mve_opcodes): Fix disassembly of
 197         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
 198         (is_mve_encoding_conflict): MVE vector loads should not match
 199         when P = W = 0.
 200         (is_mve_unpredictable): It's not unpredictable to use the same
 201         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
 202
 203 2021-05-11  Nick Clifton  <nickc@redhat.com>
 204
 205         PR 27840
 206         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
 207         the end of the code buffer.
 208
 209 2021-05-06  Stafford Horne  <shorne@gmail.com>
 210
 211         PR 21464
 212         * or1k-asm.c: Regenerate.
 213
 214 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
 215
 216         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
 217         info->insn_info_valid.
 218
 219 2021-04-26  Jan Beulich  <jbeulich@suse.com>
 220
 221         * i386-opc.tbl (lea): Add Optimize.
 222         * opcodes/i386-tbl.h: Re-generate.
 223
 224 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 225
 226         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
 227         of l32r fetch and display referenced literal value.
 228
 229 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 230
 231         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
 232         to 4 for literal disassembly.
 233
 234 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 235
 236         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
 237         for TLBI instruction.
 238
 239 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 240
 241         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
 242         DC instruction.
 243
 244 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 245
 246         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
 247         "qualifier".
 248         (convert_mov_to_movewide): Add initializer for "value".
 249
 250 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 251
 252         * aarch64-opc.c: Add RME system registers.
 253
 254 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 255
 256         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
 257         "addi d,CV,z" to "c.mv d,CV".
 258
 259 2021-04-12  Alan Modra  <amodra@gmail.com>
 260
 261         * configure.ac (--enable-checking): Add support.
 262         * config.in: Regenerate.
 263         * configure: Regenerate.
 264
 265 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 266
 267         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 268         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 269
 270 2021-04-09  Alan Modra  <amodra@gmail.com>
 271
 272         * ppc-dis.c (struct dis_private): Add "special".
 273         (POWERPC_DIALECT): Delete.  Replace uses with..
 274         (private_data): ..this.  New inline function.
 275         (disassemble_init_powerpc): Init "special" names.
 276         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 277         field of prefix instructions.
 278         (bsearch_reloc, print_got_plt): New functions.
 279         (print_insn_powerpc): For pcrel instructions, print target address
 280         and symbol if known, and decode plt and got loads too.
 281
 282 2021-04-08  Alan Modra  <amodra@gmail.com>
 283
 284         PR 27684
 285         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 286
 287 2021-04-08  Alan Modra  <amodra@gmail.com>
 288
 289         PR 27676
 290         * ppc-opc.c (DCBT_EO): Move earlier.
 291         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 292         (powerpc_operands): Add THCT and THDS entries.
 293         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 294
 295 2021-04-06  Alan Modra  <amodra@gmail.com>
 296
 297         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 298         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 299         symbol_at_address_func.
 300
 301 2021-04-05  Alan Modra  <amodra@gmail.com>
 302
 303         * configure.ac: Don't check for limits.h, string.h, strings.h or
 304         stdlib.h.
 305         (AC_ISC_POSIX): Don't invoke.
 306         * sysdep.h: Include stdlib.h and string.h unconditionally.
 307         * i386-opc.h: Include limits.h unconditionally.
 308         * wasm32-dis.c: Likewise.
 309         * cgen-opc.c: Don't include alloca-conf.h.
 310         * config.in: Regenerate.
 311         * configure: Regenerate.
 312
 313 2021-04-01  Martin Liska  <mliska@suse.cz>
 314
 315         * arm-dis.c (strneq): Remove strneq and use startswith.
 316         * cr16-dis.c (print_insn_cr16): Likewise.
 317         * score-dis.c (streq): Likewise.
 318         (strneq): Likewise.
 319         * score7-dis.c (strneq): Likewise.
 320
 321 2021-04-01  Alan Modra  <amodra@gmail.com>
 322
 323         PR 27675
 324         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 325
 326 2021-03-31  Alan Modra  <amodra@gmail.com>
 327
 328         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 329         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 330         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 331         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 332         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 333         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 334         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 335         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 336         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 337         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 338         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 339         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 340         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 341         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 342         and TRUE with true throughout.
 343
 344 2021-03-31  Alan Modra  <amodra@gmail.com>
 345
 346         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 347         * aarch64-dis.h: Likewise.
 348         * aarch64-opc.c: Likewise.
 349         * avr-dis.c: Likewise.
 350         * csky-dis.c: Likewise.
 351         * nds32-asm.c: Likewise.
 352         * nds32-dis.c: Likewise.
 353         * nfp-dis.c: Likewise.
 354         * riscv-dis.c: Likewise.
 355         * s12z-dis.c: Likewise.
 356         * wasm32-dis.c: Likewise.
 357
 358 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 359
 360         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 361         (i386_seg_prefixes): New.
 362         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 363         (i386_seg_prefixes): Declare.
 364
 365 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 366
 367         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 368
 369 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 370
 371         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 372         * i386-reg.tbl (st): Move down.
 373         (st(0)): Delete. Extend comment.
 374         * i386-tbl.h: Re-generate.
 375
 376 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 377
 378         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 379         (cmpsd): Move next to cmps.
 380         (movsd): Move next to movs.
 381         (cmpxchg16b): Move to separate section.
 382         (fisttp, fisttpll): Likewise.
 383         (monitor, mwait): Likewise.
 384         * i386-tbl.h: Re-generate.
 385
 386 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 387
 388         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 389         (vpsadbw): Add C.
 390         * i386-tbl.h: Re-generate.
 391
 392 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 393
 394         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 395         pclmul, gfni): New templates. Use them wherever possible. Move
 396         SSE4.1 pextrw into respective section.
 397         * i386-tbl.h: Re-generate.
 398
 399 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 400
 401         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 402         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 403         "length".
 404         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 405         Convert all of their uses to representation in opcode.
 406
 407 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 408
 409         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 410         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 411         value of None. Shrink operands to 3 bits.
 412
 413 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 414
 415         * i386-gen.c (process_i386_opcode_modifier): New parameter
 416         "space".
 417         (output_i386_opcode): New local variable "space". Adjust
 418         process_i386_opcode_modifier() invocation.
 419         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 420         invocation.
 421         * i386-tbl.h: Re-generate.
 422
 423 2021-03-29  Alan Modra  <amodra@gmail.com>
 424
 425         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 426         (fp_qualifier_p, get_data_pattern): Likewise.
 427         (aarch64_get_operand_modifier_from_value): Likewise.
 428         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 429         (operand_variant_qualifier_p): Likewise.
 430         (qualifier_value_in_range_constraint_p): Likewise.
 431         (aarch64_get_qualifier_esize): Likewise.
 432         (aarch64_get_qualifier_nelem): Likewise.
 433         (aarch64_get_qualifier_standard_value): Likewise.
 434         (get_lower_bound, get_upper_bound): Likewise.
 435         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 436         (aarch64_print_operand): Likewise.
 437         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 438         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 439         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 440         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 441         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 442         (print_insn_tic6x): Likewise.
 443
 444 2021-03-29  Alan Modra  <amodra@gmail.com>
 445
 446         * arc-dis.c (extract_operand_value): Correct NULL cast.
 447         * frv-opc.h: Regenerate.
 448
 449 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 450
 451         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 452         MMX form.
 453         * i386-tbl.h: Re-generate.
 454
 455 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 456
 457         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 458         immediate in br.n instruction.
 459
 460 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 461
 462         * i386-dis.c (XMGatherD, VexGatherD): New.
 463         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 464         (print_insn): Check masking for S/G insns.
 465         (OP_E_memory): New local variable check_gather. Extend mandatory
 466         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 467         Extend check for disallowed 16-bit addressing.
 468         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 469         if()s to switch(). Check register conflicts for (VEX-encoded)
 470         gathers. Drop no longer reachable cases.
 471         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 472         vgatherdp*.
 473
 474 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 475
 476         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 477         zeroing-masking without masking.
 478
 479 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 480
 481         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 482         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 483         single-operand forms as deprecated.
 484         * i386-tbl.h: Re-generate.
 485
 486 2021-03-25  Alan Modra  <amodra@gmail.com>
 487
 488         PR 27647
 489         * ppc-opc.c (XLOCB_MASK): Delete.
 490         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 491         XLBH_MASK.
 492         (powerpc_opcodes): Accept a BH field on all extended forms of
 493         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 494
 495 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 496
 497         * i386-gen.c (output_i386_opcode): Drop processing of
 498         opcode_length. Calculate length from base_opcode. Adjust prefix
 499         encoding determination.
 500         (process_i386_opcodes): Drop output of fake opcode_length.
 501         * i386-opc.h (struct insn_template): Drop opcode_length field.
 502         * i386-opc.tbl: Drop opcode length field from all templates.
 503         * i386-tbl.h: Re-generate.
 504
 505 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 506
 507         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 508         parameter "prefix". Drop local variable "regular_encoding".
 509         Record prefix setting / check for consistency.
 510         (output_i386_opcode): Parse opcode_length and base_opcode
 511         earlier. Derive prefix encoding. Drop no longer applicable
 512         consistency checking. Adjust process_i386_opcode_modifier()
 513         invocation.
 514         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 515         invocation.
 516         * i386-tbl.h: Re-generate.
 517
 518 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 519
 520         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 521         check.
 522         * i386-opc.h (Prefix_*): Move #define-s.
 523         * i386-opc.tbl: Move pseudo prefix enumerator values to
 524         extension opcode field. Introduce pseudopfx template.
 525         * i386-tbl.h: Re-generate.
 526
 527 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 528
 529         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 530         comment.
 531         * i386-tbl.h: Re-generate.
 532
 533 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 534
 535         * i386-opc.h (struct insn_template): Move cpu_flags field past
 536         opcode_modifier one.
 537         * i386-tbl.h: Re-generate.
 538
 539 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 540
 541         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 542         * i386-opc.h (OpcodeSpace): New enumerator.
 543         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 544         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 545         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 546         (struct i386_opcode_modifier): New field opcodespace. Shrink
 547         opcodeprefix field.
 548         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 549         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 550         OpcodePrefix uses.
 551         * i386-tbl.h: Re-generate.
 552
 553 2021-03-22  Martin Liska  <mliska@suse.cz>
 554
 555         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 556         * arc-dis.c (parse_option): Likewise.
 557         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 558         * cris-dis.c (print_with_operands): Likewise.
 559         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 560         * i386-dis.c (print_insn): Likewise.
 561         * ia64-gen.c (fetch_insn_class): Likewise.
 562         (parse_resource_users): Likewise.
 563         (in_iclass): Likewise.
 564         (lookup_specifier): Likewise.
 565         (insert_opcode_dependencies): Likewise.
 566         * mips-dis.c (parse_mips_ase_option): Likewise.
 567         (parse_mips_dis_option): Likewise.
 568         * s390-dis.c (disassemble_init_s390): Likewise.
 569         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 570
 571 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 572
 573         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 574
 575 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 576
 577         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 578         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 579
 580 2021-03-12  Alan Modra  <amodra@gmail.com>
 581
 582         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 583
 584 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 585
 586         * i386-dis.c (OP_XMM): Re-order checks.
 587
 588 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 589
 590         * i386-dis.c (putop): Drop need_vex check when also checking
 591         vex.evex.
 592         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 593         checking vex.b.
 594
 595 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 596
 597         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 598         checks. Move case label past broadcast check.
 599
 600 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 601
 602         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 603         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 604         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 605         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 606         EVEX_W_0F38C7_M_0_L_2): Delete.
 607         (REG_EVEX_0F38C7_M_0_L_2): New.
 608         (intel_operand_size): Handle VEX and EVEX the same for
 609         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 610         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 611         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 612         vex_vsib_q_w_d_mode uses.
 613         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 614         0F38A1, and 0F38A3 entries.
 615         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 616         entry.
 617         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 618         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 619         0F38A3 entries.
 620
 621 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 622
 623         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 624         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 625         MOD_VEX_0FXOP_09_12): Rename to ...
 626         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 627         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 628         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 629         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 630         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 631         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 632         (reg_table): Adjust comments.
 633         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 634         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 635         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 636         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 637         (vex_len_table): Adjust opcode 0A_12 entry.
 638         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 639         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 640         (rm_table): Move hreset entry.
 641
 642 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 643
 644         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 645         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 646         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 647         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 648         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 649         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 650         (get_valid_dis386): Also handle 512-bit vector length when
 651         vectoring into vex_len_table[].
 652         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 653         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 654         entries.
 655         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 656         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 657         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 658         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 659         entries.
 660
 661 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 662
 663         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 664         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 665         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 666         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 667         entries.
 668         * i386-dis-evex-len.h (evex_len_table): Likewise.
 669         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 670
 671 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 672
 673         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 674         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 675         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 676         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 677         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 678         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 679         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 680         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 681         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 682         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 683         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 684         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 685         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 686         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 687         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 688         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 689         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 690         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 691         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 692         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 693         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 694         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 695         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 696         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 697         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 698         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 699         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 700         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 701         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 702         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 703         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 704         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 705         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 706         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 707         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 708         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 709         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 710         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 711         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 712         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 713         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 714         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 715         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 716         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 717         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 718         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 719         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 720         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 721         EVEX_W_0F3A43_L_n): New.
 722         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 723         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 724         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 725         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 726         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 727         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 728         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 729         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 730         0F385B, 0F38C6, and 0F38C7 entries.
 731         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 732         0F38C6 and 0F38C7.
 733         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 734         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 735         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 736         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 737
 738 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 739
 740         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 741         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 742         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 743         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 744         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 745         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 746         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 747         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 748         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 749         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 750         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 751         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 752         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 753         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 754         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 755         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 756         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 757         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 758         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 759         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 760         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 761         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 762         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 763         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 764         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 765         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 766         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 767         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 768         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 769         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 770         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 771         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 772         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 773         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 774         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 775         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 776         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 777         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 778         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 779         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 780         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 781         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 782         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 783         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 784         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 785         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 786         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 787         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 788         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 789         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 790         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 791         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 792         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 793         VEX_W_0F99_P_2_LEN_0): Delete.
 794         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 795         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 796         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 797         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 798         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 799         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 800         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 801         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 802         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 803         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 804         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 805         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 806         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 807         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 808         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 809         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 810         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 811         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 812         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 813         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 814         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 815         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 816         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 817         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 818         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 819         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 820         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 821         (prefix_table): No longer link to vex_len_table[] for opcodes
 822         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 823         0F92, 0F93, 0F98, and 0F99.
 824         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 825         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 826         0F98, and 0F99.
 827         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 828         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 829         0F98, and 0F99.
 830         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 831         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 832         0F98, and 0F99.
 833         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 834         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 835         0F98, and 0F99.
 836
 837 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 838
 839         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 840         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 841         REG_VEX_0F73_M_0 respectively.
 842         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 843         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 844         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 845         MOD_VEX_0F73_REG_7): Delete.
 846         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 847         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 848         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 849         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 850         PREFIX_VEX_0F3AF0_L_0 respectively.
 851         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 852         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 853         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 854         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 855         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 856         VEX_LEN_0F38F7): New.
 857         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 858         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 859         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 860         0F38F3.
 861         (prefix_table): No longer link to vex_len_table[] for opcodes
 862         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 863         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 864         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 865         0F38F6, 0F38F7, and 0F3AF0.
 866         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 867         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 868         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 869         0F73.
 870
 871 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 872
 873         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 874         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 875         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 876         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 877         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 878         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 879         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 880         73.
 881         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 882         0F72, and 0F73.
 883         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 884         0F73.
 885
 886 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 887
 888         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 889         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 890         (reg_table): Don't link to mod_table[] where not needed. Add
 891         PREFIX_IGNORED to nop entries.
 892         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 893         (mod_table): Add nop entries next to prefetch ones. Drop
 894         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 895         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 896         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 897         PREFIX_OPCODE from endbr* entries.
 898         (get_valid_dis386): Also consider entry's name when zapping
 899         vindex.
 900         (print_insn): Handle PREFIX_IGNORED.
 901
 902 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 903
 904         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 905         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 906         element.
 907         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 908         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 909         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 910         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 911         (struct i386_opcode_modifier): Delete notrackprefixok,
 912         islockable, hleprefixok, and repprefixok fields. Add prefixok
 913         field.
 914         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 915         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 916         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 917         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 918         Replace HLEPrefixOk.
 919         * opcodes/i386-tbl.h: Re-generate.
 920
 921 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 922
 923         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 924         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 925         64-bit form.
 926         * opcodes/i386-tbl.h: Re-generate.
 927
 928 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 929
 930         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 931         for {} instead of {0}. Don't look for '0'.
 932         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 933         size specifiers.
 934
 935 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 936
 937         PR 27158
 938         * riscv-dis.c (print_insn_args): Updated encoding macros.
 939         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 940         (match_c_addi16sp): Updated encoding macros.
 941         (match_c_lui): Likewise.
 942         (match_c_lui_with_hint): Likewise.
 943         (match_c_addi4spn): Likewise.
 944         (match_c_slli): Likewise.
 945         (match_slli_as_c_slli): Likewise.
 946         (match_c_slli64): Likewise.
 947         (match_srxi_as_c_srxi): Likewise.
 948         (riscv_insn_types): Added .insn css/cl/cs.
 949
 950 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 951
 952         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 953         (default_priv_spec): Updated type to riscv_spec_class.
 954         (parse_riscv_dis_option): Updated.
 955         * riscv-opc.c: Moved stuff and make the file tidy.
 956
 957 2021-02-17  Alan Modra  <amodra@gmail.com>
 958
 959         * wasm32-dis.c: Include limits.h.
 960         (CHAR_BIT): Provide backup define.
 961         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 962         Correct signed overflow checking.
 963
 964 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 965
 966         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 967         * i386-tbl.h: Re-generate.
 968
 969 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 970
 971         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 972         Oword.
 973         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 974
 975 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 976
 977         * s390-mkopc.c (main): Accept arch14 as cpu string.
 978         * s390-opc.txt: Add new arch14 instructions.
 979
 980 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 981
 982         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 983         favour of LIBINTL.
 984         * configure: Regenerated.
 985
 986 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 987
 988         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 989         * tic54x-opc.c (regs): Rename to ...
 990         (tic54x_regs): ... this.
 991         (mmregs): Rename to ...
 992         (tic54x_mmregs): ... this.
 993         (condition_codes): Rename to ...
 994         (tic54x_condition_codes): ... this.
 995         (cc2_codes): Rename to ...
 996         (tic54x_cc2_codes): ... this.
 997         (cc3_codes): Rename to ...
 998         (tic54x_cc3_codes): ... this.
 999         (status_bits): Rename to ...
1000         (tic54x_status_bits): ... this.
1001         (misc_symbols): Rename to ...
1002         (tic54x_misc_symbols): ... this.
1003
1004 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
1005
1006         * riscv-opc.c (MASK_RVB_IMM): Removed.
1007         (riscv_opcodes): Removed zb* instructions.
1008         (riscv_ext_version_table): Removed versions for zb*.
1009
1010 2021-01-26  Alan Modra  <amodra@gmail.com>
1011
1012         * i386-gen.c (parse_template): Ensure entire template_instance
1013         is initialised.
1014
1015 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1016
1017         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1018         (riscv_fpr_names_abi): Likewise.
1019         (riscv_opcodes): Likewise.
1020         (riscv_insn_types): Likewise.
1021
1022 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1023
1024         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1025
1026 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1027
1028         * riscv-dis.c: Comments tidy and improvement.
1029         * riscv-opc.c: Likewise.
1030
1031 2021-01-13  Alan Modra  <amodra@gmail.com>
1032
1033         * Makefile.in: Regenerate.
1034
1035 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
1036
1037         PR binutils/26792
1038         * configure.ac: Use GNU_MAKE_JOBSERVER.
1039         * aclocal.m4: Regenerated.
1040         * configure: Likewise.
1041
1042 2021-01-12  Nick Clifton  <nickc@redhat.com>
1043
1044         * po/sr.po: Updated Serbian translation.
1045
1046 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
1047
1048         PR ld/27173
1049         * configure: Regenerated.
1050
1051 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1052
1053         * aarch64-asm-2.c: Regenerate.
1054         * aarch64-dis-2.c: Likewise.
1055         * aarch64-opc-2.c: Likewise.
1056         * aarch64-opc.c (aarch64_print_operand):
1057         Delete handling of AARCH64_OPND_CSRE_CSR.
1058         * aarch64-tbl.h (aarch64_feature_csre): Delete.
1059         (CSRE): Likewise.
1060         (_CSRE_INSN): Likewise.
1061         (aarch64_opcode_table): Delete csr.
1062
1063 2021-01-11  Nick Clifton  <nickc@redhat.com>
1064
1065         * po/de.po: Updated German translation.
1066         * po/fr.po: Updated French translation.
1067         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1068         * po/sv.po: Updated Swedish translation.
1069         * po/uk.po: Updated Ukranian translation.
1070
1071 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
1072
1073         * configure: Regenerated.
1074
1075 2021-01-09  Nick Clifton  <nickc@redhat.com>
1076
1077         * configure: Regenerate.
1078         * po/opcodes.pot: Regenerate.
1079
1080 2021-01-09  Nick Clifton  <nickc@redhat.com>
1081
1082         * 2.36 release branch crated.
1083
1084 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
1085
1086         * ppc-opc.c (insert_dw, (extract_dw): New functions.
1087         (DW, (XRC_MASK): Define.
1088         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1089
1090 2021-01-09  Alan Modra  <amodra@gmail.com>
1091
1092         * configure: Regenerate.
1093
1094 2021-01-08  Nick Clifton  <nickc@redhat.com>
1095
1096         * po/sv.po: Updated Swedish translation.
1097
1098 2021-01-08  Nick Clifton  <nickc@redhat.com>
1099
1100         PR 27129
1101         * aarch64-dis.c (determine_disassembling_preference): Move call to
1102         aarch64_match_operands_constraint outside of the assertion.
1103         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1104         Replace with a return of FALSE.
1105
1106         PR 27139
1107         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1108         core system register.
1109
1110 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
1111
1112         * configure: Regenerate.
1113
1114 2021-01-07  Nick Clifton  <nickc@redhat.com>
1115
1116         * po/fr.po: Updated French translation.
1117
1118 2021-01-07  Fredrik Noring  <noring@nocrew.org>
1119
1120         * m68k-opc.c (chkl): Change minimum architecture requirement to
1121         m68020.
1122
1123 2021-01-07  Philipp Tomsich  <prt@gnu.org>
1124
1125         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1126
1127 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
1128             Jim Wilson  <jimw@sifive.com>
1129             Andrew Waterman  <andrew@sifive.com>
1130             Maxim Blinov  <maxim.blinov@embecosm.com>
1131             Kito Cheng  <kito.cheng@sifive.com>
1132             Nelson Chu  <nelson.chu@sifive.com>
1133
1134         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1135         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1136
1137 2021-01-01  Alan Modra  <amodra@gmail.com>
1138
1139         Update year range in copyright notice of all files.
1140
1141 For older changes see ChangeLog-2020
1142 \f
1143 Copyright (C) 2021 Free Software Foundation, Inc.
1144
1145 Copying and distribution of this file, with or without modification,
1146 are permitted in any medium without royalty provided the copyright
1147 notice and this notice are preserved.
1148
1149 Local Variables:
1150 mode: change-log
1151 left-margin: 8
1152 fill-column: 74
1153 version-control: never
1154 End: