opcodes/ChangeLog

   1 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
   2
   3         * aarch64-opc.c (F_DEPRECATED): New macro.
   4         (aarch64_sys_regs): Update; flag "spsr_svc" and "spsr_hyp" with
   5         F_DEPRECATED.
   6         (aarch64_print_operand): Call aarch64_sys_reg_deprecated_p on
   7         AARCH64_OPND_SYSREG.
   8
   9 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
  10
  11         * aarch64-dis.c (convert_ubfm_to_lsl): Check for cond != '111x'.
  12         (convert_from_csel): Likewise.
  13         * aarch64-opc.c (operand_general_constraint_met_p): Handle
  14         AARCH64_OPND_CLASS_COND and AARCH64_OPND_COND1.
  15         (aarch64_print_operand): Handle AARCH64_OPND_COND1.
  16         * aarch64-tbl.h (aarch64_opcode_table): Use COND1 instead of
  17         COND for cinc, cset, cinv, csetm and cneg.
  18         (AARCH64_OPERANDS): Add entry for AARCH64_OPND_COND1.
  19         * aarch64-asm-2.c: Re-generated.
  20         * aarch64-dis-2.c: Ditto.
  21         * aarch64-opc-2.c: Ditto.
  22
  23 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
  24
  25         * aarch64-opc.c (set_syntax_error): New function.
  26         (operand_general_constraint_met_p): Replace set_other_error
  27         with set_syntax_error.
  28
  29 2013-10-30  Andreas Arnez  <arnez@linux.vnet.ibm.com>
  30
  31         * s390-dis.c (init_disasm): Default to full 'zarch' opcode
  32         availability even for 31-bit programs.
  33
  34 2013-10-15  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
  35
  36         * arm-dis.c (neon_opcodes): Adjust print string for vshll.
  37
  38 2013-10-14  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
  39
  40         * micromips-opc.c (decode_micromips_operand): Add +T, +U, +V, +W,
  41         +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +x,
  42         +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
  43         (MSA): New define.
  44         (MSA64): New define.
  45         (micromips_opcodes): Add MSA instructions.
  46         * mips-dis.c (msa_control_names): New array.
  47         (mips_abi_choice): Add ASE_MSA to mips32r2.
  48         Remove ASE_MDMX from mips64r2.
  49         Add ASE_MSA and ASE_MSA64 to mips64r2.
  50         (parse_mips_dis_option): Handle -Mmsa.
  51         (print_reg): Handle cases for OP_REG_MSA and OP_REG_MSA_CTRL.
  52         (print_insn_arg): Handle cases for OP_IMM_INDEX and OP_REG_INDEX.
  53         (print_mips_disassembler_options): Print -Mmsa.
  54         * mips-opc.c (decode_mips_operand): Add +T, +U, +V, +W, +d, +e, +h, +k,
  55         +l, +n, +o, +u, +v, +w, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
  56         (MSA): New define.
  57         (MSA64): New define.
  58         (mips_builtin_op): Add MSA instructions.
  59
  60 2013-10-13  Sandra Loosemore  <sandra@codesourcery.com>
  61
  62         * nios2-opc.c (nios2_builtin_reg): Use "sstatus" rather than "ba"
  63         as the primary name of r30.
  64
  65 2013-10-12  Jan Beulich <jbeulich@suse.com>
  66
  67         * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
  68         default case.
  69         (OP_E_register): Move v_bnd_mode alongside m_mode.
  70         * i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants.
  71         Drop Reg16 and Disp16. Add NoRex64.
  72         (bndmk, bndmov, bndldx, bndstx): Drop Disp16.
  73         * i386-tbl.h: Re-generate.
  74
  75 2013-10-10  Sean Keys <skeys@ipdatasys.com>
  76
  77         * xgate-opc.c (xgate_opcode): Remove short_hand field from opcode
  78         table.
  79         * xgate-dis.c (print_insn): Refactor to work with table change.
  80
  81 2013-10-10  Roland McGrath  <mcgrathr@google.com>
  82
  83         * i386-dis.c (oappend_maybe_intel): New function.
  84         (OP_ST, OP_STi, append_seg, OP_I, OP_I64, OP_sI, OP_ESreg): Use it.
  85         (OP_C, OP_T, CMP_Fixup, OP_EX_VexImmW): Likewise.
  86         (VCMP_Fixup, VPCMP_Fixup, PCLMUL_Fixup): Likewise.
  87
  88         * cr16-opc.c (REG): Cast NAME to 'reg' enum type to suppress
  89         possible compiler warnings when the union's initializer is
  90         actually meant for the 'preg' enum typed member.
  91         * crx-opc.c (REG): Likewise.
  92
  93         * v850-dis.c (v850_cacheop_codes, v850_prefop_codes):
  94         Remove duplicate const qualifier.
  95
  96 2013-10-08  Jan Beulich <jbeulich@suse.com>
  97
  98         * i386-opc.tbl (invlpg): Use Anysize instead of Unspecified.
  99         (clflush): Use Anysize instead of Byte|Unspecified.
 100         (prefetch*): Likewise.
 101         * i386-tbl.h: Re-generate.
 102
 103 2013-10-07  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 104
 105         * micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.
 106
 107 2013-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 108
 109         * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
 110         * i386-init.h: Regenerated.
 111
 112 2013-09-30  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 113
 114         * i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS.
 115         * i386-init.h: Regenerated.
 116
 117 2013-09-20  Alan Modra  <amodra@gmail.com>
 118
 119         * configure: Regenerate.
 120
 121 2013-09-17  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 122
 123         * s390-opc.txt (clih): Make the immediate unsigned.
 124
 125 2013-09-04  Roland McGrath  <mcgrathr@google.com>
 126
 127         PR gas/15914
 128         * arm-dis.c (arm_opcodes): Add udf.
 129         (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
 130         (thumb32_opcodes): Add udf.w.
 131         (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
 132
 133 2013-09-02  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 134
 135         * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
 136         For the load fp integer instructions only the suppression flag was
 137         new with z196 version.
 138
 139 2013-08-28  Nick Clifton  <nickc@redhat.com>
 140
 141         * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
 142         immediate is not suitable for the 32-bit ABI.
 143
 144 2013-08-23  Maciej W. Rozycki  <macro@codesourcery.com>
 145
 146         * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
 147         replacing NODS.
 148
 149 2013-08-23  Yuri Chornoivan  <yurchor@ukr.net>
 150
 151         PR binutils/15834
 152         * aarch64-asm.c: Fix typos.
 153         * aarch64-dis.c: Likewise.
 154         * msp430-dis.c: Likewise.
 155
 156 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
 157
 158         * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
 159         macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
 160         Use +H rather than +C for the real "dext".
 161         * mips-opc.c (mips_builtin_opcodes): Likewise.
 162
 163 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
 164
 165         * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
 166         * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
 167         and OPTIONAL_MAPPED_REG.
 168         * mips-opc.c (decode_mips_operand): Likewise.
 169         * mips16-opc.c (decode_mips16_operand): Likewise.
 170         * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
 171
 172 2013-08-19  H.J. Lu  <hongjiu.lu@intel.com>
 173
 174         * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
 175         (PREFIX_EVEX_0F3A3F): Likewise.
 176         * i386-dis-evex.h (evex_table): Updated.
 177
 178 2013-08-06  Jürgen Urban  <JuergenUrban@gmx.de>
 179
 180         * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
 181         VCLIPW.
 182
 183 2013-08-05  Eric Botcazou  <ebotcazou@adacore.com>
 184             Konrad Eisele  <konrad@gaisler.com>
 185
 186         * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
 187         bfd_mach_sparc.
 188         * sparc-opc.c (MASK_LEON): Define.
 189         (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
 190         (letandleon): New macro.
 191         (v9andleon): Likewise.
 192         (sparc_opc): Add leon.
 193         (umac): Enable for letandleon.
 194         (smac): Likewise.
 195         (casa): Enable for v9andleon.
 196         (cas): Likewise.
 197         (casl): Likewise.
 198
 199 2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
 200             Richard Sandiford  <rdsandiford@googlemail.com>
 201
 202         * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
 203         OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
 204         (print_vu0_channel): New function.
 205         (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
 206         (print_insn_args): Handle '#'.
 207         (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
 208         * mips-opc.c (mips_vu0_channel_mask): New constant.
 209         (decode_mips_operand): Handle new VU0 operand types.
 210         (VU0, VU0CH): New macros.
 211         (mips_builtin_opcodes): Add VU0 opcodes.  Use "+7" rather than "E"
 212         for LQC2 and SQC2.  Use "+9" rather than "G" for EE CFC2 and CTC2.
 213         Use "+6" rather than "G" for QMFC2 and QMTC2.
 214
 215 2013-08-03  Richard Sandiford  <rdsandiford@googlemail.com>
 216
 217         * mips-formats.h (PCREL): Reorder parameters and update the definition
 218         to match new mips_pcrel_operand layout.
 219         (JUMP, JALX, BRANCH): Update accordingly.
 220         * mips16-opc.c (decode_mips16_operand): Likewise.
 221
 222 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 223
 224         * micromips-opc.c (WR_s): Delete.
 225
 226 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 227
 228         * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
 229         New macros.
 230         (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
 231         (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
 232         (mips_builtin_opcodes): Use the new position-based read-write flags
 233         instead of field-based ones.  Use UDI for "udi..." instructions.
 234         * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
 235         New macros.
 236         (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
 237         (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
 238         (WR_SP, RD_16): New macros.
 239         (RD_SP): Redefine as an INSN2_* flag.
 240         (MOD_SP): Redefine in terms of RD_SP and WR_SP.
 241         (mips16_opcodes): Use the new position-based read-write flags
 242         instead of field-based ones.  Use RD_16 for "nop".  Move RD_SP to
 243         pinfo2 field.
 244         * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
 245         New macros.
 246         (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
 247         (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
 248         (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
 249         (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
 250         (micromips_opcodes): Use the new position-based read-write flags
 251         instead of field-based ones.
 252         * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
 253         (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
 254         of field-based flags.
 255
 256 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 257
 258         * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
 259         (WR_SP): Replace with...
 260         (MOD_SP): ...this.
 261         (mips16_opcodes): Update accordingly.
 262         * mips-dis.c (print_insn_mips16): Likewise.
 263
 264 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 265
 266         * mips16-opc.c (mips16_opcodes): Reformat.
 267
 268 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 269
 270         * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
 271         for operands that are hard-coded to $0.
 272         * micromips-opc.c (micromips_opcodes): Likewise.
 273
 274 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 275
 276         * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
 277         for the single-operand forms of JALR and JALR.HB.
 278         * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
 279         and JALRS.HB.
 280
 281 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 282
 283         * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
 284         instructions.  Fix them to use WR_MACC instead of WR_CC and
 285         add missing RD_MACCs.
 286
 287 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 288
 289         * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
 290
 291 2013-07-29  Peter Bergner <bergner@vnet.ibm.com>
 292
 293         * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
 294
 295 2013-07-26  Sergey Guriev  <sergey.s.guriev@intel.com>
 296             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 297             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 298             Sergey Lega  <sergey.s.lega@intel.com>
 299             Anna Tikhonova  <anna.tikhonova@intel.com>
 300             Ilya Tocar  <ilya.tocar@intel.com>
 301             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 302             Ilya Verbin  <ilya.verbin@intel.com>
 303             Kirill Yukhin  <kirill.yukhin@intel.com>
 304             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 305
 306         * i386-dis-evex.h: New.
 307         * i386-dis.c (OP_Rounding): New.
 308         (VPCMP_Fixup): New.
 309         (OP_Mask): New.
 310         (Rdq): New.
 311         (XMxmmq): New.
 312         (EXdScalarS): New.
 313         (EXymm): New.
 314         (EXEvexHalfBcstXmmq): New.
 315         (EXxmm_mdq): New.
 316         (EXEvexXGscat): New.
 317         (EXEvexXNoBcst): New.
 318         (VPCMP): New.
 319         (EXxEVexR): New.
 320         (EXxEVexS): New.
 321         (XMask): New.
 322         (MaskG): New.
 323         (MaskE): New.
 324         (MaskR): New.
 325         (MaskVex): New.
 326         (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
 327         evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
 328         evex_rounding_mode, evex_sae_mode, mask_mode.
 329         (USE_EVEX_TABLE): New.
 330         (EVEX_TABLE): New.
 331         (EVEX enum): New.
 332         (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
 333         REG_EVEX_0F38C7.
 334         (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
 335         MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
 336         MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
 337         MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 338         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,  MOD_EVEX_0F38C7_REG_5,
 339         MOD_EVEX_0F38C7_REG_6.
 340         (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 341         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
 342         PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 343         PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
 344         PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
 345         PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
 346         PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
 347         PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
 348         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
 349         PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
 350         PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
 351         PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
 352         PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
 353         PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
 354         PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
 355         PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
 356         PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
 357         PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
 358         PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
 359         PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
 360         PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
 361         PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
 362         PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
 363         PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
 364         PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
 365         PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
 366         PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
 367         PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
 368         PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
 369         PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
 370         PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
 371         PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
 372         PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
 373         PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
 374         PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
 375         PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
 376         PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
 377         PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
 378         PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
 379         PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
 380         PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
 381         PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
 382         PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
 383         PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
 384         PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
 385         PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
 386         PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
 387         PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
 388         PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
 389         PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
 390         PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
 391         PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
 392         PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
 393         PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
 394         PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
 395         PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
 396         PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
 397         PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
 398         PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
 399         PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
 400         PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
 401         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
 402         PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
 403         PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
 404         PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
 405         PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
 406         PREFIX_EVEX_0F3A00,  PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
 407         PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
 408         PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
 409         PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
 410         PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
 411         PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
 412         PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
 413         PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
 414         PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
 415         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
 416         PREFIX_EVEX_0F3A55.
 417         (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
 418         VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
 419         VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
 420         VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
 421         VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
 422         VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
 423         VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
 424         VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
 425         VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
 426         VEX_W_0F3A32_P_2_LEN_0.
 427         (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
 428         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
 429         EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
 430         EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
 431         EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
 432         EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 433         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
 434         EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
 435         EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 436         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
 437         EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 438         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
 439         EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
 440         EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
 441         EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
 442         EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
 443         EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
 444         EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
 445         EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
 446         EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
 447         EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
 448         EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
 449         EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
 450         EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
 451         EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
 452         EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
 453         EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
 454         EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
 455         EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
 456         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
 457         EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
 458         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
 459         EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
 460         EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
 461         EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
 462         EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
 463         EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
 464         EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
 465         EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
 466         EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
 467         EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
 468         EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
 469         EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
 470         EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
 471         EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
 472         EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
 473         EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
 474         EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
 475         EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
 476         EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
 477         EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
 478         EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
 479         EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
 480         EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
 481         (struct vex): Add fields evex, r, v, mask_register_specifier,
 482         zeroing, ll, b.
 483         (intel_names_xmm): Add upper 16 registers.
 484         (att_names_xmm): Ditto.
 485         (intel_names_ymm): Ditto.
 486         (att_names_ymm): Ditto.
 487         (names_zmm): New.
 488         (intel_names_zmm): Ditto.
 489         (att_names_zmm): Ditto.
 490         (names_mask): Ditto.
 491         (intel_names_mask): Ditto.
 492         (att_names_mask): Ditto.
 493         (names_rounding): Ditto.
 494         (names_broadcast): Ditto.
 495         (x86_64_table): Add escape to evex-table.
 496         (reg_table): Include reg_table evex-entries from
 497         i386-dis-evex.h.  Fix prefetchwt1 instruction.
 498         (prefix_table): Add entries for new instructions.
 499         (vex_table): Ditto.
 500         (vex_len_table): Ditto.
 501         (vex_w_table): Ditto.
 502         (mod_table): Ditto.
 503         (get_valid_dis386): Properly handle new instructions.
 504         (print_insn): Handle zmm and mask registers, print mask operand.
 505         (intel_operand_size): Support EVEX, new modes and sizes.
 506         (OP_E_register): Handle new modes.
 507         (OP_E_memory): Ditto.
 508         (OP_G): Ditto.
 509         (OP_XMM): Ditto.
 510         (OP_EX): Ditto.
 511         (OP_VEX): Ditto.
 512         * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
 513         CPU_ANY_AVX_FLAGS.  Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
 514         CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 515         (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
 516         CpuAVX512PF and CpuVREX.
 517         (operand_type_init): Add OPERAND_TYPE_REGZMM,
 518         OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
 519         (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
 520         StaticRounding, SAE, Disp8MemShift, NoDefMask.
 521         (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
 522         * i386-init.h: Regenerate.
 523         * i386-opc.h (CpuAVX512F): New.
 524         (CpuAVX512CD): New.
 525         (CpuAVX512ER): New.
 526         (CpuAVX512PF): New.
 527         (CpuVREX): New.
 528         (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
 529         cpuavx512pf and cpuvrex fields.
 530         (VecSIB): Add VecSIB512.
 531         (EVex): New.
 532         (Masking): New.
 533         (VecESize): New.
 534         (Broadcast): New.
 535         (StaticRounding): New.
 536         (SAE): New.
 537         (Disp8MemShift): New.
 538         (NoDefMask): New.
 539         (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
 540         staticrounding, sae, disp8memshift and nodefmask.
 541         (RegZMM): New.
 542         (Zmmword): Ditto.
 543         (Vec_Disp8): Ditto.
 544         (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
 545         fields.
 546         (RegVRex): New.
 547         * i386-opc.tbl: Add AVX512 instructions.
 548         * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
 549         registers, mask registers.
 550         * i386-tbl.h: Regenerate.
 551
 552 2013-07-25  Aaro Koskinen  <aaro.koskinen@iki.fi>
 553
 554         PR gas/15220
 555         * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
 556         Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
 557
 558 2013-07-25  Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 559
 560         * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
 561         PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
 562         PREFIX_0F3ACC.
 563         (prefix_table): Updated.
 564         (three_byte_table): Likewise.
 565         * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
 566         (cpu_flags): Add CpuSHA.
 567         (i386_cpu_flags): Add cpusha.
 568         * i386-init.h: Regenerate.
 569         * i386-opc.h (CpuSHA): New.
 570         (CpuUnused): Restored.
 571         (i386_cpu_flags): Add cpusha.
 572         * i386-opc.tbl: Add SHA instructions.
 573         * i386-tbl.h: Regenerate.
 574
 575 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
 576             Kirill Yukhin  <kirill.yukhin@intel.com>
 577             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 578
 579         * i386-dis.c (BND_Fixup): New.
 580         (Ebnd): New.
 581         (Ev_bnd): New.
 582         (Gbnd): New.
 583         (BND): New.
 584         (v_bnd_mode): New.
 585         (bnd_mode): New.
 586         (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
 587         MOD_0F1B_PREFIX_1.
 588         (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
 589         (dis tables): Replace XX with BND for near branch and call
 590         instructions.
 591         (prefix_table): Add new entries.
 592         (mod_table): Likewise.
 593         (names_bnd): New.
 594         (intel_names_bnd): New.
 595         (att_names_bnd): New.
 596         (BND_PREFIX): New.
 597         (prefix_name): Handle BND_PREFIX.
 598         (print_insn): Initialize names_bnd.
 599         (intel_operand_size): Handle new modes.
 600         (OP_E_register): Likewise.
 601         (OP_E_memory): Likewise.
 602         (OP_G): Likewise.
 603         * i386-gen.c (cpu_flag_init): Add CpuMPX.
 604         (cpu_flags): Add CpuMPX.
 605         (operand_type_init): Add RegBND.
 606         (opcode_modifiers): Add BNDPrefixOk.
 607         (operand_types): Add RegBND.
 608         * i386-init.h: Regenerate.
 609         * i386-opc.h (CpuMPX): New.
 610         (CpuUnused): Comment out.
 611         (i386_cpu_flags): Add cpumpx.
 612         (BNDPrefixOk): New.
 613         (i386_opcode_modifier): Add bndprefixok.
 614         (RegBND): New.
 615         (i386_operand_type): Add regbnd.
 616         * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
 617         Add MPX instructions and bnd prefix.
 618         * i386-reg.tbl: Add bnd0-bnd3 registers.
 619         * i386-tbl.h: Regenerate.
 620
 621 2013-07-17  Richard Sandiford  <rdsandiford@googlemail.com>
 622
 623         * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
 624         ATTRIBUTE_UNUSED.
 625
 626 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 627
 628         * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
 629         special rules.
 630         * Makefile.in: Regenerate.
 631         * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
 632         all fields.  Reformat.
 633
 634 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 635
 636         * mips16-opc.c: Include mips-formats.h.
 637         (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
 638         static arrays.
 639         (decode_mips16_operand): New function.
 640         * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
 641         (print_insn_arg): Handle OP_ENTRY_EXIT list.
 642         Abort for OP_SAVE_RESTORE_LIST.
 643         (print_mips16_insn_arg): Change interface.  Use mips_operand
 644         structures.  Delete GET_OP_S.  Move GET_OP definition to...
 645         (print_insn_mips16): ...here.  Call init_print_arg_state.
 646         Update the call to print_mips16_insn_arg.
 647
 648 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 649
 650         * mips-formats.h: New file.
 651         * mips-opc.c: Include mips-formats.h.
 652         (reg_0_map): New static array.
 653         (decode_mips_operand): New function.
 654         * micromips-opc.c: Remove <stdio.h> include.  Include mips-formats.h.
 655         (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
 656         (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
 657         (int_c_map): New static arrays.
 658         (decode_micromips_operand): New function.
 659         * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
 660         (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
 661         (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
 662         (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
 663         (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
 664         (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
 665         (micromips_imm_b_map, micromips_imm_c_map): Delete.
 666         (print_reg): New function.
 667         (mips_print_arg_state): New structure.
 668         (init_print_arg_state, print_insn_arg): New functions.
 669         (print_insn_args): Change interface and use mips_operand structures.
 670         Delete GET_OP_S.  Move GET_OP definition to...
 671         (print_insn_mips): ...here.  Update the call to print_insn_args.
 672         (print_insn_micromips): Use print_insn_args.
 673
 674 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 675
 676         * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
 677         in macros.
 678
 679 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 680
 681         * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
 682         ADDA.S, MULA.S and SUBA.S.
 683
 684 2013-07-08  H.J. Lu  <hongjiu.lu@intel.com>
 685
 686         PR gas/13572
 687         * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
 688         * i386-tbl.h: Regenerated.
 689
 690 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 691
 692         * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros.  Move LD
 693         and SD A(B) macros up.
 694         * micromips-opc.c (micromips_opcodes): Likewise.
 695
 696 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 697
 698         * mips16-opc.c: Add entries for argumentless "entry" and "exit"
 699         instructions.
 700
 701 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 702
 703         * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
 704         MDMX-like instructions.
 705         * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
 706         printing "Q" operands for INSN_5400 instructions.
 707
 708 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 709
 710         * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
 711         "+S" for "cins".
 712         * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
 713         Combine cases.
 714
 715 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 716
 717         * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
 718         "jalx".
 719         * mips16-opc.c (mips16_opcodes): Likewise.
 720         * micromips-opc.c (micromips_opcodes): Likewise.
 721         * mips-dis.c (print_insn_args, print_mips16_insn_arg)
 722         (print_insn_mips16): Handle "+i".
 723         (print_insn_micromips): Likewise.  Conditionally preserve the
 724         ISA bit for "a" but not for "+i".
 725
 726 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 727
 728         * micromips-opc.c (WR_mhi): Rename to..
 729         (WR_mh): ...this.
 730         (micromips_opcodes): Update "movep" entry accordingly.  Replace
 731         "mh,mi" with "mh".
 732         * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
 733         (micromips_to_32_reg_h_map1): ...this.
 734         (micromips_to_32_reg_i_map): Rename to...
 735         (micromips_to_32_reg_h_map2): ...this.
 736         (print_micromips_insn): Remove "mi" case.  Print both registers
 737         in the pair for "mh".
 738
 739 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 740
 741         * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
 742         * micromips-opc.c (micromips_opcodes): Likewise.
 743         * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
 744         and "+T" handling.  Check for a "0" suffix when deciding whether to
 745         use coprocessor 0 names.  In that case, also check for ",H" selectors.
 746
 747 2013-07-05  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 748
 749         * s390-opc.c (J12_12, J24_24): New macros.
 750         (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
 751         (MASK_MII_UPI): Rename to MASK_MII_UPP.
 752         * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
 753
 754 2013-07-04  Alan Modra  <amodra@gmail.com>
 755
 756         * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
 757
 758 2013-06-26  Nick Clifton  <nickc@redhat.com>
 759
 760         * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
 761         field when checking for type 2 nop.
 762         * rx-decode.c: Regenerate.
 763
 764 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
 765
 766         * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
 767         and "movep" macros.
 768
 769 2013-06-24  Maciej W. Rozycki  <macro@codesourcery.com>
 770
 771         * mips-dis.c (is_mips16_plt_tail): New function.
 772         (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
 773         word.
 774         (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
 775
 776 2013-06-21  DJ Delorie  <dj@redhat.com>
 777
 778         * msp430-decode.opc: New.
 779         * msp430-decode.c: New/generated.
 780         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
 781         (MAINTAINER_CLEANFILES): Likewise.
 782         Add rule to build msp430-decode.c frommsp430decode.opc
 783         using the opc2c program.
 784         * Makefile.in: Regenerate.
 785         * configure.in: Add msp430-decode.lo to msp430 architecture files.
 786         * configure: Regenerate.
 787
 788 2013-06-20  Yufeng Zhang  <yufeng.zhang@arm.com>
 789
 790         * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
 791         (SYMTAB_AVAILABLE): Removed.
 792         (#include "elf/aarch64.h): Ditto.
 793
 794 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 795             Maciej W. Rozycki  <macro@codesourcery.com>
 796             Chao-Ying Fu  <fu@mips.com>
 797
 798         * micromips-opc.c (EVA): Define.
 799         (TLBINV): Define.
 800         (micromips_opcodes): Add EVA opcodes.
 801         * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
 802         (print_insn_args): Handle EVA offsets.
 803         (print_insn_micromips): Likewise.
 804         * mips-opc.c (EVA): Define.
 805         (TLBINV): Define.
 806         (mips_builtin_opcodes): Add EVA opcodes.
 807
 808 2013-06-17  Alan Modra  <amodra@gmail.com>
 809
 810         * Makefile.am (mips-opc.lo): Add rules to create automatic
 811         dependency files.  Pass archdefs.
 812         (micromips-opc.lo, mips16-opc.lo): Likewise.
 813         * Makefile.in: Regenerate.
 814
 815 2013-06-14  DJ Delorie  <dj@redhat.com>
 816
 817         * rx-decode.opc (rx_decode_opcode): Bit operations on
 818         registers are 32-bit operations, not 8-bit operations.
 819         * rx-decode.c: Regenerate.
 820
 821 2013-06-13  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 822
 823         * micromips-opc.c (IVIRT): New define.
 824         (IVIRT64): New define.
 825         (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 826         tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
 827
 828         * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
 829         dmtgc0 to print cp0 names.
 830
 831 2013-06-09  Sandra Loosemore  <sandra@codesourcery.com>
 832
 833         * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
 834         argument.
 835
 836 2013-06-08  Catherine Moore  <clm@codesourcery.com>
 837             Richard Sandiford  <rdsandiford@googlemail.com>
 838
 839         * micromips-opc.c (D32, D33, MC): Update definitions.
 840         (micromips_opcodes):  Initialize ase field.
 841         * mips-dis.c (mips_arch_choice): Add ase field.
 842         (mips_arch_choices): Initialize ase field.
 843         (set_default_mips_dis_options): Declare and setup mips_ase.
 844         * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
 845         MT32, MC): Update definitions.
 846         (mips_builtin_opcodes): Initialize ase field.
 847
 848 2013-05-24  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 849
 850         * s390-opc.txt (flogr): Require a register pair destination.
 851
 852 2013-05-23  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 853
 854         * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
 855         instruction format.
 856
 857 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 858
 859         * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
 860
 861 2013-05-20  Peter Bergner <bergner@vnet.ibm.com>
 862
 863         * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
 864         * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
 865         XLS_MASK, PPCVSX2): New defines.
 866         (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
 867         fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
 868         mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
 869         mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
 870         mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
 871         vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
 872         vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
 873         vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
 874         vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
 875         vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
 876         vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
 877         vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
 878         vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
 879         vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
 880         xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
 881         xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
 882         xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
 883         xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
 884         <lxvx, stxvx>: New extended mnemonics.
 885
 886 2013-05-17  Alan Modra  <amodra@gmail.com>
 887
 888         * ia64-raw.tbl: Replace non-ASCII char.
 889         * ia64-waw.tbl: Likewise.
 890         * ia64-asmtab.c: Regenerate.
 891
 892 2013-05-15  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 893
 894         * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
 895         * i386-init.h: Regenerated.
 896
 897 2013-05-13  Yufeng Zhang  <yufeng.zhang@arm.com>
 898
 899         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
 900         * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
 901         check from [0, 255] to [-128, 255].
 902
 903 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 904
 905         * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
 906         Add INSN_VIRT and INSN_VIRT64 to mips64r2.
 907         (parse_mips_dis_option): Handle the virt option.
 908         (print_insn_args): Handle "+J".
 909         (print_mips_disassembler_options): Print out message about virt64.
 910         * mips-opc.c (IVIRT): New define.
 911         (IVIRT64): New define.
 912         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 913         tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
 914         Move rfe to the bottom as it conflicts with tlbgp.
 915
 916 2013-05-09  Alan Modra  <amodra@gmail.com>
 917
 918         * ppc-opc.c (extract_vlesi): Properly sign extend.
 919         (extract_vlensi): Likewise.  Comment reason for setting invalid.
 920
 921 2013-05-02  Nick Clifton  <nickc@redhat.com>
 922
 923         * msp430-dis.c: Add support for MSP430X instructions.
 924
 925 2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>
 926
 927         * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
 928         to "eccinj".
 929
 930 2013-04-17  Wei-chen Wang  <cole945@gmail.com>
 931
 932         PR binutils/15369
 933         * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
 934         of CGEN_CPU_ENDIAN.
 935         (hash_insns_list): Likewise.
 936
 937 2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
 938
 939         * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
 940         warning workaround.
 941
 942 2013-04-08  Jan Beulich <jbeulich@suse.com>
 943
 944         * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
 945         * i386-tbl.h: Re-generate.
 946
 947 2013-04-06  David S. Miller  <davem@davemloft.net>
 948
 949         * sparc-dis.c (compare_opcodes): When encountering multiple aliases
 950         of an opcode, prefer the one with F_PREFERRED set.
 951         * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
 952         lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
 953         ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
 954         mark existing mnenomics as aliases.  Add "cc" suffix to edge
 955         instructions generating condition codes, mark existing mnenomics
 956         as aliases.  Add "fp" prefix to VIS compare instructions, mark
 957         existing mnenomics as aliases.
 958
 959 2013-04-03  Nick Clifton  <nickc@redhat.com>
 960
 961         * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
 962         destination address by subtracting the operand from the current
 963         address.
 964         * v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
 965         a positive value in the insn.
 966         (extract_u16_loop): Do not negate the returned value.
 967         (D16_LOOP): Add V850_INVERSE_PCREL flag.
 968
 969         (ceilf.sw): Remove duplicate entry.
 970         (cvtf.hs): New entry.
 971         (cvtf.sh): Likewise.
 972         (fmaf.s): Likewise.
 973         (fmsf.s): Likewise.
 974         (fnmaf.s): Likewise.
 975         (fnmsf.s): Likewise.
 976         (maddf.s): Restrict to E3V5 architectures.
 977         (msubf.s): Likewise.
 978         (nmaddf.s): Likewise.
 979         (nmsubf.s): Likewise.
 980
 981 2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
 982
 983         * i386-dis.c (get_sib): Add the sizeflag argument.  Properly
 984         check address mode.
 985         (print_insn): Pass sizeflag to get_sib.
 986
 987 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 988
 989         PR binutils/15068
 990         * tic6x-dis.c: Add support for displaying 16-bit insns.
 991
 992 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 993
 994         PR gas/15095
 995         * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
 996         individual msb and lsb halves in src1 & src2 fields.  Discard the
 997         src1 (lsb) value and only use src2 (msb), discarding bit 0, to
 998         follow what Ti SDK does in that case as any value in the src1
 999         field yields the same output with SDK disassembler.
1000
1001 2013-03-12  Michael Eager <eager@eagercon.com>
1002
1003         * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
1004
1005 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
1006
1007         * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
1008
1009 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
1010
1011         * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
1012
1013 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
1014
1015         * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
1016
1017 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1018
1019         * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
1020         (thumb32_opcodes): Likewise.
1021         (print_insn_thumb32): Handle 'S' control char.
1022
1023 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
1024
1025         * lm32-desc.c: Regenerate.
1026
1027 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1028
1029         * i386-reg.tbl (riz): Add RegRex64.
1030         * i386-tbl.h: Regenerated.
1031
1032 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
1033
1034         * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
1035         (aarch64_feature_crc): New static.
1036         (CRC): New macro.
1037         (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
1038         crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
1039         * aarch64-asm-2.c: Re-generate.
1040         * aarch64-dis-2.c: Ditto.
1041         * aarch64-opc-2.c: Ditto.
1042
1043 2013-02-27  Alan Modra  <amodra@gmail.com>
1044
1045         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
1046         * rl78-decode.c: Regenerate.
1047
1048 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
1049
1050         * rl78-decode.opc: Fix encoding of DIVWU insn.
1051         * rl78-decode.c: Regenerate.
1052
1053 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
1054
1055         PR gas/15159
1056         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
1057
1058         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
1059         (cpu_flags): Add CpuSMAP.
1060
1061         * i386-opc.h (CpuSMAP): New.
1062         (i386_cpu_flags): Add cpusmap.
1063
1064         * i386-opc.tbl: Add clac and stac.
1065
1066         * i386-init.h: Regenerated.
1067         * i386-tbl.h: Likewise.
1068
1069 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
1070
1071         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
1072         which also makes the disassembler output be in little
1073         endian like it should be.
1074
1075 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
1076
1077         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
1078         fields to NULL.
1079         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
1080
1081 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
1082
1083         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
1084         section disassembled.
1085
1086 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1087
1088         * arm-dis.c: Update strht pattern.
1089
1090 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
1091
1092         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
1093         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
1094         trunc.w.s macro for EE.
1095
1096 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
1097             Andrew Jenner <andrew@codesourcery.com>
1098
1099         Based on patches from Altera Corporation.
1100
1101         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
1102         nios2-opc.c.
1103         * Makefile.in: Regenerated.
1104         * configure.in: Add case for bfd_nios2_arch.
1105         * configure: Regenerated.
1106         * disassemble.c (ARCH_nios2): Define.
1107         (disassembler): Add case for bfd_arch_nios2.
1108         * nios2-dis.c: New file.
1109         * nios2-opc.c: New file.
1110
1111 2013-02-04  Alan Modra  <amodra@gmail.com>
1112
1113         * po/POTFILES.in: Regenerate.
1114         * rl78-decode.c: Regenerate.
1115         * rx-decode.c: Regenerate.
1116
1117 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
1118
1119         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
1120         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
1121         * aarch64-asm.c (convert_xtl_to_shll): New function.
1122         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1123         calling convert_xtl_to_shll.
1124         * aarch64-dis.c (convert_shll_to_xtl): New function.
1125         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1126         calling convert_shll_to_xtl.
1127         * aarch64-gen.c: Update copyright year.
1128         * aarch64-asm-2.c: Re-generate.
1129         * aarch64-dis-2.c: Re-generate.
1130         * aarch64-opc-2.c: Re-generate.
1131
1132 2013-01-24  Nick Clifton  <nickc@redhat.com>
1133
1134         * v850-dis.c: Add support for e3v5 architecture.
1135         * v850-opc.c: Likewise.
1136
1137 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
1138
1139         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
1140         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
1141         * aarch64-opc.c (operand_general_constraint_met_p): For
1142         AARCH64_MOD_LSL, move the range check on the shift amount before the
1143         alignment check; change to call set_sft_amount_out_of_range_error
1144         instead of set_imm_out_of_range_error.
1145         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
1146         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
1147         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1148         SIMD_IMM_SFT.
1149
1150 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
1151
1152         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1153
1154         * i386-init.h: Regenerated.
1155         * i386-tbl.h: Likewise.
1156
1157 2013-01-15  Nick Clifton  <nickc@redhat.com>
1158
1159         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1160         values.
1161         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1162
1163 2013-01-14  Will Newton <will.newton@imgtec.com>
1164
1165         * metag-dis.c (REG_WIDTH): Increase to 64.
1166
1167 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
1168
1169         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1170         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1171         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1172         (SH6): Update.
1173         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1174         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1175         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1176         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1177
1178 2013-01-10  Will Newton <will.newton@imgtec.com>
1179
1180         * Makefile.am: Add Meta.
1181         * configure.in: Add Meta.
1182         * disassemble.c: Add Meta support.
1183         * metag-dis.c: New file.
1184         * Makefile.in: Regenerate.
1185         * configure: Regenerate.
1186
1187 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1188
1189         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1190         (match_opcode): Rename to cr16_match_opcode.
1191
1192 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
1193
1194         * mips-dis.c: Add names for CP0 registers of r5900.
1195         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1196         instructions sq and lq.
1197         Add support for MIPS r5900 CPU.
1198         Add support for 128 bit MMI (Multimedia Instructions).
1199         Add support for EE instructions (Emotion Engine).
1200         Disable unsupported floating point instructions (64 bit and
1201         undefined compare operations).
1202         Enable instructions of MIPS ISA IV which are supported by r5900.
1203         Disable 64 bit co processor instructions.
1204         Disable 64 bit multiplication and division instructions.
1205         Disable instructions for co-processor 2 and 3, because these are
1206         not supported (preparation for later VU0 support (Vector Unit)).
1207         Disable cvt.w.s because this behaves like trunc.w.s and the
1208         correct execution can't be ensured on r5900.
1209         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1210         will confuse less developers and compilers.
1211
1212 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1213
1214         * aarch64-opc.c (aarch64_print_operand): Change to print
1215         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1216         in comment.
1217         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1218         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1219         OP_MOV_IMM_WIDE.
1220
1221 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1222
1223         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1224         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
1225
1226 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
1227
1228         * i386-gen.c (process_copyright): Update copyright year to 2013.
1229
1230 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1231
1232         * cr16-dis.c (match_opcode,make_instruction): Remove static
1233         declaration.
1234         (dwordU,wordU): Moved typedefs to opcode/cr16.h
1235         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
1236
1237 For older changes see ChangeLog-2012
1238 \f
1239 Copyright (C) 2013 Free Software Foundation, Inc.
1240
1241 Copying and distribution of this file, with or without modification,
1242 are permitted in any medium without royalty provided the copyright
1243 notice and this notice are preserved.
1244
1245 Local Variables:
1246 mode: change-log
1247 left-margin: 8
1248 fill-column: 74
1249 version-control: never
1250 End: