opcodes/ChangeLog

   1 2022-07-18  Claudiu Zissulescu  <claziss@synopsys.com>
   2
   3         * disassemble.c (disassemble_init_for_target): Set
   4         created_styled_output for ARC based targets.
   5         * arc-dis.c (find_format_from_table): Use fprintf_styled_ftype
   6         instead of fprintf_ftype throughout.
   7         (find_format): Likewise.
   8         (print_flags): Likewise.
   9         (print_insn_arc): Likewise.
  10
  11 2022-07-08  Nick Clifton  <nickc@redhat.com>
  12
  13         * 2.39 branch created.
  14
  15 2022-07-04  Marcus Nilsson  <brainbomb@gmail.com>
  16
  17         * disassemble.c: (disassemble_init_for_target): Set
  18         created_styled_output for AVR based targets.
  19         * avr-dis.c: (print_insn_avr): Use fprintf_styled_ftype
  20         instead of fprintf_ftype throughout.
  21         (avr_operand): Pass in and fill disassembler_style when
  22         parsing operands.
  23
  24 2022-04-07  Andreas Krebbel  <krebbel@linux.ibm.com>
  25
  26         * s390-mkopc.c (main): Enable z16 as CPU string in the opcode
  27         table.
  28
  29 2022-03-16  Simon Marchi  <simon.marchi@efficios.com>
  30
  31         * configure.ac: Handle bfd_amdgcn_arch.
  32         * configure: Re-generate.
  33
  34 2022-03-06  Sagar Patel  <sagarmp@cs.unc.edu>
  35             Maciej W. Rozycki  <macro@orcam.me.uk>
  36
  37         * mips-opc.c (mips_builtin_opcodes): Fix INSN2_ALIAS annotation
  38         for "bal", "beqz", "beqzl", "bnez" and "bnezl" instructions.
  39         * micromips-opc.c (micromips_opcodes): Likewise for "beqz" and
  40         "bnez" instructions.
  41
  42 2022-02-17  Nick Clifton  <nickc@redhat.com>
  43
  44         * po/sr.po: Updated Serbian translation.
  45
  46 2022-02-14  Sergei Trofimovich  <siarheit@google.com>
  47
  48         * microblaze-opcm.h: Renamed 'fsqrt' to 'microblaze_fsqrt'.
  49         * microblaze-opc.h: Follow 'fsqrt' rename.
  50
  51 2022-01-24  Nick Clifton  <nickc@redhat.com>
  52
  53         * po/ro.po: Updated Romanian translation.
  54         * po/uk.po: Updated Ukranian translation.
  55
  56 2022-01-22  Nick Clifton  <nickc@redhat.com>
  57
  58         * configure: Regenerate.
  59         * po/opcodes.pot: Regenerate.
  60
  61 2022-01-22  Nick Clifton  <nickc@redhat.com>
  62
  63         * 2.38 release branch created.
  64
  65 2022-01-17  Nick Clifton  <nickc@redhat.com>
  66
  67         * Makefile.in: Regenerate.
  68         * po/opcodes.pot: Regenerate.
  69
  70 2021-12-02  Marcus Nilsson  <brainbomb@gmail.com>
  71
  72         * avr-dis.c (avr_operand); Pass in disassemble_info and fill
  73         in insn_type on branching instructions.
  74
  75 2021-11-25  Andrew Burgess  <aburgess@redhat.com>
  76             Simon Cook  <simon.cook@embecosm.com>
  77
  78         * riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
  79         (riscv_options): New static global.
  80         (disassembler_options_riscv): New function.
  81         (print_riscv_disassembler_options): Rewrite to use
  82         disassembler_options_riscv.
  83
  84 2021-11-25  Nick Clifton  <nickc@redhat.com>
  85
  86         PR 28614
  87         * aarch64-asm.c: Replace assert(0) with real code.
  88         * aarch64-dis.c: Likewise.
  89         * aarch64-opc.c: Likewise.
  90
  91 2021-11-25  Nick Clifton  <nickc@redhat.com>
  92
  93         * po/fr.po; Updated French translation.
  94
  95 2021-10-27  Maciej W. Rozycki  <macro@embecosm.com>
  96
  97         * Makefile.am: Remove obsolete comment.
  98         * configure.ac: Refer `libbfd.la' to link shared BFD library
  99         except for Cygwin.
 100         * Makefile.in: Regenerate.
 101         * configure: Regenerate.
 102
 103 2021-09-27  Nick Alcock  <nick.alcock@oracle.com>
 104
 105         * configure: Regenerate.
 106
 107 2021-09-25  Peter Bergner  <bergner@linux.ibm.com>
 108
 109         * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
 110         on POWER5 and later.
 111
 112 2021-09-20  Andrew Burgess  <andrew.burgess@embecosm.com>
 113
 114         * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
 115         before an unknown instruction, '%d' is replaced with the
 116         instruction length.
 117
 118 2021-09-02  Nick Clifton  <nickc@redhat.com>
 119
 120         PR 28292
 121         * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
 122         of BFD_RELOC_16.
 123
 124 2021-08-17  Shahab Vahedi <shahab@synopsys.com>
 125
 126         * arc-regs.h (DEF): Fix the register numbers.
 127
 128 2021-08-10  Nick Clifton  <nickc@redhat.com>
 129
 130         * po/sr.po: Updated Serbian translation.
 131
 132 2021-07-26  Chenghua Xu  <xuchenghua@loongson.cn>
 133
 134         * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
 135
 136 2021-06-07  Andreas Krebbel  <krebbel@linux.ibm.com>
 137
 138         * s390-opc.txt: Add qpaci.
 139
 140 2021-07-03  Nick Clifton  <nickc@redhat.com>
 141
 142         * configure: Regenerate.
 143         * po/opcodes.pot: Regenerate.
 144
 145 2021-07-03  Nick Clifton  <nickc@redhat.com>
 146
 147         * 2.37 release branch created.
 148
 149 2021-07-02  Alan Modra  <amodra@gmail.com>
 150
 151         * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
 152         (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
 153         (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
 154         (nds32_opcodes, nds32_operand_fields, nds32_keywords),
 155         (nds32_keyword_gpr): Move declarations to..
 156         * nds32-asm.h: ..here, constifying to match definitions.
 157
 158 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 159
 160         * Makefile.am (GUILE): New variable.
 161         (CGEN): Use $(GUILE).
 162         * Makefile.in: Regenerate.
 163
 164 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 165
 166         * mep-asm.c (macros): Mark static & const.
 167         (lookup_macro): Change return & m to const.
 168         (expand_macro): Change mac to const.
 169         (expand_string): Change pmacro to const.
 170
 171 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 172
 173         * nds32-asm.c (operand_fields): Rename to ...
 174         (nds32_operand_fields): ... this.
 175         (keyword_gpr): Rename to ...
 176         (nds32_keyword_gpr): ... this.
 177         (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
 178         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
 179         keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
 180         keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
 181         keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
 182         Mark static.
 183         (keywords): Rename to ...
 184         (nds32_keywords): ... this.
 185         * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
 186         keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
 187
 188 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 189
 190         * z80-dis.c (opc_ed): Make const.
 191         (pref_ed): Make p const.
 192
 193 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 194
 195         * microblaze-dis.c (get_field_special): Make op const.
 196         (read_insn_microblaze): Make opr & op const.  Rename opcodes to
 197         microblaze_opcodes.
 198         (print_insn_microblaze): Make op & pop const.
 199         (get_insn_microblaze): Make op const.  Rename opcodes to
 200         microblaze_opcodes.
 201         (microblaze_get_target_address): Likewise.
 202         * microblaze-opc.h (struct op_code_struct): Make const.
 203         Rename opcodes to microblaze_opcodes.
 204
 205 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 206
 207         * aarch64-gen.c (aarch64_opcode_table): Add const.
 208         * aarch64-tbl.h (aarch64_opcode_table): Likewise.
 209
 210 2021-06-22  Andrew Burgess  <andrew.burgess@embecosm.com>
 211
 212         * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
 213         available.
 214
 215 2021-06-22  Alan Modra  <amodra@gmail.com>
 216
 217         * pj-dis.c (print_insn_pj): Don't print trailing tab.  Do
 218         print separator for pcrel insns.
 219
 220 2021-06-19  Alan Modra  <amodra@gmail.com>
 221
 222         * vax-dis.c (print_insn_vax): Avoid pointer overflow.
 223
 224 2021-06-19  Alan Modra  <amodra@gmail.com>
 225
 226         * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
 227         entire buffer.
 228
 229 2021-06-17  Alan Modra  <amodra@gmail.com>
 230
 231         * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
 232         in table.
 233
 234 2021-06-03  Alan Modra  <amodra@gmail.com>
 235
 236         PR 1202
 237         * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
 238         Use unsigned int for inst.
 239
 240 2021-06-02  Shahab Vahedi  <shahab@synopsys.com>
 241
 242         * arc-dis.c (arc_option_arg_t): New enumeration.
 243         (arc_options): New variable.
 244         (disassembler_options_arc): New function.
 245         (print_arc_disassembler_options): Reimplement in terms of
 246         "disassembler_options_arc".
 247
 248 2021-05-29  Alan Modra  <amodra@gmail.com>
 249
 250         * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
 251         Don't special case PPC_OPCODE_RAW.
 252         (lookup_prefix): Likewise.
 253         (lookup_vle, lookup_spe2): Similarly.  Add dialect parameter and..
 254         (print_insn_powerpc): ..update caller.
 255         * ppc-opc.c (EXT): Define.
 256         (powerpc_opcodes): Mark extended mnemonics with EXT.
 257         (prefix_opcodes, vle_opcodes): Likewise.
 258         (XISEL, XISEL_MASK): Add cr field and simplify.
 259         (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
 260         all isel variants to where the base mnemonic belongs.  Sort dstt,
 261         dststt and dssall.
 262
 263 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 264
 265         * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
 266         COP3 opcode instructions.
 267
 268 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 269
 270         * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
 271         "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
 272         "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
 273         "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
 274         "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
 275         "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
 276         "cop2", and "cop3" entries.
 277
 278 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 279
 280         * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
 281         entries and associated comments.
 282
 283 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 284
 285         * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
 286         of "c0".
 287
 288 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 289
 290         * mips-dis.c (mips_cp1_names_mips): New variable.
 291         (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
 292         for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
 293         "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
 294         "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
 295         "r12000", "r14000", "r16000", "mips5", "loongson2e", and
 296         "loongson2f".
 297
 298 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 299
 300         * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
 301         handling code over to...
 302         <OP_REG_CONTROL>: ... this new case.
 303         * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
 304         (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
 305         "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
 306         replacing the `G' operand code with `g'.  Update "cftc1" and
 307         "cftc2" entries replacing the `E' operand code with `y'.
 308         * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
 309         (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
 310         entries replacing the `G' operand code with `g'.
 311
 312 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 313
 314         * mips-dis.c (mips_cp0_names_r3900): New variable.
 315         (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
 316         for "r3900".
 317
 318 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 319
 320         * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
 321         and "mtthc2" to using the `G' rather than `g' operand code for
 322         the coprocessor control register referred.
 323
 324 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 325
 326         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
 327         entries with each other.
 328
 329 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
 330
 331         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
 332
 333 2021-05-25  Alan Modra  <amodra@gmail.com>
 334
 335         * cris-desc.c: Regenerate.
 336         * cris-desc.h: Regenerate.
 337         * cris-opc.h: Regenerate.
 338         * po/POTFILES.in: Regenerate.
 339
 340 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
 341
 342         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
 343         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
 344         (CGEN_CPUS): Add cris.
 345         (CRIS_DEPS): Define.
 346         (stamp-cris): New rule.
 347         * cgen.sh: Handle desc action.
 348         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
 349         * Makefile.in, configure: Regenerate.
 350
 351 2021-05-18  Job Noorman  <mtvec@pm.me>
 352
 353         PR 27814
 354         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
 355         the elf objects.
 356
 357 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
 358
 359         * arm-dis.c (mve_opcodes): Fix disassembly of
 360         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
 361         (is_mve_encoding_conflict): MVE vector loads should not match
 362         when P = W = 0.
 363         (is_mve_unpredictable): It's not unpredictable to use the same
 364         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
 365
 366 2021-05-11  Nick Clifton  <nickc@redhat.com>
 367
 368         PR 27840
 369         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
 370         the end of the code buffer.
 371
 372 2021-05-06  Stafford Horne  <shorne@gmail.com>
 373
 374         PR 21464
 375         * or1k-asm.c: Regenerate.
 376
 377 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
 378
 379         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
 380         info->insn_info_valid.
 381
 382 2021-04-26  Jan Beulich  <jbeulich@suse.com>
 383
 384         * i386-opc.tbl (lea): Add Optimize.
 385         * opcodes/i386-tbl.h: Re-generate.
 386
 387 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 388
 389         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
 390         of l32r fetch and display referenced literal value.
 391
 392 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 393
 394         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
 395         to 4 for literal disassembly.
 396
 397 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 398
 399         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
 400         for TLBI instruction.
 401
 402 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 403
 404         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
 405         DC instruction.
 406
 407 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 408
 409         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
 410         "qualifier".
 411         (convert_mov_to_movewide): Add initializer for "value".
 412
 413 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 414
 415         * aarch64-opc.c: Add RME system registers.
 416
 417 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 418
 419         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
 420         "addi d,CV,z" to "c.mv d,CV".
 421
 422 2021-04-12  Alan Modra  <amodra@gmail.com>
 423
 424         * configure.ac (--enable-checking): Add support.
 425         * config.in: Regenerate.
 426         * configure: Regenerate.
 427
 428 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 429
 430         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 431         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 432
 433 2021-04-09  Alan Modra  <amodra@gmail.com>
 434
 435         * ppc-dis.c (struct dis_private): Add "special".
 436         (POWERPC_DIALECT): Delete.  Replace uses with..
 437         (private_data): ..this.  New inline function.
 438         (disassemble_init_powerpc): Init "special" names.
 439         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 440         field of prefix instructions.
 441         (bsearch_reloc, print_got_plt): New functions.
 442         (print_insn_powerpc): For pcrel instructions, print target address
 443         and symbol if known, and decode plt and got loads too.
 444
 445 2021-04-08  Alan Modra  <amodra@gmail.com>
 446
 447         PR 27684
 448         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 449
 450 2021-04-08  Alan Modra  <amodra@gmail.com>
 451
 452         PR 27676
 453         * ppc-opc.c (DCBT_EO): Move earlier.
 454         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 455         (powerpc_operands): Add THCT and THDS entries.
 456         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 457
 458 2021-04-06  Alan Modra  <amodra@gmail.com>
 459
 460         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 461         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 462         symbol_at_address_func.
 463
 464 2021-04-05  Alan Modra  <amodra@gmail.com>
 465
 466         * configure.ac: Don't check for limits.h, string.h, strings.h or
 467         stdlib.h.
 468         (AC_ISC_POSIX): Don't invoke.
 469         * sysdep.h: Include stdlib.h and string.h unconditionally.
 470         * i386-opc.h: Include limits.h unconditionally.
 471         * wasm32-dis.c: Likewise.
 472         * cgen-opc.c: Don't include alloca-conf.h.
 473         * config.in: Regenerate.
 474         * configure: Regenerate.
 475
 476 2021-04-01  Martin Liska  <mliska@suse.cz>
 477
 478         * arm-dis.c (strneq): Remove strneq and use startswith.
 479         * cr16-dis.c (print_insn_cr16): Likewise.
 480         * score-dis.c (streq): Likewise.
 481         (strneq): Likewise.
 482         * score7-dis.c (strneq): Likewise.
 483
 484 2021-04-01  Alan Modra  <amodra@gmail.com>
 485
 486         PR 27675
 487         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 488
 489 2021-03-31  Alan Modra  <amodra@gmail.com>
 490
 491         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 492         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 493         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 494         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 495         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 496         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 497         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 498         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 499         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 500         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 501         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 502         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 503         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 504         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 505         and TRUE with true throughout.
 506
 507 2021-03-31  Alan Modra  <amodra@gmail.com>
 508
 509         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 510         * aarch64-dis.h: Likewise.
 511         * aarch64-opc.c: Likewise.
 512         * avr-dis.c: Likewise.
 513         * csky-dis.c: Likewise.
 514         * nds32-asm.c: Likewise.
 515         * nds32-dis.c: Likewise.
 516         * nfp-dis.c: Likewise.
 517         * riscv-dis.c: Likewise.
 518         * s12z-dis.c: Likewise.
 519         * wasm32-dis.c: Likewise.
 520
 521 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 522
 523         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 524         (i386_seg_prefixes): New.
 525         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 526         (i386_seg_prefixes): Declare.
 527
 528 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 529
 530         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 531
 532 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 533
 534         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 535         * i386-reg.tbl (st): Move down.
 536         (st(0)): Delete. Extend comment.
 537         * i386-tbl.h: Re-generate.
 538
 539 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 540
 541         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 542         (cmpsd): Move next to cmps.
 543         (movsd): Move next to movs.
 544         (cmpxchg16b): Move to separate section.
 545         (fisttp, fisttpll): Likewise.
 546         (monitor, mwait): Likewise.
 547         * i386-tbl.h: Re-generate.
 548
 549 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 550
 551         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 552         (vpsadbw): Add C.
 553         * i386-tbl.h: Re-generate.
 554
 555 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 556
 557         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 558         pclmul, gfni): New templates. Use them wherever possible. Move
 559         SSE4.1 pextrw into respective section.
 560         * i386-tbl.h: Re-generate.
 561
 562 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 563
 564         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 565         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 566         "length".
 567         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 568         Convert all of their uses to representation in opcode.
 569
 570 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 571
 572         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 573         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 574         value of None. Shrink operands to 3 bits.
 575
 576 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 577
 578         * i386-gen.c (process_i386_opcode_modifier): New parameter
 579         "space".
 580         (output_i386_opcode): New local variable "space". Adjust
 581         process_i386_opcode_modifier() invocation.
 582         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 583         invocation.
 584         * i386-tbl.h: Re-generate.
 585
 586 2021-03-29  Alan Modra  <amodra@gmail.com>
 587
 588         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 589         (fp_qualifier_p, get_data_pattern): Likewise.
 590         (aarch64_get_operand_modifier_from_value): Likewise.
 591         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 592         (operand_variant_qualifier_p): Likewise.
 593         (qualifier_value_in_range_constraint_p): Likewise.
 594         (aarch64_get_qualifier_esize): Likewise.
 595         (aarch64_get_qualifier_nelem): Likewise.
 596         (aarch64_get_qualifier_standard_value): Likewise.
 597         (get_lower_bound, get_upper_bound): Likewise.
 598         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 599         (aarch64_print_operand): Likewise.
 600         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 601         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 602         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 603         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 604         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 605         (print_insn_tic6x): Likewise.
 606
 607 2021-03-29  Alan Modra  <amodra@gmail.com>
 608
 609         * arc-dis.c (extract_operand_value): Correct NULL cast.
 610         * frv-opc.h: Regenerate.
 611
 612 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 613
 614         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 615         MMX form.
 616         * i386-tbl.h: Re-generate.
 617
 618 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 619
 620         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 621         immediate in br.n instruction.
 622
 623 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 624
 625         * i386-dis.c (XMGatherD, VexGatherD): New.
 626         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 627         (print_insn): Check masking for S/G insns.
 628         (OP_E_memory): New local variable check_gather. Extend mandatory
 629         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 630         Extend check for disallowed 16-bit addressing.
 631         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 632         if()s to switch(). Check register conflicts for (VEX-encoded)
 633         gathers. Drop no longer reachable cases.
 634         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 635         vgatherdp*.
 636
 637 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 638
 639         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 640         zeroing-masking without masking.
 641
 642 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 643
 644         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 645         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 646         single-operand forms as deprecated.
 647         * i386-tbl.h: Re-generate.
 648
 649 2021-03-25  Alan Modra  <amodra@gmail.com>
 650
 651         PR 27647
 652         * ppc-opc.c (XLOCB_MASK): Delete.
 653         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 654         XLBH_MASK.
 655         (powerpc_opcodes): Accept a BH field on all extended forms of
 656         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 657
 658 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 659
 660         * i386-gen.c (output_i386_opcode): Drop processing of
 661         opcode_length. Calculate length from base_opcode. Adjust prefix
 662         encoding determination.
 663         (process_i386_opcodes): Drop output of fake opcode_length.
 664         * i386-opc.h (struct insn_template): Drop opcode_length field.
 665         * i386-opc.tbl: Drop opcode length field from all templates.
 666         * i386-tbl.h: Re-generate.
 667
 668 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 669
 670         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 671         parameter "prefix". Drop local variable "regular_encoding".
 672         Record prefix setting / check for consistency.
 673         (output_i386_opcode): Parse opcode_length and base_opcode
 674         earlier. Derive prefix encoding. Drop no longer applicable
 675         consistency checking. Adjust process_i386_opcode_modifier()
 676         invocation.
 677         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 678         invocation.
 679         * i386-tbl.h: Re-generate.
 680
 681 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 682
 683         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 684         check.
 685         * i386-opc.h (Prefix_*): Move #define-s.
 686         * i386-opc.tbl: Move pseudo prefix enumerator values to
 687         extension opcode field. Introduce pseudopfx template.
 688         * i386-tbl.h: Re-generate.
 689
 690 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 691
 692         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 693         comment.
 694         * i386-tbl.h: Re-generate.
 695
 696 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 697
 698         * i386-opc.h (struct insn_template): Move cpu_flags field past
 699         opcode_modifier one.
 700         * i386-tbl.h: Re-generate.
 701
 702 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 703
 704         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 705         * i386-opc.h (OpcodeSpace): New enumerator.
 706         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 707         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 708         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 709         (struct i386_opcode_modifier): New field opcodespace. Shrink
 710         opcodeprefix field.
 711         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 712         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 713         OpcodePrefix uses.
 714         * i386-tbl.h: Re-generate.
 715
 716 2021-03-22  Martin Liska  <mliska@suse.cz>
 717
 718         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 719         * arc-dis.c (parse_option): Likewise.
 720         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 721         * cris-dis.c (print_with_operands): Likewise.
 722         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 723         * i386-dis.c (print_insn): Likewise.
 724         * ia64-gen.c (fetch_insn_class): Likewise.
 725         (parse_resource_users): Likewise.
 726         (in_iclass): Likewise.
 727         (lookup_specifier): Likewise.
 728         (insert_opcode_dependencies): Likewise.
 729         * mips-dis.c (parse_mips_ase_option): Likewise.
 730         (parse_mips_dis_option): Likewise.
 731         * s390-dis.c (disassemble_init_s390): Likewise.
 732         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 733
 734 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 735
 736         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 737
 738 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 739
 740         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 741         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 742
 743 2021-03-12  Alan Modra  <amodra@gmail.com>
 744
 745         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 746
 747 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 748
 749         * i386-dis.c (OP_XMM): Re-order checks.
 750
 751 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 752
 753         * i386-dis.c (putop): Drop need_vex check when also checking
 754         vex.evex.
 755         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 756         checking vex.b.
 757
 758 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 759
 760         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 761         checks. Move case label past broadcast check.
 762
 763 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 764
 765         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 766         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 767         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 768         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 769         EVEX_W_0F38C7_M_0_L_2): Delete.
 770         (REG_EVEX_0F38C7_M_0_L_2): New.
 771         (intel_operand_size): Handle VEX and EVEX the same for
 772         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 773         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 774         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 775         vex_vsib_q_w_d_mode uses.
 776         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 777         0F38A1, and 0F38A3 entries.
 778         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 779         entry.
 780         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 781         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 782         0F38A3 entries.
 783
 784 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 785
 786         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 787         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 788         MOD_VEX_0FXOP_09_12): Rename to ...
 789         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 790         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 791         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 792         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 793         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 794         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 795         (reg_table): Adjust comments.
 796         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 797         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 798         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 799         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 800         (vex_len_table): Adjust opcode 0A_12 entry.
 801         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 802         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 803         (rm_table): Move hreset entry.
 804
 805 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 806
 807         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 808         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 809         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 810         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 811         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 812         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 813         (get_valid_dis386): Also handle 512-bit vector length when
 814         vectoring into vex_len_table[].
 815         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 816         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 817         entries.
 818         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 819         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 820         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 821         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 822         entries.
 823
 824 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 825
 826         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 827         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 828         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 829         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 830         entries.
 831         * i386-dis-evex-len.h (evex_len_table): Likewise.
 832         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 833
 834 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 835
 836         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 837         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 838         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 839         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 840         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 841         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 842         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 843         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 844         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 845         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 846         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 847         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 848         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 849         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 850         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 851         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 852         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 853         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 854         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 855         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 856         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 857         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 858         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 859         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 860         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 861         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 862         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 863         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 864         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 865         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 866         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 867         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 868         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 869         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 870         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 871         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 872         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 873         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 874         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 875         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 876         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 877         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 878         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 879         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 880         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 881         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 882         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 883         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 884         EVEX_W_0F3A43_L_n): New.
 885         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 886         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 887         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 888         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 889         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 890         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 891         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 892         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 893         0F385B, 0F38C6, and 0F38C7 entries.
 894         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 895         0F38C6 and 0F38C7.
 896         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 897         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 898         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 899         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 900
 901 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 902
 903         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 904         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 905         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 906         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 907         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 908         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 909         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 910         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 911         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 912         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 913         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 914         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 915         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 916         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 917         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 918         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 919         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 920         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 921         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 922         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 923         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 924         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 925         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 926         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 927         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 928         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 929         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 930         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 931         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 932         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 933         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 934         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 935         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 936         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 937         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 938         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 939         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 940         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 941         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 942         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 943         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 944         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 945         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 946         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 947         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 948         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 949         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 950         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 951         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 952         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 953         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 954         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 955         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 956         VEX_W_0F99_P_2_LEN_0): Delete.
 957         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 958         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 959         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 960         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 961         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 962         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 963         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 964         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 965         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 966         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 967         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 968         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 969         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 970         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 971         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 972         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 973         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 974         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 975         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 976         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 977         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 978         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 979         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 980         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 981         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 982         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 983         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 984         (prefix_table): No longer link to vex_len_table[] for opcodes
 985         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 986         0F92, 0F93, 0F98, and 0F99.
 987         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 988         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 989         0F98, and 0F99.
 990         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 991         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 992         0F98, and 0F99.
 993         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 994         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 995         0F98, and 0F99.
 996         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 997         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 998         0F98, and 0F99.
 999
1000 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1001
1002         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
1003         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
1004         REG_VEX_0F73_M_0 respectively.
1005         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
1006         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
1007         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
1008         MOD_VEX_0F73_REG_7): Delete.
1009         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
1010         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
1011         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
1012         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
1013         PREFIX_VEX_0F3AF0_L_0 respectively.
1014         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
1015         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
1016         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
1017         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
1018         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
1019         VEX_LEN_0F38F7): New.
1020         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
1021         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
1022         0F72, and 0F73. No longer link to vex_len_table[] for opcode
1023         0F38F3.
1024         (prefix_table): No longer link to vex_len_table[] for opcodes
1025         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1026         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
1027         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
1028         0F38F6, 0F38F7, and 0F3AF0.
1029         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
1030         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1031         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
1032         0F73.
1033
1034 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1035
1036         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
1037         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
1038         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
1039         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
1040         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
1041         (MOD_0F71, MOD_0F72, MOD_0F73): New.
1042         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
1043         73.
1044         (reg_table): No longer link to mod_table[] for opcodes 0F71,
1045         0F72, and 0F73.
1046         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
1047         0F73.
1048
1049 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1050
1051         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
1052         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
1053         (reg_table): Don't link to mod_table[] where not needed. Add
1054         PREFIX_IGNORED to nop entries.
1055         (prefix_table): Replace PREFIX_OPCODE in nop entries.
1056         (mod_table): Add nop entries next to prefetch ones. Drop
1057         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
1058         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
1059         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
1060         PREFIX_OPCODE from endbr* entries.
1061         (get_valid_dis386): Also consider entry's name when zapping
1062         vindex.
1063         (print_insn): Handle PREFIX_IGNORED.
1064
1065 2021-03-09  Jan Beulich  <jbeulich@suse.com>
1066
1067         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
1068         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
1069         element.
1070         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
1071         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
1072         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
1073         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
1074         (struct i386_opcode_modifier): Delete notrackprefixok,
1075         islockable, hleprefixok, and repprefixok fields. Add prefixok
1076         field.
1077         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
1078         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
1079         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
1080         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
1081         Replace HLEPrefixOk.
1082         * opcodes/i386-tbl.h: Re-generate.
1083
1084 2021-03-09  Jan Beulich  <jbeulich@suse.com>
1085
1086         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
1087         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
1088         64-bit form.
1089         * opcodes/i386-tbl.h: Re-generate.
1090
1091 2021-03-03  Jan Beulich  <jbeulich@suse.com>
1092
1093         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
1094         for {} instead of {0}. Don't look for '0'.
1095         * i386-opc.tbl: Drop operand count field. Drop redundant operand
1096         size specifiers.
1097
1098 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
1099
1100         PR 27158
1101         * riscv-dis.c (print_insn_args): Updated encoding macros.
1102         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1103         (match_c_addi16sp): Updated encoding macros.
1104         (match_c_lui): Likewise.
1105         (match_c_lui_with_hint): Likewise.
1106         (match_c_addi4spn): Likewise.
1107         (match_c_slli): Likewise.
1108         (match_slli_as_c_slli): Likewise.
1109         (match_c_slli64): Likewise.
1110         (match_srxi_as_c_srxi): Likewise.
1111         (riscv_insn_types): Added .insn css/cl/cs.
1112
1113 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
1114
1115         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1116         (default_priv_spec): Updated type to riscv_spec_class.
1117         (parse_riscv_dis_option): Updated.
1118         * riscv-opc.c: Moved stuff and make the file tidy.
1119
1120 2021-02-17  Alan Modra  <amodra@gmail.com>
1121
1122         * wasm32-dis.c: Include limits.h.
1123         (CHAR_BIT): Provide backup define.
1124         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1125         Correct signed overflow checking.
1126
1127 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1128
1129         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1130         * i386-tbl.h: Re-generate.
1131
1132 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1133
1134         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1135         Oword.
1136         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1137
1138 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
1139
1140         * s390-mkopc.c (main): Accept arch14 as cpu string.
1141         * s390-opc.txt: Add new arch14 instructions.
1142
1143 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
1144
1145         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1146         favour of LIBINTL.
1147         * configure: Regenerated.
1148
1149 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
1150
1151         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1152         * tic54x-opc.c (regs): Rename to ...
1153         (tic54x_regs): ... this.
1154         (mmregs): Rename to ...
1155         (tic54x_mmregs): ... this.
1156         (condition_codes): Rename to ...
1157         (tic54x_condition_codes): ... this.
1158         (cc2_codes): Rename to ...
1159         (tic54x_cc2_codes): ... this.
1160         (cc3_codes): Rename to ...
1161         (tic54x_cc3_codes): ... this.
1162         (status_bits): Rename to ...
1163         (tic54x_status_bits): ... this.
1164         (misc_symbols): Rename to ...
1165         (tic54x_misc_symbols): ... this.
1166
1167 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
1168
1169         * riscv-opc.c (MASK_RVB_IMM): Removed.
1170         (riscv_opcodes): Removed zb* instructions.
1171         (riscv_ext_version_table): Removed versions for zb*.
1172
1173 2021-01-26  Alan Modra  <amodra@gmail.com>
1174
1175         * i386-gen.c (parse_template): Ensure entire template_instance
1176         is initialised.
1177
1178 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1179
1180         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1181         (riscv_fpr_names_abi): Likewise.
1182         (riscv_opcodes): Likewise.
1183         (riscv_insn_types): Likewise.
1184
1185 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1186
1187         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1188
1189 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1190
1191         * riscv-dis.c: Comments tidy and improvement.
1192         * riscv-opc.c: Likewise.
1193
1194 2021-01-13  Alan Modra  <amodra@gmail.com>
1195
1196         * Makefile.in: Regenerate.
1197
1198 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
1199
1200         PR binutils/26792
1201         * configure.ac: Use GNU_MAKE_JOBSERVER.
1202         * aclocal.m4: Regenerated.
1203         * configure: Likewise.
1204
1205 2021-01-12  Nick Clifton  <nickc@redhat.com>
1206
1207         * po/sr.po: Updated Serbian translation.
1208
1209 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
1210
1211         PR ld/27173
1212         * configure: Regenerated.
1213
1214 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1215
1216         * aarch64-asm-2.c: Regenerate.
1217         * aarch64-dis-2.c: Likewise.
1218         * aarch64-opc-2.c: Likewise.
1219         * aarch64-opc.c (aarch64_print_operand):
1220         Delete handling of AARCH64_OPND_CSRE_CSR.
1221         * aarch64-tbl.h (aarch64_feature_csre): Delete.
1222         (CSRE): Likewise.
1223         (_CSRE_INSN): Likewise.
1224         (aarch64_opcode_table): Delete csr.
1225
1226 2021-01-11  Nick Clifton  <nickc@redhat.com>
1227
1228         * po/de.po: Updated German translation.
1229         * po/fr.po: Updated French translation.
1230         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1231         * po/sv.po: Updated Swedish translation.
1232         * po/uk.po: Updated Ukranian translation.
1233
1234 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
1235
1236         * configure: Regenerated.
1237
1238 2021-01-09  Nick Clifton  <nickc@redhat.com>
1239
1240         * configure: Regenerate.
1241         * po/opcodes.pot: Regenerate.
1242
1243 2021-01-09  Nick Clifton  <nickc@redhat.com>
1244
1245         * 2.36 release branch crated.
1246
1247 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
1248
1249         * ppc-opc.c (insert_dw, (extract_dw): New functions.
1250         (DW, (XRC_MASK): Define.
1251         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1252
1253 2021-01-09  Alan Modra  <amodra@gmail.com>
1254
1255         * configure: Regenerate.
1256
1257 2021-01-08  Nick Clifton  <nickc@redhat.com>
1258
1259         * po/sv.po: Updated Swedish translation.
1260
1261 2021-01-08  Nick Clifton  <nickc@redhat.com>
1262
1263         PR 27129
1264         * aarch64-dis.c (determine_disassembling_preference): Move call to
1265         aarch64_match_operands_constraint outside of the assertion.
1266         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1267         Replace with a return of FALSE.
1268
1269         PR 27139
1270         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1271         core system register.
1272
1273 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
1274
1275         * configure: Regenerate.
1276
1277 2021-01-07  Nick Clifton  <nickc@redhat.com>
1278
1279         * po/fr.po: Updated French translation.
1280
1281 2021-01-07  Fredrik Noring  <noring@nocrew.org>
1282
1283         * m68k-opc.c (chkl): Change minimum architecture requirement to
1284         m68020.
1285
1286 2021-01-07  Philipp Tomsich  <prt@gnu.org>
1287
1288         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1289
1290 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
1291             Jim Wilson  <jimw@sifive.com>
1292             Andrew Waterman  <andrew@sifive.com>
1293             Maxim Blinov  <maxim.blinov@embecosm.com>
1294             Kito Cheng  <kito.cheng@sifive.com>
1295             Nelson Chu  <nelson.chu@sifive.com>
1296
1297         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1298         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1299
1300 2021-01-01  Alan Modra  <amodra@gmail.com>
1301
1302         Update year range in copyright notice of all files.
1303
1304 For older changes see ChangeLog-2020
1305 \f
1306 Copyright (C) 2021-2022 Free Software Foundation, Inc.
1307
1308 Copying and distribution of this file, with or without modification,
1309 are permitted in any medium without royalty provided the copyright
1310 notice and this notice are preserved.
1311
1312 Local Variables:
1313 mode: change-log
1314 left-margin: 8
1315 fill-column: 74
1316 version-control: never
1317 End: