1 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
3 * mips16-opc.c: Include mips-formats.h.
4 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
6 (decode_mips16_operand): New function.
7 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
8 (print_insn_arg): Handle OP_ENTRY_EXIT list.
9 Abort for OP_SAVE_RESTORE_LIST.
10 (print_mips16_insn_arg): Change interface. Use mips_operand
11 structures. Delete GET_OP_S. Move GET_OP definition to...
12 (print_insn_mips16): ...here. Call init_print_arg_state.
13 Update the call to print_mips16_insn_arg.
15 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
17 * mips-formats.h: New file.
18 * mips-opc.c: Include mips-formats.h.
19 (reg_0_map): New static array.
20 (decode_mips_operand): New function.
21 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
22 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
23 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
24 (int_c_map): New static arrays.
25 (decode_micromips_operand): New function.
26 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
27 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
28 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
29 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
30 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
31 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
32 (micromips_imm_b_map, micromips_imm_c_map): Delete.
33 (print_reg): New function.
34 (mips_print_arg_state): New structure.
35 (init_print_arg_state, print_insn_arg): New functions.
36 (print_insn_args): Change interface and use mips_operand structures.
37 Delete GET_OP_S. Move GET_OP definition to...
38 (print_insn_mips): ...here. Update the call to print_insn_args.
39 (print_insn_micromips): Use print_insn_args.
41 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
43 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
46 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
48 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
49 ADDA.S, MULA.S and SUBA.S.
51 2013-07-08 H.J. Lu <hongjiu.lu@intel.com>
54 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
55 * i386-tbl.h: Regenerated.
57 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
59 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
60 and SD A(B) macros up.
61 * micromips-opc.c (micromips_opcodes): Likewise.
63 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
65 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
68 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
70 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
71 MDMX-like instructions.
72 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
73 printing "Q" operands for INSN_5400 instructions.
75 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
77 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
79 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
82 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
84 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
86 * mips16-opc.c (mips16_opcodes): Likewise.
87 * micromips-opc.c (micromips_opcodes): Likewise.
88 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
89 (print_insn_mips16): Handle "+i".
90 (print_insn_micromips): Likewise. Conditionally preserve the
91 ISA bit for "a" but not for "+i".
93 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
95 * micromips-opc.c (WR_mhi): Rename to..
97 (micromips_opcodes): Update "movep" entry accordingly. Replace
99 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
100 (micromips_to_32_reg_h_map1): ...this.
101 (micromips_to_32_reg_i_map): Rename to...
102 (micromips_to_32_reg_h_map2): ...this.
103 (print_micromips_insn): Remove "mi" case. Print both registers
104 in the pair for "mh".
106 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
108 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
109 * micromips-opc.c (micromips_opcodes): Likewise.
110 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
111 and "+T" handling. Check for a "0" suffix when deciding whether to
112 use coprocessor 0 names. In that case, also check for ",H" selectors.
114 2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
116 * s390-opc.c (J12_12, J24_24): New macros.
117 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
118 (MASK_MII_UPI): Rename to MASK_MII_UPP.
119 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
121 2013-07-04 Alan Modra <amodra@gmail.com>
123 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
125 2013-06-26 Nick Clifton <nickc@redhat.com>
127 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
128 field when checking for type 2 nop.
129 * rx-decode.c: Regenerate.
131 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
133 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
136 2013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
138 * mips-dis.c (is_mips16_plt_tail): New function.
139 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
141 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
143 2013-06-21 DJ Delorie <dj@redhat.com>
145 * msp430-decode.opc: New.
146 * msp430-decode.c: New/generated.
147 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
148 (MAINTAINER_CLEANFILES): Likewise.
149 Add rule to build msp430-decode.c frommsp430decode.opc
150 using the opc2c program.
151 * Makefile.in: Regenerate.
152 * configure.in: Add msp430-decode.lo to msp430 architecture files.
153 * configure: Regenerate.
155 2013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
157 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
158 (SYMTAB_AVAILABLE): Removed.
159 (#include "elf/aarch64.h): Ditto.
161 2013-06-17 Catherine Moore <clm@codesourcery.com>
162 Maciej W. Rozycki <macro@codesourcery.com>
163 Chao-Ying Fu <fu@mips.com>
165 * micromips-opc.c (EVA): Define.
167 (micromips_opcodes): Add EVA opcodes.
168 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
169 (print_insn_args): Handle EVA offsets.
170 (print_insn_micromips): Likewise.
171 * mips-opc.c (EVA): Define.
173 (mips_builtin_opcodes): Add EVA opcodes.
175 2013-06-17 Alan Modra <amodra@gmail.com>
177 * Makefile.am (mips-opc.lo): Add rules to create automatic
178 dependency files. Pass archdefs.
179 (micromips-opc.lo, mips16-opc.lo): Likewise.
180 * Makefile.in: Regenerate.
182 2013-06-14 DJ Delorie <dj@redhat.com>
184 * rx-decode.opc (rx_decode_opcode): Bit operations on
185 registers are 32-bit operations, not 8-bit operations.
186 * rx-decode.c: Regenerate.
188 2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
190 * micromips-opc.c (IVIRT): New define.
191 (IVIRT64): New define.
192 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
193 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
195 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
196 dmtgc0 to print cp0 names.
198 2013-06-09 Sandra Loosemore <sandra@codesourcery.com>
200 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
203 2013-06-08 Catherine Moore <clm@codesourcery.com>
204 Richard Sandiford <rdsandiford@googlemail.com>
206 * micromips-opc.c (D32, D33, MC): Update definitions.
207 (micromips_opcodes): Initialize ase field.
208 * mips-dis.c (mips_arch_choice): Add ase field.
209 (mips_arch_choices): Initialize ase field.
210 (set_default_mips_dis_options): Declare and setup mips_ase.
211 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
212 MT32, MC): Update definitions.
213 (mips_builtin_opcodes): Initialize ase field.
215 2013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
217 * s390-opc.txt (flogr): Require a register pair destination.
219 2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
221 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
224 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
226 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
228 2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
230 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
231 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
232 XLS_MASK, PPCVSX2): New defines.
233 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
234 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
235 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
236 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
237 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
238 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
239 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
240 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
241 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
242 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
243 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
244 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
245 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
246 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
247 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
248 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
249 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
250 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
251 <lxvx, stxvx>: New extended mnemonics.
253 2013-05-17 Alan Modra <amodra@gmail.com>
255 * ia64-raw.tbl: Replace non-ASCII char.
256 * ia64-waw.tbl: Likewise.
257 * ia64-asmtab.c: Regenerate.
259 2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
261 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
262 * i386-init.h: Regenerated.
264 2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
266 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
267 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
268 check from [0, 255] to [-128, 255].
270 2013-05-09 Andrew Pinski <apinski@cavium.com>
272 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
273 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
274 (parse_mips_dis_option): Handle the virt option.
275 (print_insn_args): Handle "+J".
276 (print_mips_disassembler_options): Print out message about virt64.
277 * mips-opc.c (IVIRT): New define.
278 (IVIRT64): New define.
279 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
280 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
281 Move rfe to the bottom as it conflicts with tlbgp.
283 2013-05-09 Alan Modra <amodra@gmail.com>
285 * ppc-opc.c (extract_vlesi): Properly sign extend.
286 (extract_vlensi): Likewise. Comment reason for setting invalid.
288 2013-05-02 Nick Clifton <nickc@redhat.com>
290 * msp430-dis.c: Add support for MSP430X instructions.
292 2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
294 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
297 2013-04-17 Wei-chen Wang <cole945@gmail.com>
300 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
302 (hash_insns_list): Likewise.
304 2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
306 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
309 2013-04-08 Jan Beulich <jbeulich@suse.com>
311 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
312 * i386-tbl.h: Re-generate.
314 2013-04-06 David S. Miller <davem@davemloft.net>
316 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
317 of an opcode, prefer the one with F_PREFERRED set.
318 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
319 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
320 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
321 mark existing mnenomics as aliases. Add "cc" suffix to edge
322 instructions generating condition codes, mark existing mnenomics
323 as aliases. Add "fp" prefix to VIS compare instructions, mark
324 existing mnenomics as aliases.
326 2013-04-03 Nick Clifton <nickc@redhat.com>
328 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
329 destination address by subtracting the operand from the current
331 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
332 a positive value in the insn.
333 (extract_u16_loop): Do not negate the returned value.
334 (D16_LOOP): Add V850_INVERSE_PCREL flag.
336 (ceilf.sw): Remove duplicate entry.
337 (cvtf.hs): New entry.
343 (maddf.s): Restrict to E3V5 architectures.
345 (nmaddf.s): Likewise.
346 (nmsubf.s): Likewise.
348 2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
350 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
352 (print_insn): Pass sizeflag to get_sib.
354 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
357 * tic6x-dis.c: Add support for displaying 16-bit insns.
359 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
362 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
363 individual msb and lsb halves in src1 & src2 fields. Discard the
364 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
365 follow what Ti SDK does in that case as any value in the src1
366 field yields the same output with SDK disassembler.
368 2013-03-12 Michael Eager <eager@eagercon.com>
370 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
372 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
374 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
376 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
378 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
380 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
382 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
384 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
386 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
387 (thumb32_opcodes): Likewise.
388 (print_insn_thumb32): Handle 'S' control char.
390 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
392 * lm32-desc.c: Regenerate.
394 2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
396 * i386-reg.tbl (riz): Add RegRex64.
397 * i386-tbl.h: Regenerated.
399 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
401 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
402 (aarch64_feature_crc): New static.
404 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
405 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
406 * aarch64-asm-2.c: Re-generate.
407 * aarch64-dis-2.c: Ditto.
408 * aarch64-opc-2.c: Ditto.
410 2013-02-27 Alan Modra <amodra@gmail.com>
412 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
413 * rl78-decode.c: Regenerate.
415 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
417 * rl78-decode.opc: Fix encoding of DIVWU insn.
418 * rl78-decode.c: Regenerate.
420 2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
423 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
425 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
426 (cpu_flags): Add CpuSMAP.
428 * i386-opc.h (CpuSMAP): New.
429 (i386_cpu_flags): Add cpusmap.
431 * i386-opc.tbl: Add clac and stac.
433 * i386-init.h: Regenerated.
434 * i386-tbl.h: Likewise.
436 2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
438 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
439 which also makes the disassembler output be in little
440 endian like it should be.
442 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
444 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
446 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
448 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
450 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
451 section disassembled.
453 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
455 * arm-dis.c: Update strht pattern.
457 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
459 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
460 single-float. Disable ll, lld, sc and scd for EE. Disable the
461 trunc.w.s macro for EE.
463 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
464 Andrew Jenner <andrew@codesourcery.com>
466 Based on patches from Altera Corporation.
468 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
470 * Makefile.in: Regenerated.
471 * configure.in: Add case for bfd_nios2_arch.
472 * configure: Regenerated.
473 * disassemble.c (ARCH_nios2): Define.
474 (disassembler): Add case for bfd_arch_nios2.
475 * nios2-dis.c: New file.
476 * nios2-opc.c: New file.
478 2013-02-04 Alan Modra <amodra@gmail.com>
480 * po/POTFILES.in: Regenerate.
481 * rl78-decode.c: Regenerate.
482 * rx-decode.c: Regenerate.
484 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
486 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
487 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
488 * aarch64-asm.c (convert_xtl_to_shll): New function.
489 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
490 calling convert_xtl_to_shll.
491 * aarch64-dis.c (convert_shll_to_xtl): New function.
492 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
493 calling convert_shll_to_xtl.
494 * aarch64-gen.c: Update copyright year.
495 * aarch64-asm-2.c: Re-generate.
496 * aarch64-dis-2.c: Re-generate.
497 * aarch64-opc-2.c: Re-generate.
499 2013-01-24 Nick Clifton <nickc@redhat.com>
501 * v850-dis.c: Add support for e3v5 architecture.
502 * v850-opc.c: Likewise.
504 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
506 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
507 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
508 * aarch64-opc.c (operand_general_constraint_met_p): For
509 AARCH64_MOD_LSL, move the range check on the shift amount before the
510 alignment check; change to call set_sft_amount_out_of_range_error
511 instead of set_imm_out_of_range_error.
512 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
513 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
514 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
517 2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
519 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
521 * i386-init.h: Regenerated.
522 * i386-tbl.h: Likewise.
524 2013-01-15 Nick Clifton <nickc@redhat.com>
526 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
528 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
530 2013-01-14 Will Newton <will.newton@imgtec.com>
532 * metag-dis.c (REG_WIDTH): Increase to 64.
534 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
536 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
537 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
538 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
540 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
541 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
542 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
543 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
545 2013-01-10 Will Newton <will.newton@imgtec.com>
547 * Makefile.am: Add Meta.
548 * configure.in: Add Meta.
549 * disassemble.c: Add Meta support.
550 * metag-dis.c: New file.
551 * Makefile.in: Regenerate.
552 * configure: Regenerate.
554 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
556 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
557 (match_opcode): Rename to cr16_match_opcode.
559 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
561 * mips-dis.c: Add names for CP0 registers of r5900.
562 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
563 instructions sq and lq.
564 Add support for MIPS r5900 CPU.
565 Add support for 128 bit MMI (Multimedia Instructions).
566 Add support for EE instructions (Emotion Engine).
567 Disable unsupported floating point instructions (64 bit and
568 undefined compare operations).
569 Enable instructions of MIPS ISA IV which are supported by r5900.
570 Disable 64 bit co processor instructions.
571 Disable 64 bit multiplication and division instructions.
572 Disable instructions for co-processor 2 and 3, because these are
573 not supported (preparation for later VU0 support (Vector Unit)).
574 Disable cvt.w.s because this behaves like trunc.w.s and the
575 correct execution can't be ensured on r5900.
576 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
577 will confuse less developers and compilers.
579 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
581 * aarch64-opc.c (aarch64_print_operand): Change to print
582 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
584 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
585 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
588 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
590 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
591 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
593 2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
595 * i386-gen.c (process_copyright): Update copyright year to 2013.
597 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
599 * cr16-dis.c (match_opcode,make_instruction): Remove static
601 (dwordU,wordU): Moved typedefs to opcode/cr16.h
602 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
604 For older changes see ChangeLog-2012
606 Copyright (C) 2013 Free Software Foundation, Inc.
608 Copying and distribution of this file, with or without modification,
609 are permitted in any medium without royalty provided the copyright
610 notice and this notice are preserved.
616 version-control: never