1 2020-07-08 Jan Beulich <jbeulich@suse.com>
3 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
4 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
5 (xop_table): Replace operands of 4-operand insns.
6 (OP_REG_VexI4): Move VEX.W based operand swaping here.
8 2020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
10 * arc-opc.c (insert_rbd): New function.
13 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
16 2020-07-07 Jan Beulich <jbeulich@suse.com>
18 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
19 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
20 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
21 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
24 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
25 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
27 * i386-dis-evex-prefix.h: ... here.
29 2020-07-06 Jan Beulich <jbeulich@suse.com>
31 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
32 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
33 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
34 VEX_W_0FXOP_09_83): New enumerators.
35 (xop_table): Reference the above.
36 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
37 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
38 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
39 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
41 2020-07-06 Jan Beulich <jbeulich@suse.com>
43 * i386-dis.c (EVEX_W_0F3838_P_1,
44 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
45 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
46 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
47 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
48 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
49 (putop): Centralize management of last[]. Delete SAVE_LAST.
50 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
51 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
52 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
53 * i386-dis-evex-prefix.h: here.
55 2020-07-06 Jan Beulich <jbeulich@suse.com>
57 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
58 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
59 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
60 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
62 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
63 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
64 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
65 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
66 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
67 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
68 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
69 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
71 * i386-dis-evex-len.h: Adjust comments.
72 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
73 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
74 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
75 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
76 MOD_EVEX_0F385B_P_2_W_1 table entries.
77 * i386-dis-evex-w.h: Reference mod_table[] for
78 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
81 2020-07-06 Jan Beulich <jbeulich@suse.com>
83 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
84 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
86 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
87 Likewise. Mark 256-bit entries invalid.
89 2020-07-06 Jan Beulich <jbeulich@suse.com>
91 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
92 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
93 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
94 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
95 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
96 PREFIX_EVEX_0F382B): Delete.
97 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
98 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
99 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
100 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
101 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
103 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
104 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
105 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
106 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
108 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
109 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
110 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
111 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
112 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
113 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
114 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
115 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
116 PREFIX_EVEX_0F382B): Remove table entries.
117 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
118 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
119 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
121 2020-07-06 Jan Beulich <jbeulich@suse.com>
123 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
124 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
126 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
127 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
128 EVEX_LEN_0F3A01_P_2_W_1 table entries.
129 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
132 2020-07-06 Jan Beulich <jbeulich@suse.com>
134 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
135 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
136 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
137 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
138 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
139 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
140 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
141 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
142 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
145 2020-07-06 Jan Beulich <jbeulich@suse.com>
147 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
148 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
149 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
151 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
153 * i386-dis-evex.h (evex_table): Reference VEX table entry for
155 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
157 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
159 2020-07-06 Jan Beulich <jbeulich@suse.com>
161 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
162 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
163 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
164 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
165 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
166 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
167 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
168 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
169 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
170 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
171 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
172 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
173 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
174 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
175 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
176 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
177 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
178 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
179 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
180 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
181 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
182 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
183 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
184 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
185 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
186 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
187 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
188 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
189 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
190 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
191 (prefix_table): Add EXxEVexR to FMA table entries.
192 (OP_Rounding): Move abort() invocation.
193 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
194 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
195 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
196 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
197 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
198 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
199 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
200 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
201 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
202 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
204 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
205 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
206 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
207 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
208 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
209 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
210 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
211 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
212 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
213 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
214 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
215 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
216 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
217 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
218 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
219 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
220 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
221 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
222 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
223 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
224 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
225 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
226 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
227 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
228 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
229 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
230 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
231 Delete table entries.
232 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
233 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
234 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
237 2020-07-06 Jan Beulich <jbeulich@suse.com>
239 * i386-dis.c (EXqScalarS): Delete.
240 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
241 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
243 2020-07-06 Jan Beulich <jbeulich@suse.com>
245 * i386-dis.c (safe-ctype.h): Include.
246 (EXdScalar, EXqScalar): Delete.
247 (d_scalar_mode, q_scalar_mode): Delete.
248 (prefix_table, vex_len_table): Use EXxmm_md in place of
249 EXdScalar and EXxmm_mq in place of EXqScalar.
250 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
251 d_scalar_mode and q_scalar_mode.
252 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
253 (vmovsd): Use EXxmm_mq.
255 2020-07-06 Yuri Chornoivan <yurchor@ukr.net>
258 * arc-dis.c: Fix spelling mistake.
259 * po/opcodes.pot: Regenerate.
261 2020-07-06 Nick Clifton <nickc@redhat.com>
263 * po/pt_BR.po: Updated Brazilian Portugugese translation.
264 * po/uk.po: Updated Ukranian translation.
266 2020-07-04 Nick Clifton <nickc@redhat.com>
268 * configure: Regenerate.
269 * po/opcodes.pot: Regenerate.
271 2020-07-04 Nick Clifton <nickc@redhat.com>
273 Binutils 2.35 branch created.
275 2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
277 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
278 * i386-opc.h (VexSwapSources): New.
279 (i386_opcode_modifier): Add vexswapsources.
280 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
281 with two source operands swapped.
282 * i386-tbl.h: Regenerated.
284 2020-06-30 Nelson Chu <nelson.chu@sifive.com>
286 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
287 unprivileged CSR can also be initialized.
289 2020-06-29 Alan Modra <amodra@gmail.com>
291 * arm-dis.c: Use C style comments.
292 * cr16-opc.c: Likewise.
293 * ft32-dis.c: Likewise.
294 * moxie-opc.c: Likewise.
295 * tic54x-dis.c: Likewise.
296 * s12z-opc.c: Remove useless comment.
297 * xgate-dis.c: Likewise.
299 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
301 * i386-opc.tbl: Add a blank line.
303 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
305 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
306 (VecSIB128): Renamed to ...
308 (VecSIB256): Renamed to ...
310 (VecSIB512): Renamed to ...
312 (VecSIB): Renamed to ...
314 (i386_opcode_modifier): Replace vecsib with sib.
315 * i386-opc.tbl (VecSIB128): New.
316 (VecSIB256): Likewise.
317 (VecSIB512): Likewise.
318 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
319 and VecSIB512, respectively.
321 2020-06-26 Jan Beulich <jbeulich@suse.com>
323 * i386-dis.c: Adjust description of I macro.
324 (x86_64_table): Drop use of I.
325 (float_mem): Replace use of I.
326 (putop): Remove handling of I. Adjust setting/clearing of "alt".
328 2020-06-26 Jan Beulich <jbeulich@suse.com>
330 * i386-dis.c: (print_insn): Avoid straight assignment to
331 priv.orig_sizeflag when processing -M sub-options.
333 2020-06-25 Jan Beulich <jbeulich@suse.com>
335 * i386-dis.c: Adjust description of J macro.
336 (dis386, x86_64_table, mod_table): Replace J.
337 (putop): Remove handling of J.
339 2020-06-25 Jan Beulich <jbeulich@suse.com>
341 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
343 2020-06-25 Jan Beulich <jbeulich@suse.com>
345 * i386-dis.c: Adjust description of "LQ" macro.
346 (dis386_twobyte): Use LQ for sysret.
347 (putop): Adjust handling of LQ.
349 2020-06-22 Nelson Chu <nelson.chu@sifive.com>
351 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
352 * riscv-dis.c: Include elfxx-riscv.h.
354 2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
356 * i386-dis.c (prefix_table): Revert the last vmgexit change.
358 2020-06-17 Lili Cui <lili.cui@intel.com>
360 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
362 2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
365 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
366 * i386-opc.tbl: Likewise.
367 * i386-tbl.h: Regenerated.
369 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
371 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
373 2020-06-11 Alex Coplan <alex.coplan@arm.com>
375 * aarch64-opc.c (SYSREG): New macro for describing system registers.
387 (SR_ID_PFR2): Likewise.
388 (SR_PROFILE): Likewise.
389 (SR_MEMTAG): Likewise.
390 (SR_SCXTNUM): Likewise.
391 (aarch64_sys_regs): Refactor to store feature information in the table.
392 (aarch64_sys_reg_supported_p): Collapse logic for system registers
393 that now describe their own features.
394 (aarch64_pstatefield_supported_p): Likewise.
396 2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
398 * i386-dis.c (prefix_table): Fix a typo in comments.
400 2020-06-09 Jan Beulich <jbeulich@suse.com>
402 * i386-dis.c (rex_ignored): Delete.
403 (ckprefix): Drop rex_ignored initialization.
404 (get_valid_dis386): Drop setting of rex_ignored.
405 (print_insn): Drop checking of rex_ignored. Don't record data
406 size prefix as used with VEX-and-alike encodings.
408 2020-06-09 Jan Beulich <jbeulich@suse.com>
410 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
411 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
412 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
413 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
414 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
415 VEX_0F12, and VEX_0F16.
416 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
417 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
418 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
419 from movlps and movhlps. New MOD_0F12_PREFIX_2,
420 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
421 MOD_VEX_0F16_PREFIX_2 entries.
423 2020-06-09 Jan Beulich <jbeulich@suse.com>
425 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
426 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
427 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
428 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
429 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
430 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
431 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
432 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
433 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
434 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
435 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
436 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
437 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
438 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
439 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
440 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
441 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
442 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
443 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
444 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
445 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
446 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
447 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
448 EVEX_W_0FC6_P_2): Delete.
449 (print_insn): Add EVEX.W vs embedded prefix consistency check
450 to prefix validation.
451 * i386-dis-evex.h (evex_table): Don't further descend for
452 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
453 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
455 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
456 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
457 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
458 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
459 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
460 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
461 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
462 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
463 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
464 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
465 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
466 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
467 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
468 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
469 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
470 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
471 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
472 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
473 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
474 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
475 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
476 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
477 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
478 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
479 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
480 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
481 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
483 2020-06-09 Jan Beulich <jbeulich@suse.com>
485 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
486 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
487 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
489 (print_insn): Drop pointless check against bad_opcode. Split
490 prefix validation into legacy and VEX-and-alike parts.
491 (putop): Re-work 'X' macro handling.
493 2020-06-09 Jan Beulich <jbeulich@suse.com>
495 * i386-dis.c (MOD_0F51): Rename to ...
496 (MOD_0F50): ... this.
498 2020-06-08 Alex Coplan <alex.coplan@arm.com>
500 * arm-dis.c (arm_opcodes): Add dfb.
501 (thumb32_opcodes): Add dfb.
503 2020-06-08 Jan Beulich <jbeulich@suse.com>
505 * i386-opc.h (reg_entry): Const-qualify reg_name field.
507 2020-06-06 Alan Modra <amodra@gmail.com>
509 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
511 2020-06-05 Alan Modra <amodra@gmail.com>
513 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
514 size is large enough.
516 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
518 * disassemble.c (disassemble_init_for_target): Set endian_code for
520 * bpf-desc.c: Regenerate.
521 * bpf-opc.c: Likewise.
522 * bpf-dis.c: Likewise.
524 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
526 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
527 (cgen_put_insn_value): Likewise.
528 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
529 * cgen-dis.in (print_insn): Likewise.
530 * cgen-ibld.in (insert_1): Likewise.
531 (insert_1): Likewise.
532 (insert_insn_normal): Likewise.
533 (extract_1): Likewise.
534 * bpf-dis.c: Regenerate.
535 * bpf-ibld.c: Likewise.
536 * bpf-ibld.c: Likewise.
537 * cgen-dis.in: Likewise.
538 * cgen-ibld.in: Likewise.
539 * cgen-opc.c: Likewise.
540 * epiphany-dis.c: Likewise.
541 * epiphany-ibld.c: Likewise.
542 * fr30-dis.c: Likewise.
543 * fr30-ibld.c: Likewise.
544 * frv-dis.c: Likewise.
545 * frv-ibld.c: Likewise.
546 * ip2k-dis.c: Likewise.
547 * ip2k-ibld.c: Likewise.
548 * iq2000-dis.c: Likewise.
549 * iq2000-ibld.c: Likewise.
550 * lm32-dis.c: Likewise.
551 * lm32-ibld.c: Likewise.
552 * m32c-dis.c: Likewise.
553 * m32c-ibld.c: Likewise.
554 * m32r-dis.c: Likewise.
555 * m32r-ibld.c: Likewise.
556 * mep-dis.c: Likewise.
557 * mep-ibld.c: Likewise.
558 * mt-dis.c: Likewise.
559 * mt-ibld.c: Likewise.
560 * or1k-dis.c: Likewise.
561 * or1k-ibld.c: Likewise.
562 * xc16x-dis.c: Likewise.
563 * xc16x-ibld.c: Likewise.
564 * xstormy16-dis.c: Likewise.
565 * xstormy16-ibld.c: Likewise.
567 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
569 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
570 (print_insn_): Handle instruction endian.
571 * bpf-dis.c: Regenerate.
572 * bpf-desc.c: Regenerate.
573 * epiphany-dis.c: Likewise.
574 * epiphany-desc.c: Likewise.
575 * fr30-dis.c: Likewise.
576 * fr30-desc.c: Likewise.
577 * frv-dis.c: Likewise.
578 * frv-desc.c: Likewise.
579 * ip2k-dis.c: Likewise.
580 * ip2k-desc.c: Likewise.
581 * iq2000-dis.c: Likewise.
582 * iq2000-desc.c: Likewise.
583 * lm32-dis.c: Likewise.
584 * lm32-desc.c: Likewise.
585 * m32c-dis.c: Likewise.
586 * m32c-desc.c: Likewise.
587 * m32r-dis.c: Likewise.
588 * m32r-desc.c: Likewise.
589 * mep-dis.c: Likewise.
590 * mep-desc.c: Likewise.
591 * mt-dis.c: Likewise.
592 * mt-desc.c: Likewise.
593 * or1k-dis.c: Likewise.
594 * or1k-desc.c: Likewise.
595 * xc16x-dis.c: Likewise.
596 * xc16x-desc.c: Likewise.
597 * xstormy16-dis.c: Likewise.
598 * xstormy16-desc.c: Likewise.
600 2020-06-03 Nick Clifton <nickc@redhat.com>
602 * po/sr.po: Updated Serbian translation.
604 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
606 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
607 (riscv_get_priv_spec_class): Likewise.
609 2020-06-01 Alan Modra <amodra@gmail.com>
611 * bpf-desc.c: Regenerate.
613 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
614 David Faust <david.faust@oracle.com>
616 * bpf-desc.c: Regenerate.
617 * bpf-opc.h: Likewise.
618 * bpf-opc.c: Likewise.
619 * bpf-dis.c: Likewise.
621 2020-05-28 Alan Modra <amodra@gmail.com>
623 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
626 2020-05-28 Alan Modra <amodra@gmail.com>
628 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
630 (print_insn_ns32k): Revert last change.
632 2020-05-28 Nick Clifton <nickc@redhat.com>
634 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
637 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
639 Fix extraction of signed constants in nios2 disassembler (again).
641 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
642 extractions of signed fields.
644 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
646 * s390-opc.txt: Relocate vector load/store instructions with
647 additional alignment parameter and change architecture level
648 constraint from z14 to z13.
650 2020-05-21 Alan Modra <amodra@gmail.com>
652 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
653 * sparc-dis.c: Likewise.
654 * tic4x-dis.c: Likewise.
655 * xtensa-dis.c: Likewise.
656 * bpf-desc.c: Regenerate.
657 * epiphany-desc.c: Regenerate.
658 * fr30-desc.c: Regenerate.
659 * frv-desc.c: Regenerate.
660 * ip2k-desc.c: Regenerate.
661 * iq2000-desc.c: Regenerate.
662 * lm32-desc.c: Regenerate.
663 * m32c-desc.c: Regenerate.
664 * m32r-desc.c: Regenerate.
665 * mep-asm.c: Regenerate.
666 * mep-desc.c: Regenerate.
667 * mt-desc.c: Regenerate.
668 * or1k-desc.c: Regenerate.
669 * xc16x-desc.c: Regenerate.
670 * xstormy16-desc.c: Regenerate.
672 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
674 * riscv-opc.c (riscv_ext_version_table): The table used to store
675 all information about the supported spec and the corresponding ISA
676 versions. Currently, only Zicsr is supported to verify the
677 correctness of Z sub extension settings. Others will be supported
678 in the future patches.
679 (struct isa_spec_t, isa_specs): List for all supported ISA spec
680 classes and the corresponding strings.
681 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
682 spec class by giving a ISA spec string.
683 * riscv-opc.c (struct priv_spec_t): New structure.
684 (struct priv_spec_t priv_specs): List for all supported privilege spec
685 classes and the corresponding strings.
686 (riscv_get_priv_spec_class): New function. Get the corresponding
687 privilege spec class by giving a spec string.
688 (riscv_get_priv_spec_name): New function. Get the corresponding
689 privilege spec string by giving a CSR version class.
690 * riscv-dis.c: Updated since DECLARE_CSR is changed.
691 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
692 according to the chosen version. Build a hash table riscv_csr_hash to
693 store the valid CSR for the chosen pirv verison. Dump the direct
694 CSR address rather than it's name if it is invalid.
695 (parse_riscv_dis_option_without_args): New function. Parse the options
697 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
698 parse the options without arguments first, and then handle the options
699 with arguments. Add the new option -Mpriv-spec, which has argument.
700 * riscv-dis.c (print_riscv_disassembler_options): Add description
701 about the new OBJDUMP option.
703 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
705 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
706 WC values on POWER10 sync, dcbf and wait instructions.
707 (insert_pl, extract_pl): New functions.
708 (L2OPT, LS, WC): Use insert_ls and extract_ls.
709 (LS3): New , 3-bit L for sync.
710 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
711 (SC2, PL): New, 2-bit SC and PL for sync and wait.
712 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
713 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
714 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
715 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
716 <wait>: Enable PL operand on POWER10.
717 <dcbf>: Enable L3OPT operand on POWER10.
718 <sync>: Enable SC2 operand on POWER10.
720 2020-05-19 Stafford Horne <shorne@gmail.com>
723 * or1k-asm.c: Regenerate.
724 * or1k-desc.c: Regenerate.
725 * or1k-desc.h: Regenerate.
726 * or1k-dis.c: Regenerate.
727 * or1k-ibld.c: Regenerate.
728 * or1k-opc.c: Regenerate.
729 * or1k-opc.h: Regenerate.
730 * or1k-opinst.c: Regenerate.
732 2020-05-11 Alan Modra <amodra@gmail.com>
734 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
737 2020-05-11 Alan Modra <amodra@gmail.com>
739 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
740 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
742 2020-05-11 Alan Modra <amodra@gmail.com>
744 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
746 2020-05-11 Alan Modra <amodra@gmail.com>
748 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
749 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
751 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
753 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
756 2020-05-11 Alan Modra <amodra@gmail.com>
758 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
759 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
760 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
761 (prefix_opcodes): Add xxeval.
763 2020-05-11 Alan Modra <amodra@gmail.com>
765 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
766 xxgenpcvwm, xxgenpcvdm.
768 2020-05-11 Alan Modra <amodra@gmail.com>
770 * ppc-opc.c (MP, VXVAM_MASK): Define.
771 (VXVAPS_MASK): Use VXVA_MASK.
772 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
773 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
774 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
775 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
777 2020-05-11 Alan Modra <amodra@gmail.com>
778 Peter Bergner <bergner@linux.ibm.com>
780 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
782 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
783 YMSK2, XA6a, XA6ap, XB6a entries.
784 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
785 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
787 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
788 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
789 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
790 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
791 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
792 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
793 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
794 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
795 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
796 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
797 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
798 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
799 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
800 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
802 2020-05-11 Alan Modra <amodra@gmail.com>
804 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
805 (insert_xts, extract_xts): New functions.
806 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
807 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
808 (VXRC_MASK, VXSH_MASK): Define.
809 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
810 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
811 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
812 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
813 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
814 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
815 xxblendvh, xxblendvw, xxblendvd, xxpermx.
817 2020-05-11 Alan Modra <amodra@gmail.com>
819 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
820 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
821 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
822 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
823 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
825 2020-05-11 Alan Modra <amodra@gmail.com>
827 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
828 (XTP, DQXP, DQXP_MASK): Define.
829 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
830 (prefix_opcodes): Add plxvp and pstxvp.
832 2020-05-11 Alan Modra <amodra@gmail.com>
834 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
835 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
836 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
838 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
840 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
842 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
844 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
846 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
848 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
850 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
852 2020-05-11 Alan Modra <amodra@gmail.com>
854 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
856 2020-05-11 Alan Modra <amodra@gmail.com>
858 * ppc-dis.c (ppc_opts): Add "power10" entry.
859 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
860 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
862 2020-05-11 Nick Clifton <nickc@redhat.com>
864 * po/fr.po: Updated French translation.
866 2020-04-30 Alex Coplan <alex.coplan@arm.com>
868 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
869 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
870 (operand_general_constraint_met_p): validate
871 AARCH64_OPND_UNDEFINED.
872 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
874 * aarch64-asm-2.c: Regenerated.
875 * aarch64-dis-2.c: Regenerated.
876 * aarch64-opc-2.c: Regenerated.
878 2020-04-29 Nick Clifton <nickc@redhat.com>
881 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
884 2020-04-29 Nick Clifton <nickc@redhat.com>
886 * po/sv.po: Updated Swedish translation.
888 2020-04-29 Nick Clifton <nickc@redhat.com>
891 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
892 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
893 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
896 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
899 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
900 cmpi only on m68020up and cpu32.
902 2020-04-20 Sudakshina Das <sudi.das@arm.com>
904 * aarch64-asm.c (aarch64_ins_none): New.
905 * aarch64-asm.h (ins_none): New declaration.
906 * aarch64-dis.c (aarch64_ext_none): New.
907 * aarch64-dis.h (ext_none): New declaration.
908 * aarch64-opc.c (aarch64_print_operand): Update case for
909 AARCH64_OPND_BARRIER_PSB.
910 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
911 (AARCH64_OPERANDS): Update inserter/extracter for
912 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
913 * aarch64-asm-2.c: Regenerated.
914 * aarch64-dis-2.c: Regenerated.
915 * aarch64-opc-2.c: Regenerated.
917 2020-04-20 Sudakshina Das <sudi.das@arm.com>
919 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
920 (aarch64_feature_ras, RAS): Likewise.
921 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
922 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
923 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
924 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
925 * aarch64-asm-2.c: Regenerated.
926 * aarch64-dis-2.c: Regenerated.
927 * aarch64-opc-2.c: Regenerated.
929 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
931 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
932 (print_insn_neon): Support disassembly of conditional
935 2020-02-16 David Faust <david.faust@oracle.com>
937 * bpf-desc.c: Regenerate.
938 * bpf-desc.h: Likewise.
939 * bpf-opc.c: Regenerate.
940 * bpf-opc.h: Likewise.
942 2020-04-07 Lili Cui <lili.cui@intel.com>
944 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
945 (prefix_table): New instructions (see prefixes above).
947 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
948 CPU_ANY_TSXLDTRK_FLAGS.
949 (cpu_flags): Add CpuTSXLDTRK.
950 * i386-opc.h (enum): Add CpuTSXLDTRK.
951 (i386_cpu_flags): Add cputsxldtrk.
952 * i386-opc.tbl: Add XSUSPLDTRK insns.
953 * i386-init.h: Regenerate.
954 * i386-tbl.h: Likewise.
956 2020-04-02 Lili Cui <lili.cui@intel.com>
958 * i386-dis.c (prefix_table): New instructions serialize.
959 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
960 CPU_ANY_SERIALIZE_FLAGS.
961 (cpu_flags): Add CpuSERIALIZE.
962 * i386-opc.h (enum): Add CpuSERIALIZE.
963 (i386_cpu_flags): Add cpuserialize.
964 * i386-opc.tbl: Add SERIALIZE insns.
965 * i386-init.h: Regenerate.
966 * i386-tbl.h: Likewise.
968 2020-03-26 Alan Modra <amodra@gmail.com>
970 * disassemble.h (opcodes_assert): Declare.
971 (OPCODES_ASSERT): Define.
972 * disassemble.c: Don't include assert.h. Include opintl.h.
973 (opcodes_assert): New function.
974 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
975 (bfd_h8_disassemble): Reduce size of data array. Correctly
976 calculate maxlen. Omit insn decoding when insn length exceeds
977 maxlen. Exit from nibble loop when looking for E, before
978 accessing next data byte. Move processing of E outside loop.
979 Replace tests of maxlen in loop with assertions.
981 2020-03-26 Alan Modra <amodra@gmail.com>
983 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
985 2020-03-25 Alan Modra <amodra@gmail.com>
987 * z80-dis.c (suffix): Init mybuf.
989 2020-03-22 Alan Modra <amodra@gmail.com>
991 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
992 successflly read from section.
994 2020-03-22 Alan Modra <amodra@gmail.com>
996 * arc-dis.c (find_format): Use ISO C string concatenation rather
997 than line continuation within a string. Don't access needs_limm
998 before testing opcode != NULL.
1000 2020-03-22 Alan Modra <amodra@gmail.com>
1002 * ns32k-dis.c (print_insn_arg): Update comment.
1003 (print_insn_ns32k): Reduce size of index_offset array, and
1004 initialize, passing -1 to print_insn_arg for args that are not
1005 an index. Don't exit arg loop early. Abort on bad arg number.
1007 2020-03-22 Alan Modra <amodra@gmail.com>
1009 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
1010 * s12z-opc.c: Formatting.
1011 (operands_f): Return an int.
1012 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
1013 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
1014 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
1015 (exg_sex_discrim): Likewise.
1016 (create_immediate_operand, create_bitfield_operand),
1017 (create_register_operand_with_size, create_register_all_operand),
1018 (create_register_all16_operand, create_simple_memory_operand),
1019 (create_memory_operand, create_memory_auto_operand): Don't
1020 segfault on malloc failure.
1021 (z_ext24_decode): Return an int status, negative on fail, zero
1023 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
1024 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
1025 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
1026 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
1027 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1028 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1029 (loop_primitive_decode, shift_decode, psh_pul_decode),
1030 (bit_field_decode): Similarly.
1031 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
1032 to return value, update callers.
1033 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1034 Don't segfault on NULL operand.
1035 (decode_operation): Return OP_INVALID on first fail.
1036 (decode_s12z): Check all reads, returning -1 on fail.
1038 2020-03-20 Alan Modra <amodra@gmail.com>
1040 * metag-dis.c (print_insn_metag): Don't ignore status from
1043 2020-03-20 Alan Modra <amodra@gmail.com>
1045 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1046 Initialize parts of buffer not written when handling a possible
1047 2-byte insn at end of section. Don't attempt decoding of such
1048 an insn by the 4-byte machinery.
1050 2020-03-20 Alan Modra <amodra@gmail.com>
1052 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1053 partially filled buffer. Prevent lookup of 4-byte insns when
1054 only VLE 2-byte insns are possible due to section size. Print
1055 ".word" rather than ".long" for 2-byte leftovers.
1057 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
1060 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1062 2020-03-13 Jan Beulich <jbeulich@suse.com>
1064 * i386-dis.c (X86_64_0D): Rename to ...
1065 (X86_64_0E): ... this.
1067 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
1069 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1070 * Makefile.in: Regenerated.
1072 2020-03-09 Jan Beulich <jbeulich@suse.com>
1074 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
1076 * i386-tbl.h: Re-generate.
1078 2020-03-09 Jan Beulich <jbeulich@suse.com>
1080 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1081 vprot*, vpsha*, and vpshl*.
1082 * i386-tbl.h: Re-generate.
1084 2020-03-09 Jan Beulich <jbeulich@suse.com>
1086 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1087 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1088 * i386-tbl.h: Re-generate.
1090 2020-03-09 Jan Beulich <jbeulich@suse.com>
1092 * i386-gen.c (set_bitfield): Ignore zero-length field names.
1093 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1094 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1095 * i386-tbl.h: Re-generate.
1097 2020-03-09 Jan Beulich <jbeulich@suse.com>
1099 * i386-gen.c (struct template_arg, struct template_instance,
1100 struct template_param, struct template, templates,
1101 parse_template, expand_templates): New.
1102 (process_i386_opcodes): Various local variables moved to
1103 expand_templates. Call parse_template and expand_templates.
1104 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1105 * i386-tbl.h: Re-generate.
1107 2020-03-06 Jan Beulich <jbeulich@suse.com>
1109 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1110 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1111 register and memory source templates. Replace VexW= by VexW*
1113 * i386-tbl.h: Re-generate.
1115 2020-03-06 Jan Beulich <jbeulich@suse.com>
1117 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1118 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1119 * i386-tbl.h: Re-generate.
1121 2020-03-06 Jan Beulich <jbeulich@suse.com>
1123 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1124 * i386-tbl.h: Re-generate.
1126 2020-03-06 Jan Beulich <jbeulich@suse.com>
1128 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1129 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1130 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1131 VexW0 on SSE2AVX variants.
1132 (vmovq): Drop NoRex64 from XMM/XMM variants.
1133 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1134 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1135 applicable use VexW0.
1136 * i386-tbl.h: Re-generate.
1138 2020-03-06 Jan Beulich <jbeulich@suse.com>
1140 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1141 * i386-opc.h (Rex64): Delete.
1142 (struct i386_opcode_modifier): Remove rex64 field.
1143 * i386-opc.tbl (crc32): Drop Rex64.
1144 Replace Rex64 with Size64 everywhere else.
1145 * i386-tbl.h: Re-generate.
1147 2020-03-06 Jan Beulich <jbeulich@suse.com>
1149 * i386-dis.c (OP_E_memory): Exclude recording of used address
1150 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1151 addressed memory operands for MPX insns.
1153 2020-03-06 Jan Beulich <jbeulich@suse.com>
1155 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1156 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1157 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1158 (ptwrite): Split into non-64-bit and 64-bit forms.
1159 * i386-tbl.h: Re-generate.
1161 2020-03-06 Jan Beulich <jbeulich@suse.com>
1163 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1165 * i386-tbl.h: Re-generate.
1167 2020-03-04 Jan Beulich <jbeulich@suse.com>
1169 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1170 (prefix_table): Move vmmcall here. Add vmgexit.
1171 (rm_table): Replace vmmcall entry by prefix_table[] escape.
1172 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1173 (cpu_flags): Add CpuSEV_ES entry.
1174 * i386-opc.h (CpuSEV_ES): New.
1175 (union i386_cpu_flags): Add cpusev_es field.
1176 * i386-opc.tbl (vmgexit): New.
1177 * i386-init.h, i386-tbl.h: Re-generate.
1179 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1181 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1183 * i386-opc.h (IGNORESIZE): New.
1184 (DEFAULTSIZE): Likewise.
1185 (IgnoreSize): Removed.
1186 (DefaultSize): Likewise.
1187 (MnemonicSize): New.
1188 (i386_opcode_modifier): Replace ignoresize/defaultsize with
1190 * i386-opc.tbl (IgnoreSize): New.
1191 (DefaultSize): Likewise.
1192 * i386-tbl.h: Regenerated.
1194 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1197 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
1200 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1203 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
1204 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
1205 * i386-tbl.h: Regenerated.
1207 2020-02-26 Alan Modra <amodra@gmail.com>
1209 * aarch64-asm.c: Indent labels correctly.
1210 * aarch64-dis.c: Likewise.
1211 * aarch64-gen.c: Likewise.
1212 * aarch64-opc.c: Likewise.
1213 * alpha-dis.c: Likewise.
1214 * i386-dis.c: Likewise.
1215 * nds32-asm.c: Likewise.
1216 * nfp-dis.c: Likewise.
1217 * visium-dis.c: Likewise.
1219 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
1221 * arc-regs.h (int_vector_base): Make it available for all ARC
1224 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
1226 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
1229 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
1231 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
1232 c.mv/c.li if rs1 is zero.
1234 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
1236 * i386-gen.c (cpu_flag_init): Replace CpuABM with
1237 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
1239 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
1240 * i386-opc.h (CpuABM): Removed.
1242 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
1243 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
1244 popcnt. Remove CpuABM from lzcnt.
1245 * i386-init.h: Regenerated.
1246 * i386-tbl.h: Likewise.
1248 2020-02-17 Jan Beulich <jbeulich@suse.com>
1250 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
1251 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
1252 VexW1 instead of open-coding them.
1253 * i386-tbl.h: Re-generate.
1255 2020-02-17 Jan Beulich <jbeulich@suse.com>
1257 * i386-opc.tbl (AddrPrefixOpReg): Define.
1258 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
1259 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
1260 templates. Drop NoRex64.
1261 * i386-tbl.h: Re-generate.
1263 2020-02-17 Jan Beulich <jbeulich@suse.com>
1266 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1267 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
1268 into Intel syntax instance (with Unpsecified) and AT&T one
1270 (vcvtneps2bf16): Likewise, along with folding the two so far
1272 * i386-tbl.h: Re-generate.
1274 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1276 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1277 CPU_ANY_SSE4A_FLAGS.
1279 2020-02-17 Alan Modra <amodra@gmail.com>
1281 * i386-gen.c (cpu_flag_init): Correct last change.
1283 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1285 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
1288 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
1290 * i386-opc.tbl (movsx): Remove Intel syntax comments.
1293 2020-02-14 Jan Beulich <jbeulich@suse.com>
1296 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1297 destination for Cpu64-only variant.
1298 (movzx): Fold patterns.
1299 * i386-tbl.h: Re-generate.
1301 2020-02-13 Jan Beulich <jbeulich@suse.com>
1303 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1304 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1305 CPU_ANY_SSE4_FLAGS entry.
1306 * i386-init.h: Re-generate.
1308 2020-02-12 Jan Beulich <jbeulich@suse.com>
1310 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1311 with Unspecified, making the present one AT&T syntax only.
1312 * i386-tbl.h: Re-generate.
1314 2020-02-12 Jan Beulich <jbeulich@suse.com>
1316 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1317 * i386-tbl.h: Re-generate.
1319 2020-02-12 Jan Beulich <jbeulich@suse.com>
1322 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1323 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1324 Amd64 and Intel64 templates.
1325 (call, jmp): Likewise for far indirect variants. Dro
1327 * i386-tbl.h: Re-generate.
1329 2020-02-11 Jan Beulich <jbeulich@suse.com>
1331 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1332 * i386-opc.h (ShortForm): Delete.
1333 (struct i386_opcode_modifier): Remove shortform field.
1334 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1335 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1336 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1337 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1339 * i386-tbl.h: Re-generate.
1341 2020-02-11 Jan Beulich <jbeulich@suse.com>
1343 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1344 fucompi): Drop ShortForm from operand-less templates.
1345 * i386-tbl.h: Re-generate.
1347 2020-02-11 Alan Modra <amodra@gmail.com>
1349 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1350 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1351 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1352 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1353 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1355 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
1357 * arm-dis.c (print_insn_cde): Define 'V' parse character.
1358 (cde_opcodes): Add VCX* instructions.
1360 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
1361 Matthew Malcomson <matthew.malcomson@arm.com>
1363 * arm-dis.c (struct cdeopcode32): New.
1364 (CDE_OPCODE): New macro.
1365 (cde_opcodes): New disassembly table.
1366 (regnames): New option to table.
1367 (cde_coprocs): New global variable.
1368 (print_insn_cde): New
1369 (print_insn_thumb32): Use print_insn_cde.
1370 (parse_arm_disassembler_options): Parse coprocN args.
1372 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
1375 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1377 * i386-opc.h (AMD64): Removed.
1378 (Intel64): Likewose.
1380 (INTEL64): Likewise.
1381 (INTEL64ONLY): Likewise.
1382 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1383 * i386-opc.tbl (Amd64): New.
1384 (Intel64): Likewise.
1385 (Intel64Only): Likewise.
1386 Replace AMD64 with Amd64. Update sysenter/sysenter with
1387 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
1388 * i386-tbl.h: Regenerated.
1390 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
1393 * z80-dis.c: Add support for GBZ80 opcodes.
1395 2020-02-04 Alan Modra <amodra@gmail.com>
1397 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1399 2020-02-03 Alan Modra <amodra@gmail.com>
1401 * m32c-ibld.c: Regenerate.
1403 2020-02-01 Alan Modra <amodra@gmail.com>
1405 * frv-ibld.c: Regenerate.
1407 2020-01-31 Jan Beulich <jbeulich@suse.com>
1409 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1410 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1411 (OP_E_memory): Replace xmm_mdq_mode case label by
1412 vex_scalar_w_dq_mode one.
1413 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1415 2020-01-31 Jan Beulich <jbeulich@suse.com>
1417 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1418 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1419 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1420 (intel_operand_size): Drop vex_w_dq_mode case label.
1422 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
1424 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1425 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1427 2020-01-30 Alan Modra <amodra@gmail.com>
1429 * m32c-ibld.c: Regenerate.
1431 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
1433 * bpf-opc.c: Regenerate.
1435 2020-01-30 Jan Beulich <jbeulich@suse.com>
1437 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1438 (dis386): Use them to replace C2/C3 table entries.
1439 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1440 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1441 ones. Use Size64 instead of DefaultSize on Intel64 ones.
1442 * i386-tbl.h: Re-generate.
1444 2020-01-30 Jan Beulich <jbeulich@suse.com>
1446 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1448 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1450 * i386-tbl.h: Re-generate.
1452 2020-01-30 Alan Modra <amodra@gmail.com>
1454 * tic4x-dis.c (tic4x_dp): Make unsigned.
1456 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
1457 Jan Beulich <jbeulich@suse.com>
1460 * i386-dis.c (MOVSXD_Fixup): New function.
1461 (movsxd_mode): New enum.
1462 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1463 (intel_operand_size): Handle movsxd_mode.
1464 (OP_E_register): Likewise.
1466 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1467 register on movsxd. Add movsxd with 16-bit destination register
1468 for AMD64 and Intel64 ISAs.
1469 * i386-tbl.h: Regenerated.
1471 2020-01-27 Tamar Christina <tamar.christina@arm.com>
1474 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1475 * aarch64-asm-2.c: Regenerate
1476 * aarch64-dis-2.c: Likewise.
1477 * aarch64-opc-2.c: Likewise.
1479 2020-01-21 Jan Beulich <jbeulich@suse.com>
1481 * i386-opc.tbl (sysret): Drop DefaultSize.
1482 * i386-tbl.h: Re-generate.
1484 2020-01-21 Jan Beulich <jbeulich@suse.com>
1486 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1488 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1489 * i386-tbl.h: Re-generate.
1491 2020-01-20 Nick Clifton <nickc@redhat.com>
1493 * po/de.po: Updated German translation.
1494 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1495 * po/uk.po: Updated Ukranian translation.
1497 2020-01-20 Alan Modra <amodra@gmail.com>
1499 * hppa-dis.c (fput_const): Remove useless cast.
1501 2020-01-20 Alan Modra <amodra@gmail.com>
1503 * arm-dis.c (print_insn_arm): Wrap 'T' value.
1505 2020-01-18 Nick Clifton <nickc@redhat.com>
1507 * configure: Regenerate.
1508 * po/opcodes.pot: Regenerate.
1510 2020-01-18 Nick Clifton <nickc@redhat.com>
1512 Binutils 2.34 branch created.
1514 2020-01-17 Christian Biesinger <cbiesinger@google.com>
1516 * opintl.h: Fix spelling error (seperate).
1518 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
1520 * i386-opc.tbl: Add {vex} pseudo prefix.
1521 * i386-tbl.h: Regenerated.
1523 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1526 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1527 (neon_opcodes): Likewise.
1528 (select_arm_features): Make sure we enable MVE bits when selecting
1529 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
1532 2020-01-16 Jan Beulich <jbeulich@suse.com>
1534 * i386-opc.tbl: Drop stale comment from XOP section.
1536 2020-01-16 Jan Beulich <jbeulich@suse.com>
1538 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1539 (extractps): Add VexWIG to SSE2AVX forms.
1540 * i386-tbl.h: Re-generate.
1542 2020-01-16 Jan Beulich <jbeulich@suse.com>
1544 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1545 Size64 from and use VexW1 on SSE2AVX forms.
1546 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1547 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1548 * i386-tbl.h: Re-generate.
1550 2020-01-15 Alan Modra <amodra@gmail.com>
1552 * tic4x-dis.c (tic4x_version): Make unsigned long.
1553 (optab, optab_special, registernames): New file scope vars.
1554 (tic4x_print_register): Set up registernames rather than
1555 malloc'd registertable.
1556 (tic4x_disassemble): Delete optable and optable_special. Use
1557 optab and optab_special instead. Throw away old optab,
1558 optab_special and registernames when info->mach changes.
1560 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
1563 * z80-dis.c (suffix): Use .db instruction to generate double
1566 2020-01-14 Alan Modra <amodra@gmail.com>
1568 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
1569 values to unsigned before shifting.
1571 2020-01-13 Thomas Troeger <tstroege@gmx.de>
1573 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1575 (print_insn_thumb16, print_insn_thumb32): Likewise.
1576 (print_insn): Initialize the insn info.
1577 * i386-dis.c (print_insn): Initialize the insn info fields, and
1580 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1582 * arc-opc.c (C_NE): Make it required.
1584 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1586 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1587 reserved register name.
1589 2020-01-13 Alan Modra <amodra@gmail.com>
1591 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1592 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1594 2020-01-13 Alan Modra <amodra@gmail.com>
1596 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
1597 result of wasm_read_leb128 in a uint64_t and check that bits
1598 are not lost when copying to other locals. Use uint32_t for
1599 most locals. Use PRId64 when printing int64_t.
1601 2020-01-13 Alan Modra <amodra@gmail.com>
1603 * score-dis.c: Formatting.
1604 * score7-dis.c: Formatting.
1606 2020-01-13 Alan Modra <amodra@gmail.com>
1608 * score-dis.c (print_insn_score48): Use unsigned variables for
1609 unsigned values. Don't left shift negative values.
1610 (print_insn_score32): Likewise.
1611 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1613 2020-01-13 Alan Modra <amodra@gmail.com>
1615 * tic4x-dis.c (tic4x_print_register): Remove dead code.
1617 2020-01-13 Alan Modra <amodra@gmail.com>
1619 * fr30-ibld.c: Regenerate.
1621 2020-01-13 Alan Modra <amodra@gmail.com>
1623 * xgate-dis.c (print_insn): Don't left shift signed value.
1624 (ripBits): Formatting, use 1u.
1626 2020-01-10 Alan Modra <amodra@gmail.com>
1628 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1629 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
1631 2020-01-10 Alan Modra <amodra@gmail.com>
1633 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1634 and XRREG value earlier to avoid a shift with negative exponent.
1635 * m10200-dis.c (disassemble): Similarly.
1637 2020-01-09 Nick Clifton <nickc@redhat.com>
1640 * z80-dis.c (ld_ii_ii): Use correct cast.
1642 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1645 * z80-dis.c (ld_ii_ii): Use character constant when checking
1648 2020-01-09 Jan Beulich <jbeulich@suse.com>
1650 * i386-dis.c (SEP_Fixup): New.
1652 (dis386_twobyte): Use it for sysenter/sysexit.
1653 (enum x86_64_isa): Change amd64 enumerator to value 1.
1654 (OP_J): Compare isa64 against intel64 instead of amd64.
1655 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1657 * i386-tbl.h: Re-generate.
1659 2020-01-08 Alan Modra <amodra@gmail.com>
1661 * z8k-dis.c: Include libiberty.h
1662 (instr_data_s): Make max_fetched unsigned.
1663 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1664 Don't exceed byte_info bounds.
1665 (output_instr): Make num_bytes unsigned.
1666 (unpack_instr): Likewise for nibl_count and loop.
1667 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1669 * z8k-opc.h: Regenerate.
1671 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
1673 * arc-tbl.h (llock): Use 'LLOCK' as class.
1675 (scond): Use 'SCOND' as class.
1677 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1680 2020-01-06 Alan Modra <amodra@gmail.com>
1682 * m32c-ibld.c: Regenerate.
1684 2020-01-06 Alan Modra <amodra@gmail.com>
1687 * z80-dis.c (suffix): Don't use a local struct buffer copy.
1688 Peek at next byte to prevent recursion on repeated prefix bytes.
1689 Ensure uninitialised "mybuf" is not accessed.
1690 (print_insn_z80): Don't zero n_fetch and n_used here,..
1691 (print_insn_z80_buf): ..do it here instead.
1693 2020-01-04 Alan Modra <amodra@gmail.com>
1695 * m32r-ibld.c: Regenerate.
1697 2020-01-04 Alan Modra <amodra@gmail.com>
1699 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1701 2020-01-04 Alan Modra <amodra@gmail.com>
1703 * crx-dis.c (match_opcode): Avoid shift left of signed value.
1705 2020-01-04 Alan Modra <amodra@gmail.com>
1707 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1709 2020-01-03 Jan Beulich <jbeulich@suse.com>
1711 * aarch64-tbl.h (aarch64_opcode_table): Use
1712 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1714 2020-01-03 Jan Beulich <jbeulich@suse.com>
1716 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1717 forms of SUDOT and USDOT.
1719 2020-01-03 Jan Beulich <jbeulich@suse.com>
1721 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1723 * opcodes/aarch64-dis-2.c: Re-generate.
1725 2020-01-03 Jan Beulich <jbeulich@suse.com>
1727 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1729 * opcodes/aarch64-dis-2.c: Re-generate.
1731 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
1733 * z80-dis.c: Add support for eZ80 and Z80 instructions.
1735 2020-01-01 Alan Modra <amodra@gmail.com>
1737 Update year range in copyright notice of all files.
1739 For older changes see ChangeLog-2019
1741 Copyright (C) 2020 Free Software Foundation, Inc.
1743 Copying and distribution of this file, with or without modification,
1744 are permitted in any medium without royalty provided the copyright
1745 notice and this notice are preserved.
1751 version-control: never