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1 2011-06-02 Nick Clifton <nickc@redhat.com>
2
3 * arm-dis.c: Fix spelling mistakes.
4 * op/opcodes.pot: Regenerate.
5
6 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
7
8 * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
9 S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type.
10 * s390-opc.txt: Fix cxr instruction type.
11
12 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
13
14 * s390-opc.c: Add new instruction types marking register pair
15 operands.
16 * s390-opc.txt: Match instructions having register pair operands
17 to the new instruction types.
18
19 2011-05-19 Nick Clifton <nickc@redhat.com>
20
21 * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
22 operands.
23
24 2011-05-10 Quentin Neill <quentin.neill@amd.com>
25
26 * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
27 * i386-init.h: Regenerated.
28
29 2011-04-27 Nick Clifton <nickc@redhat.com>
30
31 * po/da.po: Updated Danish translation.
32
33 2011-04-26 Anton Blanchard <anton@samba.org>
34
35 * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
36
37 2011-04-21 DJ Delorie <dj@redhat.com>
38
39 * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
40 * rx-decode.c: Regenerate.
41
42 2011-04-20 H.J. Lu <hongjiu.lu@intel.com>
43
44 * i386-init.h: Regenerated.
45
46 2011-04-19 Quentin Neill <quentin.neill@amd.com>
47
48 * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
49 from bdver1 flags.
50
51 2011-04-13 Nick Clifton <nickc@redhat.com>
52
53 * v850-dis.c (disassemble): Always print a closing square brace if
54 an opening square brace was printed.
55
56 2011-04-12 Nick Clifton <nickc@redhat.com>
57
58 PR binutils/12534
59 * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
60 patterns.
61 (print_insn_thumb32): Handle %L.
62
63 2011-04-11 Julian Brown <julian@codesourcery.com>
64
65 * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
66 (print_insn_thumb32): Add APSR bitmask support.
67
68 2011-04-07 Paul Carroll<pcarroll@codesourcery.com>
69
70 * arm-dis.c (print_insn): init vars moved into private_data structure.
71
72 2011-03-24 Mike Frysinger <vapier@gentoo.org>
73
74 * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
75
76 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
77
78 * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
79 post-increment to support LPM Z+ instruction. Add support for 'E'
80 constraint for DES instruction.
81 (print_insn_avr): Adjust calls to avr_operand. Rename variable.
82
83 2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
84
85 * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
86
87 2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
88
89 * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
90 Use branch types instead.
91 (print_insn): Likewise.
92
93 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
94
95 * mips-opc.c (mips_builtin_opcodes): Correct register use
96 annotation of "alnv.ps".
97
98 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
99
100 * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
101
102 2011-02-22 Mike Frysinger <vapier@gentoo.org>
103
104 * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
105
106 2011-02-22 Mike Frysinger <vapier@gentoo.org>
107
108 * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
109
110 2011-02-19 Mike Frysinger <vapier@gentoo.org>
111
112 * bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and
113 a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
114 av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
115 exception, end_of_registers, msize, memory, bfd_mach.
116 (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
117 LB0REG, LC1REG, LT1REG, LB1REG): Delete
118 (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
119 (get_allreg): Change to new defines. Fallback to abort().
120
121 2011-02-14 Mike Frysinger <vapier@gentoo.org>
122
123 * bfin-dis.c: Add whitespace/parenthesis where needed.
124
125 2011-02-14 Mike Frysinger <vapier@gentoo.org>
126
127 * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
128 than 7.
129
130 2011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
131
132 * configure: Regenerate.
133
134 2011-02-13 Mike Frysinger <vapier@gentoo.org>
135
136 * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
137
138 2011-02-13 Mike Frysinger <vapier@gentoo.org>
139
140 * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output
141 dregs only when P is set, and dregs_lo otherwise.
142
143 2011-02-13 Mike Frysinger <vapier@gentoo.org>
144
145 * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
146
147 2011-02-12 Mike Frysinger <vapier@gentoo.org>
148
149 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
150
151 2011-02-12 Mike Frysinger <vapier@gentoo.org>
152
153 * bfin-dis.c (machine_registers): Delete REG_GP.
154 (reg_names): Delete "GP".
155 (decode_allregs): Change REG_GP to REG_LASTREG.
156
157 2011-02-12 Mike Frysinger <vapier@gentoo.org>
158
159 * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
160 M_IH, M_IU): Delete.
161
162 2011-02-11 Mike Frysinger <vapier@gentoo.org>
163
164 * bfin-dis.c (reg_names): Add const.
165 (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
166 decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
167 decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
168 decode_counters, decode_allregs): Likewise.
169
170 2011-02-09 Michael Snyder <msnyder@vmware.com>
171
172 * i386-dis.c (OP_J): Parenthesize expression to prevent
173 truncated addresses.
174 (print_insn): Fix indentation off-by-one.
175
176 2011-02-01 Nick Clifton <nickc@redhat.com>
177
178 * po/da.po: Updated Danish translation.
179
180 2011-01-21 Dave Murphy <davem@devkitpro.org>
181
182 * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
183
184 2011-01-18 H.J. Lu <hongjiu.lu@intel.com>
185
186 * i386-dis.c (sIbT): New.
187 (b_T_mode): Likewise.
188 (dis386): Replace sIb with sIbT on "pushT".
189 (x86_64_table): Replace sIb with Ib on "aam" and "aad".
190 (OP_sI): Handle b_T_mode. Properly sign-extend byte.
191
192 2011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com>
193
194 * i386-init.h: Regenerated.
195 * i386-tbl.h: Regenerated
196
197 2011-01-17 Quentin Neill <quentin.neill@amd.com>
198
199 * i386-dis.c (REG_XOP_TBM_01): New.
200 (REG_XOP_TBM_02): New.
201 (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
202 (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
203 entries, and add bextr instruction.
204
205 * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
206 (cpu_flags): Add CpuTBM.
207
208 * i386-opc.h (CpuTBM) New.
209 (i386_cpu_flags): Add bit cputbm.
210
211 * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
212 blcs, blsfill, blsic, t1mskc, and tzmsk.
213
214 2011-01-12 DJ Delorie <dj@redhat.com>
215
216 * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
217
218 2011-01-11 Mingjie Xing <mingjie.xing@gmail.com>
219
220 * mips-dis.c (print_insn_args): Adjust the value to print the real
221 offset for "+c" argument.
222
223 2011-01-10 Nick Clifton <nickc@redhat.com>
224
225 * po/da.po: Updated Danish translation.
226
227 2011-01-05 Nathan Sidwell <nathan@codesourcery.com>
228
229 * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
230
231 2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
232
233 * i386-dis.c (REG_VEX_38F3): New.
234 (PREFIX_0FBC): Likewise.
235 (PREFIX_VEX_38F2): Likewise.
236 (PREFIX_VEX_38F3_REG_1): Likewise.
237 (PREFIX_VEX_38F3_REG_2): Likewise.
238 (PREFIX_VEX_38F3_REG_3): Likewise.
239 (PREFIX_VEX_38F7): Likewise.
240 (VEX_LEN_38F2_P_0): Likewise.
241 (VEX_LEN_38F3_R_1_P_0): Likewise.
242 (VEX_LEN_38F3_R_2_P_0): Likewise.
243 (VEX_LEN_38F3_R_3_P_0): Likewise.
244 (VEX_LEN_38F7_P_0): Likewise.
245 (dis386_twobyte): Use PREFIX_0FBC.
246 (reg_table): Add REG_VEX_38F3.
247 (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
248 PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
249 PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
250 (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
251 PREFIX_VEX_38F7.
252 (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
253 VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
254 VEX_LEN_38F7_P_0.
255
256 * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
257 (cpu_flags): Add CpuBMI.
258
259 * i386-opc.h (CpuBMI): New.
260 (i386_cpu_flags): Add cpubmi.
261
262 * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
263 * i386-init.h: Regenerated.
264 * i386-tbl.h: Likewise.
265
266 2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
267
268 * i386-dis.c (VexGdq): New.
269 (OP_VEX): Handle dq_mode.
270
271 2011-01-01 H.J. Lu <hongjiu.lu@intel.com>
272
273 * i386-gen.c (process_copyright): Update copyright to 2011.
274
275 For older changes see ChangeLog-2010
276 \f
277 Local Variables:
278 mode: change-log
279 left-margin: 8
280 fill-column: 74
281 version-control: never
282 End: