1 2018-07-28 John Darrington <john@darrington.wattle.id.au>
3 * s12z-dis.c (bm_decode): Deal with cases where the mode is BM_RESERVED0 or BM_RESERVED1
4 * s12z-dis.c (bm_rel_decode): ditto
5 * s12z-dis.c (bm_n_bytes): ditto
7 2018-07-28 John Darrington <john@darrington.wattle.id.au>
11 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
13 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
14 address with the addr32 prefix and without base nor index
17 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
19 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
20 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
21 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
22 (cpu_flags): Add CpuCMOV and CpuFXSR.
23 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
24 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
25 * i386-init.h: Regenerated.
26 * i386-tbl.h: Likewise.
28 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
30 * arc-regs.h: Update auxiliary registers.
32 2018-08-06 Jan Beulich <jbeulich@suse.com>
34 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
35 (RegIP, RegIZ): Define.
36 * i386-reg.tbl: Adjust comments.
37 (rip): Use Qword instead of BaseIndex. Use RegIP.
38 (eip): Use Dword instead of BaseIndex. Use RegIP.
39 (riz): Add Qword. Use RegIZ.
40 (eiz): Add Dword. Use RegIZ.
41 * i386-tbl.h: Re-generate.
43 2018-08-03 Jan Beulich <jbeulich@suse.com>
45 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
46 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
47 vpmovzxdq, vpmovzxwd): Remove NoRex64.
48 * i386-tbl.h: Re-generate.
50 2018-08-03 Jan Beulich <jbeulich@suse.com>
52 * i386-gen.c (operand_types): Remove Mem field.
53 * i386-opc.h (union i386_operand_type): Remove mem field.
54 * i386-init.h, i386-tbl.h: Re-generate.
56 2018-08-01 Alan Modra <amodra@gmail.com>
58 * po/POTFILES.in: Regenerate.
60 2018-07-31 Nick Clifton <nickc@redhat.com>
62 * po/sv.po: Updated Swedish translation.
64 2018-07-31 Jan Beulich <jbeulich@suse.com>
66 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
67 * i386-init.h, i386-tbl.h: Re-generate.
69 2018-07-31 Jan Beulich <jbeulich@suse.com>
71 * i386-opc.h (ZEROING_MASKING) Rename to ...
72 (DYNAMIC_MASKING): ... this. Adjust comment.
73 * i386-opc.tbl (MaskingMorZ): Define.
74 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
75 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
76 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
77 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
78 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
79 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
80 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
81 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
82 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
84 2018-07-31 Jan Beulich <jbeulich@suse.com>
86 * i386-opc.tbl: Use element rather than vector size for AVX512*
88 * i386-tbl.h: Re-generate.
90 2018-07-31 Jan Beulich <jbeulich@suse.com>
92 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
93 (cpu_flags): Drop CpuVREX.
94 * i386-opc.h (CpuVREX): Delete.
95 (union i386_cpu_flags): Remove cpuvrex.
96 * i386-init.h, i386-tbl.h: Re-generate.
98 2018-07-30 Jim Wilson <jimw@sifive.com>
100 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
102 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
104 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
106 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
107 * Makefile.in: Regenerated.
108 * configure.ac: Add C-SKY.
109 * configure: Regenerated.
110 * csky-dis.c: New file.
111 * csky-opc.h: New file.
112 * disassemble.c (ARCH_csky): Define.
113 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
114 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
116 2018-07-27 Alan Modra <amodra@gmail.com>
118 * ppc-opc.c (insert_sprbat): Correct function parameter and
120 (extract_sprbat): Likewise, variable too.
122 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
123 Alan Modra <amodra@gmail.com>
125 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
126 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
127 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
128 support disjointed BAT.
129 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
130 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
131 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
133 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
134 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
136 * i386-gen.c (adjust_broadcast_modifier): New function.
137 (process_i386_opcode_modifier): Add an argument for operands.
138 Adjust the Broadcast value based on operands.
139 (output_i386_opcode): Pass operand_types to
140 process_i386_opcode_modifier.
141 (process_i386_opcodes): Pass NULL as operands to
142 process_i386_opcode_modifier.
143 * i386-opc.h (BYTE_BROADCAST): New.
144 (WORD_BROADCAST): Likewise.
145 (DWORD_BROADCAST): Likewise.
146 (QWORD_BROADCAST): Likewise.
147 (i386_opcode_modifier): Expand broadcast to 3 bits.
148 * i386-tbl.h: Regenerated.
150 2018-07-24 Alan Modra <amodra@gmail.com>
153 * or1k-desc.h: Regenerate.
155 2018-07-24 Jan Beulich <jbeulich@suse.com>
157 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
158 vcvtusi2ss, and vcvtusi2sd.
159 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
160 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
161 * i386-tbl.h: Re-generate.
163 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
165 * arc-opc.c (extract_w6): Fix extending the sign.
167 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
169 * arc-tbl.h (vewt): Allow it for ARC EM family.
171 2018-07-23 Alan Modra <amodra@gmail.com>
174 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
175 opcode variants for mtspr/mfspr encodings.
177 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
178 Maciej W. Rozycki <macro@mips.com>
180 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
181 loongson3a descriptors.
182 (parse_mips_ase_option): Handle -M loongson-mmi option.
183 (print_mips_disassembler_options): Document -M loongson-mmi.
184 * mips-opc.c (LMMI): New macro.
185 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
188 2018-07-19 Jan Beulich <jbeulich@suse.com>
190 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
191 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
192 IgnoreSize and [XYZ]MMword where applicable.
193 * i386-tbl.h: Re-generate.
195 2018-07-19 Jan Beulich <jbeulich@suse.com>
197 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
198 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
199 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
200 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
201 * i386-tbl.h: Re-generate.
203 2018-07-19 Jan Beulich <jbeulich@suse.com>
205 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
206 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
207 VPCLMULQDQ templates into their respective AVX512VL counterparts
208 where possible, using Disp8ShiftVL and CheckRegSize instead of
209 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
210 * i386-tbl.h: Re-generate.
212 2018-07-19 Jan Beulich <jbeulich@suse.com>
214 * i386-opc.tbl: Fold AVX512DQ templates into their respective
215 AVX512VL counterparts where possible, using Disp8ShiftVL and
216 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
217 IgnoreSize) as appropriate.
218 * i386-tbl.h: Re-generate.
220 2018-07-19 Jan Beulich <jbeulich@suse.com>
222 * i386-opc.tbl: Fold AVX512BW templates into their respective
223 AVX512VL counterparts where possible, using Disp8ShiftVL and
224 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
225 IgnoreSize) as appropriate.
226 * i386-tbl.h: Re-generate.
228 2018-07-19 Jan Beulich <jbeulich@suse.com>
230 * i386-opc.tbl: Fold AVX512CD templates into their respective
231 AVX512VL counterparts where possible, using Disp8ShiftVL and
232 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
233 IgnoreSize) as appropriate.
234 * i386-tbl.h: Re-generate.
236 2018-07-19 Jan Beulich <jbeulich@suse.com>
238 * i386-opc.h (DISP8_SHIFT_VL): New.
239 * i386-opc.tbl (Disp8ShiftVL): Define.
240 (various): Fold AVX512VL templates into their respective
241 AVX512F counterparts where possible, using Disp8ShiftVL and
242 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
243 IgnoreSize) as appropriate.
244 * i386-tbl.h: Re-generate.
246 2018-07-19 Jan Beulich <jbeulich@suse.com>
248 * Makefile.am: Change dependencies and rule for
249 $(srcdir)/i386-init.h.
250 * Makefile.in: Re-generate.
251 * i386-gen.c (process_i386_opcodes): New local variable
252 "marker". Drop opening of input file. Recognize marker and line
254 * i386-opc.tbl (OPCODE_I386_H): Define.
255 (i386-opc.h): Include it.
258 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
261 * i386-opc.h (Byte): Update comments.
270 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
272 * i386-tbl.h: Regenerated.
274 2018-07-12 Sudakshina Das <sudi.das@arm.com>
276 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
277 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
278 * aarch64-asm-2.c: Regenerate.
279 * aarch64-dis-2.c: Regenerate.
280 * aarch64-opc-2.c: Regenerate.
282 2018-07-12 Tamar Christina <tamar.christina@arm.com>
285 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
286 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
287 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
288 sqdmulh, sqrdmulh): Use Em16.
290 2018-07-11 Sudakshina Das <sudi.das@arm.com>
292 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
293 csdb together with them.
294 (thumb32_opcodes): Likewise.
296 2018-07-11 Jan Beulich <jbeulich@suse.com>
298 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
299 requiring 32-bit registers as operands 2 and 3. Improve
301 (mwait, mwaitx): Fold templates. Improve comments.
302 OPERAND_TYPE_INOUTPORTREG.
303 * i386-tbl.h: Re-generate.
305 2018-07-11 Jan Beulich <jbeulich@suse.com>
307 * i386-gen.c (operand_type_init): Remove
308 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
309 OPERAND_TYPE_INOUTPORTREG.
310 * i386-init.h: Re-generate.
312 2018-07-11 Jan Beulich <jbeulich@suse.com>
314 * i386-opc.tbl (wrssd, wrussd): Add Dword.
315 (wrssq, wrussq): Add Qword.
316 * i386-tbl.h: Re-generate.
318 2018-07-11 Jan Beulich <jbeulich@suse.com>
320 * i386-opc.h: Rename OTMax to OTNum.
321 (OTNumOfUints): Adjust calculation.
322 (OTUnused): Directly alias to OTNum.
324 2018-07-09 Maciej W. Rozycki <macro@mips.com>
326 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
328 (lea_reg_xys): Likewise.
329 (print_insn_loop_primitive): Rename `reg' local variable to
332 2018-07-06 Tamar Christina <tamar.christina@arm.com>
335 * aarch64-tbl.h (ldarh): Fix disassembly mask.
337 2018-07-06 Tamar Christina <tamar.christina@arm.com>
340 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
341 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
343 2018-07-02 Maciej W. Rozycki <macro@mips.com>
346 * mips-dis.c (mips_option_arg_t): New enumeration.
347 (mips_options): New variable.
348 (disassembler_options_mips): New function.
349 (print_mips_disassembler_options): Reimplement in terms of
350 `disassembler_options_mips'.
351 * arm-dis.c (disassembler_options_arm): Adapt to using the
352 `disasm_options_and_args_t' structure.
353 * ppc-dis.c (disassembler_options_powerpc): Likewise.
354 * s390-dis.c (disassembler_options_s390): Likewise.
356 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
358 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
360 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
361 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
362 * testsuite/ld-arm/tls-longplt.d: Likewise.
364 2018-06-29 Tamar Christina <tamar.christina@arm.com>
367 * aarch64-asm-2.c: Regenerate.
368 * aarch64-dis-2.c: Likewise.
369 * aarch64-opc-2.c: Likewise.
370 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
371 * aarch64-opc.c (operand_general_constraint_met_p,
372 aarch64_print_operand): Likewise.
373 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
374 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
376 (AARCH64_OPERANDS): Add Em2.
378 2018-06-26 Nick Clifton <nickc@redhat.com>
380 * po/uk.po: Updated Ukranian translation.
381 * po/de.po: Updated German translation.
382 * po/pt_BR.po: Updated Brazilian Portuguese translation.
384 2018-06-26 Nick Clifton <nickc@redhat.com>
386 * nfp-dis.c: Fix spelling mistake.
388 2018-06-24 Nick Clifton <nickc@redhat.com>
390 * configure: Regenerate.
391 * po/opcodes.pot: Regenerate.
393 2018-06-24 Nick Clifton <nickc@redhat.com>
397 2018-06-19 Tamar Christina <tamar.christina@arm.com>
399 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
400 * aarch64-asm-2.c: Regenerate.
401 * aarch64-dis-2.c: Likewise.
403 2018-06-21 Maciej W. Rozycki <macro@mips.com>
405 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
406 `-M ginv' option description.
408 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
411 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
414 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
416 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
417 * configure.ac: Remove AC_PREREQ.
418 * Makefile.in: Re-generate.
419 * aclocal.m4: Re-generate.
420 * configure: Re-generate.
422 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
424 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
425 mips64r6 descriptors.
426 (parse_mips_ase_option): Handle -Mginv option.
427 (print_mips_disassembler_options): Document -Mginv.
428 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
430 (mips_opcodes): Define ginvi and ginvt.
432 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
433 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
435 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
436 * mips-opc.c (CRC, CRC64): New macros.
437 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
438 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
441 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
444 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
445 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
447 2018-06-06 Alan Modra <amodra@gmail.com>
449 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
450 setjmp. Move init for some other vars later too.
452 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
454 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
455 (dis_private): Add new fields for property section tracking.
456 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
457 (xtensa_instruction_fits): New functions.
458 (fetch_data): Bump minimal fetch size to 4.
459 (print_insn_xtensa): Make struct dis_private static.
460 Load and prepare property table on section change.
461 Don't disassemble literals. Don't disassemble instructions that
462 cross property table boundaries.
464 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
466 * configure: Regenerated.
468 2018-06-01 Jan Beulich <jbeulich@suse.com>
470 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
471 * i386-tbl.h: Re-generate.
473 2018-06-01 Jan Beulich <jbeulich@suse.com>
475 * i386-opc.tbl (sldt, str): Add NoRex64.
476 * i386-tbl.h: Re-generate.
478 2018-06-01 Jan Beulich <jbeulich@suse.com>
480 * i386-opc.tbl (invpcid): Add Oword.
481 * i386-tbl.h: Re-generate.
483 2018-06-01 Alan Modra <amodra@gmail.com>
485 * sysdep.h (_bfd_error_handler): Don't declare.
486 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
487 * rl78-decode.opc: Likewise.
488 * msp430-decode.c: Regenerate.
489 * rl78-decode.c: Regenerate.
491 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
493 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
494 * i386-init.h : Regenerated.
496 2018-05-25 Alan Modra <amodra@gmail.com>
498 * Makefile.in: Regenerate.
499 * po/POTFILES.in: Regenerate.
501 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
503 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
504 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
505 (insert_bab, extract_bab, insert_btab, extract_btab,
506 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
507 (BAT, BBA VBA RBS XB6S): Delete macros.
508 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
509 (BB, BD, RBX, XC6): Update for new macros.
510 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
511 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
512 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
513 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
515 2018-05-18 John Darrington <john@darrington.wattle.id.au>
517 * Makefile.am: Add support for s12z architecture.
518 * configure.ac: Likewise.
519 * disassemble.c: Likewise.
520 * disassemble.h: Likewise.
521 * Makefile.in: Regenerate.
522 * configure: Regenerate.
523 * s12z-dis.c: New file.
526 2018-05-18 Alan Modra <amodra@gmail.com>
528 * nfp-dis.c: Don't #include libbfd.h.
529 (init_nfp3200_priv): Use bfd_get_section_contents.
530 (nit_nfp6000_mecsr_sec): Likewise.
532 2018-05-17 Nick Clifton <nickc@redhat.com>
534 * po/zh_CN.po: Updated simplified Chinese translation.
536 2018-05-16 Tamar Christina <tamar.christina@arm.com>
539 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
540 * aarch64-dis-2.c: Regenerate.
542 2018-05-15 Tamar Christina <tamar.christina@arm.com>
545 * aarch64-asm.c (opintl.h): Include.
546 (aarch64_ins_sysreg): Enforce read/write constraints.
547 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
548 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
549 (F_REG_READ, F_REG_WRITE): New.
550 * aarch64-opc.c (aarch64_print_operand): Generate notes for
552 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
553 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
554 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
555 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
556 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
557 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
558 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
559 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
560 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
561 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
562 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
563 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
564 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
565 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
566 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
567 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
568 msr (F_SYS_WRITE), mrs (F_SYS_READ).
570 2018-05-15 Tamar Christina <tamar.christina@arm.com>
573 * aarch64-dis.c (no_notes: New.
574 (parse_aarch64_dis_option): Support notes.
575 (aarch64_decode_insn, print_operands): Likewise.
576 (print_aarch64_disassembler_options): Document notes.
577 * aarch64-opc.c (aarch64_print_operand): Support notes.
579 2018-05-15 Tamar Christina <tamar.christina@arm.com>
582 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
583 and take error struct.
584 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
585 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
586 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
587 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
588 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
589 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
590 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
591 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
592 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
593 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
594 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
595 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
596 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
597 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
598 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
599 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
600 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
601 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
602 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
603 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
604 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
605 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
606 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
607 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
608 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
609 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
610 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
611 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
612 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
613 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
614 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
615 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
616 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
617 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
618 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
619 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
620 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
621 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
622 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
623 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
624 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
625 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
626 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
627 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
628 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
629 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
630 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
631 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
632 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
633 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
634 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
635 (determine_disassembling_preference, aarch64_decode_insn,
636 print_insn_aarch64_word, print_insn_data): Take errors struct.
637 (print_insn_aarch64): Use errors.
638 * aarch64-asm-2.c: Regenerate.
639 * aarch64-dis-2.c: Regenerate.
640 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
641 boolean in aarch64_insert_operan.
642 (print_operand_extractor): Likewise.
643 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
645 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
647 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
649 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
651 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
653 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
655 * cr16-opc.c (cr16_instruction): Comment typo fix.
656 * hppa-dis.c (print_insn_hppa): Likewise.
658 2018-05-08 Jim Wilson <jimw@sifive.com>
660 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
661 (match_c_slli64, match_srxi_as_c_srxi): New.
662 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
663 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
664 <c.slli, c.srli, c.srai>: Use match_s_slli.
665 <c.slli64, c.srli64, c.srai64>: New.
667 2018-05-08 Alan Modra <amodra@gmail.com>
669 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
670 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
671 partition opcode space for index lookup.
673 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
675 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
676 <insn_length>: ...with this. Update usage.
677 Remove duplicate call to *info->memory_error_func.
679 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
680 H.J. Lu <hongjiu.lu@intel.com>
682 * i386-dis.c (Gva): New.
683 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
684 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
685 (prefix_table): New instructions (see prefix above).
686 (mod_table): New instructions (see prefix above).
687 (OP_G): Handle va_mode.
688 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
690 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
691 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
692 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
693 * i386-opc.tbl: Add movidir{i,64b}.
694 * i386-init.h: Regenerated.
695 * i386-tbl.h: Likewise.
697 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
699 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
701 * i386-opc.h (AddrPrefixOp0): Renamed to ...
702 (AddrPrefixOpReg): This.
703 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
704 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
706 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
708 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
709 (vle_num_opcodes): Likewise.
710 (spe2_num_opcodes): Likewise.
711 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
713 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
714 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
717 2018-05-01 Tamar Christina <tamar.christina@arm.com>
719 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
721 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
723 Makefile.am: Added nfp-dis.c.
724 configure.ac: Added bfd_nfp_arch.
725 disassemble.h: Added print_insn_nfp prototype.
726 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
727 nfp-dis.c: New, for NFP support.
728 po/POTFILES.in: Added nfp-dis.c to the list.
729 Makefile.in: Regenerate.
730 configure: Regenerate.
732 2018-04-26 Jan Beulich <jbeulich@suse.com>
734 * i386-opc.tbl: Fold various non-memory operand AVX512VL
735 templates into their base ones.
736 * i386-tlb.h: Re-generate.
738 2018-04-26 Jan Beulich <jbeulich@suse.com>
740 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
741 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
742 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
743 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
744 * i386-init.h: Re-generate.
746 2018-04-26 Jan Beulich <jbeulich@suse.com>
748 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
749 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
750 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
751 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
753 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
755 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
757 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
758 cpuregzmm, and cpuregmask.
759 * i386-init.h: Re-generate.
760 * i386-tbl.h: Re-generate.
762 2018-04-26 Jan Beulich <jbeulich@suse.com>
764 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
765 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
766 * i386-init.h: Re-generate.
768 2018-04-26 Jan Beulich <jbeulich@suse.com>
770 * i386-gen.c (VexImmExt): Delete.
771 * i386-opc.h (VexImmExt, veximmext): Delete.
772 * i386-opc.tbl: Drop all VexImmExt uses.
773 * i386-tlb.h: Re-generate.
775 2018-04-25 Jan Beulich <jbeulich@suse.com>
777 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
779 * i386-tlb.h: Re-generate.
781 2018-04-25 Tamar Christina <tamar.christina@arm.com>
783 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
785 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
787 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
789 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
790 (cpu_flags): Add CpuCLDEMOTE.
791 * i386-init.h: Regenerate.
792 * i386-opc.h (enum): Add CpuCLDEMOTE,
793 (i386_cpu_flags): Add cpucldemote.
794 * i386-opc.tbl: Add cldemote.
795 * i386-tbl.h: Regenerate.
797 2018-04-16 Alan Modra <amodra@gmail.com>
799 * Makefile.am: Remove sh5 and sh64 support.
800 * configure.ac: Likewise.
801 * disassemble.c: Likewise.
802 * disassemble.h: Likewise.
803 * sh-dis.c: Likewise.
804 * sh64-dis.c: Delete.
805 * sh64-opc.c: Delete.
806 * sh64-opc.h: Delete.
807 * Makefile.in: Regenerate.
808 * configure: Regenerate.
809 * po/POTFILES.in: Regenerate.
811 2018-04-16 Alan Modra <amodra@gmail.com>
813 * Makefile.am: Remove w65 support.
814 * configure.ac: Likewise.
815 * disassemble.c: Likewise.
816 * disassemble.h: Likewise.
819 * Makefile.in: Regenerate.
820 * configure: Regenerate.
821 * po/POTFILES.in: Regenerate.
823 2018-04-16 Alan Modra <amodra@gmail.com>
825 * configure.ac: Remove we32k support.
826 * configure: Regenerate.
828 2018-04-16 Alan Modra <amodra@gmail.com>
830 * Makefile.am: Remove m88k support.
831 * configure.ac: Likewise.
832 * disassemble.c: Likewise.
833 * disassemble.h: Likewise.
834 * m88k-dis.c: Delete.
835 * Makefile.in: Regenerate.
836 * configure: Regenerate.
837 * po/POTFILES.in: Regenerate.
839 2018-04-16 Alan Modra <amodra@gmail.com>
841 * Makefile.am: Remove i370 support.
842 * configure.ac: Likewise.
843 * disassemble.c: Likewise.
844 * disassemble.h: Likewise.
845 * i370-dis.c: Delete.
846 * i370-opc.c: Delete.
847 * Makefile.in: Regenerate.
848 * configure: Regenerate.
849 * po/POTFILES.in: Regenerate.
851 2018-04-16 Alan Modra <amodra@gmail.com>
853 * Makefile.am: Remove h8500 support.
854 * configure.ac: Likewise.
855 * disassemble.c: Likewise.
856 * disassemble.h: Likewise.
857 * h8500-dis.c: Delete.
858 * h8500-opc.h: Delete.
859 * Makefile.in: Regenerate.
860 * configure: Regenerate.
861 * po/POTFILES.in: Regenerate.
863 2018-04-16 Alan Modra <amodra@gmail.com>
865 * configure.ac: Remove tahoe support.
866 * configure: Regenerate.
868 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
870 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
872 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
874 * i386-tbl.h: Regenerated.
876 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
878 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
879 PREFIX_MOD_1_0FAE_REG_6.
881 (OP_E_register): Use va_mode.
882 * i386-dis-evex.h (prefix_table):
883 New instructions (see prefixes above).
884 * i386-gen.c (cpu_flag_init): Add WAITPKG.
885 (cpu_flags): Likewise.
886 * i386-opc.h (enum): Likewise.
887 (i386_cpu_flags): Likewise.
888 * i386-opc.tbl: Add umonitor, umwait, tpause.
889 * i386-init.h: Regenerate.
890 * i386-tbl.h: Likewise.
892 2018-04-11 Alan Modra <amodra@gmail.com>
894 * opcodes/i860-dis.c: Delete.
895 * opcodes/i960-dis.c: Delete.
896 * Makefile.am: Remove i860 and i960 support.
897 * configure.ac: Likewise.
898 * disassemble.c: Likewise.
899 * disassemble.h: Likewise.
900 * Makefile.in: Regenerate.
901 * configure: Regenerate.
902 * po/POTFILES.in: Regenerate.
904 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
907 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
909 (print_insn): Clear vex instead of vex.evex.
911 2018-04-04 Nick Clifton <nickc@redhat.com>
913 * po/es.po: Updated Spanish translation.
915 2018-03-28 Jan Beulich <jbeulich@suse.com>
917 * i386-gen.c (opcode_modifiers): Delete VecESize.
918 * i386-opc.h (VecESize): Delete.
919 (struct i386_opcode_modifier): Delete vecesize.
920 * i386-opc.tbl: Drop VecESize.
921 * i386-tlb.h: Re-generate.
923 2018-03-28 Jan Beulich <jbeulich@suse.com>
925 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
926 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
927 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
928 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
929 * i386-tlb.h: Re-generate.
931 2018-03-28 Jan Beulich <jbeulich@suse.com>
933 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
935 * i386-tlb.h: Re-generate.
937 2018-03-28 Jan Beulich <jbeulich@suse.com>
939 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
940 (vex_len_table): Drop Y for vcvt*2si.
941 (putop): Replace plain 'Y' handling by abort().
943 2018-03-28 Nick Clifton <nickc@redhat.com>
946 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
947 instructions with only a base address register.
948 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
949 handle AARHC64_OPND_SVE_ADDR_R.
950 (aarch64_print_operand): Likewise.
951 * aarch64-asm-2.c: Regenerate.
952 * aarch64_dis-2.c: Regenerate.
953 * aarch64-opc-2.c: Regenerate.
955 2018-03-22 Jan Beulich <jbeulich@suse.com>
957 * i386-opc.tbl: Drop VecESize from register only insn forms and
958 memory forms not allowing broadcast.
959 * i386-tlb.h: Re-generate.
961 2018-03-22 Jan Beulich <jbeulich@suse.com>
963 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
964 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
965 sha256*): Drop Disp<N>.
967 2018-03-22 Jan Beulich <jbeulich@suse.com>
969 * i386-dis.c (EbndS, bnd_swap_mode): New.
970 (prefix_table): Use EbndS.
971 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
972 * i386-opc.tbl (bndmov): Move misplaced Load.
973 * i386-tlb.h: Re-generate.
975 2018-03-22 Jan Beulich <jbeulich@suse.com>
977 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
978 templates allowing memory operands and folded ones for register
980 * i386-tlb.h: Re-generate.
982 2018-03-22 Jan Beulich <jbeulich@suse.com>
984 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
985 256-bit templates. Drop redundant leftover Disp<N>.
986 * i386-tlb.h: Re-generate.
988 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
990 * riscv-opc.c (riscv_insn_types): New.
992 2018-03-13 Nick Clifton <nickc@redhat.com>
994 * po/pt_BR.po: Updated Brazilian Portuguese translation.
996 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
998 * i386-opc.tbl: Add Optimize to clr.
999 * i386-tbl.h: Regenerated.
1001 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1003 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1004 * i386-opc.h (OldGcc): Removed.
1005 (i386_opcode_modifier): Remove oldgcc.
1006 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1007 instructions for old (<= 2.8.1) versions of gcc.
1008 * i386-tbl.h: Regenerated.
1010 2018-03-08 Jan Beulich <jbeulich@suse.com>
1012 * i386-opc.h (EVEXDYN): New.
1013 * i386-opc.tbl: Fold various AVX512VL templates.
1014 * i386-tlb.h: Re-generate.
1016 2018-03-08 Jan Beulich <jbeulich@suse.com>
1018 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1019 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1020 vpexpandd, vpexpandq): Fold AFX512VF templates.
1021 * i386-tlb.h: Re-generate.
1023 2018-03-08 Jan Beulich <jbeulich@suse.com>
1025 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1026 Fold 128- and 256-bit VEX-encoded templates.
1027 * i386-tlb.h: Re-generate.
1029 2018-03-08 Jan Beulich <jbeulich@suse.com>
1031 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1032 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1033 vpexpandd, vpexpandq): Fold AVX512F templates.
1034 * i386-tlb.h: Re-generate.
1036 2018-03-08 Jan Beulich <jbeulich@suse.com>
1038 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1039 64-bit templates. Drop Disp<N>.
1040 * i386-tlb.h: Re-generate.
1042 2018-03-08 Jan Beulich <jbeulich@suse.com>
1044 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1045 and 256-bit templates.
1046 * i386-tlb.h: Re-generate.
1048 2018-03-08 Jan Beulich <jbeulich@suse.com>
1050 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1051 * i386-tlb.h: Re-generate.
1053 2018-03-08 Jan Beulich <jbeulich@suse.com>
1055 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1057 * i386-tlb.h: Re-generate.
1059 2018-03-08 Jan Beulich <jbeulich@suse.com>
1061 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1062 * i386-tlb.h: Re-generate.
1064 2018-03-08 Jan Beulich <jbeulich@suse.com>
1066 * i386-gen.c (opcode_modifiers): Delete FloatD.
1067 * i386-opc.h (FloatD): Delete.
1068 (struct i386_opcode_modifier): Delete floatd.
1069 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1071 * i386-tlb.h: Re-generate.
1073 2018-03-08 Jan Beulich <jbeulich@suse.com>
1075 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1077 2018-03-08 Jan Beulich <jbeulich@suse.com>
1079 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1080 * i386-tlb.h: Re-generate.
1082 2018-03-08 Jan Beulich <jbeulich@suse.com>
1084 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1086 * i386-tlb.h: Re-generate.
1088 2018-03-07 Alan Modra <amodra@gmail.com>
1090 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1092 * disassemble.h (print_insn_rs6000): Delete.
1093 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1094 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1095 (print_insn_rs6000): Delete.
1097 2018-03-03 Alan Modra <amodra@gmail.com>
1099 * sysdep.h (opcodes_error_handler): Define.
1100 (_bfd_error_handler): Declare.
1101 * Makefile.am: Remove stray #.
1102 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1104 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1105 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1106 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1107 opcodes_error_handler to print errors. Standardize error messages.
1108 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1109 and include opintl.h.
1110 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1111 * i386-gen.c: Standardize error messages.
1112 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1113 * Makefile.in: Regenerate.
1114 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1115 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1116 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1117 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1118 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1119 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1120 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1121 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1122 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1123 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1124 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1125 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1126 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1128 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1130 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1131 vpsub[bwdq] instructions.
1132 * i386-tbl.h: Regenerated.
1134 2018-03-01 Alan Modra <amodra@gmail.com>
1136 * configure.ac (ALL_LINGUAS): Sort.
1137 * configure: Regenerate.
1139 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1141 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1142 macro by assignements.
1144 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1147 * i386-gen.c (opcode_modifiers): Add Optimize.
1148 * i386-opc.h (Optimize): New enum.
1149 (i386_opcode_modifier): Add optimize.
1150 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1151 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1152 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1153 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1154 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1156 * i386-tbl.h: Regenerated.
1158 2018-02-26 Alan Modra <amodra@gmail.com>
1160 * crx-dis.c (getregliststring): Allocate a large enough buffer
1161 to silence false positive gcc8 warning.
1163 2018-02-22 Shea Levy <shea@shealevy.com>
1165 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1167 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1169 * i386-opc.tbl: Add {rex},
1170 * i386-tbl.h: Regenerated.
1172 2018-02-20 Maciej W. Rozycki <macro@mips.com>
1174 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1175 (mips16_opcodes): Replace `M' with `m' for "restore".
1177 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1179 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1181 2018-02-13 Maciej W. Rozycki <macro@mips.com>
1183 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1184 variable to `function_index'.
1186 2018-02-13 Nick Clifton <nickc@redhat.com>
1189 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1190 about truncation of printing.
1192 2018-02-12 Henry Wong <henry@stuffedcow.net>
1194 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1196 2018-02-05 Nick Clifton <nickc@redhat.com>
1198 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1200 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1202 * i386-dis.c (enum): Add pconfig.
1203 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1204 (cpu_flags): Add CpuPCONFIG.
1205 * i386-opc.h (enum): Add CpuPCONFIG.
1206 (i386_cpu_flags): Add cpupconfig.
1207 * i386-opc.tbl: Add PCONFIG instruction.
1208 * i386-init.h: Regenerate.
1209 * i386-tbl.h: Likewise.
1211 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1213 * i386-dis.c (enum): Add PREFIX_0F09.
1214 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1215 (cpu_flags): Add CpuWBNOINVD.
1216 * i386-opc.h (enum): Add CpuWBNOINVD.
1217 (i386_cpu_flags): Add cpuwbnoinvd.
1218 * i386-opc.tbl: Add WBNOINVD instruction.
1219 * i386-init.h: Regenerate.
1220 * i386-tbl.h: Likewise.
1222 2018-01-17 Jim Wilson <jimw@sifive.com>
1224 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1226 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1228 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1229 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1230 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1231 (cpu_flags): Add CpuIBT, CpuSHSTK.
1232 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1233 (i386_cpu_flags): Add cpuibt, cpushstk.
1234 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1235 * i386-init.h: Regenerate.
1236 * i386-tbl.h: Likewise.
1238 2018-01-16 Nick Clifton <nickc@redhat.com>
1240 * po/pt_BR.po: Updated Brazilian Portugese translation.
1241 * po/de.po: Updated German translation.
1243 2018-01-15 Jim Wilson <jimw@sifive.com>
1245 * riscv-opc.c (match_c_nop): New.
1246 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1248 2018-01-15 Nick Clifton <nickc@redhat.com>
1250 * po/uk.po: Updated Ukranian translation.
1252 2018-01-13 Nick Clifton <nickc@redhat.com>
1254 * po/opcodes.pot: Regenerated.
1256 2018-01-13 Nick Clifton <nickc@redhat.com>
1258 * configure: Regenerate.
1260 2018-01-13 Nick Clifton <nickc@redhat.com>
1262 2.30 branch created.
1264 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1266 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1267 * i386-tbl.h: Regenerate.
1269 2018-01-10 Jan Beulich <jbeulich@suse.com>
1271 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1272 * i386-tbl.h: Re-generate.
1274 2018-01-10 Jan Beulich <jbeulich@suse.com>
1276 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1277 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1278 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1279 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1280 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1281 Disp8MemShift of AVX512VL forms.
1282 * i386-tbl.h: Re-generate.
1284 2018-01-09 Jim Wilson <jimw@sifive.com>
1286 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1287 then the hi_addr value is zero.
1289 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1291 * arm-dis.c (arm_opcodes): Add csdb.
1292 (thumb32_opcodes): Add csdb.
1294 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1296 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1297 * aarch64-asm-2.c: Regenerate.
1298 * aarch64-dis-2.c: Regenerate.
1299 * aarch64-opc-2.c: Regenerate.
1301 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1304 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1305 Remove AVX512 vmovd with 64-bit operands.
1306 * i386-tbl.h: Regenerated.
1308 2018-01-05 Jim Wilson <jimw@sifive.com>
1310 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1313 2018-01-03 Alan Modra <amodra@gmail.com>
1315 Update year range in copyright notice of all files.
1317 2018-01-02 Jan Beulich <jbeulich@suse.com>
1319 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1320 and OPERAND_TYPE_REGZMM entries.
1322 For older changes see ChangeLog-2017
1324 Copyright (C) 2018 Free Software Foundation, Inc.
1326 Copying and distribution of this file, with or without modification,
1327 are permitted in any medium without royalty provided the copyright
1328 notice and this notice are preserved.
1334 version-control: never