opcodes/ChangeLog

   1 2021-03-12  Alan Modra  <amodra@gmail.com>
   2
   3         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
   4
   5 2021-03-11  Jan Beulich  <jbeulich@suse.com>
   6
   7         * i386-dis.c (OP_XMM): Re-order checks.
   8
   9 2021-03-11  Jan Beulich  <jbeulich@suse.com>
  10
  11         * i386-dis.c (putop): Drop need_vex check when also checking
  12         vex.evex.
  13         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
  14         checking vex.b.
  15
  16 2021-03-11  Jan Beulich  <jbeulich@suse.com>
  17
  18         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
  19         checks. Move case label past broadcast check.
  20
  21 2021-03-10  Jan Beulich  <jbeulich@suse.com>
  22
  23         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
  24         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
  25         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
  26         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
  27         EVEX_W_0F38C7_M_0_L_2): Delete.
  28         (REG_EVEX_0F38C7_M_0_L_2): New.
  29         (intel_operand_size): Handle VEX and EVEX the same for
  30         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
  31         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
  32         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
  33         vex_vsib_q_w_d_mode uses.
  34         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
  35         0F38A1, and 0F38A3 entries.
  36         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
  37         entry.
  38         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
  39         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
  40         0F38A3 entries.
  41
  42 2021-03-10  Jan Beulich  <jbeulich@suse.com>
  43
  44         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
  45         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
  46         MOD_VEX_0FXOP_09_12): Rename to ...
  47         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
  48         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
  49         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
  50         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
  51         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
  52         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
  53         (reg_table): Adjust comments.
  54         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
  55         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
  56         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
  57         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
  58         (vex_len_table): Adjust opcode 0A_12 entry.
  59         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
  60         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
  61         (rm_table): Move hreset entry.
  62
  63 2021-03-10  Jan Beulich  <jbeulich@suse.com>
  64
  65         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
  66         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
  67         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
  68         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
  69         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
  70         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
  71         (get_valid_dis386): Also handle 512-bit vector length when
  72         vectoring into vex_len_table[].
  73         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
  74         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
  75         entries.
  76         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
  77         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
  78         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
  79         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
  80         entries.
  81
  82 2021-03-10  Jan Beulich  <jbeulich@suse.com>
  83
  84         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
  85         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
  86         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
  87         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
  88         entries.
  89         * i386-dis-evex-len.h (evex_len_table): Likewise.
  90         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
  91
  92 2021-03-10  Jan Beulich  <jbeulich@suse.com>
  93
  94         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
  95         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
  96         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
  97         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
  98         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
  99         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 100         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 101         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 102         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 103         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 104         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 105         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 106         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 107         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 108         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 109         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 110         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 111         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 112         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 113         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 114         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 115         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 116         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 117         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 118         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 119         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 120         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 121         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 122         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 123         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 124         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 125         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 126         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 127         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 128         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 129         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 130         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 131         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 132         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 133         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 134         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 135         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 136         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 137         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 138         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 139         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 140         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 141         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 142         EVEX_W_0F3A43_L_n): New.
 143         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 144         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 145         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 146         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 147         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 148         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 149         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 150         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 151         0F385B, 0F38C6, and 0F38C7 entries.
 152         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 153         0F38C6 and 0F38C7.
 154         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 155         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 156         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 157         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 158
 159 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 160
 161         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 162         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 163         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 164         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 165         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 166         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 167         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 168         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 169         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 170         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 171         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 172         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 173         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 174         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 175         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 176         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 177         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 178         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 179         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 180         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 181         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 182         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 183         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 184         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 185         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 186         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 187         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 188         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 189         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 190         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 191         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 192         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 193         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 194         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 195         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 196         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 197         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 198         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 199         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 200         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 201         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 202         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 203         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 204         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 205         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 206         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 207         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 208         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 209         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 210         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 211         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 212         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 213         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 214         VEX_W_0F99_P_2_LEN_0): Delete.
 215         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 216         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 217         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 218         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 219         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 220         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 221         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 222         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 223         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 224         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 225         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 226         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 227         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 228         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 229         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 230         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 231         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 232         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 233         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 234         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 235         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 236         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 237         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 238         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 239         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 240         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 241         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 242         (prefix_table): No longer link to vex_len_table[] for opcodes
 243         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 244         0F92, 0F93, 0F98, and 0F99.
 245         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 246         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 247         0F98, and 0F99.
 248         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 249         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 250         0F98, and 0F99.
 251         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 252         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 253         0F98, and 0F99.
 254         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 255         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 256         0F98, and 0F99.
 257
 258 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 259
 260         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 261         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 262         REG_VEX_0F73_M_0 respectively.
 263         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 264         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 265         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 266         MOD_VEX_0F73_REG_7): Delete.
 267         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 268         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 269         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 270         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 271         PREFIX_VEX_0F3AF0_L_0 respectively.
 272         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 273         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 274         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 275         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 276         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 277         VEX_LEN_0F38F7): New.
 278         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 279         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 280         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 281         0F38F3.
 282         (prefix_table): No longer link to vex_len_table[] for opcodes
 283         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 284         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 285         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 286         0F38F6, 0F38F7, and 0F3AF0.
 287         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 288         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 289         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 290         0F73.
 291
 292 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 293
 294         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 295         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 296         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 297         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 298         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 299         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 300         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 301         73.
 302         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 303         0F72, and 0F73.
 304         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 305         0F73.
 306
 307 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 308
 309         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 310         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 311         (reg_table): Don't link to mod_table[] where not needed. Add
 312         PREFIX_IGNORED to nop entries.
 313         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 314         (mod_table): Add nop entries next to prefetch ones. Drop
 315         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 316         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 317         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 318         PREFIX_OPCODE from endbr* entries.
 319         (get_valid_dis386): Also consider entry's name when zapping
 320         vindex.
 321         (print_insn): Handle PREFIX_IGNORED.
 322
 323 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 324
 325         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 326         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 327         element.
 328         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 329         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 330         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 331         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 332         (struct i386_opcode_modifier): Delete notrackprefixok,
 333         islockable, hleprefixok, and repprefixok fields. Add prefixok
 334         field.
 335         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 336         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 337         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 338         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 339         Replace HLEPrefixOk.
 340         * opcodes/i386-tbl.h: Re-generate.
 341
 342 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 343
 344         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 345         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 346         64-bit form.
 347         * opcodes/i386-tbl.h: Re-generate.
 348
 349 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 350
 351         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 352         for {} instead of {0}. Don't look for '0'.
 353         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 354         size specifiers.
 355
 356 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 357
 358         PR 27158
 359         * riscv-dis.c (print_insn_args): Updated encoding macros.
 360         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 361         (match_c_addi16sp): Updated encoding macros.
 362         (match_c_lui): Likewise.
 363         (match_c_lui_with_hint): Likewise.
 364         (match_c_addi4spn): Likewise.
 365         (match_c_slli): Likewise.
 366         (match_slli_as_c_slli): Likewise.
 367         (match_c_slli64): Likewise.
 368         (match_srxi_as_c_srxi): Likewise.
 369         (riscv_insn_types): Added .insn css/cl/cs.
 370
 371 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 372
 373         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 374         (default_priv_spec): Updated type to riscv_spec_class.
 375         (parse_riscv_dis_option): Updated.
 376         * riscv-opc.c: Moved stuff and make the file tidy.
 377
 378 2021-02-17  Alan Modra  <amodra@gmail.com>
 379
 380         * wasm32-dis.c: Include limits.h.
 381         (CHAR_BIT): Provide backup define.
 382         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 383         Correct signed overflow checking.
 384
 385 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 386
 387         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 388         * i386-tbl.h: Re-generate.
 389
 390 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 391
 392         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 393         Oword.
 394         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 395
 396 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 397
 398         * s390-mkopc.c (main): Accept arch14 as cpu string.
 399         * s390-opc.txt: Add new arch14 instructions.
 400
 401 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 402
 403         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 404         favour of LIBINTL.
 405         * configure: Regenerated.
 406
 407 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 408
 409         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 410         * tic54x-opc.c (regs): Rename to ...
 411         (tic54x_regs): ... this.
 412         (mmregs): Rename to ...
 413         (tic54x_mmregs): ... this.
 414         (condition_codes): Rename to ...
 415         (tic54x_condition_codes): ... this.
 416         (cc2_codes): Rename to ...
 417         (tic54x_cc2_codes): ... this.
 418         (cc3_codes): Rename to ...
 419         (tic54x_cc3_codes): ... this.
 420         (status_bits): Rename to ...
 421         (tic54x_status_bits): ... this.
 422         (misc_symbols): Rename to ...
 423         (tic54x_misc_symbols): ... this.
 424
 425 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 426
 427         * riscv-opc.c (MASK_RVB_IMM): Removed.
 428         (riscv_opcodes): Removed zb* instructions.
 429         (riscv_ext_version_table): Removed versions for zb*.
 430
 431 2021-01-26  Alan Modra  <amodra@gmail.com>
 432
 433         * i386-gen.c (parse_template): Ensure entire template_instance
 434         is initialised.
 435
 436 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 437
 438         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 439         (riscv_fpr_names_abi): Likewise.
 440         (riscv_opcodes): Likewise.
 441         (riscv_insn_types): Likewise.
 442
 443 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 444
 445         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 446
 447 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 448
 449         * riscv-dis.c: Comments tidy and improvement.
 450         * riscv-opc.c: Likewise.
 451
 452 2021-01-13  Alan Modra  <amodra@gmail.com>
 453
 454         * Makefile.in: Regenerate.
 455
 456 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 457
 458         PR binutils/26792
 459         * configure.ac: Use GNU_MAKE_JOBSERVER.
 460         * aclocal.m4: Regenerated.
 461         * configure: Likewise.
 462
 463 2021-01-12  Nick Clifton  <nickc@redhat.com>
 464
 465         * po/sr.po: Updated Serbian translation.
 466
 467 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 468
 469         PR ld/27173
 470         * configure: Regenerated.
 471
 472 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 473
 474         * aarch64-asm-2.c: Regenerate.
 475         * aarch64-dis-2.c: Likewise.
 476         * aarch64-opc-2.c: Likewise.
 477         * aarch64-opc.c (aarch64_print_operand):
 478         Delete handling of AARCH64_OPND_CSRE_CSR.
 479         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 480         (CSRE): Likewise.
 481         (_CSRE_INSN): Likewise.
 482         (aarch64_opcode_table): Delete csr.
 483
 484 2021-01-11  Nick Clifton  <nickc@redhat.com>
 485
 486         * po/de.po: Updated German translation.
 487         * po/fr.po: Updated French translation.
 488         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 489         * po/sv.po: Updated Swedish translation.
 490         * po/uk.po: Updated Ukranian translation.
 491
 492 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 493
 494         * configure: Regenerated.
 495
 496 2021-01-09  Nick Clifton  <nickc@redhat.com>
 497
 498         * configure: Regenerate.
 499         * po/opcodes.pot: Regenerate.
 500
 501 2021-01-09  Nick Clifton  <nickc@redhat.com>
 502
 503         * 2.36 release branch crated.
 504
 505 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 506
 507         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 508         (DW, (XRC_MASK): Define.
 509         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 510
 511 2021-01-09  Alan Modra  <amodra@gmail.com>
 512
 513         * configure: Regenerate.
 514
 515 2021-01-08  Nick Clifton  <nickc@redhat.com>
 516
 517         * po/sv.po: Updated Swedish translation.
 518
 519 2021-01-08  Nick Clifton  <nickc@redhat.com>
 520
 521         PR 27129
 522         * aarch64-dis.c (determine_disassembling_preference): Move call to
 523         aarch64_match_operands_constraint outside of the assertion.
 524         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 525         Replace with a return of FALSE.
 526
 527         PR 27139
 528         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 529         core system register.
 530
 531 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 532
 533         * configure: Regenerate.
 534
 535 2021-01-07  Nick Clifton  <nickc@redhat.com>
 536
 537         * po/fr.po: Updated French translation.
 538
 539 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 540
 541         * m68k-opc.c (chkl): Change minimum architecture requirement to
 542         m68020.
 543
 544 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 545
 546         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 547
 548 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 549             Jim Wilson  <jimw@sifive.com>
 550             Andrew Waterman  <andrew@sifive.com>
 551             Maxim Blinov  <maxim.blinov@embecosm.com>
 552             Kito Cheng  <kito.cheng@sifive.com>
 553             Nelson Chu  <nelson.chu@sifive.com>
 554
 555         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
 556         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 557
 558 2021-01-01  Alan Modra  <amodra@gmail.com>
 559
 560         Update year range in copyright notice of all files.
 561
 562 For older changes see ChangeLog-2020
 563 \f
 564 Copyright (C) 2021 Free Software Foundation, Inc.
 565
 566 Copying and distribution of this file, with or without modification,
 567 are permitted in any medium without royalty provided the copyright
 568 notice and this notice are preserved.
 569
 570 Local Variables:
 571 mode: change-log
 572 left-margin: 8
 573 fill-column: 74
 574 version-control: never
 575 End: