1 2020-06-26 Jan Beulich <jbeulich@suse.com>
3 * i386-dis.c: Adjust description of I macro.
4 (x86_64_table): Drop use of I.
5 (float_mem): Replace use of I.
6 (putop): Remove handling of I. Adjust setting/clearing of "alt".
8 2020-06-26 Jan Beulich <jbeulich@suse.com>
10 * i386-dis.c: (print_insn): Avoid straight assignment to
11 priv.orig_sizeflag when processing -M sub-options.
13 2020-06-25 Jan Beulich <jbeulich@suse.com>
15 * i386-dis.c: Adjust description of J macro.
16 (dis386, x86_64_table, mod_table): Replace J.
17 (putop): Remove handling of J.
19 2020-06-25 Jan Beulich <jbeulich@suse.com>
21 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
23 2020-06-25 Jan Beulich <jbeulich@suse.com>
25 * i386-dis.c: Adjust description of "LQ" macro.
26 (dis386_twobyte): Use LQ for sysret.
27 (putop): Adjust handling of LQ.
29 2020-06-22 Nelson Chu <nelson.chu@sifive.com>
31 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
32 * riscv-dis.c: Include elfxx-riscv.h.
34 2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
36 * i386-dis.c (prefix_table): Revert the last vmgexit change.
38 2020-06-17 Lili Cui <lili.cui@intel.com>
40 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
42 2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
45 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
46 * i386-opc.tbl: Likewise.
47 * i386-tbl.h: Regenerated.
49 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
51 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
53 2020-06-11 Alex Coplan <alex.coplan@arm.com>
55 * aarch64-opc.c (SYSREG): New macro for describing system registers.
67 (SR_ID_PFR2): Likewise.
68 (SR_PROFILE): Likewise.
69 (SR_MEMTAG): Likewise.
70 (SR_SCXTNUM): Likewise.
71 (aarch64_sys_regs): Refactor to store feature information in the table.
72 (aarch64_sys_reg_supported_p): Collapse logic for system registers
73 that now describe their own features.
74 (aarch64_pstatefield_supported_p): Likewise.
76 2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
78 * i386-dis.c (prefix_table): Fix a typo in comments.
80 2020-06-09 Jan Beulich <jbeulich@suse.com>
82 * i386-dis.c (rex_ignored): Delete.
83 (ckprefix): Drop rex_ignored initialization.
84 (get_valid_dis386): Drop setting of rex_ignored.
85 (print_insn): Drop checking of rex_ignored. Don't record data
86 size prefix as used with VEX-and-alike encodings.
88 2020-06-09 Jan Beulich <jbeulich@suse.com>
90 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
91 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
92 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
93 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
94 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
95 VEX_0F12, and VEX_0F16.
96 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
97 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
98 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
99 from movlps and movhlps. New MOD_0F12_PREFIX_2,
100 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
101 MOD_VEX_0F16_PREFIX_2 entries.
103 2020-06-09 Jan Beulich <jbeulich@suse.com>
105 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
106 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
107 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
108 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
109 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
110 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
111 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
112 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
113 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
114 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
115 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
116 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
117 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
118 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
119 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
120 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
121 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
122 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
123 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
124 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
125 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
126 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
127 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
128 EVEX_W_0FC6_P_2): Delete.
129 (print_insn): Add EVEX.W vs embedded prefix consistency check
130 to prefix validation.
131 * i386-dis-evex.h (evex_table): Don't further descend for
132 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
133 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
135 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
136 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
137 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
138 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
139 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
140 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
141 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
142 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
143 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
144 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
145 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
146 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
147 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
148 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
149 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
150 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
151 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
152 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
153 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
154 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
155 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
156 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
157 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
158 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
159 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
160 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
161 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
163 2020-06-09 Jan Beulich <jbeulich@suse.com>
165 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
166 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
167 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
169 (print_insn): Drop pointless check against bad_opcode. Split
170 prefix validation into legacy and VEX-and-alike parts.
171 (putop): Re-work 'X' macro handling.
173 2020-06-09 Jan Beulich <jbeulich@suse.com>
175 * i386-dis.c (MOD_0F51): Rename to ...
176 (MOD_0F50): ... this.
178 2020-06-08 Alex Coplan <alex.coplan@arm.com>
180 * arm-dis.c (arm_opcodes): Add dfb.
181 (thumb32_opcodes): Add dfb.
183 2020-06-08 Jan Beulich <jbeulich@suse.com>
185 * i386-opc.h (reg_entry): Const-qualify reg_name field.
187 2020-06-06 Alan Modra <amodra@gmail.com>
189 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
191 2020-06-05 Alan Modra <amodra@gmail.com>
193 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
194 size is large enough.
196 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
198 * disassemble.c (disassemble_init_for_target): Set endian_code for
200 * bpf-desc.c: Regenerate.
201 * bpf-opc.c: Likewise.
202 * bpf-dis.c: Likewise.
204 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
206 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
207 (cgen_put_insn_value): Likewise.
208 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
209 * cgen-dis.in (print_insn): Likewise.
210 * cgen-ibld.in (insert_1): Likewise.
211 (insert_1): Likewise.
212 (insert_insn_normal): Likewise.
213 (extract_1): Likewise.
214 * bpf-dis.c: Regenerate.
215 * bpf-ibld.c: Likewise.
216 * bpf-ibld.c: Likewise.
217 * cgen-dis.in: Likewise.
218 * cgen-ibld.in: Likewise.
219 * cgen-opc.c: Likewise.
220 * epiphany-dis.c: Likewise.
221 * epiphany-ibld.c: Likewise.
222 * fr30-dis.c: Likewise.
223 * fr30-ibld.c: Likewise.
224 * frv-dis.c: Likewise.
225 * frv-ibld.c: Likewise.
226 * ip2k-dis.c: Likewise.
227 * ip2k-ibld.c: Likewise.
228 * iq2000-dis.c: Likewise.
229 * iq2000-ibld.c: Likewise.
230 * lm32-dis.c: Likewise.
231 * lm32-ibld.c: Likewise.
232 * m32c-dis.c: Likewise.
233 * m32c-ibld.c: Likewise.
234 * m32r-dis.c: Likewise.
235 * m32r-ibld.c: Likewise.
236 * mep-dis.c: Likewise.
237 * mep-ibld.c: Likewise.
238 * mt-dis.c: Likewise.
239 * mt-ibld.c: Likewise.
240 * or1k-dis.c: Likewise.
241 * or1k-ibld.c: Likewise.
242 * xc16x-dis.c: Likewise.
243 * xc16x-ibld.c: Likewise.
244 * xstormy16-dis.c: Likewise.
245 * xstormy16-ibld.c: Likewise.
247 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
249 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
250 (print_insn_): Handle instruction endian.
251 * bpf-dis.c: Regenerate.
252 * bpf-desc.c: Regenerate.
253 * epiphany-dis.c: Likewise.
254 * epiphany-desc.c: Likewise.
255 * fr30-dis.c: Likewise.
256 * fr30-desc.c: Likewise.
257 * frv-dis.c: Likewise.
258 * frv-desc.c: Likewise.
259 * ip2k-dis.c: Likewise.
260 * ip2k-desc.c: Likewise.
261 * iq2000-dis.c: Likewise.
262 * iq2000-desc.c: Likewise.
263 * lm32-dis.c: Likewise.
264 * lm32-desc.c: Likewise.
265 * m32c-dis.c: Likewise.
266 * m32c-desc.c: Likewise.
267 * m32r-dis.c: Likewise.
268 * m32r-desc.c: Likewise.
269 * mep-dis.c: Likewise.
270 * mep-desc.c: Likewise.
271 * mt-dis.c: Likewise.
272 * mt-desc.c: Likewise.
273 * or1k-dis.c: Likewise.
274 * or1k-desc.c: Likewise.
275 * xc16x-dis.c: Likewise.
276 * xc16x-desc.c: Likewise.
277 * xstormy16-dis.c: Likewise.
278 * xstormy16-desc.c: Likewise.
280 2020-06-03 Nick Clifton <nickc@redhat.com>
282 * po/sr.po: Updated Serbian translation.
284 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
286 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
287 (riscv_get_priv_spec_class): Likewise.
289 2020-06-01 Alan Modra <amodra@gmail.com>
291 * bpf-desc.c: Regenerate.
293 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
294 David Faust <david.faust@oracle.com>
296 * bpf-desc.c: Regenerate.
297 * bpf-opc.h: Likewise.
298 * bpf-opc.c: Likewise.
299 * bpf-dis.c: Likewise.
301 2020-05-28 Alan Modra <amodra@gmail.com>
303 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
306 2020-05-28 Alan Modra <amodra@gmail.com>
308 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
310 (print_insn_ns32k): Revert last change.
312 2020-05-28 Nick Clifton <nickc@redhat.com>
314 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
317 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
319 Fix extraction of signed constants in nios2 disassembler (again).
321 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
322 extractions of signed fields.
324 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
326 * s390-opc.txt: Relocate vector load/store instructions with
327 additional alignment parameter and change architecture level
328 constraint from z14 to z13.
330 2020-05-21 Alan Modra <amodra@gmail.com>
332 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
333 * sparc-dis.c: Likewise.
334 * tic4x-dis.c: Likewise.
335 * xtensa-dis.c: Likewise.
336 * bpf-desc.c: Regenerate.
337 * epiphany-desc.c: Regenerate.
338 * fr30-desc.c: Regenerate.
339 * frv-desc.c: Regenerate.
340 * ip2k-desc.c: Regenerate.
341 * iq2000-desc.c: Regenerate.
342 * lm32-desc.c: Regenerate.
343 * m32c-desc.c: Regenerate.
344 * m32r-desc.c: Regenerate.
345 * mep-asm.c: Regenerate.
346 * mep-desc.c: Regenerate.
347 * mt-desc.c: Regenerate.
348 * or1k-desc.c: Regenerate.
349 * xc16x-desc.c: Regenerate.
350 * xstormy16-desc.c: Regenerate.
352 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
354 * riscv-opc.c (riscv_ext_version_table): The table used to store
355 all information about the supported spec and the corresponding ISA
356 versions. Currently, only Zicsr is supported to verify the
357 correctness of Z sub extension settings. Others will be supported
358 in the future patches.
359 (struct isa_spec_t, isa_specs): List for all supported ISA spec
360 classes and the corresponding strings.
361 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
362 spec class by giving a ISA spec string.
363 * riscv-opc.c (struct priv_spec_t): New structure.
364 (struct priv_spec_t priv_specs): List for all supported privilege spec
365 classes and the corresponding strings.
366 (riscv_get_priv_spec_class): New function. Get the corresponding
367 privilege spec class by giving a spec string.
368 (riscv_get_priv_spec_name): New function. Get the corresponding
369 privilege spec string by giving a CSR version class.
370 * riscv-dis.c: Updated since DECLARE_CSR is changed.
371 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
372 according to the chosen version. Build a hash table riscv_csr_hash to
373 store the valid CSR for the chosen pirv verison. Dump the direct
374 CSR address rather than it's name if it is invalid.
375 (parse_riscv_dis_option_without_args): New function. Parse the options
377 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
378 parse the options without arguments first, and then handle the options
379 with arguments. Add the new option -Mpriv-spec, which has argument.
380 * riscv-dis.c (print_riscv_disassembler_options): Add description
381 about the new OBJDUMP option.
383 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
385 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
386 WC values on POWER10 sync, dcbf and wait instructions.
387 (insert_pl, extract_pl): New functions.
388 (L2OPT, LS, WC): Use insert_ls and extract_ls.
389 (LS3): New , 3-bit L for sync.
390 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
391 (SC2, PL): New, 2-bit SC and PL for sync and wait.
392 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
393 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
394 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
395 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
396 <wait>: Enable PL operand on POWER10.
397 <dcbf>: Enable L3OPT operand on POWER10.
398 <sync>: Enable SC2 operand on POWER10.
400 2020-05-19 Stafford Horne <shorne@gmail.com>
403 * or1k-asm.c: Regenerate.
404 * or1k-desc.c: Regenerate.
405 * or1k-desc.h: Regenerate.
406 * or1k-dis.c: Regenerate.
407 * or1k-ibld.c: Regenerate.
408 * or1k-opc.c: Regenerate.
409 * or1k-opc.h: Regenerate.
410 * or1k-opinst.c: Regenerate.
412 2020-05-11 Alan Modra <amodra@gmail.com>
414 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
417 2020-05-11 Alan Modra <amodra@gmail.com>
419 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
420 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
422 2020-05-11 Alan Modra <amodra@gmail.com>
424 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
426 2020-05-11 Alan Modra <amodra@gmail.com>
428 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
429 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
431 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
433 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
436 2020-05-11 Alan Modra <amodra@gmail.com>
438 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
439 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
440 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
441 (prefix_opcodes): Add xxeval.
443 2020-05-11 Alan Modra <amodra@gmail.com>
445 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
446 xxgenpcvwm, xxgenpcvdm.
448 2020-05-11 Alan Modra <amodra@gmail.com>
450 * ppc-opc.c (MP, VXVAM_MASK): Define.
451 (VXVAPS_MASK): Use VXVA_MASK.
452 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
453 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
454 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
455 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
457 2020-05-11 Alan Modra <amodra@gmail.com>
458 Peter Bergner <bergner@linux.ibm.com>
460 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
462 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
463 YMSK2, XA6a, XA6ap, XB6a entries.
464 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
465 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
467 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
468 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
469 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
470 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
471 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
472 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
473 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
474 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
475 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
476 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
477 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
478 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
479 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
480 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
482 2020-05-11 Alan Modra <amodra@gmail.com>
484 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
485 (insert_xts, extract_xts): New functions.
486 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
487 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
488 (VXRC_MASK, VXSH_MASK): Define.
489 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
490 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
491 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
492 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
493 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
494 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
495 xxblendvh, xxblendvw, xxblendvd, xxpermx.
497 2020-05-11 Alan Modra <amodra@gmail.com>
499 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
500 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
501 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
502 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
503 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
505 2020-05-11 Alan Modra <amodra@gmail.com>
507 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
508 (XTP, DQXP, DQXP_MASK): Define.
509 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
510 (prefix_opcodes): Add plxvp and pstxvp.
512 2020-05-11 Alan Modra <amodra@gmail.com>
514 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
515 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
516 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
518 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
520 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
522 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
524 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
526 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
528 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
530 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
532 2020-05-11 Alan Modra <amodra@gmail.com>
534 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
536 2020-05-11 Alan Modra <amodra@gmail.com>
538 * ppc-dis.c (ppc_opts): Add "power10" entry.
539 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
540 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
542 2020-05-11 Nick Clifton <nickc@redhat.com>
544 * po/fr.po: Updated French translation.
546 2020-04-30 Alex Coplan <alex.coplan@arm.com>
548 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
549 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
550 (operand_general_constraint_met_p): validate
551 AARCH64_OPND_UNDEFINED.
552 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
554 * aarch64-asm-2.c: Regenerated.
555 * aarch64-dis-2.c: Regenerated.
556 * aarch64-opc-2.c: Regenerated.
558 2020-04-29 Nick Clifton <nickc@redhat.com>
561 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
564 2020-04-29 Nick Clifton <nickc@redhat.com>
566 * po/sv.po: Updated Swedish translation.
568 2020-04-29 Nick Clifton <nickc@redhat.com>
571 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
572 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
573 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
576 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
579 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
580 cmpi only on m68020up and cpu32.
582 2020-04-20 Sudakshina Das <sudi.das@arm.com>
584 * aarch64-asm.c (aarch64_ins_none): New.
585 * aarch64-asm.h (ins_none): New declaration.
586 * aarch64-dis.c (aarch64_ext_none): New.
587 * aarch64-dis.h (ext_none): New declaration.
588 * aarch64-opc.c (aarch64_print_operand): Update case for
589 AARCH64_OPND_BARRIER_PSB.
590 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
591 (AARCH64_OPERANDS): Update inserter/extracter for
592 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
593 * aarch64-asm-2.c: Regenerated.
594 * aarch64-dis-2.c: Regenerated.
595 * aarch64-opc-2.c: Regenerated.
597 2020-04-20 Sudakshina Das <sudi.das@arm.com>
599 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
600 (aarch64_feature_ras, RAS): Likewise.
601 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
602 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
603 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
604 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
605 * aarch64-asm-2.c: Regenerated.
606 * aarch64-dis-2.c: Regenerated.
607 * aarch64-opc-2.c: Regenerated.
609 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
611 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
612 (print_insn_neon): Support disassembly of conditional
615 2020-02-16 David Faust <david.faust@oracle.com>
617 * bpf-desc.c: Regenerate.
618 * bpf-desc.h: Likewise.
619 * bpf-opc.c: Regenerate.
620 * bpf-opc.h: Likewise.
622 2020-04-07 Lili Cui <lili.cui@intel.com>
624 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
625 (prefix_table): New instructions (see prefixes above).
627 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
628 CPU_ANY_TSXLDTRK_FLAGS.
629 (cpu_flags): Add CpuTSXLDTRK.
630 * i386-opc.h (enum): Add CpuTSXLDTRK.
631 (i386_cpu_flags): Add cputsxldtrk.
632 * i386-opc.tbl: Add XSUSPLDTRK insns.
633 * i386-init.h: Regenerate.
634 * i386-tbl.h: Likewise.
636 2020-04-02 Lili Cui <lili.cui@intel.com>
638 * i386-dis.c (prefix_table): New instructions serialize.
639 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
640 CPU_ANY_SERIALIZE_FLAGS.
641 (cpu_flags): Add CpuSERIALIZE.
642 * i386-opc.h (enum): Add CpuSERIALIZE.
643 (i386_cpu_flags): Add cpuserialize.
644 * i386-opc.tbl: Add SERIALIZE insns.
645 * i386-init.h: Regenerate.
646 * i386-tbl.h: Likewise.
648 2020-03-26 Alan Modra <amodra@gmail.com>
650 * disassemble.h (opcodes_assert): Declare.
651 (OPCODES_ASSERT): Define.
652 * disassemble.c: Don't include assert.h. Include opintl.h.
653 (opcodes_assert): New function.
654 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
655 (bfd_h8_disassemble): Reduce size of data array. Correctly
656 calculate maxlen. Omit insn decoding when insn length exceeds
657 maxlen. Exit from nibble loop when looking for E, before
658 accessing next data byte. Move processing of E outside loop.
659 Replace tests of maxlen in loop with assertions.
661 2020-03-26 Alan Modra <amodra@gmail.com>
663 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
665 2020-03-25 Alan Modra <amodra@gmail.com>
667 * z80-dis.c (suffix): Init mybuf.
669 2020-03-22 Alan Modra <amodra@gmail.com>
671 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
672 successflly read from section.
674 2020-03-22 Alan Modra <amodra@gmail.com>
676 * arc-dis.c (find_format): Use ISO C string concatenation rather
677 than line continuation within a string. Don't access needs_limm
678 before testing opcode != NULL.
680 2020-03-22 Alan Modra <amodra@gmail.com>
682 * ns32k-dis.c (print_insn_arg): Update comment.
683 (print_insn_ns32k): Reduce size of index_offset array, and
684 initialize, passing -1 to print_insn_arg for args that are not
685 an index. Don't exit arg loop early. Abort on bad arg number.
687 2020-03-22 Alan Modra <amodra@gmail.com>
689 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
690 * s12z-opc.c: Formatting.
691 (operands_f): Return an int.
692 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
693 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
694 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
695 (exg_sex_discrim): Likewise.
696 (create_immediate_operand, create_bitfield_operand),
697 (create_register_operand_with_size, create_register_all_operand),
698 (create_register_all16_operand, create_simple_memory_operand),
699 (create_memory_operand, create_memory_auto_operand): Don't
700 segfault on malloc failure.
701 (z_ext24_decode): Return an int status, negative on fail, zero
703 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
704 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
705 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
706 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
707 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
708 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
709 (loop_primitive_decode, shift_decode, psh_pul_decode),
710 (bit_field_decode): Similarly.
711 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
712 to return value, update callers.
713 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
714 Don't segfault on NULL operand.
715 (decode_operation): Return OP_INVALID on first fail.
716 (decode_s12z): Check all reads, returning -1 on fail.
718 2020-03-20 Alan Modra <amodra@gmail.com>
720 * metag-dis.c (print_insn_metag): Don't ignore status from
723 2020-03-20 Alan Modra <amodra@gmail.com>
725 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
726 Initialize parts of buffer not written when handling a possible
727 2-byte insn at end of section. Don't attempt decoding of such
728 an insn by the 4-byte machinery.
730 2020-03-20 Alan Modra <amodra@gmail.com>
732 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
733 partially filled buffer. Prevent lookup of 4-byte insns when
734 only VLE 2-byte insns are possible due to section size. Print
735 ".word" rather than ".long" for 2-byte leftovers.
737 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
740 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
742 2020-03-13 Jan Beulich <jbeulich@suse.com>
744 * i386-dis.c (X86_64_0D): Rename to ...
745 (X86_64_0E): ... this.
747 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
749 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
750 * Makefile.in: Regenerated.
752 2020-03-09 Jan Beulich <jbeulich@suse.com>
754 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
756 * i386-tbl.h: Re-generate.
758 2020-03-09 Jan Beulich <jbeulich@suse.com>
760 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
761 vprot*, vpsha*, and vpshl*.
762 * i386-tbl.h: Re-generate.
764 2020-03-09 Jan Beulich <jbeulich@suse.com>
766 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
767 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
768 * i386-tbl.h: Re-generate.
770 2020-03-09 Jan Beulich <jbeulich@suse.com>
772 * i386-gen.c (set_bitfield): Ignore zero-length field names.
773 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
774 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
775 * i386-tbl.h: Re-generate.
777 2020-03-09 Jan Beulich <jbeulich@suse.com>
779 * i386-gen.c (struct template_arg, struct template_instance,
780 struct template_param, struct template, templates,
781 parse_template, expand_templates): New.
782 (process_i386_opcodes): Various local variables moved to
783 expand_templates. Call parse_template and expand_templates.
784 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
785 * i386-tbl.h: Re-generate.
787 2020-03-06 Jan Beulich <jbeulich@suse.com>
789 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
790 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
791 register and memory source templates. Replace VexW= by VexW*
793 * i386-tbl.h: Re-generate.
795 2020-03-06 Jan Beulich <jbeulich@suse.com>
797 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
798 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
799 * i386-tbl.h: Re-generate.
801 2020-03-06 Jan Beulich <jbeulich@suse.com>
803 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
804 * i386-tbl.h: Re-generate.
806 2020-03-06 Jan Beulich <jbeulich@suse.com>
808 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
809 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
810 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
811 VexW0 on SSE2AVX variants.
812 (vmovq): Drop NoRex64 from XMM/XMM variants.
813 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
814 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
815 applicable use VexW0.
816 * i386-tbl.h: Re-generate.
818 2020-03-06 Jan Beulich <jbeulich@suse.com>
820 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
821 * i386-opc.h (Rex64): Delete.
822 (struct i386_opcode_modifier): Remove rex64 field.
823 * i386-opc.tbl (crc32): Drop Rex64.
824 Replace Rex64 with Size64 everywhere else.
825 * i386-tbl.h: Re-generate.
827 2020-03-06 Jan Beulich <jbeulich@suse.com>
829 * i386-dis.c (OP_E_memory): Exclude recording of used address
830 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
831 addressed memory operands for MPX insns.
833 2020-03-06 Jan Beulich <jbeulich@suse.com>
835 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
836 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
837 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
838 (ptwrite): Split into non-64-bit and 64-bit forms.
839 * i386-tbl.h: Re-generate.
841 2020-03-06 Jan Beulich <jbeulich@suse.com>
843 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
845 * i386-tbl.h: Re-generate.
847 2020-03-04 Jan Beulich <jbeulich@suse.com>
849 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
850 (prefix_table): Move vmmcall here. Add vmgexit.
851 (rm_table): Replace vmmcall entry by prefix_table[] escape.
852 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
853 (cpu_flags): Add CpuSEV_ES entry.
854 * i386-opc.h (CpuSEV_ES): New.
855 (union i386_cpu_flags): Add cpusev_es field.
856 * i386-opc.tbl (vmgexit): New.
857 * i386-init.h, i386-tbl.h: Re-generate.
859 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
861 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
863 * i386-opc.h (IGNORESIZE): New.
864 (DEFAULTSIZE): Likewise.
865 (IgnoreSize): Removed.
866 (DefaultSize): Likewise.
868 (i386_opcode_modifier): Replace ignoresize/defaultsize with
870 * i386-opc.tbl (IgnoreSize): New.
871 (DefaultSize): Likewise.
872 * i386-tbl.h: Regenerated.
874 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
877 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
880 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
883 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
884 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
885 * i386-tbl.h: Regenerated.
887 2020-02-26 Alan Modra <amodra@gmail.com>
889 * aarch64-asm.c: Indent labels correctly.
890 * aarch64-dis.c: Likewise.
891 * aarch64-gen.c: Likewise.
892 * aarch64-opc.c: Likewise.
893 * alpha-dis.c: Likewise.
894 * i386-dis.c: Likewise.
895 * nds32-asm.c: Likewise.
896 * nfp-dis.c: Likewise.
897 * visium-dis.c: Likewise.
899 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
901 * arc-regs.h (int_vector_base): Make it available for all ARC
904 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
906 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
909 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
911 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
912 c.mv/c.li if rs1 is zero.
914 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
916 * i386-gen.c (cpu_flag_init): Replace CpuABM with
917 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
919 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
920 * i386-opc.h (CpuABM): Removed.
922 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
923 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
924 popcnt. Remove CpuABM from lzcnt.
925 * i386-init.h: Regenerated.
926 * i386-tbl.h: Likewise.
928 2020-02-17 Jan Beulich <jbeulich@suse.com>
930 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
931 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
932 VexW1 instead of open-coding them.
933 * i386-tbl.h: Re-generate.
935 2020-02-17 Jan Beulich <jbeulich@suse.com>
937 * i386-opc.tbl (AddrPrefixOpReg): Define.
938 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
939 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
940 templates. Drop NoRex64.
941 * i386-tbl.h: Re-generate.
943 2020-02-17 Jan Beulich <jbeulich@suse.com>
946 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
947 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
948 into Intel syntax instance (with Unpsecified) and AT&T one
950 (vcvtneps2bf16): Likewise, along with folding the two so far
952 * i386-tbl.h: Re-generate.
954 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
956 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
959 2020-02-17 Alan Modra <amodra@gmail.com>
961 * i386-gen.c (cpu_flag_init): Correct last change.
963 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
965 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
968 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
970 * i386-opc.tbl (movsx): Remove Intel syntax comments.
973 2020-02-14 Jan Beulich <jbeulich@suse.com>
976 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
977 destination for Cpu64-only variant.
978 (movzx): Fold patterns.
979 * i386-tbl.h: Re-generate.
981 2020-02-13 Jan Beulich <jbeulich@suse.com>
983 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
984 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
985 CPU_ANY_SSE4_FLAGS entry.
986 * i386-init.h: Re-generate.
988 2020-02-12 Jan Beulich <jbeulich@suse.com>
990 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
991 with Unspecified, making the present one AT&T syntax only.
992 * i386-tbl.h: Re-generate.
994 2020-02-12 Jan Beulich <jbeulich@suse.com>
996 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
997 * i386-tbl.h: Re-generate.
999 2020-02-12 Jan Beulich <jbeulich@suse.com>
1002 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1003 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1004 Amd64 and Intel64 templates.
1005 (call, jmp): Likewise for far indirect variants. Dro
1007 * i386-tbl.h: Re-generate.
1009 2020-02-11 Jan Beulich <jbeulich@suse.com>
1011 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1012 * i386-opc.h (ShortForm): Delete.
1013 (struct i386_opcode_modifier): Remove shortform field.
1014 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1015 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1016 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1017 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1019 * i386-tbl.h: Re-generate.
1021 2020-02-11 Jan Beulich <jbeulich@suse.com>
1023 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1024 fucompi): Drop ShortForm from operand-less templates.
1025 * i386-tbl.h: Re-generate.
1027 2020-02-11 Alan Modra <amodra@gmail.com>
1029 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1030 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1031 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1032 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1033 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1035 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
1037 * arm-dis.c (print_insn_cde): Define 'V' parse character.
1038 (cde_opcodes): Add VCX* instructions.
1040 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
1041 Matthew Malcomson <matthew.malcomson@arm.com>
1043 * arm-dis.c (struct cdeopcode32): New.
1044 (CDE_OPCODE): New macro.
1045 (cde_opcodes): New disassembly table.
1046 (regnames): New option to table.
1047 (cde_coprocs): New global variable.
1048 (print_insn_cde): New
1049 (print_insn_thumb32): Use print_insn_cde.
1050 (parse_arm_disassembler_options): Parse coprocN args.
1052 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
1055 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1057 * i386-opc.h (AMD64): Removed.
1058 (Intel64): Likewose.
1060 (INTEL64): Likewise.
1061 (INTEL64ONLY): Likewise.
1062 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1063 * i386-opc.tbl (Amd64): New.
1064 (Intel64): Likewise.
1065 (Intel64Only): Likewise.
1066 Replace AMD64 with Amd64. Update sysenter/sysenter with
1067 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
1068 * i386-tbl.h: Regenerated.
1070 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
1073 * z80-dis.c: Add support for GBZ80 opcodes.
1075 2020-02-04 Alan Modra <amodra@gmail.com>
1077 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1079 2020-02-03 Alan Modra <amodra@gmail.com>
1081 * m32c-ibld.c: Regenerate.
1083 2020-02-01 Alan Modra <amodra@gmail.com>
1085 * frv-ibld.c: Regenerate.
1087 2020-01-31 Jan Beulich <jbeulich@suse.com>
1089 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1090 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1091 (OP_E_memory): Replace xmm_mdq_mode case label by
1092 vex_scalar_w_dq_mode one.
1093 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1095 2020-01-31 Jan Beulich <jbeulich@suse.com>
1097 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1098 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1099 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1100 (intel_operand_size): Drop vex_w_dq_mode case label.
1102 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
1104 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1105 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1107 2020-01-30 Alan Modra <amodra@gmail.com>
1109 * m32c-ibld.c: Regenerate.
1111 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
1113 * bpf-opc.c: Regenerate.
1115 2020-01-30 Jan Beulich <jbeulich@suse.com>
1117 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1118 (dis386): Use them to replace C2/C3 table entries.
1119 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1120 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1121 ones. Use Size64 instead of DefaultSize on Intel64 ones.
1122 * i386-tbl.h: Re-generate.
1124 2020-01-30 Jan Beulich <jbeulich@suse.com>
1126 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1128 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1130 * i386-tbl.h: Re-generate.
1132 2020-01-30 Alan Modra <amodra@gmail.com>
1134 * tic4x-dis.c (tic4x_dp): Make unsigned.
1136 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
1137 Jan Beulich <jbeulich@suse.com>
1140 * i386-dis.c (MOVSXD_Fixup): New function.
1141 (movsxd_mode): New enum.
1142 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1143 (intel_operand_size): Handle movsxd_mode.
1144 (OP_E_register): Likewise.
1146 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1147 register on movsxd. Add movsxd with 16-bit destination register
1148 for AMD64 and Intel64 ISAs.
1149 * i386-tbl.h: Regenerated.
1151 2020-01-27 Tamar Christina <tamar.christina@arm.com>
1154 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1155 * aarch64-asm-2.c: Regenerate
1156 * aarch64-dis-2.c: Likewise.
1157 * aarch64-opc-2.c: Likewise.
1159 2020-01-21 Jan Beulich <jbeulich@suse.com>
1161 * i386-opc.tbl (sysret): Drop DefaultSize.
1162 * i386-tbl.h: Re-generate.
1164 2020-01-21 Jan Beulich <jbeulich@suse.com>
1166 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1168 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1169 * i386-tbl.h: Re-generate.
1171 2020-01-20 Nick Clifton <nickc@redhat.com>
1173 * po/de.po: Updated German translation.
1174 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1175 * po/uk.po: Updated Ukranian translation.
1177 2020-01-20 Alan Modra <amodra@gmail.com>
1179 * hppa-dis.c (fput_const): Remove useless cast.
1181 2020-01-20 Alan Modra <amodra@gmail.com>
1183 * arm-dis.c (print_insn_arm): Wrap 'T' value.
1185 2020-01-18 Nick Clifton <nickc@redhat.com>
1187 * configure: Regenerate.
1188 * po/opcodes.pot: Regenerate.
1190 2020-01-18 Nick Clifton <nickc@redhat.com>
1192 Binutils 2.34 branch created.
1194 2020-01-17 Christian Biesinger <cbiesinger@google.com>
1196 * opintl.h: Fix spelling error (seperate).
1198 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
1200 * i386-opc.tbl: Add {vex} pseudo prefix.
1201 * i386-tbl.h: Regenerated.
1203 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1206 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1207 (neon_opcodes): Likewise.
1208 (select_arm_features): Make sure we enable MVE bits when selecting
1209 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
1212 2020-01-16 Jan Beulich <jbeulich@suse.com>
1214 * i386-opc.tbl: Drop stale comment from XOP section.
1216 2020-01-16 Jan Beulich <jbeulich@suse.com>
1218 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1219 (extractps): Add VexWIG to SSE2AVX forms.
1220 * i386-tbl.h: Re-generate.
1222 2020-01-16 Jan Beulich <jbeulich@suse.com>
1224 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1225 Size64 from and use VexW1 on SSE2AVX forms.
1226 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1227 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1228 * i386-tbl.h: Re-generate.
1230 2020-01-15 Alan Modra <amodra@gmail.com>
1232 * tic4x-dis.c (tic4x_version): Make unsigned long.
1233 (optab, optab_special, registernames): New file scope vars.
1234 (tic4x_print_register): Set up registernames rather than
1235 malloc'd registertable.
1236 (tic4x_disassemble): Delete optable and optable_special. Use
1237 optab and optab_special instead. Throw away old optab,
1238 optab_special and registernames when info->mach changes.
1240 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
1243 * z80-dis.c (suffix): Use .db instruction to generate double
1246 2020-01-14 Alan Modra <amodra@gmail.com>
1248 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
1249 values to unsigned before shifting.
1251 2020-01-13 Thomas Troeger <tstroege@gmx.de>
1253 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1255 (print_insn_thumb16, print_insn_thumb32): Likewise.
1256 (print_insn): Initialize the insn info.
1257 * i386-dis.c (print_insn): Initialize the insn info fields, and
1260 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1262 * arc-opc.c (C_NE): Make it required.
1264 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1266 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1267 reserved register name.
1269 2020-01-13 Alan Modra <amodra@gmail.com>
1271 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1272 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1274 2020-01-13 Alan Modra <amodra@gmail.com>
1276 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
1277 result of wasm_read_leb128 in a uint64_t and check that bits
1278 are not lost when copying to other locals. Use uint32_t for
1279 most locals. Use PRId64 when printing int64_t.
1281 2020-01-13 Alan Modra <amodra@gmail.com>
1283 * score-dis.c: Formatting.
1284 * score7-dis.c: Formatting.
1286 2020-01-13 Alan Modra <amodra@gmail.com>
1288 * score-dis.c (print_insn_score48): Use unsigned variables for
1289 unsigned values. Don't left shift negative values.
1290 (print_insn_score32): Likewise.
1291 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1293 2020-01-13 Alan Modra <amodra@gmail.com>
1295 * tic4x-dis.c (tic4x_print_register): Remove dead code.
1297 2020-01-13 Alan Modra <amodra@gmail.com>
1299 * fr30-ibld.c: Regenerate.
1301 2020-01-13 Alan Modra <amodra@gmail.com>
1303 * xgate-dis.c (print_insn): Don't left shift signed value.
1304 (ripBits): Formatting, use 1u.
1306 2020-01-10 Alan Modra <amodra@gmail.com>
1308 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1309 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
1311 2020-01-10 Alan Modra <amodra@gmail.com>
1313 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1314 and XRREG value earlier to avoid a shift with negative exponent.
1315 * m10200-dis.c (disassemble): Similarly.
1317 2020-01-09 Nick Clifton <nickc@redhat.com>
1320 * z80-dis.c (ld_ii_ii): Use correct cast.
1322 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1325 * z80-dis.c (ld_ii_ii): Use character constant when checking
1328 2020-01-09 Jan Beulich <jbeulich@suse.com>
1330 * i386-dis.c (SEP_Fixup): New.
1332 (dis386_twobyte): Use it for sysenter/sysexit.
1333 (enum x86_64_isa): Change amd64 enumerator to value 1.
1334 (OP_J): Compare isa64 against intel64 instead of amd64.
1335 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1337 * i386-tbl.h: Re-generate.
1339 2020-01-08 Alan Modra <amodra@gmail.com>
1341 * z8k-dis.c: Include libiberty.h
1342 (instr_data_s): Make max_fetched unsigned.
1343 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1344 Don't exceed byte_info bounds.
1345 (output_instr): Make num_bytes unsigned.
1346 (unpack_instr): Likewise for nibl_count and loop.
1347 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1349 * z8k-opc.h: Regenerate.
1351 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
1353 * arc-tbl.h (llock): Use 'LLOCK' as class.
1355 (scond): Use 'SCOND' as class.
1357 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1360 2020-01-06 Alan Modra <amodra@gmail.com>
1362 * m32c-ibld.c: Regenerate.
1364 2020-01-06 Alan Modra <amodra@gmail.com>
1367 * z80-dis.c (suffix): Don't use a local struct buffer copy.
1368 Peek at next byte to prevent recursion on repeated prefix bytes.
1369 Ensure uninitialised "mybuf" is not accessed.
1370 (print_insn_z80): Don't zero n_fetch and n_used here,..
1371 (print_insn_z80_buf): ..do it here instead.
1373 2020-01-04 Alan Modra <amodra@gmail.com>
1375 * m32r-ibld.c: Regenerate.
1377 2020-01-04 Alan Modra <amodra@gmail.com>
1379 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1381 2020-01-04 Alan Modra <amodra@gmail.com>
1383 * crx-dis.c (match_opcode): Avoid shift left of signed value.
1385 2020-01-04 Alan Modra <amodra@gmail.com>
1387 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1389 2020-01-03 Jan Beulich <jbeulich@suse.com>
1391 * aarch64-tbl.h (aarch64_opcode_table): Use
1392 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1394 2020-01-03 Jan Beulich <jbeulich@suse.com>
1396 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1397 forms of SUDOT and USDOT.
1399 2020-01-03 Jan Beulich <jbeulich@suse.com>
1401 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1403 * opcodes/aarch64-dis-2.c: Re-generate.
1405 2020-01-03 Jan Beulich <jbeulich@suse.com>
1407 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1409 * opcodes/aarch64-dis-2.c: Re-generate.
1411 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
1413 * z80-dis.c: Add support for eZ80 and Z80 instructions.
1415 2020-01-01 Alan Modra <amodra@gmail.com>
1417 Update year range in copyright notice of all files.
1419 For older changes see ChangeLog-2019
1421 Copyright (C) 2020 Free Software Foundation, Inc.
1423 Copying and distribution of this file, with or without modification,
1424 are permitted in any medium without royalty provided the copyright
1425 notice and this notice are preserved.
1431 version-control: never