1 2013-05-09 Andrew Pinski <apinski@cavium.com>
3 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
4 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
5 (parse_mips_dis_option): Handle the virt option.
6 (print_insn_args): Handle "+J".
7 (print_mips_disassembler_options): Print out message about virt64.
8 * mips-opc.c (IVIRT): New define.
10 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
11 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
12 Move rfe to the bottom as it conflicts with tlbgp.
14 2013-05-09 Alan Modra <amodra@gmail.com>
16 * ppc-opc.c (extract_vlesi): Properly sign extend.
17 (extract_vlensi): Likewise. Comment reason for setting invalid.
19 2013-05-02 Nick Clifton <nickc@redhat.com>
21 * msp430-dis.c: Add support for MSP430X instructions.
23 2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
25 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
28 2013-04-17 Wei-chen Wang <cole945@gmail.com>
31 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
33 (hash_insns_list): Likewise.
35 2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
37 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
40 2013-04-08 Jan Beulich <jbeulich@suse.com>
42 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
43 * i386-tbl.h: Re-generate.
45 2013-04-06 David S. Miller <davem@davemloft.net>
47 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
48 of an opcode, prefer the one with F_PREFERRED set.
49 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
50 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
51 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
52 mark existing mnenomics as aliases. Add "cc" suffix to edge
53 instructions generating condition codes, mark existing mnenomics
54 as aliases. Add "fp" prefix to VIS compare instructions, mark
55 existing mnenomics as aliases.
57 2013-04-03 Nick Clifton <nickc@redhat.com>
59 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
60 destination address by subtracting the operand from the current
62 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
63 a positive value in the insn.
64 (extract_u16_loop): Do not negate the returned value.
65 (D16_LOOP): Add V850_INVERSE_PCREL flag.
67 (ceilf.sw): Remove duplicate entry.
74 (maddf.s): Restrict to E3V5 architectures.
79 2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
81 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
83 (print_insn): Pass sizeflag to get_sib.
85 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
88 * tic6x-dis.c: Add support for displaying 16-bit insns.
90 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
93 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
94 individual msb and lsb halves in src1 & src2 fields. Discard the
95 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
96 follow what Ti SDK does in that case as any value in the src1
97 field yields the same output with SDK disassembler.
99 2013-03-12 Michael Eager <eager@eagercon.com>
101 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
103 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
105 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
107 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
109 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
111 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
113 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
115 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
117 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
118 (thumb32_opcodes): Likewise.
119 (print_insn_thumb32): Handle 'S' control char.
121 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
123 * lm32-desc.c: Regenerate.
125 2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
127 * i386-reg.tbl (riz): Add RegRex64.
128 * i386-tbl.h: Regenerated.
130 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
132 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
133 (aarch64_feature_crc): New static.
135 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
136 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
137 * aarch64-asm-2.c: Re-generate.
138 * aarch64-dis-2.c: Ditto.
139 * aarch64-opc-2.c: Ditto.
141 2013-02-27 Alan Modra <amodra@gmail.com>
143 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
144 * rl78-decode.c: Regenerate.
146 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
148 * rl78-decode.opc: Fix encoding of DIVWU insn.
149 * rl78-decode.c: Regenerate.
151 2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
154 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
156 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
157 (cpu_flags): Add CpuSMAP.
159 * i386-opc.h (CpuSMAP): New.
160 (i386_cpu_flags): Add cpusmap.
162 * i386-opc.tbl: Add clac and stac.
164 * i386-init.h: Regenerated.
165 * i386-tbl.h: Likewise.
167 2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
169 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
170 which also makes the disassembler output be in little
171 endian like it should be.
173 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
175 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
177 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
179 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
181 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
182 section disassembled.
184 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
186 * arm-dis.c: Update strht pattern.
188 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
190 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
191 single-float. Disable ll, lld, sc and scd for EE. Disable the
192 trunc.w.s macro for EE.
194 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
195 Andrew Jenner <andrew@codesourcery.com>
197 Based on patches from Altera Corporation.
199 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
201 * Makefile.in: Regenerated.
202 * configure.in: Add case for bfd_nios2_arch.
203 * configure: Regenerated.
204 * disassemble.c (ARCH_nios2): Define.
205 (disassembler): Add case for bfd_arch_nios2.
206 * nios2-dis.c: New file.
207 * nios2-opc.c: New file.
209 2013-02-04 Alan Modra <amodra@gmail.com>
211 * po/POTFILES.in: Regenerate.
212 * rl78-decode.c: Regenerate.
213 * rx-decode.c: Regenerate.
215 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
217 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
218 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
219 * aarch64-asm.c (convert_xtl_to_shll): New function.
220 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
221 calling convert_xtl_to_shll.
222 * aarch64-dis.c (convert_shll_to_xtl): New function.
223 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
224 calling convert_shll_to_xtl.
225 * aarch64-gen.c: Update copyright year.
226 * aarch64-asm-2.c: Re-generate.
227 * aarch64-dis-2.c: Re-generate.
228 * aarch64-opc-2.c: Re-generate.
230 2013-01-24 Nick Clifton <nickc@redhat.com>
232 * v850-dis.c: Add support for e3v5 architecture.
233 * v850-opc.c: Likewise.
235 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
237 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
238 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
239 * aarch64-opc.c (operand_general_constraint_met_p): For
240 AARCH64_MOD_LSL, move the range check on the shift amount before the
241 alignment check; change to call set_sft_amount_out_of_range_error
242 instead of set_imm_out_of_range_error.
243 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
244 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
245 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
248 2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
250 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
252 * i386-init.h: Regenerated.
253 * i386-tbl.h: Likewise.
255 2013-01-15 Nick Clifton <nickc@redhat.com>
257 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
259 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
261 2013-01-14 Will Newton <will.newton@imgtec.com>
263 * metag-dis.c (REG_WIDTH): Increase to 64.
265 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
267 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
268 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
269 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
271 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
272 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
273 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
274 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
276 2013-01-10 Will Newton <will.newton@imgtec.com>
278 * Makefile.am: Add Meta.
279 * configure.in: Add Meta.
280 * disassemble.c: Add Meta support.
281 * metag-dis.c: New file.
282 * Makefile.in: Regenerate.
283 * configure: Regenerate.
285 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
287 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
288 (match_opcode): Rename to cr16_match_opcode.
290 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
292 * mips-dis.c: Add names for CP0 registers of r5900.
293 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
294 instructions sq and lq.
295 Add support for MIPS r5900 CPU.
296 Add support for 128 bit MMI (Multimedia Instructions).
297 Add support for EE instructions (Emotion Engine).
298 Disable unsupported floating point instructions (64 bit and
299 undefined compare operations).
300 Enable instructions of MIPS ISA IV which are supported by r5900.
301 Disable 64 bit co processor instructions.
302 Disable 64 bit multiplication and division instructions.
303 Disable instructions for co-processor 2 and 3, because these are
304 not supported (preparation for later VU0 support (Vector Unit)).
305 Disable cvt.w.s because this behaves like trunc.w.s and the
306 correct execution can't be ensured on r5900.
307 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
308 will confuse less developers and compilers.
310 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
312 * aarch64-opc.c (aarch64_print_operand): Change to print
313 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
315 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
316 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
319 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
321 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
322 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
324 2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
326 * i386-gen.c (process_copyright): Update copyright year to 2013.
328 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
330 * cr16-dis.c (match_opcode,make_instruction): Remove static
332 (dwordU,wordU): Moved typedefs to opcode/cr16.h
333 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
335 For older changes see ChangeLog-2012
337 Copyright (C) 2013 Free Software Foundation, Inc.
339 Copying and distribution of this file, with or without modification,
340 are permitted in any medium without royalty provided the copyright
341 notice and this notice are preserved.
347 version-control: never