1 2021-04-01 Martin Liska <mliska@suse.cz>
3 * arm-dis.c (strneq): Remove strneq and use startswith.
4 * cr16-dis.c (print_insn_cr16): Likewise.
5 * score-dis.c (streq): Likewise.
7 * score7-dis.c (strneq): Likewise.
9 2021-04-01 Alan Modra <amodra@gmail.com>
12 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
14 2021-03-31 Alan Modra <amodra@gmail.com>
16 * sysdep.h (POISON_BFD_BOOLEAN): Define.
17 * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
18 * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
19 * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
20 * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
21 * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
22 * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
23 * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
24 * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
25 * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
26 * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
27 * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
28 * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
29 * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
30 and TRUE with true throughout.
32 2021-03-31 Alan Modra <amodra@gmail.com>
34 * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
35 * aarch64-dis.h: Likewise.
36 * aarch64-opc.c: Likewise.
37 * avr-dis.c: Likewise.
38 * csky-dis.c: Likewise.
39 * nds32-asm.c: Likewise.
40 * nds32-dis.c: Likewise.
41 * nfp-dis.c: Likewise.
42 * riscv-dis.c: Likewise.
43 * s12z-dis.c: Likewise.
44 * wasm32-dis.c: Likewise.
46 2021-03-30 Jan Beulich <jbeulich@suse.com>
48 * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
49 (i386_seg_prefixes): New.
50 * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
51 (i386_seg_prefixes): Declare.
53 2021-03-30 Jan Beulich <jbeulich@suse.com>
55 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
57 2021-03-30 Jan Beulich <jbeulich@suse.com>
59 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
60 * i386-reg.tbl (st): Move down.
61 (st(0)): Delete. Extend comment.
62 * i386-tbl.h: Re-generate.
64 2021-03-29 Jan Beulich <jbeulich@suse.com>
66 * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
67 (cmpsd): Move next to cmps.
68 (movsd): Move next to movs.
69 (cmpxchg16b): Move to separate section.
70 (fisttp, fisttpll): Likewise.
71 (monitor, mwait): Likewise.
72 * i386-tbl.h: Re-generate.
74 2021-03-29 Jan Beulich <jbeulich@suse.com>
76 * i386-opc.tbl (psadbw): Add <sse2:comm>.
78 * i386-tbl.h: Re-generate.
80 2021-03-29 Jan Beulich <jbeulich@suse.com>
82 * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
83 pclmul, gfni): New templates. Use them wherever possible. Move
84 SSE4.1 pextrw into respective section.
85 * i386-tbl.h: Re-generate.
87 2021-03-29 Jan Beulich <jbeulich@suse.com>
89 * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
90 strtoull(). Bump upper loop bound. Widen masks. Sanity check
92 * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
93 Convert all of their uses to representation in opcode.
95 2021-03-29 Jan Beulich <jbeulich@suse.com>
97 * i386-opc.h (struct insn_template): Shrink base_opcode to 16
98 bits. Shrink extension_opcode to 9 bits. Make it signed. Change
99 value of None. Shrink operands to 3 bits.
101 2021-03-29 Jan Beulich <jbeulich@suse.com>
103 * i386-gen.c (process_i386_opcode_modifier): New parameter
105 (output_i386_opcode): New local variable "space". Adjust
106 process_i386_opcode_modifier() invocation.
107 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
109 * i386-tbl.h: Re-generate.
111 2021-03-29 Alan Modra <amodra@gmail.com>
113 * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
114 (fp_qualifier_p, get_data_pattern): Likewise.
115 (aarch64_get_operand_modifier_from_value): Likewise.
116 (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
117 (operand_variant_qualifier_p): Likewise.
118 (qualifier_value_in_range_constraint_p): Likewise.
119 (aarch64_get_qualifier_esize): Likewise.
120 (aarch64_get_qualifier_nelem): Likewise.
121 (aarch64_get_qualifier_standard_value): Likewise.
122 (get_lower_bound, get_upper_bound): Likewise.
123 (aarch64_find_best_match, match_operands_qualifier): Likewise.
124 (aarch64_print_operand): Likewise.
125 * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
126 (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
127 (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
128 * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
129 * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
130 (print_insn_tic6x): Likewise.
132 2021-03-29 Alan Modra <amodra@gmail.com>
134 * arc-dis.c (extract_operand_value): Correct NULL cast.
135 * frv-opc.h: Regenerate.
137 2021-03-26 Jan Beulich <jbeulich@suse.com>
139 * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
141 * i386-tbl.h: Re-generate.
143 2021-03-25 Abid Qadeer <abidh@codesourcery.com>
145 * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
146 immediate in br.n instruction.
148 2021-03-25 Jan Beulich <jbeulich@suse.com>
150 * i386-dis.c (XMGatherD, VexGatherD): New.
151 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
152 (print_insn): Check masking for S/G insns.
153 (OP_E_memory): New local variable check_gather. Extend mandatory
154 SIB check. Check register conflicts for (EVEX-encoded) gathers.
155 Extend check for disallowed 16-bit addressing.
156 (OP_VEX): New local variables modrm_reg and sib_index. Convert
157 if()s to switch(). Check register conflicts for (VEX-encoded)
158 gathers. Drop no longer reachable cases.
159 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
162 2021-03-25 Jan Beulich <jbeulich@suse.com>
164 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
165 zeroing-masking without masking.
167 2021-03-25 Jan Beulich <jbeulich@suse.com>
169 * i386-opc.tbl (invlpgb): Fix multi-operand form.
170 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
171 single-operand forms as deprecated.
172 * i386-tbl.h: Re-generate.
174 2021-03-25 Alan Modra <amodra@gmail.com>
177 * ppc-opc.c (XLOCB_MASK): Delete.
178 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
180 (powerpc_opcodes): Accept a BH field on all extended forms of
181 bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
183 2021-03-24 Jan Beulich <jbeulich@suse.com>
185 * i386-gen.c (output_i386_opcode): Drop processing of
186 opcode_length. Calculate length from base_opcode. Adjust prefix
187 encoding determination.
188 (process_i386_opcodes): Drop output of fake opcode_length.
189 * i386-opc.h (struct insn_template): Drop opcode_length field.
190 * i386-opc.tbl: Drop opcode length field from all templates.
191 * i386-tbl.h: Re-generate.
193 2021-03-24 Jan Beulich <jbeulich@suse.com>
195 * i386-gen.c (process_i386_opcode_modifier): Return void. New
196 parameter "prefix". Drop local variable "regular_encoding".
197 Record prefix setting / check for consistency.
198 (output_i386_opcode): Parse opcode_length and base_opcode
199 earlier. Derive prefix encoding. Drop no longer applicable
200 consistency checking. Adjust process_i386_opcode_modifier()
202 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
204 * i386-tbl.h: Re-generate.
206 2021-03-24 Jan Beulich <jbeulich@suse.com>
208 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
210 * i386-opc.h (Prefix_*): Move #define-s.
211 * i386-opc.tbl: Move pseudo prefix enumerator values to
212 extension opcode field. Introduce pseudopfx template.
213 * i386-tbl.h: Re-generate.
215 2021-03-23 Jan Beulich <jbeulich@suse.com>
217 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
219 * i386-tbl.h: Re-generate.
221 2021-03-23 Jan Beulich <jbeulich@suse.com>
223 * i386-opc.h (struct insn_template): Move cpu_flags field past
225 * i386-tbl.h: Re-generate.
227 2021-03-23 Jan Beulich <jbeulich@suse.com>
229 * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
230 * i386-opc.h (OpcodeSpace): New enumerator.
231 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
232 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
233 SPACE_XOP09, SPACE_XOP0A): ... respectively.
234 (struct i386_opcode_modifier): New field opcodespace. Shrink
236 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
237 SpaceXOP09, SpaceXOP0A): Define. Use them to replace
239 * i386-tbl.h: Re-generate.
241 2021-03-22 Martin Liska <mliska@suse.cz>
243 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
244 * arc-dis.c (parse_option): Likewise.
245 * arm-dis.c (parse_arm_disassembler_options): Likewise.
246 * cris-dis.c (print_with_operands): Likewise.
247 * h8300-dis.c (bfd_h8_disassemble): Likewise.
248 * i386-dis.c (print_insn): Likewise.
249 * ia64-gen.c (fetch_insn_class): Likewise.
250 (parse_resource_users): Likewise.
251 (in_iclass): Likewise.
252 (lookup_specifier): Likewise.
253 (insert_opcode_dependencies): Likewise.
254 * mips-dis.c (parse_mips_ase_option): Likewise.
255 (parse_mips_dis_option): Likewise.
256 * s390-dis.c (disassemble_init_s390): Likewise.
257 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
259 2021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
261 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
263 2021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
265 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
266 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
268 2021-03-12 Alan Modra <amodra@gmail.com>
270 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
272 2021-03-11 Jan Beulich <jbeulich@suse.com>
274 * i386-dis.c (OP_XMM): Re-order checks.
276 2021-03-11 Jan Beulich <jbeulich@suse.com>
278 * i386-dis.c (putop): Drop need_vex check when also checking
280 (intel_operand_size, OP_E_memory): Drop vex.evex check when also
283 2021-03-11 Jan Beulich <jbeulich@suse.com>
285 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
286 checks. Move case label past broadcast check.
288 2021-03-10 Jan Beulich <jbeulich@suse.com>
290 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
291 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
292 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
293 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
294 EVEX_W_0F38C7_M_0_L_2): Delete.
295 (REG_EVEX_0F38C7_M_0_L_2): New.
296 (intel_operand_size): Handle VEX and EVEX the same for
297 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
298 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
299 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
300 vex_vsib_q_w_d_mode uses.
301 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
302 0F38A1, and 0F38A3 entries.
303 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
305 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
306 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
309 2021-03-10 Jan Beulich <jbeulich@suse.com>
311 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
312 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
313 MOD_VEX_0FXOP_09_12): Rename to ...
314 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
315 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
316 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
317 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
318 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
319 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
320 (reg_table): Adjust comments.
321 (x86_64_table): Move X86_64_0F24, X86_64_0F26,
322 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
323 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
324 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
325 (vex_len_table): Adjust opcode 0A_12 entry.
326 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
327 MOD_C5_32BIT, and MOD_XOP_09_12 entries.
328 (rm_table): Move hreset entry.
330 2021-03-10 Jan Beulich <jbeulich@suse.com>
332 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
333 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
334 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
335 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
336 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
337 (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
338 (get_valid_dis386): Also handle 512-bit vector length when
339 vectoring into vex_len_table[].
340 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
341 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
343 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
344 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
345 * i386-dis-evex-prefix.h: Adjust 0F7E entry.
346 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
349 2021-03-10 Jan Beulich <jbeulich@suse.com>
351 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
352 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
353 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
354 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
356 * i386-dis-evex-len.h (evex_len_table): Likewise.
357 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
359 2021-03-10 Jan Beulich <jbeulich@suse.com>
361 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
362 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
363 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
364 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
365 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
366 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
367 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
368 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
369 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
370 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
371 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
372 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
373 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
374 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
375 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
376 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
377 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
378 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
379 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
380 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
381 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
382 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
383 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
384 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
385 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
386 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
387 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
388 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
389 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
390 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
391 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
392 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
393 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
394 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
395 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
396 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
397 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
398 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
399 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
400 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
401 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
402 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
403 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
404 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
405 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
406 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
407 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
408 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
409 EVEX_W_0F3A43_L_n): New.
410 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
411 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
412 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
413 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
414 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
415 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
416 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
417 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
418 0F385B, 0F38C6, and 0F38C7 entries.
419 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
421 * i386-dis-evex-w.h: No longer link to evex_len_table[] for
422 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
423 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
424 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
426 2021-03-10 Jan Beulich <jbeulich@suse.com>
428 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
429 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
430 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
431 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
432 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
433 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
434 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
435 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
436 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
437 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
438 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
439 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
440 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
441 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
442 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
443 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
444 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
445 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
446 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
447 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
448 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
449 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
450 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
451 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
452 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
453 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
454 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
455 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
456 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
457 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
458 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
459 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
460 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
461 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
462 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
463 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
464 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
465 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
466 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
467 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
468 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
469 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
470 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
471 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
472 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
473 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
474 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
475 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
476 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
477 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
478 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
479 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
480 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
481 VEX_W_0F99_P_2_LEN_0): Delete.
482 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
483 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
484 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
485 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
486 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
487 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
488 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
489 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
490 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
491 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
492 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
493 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
494 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
495 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
496 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
497 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
498 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
499 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
500 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
501 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
502 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
503 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
504 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
505 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
506 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
507 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
508 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
509 (prefix_table): No longer link to vex_len_table[] for opcodes
510 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
511 0F92, 0F93, 0F98, and 0F99.
512 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
513 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
515 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
516 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
518 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
519 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
521 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
522 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
525 2021-03-10 Jan Beulich <jbeulich@suse.com>
527 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
528 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
529 REG_VEX_0F73_M_0 respectively.
530 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
531 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
532 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
533 MOD_VEX_0F73_REG_7): Delete.
534 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
535 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
536 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
537 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
538 PREFIX_VEX_0F3AF0_L_0 respectively.
539 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
540 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
541 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
542 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
543 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
544 VEX_LEN_0F38F7): New.
545 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
546 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
547 0F72, and 0F73. No longer link to vex_len_table[] for opcode
549 (prefix_table): No longer link to vex_len_table[] for opcodes
550 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
551 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
552 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
553 0F38F6, 0F38F7, and 0F3AF0.
554 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
555 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
556 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
559 2021-03-10 Jan Beulich <jbeulich@suse.com>
561 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
562 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
563 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
564 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
565 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
566 (MOD_0F71, MOD_0F72, MOD_0F73): New.
567 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
569 (reg_table): No longer link to mod_table[] for opcodes 0F71,
571 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
574 2021-03-10 Jan Beulich <jbeulich@suse.com>
576 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
577 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
578 (reg_table): Don't link to mod_table[] where not needed. Add
579 PREFIX_IGNORED to nop entries.
580 (prefix_table): Replace PREFIX_OPCODE in nop entries.
581 (mod_table): Add nop entries next to prefetch ones. Drop
582 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
583 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
584 (rm_table): Add PREFIX_IGNORED to nop entries. Drop
585 PREFIX_OPCODE from endbr* entries.
586 (get_valid_dis386): Also consider entry's name when zapping
588 (print_insn): Handle PREFIX_IGNORED.
590 2021-03-09 Jan Beulich <jbeulich@suse.com>
592 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
593 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
595 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
596 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
597 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
598 PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
599 (struct i386_opcode_modifier): Delete notrackprefixok,
600 islockable, hleprefixok, and repprefixok fields. Add prefixok
602 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
603 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
604 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
605 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
607 * opcodes/i386-tbl.h: Re-generate.
609 2021-03-09 Jan Beulich <jbeulich@suse.com>
611 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
612 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
614 * opcodes/i386-tbl.h: Re-generate.
616 2021-03-03 Jan Beulich <jbeulich@suse.com>
618 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
619 for {} instead of {0}. Don't look for '0'.
620 * i386-opc.tbl: Drop operand count field. Drop redundant operand
623 2021-02-19 Nelson Chu <nelson.chu@sifive.com>
626 * riscv-dis.c (print_insn_args): Updated encoding macros.
627 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
628 (match_c_addi16sp): Updated encoding macros.
629 (match_c_lui): Likewise.
630 (match_c_lui_with_hint): Likewise.
631 (match_c_addi4spn): Likewise.
632 (match_c_slli): Likewise.
633 (match_slli_as_c_slli): Likewise.
634 (match_c_slli64): Likewise.
635 (match_srxi_as_c_srxi): Likewise.
636 (riscv_insn_types): Added .insn css/cl/cs.
638 2021-02-18 Nelson Chu <nelson.chu@sifive.com>
640 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
641 (default_priv_spec): Updated type to riscv_spec_class.
642 (parse_riscv_dis_option): Updated.
643 * riscv-opc.c: Moved stuff and make the file tidy.
645 2021-02-17 Alan Modra <amodra@gmail.com>
647 * wasm32-dis.c: Include limits.h.
648 (CHAR_BIT): Provide backup define.
649 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
650 Correct signed overflow checking.
652 2021-02-16 Jan Beulich <jbeulich@suse.com>
654 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
655 * i386-tbl.h: Re-generate.
657 2021-02-16 Jan Beulich <jbeulich@suse.com>
659 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
661 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
663 2021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
665 * s390-mkopc.c (main): Accept arch14 as cpu string.
666 * s390-opc.txt: Add new arch14 instructions.
668 2021-02-04 Nick Alcock <nick.alcock@oracle.com>
670 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
672 * configure: Regenerated.
674 2021-02-08 Mike Frysinger <vapier@gentoo.org>
676 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
677 * tic54x-opc.c (regs): Rename to ...
678 (tic54x_regs): ... this.
679 (mmregs): Rename to ...
680 (tic54x_mmregs): ... this.
681 (condition_codes): Rename to ...
682 (tic54x_condition_codes): ... this.
683 (cc2_codes): Rename to ...
684 (tic54x_cc2_codes): ... this.
685 (cc3_codes): Rename to ...
686 (tic54x_cc3_codes): ... this.
687 (status_bits): Rename to ...
688 (tic54x_status_bits): ... this.
689 (misc_symbols): Rename to ...
690 (tic54x_misc_symbols): ... this.
692 2021-02-04 Nelson Chu <nelson.chu@sifive.com>
694 * riscv-opc.c (MASK_RVB_IMM): Removed.
695 (riscv_opcodes): Removed zb* instructions.
696 (riscv_ext_version_table): Removed versions for zb*.
698 2021-01-26 Alan Modra <amodra@gmail.com>
700 * i386-gen.c (parse_template): Ensure entire template_instance
703 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
705 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
706 (riscv_fpr_names_abi): Likewise.
707 (riscv_opcodes): Likewise.
708 (riscv_insn_types): Likewise.
710 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
712 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
714 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
716 * riscv-dis.c: Comments tidy and improvement.
717 * riscv-opc.c: Likewise.
719 2021-01-13 Alan Modra <amodra@gmail.com>
721 * Makefile.in: Regenerate.
723 2021-01-12 H.J. Lu <hongjiu.lu@intel.com>
726 * configure.ac: Use GNU_MAKE_JOBSERVER.
727 * aclocal.m4: Regenerated.
728 * configure: Likewise.
730 2021-01-12 Nick Clifton <nickc@redhat.com>
732 * po/sr.po: Updated Serbian translation.
734 2021-01-11 H.J. Lu <hongjiu.lu@intel.com>
737 * configure: Regenerated.
739 2021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
741 * aarch64-asm-2.c: Regenerate.
742 * aarch64-dis-2.c: Likewise.
743 * aarch64-opc-2.c: Likewise.
744 * aarch64-opc.c (aarch64_print_operand):
745 Delete handling of AARCH64_OPND_CSRE_CSR.
746 * aarch64-tbl.h (aarch64_feature_csre): Delete.
748 (_CSRE_INSN): Likewise.
749 (aarch64_opcode_table): Delete csr.
751 2021-01-11 Nick Clifton <nickc@redhat.com>
753 * po/de.po: Updated German translation.
754 * po/fr.po: Updated French translation.
755 * po/pt_BR.po: Updated Brazilian Portuguese translation.
756 * po/sv.po: Updated Swedish translation.
757 * po/uk.po: Updated Ukranian translation.
759 2021-01-09 H.J. Lu <hongjiu.lu@intel.com>
761 * configure: Regenerated.
763 2021-01-09 Nick Clifton <nickc@redhat.com>
765 * configure: Regenerate.
766 * po/opcodes.pot: Regenerate.
768 2021-01-09 Nick Clifton <nickc@redhat.com>
770 * 2.36 release branch crated.
772 2021-01-08 Peter Bergner <bergner@linux.ibm.com>
774 * ppc-opc.c (insert_dw, (extract_dw): New functions.
775 (DW, (XRC_MASK): Define.
776 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
778 2021-01-09 Alan Modra <amodra@gmail.com>
780 * configure: Regenerate.
782 2021-01-08 Nick Clifton <nickc@redhat.com>
784 * po/sv.po: Updated Swedish translation.
786 2021-01-08 Nick Clifton <nickc@redhat.com>
789 * aarch64-dis.c (determine_disassembling_preference): Move call to
790 aarch64_match_operands_constraint outside of the assertion.
791 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
792 Replace with a return of FALSE.
795 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
796 core system register.
798 2021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
800 * configure: Regenerate.
802 2021-01-07 Nick Clifton <nickc@redhat.com>
804 * po/fr.po: Updated French translation.
806 2021-01-07 Fredrik Noring <noring@nocrew.org>
808 * m68k-opc.c (chkl): Change minimum architecture requirement to
811 2021-01-07 Philipp Tomsich <prt@gnu.org>
813 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
815 2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
816 Jim Wilson <jimw@sifive.com>
817 Andrew Waterman <andrew@sifive.com>
818 Maxim Blinov <maxim.blinov@embecosm.com>
819 Kito Cheng <kito.cheng@sifive.com>
820 Nelson Chu <nelson.chu@sifive.com>
822 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
823 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
825 2021-01-01 Alan Modra <amodra@gmail.com>
827 Update year range in copyright notice of all files.
829 For older changes see ChangeLog-2020
831 Copyright (C) 2021 Free Software Foundation, Inc.
833 Copying and distribution of this file, with or without modification,
834 are permitted in any medium without royalty provided the copyright
835 notice and this notice are preserved.
841 version-control: never