opcodes/ChangeLog

   1 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
   2
   3         * aarch64-asm-2.c: Regenerated.
   4         * aarch64-dis-2.c: Regenerated.
   5         * aarch64-opc-2.c: Regenerated.
   6         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
   7         for SVE_Zm4_11_INDEX.
   8         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
   9         (fields): Handle SVE_i2h field.
  10         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
  11         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
  12
  13 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  14
  15         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
  16         sve_shift_tsz_bhsd iclass encode.
  17         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
  18         sve_shift_tsz_bhsd iclass decode.
  19
  20 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  21
  22         * aarch64-asm-2.c: Regenerated.
  23         * aarch64-dis-2.c: Regenerated.
  24         * aarch64-opc-2.c: Regenerated.
  25         * aarch64-asm.c (aarch64_ins_sve_shrimm):
  26         (aarch64_encode_variant_using_iclass): Handle
  27         sve_shift_tsz_hsd iclass encode.
  28         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
  29         sve_shift_tsz_hsd iclass decode.
  30         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
  31         for SVE_SHRIMM_UNPRED_22.
  32         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
  33         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
  34         operand.
  35
  36 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  37
  38         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
  39         sve_size_013 iclass encode.
  40         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
  41         sve_size_013 iclass decode.
  42
  43 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  44
  45         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
  46         sve_size_bh iclass encode.
  47         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
  48         sve_size_bh iclass decode.
  49
  50 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  51
  52         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
  53         sve_size_sd2 iclass encode.
  54         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
  55         sve_size_sd2 iclass decode.
  56         * aarch64-opc.c (fields): Handle SVE_sz2 field.
  57         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
  58
  59 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  60
  61         * aarch64-asm-2.c: Regenerated.
  62         * aarch64-dis-2.c: Regenerated.
  63         * aarch64-opc-2.c: Regenerated.
  64         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
  65         for SVE_ADDR_ZX.
  66         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
  67         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
  68
  69 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  70
  71         * aarch64-asm-2.c: Regenerated.
  72         * aarch64-dis-2.c: Regenerated.
  73         * aarch64-opc-2.c: Regenerated.
  74         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
  75         for SVE_Zm3_11_INDEX.
  76         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
  77         (fields): Handle SVE_i3l and SVE_i3h2 fields.
  78         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
  79         fields.
  80         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
  81
  82 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  83
  84         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
  85         sve_size_hsd2 iclass encode.
  86         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
  87         sve_size_hsd2 iclass decode.
  88         * aarch64-opc.c (fields): Handle SVE_size field.
  89         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
  90
  91 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  92
  93         * aarch64-asm-2.c: Regenerated.
  94         * aarch64-dis-2.c: Regenerated.
  95         * aarch64-opc-2.c: Regenerated.
  96         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
  97         for SVE_IMM_ROT3.
  98         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
  99         (fields): Handle SVE_rot3 field.
 100         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 101         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 102
 103 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 104
 105         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 106         instructions.
 107
 108 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 109
 110         * aarch64-tbl.h
 111         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 112         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 113         aarch64_feature_sve2bitperm): New feature sets.
 114         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 115         for feature set addresses.
 116         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 117         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 118
 119 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 120             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 121
 122         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 123         argument and set ASE_EVA_R6 appropriately.
 124         (set_default_mips_dis_options): Pass ISA to above.
 125         (parse_mips_dis_option): Likewise.
 126         * mips-opc.c (EVAR6): New macro.
 127         (mips_builtin_opcodes): Add llwpe, scwpe.
 128
 129 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 130
 131         * aarch64-asm-2.c: Regenerated.
 132         * aarch64-dis-2.c: Regenerated.
 133         * aarch64-opc-2.c: Regenerated.
 134         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 135         AARCH64_OPND_TME_UIMM16.
 136         (aarch64_print_operand): Likewise.
 137         * aarch64-tbl.h (QL_IMM_NIL): New.
 138         (TME): New.
 139         (_TME_INSN): New.
 140         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 141
 142 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 143
 144         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 145
 146 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 147             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 148
 149         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 150
 151 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 152
 153         * s12z-opc.h: Add extern "C" bracketing to help
 154         users who wish to use this interface in c++ code.
 155
 156 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 157
 158         * s12z-opc.c (bm_decode): Handle bit map operations with the
 159         "reserved0" mode.
 160
 161 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 162
 163         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 164         specifier.  Add entries for VLDR and VSTR of system registers.
 165         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 166         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 167         of %J and %K format specifier.
 168
 169 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 170
 171         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 172         Add new entries for VSCCLRM instruction.
 173         (print_insn_coprocessor): Handle new %C format control code.
 174
 175 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 176
 177         * arm-dis.c (enum isa): New enum.
 178         (struct sopcode32): New structure.
 179         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 180         set isa field of all current entries to ANY.
 181         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 182         Only match an entry if its isa field allows the current mode.
 183
 184 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 185
 186         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 187         CLRM.
 188         (print_insn_thumb32): Add logic to print %n CLRM register list.
 189
 190 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 191
 192         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 193         and %Q patterns.
 194
 195 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 196
 197         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 198         (print_insn_thumb32): Edit the switch case for %Z.
 199
 200 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 201
 202         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 203
 204 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 205
 206         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 207
 208 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 209
 210         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 211
 212 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 213
 214         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 215         Arm register with r13 and r15 unpredictable.
 216         (thumb32_opcodes): New instructions for bfx and bflx.
 217
 218 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 219
 220         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 221
 222 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 223
 224         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 225
 226 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 227
 228         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 229
 230 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 231
 232         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 233
 234 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 235
 236         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 237         "optr". ("operator" is a reserved word in c++).
 238
 239 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 240
 241         * aarch64-opc.c (aarch64_print_operand): Add case for
 242         AARCH64_OPND_Rt_SP.
 243         (verify_constraints): Likewise.
 244         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 245         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 246         to accept Rt|SP as first operand.
 247         (AARCH64_OPERANDS): Add new Rt_SP.
 248         * aarch64-asm-2.c: Regenerated.
 249         * aarch64-dis-2.c: Regenerated.
 250         * aarch64-opc-2.c: Regenerated.
 251
 252 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 253
 254         * aarch64-asm-2.c: Regenerated.
 255         * aarch64-dis-2.c: Likewise.
 256         * aarch64-opc-2.c: Likewise.
 257         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 258
 259 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 260
 261         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 262
 263 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 264
 265         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 266         * i386-init.h: Regenerated.
 267
 268 2019-04-07  Alan Modra  <amodra@gmail.com>
 269
 270         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 271         op_separator to control printing of spaces, comma and parens
 272         rather than need_comma, need_paren and spaces vars.
 273
 274 2019-04-07  Alan Modra  <amodra@gmail.com>
 275
 276         PR 24421
 277         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 278         (print_insn_neon, print_insn_arm): Likewise.
 279
 280 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 281
 282         * i386-dis-evex.h (evex_table): Updated to support BF16
 283         instructions.
 284         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 285         and EVEX_W_0F3872_P_3.
 286         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 287         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 288         * i386-opc.h (enum): Add CpuAVX512_BF16.
 289         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 290         * i386-opc.tbl: Add AVX512 BF16 instructions.
 291         * i386-init.h: Regenerated.
 292         * i386-tbl.h: Likewise.
 293
 294 2019-04-05  Alan Modra  <amodra@gmail.com>
 295
 296         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 297         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 298         to favour printing of "-" branch hint when using the "y" bit.
 299         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 300
 301 2019-04-05  Alan Modra  <amodra@gmail.com>
 302
 303         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 304         opcode until first operand is output.
 305
 306 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 307
 308         PR gas/24349
 309         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 310         (valid_bo_post_v2): Add support for 'at' branch hints.
 311         (insert_bo): Only error on branch on ctr.
 312         (get_bo_hint_mask): New function.
 313         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 314         for inserting 'at' branch hints.
 315         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 316         for extracting 'at' branch hints.
 317         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 318         (BOE): Delete operand.
 319         (BOM, BOP): New operands.
 320         (RM): Update value.
 321         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 322         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 323         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 324         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 325         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 326         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 327         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 328         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 329         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 330         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 331         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 332         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 333         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 334         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 335         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 336         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 337         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 338         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 339         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 340         bttarl+>: New extended mnemonics.
 341
 342 2019-03-28  Alan Modra  <amodra@gmail.com>
 343
 344         PR 24390
 345         * ppc-opc.c (BTF): Define.
 346         (powerpc_opcodes): Use for mtfsb*.
 347         * ppc-dis.c (print_insn_powerpc): Print fields with both
 348         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 349
 350 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 351
 352         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 353         (mapping_symbol_for_insn): Implement new algorithm.
 354         (print_insn): Remove duplicate code.
 355
 356 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 357
 358         * aarch64-dis.c (print_insn_aarch64):
 359         Implement override.
 360
 361 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 362
 363         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 364         order.
 365
 366 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 367
 368         * aarch64-dis.c (last_stop_offset): New.
 369         (print_insn_aarch64): Use stop_offset.
 370
 371 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 372
 373         PR gas/24359
 374         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 375         CPU_ANY_AVX2_FLAGS.
 376         * i386-init.h: Regenerated.
 377
 378 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 379
 380         PR gas/24348
 381         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 382         vmovdqu16, vmovdqu32 and vmovdqu64.
 383         * i386-tbl.h: Regenerated.
 384
 385 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 386
 387         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 388         from vstrszb, vstrszh, and vstrszf.
 389
 390 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 391
 392         * s390-opc.txt: Add instruction descriptions.
 393
 394 2019-02-08  Jim Wilson  <jimw@sifive.com>
 395
 396         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 397         <bne>: Likewise.
 398
 399 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 400
 401         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
 402
 403 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 404
 405         PR binutils/23212
 406         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
 407         * aarch64-opc.c (verify_elem_sd): New.
 408         (fields): Add FLD_sz entr.
 409         * aarch64-tbl.h (_SIMD_INSN): New.
 410         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
 411         fmulx scalar and vector by element isns.
 412
 413 2019-02-07  Nick Clifton  <nickc@redhat.com>
 414
 415         * po/sv.po: Updated Swedish translation.
 416
 417 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
 418
 419         * s390-mkopc.c (main): Accept arch13 as cpu string.
 420         * s390-opc.c: Add new instruction formats and instruction opcode
 421         masks.
 422         * s390-opc.txt: Add new arch13 instructions.
 423
 424 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 425
 426         * aarch64-tbl.h (QL_LDST_AT): Update macro.
 427         (aarch64_opcode): Change encoding for stg, stzg
 428         st2g and st2zg.
 429         * aarch64-asm-2.c: Regenerated.
 430         * aarch64-dis-2.c: Regenerated.
 431         * aarch64-opc-2.c: Regenerated.
 432
 433 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 434
 435         * aarch64-asm-2.c: Regenerated.
 436         * aarch64-dis-2.c: Likewise.
 437         * aarch64-opc-2.c: Likewise.
 438         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
 439
 440 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 441             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 442
 443         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
 444         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
 445         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
 446         * aarch64-dis.h (ext_addr_simple_2): Likewise.
 447         * aarch64-opc.c (operand_general_constraint_met_p): Remove
 448         case for ldstgv_indexed.
 449         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
 450         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
 451         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
 452         * aarch64-asm-2.c: Regenerated.
 453         * aarch64-dis-2.c: Regenerated.
 454         * aarch64-opc-2.c: Regenerated.
 455
 456 2019-01-23  Nick Clifton  <nickc@redhat.com>
 457
 458         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 459
 460 2019-01-21  Nick Clifton  <nickc@redhat.com>
 461
 462         * po/de.po: Updated German translation.
 463         * po/uk.po: Updated Ukranian translation.
 464
 465 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 466         * mips-dis.c (mips_arch_choices): Fix typo in
 467         gs464, gs464e and gs264e descriptors.
 468
 469 2019-01-19  Nick Clifton  <nickc@redhat.com>
 470
 471         * configure: Regenerate.
 472         * po/opcodes.pot: Regenerate.
 473
 474 2018-06-24  Nick Clifton  <nickc@redhat.com>
 475
 476         2.32 branch created.
 477
 478 2019-01-09  John Darrington <john@darrington.wattle.id.au>
 479
 480         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
 481         if it is null.
 482         -dis.c (opr_emit_disassembly): Do not omit an index if it is
 483         zero.
 484
 485 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
 486
 487         * configure: Regenerate.
 488
 489 2019-01-07  Alan Modra  <amodra@gmail.com>
 490
 491         * configure: Regenerate.
 492         * po/POTFILES.in: Regenerate.
 493
 494 2019-01-03  John Darrington <john@darrington.wattle.id.au>
 495
 496         * s12z-opc.c: New file.
 497         * s12z-opc.h: New file.
 498         * s12z-dis.c: Removed all code not directly related to display
 499         of instructions.  Used the interface provided by the new files
 500         instead.
 501         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
 502         * Makefile.in: Regenerate.
 503         * configure.ac (bfd_s12z_arch): Correct the dependencies.
 504         * configure: Regenerate.
 505
 506 2019-01-01  Alan Modra  <amodra@gmail.com>
 507
 508         Update year range in copyright notice of all files.
 509
 510 For older changes see ChangeLog-2018
 511 \f
 512 Copyright (C) 2019 Free Software Foundation, Inc.
 513
 514 Copying and distribution of this file, with or without modification,
 515 are permitted in any medium without royalty provided the copyright
 516 notice and this notice are preserved.
 517
 518 Local Variables:
 519 mode: change-log
 520 left-margin: 8
 521 fill-column: 74
 522 version-control: never
 523 End: