opcodes/ChangeLog

   1 2020-05-11  Alan Modra  <amodra@gmail.com>
   2
   3         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
   4         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
   5         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
   6         (prefix_opcodes): Add xxeval.
   7
   8 2020-05-11  Alan Modra  <amodra@gmail.com>
   9
  10         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
  11         xxgenpcvwm, xxgenpcvdm.
  12
  13 2020-05-11  Alan Modra  <amodra@gmail.com>
  14
  15         * ppc-opc.c (MP, VXVAM_MASK): Define.
  16         (VXVAPS_MASK): Use VXVA_MASK.
  17         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
  18         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
  19         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
  20         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
  21
  22 2020-05-11  Alan Modra  <amodra@gmail.com>
  23             Peter Bergner  <bergner@linux.ibm.com>
  24
  25         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
  26         New functions.
  27         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
  28         YMSK2, XA6a, XA6ap, XB6a entries.
  29         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
  30         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
  31         (PPCVSX4): Define.
  32         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
  33         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
  34         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
  35         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
  36         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
  37         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
  38         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
  39         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
  40         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
  41         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
  42         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
  43         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
  44         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
  45         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
  46
  47 2020-05-11  Alan Modra  <amodra@gmail.com>
  48
  49         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
  50         (insert_xts, extract_xts): New functions.
  51         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
  52         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
  53         (VXRC_MASK, VXSH_MASK): Define.
  54         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
  55         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
  56         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
  57         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
  58         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
  59         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
  60         xxblendvh, xxblendvw, xxblendvd, xxpermx.
  61
  62 2020-05-11  Alan Modra  <amodra@gmail.com>
  63
  64         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
  65         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
  66         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
  67         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
  68         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
  69
  70 2020-05-11  Alan Modra  <amodra@gmail.com>
  71
  72         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
  73         (XTP, DQXP, DQXP_MASK): Define.
  74         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
  75         (prefix_opcodes): Add plxvp and pstxvp.
  76
  77 2020-05-11  Alan Modra  <amodra@gmail.com>
  78
  79         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
  80         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
  81         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
  82
  83 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
  84
  85         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
  86
  87 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
  88
  89         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
  90         (L1OPT): Define.
  91         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
  92
  93 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
  94
  95         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
  96
  97 2020-05-11  Alan Modra  <amodra@gmail.com>
  98
  99         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 100
 101 2020-05-11  Alan Modra  <amodra@gmail.com>
 102
 103         * ppc-dis.c (ppc_opts): Add "power10" entry.
 104         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 105         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 106
 107 2020-05-11  Nick Clifton  <nickc@redhat.com>
 108
 109         * po/fr.po: Updated French translation.
 110
 111 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 112
 113         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 114         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 115         (operand_general_constraint_met_p): validate
 116         AARCH64_OPND_UNDEFINED.
 117         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 118         for FLD_imm16_2.
 119         * aarch64-asm-2.c: Regenerated.
 120         * aarch64-dis-2.c: Regenerated.
 121         * aarch64-opc-2.c: Regenerated.
 122
 123 2020-04-29  Nick Clifton  <nickc@redhat.com>
 124
 125         PR 22699
 126         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 127         and SETRC insns.
 128
 129 2020-04-29  Nick Clifton  <nickc@redhat.com>
 130
 131         * po/sv.po: Updated Swedish translation.
 132
 133 2020-04-29  Nick Clifton  <nickc@redhat.com>
 134
 135         PR 22699
 136         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 137         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 138         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 139         IMM0_8U case.
 140
 141 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 142
 143         PR 25848
 144         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 145         cmpi only on m68020up and cpu32.
 146
 147 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 148
 149         * aarch64-asm.c (aarch64_ins_none): New.
 150         * aarch64-asm.h (ins_none): New declaration.
 151         * aarch64-dis.c (aarch64_ext_none): New.
 152         * aarch64-dis.h (ext_none): New declaration.
 153         * aarch64-opc.c (aarch64_print_operand): Update case for
 154         AARCH64_OPND_BARRIER_PSB.
 155         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 156         (AARCH64_OPERANDS): Update inserter/extracter for
 157         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 158         * aarch64-asm-2.c: Regenerated.
 159         * aarch64-dis-2.c: Regenerated.
 160         * aarch64-opc-2.c: Regenerated.
 161
 162 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 163
 164         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 165         (aarch64_feature_ras, RAS): Likewise.
 166         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 167         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 168         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 169         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 170         * aarch64-asm-2.c: Regenerated.
 171         * aarch64-dis-2.c: Regenerated.
 172         * aarch64-opc-2.c: Regenerated.
 173
 174 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 175
 176         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 177         (print_insn_neon): Support disassembly of conditional
 178         instructions.
 179
 180 2020-02-16  David Faust  <david.faust@oracle.com>
 181
 182         * bpf-desc.c: Regenerate.
 183         * bpf-desc.h: Likewise.
 184         * bpf-opc.c: Regenerate.
 185         * bpf-opc.h: Likewise.
 186
 187 2020-04-07  Lili Cui  <lili.cui@intel.com>
 188
 189         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 190         (prefix_table): New instructions (see prefixes above).
 191         (rm_table): Likewise
 192         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 193         CPU_ANY_TSXLDTRK_FLAGS.
 194         (cpu_flags): Add CpuTSXLDTRK.
 195         * i386-opc.h (enum): Add CpuTSXLDTRK.
 196         (i386_cpu_flags): Add cputsxldtrk.
 197         * i386-opc.tbl: Add XSUSPLDTRK insns.
 198         * i386-init.h: Regenerate.
 199         * i386-tbl.h: Likewise.
 200
 201 2020-04-02  Lili Cui  <lili.cui@intel.com>
 202
 203         * i386-dis.c (prefix_table): New instructions serialize.
 204         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 205         CPU_ANY_SERIALIZE_FLAGS.
 206         (cpu_flags): Add CpuSERIALIZE.
 207         * i386-opc.h (enum): Add CpuSERIALIZE.
 208         (i386_cpu_flags): Add cpuserialize.
 209         * i386-opc.tbl: Add SERIALIZE insns.
 210         * i386-init.h: Regenerate.
 211         * i386-tbl.h: Likewise.
 212
 213 2020-03-26  Alan Modra  <amodra@gmail.com>
 214
 215         * disassemble.h (opcodes_assert): Declare.
 216         (OPCODES_ASSERT): Define.
 217         * disassemble.c: Don't include assert.h.  Include opintl.h.
 218         (opcodes_assert): New function.
 219         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 220         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 221         calculate maxlen.  Omit insn decoding when insn length exceeds
 222         maxlen.  Exit from nibble loop when looking for E, before
 223         accessing next data byte.  Move processing of E outside loop.
 224         Replace tests of maxlen in loop with assertions.
 225
 226 2020-03-26  Alan Modra  <amodra@gmail.com>
 227
 228         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 229
 230 2020-03-25  Alan Modra  <amodra@gmail.com>
 231
 232         * z80-dis.c (suffix): Init mybuf.
 233
 234 2020-03-22  Alan Modra  <amodra@gmail.com>
 235
 236         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 237         successflly read from section.
 238
 239 2020-03-22  Alan Modra  <amodra@gmail.com>
 240
 241         * arc-dis.c (find_format): Use ISO C string concatenation rather
 242         than line continuation within a string.  Don't access needs_limm
 243         before testing opcode != NULL.
 244
 245 2020-03-22  Alan Modra  <amodra@gmail.com>
 246
 247         * ns32k-dis.c (print_insn_arg): Update comment.
 248         (print_insn_ns32k): Reduce size of index_offset array, and
 249         initialize, passing -1 to print_insn_arg for args that are not
 250         an index.  Don't exit arg loop early.  Abort on bad arg number.
 251
 252 2020-03-22  Alan Modra  <amodra@gmail.com>
 253
 254         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 255         * s12z-opc.c: Formatting.
 256         (operands_f): Return an int.
 257         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 258         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 259         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 260         (exg_sex_discrim): Likewise.
 261         (create_immediate_operand, create_bitfield_operand),
 262         (create_register_operand_with_size, create_register_all_operand),
 263         (create_register_all16_operand, create_simple_memory_operand),
 264         (create_memory_operand, create_memory_auto_operand): Don't
 265         segfault on malloc failure.
 266         (z_ext24_decode): Return an int status, negative on fail, zero
 267         on success.
 268         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 269         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 270         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 271         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 272         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 273         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 274         (loop_primitive_decode, shift_decode, psh_pul_decode),
 275         (bit_field_decode): Similarly.
 276         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 277         to return value, update callers.
 278         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 279         Don't segfault on NULL operand.
 280         (decode_operation): Return OP_INVALID on first fail.
 281         (decode_s12z): Check all reads, returning -1 on fail.
 282
 283 2020-03-20  Alan Modra  <amodra@gmail.com>
 284
 285         * metag-dis.c (print_insn_metag): Don't ignore status from
 286         read_memory_func.
 287
 288 2020-03-20  Alan Modra  <amodra@gmail.com>
 289
 290         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 291         Initialize parts of buffer not written when handling a possible
 292         2-byte insn at end of section.  Don't attempt decoding of such
 293         an insn by the 4-byte machinery.
 294
 295 2020-03-20  Alan Modra  <amodra@gmail.com>
 296
 297         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 298         partially filled buffer.  Prevent lookup of 4-byte insns when
 299         only VLE 2-byte insns are possible due to section size.  Print
 300         ".word" rather than ".long" for 2-byte leftovers.
 301
 302 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 303
 304         PR 25641
 305         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 306
 307 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 308
 309         * i386-dis.c (X86_64_0D): Rename to ...
 310         (X86_64_0E): ... this.
 311
 312 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 313
 314         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 315         * Makefile.in: Regenerated.
 316
 317 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 318
 319         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 320         3-operand pseudos.
 321         * i386-tbl.h: Re-generate.
 322
 323 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 324
 325         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 326         vprot*, vpsha*, and vpshl*.
 327         * i386-tbl.h: Re-generate.
 328
 329 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 330
 331         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 332         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 333         * i386-tbl.h: Re-generate.
 334
 335 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 336
 337         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 338         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 339         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 340         * i386-tbl.h: Re-generate.
 341
 342 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 343
 344         * i386-gen.c (struct template_arg, struct template_instance,
 345         struct template_param, struct template, templates,
 346         parse_template, expand_templates): New.
 347         (process_i386_opcodes): Various local variables moved to
 348         expand_templates. Call parse_template and expand_templates.
 349         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 350         * i386-tbl.h: Re-generate.
 351
 352 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 353
 354         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 355         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 356         register and memory source templates. Replace VexW= by VexW*
 357         where applicable.
 358         * i386-tbl.h: Re-generate.
 359
 360 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 361
 362         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 363         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 364         * i386-tbl.h: Re-generate.
 365
 366 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 367
 368         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 369         * i386-tbl.h: Re-generate.
 370
 371 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 372
 373         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 374         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 375         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 376         VexW0 on SSE2AVX variants.
 377         (vmovq): Drop NoRex64 from XMM/XMM variants.
 378         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 379         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 380         applicable use VexW0.
 381         * i386-tbl.h: Re-generate.
 382
 383 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 384
 385         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 386         * i386-opc.h (Rex64): Delete.
 387         (struct i386_opcode_modifier): Remove rex64 field.
 388         * i386-opc.tbl (crc32): Drop Rex64.
 389         Replace Rex64 with Size64 everywhere else.
 390         * i386-tbl.h: Re-generate.
 391
 392 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 393
 394         * i386-dis.c (OP_E_memory): Exclude recording of used address
 395         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 396         addressed memory operands for MPX insns.
 397
 398 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 399
 400         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 401         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 402         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 403         (ptwrite): Split into non-64-bit and 64-bit forms.
 404         * i386-tbl.h: Re-generate.
 405
 406 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 407
 408         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 409         template.
 410         * i386-tbl.h: Re-generate.
 411
 412 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 413
 414         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 415         (prefix_table): Move vmmcall here. Add vmgexit.
 416         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 417         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 418         (cpu_flags): Add CpuSEV_ES entry.
 419         * i386-opc.h (CpuSEV_ES): New.
 420         (union i386_cpu_flags): Add cpusev_es field.
 421         * i386-opc.tbl (vmgexit): New.
 422         * i386-init.h, i386-tbl.h: Re-generate.
 423
 424 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 425
 426         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 427         with MnemonicSize.
 428         * i386-opc.h (IGNORESIZE): New.
 429         (DEFAULTSIZE): Likewise.
 430         (IgnoreSize): Removed.
 431         (DefaultSize): Likewise.
 432         (MnemonicSize): New.
 433         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 434         mnemonicsize.
 435         * i386-opc.tbl (IgnoreSize): New.
 436         (DefaultSize): Likewise.
 437         * i386-tbl.h: Regenerated.
 438
 439 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 440
 441         PR 25627
 442         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 443         instructions.
 444
 445 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 446
 447         PR gas/25622
 448         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 449         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 450         * i386-tbl.h: Regenerated.
 451
 452 2020-02-26  Alan Modra  <amodra@gmail.com>
 453
 454         * aarch64-asm.c: Indent labels correctly.
 455         * aarch64-dis.c: Likewise.
 456         * aarch64-gen.c: Likewise.
 457         * aarch64-opc.c: Likewise.
 458         * alpha-dis.c: Likewise.
 459         * i386-dis.c: Likewise.
 460         * nds32-asm.c: Likewise.
 461         * nfp-dis.c: Likewise.
 462         * visium-dis.c: Likewise.
 463
 464 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 465
 466         * arc-regs.h (int_vector_base): Make it available for all ARC
 467         CPUs.
 468
 469 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 470
 471         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 472         changed.
 473
 474 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 475
 476         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 477         c.mv/c.li if rs1 is zero.
 478
 479 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 480
 481         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 482         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 483         CPU_POPCNT_FLAGS.
 484         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 485         * i386-opc.h (CpuABM): Removed.
 486         (CpuPOPCNT): New.
 487         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 488         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 489         popcnt.  Remove CpuABM from lzcnt.
 490         * i386-init.h: Regenerated.
 491         * i386-tbl.h: Likewise.
 492
 493 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 494
 495         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 496         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 497         VexW1 instead of open-coding them.
 498         * i386-tbl.h: Re-generate.
 499
 500 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 501
 502         * i386-opc.tbl (AddrPrefixOpReg): Define.
 503         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 504         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 505         templates. Drop NoRex64.
 506         * i386-tbl.h: Re-generate.
 507
 508 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 509
 510         PR gas/6518
 511         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 512         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 513         into Intel syntax instance (with Unpsecified) and AT&T one
 514         (without).
 515         (vcvtneps2bf16): Likewise, along with folding the two so far
 516         separate ones.
 517         * i386-tbl.h: Re-generate.
 518
 519 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 520
 521         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 522         CPU_ANY_SSE4A_FLAGS.
 523
 524 2020-02-17  Alan Modra  <amodra@gmail.com>
 525
 526         * i386-gen.c (cpu_flag_init): Correct last change.
 527
 528 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 529
 530         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 531         CPU_ANY_SSE4_FLAGS.
 532
 533 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 534
 535         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 536         (movzx): Likewise.
 537
 538 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 539
 540         PR gas/25438
 541         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 542         destination for Cpu64-only variant.
 543         (movzx): Fold patterns.
 544         * i386-tbl.h: Re-generate.
 545
 546 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 547
 548         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 549         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 550         CPU_ANY_SSE4_FLAGS entry.
 551         * i386-init.h: Re-generate.
 552
 553 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 554
 555         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 556         with Unspecified, making the present one AT&T syntax only.
 557         * i386-tbl.h: Re-generate.
 558
 559 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 560
 561         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 562         * i386-tbl.h: Re-generate.
 563
 564 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 565
 566         PR gas/24546
 567         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 568         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 569         Amd64 and Intel64 templates.
 570         (call, jmp): Likewise for far indirect variants. Dro
 571         Unspecified.
 572         * i386-tbl.h: Re-generate.
 573
 574 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 575
 576         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 577         * i386-opc.h (ShortForm): Delete.
 578         (struct i386_opcode_modifier): Remove shortform field.
 579         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 580         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 581         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 582         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 583         Drop ShortForm.
 584         * i386-tbl.h: Re-generate.
 585
 586 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 587
 588         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 589         fucompi): Drop ShortForm from operand-less templates.
 590         * i386-tbl.h: Re-generate.
 591
 592 2020-02-11  Alan Modra  <amodra@gmail.com>
 593
 594         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 595         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 596         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 597         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 598         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 599
 600 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 601
 602         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 603         (cde_opcodes): Add VCX* instructions.
 604
 605 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 606             Matthew Malcomson  <matthew.malcomson@arm.com>
 607
 608         * arm-dis.c (struct cdeopcode32): New.
 609         (CDE_OPCODE): New macro.
 610         (cde_opcodes): New disassembly table.
 611         (regnames): New option to table.
 612         (cde_coprocs): New global variable.
 613         (print_insn_cde): New
 614         (print_insn_thumb32): Use print_insn_cde.
 615         (parse_arm_disassembler_options): Parse coprocN args.
 616
 617 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 618
 619         PR gas/25516
 620         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 621         with ISA64.
 622         * i386-opc.h (AMD64): Removed.
 623         (Intel64): Likewose.
 624         (AMD64): New.
 625         (INTEL64): Likewise.
 626         (INTEL64ONLY): Likewise.
 627         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 628         * i386-opc.tbl (Amd64): New.
 629         (Intel64): Likewise.
 630         (Intel64Only): Likewise.
 631         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 632         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 633         * i386-tbl.h: Regenerated.
 634
 635 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 636
 637         PR 25469
 638         * z80-dis.c: Add support for GBZ80 opcodes.
 639
 640 2020-02-04  Alan Modra  <amodra@gmail.com>
 641
 642         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 643
 644 2020-02-03  Alan Modra  <amodra@gmail.com>
 645
 646         * m32c-ibld.c: Regenerate.
 647
 648 2020-02-01  Alan Modra  <amodra@gmail.com>
 649
 650         * frv-ibld.c: Regenerate.
 651
 652 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 653
 654         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 655         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 656         (OP_E_memory): Replace xmm_mdq_mode case label by
 657         vex_scalar_w_dq_mode one.
 658         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 659
 660 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 661
 662         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 663         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 664         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 665         (intel_operand_size): Drop vex_w_dq_mode case label.
 666
 667 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 668
 669         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 670         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 671
 672 2020-01-30  Alan Modra  <amodra@gmail.com>
 673
 674         * m32c-ibld.c: Regenerate.
 675
 676 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 677
 678         * bpf-opc.c: Regenerate.
 679
 680 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 681
 682         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 683         (dis386): Use them to replace C2/C3 table entries.
 684         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 685         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 686         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 687         * i386-tbl.h: Re-generate.
 688
 689 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 690
 691         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 692         forms.
 693         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 694         DefaultSize.
 695         * i386-tbl.h: Re-generate.
 696
 697 2020-01-30  Alan Modra  <amodra@gmail.com>
 698
 699         * tic4x-dis.c (tic4x_dp): Make unsigned.
 700
 701 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 702             Jan Beulich  <jbeulich@suse.com>
 703
 704         PR binutils/25445
 705         * i386-dis.c (MOVSXD_Fixup): New function.
 706         (movsxd_mode): New enum.
 707         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 708         (intel_operand_size): Handle movsxd_mode.
 709         (OP_E_register): Likewise.
 710         (OP_G): Likewise.
 711         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 712         register on movsxd.  Add movsxd with 16-bit destination register
 713         for AMD64 and Intel64 ISAs.
 714         * i386-tbl.h: Regenerated.
 715
 716 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 717
 718         PR 25403
 719         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 720         * aarch64-asm-2.c: Regenerate
 721         * aarch64-dis-2.c: Likewise.
 722         * aarch64-opc-2.c: Likewise.
 723
 724 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 725
 726         * i386-opc.tbl (sysret): Drop DefaultSize.
 727         * i386-tbl.h: Re-generate.
 728
 729 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 730
 731         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 732         Dword.
 733         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 734         * i386-tbl.h: Re-generate.
 735
 736 2020-01-20  Nick Clifton  <nickc@redhat.com>
 737
 738         * po/de.po: Updated German translation.
 739         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 740         * po/uk.po: Updated Ukranian translation.
 741
 742 2020-01-20  Alan Modra  <amodra@gmail.com>
 743
 744         * hppa-dis.c (fput_const): Remove useless cast.
 745
 746 2020-01-20  Alan Modra  <amodra@gmail.com>
 747
 748         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 749
 750 2020-01-18  Nick Clifton  <nickc@redhat.com>
 751
 752         * configure: Regenerate.
 753         * po/opcodes.pot: Regenerate.
 754
 755 2020-01-18  Nick Clifton  <nickc@redhat.com>
 756
 757         Binutils 2.34 branch created.
 758
 759 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 760
 761         * opintl.h: Fix spelling error (seperate).
 762
 763 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 764
 765         * i386-opc.tbl: Add {vex} pseudo prefix.
 766         * i386-tbl.h: Regenerated.
 767
 768 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 769
 770         PR 25376
 771         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 772         (neon_opcodes): Likewise.
 773         (select_arm_features): Make sure we enable MVE bits when selecting
 774         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 775         any architecture.
 776
 777 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 778
 779         * i386-opc.tbl: Drop stale comment from XOP section.
 780
 781 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 782
 783         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 784         (extractps): Add VexWIG to SSE2AVX forms.
 785         * i386-tbl.h: Re-generate.
 786
 787 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 788
 789         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 790         Size64 from and use VexW1 on SSE2AVX forms.
 791         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 792         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 793         * i386-tbl.h: Re-generate.
 794
 795 2020-01-15  Alan Modra  <amodra@gmail.com>
 796
 797         * tic4x-dis.c (tic4x_version): Make unsigned long.
 798         (optab, optab_special, registernames): New file scope vars.
 799         (tic4x_print_register): Set up registernames rather than
 800         malloc'd registertable.
 801         (tic4x_disassemble): Delete optable and optable_special.  Use
 802         optab and optab_special instead.  Throw away old optab,
 803         optab_special and registernames when info->mach changes.
 804
 805 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 806
 807         PR 25377
 808         * z80-dis.c (suffix): Use .db instruction to generate double
 809         prefix.
 810
 811 2020-01-14  Alan Modra  <amodra@gmail.com>
 812
 813         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 814         values to unsigned before shifting.
 815
 816 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 817
 818         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 819         flow instructions.
 820         (print_insn_thumb16, print_insn_thumb32): Likewise.
 821         (print_insn): Initialize the insn info.
 822         * i386-dis.c (print_insn): Initialize the insn info fields, and
 823         detect jumps.
 824
 825 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 826
 827         * arc-opc.c (C_NE): Make it required.
 828
 829 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 830
 831         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 832         reserved register name.
 833
 834 2020-01-13  Alan Modra  <amodra@gmail.com>
 835
 836         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 837         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 838
 839 2020-01-13  Alan Modra  <amodra@gmail.com>
 840
 841         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 842         result of wasm_read_leb128 in a uint64_t and check that bits
 843         are not lost when copying to other locals.  Use uint32_t for
 844         most locals.  Use PRId64 when printing int64_t.
 845
 846 2020-01-13  Alan Modra  <amodra@gmail.com>
 847
 848         * score-dis.c: Formatting.
 849         * score7-dis.c: Formatting.
 850
 851 2020-01-13  Alan Modra  <amodra@gmail.com>
 852
 853         * score-dis.c (print_insn_score48): Use unsigned variables for
 854         unsigned values.  Don't left shift negative values.
 855         (print_insn_score32): Likewise.
 856         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 857
 858 2020-01-13  Alan Modra  <amodra@gmail.com>
 859
 860         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 861
 862 2020-01-13  Alan Modra  <amodra@gmail.com>
 863
 864         * fr30-ibld.c: Regenerate.
 865
 866 2020-01-13  Alan Modra  <amodra@gmail.com>
 867
 868         * xgate-dis.c (print_insn): Don't left shift signed value.
 869         (ripBits): Formatting, use 1u.
 870
 871 2020-01-10  Alan Modra  <amodra@gmail.com>
 872
 873         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 874         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 875
 876 2020-01-10  Alan Modra  <amodra@gmail.com>
 877
 878         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 879         and XRREG value earlier to avoid a shift with negative exponent.
 880         * m10200-dis.c (disassemble): Similarly.
 881
 882 2020-01-09  Nick Clifton  <nickc@redhat.com>
 883
 884         PR 25224
 885         * z80-dis.c (ld_ii_ii): Use correct cast.
 886
 887 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 888
 889         PR 25224
 890         * z80-dis.c (ld_ii_ii): Use character constant when checking
 891         opcode byte value.
 892
 893 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 894
 895         * i386-dis.c (SEP_Fixup): New.
 896         (SEP): Define.
 897         (dis386_twobyte): Use it for sysenter/sysexit.
 898         (enum x86_64_isa): Change amd64 enumerator to value 1.
 899         (OP_J): Compare isa64 against intel64 instead of amd64.
 900         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 901         forms.
 902         * i386-tbl.h: Re-generate.
 903
 904 2020-01-08  Alan Modra  <amodra@gmail.com>
 905
 906         * z8k-dis.c: Include libiberty.h
 907         (instr_data_s): Make max_fetched unsigned.
 908         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 909         Don't exceed byte_info bounds.
 910         (output_instr): Make num_bytes unsigned.
 911         (unpack_instr): Likewise for nibl_count and loop.
 912         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 913         idx unsigned.
 914         * z8k-opc.h: Regenerate.
 915
 916 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 917
 918         * arc-tbl.h (llock): Use 'LLOCK' as class.
 919         (llockd): Likewise.
 920         (scond): Use 'SCOND' as class.
 921         (scondd): Likewise.
 922         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 923         (scondd): Likewise.
 924
 925 2020-01-06  Alan Modra  <amodra@gmail.com>
 926
 927         * m32c-ibld.c: Regenerate.
 928
 929 2020-01-06  Alan Modra  <amodra@gmail.com>
 930
 931         PR 25344
 932         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 933         Peek at next byte to prevent recursion on repeated prefix bytes.
 934         Ensure uninitialised "mybuf" is not accessed.
 935         (print_insn_z80): Don't zero n_fetch and n_used here,..
 936         (print_insn_z80_buf): ..do it here instead.
 937
 938 2020-01-04  Alan Modra  <amodra@gmail.com>
 939
 940         * m32r-ibld.c: Regenerate.
 941
 942 2020-01-04  Alan Modra  <amodra@gmail.com>
 943
 944         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 945
 946 2020-01-04  Alan Modra  <amodra@gmail.com>
 947
 948         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 949
 950 2020-01-04  Alan Modra  <amodra@gmail.com>
 951
 952         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 953
 954 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 955
 956         * aarch64-tbl.h (aarch64_opcode_table): Use
 957         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 958
 959 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 960
 961         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 962         forms of SUDOT and USDOT.
 963
 964 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 965
 966         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 967         uzip{1,2}.
 968         * opcodes/aarch64-dis-2.c: Re-generate.
 969
 970 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 971
 972         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 973         FMMLA encoding.
 974         * opcodes/aarch64-dis-2.c: Re-generate.
 975
 976 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 977
 978         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 979
 980 2020-01-01  Alan Modra  <amodra@gmail.com>
 981
 982         Update year range in copyright notice of all files.
 983
 984 For older changes see ChangeLog-2019
 985 \f
 986 Copyright (C) 2020 Free Software Foundation, Inc.
 987
 988 Copying and distribution of this file, with or without modification,
 989 are permitted in any medium without royalty provided the copyright
 990 notice and this notice are preserved.
 991
 992 Local Variables:
 993 mode: change-log
 994 left-margin: 8
 995 fill-column: 74
 996 version-control: never
 997 End: