opcodes/ChangeLog

   1 2019-07-16  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-gen.c (operand_types): Move RegMem ...
   4         (opcode_modifiers): ... here.
   5         * i386-opc.h (RegMem): Move to opcode modifer enum.
   6         (union i386_operand_type): Move regmem field ...
   7         (struct i386_opcode_modifier): ... here.
   8         * i386-opc.tbl (RegMem): Define.
   9         (mov, movq): Move RegMem on segment, control, debug, and test
  10         register flavors.
  11         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
  12         to non-SSE2AVX flavor.
  13         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
  14         Move RegMem on register only flavors. Drop IgnoreSize from
  15         legacy encoding flavors.
  16         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
  17         flavors.
  18         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
  19         register only flavors.
  20         (vmovd): Move RegMem and drop IgnoreSize on register only
  21         flavor. Change opcode and operand order to store form.
  22         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
  23
  24 2019-07-16  Jan Beulich  <jbeulich@suse.com>
  25
  26         * i386-gen.c (operand_type_init, operand_types): Replace SReg
  27         entries.
  28         * i386-opc.h (SReg2, SReg3): Replace by ...
  29         (SReg): ... this.
  30         (union i386_operand_type): Replace sreg fields.
  31         * i386-opc.tbl (mov, ): Use SReg.
  32         (push, pop): Likewies. Drop i386 and x86-64 specific segment
  33         register flavors.
  34         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
  35         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
  36
  37 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
  38
  39         * bpf-desc.c: Regenerate.
  40         * bpf-opc.c: Likewise.
  41         * bpf-opc.h: Likewise.
  42
  43 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
  44
  45         * bpf-desc.c: Regenerate.
  46         * bpf-opc.c: Likewise.
  47
  48 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
  49
  50         * arm-dis.c (print_insn_coprocessor): Rename index to
  51         index_operand.
  52
  53 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
  54
  55         * riscv-opc.c (riscv_insn_types): Add r4 type.
  56
  57         * riscv-opc.c (riscv_insn_types): Add b and j type.
  58
  59         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
  60         format for sb type and correct s type.
  61
  62 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
  63
  64         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
  65         SVE FMOV alias of FCPY.
  66
  67 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
  68
  69         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
  70         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
  71
  72 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
  73
  74         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
  75         registers in an instruction prefixed by MOVPRFX.
  76
  77 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
  78
  79         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
  80         sve_size_13 icode to account for variant behaviour of
  81         pmull{t,b}.
  82         * aarch64-dis-2.c: Regenerate.
  83         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
  84         sve_size_13 icode to account for variant behaviour of
  85         pmull{t,b}.
  86         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
  87         (OP_SVE_VVV_Q_D): Add new qualifier.
  88         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
  89         (struct aarch64_opcode): Split pmull{t,b} into those requiring
  90         AES and those not.
  91
  92 2019-07-01  Jan Beulich  <jbeulich@suse.com>
  93
  94         * opcodes/i386-gen.c (operand_type_init): Remove
  95         OPERAND_TYPE_VEC_IMM4 entry.
  96         (operand_types): Remove Vec_Imm4.
  97         * opcodes/i386-opc.h (Vec_Imm4): Delete.
  98         (union i386_operand_type): Remove vec_imm4.
  99         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 100         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 101
 102 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 103
 104         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 105         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 106         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 107         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 108         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 109         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 110         * i386-tbl.h: Re-generate.
 111
 112 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 113
 114         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 115         register operands.
 116         * i386-tbl.h: Re-generate.
 117
 118 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 119
 120         * i386-opc.tbl (C): New.
 121         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 122         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 123         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 124         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 125         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 126         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 127         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 128         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 129         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 130         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 131         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 132         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 133         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 134         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 135         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 136         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 137         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 138         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 139         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 140         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 141         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 142         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 143         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 144         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 145         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 146         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 147         flavors.
 148         * i386-tbl.h: Re-generate.
 149
 150 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 151
 152         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 153         register operands.
 154         * i386-tbl.h: Re-generate.
 155
 156 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 157
 158         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 159         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 160         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 161         * i386-tbl.h: Re-generate.
 162
 163 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 164
 165         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 166         Disp8MemShift from register only templates.
 167         * i386-tbl.h: Re-generate.
 168
 169 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 170
 171         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 172         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 173         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 174         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 175         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 176         EVEX_W_0F11_P_3_M_1): Delete.
 177         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 178         EVEX_W_0F11_P_3): New.
 179         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 180         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 181         MOD_EVEX_0F11_PREFIX_3 table entries.
 182         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 183         PREFIX_EVEX_0F11 table entries.
 184         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 185         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 186         EVEX_W_0F11_P_3_M_{0,1} table entries.
 187
 188 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 189
 190         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 191         Delete.
 192
 193 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 194
 195         PR binutils/24719
 196         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 197         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 198         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 199         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 200         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 201         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 202         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 203         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 204         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 205         PREFIX_EVEX_0F38C6_REG_6 entries.
 206         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 207         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 208         EVEX_W_0F38C7_R_6_P_2 entries.
 209         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 210         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 211         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 212         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 213         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 214         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 215         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 216
 217 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 218
 219         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 220         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 221         VEX_LEN_0F2D_P_3): Delete.
 222         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 223         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 224         (prefix_table): ... here.
 225
 226 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 227
 228         * i386-dis.c (Iq): Delete.
 229         (Id): New.
 230         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 231         TBM insns.
 232         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 233         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 234         (OP_E_memory): Also honor needindex when deciding whether an
 235         address size prefix needs printing.
 236         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 237
 238 2019-06-26  Jim Wilson  <jimw@sifive.com>
 239
 240         PR binutils/24739
 241         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 242         Set info->display_endian to info->endian_code.
 243
 244 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 245
 246         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 247         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 248         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 249         OPERAND_TYPE_ACC64 entries.
 250         * i386-init.h: Re-generate.
 251
 252 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 253
 254         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 255         Delete.
 256         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 257         of dqa_mode.
 258         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 259         entries here.
 260         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 261         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 262
 263 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 264
 265         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 266         variables.
 267
 268 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 269
 270         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 271         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 272         movnti.
 273         * i386-opc.tbl (movnti): Add IgnoreSize.
 274         * i386-tbl.h: Re-generate.
 275
 276 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 277
 278         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 279         * i386-tbl.h: Re-generate.
 280
 281 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 282
 283         * i386-dis-evex.h: Break into ...
 284         * i386-dis-evex-len.h: New file.
 285         * i386-dis-evex-mod.h: Likewise.
 286         * i386-dis-evex-prefix.h: Likewise.
 287         * i386-dis-evex-reg.h: Likewise.
 288         * i386-dis-evex-w.h: Likewise.
 289         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 290         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 291         i386-dis-evex-mod.h.
 292
 293 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 294
 295         PR binutils/24700
 296         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 297         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 298         EVEX_W_0F385B_P_2.
 299         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 300         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 301         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 302         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 303         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 304         EVEX_LEN_0F385B_P_2_W_1.
 305         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 306         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 307         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 308         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 309         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 310         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 311         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 312         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 313         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 314         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 315
 316 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 317
 318         PR binutils/24691
 319         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 320         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 321         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 322         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 323         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 324         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 325         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 326         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 327         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 328         EVEX_LEN_0F3A43_P_2_W_1.
 329         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 330         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 331         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 332         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 333         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 334         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 335         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 336         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 337         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 338         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 339         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 340         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 341
 342 2019-06-14  Nick Clifton  <nickc@redhat.com>
 343
 344         * po/fr.po; Updated French translation.
 345
 346 2019-06-13  Stafford Horne  <shorne@gmail.com>
 347
 348         * or1k-asm.c: Regenerated.
 349         * or1k-desc.c: Regenerated.
 350         * or1k-desc.h: Regenerated.
 351         * or1k-dis.c: Regenerated.
 352         * or1k-ibld.c: Regenerated.
 353         * or1k-opc.c: Regenerated.
 354         * or1k-opc.h: Regenerated.
 355         * or1k-opinst.c: Regenerated.
 356
 357 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 358
 359         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 360
 361 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 362
 363         PR binutils/24633
 364         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 365         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 366         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 367         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 368         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 369         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 370         EVEX_LEN_0F3A1B_P_2_W_1.
 371         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 372         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 373         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 374         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 375         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 376         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 377         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 378         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 379
 380 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 381
 382         PR binutils/24626
 383         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 384         EVEX.vvvv when disassembling VEX and EVEX instructions.
 385         (OP_VEX): Set vex.register_specifier to 0 after readding
 386         vex.register_specifier.
 387         (OP_Vex_2src_1): Likewise.
 388         (OP_Vex_2src_2): Likewise.
 389         (OP_LWP_E): Likewise.
 390         (OP_EX_Vex): Don't check vex.register_specifier.
 391         (OP_XMM_Vex): Likewise.
 392
 393 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 394             Lili Cui  <lili.cui@intel.com>
 395
 396         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 397         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 398         instructions.
 399         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 400         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 401         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 402         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 403         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 404         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 405         * i386-init.h: Regenerated.
 406         * i386-tbl.h: Likewise.
 407
 408 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 409             Lili Cui  <lili.cui@intel.com>
 410
 411         * doc/c-i386.texi: Document enqcmd.
 412         * testsuite/gas/i386/enqcmd-intel.d: New file.
 413         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 414         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 415         * testsuite/gas/i386/enqcmd.d: Likewise.
 416         * testsuite/gas/i386/enqcmd.s: Likewise.
 417         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 418         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 419         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 420         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 421         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 422         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 423         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 424         and x86-64-enqcmd.
 425
 426 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 427
 428         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 429
 430 2019-06-03  Alan Modra  <amodra@gmail.com>
 431
 432         * ppc-dis.c (prefix_opcd_indices): Correct size.
 433
 434 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 435
 436         PR gas/24625
 437         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 438         Disp8ShiftVL.
 439         * i386-tbl.h: Regenerated.
 440
 441 2019-05-24  Alan Modra  <amodra@gmail.com>
 442
 443         * po/POTFILES.in: Regenerate.
 444
 445 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 446             Alan Modra  <amodra@gmail.com>
 447
 448         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 449         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 450         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 451         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 452         XTOP>): Define and add entries.
 453         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 454         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 455         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 456         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 457
 458 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 459             Alan Modra  <amodra@gmail.com>
 460
 461         * ppc-dis.c (ppc_opts): Add "future" entry.
 462         (PREFIX_OPCD_SEGS): Define.
 463         (prefix_opcd_indices): New array.
 464         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 465         (lookup_prefix): New function.
 466         (print_insn_powerpc): Handle 64-bit prefix instructions.
 467         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 468         (PMRR, POWERXX): Define.
 469         (prefix_opcodes): New instruction table.
 470         (prefix_num_opcodes): New constant.
 471
 472 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 473
 474         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 475         * configure: Regenerated.
 476         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 477         and cpu/bpf.opc.
 478         (HFILES): Add bpf-desc.h and bpf-opc.h.
 479         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 480         bpf-ibld.c and bpf-opc.c.
 481         (BPF_DEPS): Define.
 482         * Makefile.in: Regenerated.
 483         * disassemble.c (ARCH_bpf): Define.
 484         (disassembler): Add case for bfd_arch_bpf.
 485         (disassemble_init_for_target): Likewise.
 486         (enum epbf_isa_attr): Define.
 487         * disassemble.h: extern print_insn_bpf.
 488         * bpf-asm.c: Generated.
 489         * bpf-opc.h: Likewise.
 490         * bpf-opc.c: Likewise.
 491         * bpf-ibld.c: Likewise.
 492         * bpf-dis.c: Likewise.
 493         * bpf-desc.h: Likewise.
 494         * bpf-desc.c: Likewise.
 495
 496 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 497
 498         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 499         and VMSR with the new operands.
 500
 501 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 502
 503         * arm-dis.c (enum mve_instructions): New enum
 504         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 505         and cneg.
 506         (mve_opcodes): New instructions as above.
 507         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 508         csneg and csel.
 509         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 510
 511 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 512
 513         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 514         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 515         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 516         uqshl, urshrl and urshr.
 517         (is_mve_okay_in_it): Add new instructions to TRUE list.
 518         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 519         (print_insn_mve): Updated to accept new %j,
 520         %<bitfield>m and %<bitfield>n patterns.
 521
 522 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 523
 524         * mips-opc.c (mips_builtin_opcodes): Change source register
 525         constraint for DAUI.
 526
 527 2019-05-20  Nick Clifton  <nickc@redhat.com>
 528
 529         * po/fr.po: Updated French translation.
 530
 531 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 532             Michael Collison <michael.collison@arm.com>
 533
 534         * arm-dis.c (thumb32_opcodes): Add new instructions.
 535         (enum mve_instructions): Likewise.
 536         (enum mve_undefined): Add new reasons.
 537         (is_mve_encoding_conflict): Handle new instructions.
 538         (is_mve_undefined): Likewise.
 539         (is_mve_unpredictable): Likewise.
 540         (print_mve_undefined): Likewise.
 541         (print_mve_size): Likewise.
 542
 543 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 544             Michael Collison <michael.collison@arm.com>
 545
 546         * arm-dis.c (thumb32_opcodes): Add new instructions.
 547         (enum mve_instructions): Likewise.
 548         (is_mve_encoding_conflict): Handle new instructions.
 549         (is_mve_undefined): Likewise.
 550         (is_mve_unpredictable): Likewise.
 551         (print_mve_size): Likewise.
 552
 553 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 554             Michael Collison <michael.collison@arm.com>
 555
 556         * arm-dis.c (thumb32_opcodes): Add new instructions.
 557         (enum mve_instructions): Likewise.
 558         (is_mve_encoding_conflict): Likewise.
 559         (is_mve_unpredictable): Likewise.
 560         (print_mve_size): Likewise.
 561
 562 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 563             Michael Collison <michael.collison@arm.com>
 564
 565         * arm-dis.c (thumb32_opcodes): Add new instructions.
 566         (enum mve_instructions): Likewise.
 567         (is_mve_encoding_conflict): Handle new instructions.
 568         (is_mve_undefined): Likewise.
 569         (is_mve_unpredictable): Likewise.
 570         (print_mve_size): Likewise.
 571
 572 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 573             Michael Collison <michael.collison@arm.com>
 574
 575         * arm-dis.c (thumb32_opcodes): Add new instructions.
 576         (enum mve_instructions): Likewise.
 577         (is_mve_encoding_conflict): Handle new instructions.
 578         (is_mve_undefined): Likewise.
 579         (is_mve_unpredictable): Likewise.
 580         (print_mve_size): Likewise.
 581         (print_insn_mve): Likewise.
 582
 583 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 584             Michael Collison <michael.collison@arm.com>
 585
 586         * arm-dis.c (thumb32_opcodes): Add new instructions.
 587         (print_insn_thumb32): Handle new instructions.
 588
 589 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 590             Michael Collison <michael.collison@arm.com>
 591
 592         * arm-dis.c (enum mve_instructions): Add new instructions.
 593         (enum mve_undefined): Add new reasons.
 594         (is_mve_encoding_conflict): Handle new instructions.
 595         (is_mve_undefined): Likewise.
 596         (is_mve_unpredictable): Likewise.
 597         (print_mve_undefined): Likewise.
 598         (print_mve_size): Likewise.
 599         (print_mve_shift_n): Likewise.
 600         (print_insn_mve): Likewise.
 601
 602 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 603             Michael Collison <michael.collison@arm.com>
 604
 605         * arm-dis.c (enum mve_instructions): Add new instructions.
 606         (is_mve_encoding_conflict): Handle new instructions.
 607         (is_mve_unpredictable): Likewise.
 608         (print_mve_rotate): Likewise.
 609         (print_mve_size): Likewise.
 610         (print_insn_mve): Likewise.
 611
 612 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 613             Michael Collison <michael.collison@arm.com>
 614
 615         * arm-dis.c (enum mve_instructions): Add new instructions.
 616         (is_mve_encoding_conflict): Handle new instructions.
 617         (is_mve_unpredictable): Likewise.
 618         (print_mve_size): Likewise.
 619         (print_insn_mve): Likewise.
 620
 621 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 622             Michael Collison <michael.collison@arm.com>
 623
 624         * arm-dis.c (enum mve_instructions): Add new instructions.
 625         (enum mve_undefined): Add new reasons.
 626         (is_mve_encoding_conflict): Handle new instructions.
 627         (is_mve_undefined): Likewise.
 628         (is_mve_unpredictable): Likewise.
 629         (print_mve_undefined): Likewise.
 630         (print_mve_size): Likewise.
 631         (print_insn_mve): Likewise.
 632
 633 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 634             Michael Collison <michael.collison@arm.com>
 635
 636         * arm-dis.c (enum mve_instructions): Add new instructions.
 637         (is_mve_encoding_conflict): Handle new instructions.
 638         (is_mve_undefined): Likewise.
 639         (is_mve_unpredictable): Likewise.
 640         (print_mve_size): Likewise.
 641         (print_insn_mve): Likewise.
 642
 643 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 644             Michael Collison <michael.collison@arm.com>
 645
 646         * arm-dis.c (enum mve_instructions): Add new instructions.
 647         (enum mve_unpredictable): Add new reasons.
 648         (enum mve_undefined): Likewise.
 649         (is_mve_okay_in_it): Handle new isntructions.
 650         (is_mve_encoding_conflict): Likewise.
 651         (is_mve_undefined): Likewise.
 652         (is_mve_unpredictable): Likewise.
 653         (print_mve_vmov_index): Likewise.
 654         (print_simd_imm8): Likewise.
 655         (print_mve_undefined): Likewise.
 656         (print_mve_unpredictable): Likewise.
 657         (print_mve_size): Likewise.
 658         (print_insn_mve): Likewise.
 659
 660 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 661             Michael Collison <michael.collison@arm.com>
 662
 663         * arm-dis.c (enum mve_instructions): Add new instructions.
 664         (enum mve_unpredictable): Add new reasons.
 665         (enum mve_undefined): Likewise.
 666         (is_mve_encoding_conflict): Handle new instructions.
 667         (is_mve_undefined): Likewise.
 668         (is_mve_unpredictable): Likewise.
 669         (print_mve_undefined): Likewise.
 670         (print_mve_unpredictable): Likewise.
 671         (print_mve_rounding_mode): Likewise.
 672         (print_mve_vcvt_size): Likewise.
 673         (print_mve_size): Likewise.
 674         (print_insn_mve): Likewise.
 675
 676 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 677             Michael Collison <michael.collison@arm.com>
 678
 679         * arm-dis.c (enum mve_instructions): Add new instructions.
 680         (enum mve_unpredictable): Add new reasons.
 681         (enum mve_undefined): Likewise.
 682         (is_mve_undefined): Handle new instructions.
 683         (is_mve_unpredictable): Likewise.
 684         (print_mve_undefined): Likewise.
 685         (print_mve_unpredictable): Likewise.
 686         (print_mve_size): Likewise.
 687         (print_insn_mve): Likewise.
 688
 689 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 690             Michael Collison <michael.collison@arm.com>
 691
 692         * arm-dis.c (enum mve_instructions): Add new instructions.
 693         (enum mve_undefined): Add new reasons.
 694         (insns): Add new instructions.
 695         (is_mve_encoding_conflict):
 696         (print_mve_vld_str_addr): New print function.
 697         (is_mve_undefined): Handle new instructions.
 698         (is_mve_unpredictable): Likewise.
 699         (print_mve_undefined): Likewise.
 700         (print_mve_size): Likewise.
 701         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 702         (print_insn_mve):  Handle new operands.
 703
 704 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 705             Michael Collison <michael.collison@arm.com>
 706
 707         * arm-dis.c (enum mve_instructions): Add new instructions.
 708         (enum mve_unpredictable): Add new reasons.
 709         (is_mve_encoding_conflict): Handle new instructions.
 710         (is_mve_unpredictable): Likewise.
 711         (mve_opcodes): Add new instructions.
 712         (print_mve_unpredictable): Handle new reasons.
 713         (print_mve_register_blocks): New print function.
 714         (print_mve_size): Handle new instructions.
 715         (print_insn_mve): Likewise.
 716
 717 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 718             Michael Collison <michael.collison@arm.com>
 719
 720         * arm-dis.c (enum mve_instructions): Add new instructions.
 721         (enum mve_unpredictable): Add new reasons.
 722         (enum mve_undefined): Likewise.
 723         (is_mve_encoding_conflict): Handle new instructions.
 724         (is_mve_undefined): Likewise.
 725         (is_mve_unpredictable): Likewise.
 726         (coprocessor_opcodes): Move NEON VDUP from here...
 727         (neon_opcodes): ... to here.
 728         (mve_opcodes): Add new instructions.
 729         (print_mve_undefined):  Handle new reasons.
 730         (print_mve_unpredictable): Likewise.
 731         (print_mve_size): Handle new instructions.
 732         (print_insn_neon): Handle vdup.
 733         (print_insn_mve): Handle new operands.
 734
 735 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 736             Michael Collison <michael.collison@arm.com>
 737
 738         * arm-dis.c (enum mve_instructions): Add new instructions.
 739         (enum mve_unpredictable): Add new values.
 740         (mve_opcodes): Add new instructions.
 741         (vec_condnames): New array with vector conditions.
 742         (mve_predicatenames): New array with predicate suffixes.
 743         (mve_vec_sizename): New array with vector sizes.
 744         (enum vpt_pred_state): New enum with vector predication states.
 745         (struct vpt_block): New struct type for vpt blocks.
 746         (vpt_block_state): Global struct to keep track of state.
 747         (mve_extract_pred_mask): New helper function.
 748         (num_instructions_vpt_block): Likewise.
 749         (mark_outside_vpt_block): Likewise.
 750         (mark_inside_vpt_block): Likewise.
 751         (invert_next_predicate_state): Likewise.
 752         (update_next_predicate_state): Likewise.
 753         (update_vpt_block_state): Likewise.
 754         (is_vpt_instruction): Likewise.
 755         (is_mve_encoding_conflict): Add entries for new instructions.
 756         (is_mve_unpredictable): Likewise.
 757         (print_mve_unpredictable): Handle new cases.
 758         (print_instruction_predicate): Likewise.
 759         (print_mve_size): New function.
 760         (print_vec_condition): New function.
 761         (print_insn_mve): Handle vpt blocks and new print operands.
 762
 763 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 764
 765         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 766         8, 14 and 15 for Armv8.1-M Mainline.
 767
 768 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 769             Michael Collison <michael.collison@arm.com>
 770
 771         * arm-dis.c (enum mve_instructions): New enum.
 772         (enum mve_unpredictable): Likewise.
 773         (enum mve_undefined): Likewise.
 774         (struct mopcode32): New struct.
 775         (is_mve_okay_in_it): New function.
 776         (is_mve_architecture): Likewise.
 777         (arm_decode_field): Likewise.
 778         (arm_decode_field_multiple): Likewise.
 779         (is_mve_encoding_conflict): Likewise.
 780         (is_mve_undefined): Likewise.
 781         (is_mve_unpredictable): Likewise.
 782         (print_mve_undefined): Likewise.
 783         (print_mve_unpredictable): Likewise.
 784         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 785         (print_insn_mve): New function.
 786         (print_insn_thumb32): Handle MVE architecture.
 787         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 788
 789 2019-05-10  Nick Clifton  <nickc@redhat.com>
 790
 791         PR 24538
 792         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 793         end of the table prematurely.
 794
 795 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 796
 797         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 798         macros for R6.
 799
 800 2019-05-11  Alan Modra  <amodra@gmail.com>
 801
 802         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 803         when -Mraw is in effect.
 804
 805 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 806
 807         * aarch64-dis-2.c: Regenerate.
 808         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 809         (OP_SVE_BBB): New variant set.
 810         (OP_SVE_DDDD): New variant set.
 811         (OP_SVE_HHH): New variant set.
 812         (OP_SVE_HHHU): New variant set.
 813         (OP_SVE_SSS): New variant set.
 814         (OP_SVE_SSSU): New variant set.
 815         (OP_SVE_SHH): New variant set.
 816         (OP_SVE_SBBU): New variant set.
 817         (OP_SVE_DSS): New variant set.
 818         (OP_SVE_DHHU): New variant set.
 819         (OP_SVE_VMV_HSD_BHS): New variant set.
 820         (OP_SVE_VVU_HSD_BHS): New variant set.
 821         (OP_SVE_VVVU_SD_BH): New variant set.
 822         (OP_SVE_VVVU_BHSD): New variant set.
 823         (OP_SVE_VVV_QHD_DBS): New variant set.
 824         (OP_SVE_VVV_HSD_BHS): New variant set.
 825         (OP_SVE_VVV_HSD_BHS2): New variant set.
 826         (OP_SVE_VVV_BHS_HSD): New variant set.
 827         (OP_SVE_VV_BHS_HSD): New variant set.
 828         (OP_SVE_VVV_SD): New variant set.
 829         (OP_SVE_VVU_BHS_HSD): New variant set.
 830         (OP_SVE_VZVV_SD): New variant set.
 831         (OP_SVE_VZVV_BH): New variant set.
 832         (OP_SVE_VZV_SD): New variant set.
 833         (aarch64_opcode_table): Add sve2 instructions.
 834
 835 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 836
 837         * aarch64-asm-2.c: Regenerated.
 838         * aarch64-dis-2.c: Regenerated.
 839         * aarch64-opc-2.c: Regenerated.
 840         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 841         for SVE_SHLIMM_UNPRED_22.
 842         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 843         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 844         operand.
 845
 846 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 847
 848         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 849         sve_size_tsz_bhs iclass encode.
 850         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 851         sve_size_tsz_bhs iclass decode.
 852
 853 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 854
 855         * aarch64-asm-2.c: Regenerated.
 856         * aarch64-dis-2.c: Regenerated.
 857         * aarch64-opc-2.c: Regenerated.
 858         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 859         for SVE_Zm4_11_INDEX.
 860         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 861         (fields): Handle SVE_i2h field.
 862         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 863         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 864
 865 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 866
 867         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 868         sve_shift_tsz_bhsd iclass encode.
 869         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 870         sve_shift_tsz_bhsd iclass decode.
 871
 872 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 873
 874         * aarch64-asm-2.c: Regenerated.
 875         * aarch64-dis-2.c: Regenerated.
 876         * aarch64-opc-2.c: Regenerated.
 877         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 878         (aarch64_encode_variant_using_iclass): Handle
 879         sve_shift_tsz_hsd iclass encode.
 880         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 881         sve_shift_tsz_hsd iclass decode.
 882         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 883         for SVE_SHRIMM_UNPRED_22.
 884         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 885         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 886         operand.
 887
 888 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 889
 890         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 891         sve_size_013 iclass encode.
 892         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 893         sve_size_013 iclass decode.
 894
 895 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 896
 897         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 898         sve_size_bh iclass encode.
 899         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 900         sve_size_bh iclass decode.
 901
 902 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 903
 904         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 905         sve_size_sd2 iclass encode.
 906         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 907         sve_size_sd2 iclass decode.
 908         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 909         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 910
 911 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 912
 913         * aarch64-asm-2.c: Regenerated.
 914         * aarch64-dis-2.c: Regenerated.
 915         * aarch64-opc-2.c: Regenerated.
 916         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 917         for SVE_ADDR_ZX.
 918         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 919         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 920
 921 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 922
 923         * aarch64-asm-2.c: Regenerated.
 924         * aarch64-dis-2.c: Regenerated.
 925         * aarch64-opc-2.c: Regenerated.
 926         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 927         for SVE_Zm3_11_INDEX.
 928         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 929         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 930         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 931         fields.
 932         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 933
 934 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 935
 936         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 937         sve_size_hsd2 iclass encode.
 938         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 939         sve_size_hsd2 iclass decode.
 940         * aarch64-opc.c (fields): Handle SVE_size field.
 941         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 942
 943 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 944
 945         * aarch64-asm-2.c: Regenerated.
 946         * aarch64-dis-2.c: Regenerated.
 947         * aarch64-opc-2.c: Regenerated.
 948         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 949         for SVE_IMM_ROT3.
 950         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 951         (fields): Handle SVE_rot3 field.
 952         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 953         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 954
 955 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 956
 957         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 958         instructions.
 959
 960 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 961
 962         * aarch64-tbl.h
 963         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 964         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 965         aarch64_feature_sve2bitperm): New feature sets.
 966         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 967         for feature set addresses.
 968         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 969         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 970
 971 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 972             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 973
 974         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 975         argument and set ASE_EVA_R6 appropriately.
 976         (set_default_mips_dis_options): Pass ISA to above.
 977         (parse_mips_dis_option): Likewise.
 978         * mips-opc.c (EVAR6): New macro.
 979         (mips_builtin_opcodes): Add llwpe, scwpe.
 980
 981 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 982
 983         * aarch64-asm-2.c: Regenerated.
 984         * aarch64-dis-2.c: Regenerated.
 985         * aarch64-opc-2.c: Regenerated.
 986         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 987         AARCH64_OPND_TME_UIMM16.
 988         (aarch64_print_operand): Likewise.
 989         * aarch64-tbl.h (QL_IMM_NIL): New.
 990         (TME): New.
 991         (_TME_INSN): New.
 992         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 993
 994 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 995
 996         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 997
 998 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 999             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1000
1001         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1002
1003 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1004
1005         * s12z-opc.h: Add extern "C" bracketing to help
1006         users who wish to use this interface in c++ code.
1007
1008 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1009
1010         * s12z-opc.c (bm_decode): Handle bit map operations with the
1011         "reserved0" mode.
1012
1013 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1014
1015         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1016         specifier.  Add entries for VLDR and VSTR of system registers.
1017         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1018         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1019         of %J and %K format specifier.
1020
1021 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1022
1023         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1024         Add new entries for VSCCLRM instruction.
1025         (print_insn_coprocessor): Handle new %C format control code.
1026
1027 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1028
1029         * arm-dis.c (enum isa): New enum.
1030         (struct sopcode32): New structure.
1031         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1032         set isa field of all current entries to ANY.
1033         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1034         Only match an entry if its isa field allows the current mode.
1035
1036 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1037
1038         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1039         CLRM.
1040         (print_insn_thumb32): Add logic to print %n CLRM register list.
1041
1042 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1043
1044         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1045         and %Q patterns.
1046
1047 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1048
1049         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1050         (print_insn_thumb32): Edit the switch case for %Z.
1051
1052 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1053
1054         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1055
1056 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1057
1058         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1059
1060 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1061
1062         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1063
1064 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1065
1066         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1067         Arm register with r13 and r15 unpredictable.
1068         (thumb32_opcodes): New instructions for bfx and bflx.
1069
1070 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1071
1072         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1073
1074 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1075
1076         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1077
1078 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1079
1080         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1081
1082 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1083
1084         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1085
1086 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1087
1088         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1089         "optr". ("operator" is a reserved word in c++).
1090
1091 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1092
1093         * aarch64-opc.c (aarch64_print_operand): Add case for
1094         AARCH64_OPND_Rt_SP.
1095         (verify_constraints): Likewise.
1096         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1097         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1098         to accept Rt|SP as first operand.
1099         (AARCH64_OPERANDS): Add new Rt_SP.
1100         * aarch64-asm-2.c: Regenerated.
1101         * aarch64-dis-2.c: Regenerated.
1102         * aarch64-opc-2.c: Regenerated.
1103
1104 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1105
1106         * aarch64-asm-2.c: Regenerated.
1107         * aarch64-dis-2.c: Likewise.
1108         * aarch64-opc-2.c: Likewise.
1109         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1110
1111 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1112
1113         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1114
1115 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1116
1117         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1118         * i386-init.h: Regenerated.
1119
1120 2019-04-07  Alan Modra  <amodra@gmail.com>
1121
1122         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1123         op_separator to control printing of spaces, comma and parens
1124         rather than need_comma, need_paren and spaces vars.
1125
1126 2019-04-07  Alan Modra  <amodra@gmail.com>
1127
1128         PR 24421
1129         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1130         (print_insn_neon, print_insn_arm): Likewise.
1131
1132 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1133
1134         * i386-dis-evex.h (evex_table): Updated to support BF16
1135         instructions.
1136         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1137         and EVEX_W_0F3872_P_3.
1138         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1139         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1140         * i386-opc.h (enum): Add CpuAVX512_BF16.
1141         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1142         * i386-opc.tbl: Add AVX512 BF16 instructions.
1143         * i386-init.h: Regenerated.
1144         * i386-tbl.h: Likewise.
1145
1146 2019-04-05  Alan Modra  <amodra@gmail.com>
1147
1148         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1149         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1150         to favour printing of "-" branch hint when using the "y" bit.
1151         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1152
1153 2019-04-05  Alan Modra  <amodra@gmail.com>
1154
1155         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1156         opcode until first operand is output.
1157
1158 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1159
1160         PR gas/24349
1161         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1162         (valid_bo_post_v2): Add support for 'at' branch hints.
1163         (insert_bo): Only error on branch on ctr.
1164         (get_bo_hint_mask): New function.
1165         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1166         for inserting 'at' branch hints.
1167         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1168         for extracting 'at' branch hints.
1169         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1170         (BOE): Delete operand.
1171         (BOM, BOP): New operands.
1172         (RM): Update value.
1173         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1174         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1175         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1176         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1177         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1178         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1179         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1180         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1181         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1182         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1183         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1184         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1185         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1186         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1187         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1188         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1189         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1190         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1191         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1192         bttarl+>: New extended mnemonics.
1193
1194 2019-03-28  Alan Modra  <amodra@gmail.com>
1195
1196         PR 24390
1197         * ppc-opc.c (BTF): Define.
1198         (powerpc_opcodes): Use for mtfsb*.
1199         * ppc-dis.c (print_insn_powerpc): Print fields with both
1200         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1201
1202 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1203
1204         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1205         (mapping_symbol_for_insn): Implement new algorithm.
1206         (print_insn): Remove duplicate code.
1207
1208 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1209
1210         * aarch64-dis.c (print_insn_aarch64):
1211         Implement override.
1212
1213 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1214
1215         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1216         order.
1217
1218 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1219
1220         * aarch64-dis.c (last_stop_offset): New.
1221         (print_insn_aarch64): Use stop_offset.
1222
1223 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1224
1225         PR gas/24359
1226         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1227         CPU_ANY_AVX2_FLAGS.
1228         * i386-init.h: Regenerated.
1229
1230 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1231
1232         PR gas/24348
1233         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1234         vmovdqu16, vmovdqu32 and vmovdqu64.
1235         * i386-tbl.h: Regenerated.
1236
1237 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1238
1239         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1240         from vstrszb, vstrszh, and vstrszf.
1241
1242 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1243
1244         * s390-opc.txt: Add instruction descriptions.
1245
1246 2019-02-08  Jim Wilson  <jimw@sifive.com>
1247
1248         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1249         <bne>: Likewise.
1250
1251 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1252
1253         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1254
1255 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1256
1257         PR binutils/23212
1258         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1259         * aarch64-opc.c (verify_elem_sd): New.
1260         (fields): Add FLD_sz entr.
1261         * aarch64-tbl.h (_SIMD_INSN): New.
1262         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1263         fmulx scalar and vector by element isns.
1264
1265 2019-02-07  Nick Clifton  <nickc@redhat.com>
1266
1267         * po/sv.po: Updated Swedish translation.
1268
1269 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1270
1271         * s390-mkopc.c (main): Accept arch13 as cpu string.
1272         * s390-opc.c: Add new instruction formats and instruction opcode
1273         masks.
1274         * s390-opc.txt: Add new arch13 instructions.
1275
1276 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1277
1278         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1279         (aarch64_opcode): Change encoding for stg, stzg
1280         st2g and st2zg.
1281         * aarch64-asm-2.c: Regenerated.
1282         * aarch64-dis-2.c: Regenerated.
1283         * aarch64-opc-2.c: Regenerated.
1284
1285 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1286
1287         * aarch64-asm-2.c: Regenerated.
1288         * aarch64-dis-2.c: Likewise.
1289         * aarch64-opc-2.c: Likewise.
1290         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1291
1292 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1293             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1294
1295         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1296         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1297         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1298         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1299         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1300         case for ldstgv_indexed.
1301         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1302         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1303         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1304         * aarch64-asm-2.c: Regenerated.
1305         * aarch64-dis-2.c: Regenerated.
1306         * aarch64-opc-2.c: Regenerated.
1307
1308 2019-01-23  Nick Clifton  <nickc@redhat.com>
1309
1310         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1311
1312 2019-01-21  Nick Clifton  <nickc@redhat.com>
1313
1314         * po/de.po: Updated German translation.
1315         * po/uk.po: Updated Ukranian translation.
1316
1317 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1318         * mips-dis.c (mips_arch_choices): Fix typo in
1319         gs464, gs464e and gs264e descriptors.
1320
1321 2019-01-19  Nick Clifton  <nickc@redhat.com>
1322
1323         * configure: Regenerate.
1324         * po/opcodes.pot: Regenerate.
1325
1326 2018-06-24  Nick Clifton  <nickc@redhat.com>
1327
1328         2.32 branch created.
1329
1330 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1331
1332         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1333         if it is null.
1334         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1335         zero.
1336
1337 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1338
1339         * configure: Regenerate.
1340
1341 2019-01-07  Alan Modra  <amodra@gmail.com>
1342
1343         * configure: Regenerate.
1344         * po/POTFILES.in: Regenerate.
1345
1346 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1347
1348         * s12z-opc.c: New file.
1349         * s12z-opc.h: New file.
1350         * s12z-dis.c: Removed all code not directly related to display
1351         of instructions.  Used the interface provided by the new files
1352         instead.
1353         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1354         * Makefile.in: Regenerate.
1355         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1356         * configure: Regenerate.
1357
1358 2019-01-01  Alan Modra  <amodra@gmail.com>
1359
1360         Update year range in copyright notice of all files.
1361
1362 For older changes see ChangeLog-2018
1363 \f
1364 Copyright (C) 2019 Free Software Foundation, Inc.
1365
1366 Copying and distribution of this file, with or without modification,
1367 are permitted in any medium without royalty provided the copyright
1368 notice and this notice are preserved.
1369
1370 Local Variables:
1371 mode: change-log
1372 left-margin: 8
1373 fill-column: 74
1374 version-control: never
1375 End: