opcodes/ChangeLog

   1 2021-11-11  Alex Coplan  <alex.coplan@arm.com>
   2
   3         * aarch64-opc.c (operand_general_constraint_met_p): Always check
   4         if the immediate is in range for AARCH64_OPND_A64C_IMM6_EXT.
   5
   6 2021-09-24  Alex Coplan  <alex.coplan@arm.com>
   7
   8         * aarch64-tbl.h (aarch64_opcode_table): Update A64C_INSNs
   9         ldtr/sttr to take A64C_ADDR_SIMM9 instead of ADDR_SIMM9
  10         operands.
  11
  12 2021-03-17  Luis Machado  <luis.machado@arm.com>
  13
  14         * aarch64-dis.c (enum map_type): Moved to include/opcode/aarch64.h.
  15         (MAYBE_C64): Adjust.
  16         (get_sym_code_type): Adjust.
  17         (print_insn_aarch64): Use private data when available.
  18
  19 2020-10-20  Luis Machado  <luis.machado@arm.com>
  20
  21         * aarch64-tbl.h (aarch64_opcode_table): Update iclass field
  22         for add/sub
  23
  24 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
  25
  26         * aarch64-dis.c (get_sym_code_type): Fix C64 PLT disassembly.
  27
  28 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
  29
  30         * aarch64-opc.c (operand_general_constraint_met_p): Expect
  31         capability registers for cache operations in C64.
  32         (aarch64_print_operand): Print register arguments for cache
  33         instructions correctly.
  34         * aarch64-tbl.h (aarch64_opcode_table): New instructions.
  35         (AARCH64_OPERANDS): New operands.
  36         * aarch64-asm-2.c: Regenerate.
  37         * aarch64-dis-2.c: Regenerate.
  38         * aarch64-opc-2.c: Regenerate.
  39
  40 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
  41
  42         * aarch64-asm.c (aarch64_ins_sysreg): Adjust for morello
  43         MRS/MSR.
  44         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
  45         * aarch64-opc.c (fields): New field a64c_op0.
  46         (operand_general_constraint_met_p): Add SYSREG operand
  47         validation.
  48         (aarch64_print_operand): Print Morello MRS/MSR operands
  49         correctly.
  50         (SR_MORELLO): New macro.
  51         (aarch64_sys_regs): Use it.  Add Morello system registers.
  52         (aarch64_sys_reg_capreg_supported_p): New function.
  53         * aarch64-opc.h (aarch64_field_kind): New field FLD_a64c_op0.
  54         * aarch64-tbl.h (QL2_SRC_CA, QL2_DST_CA): New macros.
  55         (aarch64_opcode_table): New instructions.
  56         * aarch64-asm-2.c: Regenerate.
  57         * aarch64-dis-2.c: Regenerate.
  58         * aarch64-opc-2.c: Regenerate.
  59
  60 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
  61
  62         * aarch64-dis.c (aarch64_ext_regno): Reject A64 ADR when in
  63         C64.
  64         (aarch64_ext_imm): Select ADRDP in C64.
  65         * aarch64-opc.c (fields): Add a64c_immhi field.
  66         (validate_adr_reg_for_feature): New function.
  67         (operand_general_constraint_met_p): Use it.
  68         (aarch64_print_operand): Add A64C_ADDR_ADRDP.
  69         * aarch64-opc.h (aarch64_field_kind): FLD_a64c_immhi.
  70         * aarch64-tbl.h (aarch64_opcode_table): Add new instructions.
  71         (AARCH64_OPERANDS): Add new operands.
  72         * aarch64-asm-2.c: Regenerate.
  73         * aarch64-dis-2.c: Regenerate.
  74         * aarch64-opc-2.c: Regenerate.
  75
  76 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
  77
  78         * aarch64-tbl.h (aarch64_opcode_table): Change OP of LDUR/STUR
  79         instructions.
  80         * aarch64-opc-2.c: Regenerate.
  81
  82 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
  83
  84         * aarch64-asm.c (aarch64_ins_addr_uimm): Shift only if
  85         F_NOSHIFT is not set.
  86         * aarch64-tbl.h (QL2_B_ADDR, QL2_X_ADDR, QL2_H_ADDR): New
  87         macro.
  88         (aarch64_opcode_table): New instructions.
  89         * aarch64-asm-2.c: Regenerate.
  90         * aarch64-dis-2.c: Regenerate.
  91         * aarch64-opc-2.c: Regenerate.
  92
  93 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
  94
  95         * aarch64-asm.c (aarch64_ins_fregsz): New function.
  96         (aarch64_ins_addr_simm): Add ldst_altbase to assert.
  97         * aarch64-asm.h (ins_fregsz): New function declaration.
  98         * aarch64-dis.c (aarch64_ext_fregsz): New function.
  99         (aarch64_ext_addr_simm): Disable writeback for ldst_altbase.
 100         * aarch64-dis.h (ext_fregsz): New function declaration.
 101         * aarch64-opc.c (fields): Add altbase_sf2 and altbase_sf3.
 102         (operand_general_constraint_met_p): Add CAPADDR_SIMM9.
 103         (aarch64_print_operand): Add CAPADDR_SIMM9, Rsz2, Fsz, St.
 104         * aarch64-opc.h (aarch64_field_kind): Add FLD_altbase_sf2, FLD_altbase_sf3.
 105         * aarch64-tbl.h (aarch64_opcode_table): New instructions.
 106         (AARCH64_OPERANDS): New operands.
 107         * aarch64-asm-2.c: Regenerate.
 108         * aarch64-dis-2.c: Regenerate.
 109         * aarch64-opc-2.c: Regenerate.
 110
 111 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
 112
 113         * aarch64-asm.c (aarch64_ins_regsz): New function.
 114         (aarch64_ins_ft): Support altbase loads.
 115         (aarch64_ins_addr_uimm12): Rename to aarch64_ins_addr_uimm.
 116         * aarch64-asm.h: (ins_regsz): New function declaration.
 117         (ins_addr_uimm12): Rename to ins_addr_uimm.
 118         * aarch64-dis.c (aarch64_ext_regsz): New function.
 119         (aarch64_ext_ft): Support altbase loads.
 120         (aarch64_ext_addr_uimm12): Rename to aarch64_ext_addr_uimm.
 121         * aarch64-dis.h: (ext_regsz): New function declaration.
 122         (dis_addr_uimm12): Rename to dis_addr_uimm.
 123         * aarch64-opc.c (fields): Add altbase_sf.
 124         (operand_general_constraint_met_p): Check constraints for
 125         ldst_altbase, CAPADDR_REGOFF, CAPADDR_UIMM9.
 126         (aarch64_print_operand): Print Rsz, CAPADDR_REGOFF,
 127         CAPADDR_UIMM9.
 128         * aarch64-opc.h (aarch64_field_kind): Add FLD_altbase_sf.
 129         * aarch64-tbl.h (QL2_A64C_R_CAPADDR, QL2_A64C_FP_CAPADDR): New
 130         macro.
 131         (aarch64_opcode_table): New instructions.
 132         (AARCH64_OPERANDS): New operands.
 133         * aarch64-asm-2.c: Regenerate.
 134         * aarch64-dis-2.c: Regenerate.
 135         * aarch64-opc-2.c: Regenerate.
 136
 137 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
 138
 139         * aarch64-opc.c (get_altbase_reg_name): New function.
 140         (aarch64_print_operand): Use it.  Add Wt.
 141         * aarch64-tbl.h (QL2_A64C_W_CAPADDR): New macro.
 142         (aarch64_opcode_table): Add instructions.
 143         (AARCH64_OPERANDS): New operand.
 144         * aarch64-asm-2.c: Regenerate.
 145         * aarch64-dis-2.c: Regenerate.
 146         * aarch64-opc-2.c: Regenerate.
 147
 148 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
 149
 150         * aarch64-asm.c (aarch64_ins_addr_simm): Support scaling.
 151         * aarch64-dis.c (aarch64_ext_addr_simm): Likewise.
 152         * aarch64-opc.c (operand_general_constraint_met_p,
 153         aarch64_print_operand): Add A64C_ADDR_SIMM9.
 154         * aarch64-tbl.h (aarch64_opcode_table): New instructions.
 155         (AARCH64_OPERANDS): New operands.
 156         * aarch64-asm-2.c: Regenerate.
 157         * aarch64-dis-2.c: Regenerate.
 158         * aarch64-opc-2.c: Regenerate.
 159
 160 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
 161
 162         * aarch64-asm-2.c: Regenerate.
 163         * aarch64-dis-2.c: Regenerate.
 164         * aarch64-opc-2.c: Regenerate.
 165         * aarch64-opc.c (fields): Add imm17.
 166         (operand_general_constraint_met_p, aarch64_print_operand): Add
 167         ADDR_PCREL17.
 168         * aarch64-opc.h (aarch64_field_kind): Add FLD_imm17.
 169         * aarch64-tbl.h (QL2_A64C_CA_PCREL): New macro.
 170         (aarch64_opcode_table): New instruction.
 171         (AARCH64_OPERANDS): New operand.
 172
 173 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
 174
 175         * aarch64-asm-2.c: Regenerate.
 176         * aarch64-dis-2.c: Regenerate.
 177         * aarch64-opc-2.c: Regenerate.
 178         * aarch64-opc.c (fields): Add a64c_index2.
 179         (operand_general_constraint_met_p, aarch64_print_operand): Add
 180         A64C_ADDR_SIMM7.
 181         * aarch64-opc.h (aarch64_field_kind): Add FLD_a64c_index2.
 182         * aarch64-tbl.h (QL2_A64C_CA_ADDR, QL2_A64C_X_ADDR,
 183         QL3_A64C_W_CA_ADDR, QL4_A64C_W_CA_CA_ADDR): New macros.
 184         (aarch64_opcode_table): New instructions.
 185         (AARCH64_OPERANDS): New operands.
 186
 187 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
 188
 189         * aarch64-asm.c (aarch64_ins_addr_simple): Fix comment.
 190         (aarch64_ins_addr_simm): Support capability address operands.
 191         * aarch64-dis.c (aarch64_ext_addr_simple): Fix comment.
 192         (aarch64_ext_addr_simm): Support capability address operands.
 193         * aarch64-opc.c (fields): Add capaddr_simm7.
 194         (operand_general_constraint_met_p): Add CAPADDR_SIMM7.
 195         (aarch64_print_operand): Add CAPADDR_SIMM7 and CAPADDR_SIMPLE.
 196         * aarch64-opc.h (aarch64_field_kind): Add FLD_capaddr_simm7.
 197         * aarch64-tbl.h (QL1_A64C_CAPADDR, QL2_A64C_CA_CAPADDR): New
 198         macros.
 199         (aarch64_opcode_table): New instructions.
 200         (AARCH64_OPERANDS): New operands.
 201         * aarch64-asm-2.c: Regenerate.
 202         * aarch64-dis-2.c: Regenerate.
 203         * aarch64-opc-2.c: Regenerate.
 204
 205 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
 206
 207         * aarch64-asm.c (aarch64_ins_form): New function.
 208         * aarch64-asm.h (ins_form): New function declaration.
 209         * aarch64-dis.c (aarch64_ext_form): New function.
 210         * aarch64-dis.h (ext_form): New function declaraion.
 211         * aarch64-opc.c (fields): New field form.
 212         (aarch64_forms): Initialise array.
 213         (get_form_from_value, get_form_from_str): New functions.
 214         (aarch64_print_operand): Add FORM.
 215         * aarch64-opc.h (aarch64_field_kind): Add FLD_form.
 216         * aarch64-tbl.h (aarch64_opcode_table): New instructions.
 217         (AARCH64_OPERANDS): New operands.
 218         * aarch64-asm-2.c: Regenerate.
 219         * aarch64-dis-2.c: Regenerate.
 220         * aarch64-opc-2.c: Regenerate.
 221
 222 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
 223
 224         * aarch64-asm.c (aarch64_ins_aimm): Fix comment.
 225         * aarch64-dis.c (aarch64_ext_a64c_imm6): New function.
 226         * aarch64-dis.h (ext_a64c_imm6): New function.
 227         * aarch64-opc.c (fields): New field a64c_shift.
 228         (operand_general_constraint_met_p, aarch64_print_operand): Add
 229         IMM6_EXT.
 230         * aarch64-opc.h (aarch64_field_kind): Add new field.
 231         * aarch64-tbl.h (aarch64_opcode_table): New instructions.
 232         (AARCH64_OPERANDS): New operands.
 233         * aarch64-asm-2.c: Regenerate.
 234         * aarch64-dis-2.c: Regenerate.
 235         * aarch64-opc-2.c: Regenerate.
 236
 237 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
 238
 239         * aarch64-asm.c (aarch64_ins_perm): New function.
 240         * aarch64-asm.h (ins_perm): New function.
 241         * aarch64-dis.c (aarch64_ext_perm): New function.
 242         * aarch64-dis.h (ext_perm): New function.
 243         * aarch64-opc.c (fields): New field perm.
 244         (get_perm_str, get_perm_bit): New functions.
 245         (aarch64_print_operand): Add PERM.
 246         * aarch64-opc.h (aarch64_field_kind): Add perm.
 247         * aarch64-tbl.h (QL_I2SAMEQ): New macro.
 248         (aarch64_opcode_table): New instructions.
 249         (AARCH64_OPERANDS): New operands.
 250         * aarch64-asm-2.c: Regenerate.
 251         * aarch64-dis-2.c: Regenerate.
 252         * aarch64-opc-2.c: Regenerate.
 253
 254 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
 255
 256         * aarch64-tbl.h (QL2_A64C_X_CA, QL2_A64C_CA_X, QL2_A64C_X_X,
 257         QL3_A64C_X_CA_CA, QL3_A64C_CA_CA_ADDR, QL4_A64C_CSEL): New
 258         macros.
 259         (aarch64_opcode_table): New instructions.
 260         * aarch64-asm-2.c: Regenerate.
 261         * aarch64-dis-2.c: Regenerate.
 262         * aarch64-opc-2.c: Regenerate.
 263
 264 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
 265
 266         * aarch64-dis.c (aarch64_ext_a64c_immv): New function.
 267         (aarch64_ext_regno): Set PRESENT flag for A64 RET.
 268         * aarch64-dis.h (aarch64_ext_a64c_immv): New function.
 269         * aarch64-opc.c (operand_general_constraint_met_p): Add
 270         A64C_IMMV4.  Remove ATTRIBUTE_UNUSED.  Reject A64 RET without
 271         operand when in C64.
 272         (aarch64_match_operands_constraint): Remove ATTRIBUTE_UNUSED.
 273         (aarch64_print_operand): Add A64C_IMMV4, Cam_SP and CST_REG.
 274         * aarch64-tbl.h (QL1_A64C_CA, QL3_A64C_CA_CA_CA): New macros.
 275         (aarch64_opcode_table): New instructions.
 276         (AARCH64_OPERANDS): New operands.
 277         * aarch64-asm-2.c: Regenerate.
 278         * aarch64-dis-2.c: Regenerate.
 279         * aarch64-opc-2.c: Regenerate.
 280
 281 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
 282
 283         * aarch64-opc.c (fields): Add a64c_imm8.
 284         (aarch64_print_operand): Add A64C_IMM8.
 285         * aarch64-opc.h (aarch64_field_kind): Add a64c_imm8.
 286         * aarch64-tbl.h (QL3_A64C_CA_CA_X): New macro.
 287         (aarch64_opcode_table): New instructions.
 288         (AARCH64_OPERANDS): Add A64C_IMM8.
 289         * aarch64-asm-2.c: Regenerate.
 290         * aarch64-dis-2.c: Regenerate.
 291         * aarch64-opc-2.c: Regenerate.
 292
 293 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
 294
 295         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reg_extended):
 296         Identify capability register class.
 297         (do_ext_aimm): New function.
 298         (arch64_ext_aimm): Call it.
 299         (aarch64_ext_a64c_aimm): New function.
 300         * aarch64-dis.h (ext_a64c_aimm): New function.
 301         * aarch64-opc.c (fields): Add a64c_shift_ai field.
 302         (operand_general_constraint_met_p, aarch64_print_operand): Add
 303         A64C_AIMM and A64C_Rm_EXT.
 304         * aarch64-opc.h (aarch64_field_kind): Add a64c_shift_ai.
 305         * aarch64-tbl.h (QL3_A64C_CA_CA_NIL, QL3_A64C_CA_CA_R): New
 306         macro.
 307         (aarch64_opcode_table): New instructions.
 308         (AARCH64_OPERANDS): Add new operands.
 309         * aarch64-asm-2.c: Regenerate.
 310         * aarch64-dis-2.c: Regenerate.
 311         * aarch64-opc-2.c: Regenerate.
 312
 313 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
 314
 315         * aarch64-asm.c (do_special_encoding): Recognise capability
 316         registers.
 317         * aarch64-opc.c (aarch64_opnd_qualifiers): Capability operand
 318         qualifiers.
 319         (aarch64_print_operand): Support capability operands.
 320         * aarch64-opc.h (select_operand_for_sf_field_coding):
 321         Recognise capability registers.
 322         * aarch64-tbl.h (QL2_A64C_CA_CA): New macro.
 323         (aarch64_opcode_table): Add mov and cpy.
 324         (AARCH64_OPERANDS): Add capability register operands.
 325         * aarch64-asm-2.c: Regenerate.
 326         * aarch64-dis-2.c: Regenerate.
 327         * aarch64-opc-2.c: Regenerate.
 328
 329 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
 330
 331         * aarch64-dis.c: Include elf/aarch64.h.
 332         (get_sym_code_type): Identify C64 functions.
 333
 334 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
 335
 336         * aarch64-asm.c (aarch64_opcode_encode): Add CPU variant
 337         argument.
 338         * aarch64-dis.c (map_type): Add MAP_C64.
 339         (MAYBE_C64): New macro.
 340         (determine_disassembling_preference, print_operands): Use it.
 341         (aarch64_symbol_is_valid): Test for $c.
 342         (get_sym_code_type): Recognise MAP_C64.
 343         (select_aarch64_variant): Clear AARCH64_FEATURE_C64.
 344         (determine_disassembling_preference, aarch64_opcode_decode):
 345         Adjust calls to aarch64_match_operands_constraint.
 346         * aarch64-opc.c (get_altbase_reg_name, get_base_reg_name): New
 347         functions.
 348         (aarch64_print_operand): Use them.
 349         (aarch64_match_operands_constraint): Likewise.
 350         * aarch64-opc.h (aarch64_match_operands_constraint): Add CPU
 351         variant argument.
 352
 353 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
 354
 355         * aarch64-opc.c (fields): New capability register fields.
 356         (aarch64_opnd_qualifiers): Capability operand qualifiers.
 357         (int_reg): Add capability register bank.
 358         (get_int_reg_name): Adjust for capability registers.
 359         (get_cap_reg_name): New function.
 360         (aarch64_print_operand): Support printing capability operands.
 361         * aarch64-opc.h (aarch64_field_kind): Add capability operand
 362         fields.
 363         (OPD_F_MAYBE_CSP): New macro.
 364         (operand_maybe_cap_stack_pointer): New function.
 365         * aarch64-tbl.h (QL2_A64C_CA_CA, A64C, A64C_INSN): New macros.
 366         (aarch64_feature_a64c): New feature set.
 367
 368 2020-10-16  Lili Cui  <lili.cui@intel.com>
 369
 370         * i386-opc.tbl: Rename CpuVEX_PREFIX to PseudoVexPrefix
 371         and move it from cpu_flags to opcode_modifiers.
 372         Use VexW0 and VexVVVV in the AVX-VNNI instructions.
 373         * i386-gen.c: Likewise.
 374         * i386-opc.h: Likewise.
 375         * i386-opc.h: Likewise.
 376         * i386-init.h: Regenerated.
 377         * i386-tbl.h: Likewise.
 378
 379 2020-10-14  H.J. Lu  <hongjiu.lu@intel.com>
 380             Lili Cui  <lili.cui@intel.com>
 381
 382         * i386-dis.c (PREFIX_VEX_0F3850): New.
 383         (PREFIX_VEX_0F3851): Likewise.
 384         (PREFIX_VEX_0F3852): Likewise.
 385         (PREFIX_VEX_0F3853): Likewise.
 386         (VEX_W_0F3850_P_2): Likewise.
 387         (VEX_W_0F3851_P_2): Likewise.
 388         (VEX_W_0F3852_P_2): Likewise.
 389         (VEX_W_0F3853_P_2): Likewise.
 390         (prefix_table): Add PREFIX_VEX_0F3850, PREFIX_VEX_0F3851,
 391         PREFIX_VEX_0F3852 and PREFIX_VEX_0F3853.
 392         (vex_table): Add VEX_W_0F3850_P_2, VEX_W_0F3851_P_2,
 393         VEX_W_0F3852_P_2 and VEX_W_0F3853_P_2.
 394         (putop): Add support for "XV" to print "{vex3}" pseudo prefix.
 395         * i386-gen.c (cpu_flag_init): Clear the CpuAVX_VNNI bit in
 396         CPU_UNKNOWN_FLAGS.  Add CPU_AVX_VNNI_FLAGS and
 397         CPU_ANY_AVX_VNNI_FLAGS.
 398         (cpu_flags): Add CpuAVX_VNNI and CpuVEX_PREFIX.
 399         * i386-opc.h (CpuAVX_VNNI): New.
 400         (CpuVEX_PREFIX): Likewise.
 401         (i386_cpu_flags): Add cpuavx_vnni and cpuvex_prefix.
 402         * i386-opc.tbl: Add Intel AVX VNNI instructions.
 403         * i386-init.h: Regenerated.
 404         * i386-tbl.h: Likewise.
 405
 406 2020-10-14  Lili Cui  <lili.cui@intel.com>
 407             H.J. Lu  <hongjiu.lu@intel.com>
 408
 409         * i386-dis.c (PREFIX_0F3A0F): New.
 410         (MOD_0F3A0F_PREFIX_1): Likewise.
 411         (REG_0F3A0F_PREFIX_1_MOD_3): Likewise.
 412         (RM_0F3A0F_P_1_MOD_3_REG_0): Likewise.
 413         (prefix_table): Add PREFIX_0F3A0F.
 414         (mod_table): Add MOD_0F3A0F_PREFIX_1.
 415         (reg_table): Add REG_0F3A0F_PREFIX_1_MOD_3.
 416         (rm_table): Add RM_0F3A0F_P_1_MOD_3_REG_0.
 417         * i386-gen.c (cpu_flag_init): Add HRESET_FLAGS,
 418         CPU_ANY_HRESET_FLAGS.
 419         (cpu_flags): Add CpuHRESET.
 420         (output_i386_opcode): Allow 4 byte base_opcode.
 421         * i386-opc.h (enum): Add CpuHRESET.
 422         (i386_cpu_flags): Add cpuhreset.
 423         * i386-opc.tbl: Add Intel HRESET instruction.
 424         * i386-init.h: Regenerate.
 425         * i386-tbl.h: Likewise.
 426
 427 2020-10-14  Lili Cui  <lili.cui@intel.com>
 428
 429         * i386-dis.c (enum): Add
 430         PREFIX_MOD_3_0F01_REG_5_RM_4,
 431         PREFIX_MOD_3_0F01_REG_5_RM_5,
 432         PREFIX_MOD_3_0F01_REG_5_RM_6,
 433         PREFIX_MOD_3_0F01_REG_5_RM_7,
 434         X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
 435         X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
 436         X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
 437         X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
 438         X86_64_0FC7_REG_6_MOD_3_PREFIX_1.
 439         (prefix_table): New instructions (see prefixes above).
 440         (rm_table): Likewise
 441         * i386-gen.c (cpu_flag_init): Add CPU_UINTR_FLAGS,
 442         CPU_ANY_UINTR_FLAGS.
 443         (cpu_flags): Add CpuUINTR.
 444         * i386-opc.h (enum): Add CpuUINTR.
 445         (i386_cpu_flags): Add cpuuintr.
 446         * i386-opc.tbl: Add UINTR insns.
 447         * i386-init.h: Regenerate.
 448         * i386-tbl.h: Likewise.
 449
 450 2020-10-14  H.J. Lu  <hongjiu.lu@intel.com>
 451
 452         * i386-gen.c (process_i386_opcode_modifier): Return 1 for
 453         non-VEX/EVEX/prefix encoding.
 454         (output_i386_opcode): Fail if non-VEX/EVEX/prefix base_opcode
 455         has a prefix byte.
 456         * i386-opc.tbl: Replace the prefix byte in non-VEX/EVEX
 457         base_opcode with PREFIX_0X66, PREFIX_0XF2 or PREFIX_0XF3.
 458         * i386-tbl.h: Regenerated.
 459
 460 2020-10-13  H.J. Lu  <hongjiu.lu@intel.com>
 461
 462         * i386-gen.c (opcode_modifiers): Replace VexOpcode with
 463         OpcodePrefix.
 464         * i386-opc.h (VexOpcode): Renamed to ...
 465         (OpcodePrefix): This.
 466         (PREFIX_NONE): New.
 467         (PREFIX_0X66): Likewise.
 468         (PREFIX_0XF2): Likewise.
 469         (PREFIX_0XF3): Likewise.
 470         * i386-opc.tbl (Prefix_0X66): New.
 471         (Prefix_0XF2): Likewise.
 472         (Prefix_0XF3): Likewise.
 473         Replace VexOpcode= with OpcodePrefix=.  Use Prefix_0X66 on xorpd.
 474         Use Prefix_0XF3 on cvtdq2pd.  Use Prefix_0XF2 on cvtpd2dq.
 475         * i386-tbl.h: Regenerated.
 476
 477 2020-10-05  Samanta Navarro  <ferivoz@riseup.net>
 478
 479         * cgen-asm.c: Fix spelling mistakes.
 480         * cgen-dis.c: Fix spelling mistakes.
 481         * tic30-dis.c: Fix spelling mistakes.
 482
 483 2020-10-05  H.J. Lu  <hongjiu.lu@intel.com>
 484
 485         PR binutils/26704
 486         * i386-dis.c (putop): Always display suffix for %LQ in 64bit.
 487
 488 2020-10-05  H.J. Lu  <hongjiu.lu@intel.com>
 489
 490         PR binutils/26705
 491         * i386-dis.c (print_insn): Clear modrm if not needed.
 492         (putop): Check need_modrm for modrm.mod != 3.  Don't check
 493         need_modrm for modrm.mod == 3.
 494
 495 2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 496
 497         * aarch64-opc.c: Added ETMv4 system registers TRCACATRn, TRCACVRn,
 498         TRCAUTHSTATUS, TRCAUXCTLR, TRCBBCTLR, TRCCCCTLR, TRCCIDCCTLR0, TRCCIDCCTLR1,
 499         TRCCIDCVRn, TRCCIDR0, TRCCIDR1, TRCCIDR2, TRCCIDR3, TRCCLAIMCLR, TRCCLAIMSET,
 500         TRCCNTCTLRn, TRCCNTRLDVRn, TRCCNTVRn, TRCCONFIGR, TRCDEVAFF0, TRCDEVAFF1,
 501         TRCDEVARCH, TRCDEVID, TRCDEVTYPE, TRCDVCMRn, TRCDVCVRn, TRCEVENTCTL0R,
 502         TRCEVENTCTL1R, TRCEXTINSELR, TRCIDR0, TRCIDR1, TRCIDR2, TRCIDR3, TRCIDR4,
 503         TRCIDR5, TRCIDR6, TRCIDR7, TRCIDR8, TRCIDR9, TRCIDR10, TRCIDR11, TRCIDR12,
 504         TRCIDR13, TRCIMSPEC0, TRCIMSPECn, TRCITCTRL, TRCLAR WOTRCLSR, TRCOSLAR
 505         WOTRCOSLSR, TRCPDCR, TRCPDSR, TRCPIDR0, TRCPIDR1, TRCPIDR2, TRCPIDR3,
 506         TRCPIDR4, TRCPIDR[5,6,7], TRCPRGCTLR, TRCP,CSELR, TRCQCTLR, TRCRSCTLRn,
 507         TRCSEQEVRn, TRCSEQRSTEVR, TRCSEQSTR, TRCSSCCRn, TRCSSCSRn, TRCSSPCICRn,
 508         TRCSTALLCTLR, TRCSTATR, TRCSYNCPR, TRCTRACEIDR,  TRCTSCTLR, TRCVDARCCTLR,
 509         TRCVDCTLR, TRCVDSACCTLR, TRCVICTLR, TRCVIIECTLR, TRCVIPCSSCTLR, TRCVISSCTLR,
 510         TRCVMIDCCTLR0, TRCVMIDCCTLR1 and TRCVMIDCVRn.
 511
 512 2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 513
 514         * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
 515
 516 2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 517
 518         * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
 519         TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
 520
 521 2020-09-26  Alan Modra  <amodra@gmail.com>
 522
 523         * csky-opc.h: Formatting.
 524         (GENERAL_REG_BANK): Correct spelling.  Update use throughout file.
 525         (get_register_name): Mask arch with CSKY_ARCH_MASK for shift,
 526         and shift 1u.
 527         (get_register_number): Likewise.
 528         * csky-dis.c (get_gr_name, get_cr_name): Don't mask mach_flag.
 529
 530 2020-09-24  Lili Cui  <lili.cui@intel.com>
 531
 532         PR 26654
 533         * i386-dis.c (enum): Put MOD_VEX_0F38* together.
 534
 535 2020-09-24  Andrew Burgess <andrew.burgess@embecosm.com>
 536
 537         * csky-dis.c (csky_output_operand): Enclose body of if in curly
 538         braces.
 539
 540 2020-09-24  Lili Cui  <lili.cui@intel.com>
 541
 542         * i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5,
 543         PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7,
 544         X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2,
 545         X86_64_0F01_REG_1_RM_7_P_2.
 546         (prefix_table): Likewise.
 547         (x86_64_table): Likewise.
 548         (rm_table): Likewise.
 549         * i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS
 550         and CPU_ANY_TDX_FLAGS.
 551         (cpu_flags): Add CpuTDX.
 552         * i386-opc.h (enum): Add CpuTDX.
 553         (i386_cpu_flags): Add cputdx.
 554         * i386-opc.tbl: Add TDX insns.
 555         * i386-init.h: Regenerate.
 556         * i386-tbl.h: Likewise.
 557
 558 2020-09-17 Cooper Qu <<cooper.qu@linux.alibaba.com>>
 559
 560         * csky-dis.c (using_abi): New.
 561         (parse_csky_dis_options): New function.
 562         (get_gr_name): New function.
 563         (get_cr_name): New function.
 564         (csky_output_operand): Use get_gr_name and get_cr_name to
 565         disassemble and add handle of OPRND_TYPE_IMM5b_LS.
 566         (print_insn_csky): Parse disassembler options.
 567         * csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum.
 568         (GENARAL_REG_BANK): Define.
 569         (REG_SUPPORT_ALL): Define.
 570         (REG_SUPPORT_ALL): New.
 571         (ASH): Define.
 572         (REG_SUPPORT_A): Define.
 573         (REG_SUPPORT_B): Define.
 574         (REG_SUPPORT_C): Define.
 575         (REG_SUPPORT_D): Define.
 576         (REG_SUPPORT_E): Define.
 577         (csky_abiv1_general_regs): New.
 578         (csky_abiv1_control_regs): New.
 579         (csky_abiv2_general_regs): New.
 580         (csky_abiv2_control_regs): New.
 581         (get_register_name): New function.
 582         (get_register_number): New function.
 583         (csky_get_general_reg_name): New function.
 584         (csky_get_general_regno): New function.
 585         (csky_get_control_reg_name): New function.
 586         (csky_get_control_regno): New function.
 587         (csky_v2_opcodes): Prefer two oprerans format for bclri and
 588         bseti, strengthen the operands legality check of addc, zext
 589         and sext.
 590
 591 2020-09-23  Lili Cui  <lili.cui@intel.com>
 592
 593         * i386-dis.c (enum): Add REG_0F38D8_PREFIX_1,
 594         MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1,
 595         MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1,
 596         MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1,
 597         PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB.
 598         (reg_table): New instructions (see prefixes above).
 599         (prefix_table): Likewise.
 600         (three_byte_table): Likewise.
 601         (mod_table): Likewise
 602         * i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS,
 603         CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS.
 604         (cpu_flags): Likewise.
 605         (operand_type_init): Likewise.
 606         * i386-opc.h (enum): Add CpuKL and CpuWide_KL.
 607         (i386_cpu_flags): Add cpukl and cpuwide_kl.
 608         * i386-opc.tbl: Add KL and WIDE_KL insns.
 609         * i386-init.h: Regenerate.
 610         * i386-tbl.h: Likewise.
 611
 612 2020-09-21  Alan Modra  <amodra@gmail.com>
 613
 614         * rx-dis.c (flag_names): Add missing comma.
 615         (register_names, flag_names, double_register_names),
 616         (double_register_high_names, double_register_low_names),
 617         (double_control_register_names, double_condition_names): Remove
 618         trailing commas.
 619
 620 2020-09-18  David Faust  <david.faust@oracle.com>
 621
 622         * bpf-desc.c: Regenerate.
 623         * bpf-desc.h: Likewise.
 624         * bpf-opc.c: Likewise.
 625         * bpf-opc.h: Likewise.
 626
 627 2020-09-16  Andrew Burgess <andrew.burgess@embecosm.com>
 628
 629         * csky-dis.c (csky_get_disassembler): Don't return NULL when there
 630         is no BFD.
 631
 632 2020-09-16  Alan Modra  <amodra@gmail.com>
 633
 634         * ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation.
 635
 636 2020-09-10  Nick Clifton  <nickc@redhat.com>
 637
 638         * ppc-dis.c (ppc_symbol_is_valid): New function.  Returns false
 639         for hidden, local, no-type symbols.
 640         (disassemble_init_powerpc): Point the symbol_is_valid field in the
 641         info structure at the new function.
 642
 643 2020-09-10  Cooper Qu  <cooper.qu@linux.alibaba.com>
 644
 645         * csky-opc.h (csky_v2_opcodes): Add L2Cache instructions.
 646         * testsuite/gas/csky/cskyv2_ck860.d : Adjust to icache.iva
 647         opcode fixing.
 648
 649 2020-09-10  Nick Clifton  <nickc@redhat.com>
 650
 651         * csky-dis.c (csky_output_operand): Coerce the immediate values to
 652         long before printing.
 653
 654 2020-09-10  Alan Modra  <amodra@gmail.com>
 655
 656         * csky-dis.c (csky_output_operand): Don't sprintf str to itself.
 657
 658 2020-09-07  Cooper Qu  <cooper.qu@linux.alibaba.com>
 659
 660         * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
 661         ISA flag.
 662
 663 2020-09-07  Cooper Qu  <cooper.qu@linux.alibaba.com>
 664
 665         * csky-dis.c (csky_output_operand): Add handlers for
 666         OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
 667         OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
 668         to support FPUV3 instructions.
 669         * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
 670         OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
 671         OPRND_TYPE_DFLOAT_FMOVI.
 672         (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
 673          OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
 674          OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
 675          OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
 676          OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
 677          OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
 678          OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
 679          OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
 680          OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
 681          OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
 682          OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
 683          OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
 684          OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
 685         (csky_v2_opcodes): Add FPUV3 instructions.
 686
 687 2020-09-08  Alex Coplan  <alex.coplan@arm.com>
 688
 689         * aarch64-dis.c (print_operands): Pass CPU features to
 690         aarch64_print_operand().
 691         * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
 692         preferred disassembly of system registers.
 693         (SR_RNG): Refactor to use new SR_FEAT2 macro.
 694         (SR_FEAT2): New.
 695         (SR_V8_1_A): New.
 696         (SR_V8_4_A): New.
 697         (SR_V8_A): New.
 698         (SR_V8_R): New.
 699         (SR_EXPAND_ELx): New.
 700         (SR_EXPAND_EL12): New.
 701         (aarch64_sys_regs): Specify which registers are only on
 702         A-profile, add R-profile system registers.
 703         (ENC_BARLAR): New.
 704         (PRBARn_ELx): New.
 705         (PRLARn_ELx): New.
 706         (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
 707         Armv8-R AArch64.
 708
 709 2020-09-08  Alex Coplan  <alex.coplan@arm.com>
 710
 711         * aarch64-tbl.h (aarch64_feature_v8_r): New.
 712         (ARMV8_R): New.
 713         (V8_R_INSN): New.
 714         (aarch64_opcode_table): Add dfb.
 715         * aarch64-opc-2.c: Regenerate.
 716         * aarch64-asm-2.c: Regenerate.
 717         * aarch64-dis-2.c: Regenerate.
 718
 719 2020-09-08  Alex Coplan  <alex.coplan@arm.com>
 720
 721         * aarch64-dis.c (arch_variant): New.
 722         (determine_disassembling_preference): Disassemble according to
 723         arch variant.
 724         (select_aarch64_variant): New.
 725         (print_insn_aarch64): Set feature set.
 726
 727 2020-09-02  Alan Modra  <amodra@gmail.com>
 728
 729         * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
 730         (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9),
 731         (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16),
 732         (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9),
 733         (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID),
 734         (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP),
 735         (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long
 736         for value parameter and update code to suit.
 737         (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16),
 738         (extract_d22, extract_d23, extract_i9): Use unsigned long variables.
 739
 740 2020-09-02  Alan Modra  <amodra@gmail.com>
 741
 742         * i386-dis.c (OP_E_memory): Don't cast to signed type when
 743         negating.
 744         (get32, get32s): Use unsigned types in shift expressions.
 745
 746 2020-09-02  Alan Modra  <amodra@gmail.com>
 747
 748         * csky-dis.c (print_insn_csky): Use unsigned type for "given".
 749
 750 2020-09-02  Alan Modra  <amodra@gmail.com>
 751
 752         * crx-dis.c: Whitespace.
 753         (print_arg): Use unsigned type for longdisp and mask variables,
 754         and for left shift constant.
 755
 756 2020-09-02  Alan Modra  <amodra@gmail.com>
 757
 758         * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
 759         * bpf-ibld.c: Regenerate.
 760         * epiphany-ibld.c: Regenerate.
 761         * fr30-ibld.c: Regenerate.
 762         * frv-ibld.c: Regenerate.
 763         * ip2k-ibld.c: Regenerate.
 764         * iq2000-ibld.c: Regenerate.
 765         * lm32-ibld.c: Regenerate.
 766         * m32c-ibld.c: Regenerate.
 767         * m32r-ibld.c: Regenerate.
 768         * mep-ibld.c: Regenerate.
 769         * mt-ibld.c: Regenerate.
 770         * or1k-ibld.c: Regenerate.
 771         * xc16x-ibld.c: Regenerate.
 772         * xstormy16-ibld.c: Regenerate.
 773
 774 2020-09-02  Alan Modra  <amodra@gmail.com>
 775
 776         * bfin-dis.c (MASKBITS): Use SIGNBIT.
 777
 778 2020-09-02  Cooper Qu  <cooper.qu@linux.alibaba.com>
 779
 780         * csky-opc.h (csky_v2_opcodes): Move divul and divsl
 781         to CSKYV2_ISA_3E3R3 instruction set.
 782
 783 2020-09-02  Cooper Qu  <cooper.qu@linux.alibaba.com>
 784
 785         * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
 786
 787 2020-09-01  Alan Modra  <amodra@gmail.com>
 788
 789         * mep-ibld.c: Regenerate.
 790
 791 2020-08-31  Cooper Qu  <cooper.qu@linux.alibaba.com>
 792
 793         * csky-dis.c (csky_output_operand): Assign dis_info.value for
 794         OPRND_TYPE_VREG.
 795
 796 2020-08-30  Alan Modra  <amodra@gmail.com>
 797
 798         * cr16-dis.c: Formatting.
 799         (parameter): Delete struct typedef.  Use dwordU instead
 800         throughout file.
 801         (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
 802         and tbitb.
 803         (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
 804
 805 2020-08-29  Alan Modra  <amodra@gmail.com>
 806
 807         PR 26446
 808         * csky-opc.h (MAX_OPRND_NUM): Define to 5.
 809         (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
 810
 811 2020-08-28  Alan Modra  <amodra@gmail.com>
 812
 813         PR 26449
 814         PR 26450
 815         * cgen-ibld.in (insert_1): Use 1UL in forming mask.
 816         (extract_normal): Likewise.
 817         (insert_normal): Likewise, and move past zero length test.
 818         (put_insn_int_value): Handle mask for zero length, use 1UL.
 819         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 820         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 821         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 822         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 823
 824 2020-08-28  Cooper Qu  <cooper.qu@linux.alibaba.com>
 825
 826         * csky-dis.c (CSKY_DEFAULT_ISA): Define.
 827         (csky_dis_info): Add member isa.
 828         (csky_find_inst_info): Skip instructions that do not belong to
 829         current CPU.
 830         (csky_get_disassembler): Get infomation from attribute section.
 831         (print_insn_csky): Set defualt ISA flag.
 832         * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
 833         * csky-opc.h (struct csky_opcode): Change isa_flag16 and
 834         isa_flag32'type to unsigned 64 bits.
 835
 836 2020-08-26  Jose E. Marchesi  <jemarch@gnu.org>
 837
 838         * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
 839
 840 2020-08-26  David Faust  <david.faust@oracle.com>
 841
 842         * bpf-desc.c: Regenerate.
 843         * bpf-desc.h: Likewise.
 844         * bpf-opc.c: Likewise.
 845         * bpf-opc.h: Likewise.
 846         * disassemble.c (disassemble_init_for_target): Set bits for xBPF
 847         ISA when appropriate.
 848
 849 2020-08-25  Alan Modra  <amodra@gmail.com>
 850
 851         PR 26504
 852         * vax-dis.c (parse_disassembler_options): Always add at least one
 853         to entry_addr_total_slots.
 854
 855 2020-08-24  Cooper Qu  <cooper.qu@linux.alibaba.com>
 856
 857         * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
 858         in other CPUs to speed up disassembling.
 859         * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
 860         Change plsli.u16 to plsli.16, change sync's operand format.
 861
 862 2020-08-21  Cooper Qu  <cooper.qu@linux.alibaba.com>
 863
 864         * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
 865
 866 2020-08-21  Nick Clifton  <nickc@redhat.com>
 867
 868         * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
 869         symbols.
 870
 871 2020-08-21  Cooper Qu  <cooper.qu@linux.alibaba.com>
 872
 873         * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
 874
 875 2020-08-19  Alan Modra  <amodra@gmail.com>
 876
 877         * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
 878         vcmpuq and xvtlsbb.
 879
 880 2020-08-18  Peter Bergner  <bergner@linux.ibm.com>
 881
 882         * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
 883         <xvcvbf16spn>: ...to this.
 884
 885 2020-08-12  Alex Coplan  <alex.coplan@arm.com>
 886
 887         * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
 888
 889 2020-08-12  Nick Clifton  <nickc@redhat.com>
 890
 891         * po/sr.po: Updated Serbian translation.
 892
 893 2020-08-11  Alan Modra  <amodra@gmail.com>
 894
 895         * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
 896
 897 2020-08-10  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 898
 899         * aarch64-opc.c (aarch64_print_operand):
 900         (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
 901         (aarch64_sys_reg_supported_p): Function removed.
 902         (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
 903         (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
 904         into this function.
 905
 906 2020-08-10  Alan Modra  <amodra@gmail.com>
 907
 908         * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
 909         instructions.
 910
 911 2020-08-10  Alan Modra  <amodra@gmail.com>
 912
 913         * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
 914         Enable icbt for power5, miso for power8.
 915
 916 2020-08-10  Alan Modra  <amodra@gmail.com>
 917
 918         * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
 919         mtvsrd, and similarly for mfvsrd.
 920
 921 2020-08-04  Christian Groessler  <chris@groessler.org>
 922             Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
 923
 924         * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
 925         opcodes (special "out" to absolute address).
 926         * z8k-opc.h: Regenerate.
 927
 928 2020-07-30  H.J. Lu  <hongjiu.lu@intel.com>
 929
 930         PR gas/26305
 931         * i386-opc.h (Prefix_Disp8): New.
 932         (Prefix_Disp16): Likewise.
 933         (Prefix_Disp32): Likewise.
 934         (Prefix_Load): Likewise.
 935         (Prefix_Store): Likewise.
 936         (Prefix_VEX): Likewise.
 937         (Prefix_VEX3): Likewise.
 938         (Prefix_EVEX): Likewise.
 939         (Prefix_REX): Likewise.
 940         (Prefix_NoOptimize): Likewise.
 941         * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes.  Add {disp16}.
 942         * i386-tbl.h: Regenerated.
 943
 944 2020-07-29  Andreas Arnez  <arnez@linux.ibm.com>
 945
 946         * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
 947         default case with abort() instead of printing an error message and
 948         continuing, to avoid a maybe-uninitialized warning.
 949
 950 2020-07-24  Nick Clifton  <nickc@redhat.com>
 951
 952         * po/de.po: Updated German translation.
 953
 954 2020-07-21  Jan Beulich  <jbeulich@suse.com>
 955
 956         * i386-dis.c (OP_E_memory): Revert previous change.
 957
 958 2020-07-15  H.J. Lu  <hongjiu.lu@intel.com>
 959
 960         PR gas/26237
 961         * i386-dis.c (OP_E_memory): Don't display eiz with no scale
 962         without base nor index registers.
 963
 964 2020-07-15  Jan Beulich  <jbeulich@suse.com>
 965
 966         * i386-dis.c (putop): Move 'V' and 'W' handling.
 967
 968 2020-07-15  Jan Beulich  <jbeulich@suse.com>
 969
 970         * i386-dis.c (dis386): Adjust 'V' description. Use P-based
 971         construct for push/pop of register.
 972         (putop): Honor cond when handling 'P'. Drop handling of plain
 973         'V'.
 974
 975 2020-07-15  Jan Beulich  <jbeulich@suse.com>
 976
 977         * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
 978         description. Drop '&' description. Use P for push of immediate,
 979         pushf/popf, enter, and leave. Use %LP for lret/retf.
 980         (dis386_twobyte): Use P for push/pop of fs/gs.
 981         (reg_table): Use P for push/pop. Use @ for near call/jmp.
 982         (x86_64_table): Use P for far call/jmp.
 983         (putop): Drop handling of 'U' and '&'. Move and adjust handling
 984         of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
 985         labels.
 986         (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
 987         and dqw_mode (unconditional).
 988
 989 2020-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 990
 991         PR gas/26237
 992         * i386-dis.c (OP_E_memory): Without base nor index registers,
 993         32-bit displacement to 64 bits.
 994
 995 2020-07-14  Claudiu Zissulescu  <claziss@gmail.com>
 996
 997         * arc-dis.c (print_insn_arc): Detect and emit a warning when a
 998         faulty double register pair is detected.
 999
1000 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1001
1002         * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
1003
1004 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1005
1006         * i386-dis.c (OP_R, Rm): Delete.
1007         (MOD_0F24, MOD_0F26): Rename to ...
1008         (X86_64_0F24, X86_64_0F26): ... respectively.
1009         (dis386): Update 'L' and 'Z' comments.
1010         (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
1011         table references.
1012         (mod_table): Move opcode 0F24 and 0F26 entries ...
1013         (x86_64_table): ... here.
1014         (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
1015         'Z' case block.
1016
1017 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1018
1019         * i386-dis.c (Rd, Rdq, MaskR): Delete.
1020         (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
1021         MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
1022         MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
1023         MOD_EVEX_0F387C): New enumerators.
1024         (reg_table): Use Edq for rdssp.
1025         (prefix_table): Use Edq for incssp.
1026         (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
1027         kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
1028         ktest*, and kshift*. Use Edq / MaskE for kmov*.
1029         * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
1030         * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
1031         0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
1032         * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
1033         0F3828_P_1 and 0F3838_P_1.
1034         * i386-dis-evex-w.h: Reference mod_table[] for opcodes
1035         0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
1036
1037 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1038
1039         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
1040         PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
1041         PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
1042         PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
1043         PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
1044         PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
1045         (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
1046         VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
1047         VEX_LEN_0F38F3_R_3_P_0): Rename to ...
1048         (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
1049         VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
1050         (reg_table, prefix_table, three_byte_table, vex_table,
1051         vex_len_table, mod_table, rm_table): Replace / remove respective
1052         entries.
1053         (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
1054         of PREFIX_DATA in used_prefixes.
1055
1056 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1057
1058         * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
1059         MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
1060         MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
1061         MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
1062         (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
1063         MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
1064         (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
1065         VEX_W_0F3A33_L_0): Delete.
1066         (dis386): Adjust "BW" description.
1067         (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
1068         0F3A31, 0F3A32, and 0F3A33.
1069         (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
1070         entries.
1071         (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
1072         entries.
1073
1074 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1075
1076         * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
1077         PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
1078         PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
1079         PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
1080         PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
1081         PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
1082         PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
1083         PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
1084         PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
1085         PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
1086         PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
1087         PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
1088         PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
1089         PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
1090         PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
1091         PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
1092         PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
1093         PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
1094         PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
1095         PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
1096         PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
1097         PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
1098         PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
1099         PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
1100         PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
1101         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
1102         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
1103         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
1104         PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
1105         PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
1106         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
1107         PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
1108         PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
1109         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
1110         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
1111         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
1112         PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
1113         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
1114         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
1115         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
1116         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
1117         PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
1118         PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
1119         PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
1120         PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
1121         PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
1122         PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
1123         PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
1124         PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
1125         PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
1126         PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
1127         PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
1128         PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
1129         PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
1130         PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
1131         PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
1132         PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
1133         PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
1134         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
1135         PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
1136         PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
1137         PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
1138         PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
1139         PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
1140         PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
1141         PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
1142         PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
1143         PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
1144         PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
1145         PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
1146         PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
1147         PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
1148         PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
1149         PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
1150         PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
1151         PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
1152         PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
1153         PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
1154         PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
1155         PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
1156         PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
1157         PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
1158         PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
1159         PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
1160         PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
1161         PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
1162         PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
1163         PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
1164         PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
1165         PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
1166         PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
1167         PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
1168         PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
1169         PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
1170         PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
1171         PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
1172         PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
1173         PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
1174         PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
1175         PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
1176         PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
1177         PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
1178         PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
1179         PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
1180         PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
1181         PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
1182         PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
1183         PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
1184         PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
1185         PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
1186         PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
1187         PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
1188         PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
1189         PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
1190         PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
1191         PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
1192         PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
1193         PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
1194         PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
1195         PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
1196         PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
1197         PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
1198         PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
1199         PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
1200         PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
1201         PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
1202         PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
1203         PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
1204         PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
1205         PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
1206         PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
1207         PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
1208         PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
1209         PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
1210         PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
1211         PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
1212         PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
1213         PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
1214         PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
1215         PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
1216         PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
1217         PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
1218         PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
1219         PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
1220         PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
1221         PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
1222         PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
1223         PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
1224         PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
1225         PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
1226         PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
1227         PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
1228         PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
1229         PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
1230         PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
1231         PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
1232         PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
1233         (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
1234         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
1235         MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
1236         MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
1237         MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
1238         MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
1239         MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
1240         MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
1241         MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
1242         MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
1243         MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
1244         MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1245         MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1246         MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
1247         MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
1248         VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
1249         VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
1250         VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
1251         VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
1252         VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
1253         VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
1254         VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
1255         VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
1256         VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
1257         VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
1258         VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
1259         VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
1260         VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
1261         EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
1262         EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
1263         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
1264         EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
1265         EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
1266         EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1267         EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
1268         EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1269         EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1270         EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
1271         EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
1272         EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
1273         EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
1274         EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
1275         EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1276         EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
1277         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1278         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1279         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1280         EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
1281         EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
1282         EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
1283         EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
1284         EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
1285         EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
1286         EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
1287         EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
1288         VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
1289         VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
1290         VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
1291         VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
1292         VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
1293         VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
1294         VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
1295         VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
1296         VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
1297         VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
1298         VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
1299         VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
1300         VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
1301         VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
1302         VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
1303         VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
1304         VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
1305         VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
1306         EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
1307         EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
1308         EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
1309         EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
1310         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
1311         EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
1312         EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
1313         EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
1314         EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
1315         EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
1316         EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
1317         EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
1318         EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
1319         EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
1320         EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
1321         EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
1322         EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
1323         EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
1324         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
1325         EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
1326         EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
1327         EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1328         EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
1329         EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
1330         EVEX_W_0F3A72_P_2): Rename to ...
1331         (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
1332         MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
1333         MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
1334         MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
1335         MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
1336         MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
1337         MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
1338         MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
1339         MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
1340         MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
1341         MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
1342         VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
1343         VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
1344         VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
1345         VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
1346         VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
1347         VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
1348         VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
1349         VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
1350         VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
1351         EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
1352         EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
1353         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
1354         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
1355         EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
1356         EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
1357         EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
1358         EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
1359         EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
1360         EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
1361         EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
1362         EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
1363         EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
1364         EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
1365         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
1366         EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
1367         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
1368         EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
1369         EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
1370         EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
1371         EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
1372         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
1373         EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
1374         EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
1375         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
1376         VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
1377         VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
1378         VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
1379         VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
1380         VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
1381         VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
1382         VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
1383         VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
1384         VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
1385         VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
1386         VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
1387         VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
1388         VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
1389         EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
1390         EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
1391         EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
1392         EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
1393         EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
1394         EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
1395         EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
1396         EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
1397         EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
1398         EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
1399         EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
1400         EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
1401         EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
1402         EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
1403         respectively.
1404         (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
1405         vex_w_table, mod_table): Replace / remove respective entries.
1406         (print_insn): Move up dp->prefix_requirement handling. Handle
1407         PREFIX_DATA.
1408         * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
1409         i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
1410         Replace / remove respective entries.
1411
1412 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1413
1414         * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
1415         PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
1416         (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
1417         vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
1418         Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
1419         the latter two.
1420         * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1421         0F2C, 0F2D, 0F2E, and 0F2F.
1422         * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
1423         0F2F table entries.
1424
1425 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1426
1427         * i386-dis.c (OP_VexR, VexScalarR): New.
1428         (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
1429         XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
1430         need_vex_reg): Delete.
1431         (prefix_table): Replace VexScalar by VexScalarR and
1432         XMVexScalar by XMScalar for vmovss and vmovsd. Replace
1433         EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
1434         (vex_len_table): Replace EXqVexScalarS by EXqS.
1435         (get_valid_dis386): Don't set need_vex_reg.
1436         (print_insn): Don't initialize need_vex_reg.
1437         (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
1438         q_scalar_swap_mode cases.
1439         (OP_EX): Don't check for d_scalar_swap_mode and
1440         q_scalar_swap_mode.
1441         (OP_VEX): Done check need_vex_reg.
1442         * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
1443         XMVexScalar by XMScalar for vmovss and vmovsd. Replace
1444         EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
1445
1446 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1447
1448         * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
1449         (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
1450         VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
1451         VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
1452         (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
1453         VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
1454         VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
1455         VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
1456         (vex_table): Replace Vex128 by Vex.
1457         (vex_len_table): Likewise. Adjust referenced enum names.
1458         (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
1459         referenced enum names.
1460         (OP_VEX): Drop vex128_mode and vex256_mode cases.
1461         * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
1462
1463 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1464
1465         * i386-dis.c (dis386): "LW" description now applies to "DQ".
1466         (putop): Handle "DQ". Don't handle "LW" anymore.
1467         (prefix_table, mod_table): Replace %LW by %DQ.
1468         * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
1469
1470 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1471
1472         * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
1473         dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
1474         d_scalar_swap_mode case handling. Move shift adjsutment into
1475         the case its applicable to.
1476
1477 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1478
1479         * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
1480         (EXbScalar, EXwScalar): Fold to ...
1481         (EXbwUnit): ... this.
1482         (b_scalar_mode, w_scalar_mode): Fold to ...
1483         (bw_unit_mode): ... this.
1484         (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
1485         w_scalar_mode handling by bw_unit_mode one.
1486         * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
1487         ...
1488         * i386-dis-evex-prefix.h: ... here.
1489
1490 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1491
1492         * i386-dis.c (PCMPESTR_Fixup): Delete.
1493         (dis386): Adjust "LQ" description.
1494         (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
1495         cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
1496         PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
1497         vpcmpestrm, and vpcmpestri.
1498         (putop): Honor "cond" when handling LQ.
1499         * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
1500         vcvtsi2ss and vcvtusi2ss.
1501         * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
1502         vcvtsi2sd and vcvtusi2sd.
1503
1504 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1505
1506         * i386-dis.c (VCMP_Fixup, VCMP): Delete.
1507         (simd_cmp_op): Add const.
1508         (vex_cmp_op): Move up and drop initial 8 entries. Add const.
1509         (CMP_Fixup): Handle VEX case.
1510         (prefix_table): Replace VCMP by CMP.
1511         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
1512
1513 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1514
1515         * i386-dis.c (MOVBE_Fixup): Delete.
1516         (Mv): Define.
1517         (prefix_table): Use Mv for movbe entries.
1518
1519 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1520
1521         * i386-dis.c (CRC32_Fixup): Delete.
1522         (prefix_table): Use Eb/Ev for crc32 entries.
1523
1524 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1525
1526         * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
1527         Conditionalize invocations of "USED_REX (0)".
1528
1529 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1530
1531         * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
1532         CH, DH, BH, AX, DX): Delete.
1533         (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
1534         eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
1535         dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
1536
1537 2020-07-10  Lili Cui  <lili.cui@intel.com>
1538
1539         * i386-dis.c (TMM): New.
1540         (EXtmm): Likewise.
1541         (VexTmm): Likewise.
1542         (MVexSIBMEM): Likewise.
1543         (tmm_mode): Likewise.
1544         (vex_sibmem_mode): Likewise.
1545         (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
1546         (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
1547         (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
1548         (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
1549         (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
1550         (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
1551         (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
1552         (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
1553         (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
1554         (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
1555         (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
1556         (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
1557         (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
1558         (PREFIX_VEX_0F3849_X86_64): Likewise.
1559         (PREFIX_VEX_0F384B_X86_64): Likewise.
1560         (PREFIX_VEX_0F385C_X86_64): Likewise.
1561         (PREFIX_VEX_0F385E_X86_64): Likewise.
1562         (X86_64_VEX_0F3849): Likewise.
1563         (X86_64_VEX_0F384B): Likewise.
1564         (X86_64_VEX_0F385C): Likewise.
1565         (X86_64_VEX_0F385E): Likewise.
1566         (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
1567         (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
1568         (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
1569         (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
1570         (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
1571         (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
1572         (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
1573         (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
1574         (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
1575         (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
1576         (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
1577         (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
1578         (VEX_W_0F3849_X86_64_P_0): Likewise.
1579         (VEX_W_0F3849_X86_64_P_2): Likewise.
1580         (VEX_W_0F3849_X86_64_P_3): Likewise.
1581         (VEX_W_0F384B_X86_64_P_1): Likewise.
1582         (VEX_W_0F384B_X86_64_P_2): Likewise.
1583         (VEX_W_0F384B_X86_64_P_3): Likewise.
1584         (VEX_W_0F385C_X86_64_P_1): Likewise.
1585         (VEX_W_0F385E_X86_64_P_0): Likewise.
1586         (VEX_W_0F385E_X86_64_P_1): Likewise.
1587         (VEX_W_0F385E_X86_64_P_2): Likewise.
1588         (VEX_W_0F385E_X86_64_P_3): Likewise.
1589         (names_tmm): Likewise.
1590         (att_names_tmm): Likewise.
1591         (intel_operand_size): Handle void_mode.
1592         (OP_XMM): Handle tmm_mode.
1593         (OP_EX): Likewise.
1594         (OP_VEX): Likewise.
1595         * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
1596         CpuAMX_BF16 and CpuAMX_TILE.
1597         (operand_type_shorthands): Add RegTMM.
1598         (operand_type_init): Likewise.
1599         (operand_types): Add Tmmword.
1600         (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1601         (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1602         * i386-opc.h (CpuAMX_INT8): New.
1603         (CpuAMX_BF16): Likewise.
1604         (CpuAMX_TILE): Likewise.
1605         (SIBMEM): Likewise.
1606         (Tmmword): Likewise.
1607         (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
1608         (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
1609         (i386_operand_type): Add tmmword.
1610         * i386-opc.tbl: Add AMX instructions.
1611         * i386-reg.tbl: Add AMX registers.
1612         * i386-init.h: Regenerated.
1613         * i386-tbl.h: Likewise.
1614
1615 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1616
1617         * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
1618         (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
1619         Rename to ...
1620         (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
1621         REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
1622         respectively.
1623         (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
1624         VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
1625         VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
1626         VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
1627         VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
1628         VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
1629         VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
1630         VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
1631         VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
1632         VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
1633         VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
1634         VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
1635         VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
1636         VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
1637         VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
1638         VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
1639         VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
1640         VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
1641         VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
1642         VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
1643         VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
1644         VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
1645         VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
1646         VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
1647         VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
1648         VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
1649         VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
1650         VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
1651         VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
1652         VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
1653         VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
1654         VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
1655         VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
1656         VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
1657         VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
1658         VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
1659         (reg_table): Re-order XOP entries. Adjust their operands.
1660         (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
1661         08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
1662         08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
1663         09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
1664         09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
1665         09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
1666         entries by references ...
1667         (vex_len_table): ... to resepctive new entries here. For several
1668         new and existing entries reference ...
1669         (vex_w_table): ... new entries here.
1670         (mod_table): New MOD_VEX_0FXOP_09_12 entry.
1671
1672 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1673
1674         * i386-dis.c (XMVexScalarI4): Define.
1675         (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
1676         VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
1677         VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
1678         (vex_len_table): Move scalar FMA4 entries ...
1679         (prefix_table): ... here.
1680         (OP_REG_VexI4): Handle scalar_mode.
1681         * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
1682         * i386-tbl.h: Re-generate.
1683
1684 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1685
1686         * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
1687         Vex_2src_2): Delete.
1688         (OP_VexW, VexW): New.
1689         (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
1690         for shifts and rotates by register.
1691
1692 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1693
1694         * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
1695         VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
1696         OP_EX_VexReg): Delete.
1697         (OP_VexI4, VexI4): New.
1698         (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
1699         (prefix_table): ... here.
1700         (print_insn): Drop setting of vex_w_done.
1701
1702 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1703
1704         * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
1705         (prefix_table, vex_len_table): Replace operands for FMA4 insns.
1706         (xop_table): Replace operands of 4-operand insns.
1707         (OP_REG_VexI4): Move VEX.W based operand swaping here.
1708
1709 2020-07-07  Claudiu Zissulescu  <claziss@synopsys.com>
1710
1711         * arc-opc.c (insert_rbd): New function.
1712         (RBD): Define.
1713         (RBDdup): Likewise.
1714         * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
1715         instructions.
1716
1717 2020-07-07  Jan Beulich  <jbeulich@suse.com>
1718
1719         * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
1720         EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
1721         EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
1722         EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
1723         Delete.
1724         (putop): Handle "BW".
1725         * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
1726         0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
1727         and 0F3A3F ...
1728         * i386-dis-evex-prefix.h: ... here.
1729
1730 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1731
1732         * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
1733         (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
1734         VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
1735         VEX_W_0FXOP_09_83): New enumerators.
1736         (xop_table): Reference the above.
1737         (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
1738         (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
1739         VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
1740         (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
1741
1742 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1743
1744         * i386-dis.c (EVEX_W_0F3838_P_1,
1745         EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
1746         EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
1747         EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
1748         EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
1749         EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
1750         (putop): Centralize management of last[]. Delete SAVE_LAST.
1751         * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
1752         0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
1753         0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
1754         * i386-dis-evex-prefix.h: here.
1755
1756 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1757
1758         * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
1759         MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
1760         MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
1761         MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
1762         enumerators.
1763         (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
1764         EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
1765         EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
1766         EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
1767         (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
1768         EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
1769         EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1770         EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
1771         these, respectively.
1772         * i386-dis-evex-len.h: Adjust comments.
1773         * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
1774         MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1775         MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1776         MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
1777         MOD_EVEX_0F385B_P_2_W_1 table entries.
1778         * i386-dis-evex-w.h: Reference mod_table[] for
1779         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
1780         EVEX_W_0F385B_P_2.
1781
1782 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1783
1784         * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
1785         vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
1786         EXymm.
1787         (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
1788         Likewise. Mark 256-bit entries invalid.
1789
1790 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1791
1792         * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1793         PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1794         PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1795         PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1796         PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1797         PREFIX_EVEX_0F382B): Delete.
1798         (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
1799         EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
1800         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
1801         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
1802         EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
1803         to ...
1804         (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
1805         EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
1806         EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
1807         EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
1808         respectively.
1809         * i386-dis-evex.h (evex_table): Reference VEX_W table entries
1810         for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
1811         0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1812         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1813         PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1814         PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1815         PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1816         PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1817         PREFIX_EVEX_0F382B): Remove table entries.
1818         * i386-dis-evex-w.h: Reference VEX table entries for opcodes
1819         0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
1820         0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1821
1822 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1823
1824         * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1825         EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1826         enumerators.
1827         * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1828         EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1829         EVEX_LEN_0F3A01_P_2_W_1 table entries.
1830         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1831         entries.
1832
1833 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1834
1835         * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1836         EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1837         EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1838         EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1839         * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1840         EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1841         EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1842         EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1843         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1844         entries.
1845
1846 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1847
1848         * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1849         (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1850         (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1851         respectively.
1852         (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1853         entries.
1854         * i386-dis-evex.h (evex_table): Reference VEX table entry for
1855         opcode 0F3A1D.
1856         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1857         entry.
1858         * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1859
1860 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1861
1862         * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1863         PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1864         PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1865         PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1866         PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1867         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1868         PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1869         PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1870         PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1871         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1872         PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1873         PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1874         PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1875         PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1876         PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1877         PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1878         PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1879         PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1880         PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1881         PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1882         PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1883         PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1884         PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1885         PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1886         PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1887         PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1888         PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1889         EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1890         EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1891         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1892         (prefix_table): Add EXxEVexR to FMA table entries.
1893         (OP_Rounding): Move abort() invocation.
1894         * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1895         0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1896         0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1897         0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1898         0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1899         0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1900         0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1901         0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1902         0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1903         0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1904         0F3ACE, 0F3ACF.
1905         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1906         PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1907         PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1908         PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1909         PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1910         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1911         PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1912         PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1913         PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1914         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1915         PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1916         PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1917         PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1918         PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1919         PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1920         PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1921         PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1922         PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1923         PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1924         PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1925         PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1926         PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1927         PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1928         PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1929         PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1930         PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1931         PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1932         Delete table entries.
1933         * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1934         EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1935         EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1936         Likewise.
1937
1938 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1939
1940         * i386-dis.c (EXqScalarS): Delete.
1941         (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1942         * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1943
1944 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1945
1946         * i386-dis.c (safe-ctype.h): Include.
1947         (EXdScalar, EXqScalar): Delete.
1948         (d_scalar_mode, q_scalar_mode): Delete.
1949         (prefix_table, vex_len_table): Use EXxmm_md in place of
1950         EXdScalar and EXxmm_mq in place of EXqScalar.
1951         (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1952         d_scalar_mode and q_scalar_mode.
1953         * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1954         (vmovsd): Use EXxmm_mq.
1955
1956 2020-07-06  Yuri Chornoivan  <yurchor@ukr.net>
1957
1958         PR 26204
1959         * arc-dis.c: Fix spelling mistake.
1960         * po/opcodes.pot: Regenerate.
1961
1962 2020-07-06  Nick Clifton  <nickc@redhat.com>
1963
1964         * po/pt_BR.po: Updated Brazilian Portugugese translation.
1965         * po/uk.po: Updated Ukranian translation.
1966
1967 2020-07-04  Nick Clifton  <nickc@redhat.com>
1968
1969         * configure: Regenerate.
1970         * po/opcodes.pot: Regenerate.
1971
1972 2020-07-04  Nick Clifton  <nickc@redhat.com>
1973
1974         Binutils 2.35 branch created.
1975
1976 2020-07-02  H.J. Lu  <hongjiu.lu@intel.com>
1977
1978         * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1979         * i386-opc.h (VexSwapSources): New.
1980         (i386_opcode_modifier): Add vexswapsources.
1981         * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1982         with two source operands swapped.
1983         * i386-tbl.h: Regenerated.
1984
1985 2020-06-30  Nelson Chu  <nelson.chu@sifive.com>
1986
1987         * riscv-dis.c (print_insn_args, case 'E'): Updated.  Let the
1988         unprivileged CSR can also be initialized.
1989
1990 2020-06-29  Alan Modra  <amodra@gmail.com>
1991
1992         * arm-dis.c: Use C style comments.
1993         * cr16-opc.c: Likewise.
1994         * ft32-dis.c: Likewise.
1995         * moxie-opc.c: Likewise.
1996         * tic54x-dis.c: Likewise.
1997         * s12z-opc.c: Remove useless comment.
1998         * xgate-dis.c: Likewise.
1999
2000 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
2001
2002         * i386-opc.tbl: Add a blank line.
2003
2004 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
2005
2006         * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
2007         (VecSIB128): Renamed to ...
2008         (VECSIB128): This.
2009         (VecSIB256): Renamed to ...
2010         (VECSIB256): This.
2011         (VecSIB512): Renamed to ...
2012         (VECSIB512): This.
2013         (VecSIB): Renamed to ...
2014         (SIB): This.
2015         (i386_opcode_modifier): Replace vecsib with sib.
2016         * i386-opc.tbl (VecSIB128): New.
2017         (VecSIB256): Likewise.
2018         (VecSIB512): Likewise.
2019         Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
2020         and VecSIB512, respectively.
2021
2022 2020-06-26  Jan Beulich  <jbeulich@suse.com>
2023
2024         * i386-dis.c: Adjust description of I macro.
2025         (x86_64_table): Drop use of I.
2026         (float_mem): Replace use of I.
2027         (putop): Remove handling of I. Adjust setting/clearing of "alt".
2028
2029 2020-06-26  Jan Beulich  <jbeulich@suse.com>
2030
2031         * i386-dis.c: (print_insn): Avoid straight assignment to
2032         priv.orig_sizeflag when processing -M sub-options.
2033
2034 2020-06-25  Jan Beulich  <jbeulich@suse.com>
2035
2036         * i386-dis.c: Adjust description of J macro.
2037         (dis386, x86_64_table, mod_table): Replace J.
2038         (putop): Remove handling of J.
2039
2040 2020-06-25  Jan Beulich  <jbeulich@suse.com>
2041
2042         * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
2043
2044 2020-06-25  Jan Beulich  <jbeulich@suse.com>
2045
2046         * i386-dis.c: Adjust description of "LQ" macro.
2047         (dis386_twobyte): Use LQ for sysret.
2048         (putop): Adjust handling of LQ.
2049
2050 2020-06-22  Nelson Chu  <nelson.chu@sifive.com>
2051
2052         * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
2053         * riscv-dis.c: Include elfxx-riscv.h.
2054
2055 2020-06-18  H.J. Lu  <hongjiu.lu@intel.com>
2056
2057         * i386-dis.c (prefix_table): Revert the last vmgexit change.
2058
2059 2020-06-17  Lili Cui  <lili.cui@intel.com>
2060
2061         * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
2062
2063 2020-06-14  H.J. Lu  <hongjiu.lu@intel.com>
2064
2065         PR gas/26115
2066         * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
2067         * i386-opc.tbl: Likewise.
2068         * i386-tbl.h: Regenerated.
2069
2070 2020-06-12  Nelson Chu  <nelson.chu@sifive.com>
2071
2072         * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
2073
2074 2020-06-11  Alex Coplan  <alex.coplan@arm.com>
2075
2076         * aarch64-opc.c (SYSREG): New macro for describing system registers.
2077         (SR_CORE): Likewise.
2078         (SR_FEAT): Likewise.
2079         (SR_RNG): Likewise.
2080         (SR_V8_1): Likewise.
2081         (SR_V8_2): Likewise.
2082         (SR_V8_3): Likewise.
2083         (SR_V8_4): Likewise.
2084         (SR_PAN): Likewise.
2085         (SR_RAS): Likewise.
2086         (SR_SSBS): Likewise.
2087         (SR_SVE): Likewise.
2088         (SR_ID_PFR2): Likewise.
2089         (SR_PROFILE): Likewise.
2090         (SR_MEMTAG): Likewise.
2091         (SR_SCXTNUM): Likewise.
2092         (aarch64_sys_regs): Refactor to store feature information in the table.
2093         (aarch64_sys_reg_supported_p): Collapse logic for system registers
2094         that now describe their own features.
2095         (aarch64_pstatefield_supported_p): Likewise.
2096
2097 2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>
2098
2099         * i386-dis.c (prefix_table): Fix a typo in comments.
2100
2101 2020-06-09  Jan Beulich  <jbeulich@suse.com>
2102
2103         * i386-dis.c (rex_ignored): Delete.
2104         (ckprefix): Drop rex_ignored initialization.
2105         (get_valid_dis386): Drop setting of rex_ignored.
2106         (print_insn): Drop checking of rex_ignored. Don't record data
2107         size prefix as used with VEX-and-alike encodings.
2108
2109 2020-06-09  Jan Beulich  <jbeulich@suse.com>
2110
2111         * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
2112         MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
2113         (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
2114         (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
2115         (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
2116         VEX_0F12, and VEX_0F16.
2117         (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
2118         VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
2119         (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
2120         from movlps and movhlps. New MOD_0F12_PREFIX_2,
2121         MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
2122         MOD_VEX_0F16_PREFIX_2 entries.
2123
2124 2020-06-09  Jan Beulich  <jbeulich@suse.com>
2125
2126         * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
2127         MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
2128         (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
2129         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
2130         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
2131         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
2132         EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
2133         EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
2134         EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
2135         EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
2136         EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
2137         EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
2138         EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
2139         EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
2140         EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
2141         EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
2142         EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
2143         EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
2144         EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
2145         EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
2146         EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
2147         EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
2148         EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
2149         EVEX_W_0FC6_P_2): Delete.
2150         (print_insn): Add EVEX.W vs embedded prefix consistency check
2151         to prefix validation.
2152         * i386-dis-evex.h (evex_table): Don't further descend for
2153         vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
2154         and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
2155         and 0F2B.
2156         * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
2157         * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
2158         vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
2159         vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
2160         2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
2161         Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
2162         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
2163         PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
2164         PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
2165         * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
2166         EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
2167         EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
2168         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
2169         EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
2170         EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
2171         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
2172         EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
2173         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
2174         EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
2175         EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
2176         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
2177         EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
2178         EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
2179         EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
2180         EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
2181         EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
2182         EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
2183
2184 2020-06-09  Jan Beulich  <jbeulich@suse.com>
2185
2186         * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
2187         vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
2188         (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
2189         vmovmskpX.
2190         (print_insn): Drop pointless check against bad_opcode. Split
2191         prefix validation into legacy and VEX-and-alike parts.
2192         (putop): Re-work 'X' macro handling.
2193
2194 2020-06-09  Jan Beulich  <jbeulich@suse.com>
2195
2196         * i386-dis.c (MOD_0F51): Rename to ...
2197         (MOD_0F50): ... this.
2198
2199 2020-06-08  Alex Coplan  <alex.coplan@arm.com>
2200
2201         * arm-dis.c (arm_opcodes): Add dfb.
2202         (thumb32_opcodes): Add dfb.
2203
2204 2020-06-08  Jan Beulich  <jbeulich@suse.com>
2205
2206         * i386-opc.h (reg_entry): Const-qualify reg_name field.
2207
2208 2020-06-06  Alan Modra  <amodra@gmail.com>
2209
2210         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
2211
2212 2020-06-05  Alan Modra  <amodra@gmail.com>
2213
2214         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
2215         size is large enough.
2216
2217 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
2218
2219         * disassemble.c (disassemble_init_for_target): Set endian_code for
2220         bpf targets.
2221         * bpf-desc.c: Regenerate.
2222         * bpf-opc.c: Likewise.
2223         * bpf-dis.c: Likewise.
2224
2225 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
2226
2227         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
2228         (cgen_put_insn_value): Likewise.
2229         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
2230         * cgen-dis.in (print_insn): Likewise.
2231         * cgen-ibld.in (insert_1): Likewise.
2232         (insert_1): Likewise.
2233         (insert_insn_normal): Likewise.
2234         (extract_1): Likewise.
2235         * bpf-dis.c: Regenerate.
2236         * bpf-ibld.c: Likewise.
2237         * bpf-ibld.c: Likewise.
2238         * cgen-dis.in: Likewise.
2239         * cgen-ibld.in: Likewise.
2240         * cgen-opc.c: Likewise.
2241         * epiphany-dis.c: Likewise.
2242         * epiphany-ibld.c: Likewise.
2243         * fr30-dis.c: Likewise.
2244         * fr30-ibld.c: Likewise.
2245         * frv-dis.c: Likewise.
2246         * frv-ibld.c: Likewise.
2247         * ip2k-dis.c: Likewise.
2248         * ip2k-ibld.c: Likewise.
2249         * iq2000-dis.c: Likewise.
2250         * iq2000-ibld.c: Likewise.
2251         * lm32-dis.c: Likewise.
2252         * lm32-ibld.c: Likewise.
2253         * m32c-dis.c: Likewise.
2254         * m32c-ibld.c: Likewise.
2255         * m32r-dis.c: Likewise.
2256         * m32r-ibld.c: Likewise.
2257         * mep-dis.c: Likewise.
2258         * mep-ibld.c: Likewise.
2259         * mt-dis.c: Likewise.
2260         * mt-ibld.c: Likewise.
2261         * or1k-dis.c: Likewise.
2262         * or1k-ibld.c: Likewise.
2263         * xc16x-dis.c: Likewise.
2264         * xc16x-ibld.c: Likewise.
2265         * xstormy16-dis.c: Likewise.
2266         * xstormy16-ibld.c: Likewise.
2267
2268 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
2269
2270         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
2271         (print_insn_): Handle instruction endian.
2272         * bpf-dis.c: Regenerate.
2273         * bpf-desc.c: Regenerate.
2274         * epiphany-dis.c: Likewise.
2275         * epiphany-desc.c: Likewise.
2276         * fr30-dis.c: Likewise.
2277         * fr30-desc.c: Likewise.
2278         * frv-dis.c: Likewise.
2279         * frv-desc.c: Likewise.
2280         * ip2k-dis.c: Likewise.
2281         * ip2k-desc.c: Likewise.
2282         * iq2000-dis.c: Likewise.
2283         * iq2000-desc.c: Likewise.
2284         * lm32-dis.c: Likewise.
2285         * lm32-desc.c: Likewise.
2286         * m32c-dis.c: Likewise.
2287         * m32c-desc.c: Likewise.
2288         * m32r-dis.c: Likewise.
2289         * m32r-desc.c: Likewise.
2290         * mep-dis.c: Likewise.
2291         * mep-desc.c: Likewise.
2292         * mt-dis.c: Likewise.
2293         * mt-desc.c: Likewise.
2294         * or1k-dis.c: Likewise.
2295         * or1k-desc.c: Likewise.
2296         * xc16x-dis.c: Likewise.
2297         * xc16x-desc.c: Likewise.
2298         * xstormy16-dis.c: Likewise.
2299         * xstormy16-desc.c: Likewise.
2300
2301 2020-06-03  Nick Clifton  <nickc@redhat.com>
2302
2303         * po/sr.po: Updated Serbian translation.
2304
2305 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
2306
2307         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
2308         (riscv_get_priv_spec_class): Likewise.
2309
2310 2020-06-01  Alan Modra  <amodra@gmail.com>
2311
2312         * bpf-desc.c: Regenerate.
2313
2314 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
2315             David Faust <david.faust@oracle.com>
2316
2317         * bpf-desc.c: Regenerate.
2318         * bpf-opc.h: Likewise.
2319         * bpf-opc.c: Likewise.
2320         * bpf-dis.c: Likewise.
2321
2322 2020-05-28  Alan Modra  <amodra@gmail.com>
2323
2324         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
2325         values.
2326
2327 2020-05-28  Alan Modra  <amodra@gmail.com>
2328
2329         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
2330         immediates.
2331         (print_insn_ns32k): Revert last change.
2332
2333 2020-05-28  Nick Clifton  <nickc@redhat.com>
2334
2335         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
2336         static.
2337
2338 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
2339
2340         Fix extraction of signed constants in nios2 disassembler (again).
2341
2342         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
2343         extractions of signed fields.
2344
2345 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
2346
2347         * s390-opc.txt: Relocate vector load/store instructions with
2348         additional alignment parameter and change architecture level
2349         constraint from z14 to z13.
2350
2351 2020-05-21  Alan Modra  <amodra@gmail.com>
2352
2353         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
2354         * sparc-dis.c: Likewise.
2355         * tic4x-dis.c: Likewise.
2356         * xtensa-dis.c: Likewise.
2357         * bpf-desc.c: Regenerate.
2358         * epiphany-desc.c: Regenerate.
2359         * fr30-desc.c: Regenerate.
2360         * frv-desc.c: Regenerate.
2361         * ip2k-desc.c: Regenerate.
2362         * iq2000-desc.c: Regenerate.
2363         * lm32-desc.c: Regenerate.
2364         * m32c-desc.c: Regenerate.
2365         * m32r-desc.c: Regenerate.
2366         * mep-asm.c: Regenerate.
2367         * mep-desc.c: Regenerate.
2368         * mt-desc.c: Regenerate.
2369         * or1k-desc.c: Regenerate.
2370         * xc16x-desc.c: Regenerate.
2371         * xstormy16-desc.c: Regenerate.
2372
2373 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
2374
2375         * riscv-opc.c (riscv_ext_version_table): The table used to store
2376         all information about the supported spec and the corresponding ISA
2377         versions.  Currently, only Zicsr is supported to verify the
2378         correctness of Z sub extension settings.  Others will be supported
2379         in the future patches.
2380         (struct isa_spec_t, isa_specs): List for all supported ISA spec
2381         classes and the corresponding strings.
2382         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
2383         spec class by giving a ISA spec string.
2384         * riscv-opc.c (struct priv_spec_t): New structure.
2385         (struct priv_spec_t priv_specs): List for all supported privilege spec
2386         classes and the corresponding strings.
2387         (riscv_get_priv_spec_class): New function.  Get the corresponding
2388         privilege spec class by giving a spec string.
2389         (riscv_get_priv_spec_name): New function.  Get the corresponding
2390         privilege spec string by giving a CSR version class.
2391         * riscv-dis.c: Updated since DECLARE_CSR is changed.
2392         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
2393         according to the chosen version.  Build a hash table riscv_csr_hash to
2394         store the valid CSR for the chosen pirv verison.  Dump the direct
2395         CSR address rather than it's name if it is invalid.
2396         (parse_riscv_dis_option_without_args): New function.  Parse the options
2397         without arguments.
2398         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
2399         parse the options without arguments first, and then handle the options
2400         with arguments.  Add the new option -Mpriv-spec, which has argument.
2401         * riscv-dis.c (print_riscv_disassembler_options): Add description
2402         about the new OBJDUMP option.
2403
2404 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
2405
2406         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
2407         WC values on POWER10 sync, dcbf  and wait instructions.
2408         (insert_pl, extract_pl): New functions.
2409         (L2OPT, LS, WC): Use insert_ls and extract_ls.
2410         (LS3): New , 3-bit L for sync.
2411         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
2412         (SC2, PL): New, 2-bit SC and PL for sync and wait.
2413         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
2414         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
2415         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
2416         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
2417         <wait>: Enable PL operand on POWER10.
2418         <dcbf>: Enable L3OPT operand on POWER10.
2419         <sync>: Enable SC2 operand on POWER10.
2420
2421 2020-05-19  Stafford Horne  <shorne@gmail.com>
2422
2423         PR 25184
2424         * or1k-asm.c: Regenerate.
2425         * or1k-desc.c: Regenerate.
2426         * or1k-desc.h: Regenerate.
2427         * or1k-dis.c: Regenerate.
2428         * or1k-ibld.c: Regenerate.
2429         * or1k-opc.c: Regenerate.
2430         * or1k-opc.h: Regenerate.
2431         * or1k-opinst.c: Regenerate.
2432
2433 2020-05-11  Alan Modra  <amodra@gmail.com>
2434
2435         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
2436         xsmaxcqp, xsmincqp.
2437
2438 2020-05-11  Alan Modra  <amodra@gmail.com>
2439
2440         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
2441         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
2442
2443 2020-05-11  Alan Modra  <amodra@gmail.com>
2444
2445         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
2446
2447 2020-05-11  Alan Modra  <amodra@gmail.com>
2448
2449         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
2450         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
2451
2452 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
2453
2454         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
2455         mnemonics.
2456
2457 2020-05-11  Alan Modra  <amodra@gmail.com>
2458
2459         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
2460         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
2461         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
2462         (prefix_opcodes): Add xxeval.
2463
2464 2020-05-11  Alan Modra  <amodra@gmail.com>
2465
2466         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
2467         xxgenpcvwm, xxgenpcvdm.
2468
2469 2020-05-11  Alan Modra  <amodra@gmail.com>
2470
2471         * ppc-opc.c (MP, VXVAM_MASK): Define.
2472         (VXVAPS_MASK): Use VXVA_MASK.
2473         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
2474         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
2475         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
2476         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
2477
2478 2020-05-11  Alan Modra  <amodra@gmail.com>
2479             Peter Bergner  <bergner@linux.ibm.com>
2480
2481         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
2482         New functions.
2483         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
2484         YMSK2, XA6a, XA6ap, XB6a entries.
2485         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
2486         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
2487         (PPCVSX4): Define.
2488         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
2489         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
2490         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
2491         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
2492         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
2493         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
2494         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
2495         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
2496         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
2497         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
2498         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
2499         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
2500         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
2501         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
2502
2503 2020-05-11  Alan Modra  <amodra@gmail.com>
2504
2505         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
2506         (insert_xts, extract_xts): New functions.
2507         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
2508         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
2509         (VXRC_MASK, VXSH_MASK): Define.
2510         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
2511         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
2512         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
2513         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
2514         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
2515         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
2516         xxblendvh, xxblendvw, xxblendvd, xxpermx.
2517
2518 2020-05-11  Alan Modra  <amodra@gmail.com>
2519
2520         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
2521         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
2522         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
2523         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
2524         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
2525
2526 2020-05-11  Alan Modra  <amodra@gmail.com>
2527
2528         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
2529         (XTP, DQXP, DQXP_MASK): Define.
2530         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
2531         (prefix_opcodes): Add plxvp and pstxvp.
2532
2533 2020-05-11  Alan Modra  <amodra@gmail.com>
2534
2535         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
2536         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
2537         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
2538
2539 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
2540
2541         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
2542
2543 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
2544
2545         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
2546         (L1OPT): Define.
2547         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
2548
2549 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
2550
2551         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
2552
2553 2020-05-11  Alan Modra  <amodra@gmail.com>
2554
2555         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
2556
2557 2020-05-11  Alan Modra  <amodra@gmail.com>
2558
2559         * ppc-dis.c (ppc_opts): Add "power10" entry.
2560         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
2561         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
2562
2563 2020-05-11  Nick Clifton  <nickc@redhat.com>
2564
2565         * po/fr.po: Updated French translation.
2566
2567 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
2568
2569         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
2570         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
2571         (operand_general_constraint_met_p): validate
2572         AARCH64_OPND_UNDEFINED.
2573         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
2574         for FLD_imm16_2.
2575         * aarch64-asm-2.c: Regenerated.
2576         * aarch64-dis-2.c: Regenerated.
2577         * aarch64-opc-2.c: Regenerated.
2578
2579 2020-04-29  Nick Clifton  <nickc@redhat.com>
2580
2581         PR 22699
2582         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
2583         and SETRC insns.
2584
2585 2020-04-29  Nick Clifton  <nickc@redhat.com>
2586
2587         * po/sv.po: Updated Swedish translation.
2588
2589 2020-04-29  Nick Clifton  <nickc@redhat.com>
2590
2591         PR 22699
2592         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
2593         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
2594         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
2595         IMM0_8U case.
2596
2597 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
2598
2599         PR 25848
2600         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
2601         cmpi only on m68020up and cpu32.
2602
2603 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
2604
2605         * aarch64-asm.c (aarch64_ins_none): New.
2606         * aarch64-asm.h (ins_none): New declaration.
2607         * aarch64-dis.c (aarch64_ext_none): New.
2608         * aarch64-dis.h (ext_none): New declaration.
2609         * aarch64-opc.c (aarch64_print_operand): Update case for
2610         AARCH64_OPND_BARRIER_PSB.
2611         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
2612         (AARCH64_OPERANDS): Update inserter/extracter for
2613         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
2614         * aarch64-asm-2.c: Regenerated.
2615         * aarch64-dis-2.c: Regenerated.
2616         * aarch64-opc-2.c: Regenerated.
2617
2618 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
2619
2620         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
2621         (aarch64_feature_ras, RAS): Likewise.
2622         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
2623         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
2624         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
2625         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
2626         * aarch64-asm-2.c: Regenerated.
2627         * aarch64-dis-2.c: Regenerated.
2628         * aarch64-opc-2.c: Regenerated.
2629
2630 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
2631
2632         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
2633         (print_insn_neon): Support disassembly of conditional
2634         instructions.
2635
2636 2020-02-16  David Faust  <david.faust@oracle.com>
2637
2638         * bpf-desc.c: Regenerate.
2639         * bpf-desc.h: Likewise.
2640         * bpf-opc.c: Regenerate.
2641         * bpf-opc.h: Likewise.
2642
2643 2020-04-07  Lili Cui  <lili.cui@intel.com>
2644
2645         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
2646         (prefix_table): New instructions (see prefixes above).
2647         (rm_table): Likewise
2648         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
2649         CPU_ANY_TSXLDTRK_FLAGS.
2650         (cpu_flags): Add CpuTSXLDTRK.
2651         * i386-opc.h (enum): Add CpuTSXLDTRK.
2652         (i386_cpu_flags): Add cputsxldtrk.
2653         * i386-opc.tbl: Add XSUSPLDTRK insns.
2654         * i386-init.h: Regenerate.
2655         * i386-tbl.h: Likewise.
2656
2657 2020-04-02  Lili Cui  <lili.cui@intel.com>
2658
2659         * i386-dis.c (prefix_table): New instructions serialize.
2660         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
2661         CPU_ANY_SERIALIZE_FLAGS.
2662         (cpu_flags): Add CpuSERIALIZE.
2663         * i386-opc.h (enum): Add CpuSERIALIZE.
2664         (i386_cpu_flags): Add cpuserialize.
2665         * i386-opc.tbl: Add SERIALIZE insns.
2666         * i386-init.h: Regenerate.
2667         * i386-tbl.h: Likewise.
2668
2669 2020-03-26  Alan Modra  <amodra@gmail.com>
2670
2671         * disassemble.h (opcodes_assert): Declare.
2672         (OPCODES_ASSERT): Define.
2673         * disassemble.c: Don't include assert.h.  Include opintl.h.
2674         (opcodes_assert): New function.
2675         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
2676         (bfd_h8_disassemble): Reduce size of data array.  Correctly
2677         calculate maxlen.  Omit insn decoding when insn length exceeds
2678         maxlen.  Exit from nibble loop when looking for E, before
2679         accessing next data byte.  Move processing of E outside loop.
2680         Replace tests of maxlen in loop with assertions.
2681
2682 2020-03-26  Alan Modra  <amodra@gmail.com>
2683
2684         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
2685
2686 2020-03-25  Alan Modra  <amodra@gmail.com>
2687
2688         * z80-dis.c (suffix): Init mybuf.
2689
2690 2020-03-22  Alan Modra  <amodra@gmail.com>
2691
2692         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
2693         successflly read from section.
2694
2695 2020-03-22  Alan Modra  <amodra@gmail.com>
2696
2697         * arc-dis.c (find_format): Use ISO C string concatenation rather
2698         than line continuation within a string.  Don't access needs_limm
2699         before testing opcode != NULL.
2700
2701 2020-03-22  Alan Modra  <amodra@gmail.com>
2702
2703         * ns32k-dis.c (print_insn_arg): Update comment.
2704         (print_insn_ns32k): Reduce size of index_offset array, and
2705         initialize, passing -1 to print_insn_arg for args that are not
2706         an index.  Don't exit arg loop early.  Abort on bad arg number.
2707
2708 2020-03-22  Alan Modra  <amodra@gmail.com>
2709
2710         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
2711         * s12z-opc.c: Formatting.
2712         (operands_f): Return an int.
2713         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
2714         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
2715         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
2716         (exg_sex_discrim): Likewise.
2717         (create_immediate_operand, create_bitfield_operand),
2718         (create_register_operand_with_size, create_register_all_operand),
2719         (create_register_all16_operand, create_simple_memory_operand),
2720         (create_memory_operand, create_memory_auto_operand): Don't
2721         segfault on malloc failure.
2722         (z_ext24_decode): Return an int status, negative on fail, zero
2723         on success.
2724         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
2725         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
2726         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
2727         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
2728         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
2729         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
2730         (loop_primitive_decode, shift_decode, psh_pul_decode),
2731         (bit_field_decode): Similarly.
2732         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
2733         to return value, update callers.
2734         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
2735         Don't segfault on NULL operand.
2736         (decode_operation): Return OP_INVALID on first fail.
2737         (decode_s12z): Check all reads, returning -1 on fail.
2738
2739 2020-03-20  Alan Modra  <amodra@gmail.com>
2740
2741         * metag-dis.c (print_insn_metag): Don't ignore status from
2742         read_memory_func.
2743
2744 2020-03-20  Alan Modra  <amodra@gmail.com>
2745
2746         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
2747         Initialize parts of buffer not written when handling a possible
2748         2-byte insn at end of section.  Don't attempt decoding of such
2749         an insn by the 4-byte machinery.
2750
2751 2020-03-20  Alan Modra  <amodra@gmail.com>
2752
2753         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
2754         partially filled buffer.  Prevent lookup of 4-byte insns when
2755         only VLE 2-byte insns are possible due to section size.  Print
2756         ".word" rather than ".long" for 2-byte leftovers.
2757
2758 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
2759
2760         PR 25641
2761         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
2762
2763 2020-03-13  Jan Beulich  <jbeulich@suse.com>
2764
2765         * i386-dis.c (X86_64_0D): Rename to ...
2766         (X86_64_0E): ... this.
2767
2768 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
2769
2770         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
2771         * Makefile.in: Regenerated.
2772
2773 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2774
2775         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
2776         3-operand pseudos.
2777         * i386-tbl.h: Re-generate.
2778
2779 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2780
2781         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
2782         vprot*, vpsha*, and vpshl*.
2783         * i386-tbl.h: Re-generate.
2784
2785 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2786
2787         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
2788         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
2789         * i386-tbl.h: Re-generate.
2790
2791 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2792
2793         * i386-gen.c (set_bitfield): Ignore zero-length field names.
2794         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
2795         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
2796         * i386-tbl.h: Re-generate.
2797
2798 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2799
2800         * i386-gen.c (struct template_arg, struct template_instance,
2801         struct template_param, struct template, templates,
2802         parse_template, expand_templates): New.
2803         (process_i386_opcodes): Various local variables moved to
2804         expand_templates. Call parse_template and expand_templates.
2805         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
2806         * i386-tbl.h: Re-generate.
2807
2808 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2809
2810         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
2811         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
2812         register and memory source templates. Replace VexW= by VexW*
2813         where applicable.
2814         * i386-tbl.h: Re-generate.
2815
2816 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2817
2818         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
2819         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
2820         * i386-tbl.h: Re-generate.
2821
2822 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2823
2824         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2825         * i386-tbl.h: Re-generate.
2826
2827 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2828
2829         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2830         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2831         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2832         VexW0 on SSE2AVX variants.
2833         (vmovq): Drop NoRex64 from XMM/XMM variants.
2834         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2835         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2836         applicable use VexW0.
2837         * i386-tbl.h: Re-generate.
2838
2839 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2840
2841         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2842         * i386-opc.h (Rex64): Delete.
2843         (struct i386_opcode_modifier): Remove rex64 field.
2844         * i386-opc.tbl (crc32): Drop Rex64.
2845         Replace Rex64 with Size64 everywhere else.
2846         * i386-tbl.h: Re-generate.
2847
2848 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2849
2850         * i386-dis.c (OP_E_memory): Exclude recording of used address
2851         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2852         addressed memory operands for MPX insns.
2853
2854 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2855
2856         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2857         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2858         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2859         (ptwrite): Split into non-64-bit and 64-bit forms.
2860         * i386-tbl.h: Re-generate.
2861
2862 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2863
2864         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2865         template.
2866         * i386-tbl.h: Re-generate.
2867
2868 2020-03-04  Jan Beulich  <jbeulich@suse.com>
2869
2870         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2871         (prefix_table): Move vmmcall here. Add vmgexit.
2872         (rm_table): Replace vmmcall entry by prefix_table[] escape.
2873         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2874         (cpu_flags): Add CpuSEV_ES entry.
2875         * i386-opc.h (CpuSEV_ES): New.
2876         (union i386_cpu_flags): Add cpusev_es field.
2877         * i386-opc.tbl (vmgexit): New.
2878         * i386-init.h, i386-tbl.h: Re-generate.
2879
2880 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
2881
2882         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2883         with MnemonicSize.
2884         * i386-opc.h (IGNORESIZE): New.
2885         (DEFAULTSIZE): Likewise.
2886         (IgnoreSize): Removed.
2887         (DefaultSize): Likewise.
2888         (MnemonicSize): New.
2889         (i386_opcode_modifier): Replace ignoresize/defaultsize with
2890         mnemonicsize.
2891         * i386-opc.tbl (IgnoreSize): New.
2892         (DefaultSize): Likewise.
2893         * i386-tbl.h: Regenerated.
2894
2895 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
2896
2897         PR 25627
2898         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2899         instructions.
2900
2901 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
2902
2903         PR gas/25622
2904         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2905         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2906         * i386-tbl.h: Regenerated.
2907
2908 2020-02-26  Alan Modra  <amodra@gmail.com>
2909
2910         * aarch64-asm.c: Indent labels correctly.
2911         * aarch64-dis.c: Likewise.
2912         * aarch64-gen.c: Likewise.
2913         * aarch64-opc.c: Likewise.
2914         * alpha-dis.c: Likewise.
2915         * i386-dis.c: Likewise.
2916         * nds32-asm.c: Likewise.
2917         * nfp-dis.c: Likewise.
2918         * visium-dis.c: Likewise.
2919
2920 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
2921
2922         * arc-regs.h (int_vector_base): Make it available for all ARC
2923         CPUs.
2924
2925 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
2926
2927         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2928         changed.
2929
2930 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
2931
2932         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2933         c.mv/c.li if rs1 is zero.
2934
2935 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
2936
2937         * i386-gen.c (cpu_flag_init): Replace CpuABM with
2938         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
2939         CPU_POPCNT_FLAGS.
2940         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
2941         * i386-opc.h (CpuABM): Removed.
2942         (CpuPOPCNT): New.
2943         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
2944         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2945         popcnt.  Remove CpuABM from lzcnt.
2946         * i386-init.h: Regenerated.
2947         * i386-tbl.h: Likewise.
2948
2949 2020-02-17  Jan Beulich  <jbeulich@suse.com>
2950
2951         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2952         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2953         VexW1 instead of open-coding them.
2954         * i386-tbl.h: Re-generate.
2955
2956 2020-02-17  Jan Beulich  <jbeulich@suse.com>
2957
2958         * i386-opc.tbl (AddrPrefixOpReg): Define.
2959         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2960         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2961         templates. Drop NoRex64.
2962         * i386-tbl.h: Re-generate.
2963
2964 2020-02-17  Jan Beulich  <jbeulich@suse.com>
2965
2966         PR gas/6518
2967         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2968         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2969         into Intel syntax instance (with Unpsecified) and AT&T one
2970         (without).
2971         (vcvtneps2bf16): Likewise, along with folding the two so far
2972         separate ones.
2973         * i386-tbl.h: Re-generate.
2974
2975 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
2976
2977         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2978         CPU_ANY_SSE4A_FLAGS.
2979
2980 2020-02-17  Alan Modra  <amodra@gmail.com>
2981
2982         * i386-gen.c (cpu_flag_init): Correct last change.
2983
2984 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
2985
2986         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
2987         CPU_ANY_SSE4_FLAGS.
2988
2989 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
2990
2991         * i386-opc.tbl (movsx): Remove Intel syntax comments.
2992         (movzx): Likewise.
2993
2994 2020-02-14  Jan Beulich  <jbeulich@suse.com>
2995
2996         PR gas/25438
2997         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2998         destination for Cpu64-only variant.
2999         (movzx): Fold patterns.
3000         * i386-tbl.h: Re-generate.
3001
3002 2020-02-13  Jan Beulich  <jbeulich@suse.com>
3003
3004         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
3005         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
3006         CPU_ANY_SSE4_FLAGS entry.
3007         * i386-init.h: Re-generate.
3008
3009 2020-02-12  Jan Beulich  <jbeulich@suse.com>
3010
3011         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
3012         with Unspecified, making the present one AT&T syntax only.
3013         * i386-tbl.h: Re-generate.
3014
3015 2020-02-12  Jan Beulich  <jbeulich@suse.com>
3016
3017         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
3018         * i386-tbl.h: Re-generate.
3019
3020 2020-02-12  Jan Beulich  <jbeulich@suse.com>
3021
3022         PR gas/24546
3023         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
3024         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
3025         Amd64 and Intel64 templates.
3026         (call, jmp): Likewise for far indirect variants. Dro
3027         Unspecified.
3028         * i386-tbl.h: Re-generate.
3029
3030 2020-02-11  Jan Beulich  <jbeulich@suse.com>
3031
3032         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
3033         * i386-opc.h (ShortForm): Delete.
3034         (struct i386_opcode_modifier): Remove shortform field.
3035         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
3036         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
3037         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
3038         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
3039         Drop ShortForm.
3040         * i386-tbl.h: Re-generate.
3041
3042 2020-02-11  Jan Beulich  <jbeulich@suse.com>
3043
3044         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
3045         fucompi): Drop ShortForm from operand-less templates.
3046         * i386-tbl.h: Re-generate.
3047
3048 2020-02-11  Alan Modra  <amodra@gmail.com>
3049
3050         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
3051         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
3052         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
3053         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
3054         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
3055
3056 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
3057
3058         * arm-dis.c (print_insn_cde): Define 'V' parse character.
3059         (cde_opcodes): Add VCX* instructions.
3060
3061 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
3062             Matthew Malcomson  <matthew.malcomson@arm.com>
3063
3064         * arm-dis.c (struct cdeopcode32): New.
3065         (CDE_OPCODE): New macro.
3066         (cde_opcodes): New disassembly table.
3067         (regnames): New option to table.
3068         (cde_coprocs): New global variable.
3069         (print_insn_cde): New
3070         (print_insn_thumb32): Use print_insn_cde.
3071         (parse_arm_disassembler_options): Parse coprocN args.
3072
3073 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
3074
3075         PR gas/25516
3076         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
3077         with ISA64.
3078         * i386-opc.h (AMD64): Removed.
3079         (Intel64): Likewose.
3080         (AMD64): New.
3081         (INTEL64): Likewise.
3082         (INTEL64ONLY): Likewise.
3083         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
3084         * i386-opc.tbl (Amd64): New.
3085         (Intel64): Likewise.
3086         (Intel64Only): Likewise.
3087         Replace AMD64 with Amd64.  Update sysenter/sysenter with
3088         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
3089         * i386-tbl.h: Regenerated.
3090
3091 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
3092
3093         PR 25469
3094         * z80-dis.c: Add support for GBZ80 opcodes.
3095
3096 2020-02-04  Alan Modra  <amodra@gmail.com>
3097
3098         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
3099
3100 2020-02-03  Alan Modra  <amodra@gmail.com>
3101
3102         * m32c-ibld.c: Regenerate.
3103
3104 2020-02-01  Alan Modra  <amodra@gmail.com>
3105
3106         * frv-ibld.c: Regenerate.
3107
3108 2020-01-31  Jan Beulich  <jbeulich@suse.com>
3109
3110         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
3111         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
3112         (OP_E_memory): Replace xmm_mdq_mode case label by
3113         vex_scalar_w_dq_mode one.
3114         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
3115
3116 2020-01-31  Jan Beulich  <jbeulich@suse.com>
3117
3118         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
3119         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
3120         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
3121         (intel_operand_size): Drop vex_w_dq_mode case label.
3122
3123 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
3124
3125         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
3126         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
3127
3128 2020-01-30  Alan Modra  <amodra@gmail.com>
3129
3130         * m32c-ibld.c: Regenerate.
3131
3132 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
3133
3134         * bpf-opc.c: Regenerate.
3135
3136 2020-01-30  Jan Beulich  <jbeulich@suse.com>
3137
3138         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
3139         (dis386): Use them to replace C2/C3 table entries.
3140         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
3141         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
3142         ones. Use Size64 instead of DefaultSize on Intel64 ones.
3143         * i386-tbl.h: Re-generate.
3144
3145 2020-01-30  Jan Beulich  <jbeulich@suse.com>
3146
3147         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
3148         forms.
3149         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
3150         DefaultSize.
3151         * i386-tbl.h: Re-generate.
3152
3153 2020-01-30  Alan Modra  <amodra@gmail.com>
3154
3155         * tic4x-dis.c (tic4x_dp): Make unsigned.
3156
3157 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
3158             Jan Beulich  <jbeulich@suse.com>
3159
3160         PR binutils/25445
3161         * i386-dis.c (MOVSXD_Fixup): New function.
3162         (movsxd_mode): New enum.
3163         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
3164         (intel_operand_size): Handle movsxd_mode.
3165         (OP_E_register): Likewise.
3166         (OP_G): Likewise.
3167         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
3168         register on movsxd.  Add movsxd with 16-bit destination register
3169         for AMD64 and Intel64 ISAs.
3170         * i386-tbl.h: Regenerated.
3171
3172 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
3173
3174         PR 25403
3175         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
3176         * aarch64-asm-2.c: Regenerate
3177         * aarch64-dis-2.c: Likewise.
3178         * aarch64-opc-2.c: Likewise.
3179
3180 2020-01-21  Jan Beulich  <jbeulich@suse.com>
3181
3182         * i386-opc.tbl (sysret): Drop DefaultSize.
3183         * i386-tbl.h: Re-generate.
3184
3185 2020-01-21  Jan Beulich  <jbeulich@suse.com>
3186
3187         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
3188         Dword.
3189         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
3190         * i386-tbl.h: Re-generate.
3191
3192 2020-01-20  Nick Clifton  <nickc@redhat.com>
3193
3194         * po/de.po: Updated German translation.
3195         * po/pt_BR.po: Updated Brazilian Portuguese translation.
3196         * po/uk.po: Updated Ukranian translation.
3197
3198 2020-01-20  Alan Modra  <amodra@gmail.com>
3199
3200         * hppa-dis.c (fput_const): Remove useless cast.
3201
3202 2020-01-20  Alan Modra  <amodra@gmail.com>
3203
3204         * arm-dis.c (print_insn_arm): Wrap 'T' value.
3205
3206 2020-01-18  Nick Clifton  <nickc@redhat.com>
3207
3208         * configure: Regenerate.
3209         * po/opcodes.pot: Regenerate.
3210
3211 2020-01-18  Nick Clifton  <nickc@redhat.com>
3212
3213         Binutils 2.34 branch created.
3214
3215 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
3216
3217         * opintl.h: Fix spelling error (seperate).
3218
3219 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
3220
3221         * i386-opc.tbl: Add {vex} pseudo prefix.
3222         * i386-tbl.h: Regenerated.
3223
3224 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
3225
3226         PR 25376
3227         * arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
3228         (neon_opcodes): Likewise.
3229         (select_arm_features): Make sure we enable MVE bits when selecting
3230         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
3231         any architecture.
3232
3233 2020-01-16  Jan Beulich  <jbeulich@suse.com>
3234
3235         * i386-opc.tbl: Drop stale comment from XOP section.
3236
3237 2020-01-16  Jan Beulich  <jbeulich@suse.com>
3238
3239         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
3240         (extractps): Add VexWIG to SSE2AVX forms.
3241         * i386-tbl.h: Re-generate.
3242
3243 2020-01-16  Jan Beulich  <jbeulich@suse.com>
3244
3245         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
3246         Size64 from and use VexW1 on SSE2AVX forms.
3247         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
3248         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
3249         * i386-tbl.h: Re-generate.
3250
3251 2020-01-15  Alan Modra  <amodra@gmail.com>
3252
3253         * tic4x-dis.c (tic4x_version): Make unsigned long.
3254         (optab, optab_special, registernames): New file scope vars.
3255         (tic4x_print_register): Set up registernames rather than
3256         malloc'd registertable.
3257         (tic4x_disassemble): Delete optable and optable_special.  Use
3258         optab and optab_special instead.  Throw away old optab,
3259         optab_special and registernames when info->mach changes.
3260
3261 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
3262
3263         PR 25377
3264         * z80-dis.c (suffix): Use .db instruction to generate double
3265         prefix.
3266
3267 2020-01-14  Alan Modra  <amodra@gmail.com>
3268
3269         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
3270         values to unsigned before shifting.
3271
3272 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
3273
3274         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
3275         flow instructions.
3276         (print_insn_thumb16, print_insn_thumb32): Likewise.
3277         (print_insn): Initialize the insn info.
3278         * i386-dis.c (print_insn): Initialize the insn info fields, and
3279         detect jumps.
3280
3281 2020-01-13  Claudiu Zissulescu <claziss@gmail.com>
3282
3283         * arc-opc.c (C_NE): Make it required.
3284
3285 2020-01-13  Claudiu Zissulescu <claziss@gmail.com>
3286
3287         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
3288         reserved register name.
3289
3290 2020-01-13  Alan Modra  <amodra@gmail.com>
3291
3292         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
3293         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
3294
3295 2020-01-13  Alan Modra  <amodra@gmail.com>
3296
3297         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
3298         result of wasm_read_leb128 in a uint64_t and check that bits
3299         are not lost when copying to other locals.  Use uint32_t for
3300         most locals.  Use PRId64 when printing int64_t.
3301
3302 2020-01-13  Alan Modra  <amodra@gmail.com>
3303
3304         * score-dis.c: Formatting.
3305         * score7-dis.c: Formatting.
3306
3307 2020-01-13  Alan Modra  <amodra@gmail.com>
3308
3309         * score-dis.c (print_insn_score48): Use unsigned variables for
3310         unsigned values.  Don't left shift negative values.
3311         (print_insn_score32): Likewise.
3312         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
3313
3314 2020-01-13  Alan Modra  <amodra@gmail.com>
3315
3316         * tic4x-dis.c (tic4x_print_register): Remove dead code.
3317
3318 2020-01-13  Alan Modra  <amodra@gmail.com>
3319
3320         * fr30-ibld.c: Regenerate.
3321
3322 2020-01-13  Alan Modra  <amodra@gmail.com>
3323
3324         * xgate-dis.c (print_insn): Don't left shift signed value.
3325         (ripBits): Formatting, use 1u.
3326
3327 2020-01-10  Alan Modra  <amodra@gmail.com>
3328
3329         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
3330         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
3331
3332 2020-01-10  Alan Modra  <amodra@gmail.com>
3333
3334         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
3335         and XRREG value earlier to avoid a shift with negative exponent.
3336         * m10200-dis.c (disassemble): Similarly.
3337
3338 2020-01-09  Nick Clifton  <nickc@redhat.com>
3339
3340         PR 25224
3341         * z80-dis.c (ld_ii_ii): Use correct cast.
3342
3343 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
3344
3345         PR 25224
3346         * z80-dis.c (ld_ii_ii): Use character constant when checking
3347         opcode byte value.
3348
3349 2020-01-09  Jan Beulich  <jbeulich@suse.com>
3350
3351         * i386-dis.c (SEP_Fixup): New.
3352         (SEP): Define.
3353         (dis386_twobyte): Use it for sysenter/sysexit.
3354         (enum x86_64_isa): Change amd64 enumerator to value 1.
3355         (OP_J): Compare isa64 against intel64 instead of amd64.
3356         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
3357         forms.
3358         * i386-tbl.h: Re-generate.
3359
3360 2020-01-08  Alan Modra  <amodra@gmail.com>
3361
3362         * z8k-dis.c: Include libiberty.h
3363         (instr_data_s): Make max_fetched unsigned.
3364         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
3365         Don't exceed byte_info bounds.
3366         (output_instr): Make num_bytes unsigned.
3367         (unpack_instr): Likewise for nibl_count and loop.
3368         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
3369         idx unsigned.
3370         * z8k-opc.h: Regenerate.
3371
3372 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
3373
3374         * arc-tbl.h (llock): Use 'LLOCK' as class.
3375         (llockd): Likewise.
3376         (scond): Use 'SCOND' as class.
3377         (scondd): Likewise.
3378         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
3379         (scondd): Likewise.
3380
3381 2020-01-06  Alan Modra  <amodra@gmail.com>
3382
3383         * m32c-ibld.c: Regenerate.
3384
3385 2020-01-06  Alan Modra  <amodra@gmail.com>
3386
3387         PR 25344
3388         * z80-dis.c (suffix): Don't use a local struct buffer copy.
3389         Peek at next byte to prevent recursion on repeated prefix bytes.
3390         Ensure uninitialised "mybuf" is not accessed.
3391         (print_insn_z80): Don't zero n_fetch and n_used here,..
3392         (print_insn_z80_buf): ..do it here instead.
3393
3394 2020-01-04  Alan Modra  <amodra@gmail.com>
3395
3396         * m32r-ibld.c: Regenerate.
3397
3398 2020-01-04  Alan Modra  <amodra@gmail.com>
3399
3400         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
3401
3402 2020-01-04  Alan Modra  <amodra@gmail.com>
3403
3404         * crx-dis.c (match_opcode): Avoid shift left of signed value.
3405
3406 2020-01-04  Alan Modra  <amodra@gmail.com>
3407
3408         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
3409
3410 2020-01-03  Jan Beulich  <jbeulich@suse.com>
3411
3412         * aarch64-tbl.h (aarch64_opcode_table): Use
3413         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
3414
3415 2020-01-03  Jan Beulich  <jbeulich@suse.com>
3416
3417         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
3418         forms of SUDOT and USDOT.
3419
3420 2020-01-03  Jan Beulich  <jbeulich@suse.com>
3421
3422         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
3423         uzip{1,2}.
3424         * aarch64-dis-2.c: Re-generate.
3425
3426 2020-01-03  Jan Beulich  <jbeulich@suse.com>
3427
3428         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
3429         FMMLA encoding.
3430         * aarch64-dis-2.c: Re-generate.
3431
3432 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
3433
3434         * z80-dis.c: Add support for eZ80 and Z80 instructions.
3435
3436 2020-01-01  Alan Modra  <amodra@gmail.com>
3437
3438         Update year range in copyright notice of all files.
3439
3440 For older changes see ChangeLog-2019
3441 \f
3442 Copyright (C) 2020 Free Software Foundation, Inc.
3443
3444 Copying and distribution of this file, with or without modification,
3445 are permitted in any medium without royalty provided the copyright
3446 notice and this notice are preserved.
3447
3448 Local Variables:
3449 mode: change-log
3450 left-margin: 8
3451 fill-column: 74
3452 version-control: never
3453 End: