1 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
3 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
4 (print_insn_neon): Support disassembly of conditional
7 2020-02-16 David Faust <david.faust@oracle.com>
9 * bpf-desc.c: Regenerate.
10 * bpf-desc.h: Likewise.
11 * bpf-opc.c: Regenerate.
12 * bpf-opc.h: Likewise.
14 2020-04-07 Lili Cui <lili.cui@intel.com>
16 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
17 (prefix_table): New instructions (see prefixes above).
19 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
20 CPU_ANY_TSXLDTRK_FLAGS.
21 (cpu_flags): Add CpuTSXLDTRK.
22 * i386-opc.h (enum): Add CpuTSXLDTRK.
23 (i386_cpu_flags): Add cputsxldtrk.
24 * i386-opc.tbl: Add XSUSPLDTRK insns.
25 * i386-init.h: Regenerate.
26 * i386-tbl.h: Likewise.
28 2020-04-02 Lili Cui <lili.cui@intel.com>
30 * i386-dis.c (prefix_table): New instructions serialize.
31 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
32 CPU_ANY_SERIALIZE_FLAGS.
33 (cpu_flags): Add CpuSERIALIZE.
34 * i386-opc.h (enum): Add CpuSERIALIZE.
35 (i386_cpu_flags): Add cpuserialize.
36 * i386-opc.tbl: Add SERIALIZE insns.
37 * i386-init.h: Regenerate.
38 * i386-tbl.h: Likewise.
40 2020-03-26 Alan Modra <amodra@gmail.com>
42 * disassemble.h (opcodes_assert): Declare.
43 (OPCODES_ASSERT): Define.
44 * disassemble.c: Don't include assert.h. Include opintl.h.
45 (opcodes_assert): New function.
46 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
47 (bfd_h8_disassemble): Reduce size of data array. Correctly
48 calculate maxlen. Omit insn decoding when insn length exceeds
49 maxlen. Exit from nibble loop when looking for E, before
50 accessing next data byte. Move processing of E outside loop.
51 Replace tests of maxlen in loop with assertions.
53 2020-03-26 Alan Modra <amodra@gmail.com>
55 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
57 2020-03-25 Alan Modra <amodra@gmail.com>
59 * z80-dis.c (suffix): Init mybuf.
61 2020-03-22 Alan Modra <amodra@gmail.com>
63 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
64 successflly read from section.
66 2020-03-22 Alan Modra <amodra@gmail.com>
68 * arc-dis.c (find_format): Use ISO C string concatenation rather
69 than line continuation within a string. Don't access needs_limm
70 before testing opcode != NULL.
72 2020-03-22 Alan Modra <amodra@gmail.com>
74 * ns32k-dis.c (print_insn_arg): Update comment.
75 (print_insn_ns32k): Reduce size of index_offset array, and
76 initialize, passing -1 to print_insn_arg for args that are not
77 an index. Don't exit arg loop early. Abort on bad arg number.
79 2020-03-22 Alan Modra <amodra@gmail.com>
81 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
82 * s12z-opc.c: Formatting.
83 (operands_f): Return an int.
84 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
85 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
86 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
87 (exg_sex_discrim): Likewise.
88 (create_immediate_operand, create_bitfield_operand),
89 (create_register_operand_with_size, create_register_all_operand),
90 (create_register_all16_operand, create_simple_memory_operand),
91 (create_memory_operand, create_memory_auto_operand): Don't
92 segfault on malloc failure.
93 (z_ext24_decode): Return an int status, negative on fail, zero
95 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
96 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
97 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
98 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
99 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
100 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
101 (loop_primitive_decode, shift_decode, psh_pul_decode),
102 (bit_field_decode): Similarly.
103 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
104 to return value, update callers.
105 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
106 Don't segfault on NULL operand.
107 (decode_operation): Return OP_INVALID on first fail.
108 (decode_s12z): Check all reads, returning -1 on fail.
110 2020-03-20 Alan Modra <amodra@gmail.com>
112 * metag-dis.c (print_insn_metag): Don't ignore status from
115 2020-03-20 Alan Modra <amodra@gmail.com>
117 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
118 Initialize parts of buffer not written when handling a possible
119 2-byte insn at end of section. Don't attempt decoding of such
120 an insn by the 4-byte machinery.
122 2020-03-20 Alan Modra <amodra@gmail.com>
124 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
125 partially filled buffer. Prevent lookup of 4-byte insns when
126 only VLE 2-byte insns are possible due to section size. Print
127 ".word" rather than ".long" for 2-byte leftovers.
129 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
132 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
134 2020-03-13 Jan Beulich <jbeulich@suse.com>
136 * i386-dis.c (X86_64_0D): Rename to ...
137 (X86_64_0E): ... this.
139 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
141 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
142 * Makefile.in: Regenerated.
144 2020-03-09 Jan Beulich <jbeulich@suse.com>
146 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
148 * i386-tbl.h: Re-generate.
150 2020-03-09 Jan Beulich <jbeulich@suse.com>
152 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
153 vprot*, vpsha*, and vpshl*.
154 * i386-tbl.h: Re-generate.
156 2020-03-09 Jan Beulich <jbeulich@suse.com>
158 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
159 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
160 * i386-tbl.h: Re-generate.
162 2020-03-09 Jan Beulich <jbeulich@suse.com>
164 * i386-gen.c (set_bitfield): Ignore zero-length field names.
165 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
166 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
167 * i386-tbl.h: Re-generate.
169 2020-03-09 Jan Beulich <jbeulich@suse.com>
171 * i386-gen.c (struct template_arg, struct template_instance,
172 struct template_param, struct template, templates,
173 parse_template, expand_templates): New.
174 (process_i386_opcodes): Various local variables moved to
175 expand_templates. Call parse_template and expand_templates.
176 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
177 * i386-tbl.h: Re-generate.
179 2020-03-06 Jan Beulich <jbeulich@suse.com>
181 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
182 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
183 register and memory source templates. Replace VexW= by VexW*
185 * i386-tbl.h: Re-generate.
187 2020-03-06 Jan Beulich <jbeulich@suse.com>
189 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
190 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
191 * i386-tbl.h: Re-generate.
193 2020-03-06 Jan Beulich <jbeulich@suse.com>
195 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
196 * i386-tbl.h: Re-generate.
198 2020-03-06 Jan Beulich <jbeulich@suse.com>
200 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
201 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
202 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
203 VexW0 on SSE2AVX variants.
204 (vmovq): Drop NoRex64 from XMM/XMM variants.
205 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
206 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
207 applicable use VexW0.
208 * i386-tbl.h: Re-generate.
210 2020-03-06 Jan Beulich <jbeulich@suse.com>
212 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
213 * i386-opc.h (Rex64): Delete.
214 (struct i386_opcode_modifier): Remove rex64 field.
215 * i386-opc.tbl (crc32): Drop Rex64.
216 Replace Rex64 with Size64 everywhere else.
217 * i386-tbl.h: Re-generate.
219 2020-03-06 Jan Beulich <jbeulich@suse.com>
221 * i386-dis.c (OP_E_memory): Exclude recording of used address
222 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
223 addressed memory operands for MPX insns.
225 2020-03-06 Jan Beulich <jbeulich@suse.com>
227 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
228 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
229 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
230 (ptwrite): Split into non-64-bit and 64-bit forms.
231 * i386-tbl.h: Re-generate.
233 2020-03-06 Jan Beulich <jbeulich@suse.com>
235 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
237 * i386-tbl.h: Re-generate.
239 2020-03-04 Jan Beulich <jbeulich@suse.com>
241 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
242 (prefix_table): Move vmmcall here. Add vmgexit.
243 (rm_table): Replace vmmcall entry by prefix_table[] escape.
244 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
245 (cpu_flags): Add CpuSEV_ES entry.
246 * i386-opc.h (CpuSEV_ES): New.
247 (union i386_cpu_flags): Add cpusev_es field.
248 * i386-opc.tbl (vmgexit): New.
249 * i386-init.h, i386-tbl.h: Re-generate.
251 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
253 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
255 * i386-opc.h (IGNORESIZE): New.
256 (DEFAULTSIZE): Likewise.
257 (IgnoreSize): Removed.
258 (DefaultSize): Likewise.
260 (i386_opcode_modifier): Replace ignoresize/defaultsize with
262 * i386-opc.tbl (IgnoreSize): New.
263 (DefaultSize): Likewise.
264 * i386-tbl.h: Regenerated.
266 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
269 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
272 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
275 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
276 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
277 * i386-tbl.h: Regenerated.
279 2020-02-26 Alan Modra <amodra@gmail.com>
281 * aarch64-asm.c: Indent labels correctly.
282 * aarch64-dis.c: Likewise.
283 * aarch64-gen.c: Likewise.
284 * aarch64-opc.c: Likewise.
285 * alpha-dis.c: Likewise.
286 * i386-dis.c: Likewise.
287 * nds32-asm.c: Likewise.
288 * nfp-dis.c: Likewise.
289 * visium-dis.c: Likewise.
291 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
293 * arc-regs.h (int_vector_base): Make it available for all ARC
296 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
298 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
301 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
303 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
304 c.mv/c.li if rs1 is zero.
306 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
308 * i386-gen.c (cpu_flag_init): Replace CpuABM with
309 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
311 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
312 * i386-opc.h (CpuABM): Removed.
314 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
315 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
316 popcnt. Remove CpuABM from lzcnt.
317 * i386-init.h: Regenerated.
318 * i386-tbl.h: Likewise.
320 2020-02-17 Jan Beulich <jbeulich@suse.com>
322 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
323 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
324 VexW1 instead of open-coding them.
325 * i386-tbl.h: Re-generate.
327 2020-02-17 Jan Beulich <jbeulich@suse.com>
329 * i386-opc.tbl (AddrPrefixOpReg): Define.
330 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
331 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
332 templates. Drop NoRex64.
333 * i386-tbl.h: Re-generate.
335 2020-02-17 Jan Beulich <jbeulich@suse.com>
338 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
339 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
340 into Intel syntax instance (with Unpsecified) and AT&T one
342 (vcvtneps2bf16): Likewise, along with folding the two so far
344 * i386-tbl.h: Re-generate.
346 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
348 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
351 2020-02-17 Alan Modra <amodra@gmail.com>
353 * i386-gen.c (cpu_flag_init): Correct last change.
355 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
357 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
360 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
362 * i386-opc.tbl (movsx): Remove Intel syntax comments.
365 2020-02-14 Jan Beulich <jbeulich@suse.com>
368 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
369 destination for Cpu64-only variant.
370 (movzx): Fold patterns.
371 * i386-tbl.h: Re-generate.
373 2020-02-13 Jan Beulich <jbeulich@suse.com>
375 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
376 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
377 CPU_ANY_SSE4_FLAGS entry.
378 * i386-init.h: Re-generate.
380 2020-02-12 Jan Beulich <jbeulich@suse.com>
382 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
383 with Unspecified, making the present one AT&T syntax only.
384 * i386-tbl.h: Re-generate.
386 2020-02-12 Jan Beulich <jbeulich@suse.com>
388 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
389 * i386-tbl.h: Re-generate.
391 2020-02-12 Jan Beulich <jbeulich@suse.com>
394 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
395 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
396 Amd64 and Intel64 templates.
397 (call, jmp): Likewise for far indirect variants. Dro
399 * i386-tbl.h: Re-generate.
401 2020-02-11 Jan Beulich <jbeulich@suse.com>
403 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
404 * i386-opc.h (ShortForm): Delete.
405 (struct i386_opcode_modifier): Remove shortform field.
406 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
407 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
408 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
409 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
411 * i386-tbl.h: Re-generate.
413 2020-02-11 Jan Beulich <jbeulich@suse.com>
415 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
416 fucompi): Drop ShortForm from operand-less templates.
417 * i386-tbl.h: Re-generate.
419 2020-02-11 Alan Modra <amodra@gmail.com>
421 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
422 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
423 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
424 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
425 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
427 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
429 * arm-dis.c (print_insn_cde): Define 'V' parse character.
430 (cde_opcodes): Add VCX* instructions.
432 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
433 Matthew Malcomson <matthew.malcomson@arm.com>
435 * arm-dis.c (struct cdeopcode32): New.
436 (CDE_OPCODE): New macro.
437 (cde_opcodes): New disassembly table.
438 (regnames): New option to table.
439 (cde_coprocs): New global variable.
440 (print_insn_cde): New
441 (print_insn_thumb32): Use print_insn_cde.
442 (parse_arm_disassembler_options): Parse coprocN args.
444 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
447 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
449 * i386-opc.h (AMD64): Removed.
453 (INTEL64ONLY): Likewise.
454 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
455 * i386-opc.tbl (Amd64): New.
457 (Intel64Only): Likewise.
458 Replace AMD64 with Amd64. Update sysenter/sysenter with
459 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
460 * i386-tbl.h: Regenerated.
462 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
465 * z80-dis.c: Add support for GBZ80 opcodes.
467 2020-02-04 Alan Modra <amodra@gmail.com>
469 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
471 2020-02-03 Alan Modra <amodra@gmail.com>
473 * m32c-ibld.c: Regenerate.
475 2020-02-01 Alan Modra <amodra@gmail.com>
477 * frv-ibld.c: Regenerate.
479 2020-01-31 Jan Beulich <jbeulich@suse.com>
481 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
482 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
483 (OP_E_memory): Replace xmm_mdq_mode case label by
484 vex_scalar_w_dq_mode one.
485 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
487 2020-01-31 Jan Beulich <jbeulich@suse.com>
489 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
490 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
491 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
492 (intel_operand_size): Drop vex_w_dq_mode case label.
494 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
496 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
497 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
499 2020-01-30 Alan Modra <amodra@gmail.com>
501 * m32c-ibld.c: Regenerate.
503 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
505 * bpf-opc.c: Regenerate.
507 2020-01-30 Jan Beulich <jbeulich@suse.com>
509 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
510 (dis386): Use them to replace C2/C3 table entries.
511 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
512 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
513 ones. Use Size64 instead of DefaultSize on Intel64 ones.
514 * i386-tbl.h: Re-generate.
516 2020-01-30 Jan Beulich <jbeulich@suse.com>
518 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
520 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
522 * i386-tbl.h: Re-generate.
524 2020-01-30 Alan Modra <amodra@gmail.com>
526 * tic4x-dis.c (tic4x_dp): Make unsigned.
528 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
529 Jan Beulich <jbeulich@suse.com>
532 * i386-dis.c (MOVSXD_Fixup): New function.
533 (movsxd_mode): New enum.
534 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
535 (intel_operand_size): Handle movsxd_mode.
536 (OP_E_register): Likewise.
538 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
539 register on movsxd. Add movsxd with 16-bit destination register
540 for AMD64 and Intel64 ISAs.
541 * i386-tbl.h: Regenerated.
543 2020-01-27 Tamar Christina <tamar.christina@arm.com>
546 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
547 * aarch64-asm-2.c: Regenerate
548 * aarch64-dis-2.c: Likewise.
549 * aarch64-opc-2.c: Likewise.
551 2020-01-21 Jan Beulich <jbeulich@suse.com>
553 * i386-opc.tbl (sysret): Drop DefaultSize.
554 * i386-tbl.h: Re-generate.
556 2020-01-21 Jan Beulich <jbeulich@suse.com>
558 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
560 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
561 * i386-tbl.h: Re-generate.
563 2020-01-20 Nick Clifton <nickc@redhat.com>
565 * po/de.po: Updated German translation.
566 * po/pt_BR.po: Updated Brazilian Portuguese translation.
567 * po/uk.po: Updated Ukranian translation.
569 2020-01-20 Alan Modra <amodra@gmail.com>
571 * hppa-dis.c (fput_const): Remove useless cast.
573 2020-01-20 Alan Modra <amodra@gmail.com>
575 * arm-dis.c (print_insn_arm): Wrap 'T' value.
577 2020-01-18 Nick Clifton <nickc@redhat.com>
579 * configure: Regenerate.
580 * po/opcodes.pot: Regenerate.
582 2020-01-18 Nick Clifton <nickc@redhat.com>
584 Binutils 2.34 branch created.
586 2020-01-17 Christian Biesinger <cbiesinger@google.com>
588 * opintl.h: Fix spelling error (seperate).
590 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
592 * i386-opc.tbl: Add {vex} pseudo prefix.
593 * i386-tbl.h: Regenerated.
595 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
598 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
599 (neon_opcodes): Likewise.
600 (select_arm_features): Make sure we enable MVE bits when selecting
601 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
604 2020-01-16 Jan Beulich <jbeulich@suse.com>
606 * i386-opc.tbl: Drop stale comment from XOP section.
608 2020-01-16 Jan Beulich <jbeulich@suse.com>
610 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
611 (extractps): Add VexWIG to SSE2AVX forms.
612 * i386-tbl.h: Re-generate.
614 2020-01-16 Jan Beulich <jbeulich@suse.com>
616 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
617 Size64 from and use VexW1 on SSE2AVX forms.
618 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
619 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
620 * i386-tbl.h: Re-generate.
622 2020-01-15 Alan Modra <amodra@gmail.com>
624 * tic4x-dis.c (tic4x_version): Make unsigned long.
625 (optab, optab_special, registernames): New file scope vars.
626 (tic4x_print_register): Set up registernames rather than
627 malloc'd registertable.
628 (tic4x_disassemble): Delete optable and optable_special. Use
629 optab and optab_special instead. Throw away old optab,
630 optab_special and registernames when info->mach changes.
632 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
635 * z80-dis.c (suffix): Use .db instruction to generate double
638 2020-01-14 Alan Modra <amodra@gmail.com>
640 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
641 values to unsigned before shifting.
643 2020-01-13 Thomas Troeger <tstroege@gmx.de>
645 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
647 (print_insn_thumb16, print_insn_thumb32): Likewise.
648 (print_insn): Initialize the insn info.
649 * i386-dis.c (print_insn): Initialize the insn info fields, and
652 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
654 * arc-opc.c (C_NE): Make it required.
656 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
658 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
659 reserved register name.
661 2020-01-13 Alan Modra <amodra@gmail.com>
663 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
664 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
666 2020-01-13 Alan Modra <amodra@gmail.com>
668 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
669 result of wasm_read_leb128 in a uint64_t and check that bits
670 are not lost when copying to other locals. Use uint32_t for
671 most locals. Use PRId64 when printing int64_t.
673 2020-01-13 Alan Modra <amodra@gmail.com>
675 * score-dis.c: Formatting.
676 * score7-dis.c: Formatting.
678 2020-01-13 Alan Modra <amodra@gmail.com>
680 * score-dis.c (print_insn_score48): Use unsigned variables for
681 unsigned values. Don't left shift negative values.
682 (print_insn_score32): Likewise.
683 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
685 2020-01-13 Alan Modra <amodra@gmail.com>
687 * tic4x-dis.c (tic4x_print_register): Remove dead code.
689 2020-01-13 Alan Modra <amodra@gmail.com>
691 * fr30-ibld.c: Regenerate.
693 2020-01-13 Alan Modra <amodra@gmail.com>
695 * xgate-dis.c (print_insn): Don't left shift signed value.
696 (ripBits): Formatting, use 1u.
698 2020-01-10 Alan Modra <amodra@gmail.com>
700 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
701 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
703 2020-01-10 Alan Modra <amodra@gmail.com>
705 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
706 and XRREG value earlier to avoid a shift with negative exponent.
707 * m10200-dis.c (disassemble): Similarly.
709 2020-01-09 Nick Clifton <nickc@redhat.com>
712 * z80-dis.c (ld_ii_ii): Use correct cast.
714 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
717 * z80-dis.c (ld_ii_ii): Use character constant when checking
720 2020-01-09 Jan Beulich <jbeulich@suse.com>
722 * i386-dis.c (SEP_Fixup): New.
724 (dis386_twobyte): Use it for sysenter/sysexit.
725 (enum x86_64_isa): Change amd64 enumerator to value 1.
726 (OP_J): Compare isa64 against intel64 instead of amd64.
727 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
729 * i386-tbl.h: Re-generate.
731 2020-01-08 Alan Modra <amodra@gmail.com>
733 * z8k-dis.c: Include libiberty.h
734 (instr_data_s): Make max_fetched unsigned.
735 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
736 Don't exceed byte_info bounds.
737 (output_instr): Make num_bytes unsigned.
738 (unpack_instr): Likewise for nibl_count and loop.
739 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
741 * z8k-opc.h: Regenerate.
743 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
745 * arc-tbl.h (llock): Use 'LLOCK' as class.
747 (scond): Use 'SCOND' as class.
749 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
752 2020-01-06 Alan Modra <amodra@gmail.com>
754 * m32c-ibld.c: Regenerate.
756 2020-01-06 Alan Modra <amodra@gmail.com>
759 * z80-dis.c (suffix): Don't use a local struct buffer copy.
760 Peek at next byte to prevent recursion on repeated prefix bytes.
761 Ensure uninitialised "mybuf" is not accessed.
762 (print_insn_z80): Don't zero n_fetch and n_used here,..
763 (print_insn_z80_buf): ..do it here instead.
765 2020-01-04 Alan Modra <amodra@gmail.com>
767 * m32r-ibld.c: Regenerate.
769 2020-01-04 Alan Modra <amodra@gmail.com>
771 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
773 2020-01-04 Alan Modra <amodra@gmail.com>
775 * crx-dis.c (match_opcode): Avoid shift left of signed value.
777 2020-01-04 Alan Modra <amodra@gmail.com>
779 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
781 2020-01-03 Jan Beulich <jbeulich@suse.com>
783 * aarch64-tbl.h (aarch64_opcode_table): Use
784 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
786 2020-01-03 Jan Beulich <jbeulich@suse.com>
788 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
789 forms of SUDOT and USDOT.
791 2020-01-03 Jan Beulich <jbeulich@suse.com>
793 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
795 * opcodes/aarch64-dis-2.c: Re-generate.
797 2020-01-03 Jan Beulich <jbeulich@suse.com>
799 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
801 * opcodes/aarch64-dis-2.c: Re-generate.
803 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
805 * z80-dis.c: Add support for eZ80 and Z80 instructions.
807 2020-01-01 Alan Modra <amodra@gmail.com>
809 Update year range in copyright notice of all files.
811 For older changes see ChangeLog-2019
813 Copyright (C) 2020 Free Software Foundation, Inc.
815 Copying and distribution of this file, with or without modification,
816 are permitted in any medium without royalty provided the copyright
817 notice and this notice are preserved.
823 version-control: never