opcodes/ChangeLog

   1 2023-11-15  Arsen Arsenović  <arsen@aarsen.me>
   2
   3         * aclocal.m4: Regenerate.
   4         * po/Make-in ($(srcdir)/$(PACKAGE).pot): Output to a .pot
   5         temporary file to suppress xgettext checking charset names.
   6         * configure.ac (SHARED_LIBADD): Use LTLIBINTL rather than
   7         LIBINTL.
   8         * configure: Regenerate.
   9         * po/Make-in ($(srcdir)/$(PACKAGE).pot): Output to a .pot
  10         temporary file, to suppress xgettext checking charset names.
  11
  12 2023-10-05  Neal frager  <neal.frager@amd.com>
  13
  14         * microblaze-opcm.h (struct op_code_struct): Tidy and remove
  15         redundant entries.
  16         * microblaze-opc.h (MAX_OPCODES): Increase to 300.
  17         (op_code_struct): Add address extension instructions.
  18
  19 2023-10-04  Neal frager  <neal.frager@amd.com>
  20
  21         * microblaze-opc.h (struct op_code_struct): Add hiberante
  22         and suspend entries.
  23         * microblaze-opcm.h (enum microblaze_instr): Add microblaze_sleep,
  24         hibernate, suspend entries.
  25
  26 2023-08-24  Tom Tromey  <tom@tromey.com>
  27
  28         * cgen.sh: Don't pass "-s" to cgen.
  29         * Makefile.in: Rebuild.
  30         * Makefile.am (GUILE): Simplify.
  31
  32 2023-07-31  Jose E. Marchesi  <jose.marchesi@oracle.com>
  33
  34         PR 30705
  35         * bpf-dis.c (print_insn_bpf): Check that info->section->owner is
  36         actually available before using it.
  37
  38 2023-07-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
  39
  40         * bpf-dis.c: Initialize asm_bpf_version to -1.
  41         (print_insn_bpf): Set BPF ISA version from the cpu version ELF
  42         header flags if no explicit version set in the command line.
  43         * disassemble.c (disassemble_init_for_target): Remove unused code.
  44
  45 2023-07-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
  46
  47         * bpf-opc.c (bpf_opcodes): Fix BPF_INSN_NEGR to not use a src
  48         register.
  49
  50 2023-07-24  Jose E. Marchesi  <jose.marchesi@oracle.com>
  51
  52         * bpf-opc.c (bpf_opcodes): Add entries for the BSWAP*
  53         instructions.
  54
  55 2023-07-24  Jose E. Marchesi  <jose.marchesi@oracle.com>
  56
  57         * bpf-opc.c (bpf_opcodes): Fix pseudo-c syntax for MOVS* and LDXS*
  58         instructions.
  59
  60 2023-07-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
  61
  62         * bpf-opc.c (bpf_opcodes): Add entry for jal.
  63
  64 2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
  65
  66         * bpf-opc.c (bpf_opcodes): Add entries for LDXS{B,W,H,DW}
  67         instructions.
  68
  69 2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
  70
  71         * bpf-opc.c (bpf_opcodes): Add entries for MOVS{8,16,32}R and
  72         MOVS32{8,16,32}R instructions.  and MOVS32I instructions.
  73
  74 2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
  75
  76         * Makefile.am (TARGET64_LIBOPCODES_CFILES): Add missing bpf-dis.c
  77         * Makefile.in: Regenerate.
  78
  79 2023-07-03  Nick Clifton  <nickc@redhat.com>
  80
  81         * configure: Regenerate.
  82         * po/opcodes.pot: Regenerate.
  83
  84 2023-07-03  Nick Clifton  <nickc@redhat.com>
  85
  86         2.41 Branch Point.
  87
  88 2023-05-23  Nick Clifton  <nickc@redhat.com>
  89
  90         * po/sv.po: Updated translation.
  91
  92 2023-04-21  Tom Tromey  <tromey@adacore.com>
  93
  94         * i386-dis.c (OP_J): Check result of get16.
  95
  96 2023-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
  97
  98         * arc-tbl.h: Remove vadds2, vadds2h, vadds4h, vaddsubs,
  99         vaddsubs2h, vaddsubs4h, vsubadds, vsubadds2h, vsubadds4h, vsubs2,
 100         vsubs2h, and vsubs4h instructions.
 101
 102 2023-04-11  Nick Clifton  <nickc@redhat.com>
 103
 104         PR 30310
 105         * nfp-dis.c (init_nfp6000_priv): Check that the output section
 106         exists.
 107
 108 2023-03-15  Nick Clifton  <nickc@redhat.com>
 109
 110         PR 30231
 111         * mep-dis.c: Regenerate.
 112
 113 2023-03-15  Nick Clifton  <nickc@redhat.com>
 114
 115         PR 30230
 116         * arm-dis.c (get_sym_code_type): Check for non-ELF symbols.
 117
 118 2023-02-28  Richard Ball  <richard.ball@arm.com>
 119
 120         * aarch64-opc.c: Add MEC system registers.
 121
 122 2023-01-03  Nick Clifton  <nickc@redhat.com>
 123
 124         * po/de.po: Updated German translation.
 125         * po/ro.po: Updated Romainian translation.
 126         * po/uk.po: Updated Ukrainian translation.
 127
 128 2022-12-31  Nick Clifton  <nickc@redhat.com>
 129
 130         * 2.40 branch created.
 131
 132 2022-11-22  Shahab Vahedi  <shahab@synopsys.com>
 133
 134         * arc-regs.h: Change isa_config address to 0xc1.
 135         isa_config exists for ARC700 and ARCV2 and not ARCALL.
 136
 137 2022-10-31  Yoshinori Sato  <ysato@users.sourceforge.jp>
 138
 139         * rx-decode.opc: Switch arguments of the MVTACGU insn.
 140         * rx-decode.c: Regenerate.
 141
 142 2022-09-22  Yoshinori Sato  <ysato@users.sourceforge.jp>
 143
 144         * sh-dis.c (print_insn_sh): Enforce bit7 of LDC Rm,Rn_BANK and STC
 145         Rm_BANK,Rn is always 1.
 146
 147 2022-07-21  Peter Bergner  <bergner@linux.ibm.com>
 148
 149         * ppc-opc.c (XACC_MASK, XX3ACC_MASK): New defines.
 150         (P_GER_MASK, xxmfacc, xxmtacc, xxsetaccz, xvi8ger4pp, xvi8ger4,
 151         xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger, xvi4ger8pp, xvi4ger8,
 152         xvi16ger2spp, xvi16ger2s, xvbf16ger2pp, xvbf16ger2, xvf64gerpp,
 153         xvf64ger, xvi16ger2, xvf16ger2np, xvf32gernp, xvi8ger4spp, xvi16ger2pp,
 154         xvbf16ger2np, xvf64gernp, xvf16ger2pn, xvf32gerpn, xvbf16ger2pn,
 155         xvf64gerpn, xvf16ger2nn, xvf32gernn, xvbf16ger2nn, xvf64gernn: Use them.
 156
 157 2022-07-18  Claudiu Zissulescu  <claziss@synopsys.com>
 158
 159         * disassemble.c (disassemble_init_for_target): Set
 160         created_styled_output for ARC based targets.
 161         * arc-dis.c (find_format_from_table): Use fprintf_styled_ftype
 162         instead of fprintf_ftype throughout.
 163         (find_format): Likewise.
 164         (print_flags): Likewise.
 165         (print_insn_arc): Likewise.
 166
 167 2022-07-08  Nick Clifton  <nickc@redhat.com>
 168
 169         * 2.39 branch created.
 170
 171 2022-07-04  Marcus Nilsson  <brainbomb@gmail.com>
 172
 173         * disassemble.c: (disassemble_init_for_target): Set
 174         created_styled_output for AVR based targets.
 175         * avr-dis.c: (print_insn_avr): Use fprintf_styled_ftype
 176         instead of fprintf_ftype throughout.
 177         (avr_operand): Pass in and fill disassembler_style when
 178         parsing operands.
 179
 180 2022-04-07  Andreas Krebbel  <krebbel@linux.ibm.com>
 181
 182         * s390-mkopc.c (main): Enable z16 as CPU string in the opcode
 183         table.
 184
 185 2022-03-16  Simon Marchi  <simon.marchi@efficios.com>
 186
 187         * configure.ac: Handle bfd_amdgcn_arch.
 188         * configure: Re-generate.
 189
 190 2022-03-06  Sagar Patel  <sagarmp@cs.unc.edu>
 191             Maciej W. Rozycki  <macro@orcam.me.uk>
 192
 193         * mips-opc.c (mips_builtin_opcodes): Fix INSN2_ALIAS annotation
 194         for "bal", "beqz", "beqzl", "bnez" and "bnezl" instructions.
 195         * micromips-opc.c (micromips_opcodes): Likewise for "beqz" and
 196         "bnez" instructions.
 197
 198 2022-02-17  Nick Clifton  <nickc@redhat.com>
 199
 200         * po/sr.po: Updated Serbian translation.
 201
 202 2022-02-14  Sergei Trofimovich  <siarheit@google.com>
 203
 204         * microblaze-opcm.h: Renamed 'fsqrt' to 'microblaze_fsqrt'.
 205         * microblaze-opc.h: Follow 'fsqrt' rename.
 206
 207 2022-01-24  Nick Clifton  <nickc@redhat.com>
 208
 209         * po/ro.po: Updated Romanian translation.
 210         * po/uk.po: Updated Ukranian translation.
 211
 212 2022-01-22  Nick Clifton  <nickc@redhat.com>
 213
 214         * configure: Regenerate.
 215         * po/opcodes.pot: Regenerate.
 216
 217 2022-01-22  Nick Clifton  <nickc@redhat.com>
 218
 219         * 2.38 release branch created.
 220
 221 2022-01-17  Nick Clifton  <nickc@redhat.com>
 222
 223         * Makefile.in: Regenerate.
 224         * po/opcodes.pot: Regenerate.
 225
 226 2021-12-02  Marcus Nilsson  <brainbomb@gmail.com>
 227
 228         * avr-dis.c (avr_operand); Pass in disassemble_info and fill
 229         in insn_type on branching instructions.
 230
 231 2021-11-25  Andrew Burgess  <aburgess@redhat.com>
 232             Simon Cook  <simon.cook@embecosm.com>
 233
 234         * riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
 235         (riscv_options): New static global.
 236         (disassembler_options_riscv): New function.
 237         (print_riscv_disassembler_options): Rewrite to use
 238         disassembler_options_riscv.
 239
 240 2021-11-25  Nick Clifton  <nickc@redhat.com>
 241
 242         PR 28614
 243         * aarch64-asm.c: Replace assert(0) with real code.
 244         * aarch64-dis.c: Likewise.
 245         * aarch64-opc.c: Likewise.
 246
 247 2021-11-25  Nick Clifton  <nickc@redhat.com>
 248
 249         * po/fr.po; Updated French translation.
 250
 251 2021-10-27  Maciej W. Rozycki  <macro@embecosm.com>
 252
 253         * Makefile.am: Remove obsolete comment.
 254         * configure.ac: Refer `libbfd.la' to link shared BFD library
 255         except for Cygwin.
 256         * Makefile.in: Regenerate.
 257         * configure: Regenerate.
 258
 259 2021-09-27  Nick Alcock  <nick.alcock@oracle.com>
 260
 261         * configure: Regenerate.
 262
 263 2021-09-25  Peter Bergner  <bergner@linux.ibm.com>
 264
 265         * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
 266         on POWER5 and later.
 267
 268 2021-09-20  Andrew Burgess  <andrew.burgess@embecosm.com>
 269
 270         * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
 271         before an unknown instruction, '%d' is replaced with the
 272         instruction length.
 273
 274 2021-09-02  Nick Clifton  <nickc@redhat.com>
 275
 276         PR 28292
 277         * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
 278         of BFD_RELOC_16.
 279
 280 2021-08-17  Shahab Vahedi <shahab@synopsys.com>
 281
 282         * arc-regs.h (DEF): Fix the register numbers.
 283
 284 2021-08-10  Nick Clifton  <nickc@redhat.com>
 285
 286         * po/sr.po: Updated Serbian translation.
 287
 288 2021-07-26  Chenghua Xu  <xuchenghua@loongson.cn>
 289
 290         * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
 291
 292 2021-06-07  Andreas Krebbel  <krebbel@linux.ibm.com>
 293
 294         * s390-opc.txt: Add qpaci.
 295
 296 2021-07-03  Nick Clifton  <nickc@redhat.com>
 297
 298         * configure: Regenerate.
 299         * po/opcodes.pot: Regenerate.
 300
 301 2021-07-03  Nick Clifton  <nickc@redhat.com>
 302
 303         * 2.37 release branch created.
 304
 305 2021-07-02  Alan Modra  <amodra@gmail.com>
 306
 307         * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
 308         (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
 309         (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
 310         (nds32_opcodes, nds32_operand_fields, nds32_keywords),
 311         (nds32_keyword_gpr): Move declarations to..
 312         * nds32-asm.h: ..here, constifying to match definitions.
 313
 314 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 315
 316         * Makefile.am (GUILE): New variable.
 317         (CGEN): Use $(GUILE).
 318         * Makefile.in: Regenerate.
 319
 320 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 321
 322         * mep-asm.c (macros): Mark static & const.
 323         (lookup_macro): Change return & m to const.
 324         (expand_macro): Change mac to const.
 325         (expand_string): Change pmacro to const.
 326
 327 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 328
 329         * nds32-asm.c (operand_fields): Rename to ...
 330         (nds32_operand_fields): ... this.
 331         (keyword_gpr): Rename to ...
 332         (nds32_keyword_gpr): ... this.
 333         (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
 334         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
 335         keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
 336         keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
 337         keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
 338         Mark static.
 339         (keywords): Rename to ...
 340         (nds32_keywords): ... this.
 341         * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
 342         keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
 343
 344 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 345
 346         * z80-dis.c (opc_ed): Make const.
 347         (pref_ed): Make p const.
 348
 349 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 350
 351         * microblaze-dis.c (get_field_special): Make op const.
 352         (read_insn_microblaze): Make opr & op const.  Rename opcodes to
 353         microblaze_opcodes.
 354         (print_insn_microblaze): Make op & pop const.
 355         (get_insn_microblaze): Make op const.  Rename opcodes to
 356         microblaze_opcodes.
 357         (microblaze_get_target_address): Likewise.
 358         * microblaze-opc.h (struct op_code_struct): Make const.
 359         Rename opcodes to microblaze_opcodes.
 360
 361 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 362
 363         * aarch64-gen.c (aarch64_opcode_table): Add const.
 364         * aarch64-tbl.h (aarch64_opcode_table): Likewise.
 365
 366 2021-06-22  Andrew Burgess  <andrew.burgess@embecosm.com>
 367
 368         * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
 369         available.
 370
 371 2021-06-22  Alan Modra  <amodra@gmail.com>
 372
 373         * pj-dis.c (print_insn_pj): Don't print trailing tab.  Do
 374         print separator for pcrel insns.
 375
 376 2021-06-19  Alan Modra  <amodra@gmail.com>
 377
 378         * vax-dis.c (print_insn_vax): Avoid pointer overflow.
 379
 380 2021-06-19  Alan Modra  <amodra@gmail.com>
 381
 382         * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
 383         entire buffer.
 384
 385 2021-06-17  Alan Modra  <amodra@gmail.com>
 386
 387         * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
 388         in table.
 389
 390 2021-06-03  Alan Modra  <amodra@gmail.com>
 391
 392         PR 1202
 393         * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
 394         Use unsigned int for inst.
 395
 396 2021-06-02  Shahab Vahedi  <shahab@synopsys.com>
 397
 398         * arc-dis.c (arc_option_arg_t): New enumeration.
 399         (arc_options): New variable.
 400         (disassembler_options_arc): New function.
 401         (print_arc_disassembler_options): Reimplement in terms of
 402         "disassembler_options_arc".
 403
 404 2021-05-29  Alan Modra  <amodra@gmail.com>
 405
 406         * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
 407         Don't special case PPC_OPCODE_RAW.
 408         (lookup_prefix): Likewise.
 409         (lookup_vle, lookup_spe2): Similarly.  Add dialect parameter and..
 410         (print_insn_powerpc): ..update caller.
 411         * ppc-opc.c (EXT): Define.
 412         (powerpc_opcodes): Mark extended mnemonics with EXT.
 413         (prefix_opcodes, vle_opcodes): Likewise.
 414         (XISEL, XISEL_MASK): Add cr field and simplify.
 415         (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
 416         all isel variants to where the base mnemonic belongs.  Sort dstt,
 417         dststt and dssall.
 418
 419 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 420
 421         * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
 422         COP3 opcode instructions.
 423
 424 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 425
 426         * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
 427         "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
 428         "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
 429         "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
 430         "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
 431         "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
 432         "cop2", and "cop3" entries.
 433
 434 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 435
 436         * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
 437         entries and associated comments.
 438
 439 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 440
 441         * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
 442         of "c0".
 443
 444 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 445
 446         * mips-dis.c (mips_cp1_names_mips): New variable.
 447         (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
 448         for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
 449         "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
 450         "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
 451         "r12000", "r14000", "r16000", "mips5", "loongson2e", and
 452         "loongson2f".
 453
 454 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 455
 456         * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
 457         handling code over to...
 458         <OP_REG_CONTROL>: ... this new case.
 459         * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
 460         (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
 461         "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
 462         replacing the `G' operand code with `g'.  Update "cftc1" and
 463         "cftc2" entries replacing the `E' operand code with `y'.
 464         * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
 465         (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
 466         entries replacing the `G' operand code with `g'.
 467
 468 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 469
 470         * mips-dis.c (mips_cp0_names_r3900): New variable.
 471         (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
 472         for "r3900".
 473
 474 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 475
 476         * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
 477         and "mtthc2" to using the `G' rather than `g' operand code for
 478         the coprocessor control register referred.
 479
 480 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 481
 482         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
 483         entries with each other.
 484
 485 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
 486
 487         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
 488
 489 2021-05-25  Alan Modra  <amodra@gmail.com>
 490
 491         * cris-desc.c: Regenerate.
 492         * cris-desc.h: Regenerate.
 493         * cris-opc.h: Regenerate.
 494         * po/POTFILES.in: Regenerate.
 495
 496 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
 497
 498         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
 499         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
 500         (CGEN_CPUS): Add cris.
 501         (CRIS_DEPS): Define.
 502         (stamp-cris): New rule.
 503         * cgen.sh: Handle desc action.
 504         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
 505         * Makefile.in, configure: Regenerate.
 506
 507 2021-05-18  Job Noorman  <mtvec@pm.me>
 508
 509         PR 27814
 510         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
 511         the elf objects.
 512
 513 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
 514
 515         * arm-dis.c (mve_opcodes): Fix disassembly of
 516         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
 517         (is_mve_encoding_conflict): MVE vector loads should not match
 518         when P = W = 0.
 519         (is_mve_unpredictable): It's not unpredictable to use the same
 520         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
 521
 522 2021-05-11  Nick Clifton  <nickc@redhat.com>
 523
 524         PR 27840
 525         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
 526         the end of the code buffer.
 527
 528 2021-05-06  Stafford Horne  <shorne@gmail.com>
 529
 530         PR 21464
 531         * or1k-asm.c: Regenerate.
 532
 533 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
 534
 535         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
 536         info->insn_info_valid.
 537
 538 2021-04-26  Jan Beulich  <jbeulich@suse.com>
 539
 540         * i386-opc.tbl (lea): Add Optimize.
 541         * opcodes/i386-tbl.h: Re-generate.
 542
 543 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 544
 545         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
 546         of l32r fetch and display referenced literal value.
 547
 548 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 549
 550         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
 551         to 4 for literal disassembly.
 552
 553 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 554
 555         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
 556         for TLBI instruction.
 557
 558 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 559
 560         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
 561         DC instruction.
 562
 563 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 564
 565         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
 566         "qualifier".
 567         (convert_mov_to_movewide): Add initializer for "value".
 568
 569 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 570
 571         * aarch64-opc.c: Add RME system registers.
 572
 573 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 574
 575         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
 576         "addi d,CV,z" to "c.mv d,CV".
 577
 578 2021-04-12  Alan Modra  <amodra@gmail.com>
 579
 580         * configure.ac (--enable-checking): Add support.
 581         * config.in: Regenerate.
 582         * configure: Regenerate.
 583
 584 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 585
 586         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 587         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 588
 589 2021-04-09  Alan Modra  <amodra@gmail.com>
 590
 591         * ppc-dis.c (struct dis_private): Add "special".
 592         (POWERPC_DIALECT): Delete.  Replace uses with..
 593         (private_data): ..this.  New inline function.
 594         (disassemble_init_powerpc): Init "special" names.
 595         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 596         field of prefix instructions.
 597         (bsearch_reloc, print_got_plt): New functions.
 598         (print_insn_powerpc): For pcrel instructions, print target address
 599         and symbol if known, and decode plt and got loads too.
 600
 601 2021-04-08  Alan Modra  <amodra@gmail.com>
 602
 603         PR 27684
 604         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 605
 606 2021-04-08  Alan Modra  <amodra@gmail.com>
 607
 608         PR 27676
 609         * ppc-opc.c (DCBT_EO): Move earlier.
 610         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 611         (powerpc_operands): Add THCT and THDS entries.
 612         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 613
 614 2021-04-06  Alan Modra  <amodra@gmail.com>
 615
 616         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 617         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 618         symbol_at_address_func.
 619
 620 2021-04-05  Alan Modra  <amodra@gmail.com>
 621
 622         * configure.ac: Don't check for limits.h, string.h, strings.h or
 623         stdlib.h.
 624         (AC_ISC_POSIX): Don't invoke.
 625         * sysdep.h: Include stdlib.h and string.h unconditionally.
 626         * i386-opc.h: Include limits.h unconditionally.
 627         * wasm32-dis.c: Likewise.
 628         * cgen-opc.c: Don't include alloca-conf.h.
 629         * config.in: Regenerate.
 630         * configure: Regenerate.
 631
 632 2021-04-01  Martin Liska  <mliska@suse.cz>
 633
 634         * arm-dis.c (strneq): Remove strneq and use startswith.
 635         * cr16-dis.c (print_insn_cr16): Likewise.
 636         * score-dis.c (streq): Likewise.
 637         (strneq): Likewise.
 638         * score7-dis.c (strneq): Likewise.
 639
 640 2021-04-01  Alan Modra  <amodra@gmail.com>
 641
 642         PR 27675
 643         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 644
 645 2021-03-31  Alan Modra  <amodra@gmail.com>
 646
 647         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 648         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 649         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 650         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 651         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 652         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 653         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 654         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 655         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 656         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 657         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 658         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 659         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 660         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 661         and TRUE with true throughout.
 662
 663 2021-03-31  Alan Modra  <amodra@gmail.com>
 664
 665         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 666         * aarch64-dis.h: Likewise.
 667         * aarch64-opc.c: Likewise.
 668         * avr-dis.c: Likewise.
 669         * csky-dis.c: Likewise.
 670         * nds32-asm.c: Likewise.
 671         * nds32-dis.c: Likewise.
 672         * nfp-dis.c: Likewise.
 673         * riscv-dis.c: Likewise.
 674         * s12z-dis.c: Likewise.
 675         * wasm32-dis.c: Likewise.
 676
 677 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 678
 679         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 680         (i386_seg_prefixes): New.
 681         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 682         (i386_seg_prefixes): Declare.
 683
 684 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 685
 686         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 687
 688 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 689
 690         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 691         * i386-reg.tbl (st): Move down.
 692         (st(0)): Delete. Extend comment.
 693         * i386-tbl.h: Re-generate.
 694
 695 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 696
 697         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 698         (cmpsd): Move next to cmps.
 699         (movsd): Move next to movs.
 700         (cmpxchg16b): Move to separate section.
 701         (fisttp, fisttpll): Likewise.
 702         (monitor, mwait): Likewise.
 703         * i386-tbl.h: Re-generate.
 704
 705 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 706
 707         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 708         (vpsadbw): Add C.
 709         * i386-tbl.h: Re-generate.
 710
 711 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 712
 713         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 714         pclmul, gfni): New templates. Use them wherever possible. Move
 715         SSE4.1 pextrw into respective section.
 716         * i386-tbl.h: Re-generate.
 717
 718 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 719
 720         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 721         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 722         "length".
 723         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 724         Convert all of their uses to representation in opcode.
 725
 726 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 727
 728         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 729         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 730         value of None. Shrink operands to 3 bits.
 731
 732 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 733
 734         * i386-gen.c (process_i386_opcode_modifier): New parameter
 735         "space".
 736         (output_i386_opcode): New local variable "space". Adjust
 737         process_i386_opcode_modifier() invocation.
 738         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 739         invocation.
 740         * i386-tbl.h: Re-generate.
 741
 742 2021-03-29  Alan Modra  <amodra@gmail.com>
 743
 744         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 745         (fp_qualifier_p, get_data_pattern): Likewise.
 746         (aarch64_get_operand_modifier_from_value): Likewise.
 747         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 748         (operand_variant_qualifier_p): Likewise.
 749         (qualifier_value_in_range_constraint_p): Likewise.
 750         (aarch64_get_qualifier_esize): Likewise.
 751         (aarch64_get_qualifier_nelem): Likewise.
 752         (aarch64_get_qualifier_standard_value): Likewise.
 753         (get_lower_bound, get_upper_bound): Likewise.
 754         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 755         (aarch64_print_operand): Likewise.
 756         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 757         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 758         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 759         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 760         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 761         (print_insn_tic6x): Likewise.
 762
 763 2021-03-29  Alan Modra  <amodra@gmail.com>
 764
 765         * arc-dis.c (extract_operand_value): Correct NULL cast.
 766         * frv-opc.h: Regenerate.
 767
 768 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 769
 770         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 771         MMX form.
 772         * i386-tbl.h: Re-generate.
 773
 774 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 775
 776         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 777         immediate in br.n instruction.
 778
 779 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 780
 781         * i386-dis.c (XMGatherD, VexGatherD): New.
 782         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 783         (print_insn): Check masking for S/G insns.
 784         (OP_E_memory): New local variable check_gather. Extend mandatory
 785         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 786         Extend check for disallowed 16-bit addressing.
 787         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 788         if()s to switch(). Check register conflicts for (VEX-encoded)
 789         gathers. Drop no longer reachable cases.
 790         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 791         vgatherdp*.
 792
 793 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 794
 795         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 796         zeroing-masking without masking.
 797
 798 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 799
 800         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 801         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 802         single-operand forms as deprecated.
 803         * i386-tbl.h: Re-generate.
 804
 805 2021-03-25  Alan Modra  <amodra@gmail.com>
 806
 807         PR 27647
 808         * ppc-opc.c (XLOCB_MASK): Delete.
 809         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 810         XLBH_MASK.
 811         (powerpc_opcodes): Accept a BH field on all extended forms of
 812         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 813
 814 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 815
 816         * i386-gen.c (output_i386_opcode): Drop processing of
 817         opcode_length. Calculate length from base_opcode. Adjust prefix
 818         encoding determination.
 819         (process_i386_opcodes): Drop output of fake opcode_length.
 820         * i386-opc.h (struct insn_template): Drop opcode_length field.
 821         * i386-opc.tbl: Drop opcode length field from all templates.
 822         * i386-tbl.h: Re-generate.
 823
 824 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 825
 826         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 827         parameter "prefix". Drop local variable "regular_encoding".
 828         Record prefix setting / check for consistency.
 829         (output_i386_opcode): Parse opcode_length and base_opcode
 830         earlier. Derive prefix encoding. Drop no longer applicable
 831         consistency checking. Adjust process_i386_opcode_modifier()
 832         invocation.
 833         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 834         invocation.
 835         * i386-tbl.h: Re-generate.
 836
 837 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 838
 839         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 840         check.
 841         * i386-opc.h (Prefix_*): Move #define-s.
 842         * i386-opc.tbl: Move pseudo prefix enumerator values to
 843         extension opcode field. Introduce pseudopfx template.
 844         * i386-tbl.h: Re-generate.
 845
 846 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 847
 848         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 849         comment.
 850         * i386-tbl.h: Re-generate.
 851
 852 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 853
 854         * i386-opc.h (struct insn_template): Move cpu_flags field past
 855         opcode_modifier one.
 856         * i386-tbl.h: Re-generate.
 857
 858 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 859
 860         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 861         * i386-opc.h (OpcodeSpace): New enumerator.
 862         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 863         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 864         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 865         (struct i386_opcode_modifier): New field opcodespace. Shrink
 866         opcodeprefix field.
 867         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 868         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 869         OpcodePrefix uses.
 870         * i386-tbl.h: Re-generate.
 871
 872 2021-03-22  Martin Liska  <mliska@suse.cz>
 873
 874         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 875         * arc-dis.c (parse_option): Likewise.
 876         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 877         * cris-dis.c (print_with_operands): Likewise.
 878         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 879         * i386-dis.c (print_insn): Likewise.
 880         * ia64-gen.c (fetch_insn_class): Likewise.
 881         (parse_resource_users): Likewise.
 882         (in_iclass): Likewise.
 883         (lookup_specifier): Likewise.
 884         (insert_opcode_dependencies): Likewise.
 885         * mips-dis.c (parse_mips_ase_option): Likewise.
 886         (parse_mips_dis_option): Likewise.
 887         * s390-dis.c (disassemble_init_s390): Likewise.
 888         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 889
 890 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 891
 892         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 893
 894 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 895
 896         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 897         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 898
 899 2021-03-12  Alan Modra  <amodra@gmail.com>
 900
 901         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 902
 903 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 904
 905         * i386-dis.c (OP_XMM): Re-order checks.
 906
 907 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 908
 909         * i386-dis.c (putop): Drop need_vex check when also checking
 910         vex.evex.
 911         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 912         checking vex.b.
 913
 914 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 915
 916         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 917         checks. Move case label past broadcast check.
 918
 919 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 920
 921         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 922         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 923         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 924         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 925         EVEX_W_0F38C7_M_0_L_2): Delete.
 926         (REG_EVEX_0F38C7_M_0_L_2): New.
 927         (intel_operand_size): Handle VEX and EVEX the same for
 928         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 929         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 930         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 931         vex_vsib_q_w_d_mode uses.
 932         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 933         0F38A1, and 0F38A3 entries.
 934         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 935         entry.
 936         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 937         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 938         0F38A3 entries.
 939
 940 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 941
 942         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 943         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 944         MOD_VEX_0FXOP_09_12): Rename to ...
 945         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 946         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 947         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 948         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 949         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 950         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 951         (reg_table): Adjust comments.
 952         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 953         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 954         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 955         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 956         (vex_len_table): Adjust opcode 0A_12 entry.
 957         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 958         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 959         (rm_table): Move hreset entry.
 960
 961 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 962
 963         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 964         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 965         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 966         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 967         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 968         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 969         (get_valid_dis386): Also handle 512-bit vector length when
 970         vectoring into vex_len_table[].
 971         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 972         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 973         entries.
 974         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 975         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 976         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 977         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 978         entries.
 979
 980 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 981
 982         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 983         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 984         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 985         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 986         entries.
 987         * i386-dis-evex-len.h (evex_len_table): Likewise.
 988         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 989
 990 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 991
 992         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 993         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 994         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 995         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 996         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 997         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 998         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 999         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
1000         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
1001         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
1002         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
1003         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
1004         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
1005         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
1006         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
1007         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
1008         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
1009         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
1010         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
1011         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
1012         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
1013         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
1014         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
1015         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
1016         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
1017         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
1018         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
1019         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
1020         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
1021         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
1022         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
1023         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
1024         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
1025         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
1026         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
1027         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
1028         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
1029         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
1030         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
1031         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
1032         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
1033         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
1034         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
1035         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
1036         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
1037         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
1038         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
1039         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
1040         EVEX_W_0F3A43_L_n): New.
1041         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
1042         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
1043         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
1044         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
1045         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
1046         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
1047         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
1048         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
1049         0F385B, 0F38C6, and 0F38C7 entries.
1050         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
1051         0F38C6 and 0F38C7.
1052         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
1053         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
1054         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
1055         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
1056
1057 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1058
1059         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
1060         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
1061         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
1062         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
1063         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
1064         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
1065         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
1066         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
1067         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
1068         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
1069         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
1070         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
1071         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
1072         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
1073         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
1074         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
1075         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
1076         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
1077         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
1078         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
1079         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
1080         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
1081         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
1082         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
1083         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
1084         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
1085         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
1086         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
1087         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
1088         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
1089         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
1090         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
1091         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
1092         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
1093         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
1094         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
1095         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
1096         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
1097         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
1098         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
1099         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
1100         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
1101         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
1102         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
1103         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
1104         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
1105         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
1106         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
1107         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
1108         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
1109         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
1110         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
1111         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
1112         VEX_W_0F99_P_2_LEN_0): Delete.
1113         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
1114         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
1115         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
1116         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
1117         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
1118         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
1119         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
1120         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
1121         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
1122         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
1123         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
1124         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
1125         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
1126         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
1127         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
1128         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
1129         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
1130         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
1131         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
1132         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
1133         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
1134         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
1135         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
1136         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
1137         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
1138         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
1139         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
1140         (prefix_table): No longer link to vex_len_table[] for opcodes
1141         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
1142         0F92, 0F93, 0F98, and 0F99.
1143         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
1144         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1145         0F98, and 0F99.
1146         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
1147         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1148         0F98, and 0F99.
1149         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
1150         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1151         0F98, and 0F99.
1152         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
1153         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1154         0F98, and 0F99.
1155
1156 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1157
1158         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
1159         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
1160         REG_VEX_0F73_M_0 respectively.
1161         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
1162         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
1163         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
1164         MOD_VEX_0F73_REG_7): Delete.
1165         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
1166         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
1167         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
1168         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
1169         PREFIX_VEX_0F3AF0_L_0 respectively.
1170         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
1171         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
1172         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
1173         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
1174         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
1175         VEX_LEN_0F38F7): New.
1176         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
1177         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
1178         0F72, and 0F73. No longer link to vex_len_table[] for opcode
1179         0F38F3.
1180         (prefix_table): No longer link to vex_len_table[] for opcodes
1181         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1182         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
1183         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
1184         0F38F6, 0F38F7, and 0F3AF0.
1185         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
1186         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1187         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
1188         0F73.
1189
1190 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1191
1192         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
1193         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
1194         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
1195         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
1196         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
1197         (MOD_0F71, MOD_0F72, MOD_0F73): New.
1198         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
1199         73.
1200         (reg_table): No longer link to mod_table[] for opcodes 0F71,
1201         0F72, and 0F73.
1202         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
1203         0F73.
1204
1205 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1206
1207         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
1208         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
1209         (reg_table): Don't link to mod_table[] where not needed. Add
1210         PREFIX_IGNORED to nop entries.
1211         (prefix_table): Replace PREFIX_OPCODE in nop entries.
1212         (mod_table): Add nop entries next to prefetch ones. Drop
1213         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
1214         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
1215         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
1216         PREFIX_OPCODE from endbr* entries.
1217         (get_valid_dis386): Also consider entry's name when zapping
1218         vindex.
1219         (print_insn): Handle PREFIX_IGNORED.
1220
1221 2021-03-09  Jan Beulich  <jbeulich@suse.com>
1222
1223         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
1224         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
1225         element.
1226         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
1227         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
1228         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
1229         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
1230         (struct i386_opcode_modifier): Delete notrackprefixok,
1231         islockable, hleprefixok, and repprefixok fields. Add prefixok
1232         field.
1233         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
1234         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
1235         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
1236         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
1237         Replace HLEPrefixOk.
1238         * opcodes/i386-tbl.h: Re-generate.
1239
1240 2021-03-09  Jan Beulich  <jbeulich@suse.com>
1241
1242         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
1243         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
1244         64-bit form.
1245         * opcodes/i386-tbl.h: Re-generate.
1246
1247 2021-03-03  Jan Beulich  <jbeulich@suse.com>
1248
1249         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
1250         for {} instead of {0}. Don't look for '0'.
1251         * i386-opc.tbl: Drop operand count field. Drop redundant operand
1252         size specifiers.
1253
1254 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
1255
1256         PR 27158
1257         * riscv-dis.c (print_insn_args): Updated encoding macros.
1258         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1259         (match_c_addi16sp): Updated encoding macros.
1260         (match_c_lui): Likewise.
1261         (match_c_lui_with_hint): Likewise.
1262         (match_c_addi4spn): Likewise.
1263         (match_c_slli): Likewise.
1264         (match_slli_as_c_slli): Likewise.
1265         (match_c_slli64): Likewise.
1266         (match_srxi_as_c_srxi): Likewise.
1267         (riscv_insn_types): Added .insn css/cl/cs.
1268
1269 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
1270
1271         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1272         (default_priv_spec): Updated type to riscv_spec_class.
1273         (parse_riscv_dis_option): Updated.
1274         * riscv-opc.c: Moved stuff and make the file tidy.
1275
1276 2021-02-17  Alan Modra  <amodra@gmail.com>
1277
1278         * wasm32-dis.c: Include limits.h.
1279         (CHAR_BIT): Provide backup define.
1280         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1281         Correct signed overflow checking.
1282
1283 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1284
1285         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1286         * i386-tbl.h: Re-generate.
1287
1288 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1289
1290         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1291         Oword.
1292         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1293
1294 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
1295
1296         * s390-mkopc.c (main): Accept arch14 as cpu string.
1297         * s390-opc.txt: Add new arch14 instructions.
1298
1299 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
1300
1301         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1302         favour of LIBINTL.
1303         * configure: Regenerated.
1304
1305 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
1306
1307         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1308         * tic54x-opc.c (regs): Rename to ...
1309         (tic54x_regs): ... this.
1310         (mmregs): Rename to ...
1311         (tic54x_mmregs): ... this.
1312         (condition_codes): Rename to ...
1313         (tic54x_condition_codes): ... this.
1314         (cc2_codes): Rename to ...
1315         (tic54x_cc2_codes): ... this.
1316         (cc3_codes): Rename to ...
1317         (tic54x_cc3_codes): ... this.
1318         (status_bits): Rename to ...
1319         (tic54x_status_bits): ... this.
1320         (misc_symbols): Rename to ...
1321         (tic54x_misc_symbols): ... this.
1322
1323 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
1324
1325         * riscv-opc.c (MASK_RVB_IMM): Removed.
1326         (riscv_opcodes): Removed zb* instructions.
1327         (riscv_ext_version_table): Removed versions for zb*.
1328
1329 2021-01-26  Alan Modra  <amodra@gmail.com>
1330
1331         * i386-gen.c (parse_template): Ensure entire template_instance
1332         is initialised.
1333
1334 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1335
1336         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1337         (riscv_fpr_names_abi): Likewise.
1338         (riscv_opcodes): Likewise.
1339         (riscv_insn_types): Likewise.
1340
1341 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1342
1343         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1344
1345 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1346
1347         * riscv-dis.c: Comments tidy and improvement.
1348         * riscv-opc.c: Likewise.
1349
1350 2021-01-13  Alan Modra  <amodra@gmail.com>
1351
1352         * Makefile.in: Regenerate.
1353
1354 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
1355
1356         PR binutils/26792
1357         * configure.ac: Use GNU_MAKE_JOBSERVER.
1358         * aclocal.m4: Regenerated.
1359         * configure: Likewise.
1360
1361 2021-01-12  Nick Clifton  <nickc@redhat.com>
1362
1363         * po/sr.po: Updated Serbian translation.
1364
1365 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
1366
1367         PR ld/27173
1368         * configure: Regenerated.
1369
1370 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1371
1372         * aarch64-asm-2.c: Regenerate.
1373         * aarch64-dis-2.c: Likewise.
1374         * aarch64-opc-2.c: Likewise.
1375         * aarch64-opc.c (aarch64_print_operand):
1376         Delete handling of AARCH64_OPND_CSRE_CSR.
1377         * aarch64-tbl.h (aarch64_feature_csre): Delete.
1378         (CSRE): Likewise.
1379         (_CSRE_INSN): Likewise.
1380         (aarch64_opcode_table): Delete csr.
1381
1382 2021-01-11  Nick Clifton  <nickc@redhat.com>
1383
1384         * po/de.po: Updated German translation.
1385         * po/fr.po: Updated French translation.
1386         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1387         * po/sv.po: Updated Swedish translation.
1388         * po/uk.po: Updated Ukranian translation.
1389
1390 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
1391
1392         * configure: Regenerated.
1393
1394 2021-01-09  Nick Clifton  <nickc@redhat.com>
1395
1396         * configure: Regenerate.
1397         * po/opcodes.pot: Regenerate.
1398
1399 2021-01-09  Nick Clifton  <nickc@redhat.com>
1400
1401         * 2.36 release branch crated.
1402
1403 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
1404
1405         * ppc-opc.c (insert_dw, (extract_dw): New functions.
1406         (DW, (XRC_MASK): Define.
1407         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1408
1409 2021-01-09  Alan Modra  <amodra@gmail.com>
1410
1411         * configure: Regenerate.
1412
1413 2021-01-08  Nick Clifton  <nickc@redhat.com>
1414
1415         * po/sv.po: Updated Swedish translation.
1416
1417 2021-01-08  Nick Clifton  <nickc@redhat.com>
1418
1419         PR 27129
1420         * aarch64-dis.c (determine_disassembling_preference): Move call to
1421         aarch64_match_operands_constraint outside of the assertion.
1422         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1423         Replace with a return of FALSE.
1424
1425         PR 27139
1426         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1427         core system register.
1428
1429 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
1430
1431         * configure: Regenerate.
1432
1433 2021-01-07  Nick Clifton  <nickc@redhat.com>
1434
1435         * po/fr.po: Updated French translation.
1436
1437 2021-01-07  Fredrik Noring  <noring@nocrew.org>
1438
1439         * m68k-opc.c (chkl): Change minimum architecture requirement to
1440         m68020.
1441
1442 2021-01-07  Philipp Tomsich  <prt@gnu.org>
1443
1444         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1445
1446 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
1447             Jim Wilson  <jimw@sifive.com>
1448             Andrew Waterman  <andrew@sifive.com>
1449             Maxim Blinov  <maxim.blinov@embecosm.com>
1450             Kito Cheng  <kito.cheng@sifive.com>
1451             Nelson Chu  <nelson.chu@sifive.com>
1452
1453         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1454         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1455
1456 2021-01-01  Alan Modra  <amodra@gmail.com>
1457
1458         Update year range in copyright notice of all files.
1459
1460 For older changes see ChangeLog-2020
1461 \f
1462 Copyright (C) 2021-2023 Free Software Foundation, Inc.
1463
1464 Copying and distribution of this file, with or without modification,
1465 are permitted in any medium without royalty provided the copyright
1466 notice and this notice are preserved.
1467
1468 Local Variables:
1469 mode: change-log
1470 left-margin: 8
1471 fill-column: 74
1472 version-control: never
1473 End: