opcodes/ChangeLog

   1 2006-09-16  Nick Clifton  <nickc@redhat.com>
   2             Pedro Alves  <pedro_alves@portugalmail.pt>
   3
   4         * arm-dis.c: Make use of new STRING_COMMA_LEN and CONST_STRNEQ
   5         macros defined in bfd.h.
   6         * cris-dis.c: Likewise.
   7         * h8300-dis.c: Likewise.
   8         * i386-dis.c: Likewise.
   9         * ia64-gen.c: Likewise.
  10         * mips-dis: Likewise.
  11
  12 2006-09-04  Paul Brook  <paul@codesourcery.com>
  13
  14         * arm-dis.c (neon_opcode): Fix suffix on VMOVN.
  15
  16 2006-08-23  H.J. Lu  <hongjiu.lu@intel.com>
  17
  18         * i386-dis.c (three_byte_table): Expand to 256 elements.
  19
  20 2006-08-04  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
  21
  22         * i386-dis.c (MXC,EMC): Define.
  23         (OP_MXC): New function to handle cvt* (convert instructions) between
  24         %xmm and %mm register correctly.
  25         (OP_EMC): ditto.
  26         (prefix_user_table): Modified cvtpi2pd,cvtpd2pi and cvttpd2pi
  27         instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately
  28         with EMC/MXC.
  29
  30 2006-07-29  Richard Sandiford  <richard@codesourcery.com>
  31
  32         * m68k-opc.c (m68k_opcodes): Fix operand specificer in the Coldfire
  33         "fdaddl" entry.
  34
  35 2006-07-19  Paul Brook  <paul@codesourcery.com>
  36
  37         * armd-dis.c (arm_opcodes): Fix rbit opcode.
  38
  39 2006-07-18  H.J. Lu  <hongjiu.lu@intel.com>
  40
  41         * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to
  42         "sldt", "str" and "smsw".
  43
  44 2006-07-15  H.J. Lu  <hongjiu.lu@intel.com>
  45
  46         PR binutils/2829
  47         * i386-dis.c (GRP11_C6): NEW.
  48         (GRP11_C7): Likewise.
  49         (GRP12): Updated.
  50         (GRP13): Likewise.
  51         (GRP14): Likewise.
  52         (GRP15): Likewise.
  53         (GRP16): Likewise.
  54         (GRPAMD): Likewise.
  55         (GRPPADLCK1): Likewise.
  56         (GRPPADLCK2): Likewise.
  57         (dis386): Use GRP11_C6 and GRP11_C7 for entres 0xc6 and 0xc7,
  58         respectively.
  59         (grps): Add entries for GRP11_C6 and GRP11_C7.
  60
  61 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
  62            Michael Meissner             <michael.meissner@amd.com>
  63
  64         * i386-dis.c (dis386): Add support for 4 operand instructions. Add
  65         support for amdfam10 SSE4a/ABM instructions. Modify all
  66         initializer macros to have additional arguments. Disallow REP
  67         prefix for non-string instructions.
  68         (print_insn): Ditto.
  69
  70
  71 2006-07-05  Julian Brown  <julian@codesourcery.com>
  72
  73         * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.
  74
  75 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
  76
  77         * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.
  78         (twobyte_has_modrm): Set 1 for 0x1f.
  79
  80 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
  81
  82         * i386-dis.c (NOP_Fixup): Removed.
  83         (NOP_Fixup1): New.
  84         (NOP_Fixup2): Likewise.
  85         (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
  86
  87 2006-06-12  Julian Brown  <julian@codesourcery.com>
  88
  89         * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signed
  90         on 64-bit hosts.
  91
  92 2006-06-10  H.J. Lu  <hongjiu.lu@intel.com>
  93
  94         * i386.c (GRP10): Renamed to ...
  95         (GRP12): This.
  96         (GRP11): Renamed to ...
  97         (GRP13): This.
  98         (GRP12): Renamed to ...
  99         (GRP14): This.
 100         (GRP13): Renamed to ...
 101         (GRP15): This.
 102         (GRP14): Renamed to ...
 103         (GRP16): This.
 104         (dis386_twobyte): Updated.
 105         (grps): Likewise.
 106
 107 2006-06-09  Nick Clifton  <nickc@redhat.com>
 108
 109         * po/fi.po: Updated Finnish translation.
 110
 111 2006-06-07  Joseph S. Myers  <joseph@codesourcery.com>
 112
 113         * po/Make-in (pdf, ps): New dummy targets.
 114
 115 2006-06-06  Paul Brook  <paul@codesourcery.com>
 116
 117         * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm
 118         instructions.
 119         (neon_opcodes): Add conditional execution specifiers.
 120         (thumb_opcodes): Ditto.
 121         (thumb32_opcodes): Ditto.
 122         (arm_conditional): Change 0xe to "al" and add "" to end.
 123         (ifthen_state, ifthen_next_state, ifthen_address): New.
 124         (IFTHEN_COND): Define.
 125         (print_insn_coprocessor, print_insn_neon): Print thumb conditions.
 126         (print_insn_arm): Change %c to use new values of arm_conditional.
 127         (print_insn_thumb16): Print thumb conditions.  Add %I.
 128         (print_insn_thumb32): Print thumb conditions.
 129         (find_ifthen_state): New function.
 130         (print_insn): Track IT block state.
 131
 132 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 133             Anton Blanchard  <anton@samba.org>
 134             Peter Bergner  <bergner@vnet.ibm.com>
 135
 136         * ppc-dis.c (powerpc_dialect): Handle power6 option.
 137         (print_ppc_disassembler_options): Mention power6.
 138
 139 2006-06-06  Thiemo Seufer  <ths@mips.com>
 140             Chao-ying Fu  <fu@mips.com>
 141
 142         * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2.
 143         * mips-opc.c: Add DSP64 instructions.
 144
 145 2006-06-06  Alan Modra  <amodra@bigpond.net.au>
 146
 147         * m68hc11-dis.c (print_insn): Warning fix.
 148
 149 2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>
 150
 151         * po/Make-in (top_builddir): Define.
 152
 153 2006-06-05  Alan Modra  <amodra@bigpond.net.au>
 154
 155         * Makefile.am: Run "make dep-am".
 156         * Makefile.in: Regenerate.
 157         * config.in: Regenerate.
 158
 159 2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>
 160
 161         * Makefile.am (INCLUDES): Use @INCINTL@.
 162         * acinclude.m4: Include new gettext macros.
 163         * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
 164         Remove local code for po/Makefile.
 165         * Makefile.in, aclocal.m4, configure: Regenerated.
 166
 167 2006-05-30  Nick Clifton  <nickc@redhat.com>
 168
 169         * po/es.po: Updated Spanish translation.
 170
 171 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 172
 173         * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
 174         and fmovem entries.  Put register list entries before immediate
 175         mask entries.  Use "l" rather than "L" in the fmovem entries.
 176         * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
 177         out from INFO.
 178         (m68k_scan_mask): New function, split out from...
 179         (print_insn_m68k): ...here.  If no architecture has been set,
 180         first try printing an m680x0 instruction, then try a Coldfire one.
 181
 182 2006-05-24  Nick Clifton  <nickc@redhat.com>
 183
 184         * po/ga.po: Updated Irish translation.
 185
 186 2006-05-22  Nick Clifton  <nickc@redhat.com>
 187
 188         * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.
 189
 190 2006-05-22  Nick Clifton  <nickc@redhat.com>
 191
 192         * po/nl.po: Updated translation.
 193
 194 2006-05-18  Alan Modra  <amodra@bigpond.net.au>
 195
 196         * avr-dis.c: Formatting fix.
 197
 198 2006-05-14  Thiemo Seufer  <ths@mips.com>
 199
 200         * mips16-opc.c (I1, I32, I64): New shortcut defines.
 201         (mips16_opcodes): Change membership of instructions to their
 202         lowest baseline ISA.
 203
 204 2006-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 205
 206         * i386-dis.c (grps): Update sgdt/sidt for 64bit.
 207
 208 2006-05-05  Julian Brown  <julian@codesourcery.com>
 209
 210         * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
 211         vldm/vstm.
 212
 213 2006-05-05  Thiemo Seufer  <ths@mips.com>
 214             David Ung  <davidu@mips.com>
 215
 216         * mips-opc.c: Add macro for cache instruction.
 217
 218 2006-05-04  Thiemo Seufer  <ths@mips.com>
 219             Nigel Stephens  <nigel@mips.com>
 220             David Ung  <davidu@mips.com>
 221
 222         * mips-dis.c (mips_arch_choices): Add smartmips instruction
 223         decoding to MIPS32 and MIPS32R2.  Limit DSP decoding to release
 224         2 ISAs.  Add MIPS3D decoding to MIPS32R2.  Add MT decoding to
 225         MIPS64R2.
 226         * mips-opc.c: fix random typos in comments.
 227         (INSN_SMARTMIPS): New defines.
 228         (mips_builtin_opcodes): Add paired single support for MIPS32R2.
 229         Move bc3f, bc3fl, bc3t, bc3tl downwards.  Move flushi, flushd,
 230         flushid, wb upwards.  Move cfc3, ctc3 downwards.  Rework the
 231         FP_S and FP_D flags to denote single and double register
 232         accesses separately.  Move dmfc3, dmtc3, mfc3, mtc3 downwards.
 233         Allow jr.hb and jalr.hb for release 1 ISAs.  Allow luxc1, suxc1
 234         for MIPS32R2.  Add SmartMIPS instructions.  Add two-argument
 235         variants of bc2f, bc2fl, bc2t, bc2tl.  Add mfhc2, mthc2 to
 236         release 2 ISAs.
 237         * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
 238
 239 2006-05-03  Thiemo Seufer  <ths@mips.com>
 240
 241         * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
 242
 243 2006-05-02  Thiemo Seufer  <ths@mips.com>
 244             Nigel Stephens  <nigel@mips.com>
 245             David Ung  <davidu@mips.com>
 246
 247         * mips-dis.c (print_insn_args): Force mips16 to odd addresses.
 248         (print_mips16_insn_arg): Force mips16 to odd addresses.
 249
 250 2006-04-30  Thiemo Seufer  <ths@mips.com>
 251             David Ung  <davidu@mips.com>
 252
 253         * mips-opc.c (mips_builtin_opcodes): Add udi instructions
 254         "udi0" to "udi15".
 255         * mips-dis.c (print_insn_args): Adds udi argument handling.
 256
 257 2006-04-28  James E Wilson  <wilson@specifix.com>
 258
 259         * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
 260         error message.
 261
 262 2006-04-28  Thiemo Seufer  <ths@mips.com>
 263             David Ung  <davidu@mips.com>
 264             Nigel Stephens  <nigel@mips.com>
 265
 266         * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
 267         names.
 268
 269 2006-04-28  Thiemo Seufer  <ths@mips.com>
 270             Nigel Stephens  <nigel@mips.com>
 271             David Ung  <davidu@mips.com>
 272
 273         * mips-dis.c (print_insn_args): Add mips_opcode argument.
 274         (print_insn_mips):  Adjust print_insn_args call.
 275
 276 2006-04-28  Thiemo Seufer  <ths@mips.com>
 277             Nigel Stephens  <nigel@mips.com>
 278
 279         * mips-dis.c (print_insn_args): Print $fcc only for FP
 280         instructions, use $cc elsewise.
 281
 282 2006-04-28  Thiemo Seufer  <ths@mips.com>
 283             Nigel Stephens  <nigel@mips.com>
 284
 285         * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
 286         Map MIPS16 registers to O32 names.
 287         (print_mips16_insn_arg): Use mips16_reg_names.
 288
 289 2006-04-26  Julian Brown  <julian@codesourcery.com>
 290
 291         * arm-dis.c (print_insn_neon): Disassemble floating-point constant
 292         VMOV.
 293
 294 2006-04-26  Nathan Sidwell  <nathan@codesourcery.com>
 295             Julian Brown  <julian@codesourcery.com>
 296
 297         * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
 298         %<code>[zy] into %[zy]<code>.  Expand meaning of %<bitfield>['`?].
 299         Add unified load/store instruction names.
 300         (neon_opcode_table): New.
 301         (arm_opcodes): Expand meaning of %<bitfield>['`?].
 302         (arm_decode_bitfield): New.
 303         (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
 304         Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
 305         (print_insn_neon): New.
 306         (print_insn_arm): Adjust print_insn_coprocessor call. Call
 307         print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
 308         (print_insn_thumb32): Likewise.
 309
 310 2006-04-19  Alan Modra  <amodra@bigpond.net.au>
 311
 312         * Makefile.am: Run "make dep-am".
 313         * Makefile.in: Regenerate.
 314
 315 2006-04-19  Alan Modra  <amodra@bigpond.net.au>
 316
 317         * avr-dis.c (avr_operand): Warning fix.
 318
 319         * configure: Regenerate.
 320
 321 2006-04-16  Daniel Jacobowitz  <dan@codesourcery.com>
 322
 323         * po/POTFILES.in: Regenerated.
 324
 325 2006-04-12   Hochstein  <hochstein@algo.informatik.tu-darmstadt.de>
 326
 327         PR binutils/2454
 328         * avr-dis.c (avr_operand): Arrange for a comment to appear before
 329         the symolic form of an address, so that the output of objdump -d
 330         can be reassembled.
 331
 332 2006-04-10  DJ Delorie  <dj@redhat.com>
 333
 334         * m32c-asm.c: Regenerate.
 335
 336 2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>
 337
 338         * Makefile.am: Add install-html target.
 339         * Makefile.in: Regenerate.
 340
 341 2006-04-06  Nick Clifton  <nickc@redhat.com>
 342
 343         * po/vi/po: Updated Vietnamese translation.
 344
 345 2006-03-31  Paul Koning  <ni1d@arrl.net>
 346
 347         * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
 348
 349 2006-03-16  Bernd Schmidt  <bernd.schmidt@analog.com>
 350
 351         * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
 352         logic to identify halfword shifts.
 353
 354 2006-03-16  Paul Brook  <paul@codesourcery.com>
 355
 356         * arm-dis.c (arm_opcodes): Rename swi to svc.
 357         (thumb_opcodes): Ditto.
 358
 359 2006-03-13  DJ Delorie  <dj@redhat.com>
 360
 361         * m32c-asm.c: Regenerate.
 362         * m32c-desc.c: Likewise.
 363         * m32c-desc.h: Likewise.
 364         * m32c-dis.c: Likewise.
 365         * m32c-ibld.c: Likewise.
 366         * m32c-opc.c: Likewise.
 367         * m32c-opc.h: Likewise.
 368
 369 2006-03-10  DJ Delorie  <dj@redhat.com>
 370
 371         * m32c-desc.c: Regenerate with mul.l, mulu.l.
 372         * m32c-opc.c: Likewise.
 373         * m32c-opc.h: Likewise.
 374
 375
 376 2006-03-09  Nick Clifton  <nickc@redhat.com>
 377
 378         * po/sv.po: Updated Swedish translation.
 379
 380 2006-03-07  H.J. Lu  <hongjiu.lu@intel.com>
 381
 382         PR binutils/2428
 383         * i386-dis.c (REP_Fixup): New function.
 384         (AL): Remove duplicate.
 385         (Xbr): New.
 386         (Xvr): Likewise.
 387         (Ybr): Likewise.
 388         (Yvr): Likewise.
 389         (indirDXr): Likewise.
 390         (ALr): Likewise.
 391         (eAXr): Likewise.
 392         (dis386): Updated entries of ins, outs, movs, lods and stos.
 393
 394 2006-03-05  Nick Clifton  <nickc@redhat.com>
 395
 396         * cgen-ibld.in (insert_normal): Cope with attempts to insert a
 397         signed 32-bit value into an unsigned 32-bit field when the host is
 398         a 64-bit machine.
 399         * fr30-ibld.c: Regenerate.
 400         * frv-ibld.c: Regenerate.
 401         * ip2k-ibld.c: Regenerate.
 402         * iq2000-asm.c: Regenerate.
 403         * iq2000-ibld.c: Regenerate.
 404         * m32c-ibld.c: Regenerate.
 405         * m32r-ibld.c: Regenerate.
 406         * openrisc-ibld.c: Regenerate.
 407         * xc16x-ibld.c: Regenerate.
 408         * xstormy16-ibld.c: Regenerate.
 409
 410 2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
 411
 412         * xc16x-asm.c: Regenerate.
 413         * xc16x-dis.c: Regenerate.
 414
 415 2006-02-27  Carlos O'Donell  <carlos@codesourcery.com>
 416
 417         * po/Make-in: Add html target.
 418
 419 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 420
 421         * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
 422         Intel Merom New Instructions.
 423         (THREE_BYTE_0): Likewise.
 424         (THREE_BYTE_1): Likewise.
 425         (three_byte_table): Likewise.
 426         (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
 427         THREE_BYTE_1 for entry 0x3a.
 428         (twobyte_has_modrm): Updated.
 429         (twobyte_uses_SSE_prefix): Likewise.
 430         (print_insn): Handle 3-byte opcodes used by Intel Merom New
 431         Instructions.
 432
 433 2006-02-24  David S. Miller  <davem@sunset.davemloft.net>
 434
 435         * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
 436         (v9_hpriv_reg_names): New table.
 437         (print_insn_sparc): Allow values up to 16 for '?' and '!'.
 438         New cases '$' and '%' for read/write hyperprivileged register.
 439         * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
 440         window handling and rdhpr/wrhpr instructions.
 441
 442 2006-02-24  DJ Delorie  <dj@redhat.com>
 443
 444         * m32c-desc.c: Regenerate with linker relaxation attributes.
 445         * m32c-desc.h: Likewise.
 446         * m32c-dis.c: Likewise.
 447         * m32c-opc.c: Likewise.
 448
 449 2006-02-24  Paul Brook  <paul@codesourcery.com>
 450
 451         * arm-dis.c (arm_opcodes): Add V7 instructions.
 452         (thumb32_opcodes): Ditto.  Handle V7M MSR/MRS variants.
 453         (print_arm_address): New function.
 454         (print_insn_arm): Use it.  Add 'P' and 'U' cases.
 455         (psr_name): New function.
 456         (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
 457
 458 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 459
 460         * ia64-opc-i.c (bXc): New.
 461         (mXc): Likewise.
 462         (OpX2TaTbYaXcC): Likewise.
 463         (TF). Likewise.
 464         (TFCM). Likewise.
 465         (ia64_opcodes_i): Add instructions for tf.
 466
 467         * ia64-opc.h (IMMU5b): New.
 468
 469         * ia64-asmtab.c: Regenerated.
 470
 471 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 472
 473         * ia64-gen.c: Update copyright years.
 474         * ia64-opc-b.c: Likewise.
 475
 476 2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 477
 478         * ia64-gen.c (lookup_regindex): Handle ".vm".
 479         (print_dependency_table): Handle '\"'.
 480
 481         * ia64-ic.tbl: Updated from SDM 2.2.
 482         * ia64-raw.tbl: Likewise.
 483         * ia64-waw.tbl: Likewise.
 484         * ia64-asmtab.c: Regenerated.
 485
 486         * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
 487
 488 2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
 489             Anil Paranjape   <anilp1@kpitcummins.com>
 490             Shilin Shakti    <shilins@kpitcummins.com>
 491
 492         * xc16x-desc.h: New file
 493         * xc16x-desc.c: New file
 494         * xc16x-opc.h: New file
 495         * xc16x-opc.c: New file
 496         * xc16x-ibld.c: New file
 497         * xc16x-asm.c: New file
 498         * xc16x-dis.c: New file
 499         * Makefile.am: Entries for xc16x
 500         * Makefile.in: Regenerate
 501         * cofigure.in: Add xc16x target information.
 502         * configure: Regenerate.
 503         * disassemble.c: Add xc16x target information.
 504
 505 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 506
 507         * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
 508         moves.
 509
 510 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 511
 512         * i386-dis.c ('Z'): Add a new macro.
 513         (dis386_twobyte): Use "movZ" for control register moves.
 514
 515 2006-02-10  Nick Clifton  <nickc@redhat.com>
 516
 517         * iq2000-asm.c: Regenerate.
 518
 519 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 520
 521         * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
 522
 523 2006-01-26  David Ung  <davidu@mips.com>
 524
 525         * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
 526         ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
 527         floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
 528         nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
 529         rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
 530
 531 2006-01-18  Arnold Metselaar  <arnoldm@sourceware.org>
 532
 533         * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
 534         ld_d_r, pref_xd_cb): Use signed char to hold data to be
 535         disassembled.
 536         * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
 537         buffer overflows when disassembling instructions like
 538         ld (ix+123),0x23
 539         * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
 540         operand, if the offset is negative.
 541
 542 2006-01-17  Arnold Metselaar  <arnoldm@sourceware.org>
 543
 544         * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
 545         unsigned char to hold data to be disassembled.
 546
 547 2006-01-17  Andreas Schwab  <schwab@suse.de>
 548
 549         PR binutils/1486
 550         * disassemble.c (disassemble_init_for_target): Set
 551         disassembler_needs_relocs for bfd_arch_arm.
 552
 553 2006-01-16  Paul Brook  <paul@codesourcery.com>
 554
 555         * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
 556         f?add?, and f?sub? instructions.
 557
 558 2006-01-16  Nick Clifton  <nickc@redhat.com>
 559
 560         * po/zh_CN.po: New Chinese (simplified) translation.
 561         * configure.in (ALL_LINGUAS): Add "zh_CH".
 562         * configure: Regenerate.
 563
 564 2006-01-05  Paul Brook  <paul@codesourcery.com>
 565
 566         * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
 567
 568 2006-01-06  DJ Delorie  <dj@redhat.com>
 569
 570         * m32c-desc.c: Regenerate.
 571         * m32c-opc.c: Regenerate.
 572         * m32c-opc.h: Regenerate.
 573
 574 2006-01-03  DJ Delorie  <dj@redhat.com>
 575
 576         * cgen-ibld.in (extract_normal): Avoid memory range errors.
 577         * m32c-ibld.c: Regenerated.
 578
 579 For older changes see ChangeLog-2005
 580 \f
 581 Local Variables:
 582 mode: change-log
 583 left-margin: 8
 584 fill-column: 74
 585 version-control: never
 586 End: