opcodes/ChangeLog

   1 2020-05-11  Nick Clifton  <nickc@redhat.com>
   2
   3         * po/fr.po: Updated French translation.
   4
   5 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
   6
   7         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
   8         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
   9         (operand_general_constraint_met_p): validate
  10         AARCH64_OPND_UNDEFINED.
  11         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
  12         for FLD_imm16_2.
  13         * aarch64-asm-2.c: Regenerated.
  14         * aarch64-dis-2.c: Regenerated.
  15         * aarch64-opc-2.c: Regenerated.
  16
  17 2020-04-29  Nick Clifton  <nickc@redhat.com>
  18
  19         PR 22699
  20         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
  21         and SETRC insns.
  22
  23 2020-04-29  Nick Clifton  <nickc@redhat.com>
  24
  25         * po/sv.po: Updated Swedish translation.
  26
  27 2020-04-29  Nick Clifton  <nickc@redhat.com>
  28
  29         PR 22699
  30         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
  31         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
  32         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
  33         IMM0_8U case.
  34
  35 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
  36
  37         PR 25848
  38         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
  39         cmpi only on m68020up and cpu32.
  40
  41 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
  42
  43         * aarch64-asm.c (aarch64_ins_none): New.
  44         * aarch64-asm.h (ins_none): New declaration.
  45         * aarch64-dis.c (aarch64_ext_none): New.
  46         * aarch64-dis.h (ext_none): New declaration.
  47         * aarch64-opc.c (aarch64_print_operand): Update case for
  48         AARCH64_OPND_BARRIER_PSB.
  49         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
  50         (AARCH64_OPERANDS): Update inserter/extracter for
  51         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
  52         * aarch64-asm-2.c: Regenerated.
  53         * aarch64-dis-2.c: Regenerated.
  54         * aarch64-opc-2.c: Regenerated.
  55
  56 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
  57
  58         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
  59         (aarch64_feature_ras, RAS): Likewise.
  60         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
  61         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
  62         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
  63         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
  64         * aarch64-asm-2.c: Regenerated.
  65         * aarch64-dis-2.c: Regenerated.
  66         * aarch64-opc-2.c: Regenerated.
  67
  68 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
  69
  70         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
  71         (print_insn_neon): Support disassembly of conditional
  72         instructions.
  73
  74 2020-02-16  David Faust  <david.faust@oracle.com>
  75
  76         * bpf-desc.c: Regenerate.
  77         * bpf-desc.h: Likewise.
  78         * bpf-opc.c: Regenerate.
  79         * bpf-opc.h: Likewise.
  80
  81 2020-04-07  Lili Cui  <lili.cui@intel.com>
  82
  83         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
  84         (prefix_table): New instructions (see prefixes above).
  85         (rm_table): Likewise
  86         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
  87         CPU_ANY_TSXLDTRK_FLAGS.
  88         (cpu_flags): Add CpuTSXLDTRK.
  89         * i386-opc.h (enum): Add CpuTSXLDTRK.
  90         (i386_cpu_flags): Add cputsxldtrk.
  91         * i386-opc.tbl: Add XSUSPLDTRK insns.
  92         * i386-init.h: Regenerate.
  93         * i386-tbl.h: Likewise.
  94
  95 2020-04-02  Lili Cui  <lili.cui@intel.com>
  96
  97         * i386-dis.c (prefix_table): New instructions serialize.
  98         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
  99         CPU_ANY_SERIALIZE_FLAGS.
 100         (cpu_flags): Add CpuSERIALIZE.
 101         * i386-opc.h (enum): Add CpuSERIALIZE.
 102         (i386_cpu_flags): Add cpuserialize.
 103         * i386-opc.tbl: Add SERIALIZE insns.
 104         * i386-init.h: Regenerate.
 105         * i386-tbl.h: Likewise.
 106
 107 2020-03-26  Alan Modra  <amodra@gmail.com>
 108
 109         * disassemble.h (opcodes_assert): Declare.
 110         (OPCODES_ASSERT): Define.
 111         * disassemble.c: Don't include assert.h.  Include opintl.h.
 112         (opcodes_assert): New function.
 113         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 114         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 115         calculate maxlen.  Omit insn decoding when insn length exceeds
 116         maxlen.  Exit from nibble loop when looking for E, before
 117         accessing next data byte.  Move processing of E outside loop.
 118         Replace tests of maxlen in loop with assertions.
 119
 120 2020-03-26  Alan Modra  <amodra@gmail.com>
 121
 122         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 123
 124 2020-03-25  Alan Modra  <amodra@gmail.com>
 125
 126         * z80-dis.c (suffix): Init mybuf.
 127
 128 2020-03-22  Alan Modra  <amodra@gmail.com>
 129
 130         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 131         successflly read from section.
 132
 133 2020-03-22  Alan Modra  <amodra@gmail.com>
 134
 135         * arc-dis.c (find_format): Use ISO C string concatenation rather
 136         than line continuation within a string.  Don't access needs_limm
 137         before testing opcode != NULL.
 138
 139 2020-03-22  Alan Modra  <amodra@gmail.com>
 140
 141         * ns32k-dis.c (print_insn_arg): Update comment.
 142         (print_insn_ns32k): Reduce size of index_offset array, and
 143         initialize, passing -1 to print_insn_arg for args that are not
 144         an index.  Don't exit arg loop early.  Abort on bad arg number.
 145
 146 2020-03-22  Alan Modra  <amodra@gmail.com>
 147
 148         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 149         * s12z-opc.c: Formatting.
 150         (operands_f): Return an int.
 151         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 152         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 153         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 154         (exg_sex_discrim): Likewise.
 155         (create_immediate_operand, create_bitfield_operand),
 156         (create_register_operand_with_size, create_register_all_operand),
 157         (create_register_all16_operand, create_simple_memory_operand),
 158         (create_memory_operand, create_memory_auto_operand): Don't
 159         segfault on malloc failure.
 160         (z_ext24_decode): Return an int status, negative on fail, zero
 161         on success.
 162         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 163         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 164         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 165         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 166         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 167         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 168         (loop_primitive_decode, shift_decode, psh_pul_decode),
 169         (bit_field_decode): Similarly.
 170         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 171         to return value, update callers.
 172         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 173         Don't segfault on NULL operand.
 174         (decode_operation): Return OP_INVALID on first fail.
 175         (decode_s12z): Check all reads, returning -1 on fail.
 176
 177 2020-03-20  Alan Modra  <amodra@gmail.com>
 178
 179         * metag-dis.c (print_insn_metag): Don't ignore status from
 180         read_memory_func.
 181
 182 2020-03-20  Alan Modra  <amodra@gmail.com>
 183
 184         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 185         Initialize parts of buffer not written when handling a possible
 186         2-byte insn at end of section.  Don't attempt decoding of such
 187         an insn by the 4-byte machinery.
 188
 189 2020-03-20  Alan Modra  <amodra@gmail.com>
 190
 191         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 192         partially filled buffer.  Prevent lookup of 4-byte insns when
 193         only VLE 2-byte insns are possible due to section size.  Print
 194         ".word" rather than ".long" for 2-byte leftovers.
 195
 196 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 197
 198         PR 25641
 199         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 200
 201 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 202
 203         * i386-dis.c (X86_64_0D): Rename to ...
 204         (X86_64_0E): ... this.
 205
 206 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 207
 208         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 209         * Makefile.in: Regenerated.
 210
 211 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 212
 213         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 214         3-operand pseudos.
 215         * i386-tbl.h: Re-generate.
 216
 217 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 218
 219         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 220         vprot*, vpsha*, and vpshl*.
 221         * i386-tbl.h: Re-generate.
 222
 223 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 224
 225         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 226         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 227         * i386-tbl.h: Re-generate.
 228
 229 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 230
 231         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 232         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 233         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 234         * i386-tbl.h: Re-generate.
 235
 236 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 237
 238         * i386-gen.c (struct template_arg, struct template_instance,
 239         struct template_param, struct template, templates,
 240         parse_template, expand_templates): New.
 241         (process_i386_opcodes): Various local variables moved to
 242         expand_templates. Call parse_template and expand_templates.
 243         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 244         * i386-tbl.h: Re-generate.
 245
 246 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 247
 248         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 249         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 250         register and memory source templates. Replace VexW= by VexW*
 251         where applicable.
 252         * i386-tbl.h: Re-generate.
 253
 254 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 255
 256         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 257         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 258         * i386-tbl.h: Re-generate.
 259
 260 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 261
 262         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 263         * i386-tbl.h: Re-generate.
 264
 265 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 266
 267         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 268         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 269         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 270         VexW0 on SSE2AVX variants.
 271         (vmovq): Drop NoRex64 from XMM/XMM variants.
 272         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 273         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 274         applicable use VexW0.
 275         * i386-tbl.h: Re-generate.
 276
 277 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 278
 279         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 280         * i386-opc.h (Rex64): Delete.
 281         (struct i386_opcode_modifier): Remove rex64 field.
 282         * i386-opc.tbl (crc32): Drop Rex64.
 283         Replace Rex64 with Size64 everywhere else.
 284         * i386-tbl.h: Re-generate.
 285
 286 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 287
 288         * i386-dis.c (OP_E_memory): Exclude recording of used address
 289         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 290         addressed memory operands for MPX insns.
 291
 292 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 293
 294         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 295         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 296         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 297         (ptwrite): Split into non-64-bit and 64-bit forms.
 298         * i386-tbl.h: Re-generate.
 299
 300 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 301
 302         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 303         template.
 304         * i386-tbl.h: Re-generate.
 305
 306 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 307
 308         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 309         (prefix_table): Move vmmcall here. Add vmgexit.
 310         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 311         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 312         (cpu_flags): Add CpuSEV_ES entry.
 313         * i386-opc.h (CpuSEV_ES): New.
 314         (union i386_cpu_flags): Add cpusev_es field.
 315         * i386-opc.tbl (vmgexit): New.
 316         * i386-init.h, i386-tbl.h: Re-generate.
 317
 318 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 319
 320         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 321         with MnemonicSize.
 322         * i386-opc.h (IGNORESIZE): New.
 323         (DEFAULTSIZE): Likewise.
 324         (IgnoreSize): Removed.
 325         (DefaultSize): Likewise.
 326         (MnemonicSize): New.
 327         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 328         mnemonicsize.
 329         * i386-opc.tbl (IgnoreSize): New.
 330         (DefaultSize): Likewise.
 331         * i386-tbl.h: Regenerated.
 332
 333 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 334
 335         PR 25627
 336         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 337         instructions.
 338
 339 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 340
 341         PR gas/25622
 342         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 343         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 344         * i386-tbl.h: Regenerated.
 345
 346 2020-02-26  Alan Modra  <amodra@gmail.com>
 347
 348         * aarch64-asm.c: Indent labels correctly.
 349         * aarch64-dis.c: Likewise.
 350         * aarch64-gen.c: Likewise.
 351         * aarch64-opc.c: Likewise.
 352         * alpha-dis.c: Likewise.
 353         * i386-dis.c: Likewise.
 354         * nds32-asm.c: Likewise.
 355         * nfp-dis.c: Likewise.
 356         * visium-dis.c: Likewise.
 357
 358 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 359
 360         * arc-regs.h (int_vector_base): Make it available for all ARC
 361         CPUs.
 362
 363 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 364
 365         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 366         changed.
 367
 368 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 369
 370         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 371         c.mv/c.li if rs1 is zero.
 372
 373 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 374
 375         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 376         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 377         CPU_POPCNT_FLAGS.
 378         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 379         * i386-opc.h (CpuABM): Removed.
 380         (CpuPOPCNT): New.
 381         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 382         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 383         popcnt.  Remove CpuABM from lzcnt.
 384         * i386-init.h: Regenerated.
 385         * i386-tbl.h: Likewise.
 386
 387 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 388
 389         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 390         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 391         VexW1 instead of open-coding them.
 392         * i386-tbl.h: Re-generate.
 393
 394 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 395
 396         * i386-opc.tbl (AddrPrefixOpReg): Define.
 397         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 398         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 399         templates. Drop NoRex64.
 400         * i386-tbl.h: Re-generate.
 401
 402 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 403
 404         PR gas/6518
 405         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 406         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 407         into Intel syntax instance (with Unpsecified) and AT&T one
 408         (without).
 409         (vcvtneps2bf16): Likewise, along with folding the two so far
 410         separate ones.
 411         * i386-tbl.h: Re-generate.
 412
 413 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 414
 415         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 416         CPU_ANY_SSE4A_FLAGS.
 417
 418 2020-02-17  Alan Modra  <amodra@gmail.com>
 419
 420         * i386-gen.c (cpu_flag_init): Correct last change.
 421
 422 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 423
 424         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 425         CPU_ANY_SSE4_FLAGS.
 426
 427 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 428
 429         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 430         (movzx): Likewise.
 431
 432 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 433
 434         PR gas/25438
 435         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 436         destination for Cpu64-only variant.
 437         (movzx): Fold patterns.
 438         * i386-tbl.h: Re-generate.
 439
 440 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 441
 442         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 443         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 444         CPU_ANY_SSE4_FLAGS entry.
 445         * i386-init.h: Re-generate.
 446
 447 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 448
 449         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 450         with Unspecified, making the present one AT&T syntax only.
 451         * i386-tbl.h: Re-generate.
 452
 453 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 454
 455         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 456         * i386-tbl.h: Re-generate.
 457
 458 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 459
 460         PR gas/24546
 461         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 462         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 463         Amd64 and Intel64 templates.
 464         (call, jmp): Likewise for far indirect variants. Dro
 465         Unspecified.
 466         * i386-tbl.h: Re-generate.
 467
 468 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 469
 470         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 471         * i386-opc.h (ShortForm): Delete.
 472         (struct i386_opcode_modifier): Remove shortform field.
 473         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 474         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 475         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 476         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 477         Drop ShortForm.
 478         * i386-tbl.h: Re-generate.
 479
 480 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 481
 482         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 483         fucompi): Drop ShortForm from operand-less templates.
 484         * i386-tbl.h: Re-generate.
 485
 486 2020-02-11  Alan Modra  <amodra@gmail.com>
 487
 488         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 489         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 490         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 491         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 492         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 493
 494 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 495
 496         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 497         (cde_opcodes): Add VCX* instructions.
 498
 499 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 500             Matthew Malcomson  <matthew.malcomson@arm.com>
 501
 502         * arm-dis.c (struct cdeopcode32): New.
 503         (CDE_OPCODE): New macro.
 504         (cde_opcodes): New disassembly table.
 505         (regnames): New option to table.
 506         (cde_coprocs): New global variable.
 507         (print_insn_cde): New
 508         (print_insn_thumb32): Use print_insn_cde.
 509         (parse_arm_disassembler_options): Parse coprocN args.
 510
 511 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 512
 513         PR gas/25516
 514         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 515         with ISA64.
 516         * i386-opc.h (AMD64): Removed.
 517         (Intel64): Likewose.
 518         (AMD64): New.
 519         (INTEL64): Likewise.
 520         (INTEL64ONLY): Likewise.
 521         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 522         * i386-opc.tbl (Amd64): New.
 523         (Intel64): Likewise.
 524         (Intel64Only): Likewise.
 525         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 526         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 527         * i386-tbl.h: Regenerated.
 528
 529 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 530
 531         PR 25469
 532         * z80-dis.c: Add support for GBZ80 opcodes.
 533
 534 2020-02-04  Alan Modra  <amodra@gmail.com>
 535
 536         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 537
 538 2020-02-03  Alan Modra  <amodra@gmail.com>
 539
 540         * m32c-ibld.c: Regenerate.
 541
 542 2020-02-01  Alan Modra  <amodra@gmail.com>
 543
 544         * frv-ibld.c: Regenerate.
 545
 546 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 547
 548         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 549         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 550         (OP_E_memory): Replace xmm_mdq_mode case label by
 551         vex_scalar_w_dq_mode one.
 552         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 553
 554 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 555
 556         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 557         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 558         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 559         (intel_operand_size): Drop vex_w_dq_mode case label.
 560
 561 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 562
 563         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 564         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 565
 566 2020-01-30  Alan Modra  <amodra@gmail.com>
 567
 568         * m32c-ibld.c: Regenerate.
 569
 570 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 571
 572         * bpf-opc.c: Regenerate.
 573
 574 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 575
 576         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 577         (dis386): Use them to replace C2/C3 table entries.
 578         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 579         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 580         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 581         * i386-tbl.h: Re-generate.
 582
 583 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 584
 585         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 586         forms.
 587         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 588         DefaultSize.
 589         * i386-tbl.h: Re-generate.
 590
 591 2020-01-30  Alan Modra  <amodra@gmail.com>
 592
 593         * tic4x-dis.c (tic4x_dp): Make unsigned.
 594
 595 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 596             Jan Beulich  <jbeulich@suse.com>
 597
 598         PR binutils/25445
 599         * i386-dis.c (MOVSXD_Fixup): New function.
 600         (movsxd_mode): New enum.
 601         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 602         (intel_operand_size): Handle movsxd_mode.
 603         (OP_E_register): Likewise.
 604         (OP_G): Likewise.
 605         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 606         register on movsxd.  Add movsxd with 16-bit destination register
 607         for AMD64 and Intel64 ISAs.
 608         * i386-tbl.h: Regenerated.
 609
 610 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 611
 612         PR 25403
 613         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 614         * aarch64-asm-2.c: Regenerate
 615         * aarch64-dis-2.c: Likewise.
 616         * aarch64-opc-2.c: Likewise.
 617
 618 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 619
 620         * i386-opc.tbl (sysret): Drop DefaultSize.
 621         * i386-tbl.h: Re-generate.
 622
 623 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 624
 625         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 626         Dword.
 627         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 628         * i386-tbl.h: Re-generate.
 629
 630 2020-01-20  Nick Clifton  <nickc@redhat.com>
 631
 632         * po/de.po: Updated German translation.
 633         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 634         * po/uk.po: Updated Ukranian translation.
 635
 636 2020-01-20  Alan Modra  <amodra@gmail.com>
 637
 638         * hppa-dis.c (fput_const): Remove useless cast.
 639
 640 2020-01-20  Alan Modra  <amodra@gmail.com>
 641
 642         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 643
 644 2020-01-18  Nick Clifton  <nickc@redhat.com>
 645
 646         * configure: Regenerate.
 647         * po/opcodes.pot: Regenerate.
 648
 649 2020-01-18  Nick Clifton  <nickc@redhat.com>
 650
 651         Binutils 2.34 branch created.
 652
 653 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 654
 655         * opintl.h: Fix spelling error (seperate).
 656
 657 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 658
 659         * i386-opc.tbl: Add {vex} pseudo prefix.
 660         * i386-tbl.h: Regenerated.
 661
 662 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 663
 664         PR 25376
 665         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 666         (neon_opcodes): Likewise.
 667         (select_arm_features): Make sure we enable MVE bits when selecting
 668         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 669         any architecture.
 670
 671 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 672
 673         * i386-opc.tbl: Drop stale comment from XOP section.
 674
 675 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 676
 677         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 678         (extractps): Add VexWIG to SSE2AVX forms.
 679         * i386-tbl.h: Re-generate.
 680
 681 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 682
 683         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 684         Size64 from and use VexW1 on SSE2AVX forms.
 685         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 686         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 687         * i386-tbl.h: Re-generate.
 688
 689 2020-01-15  Alan Modra  <amodra@gmail.com>
 690
 691         * tic4x-dis.c (tic4x_version): Make unsigned long.
 692         (optab, optab_special, registernames): New file scope vars.
 693         (tic4x_print_register): Set up registernames rather than
 694         malloc'd registertable.
 695         (tic4x_disassemble): Delete optable and optable_special.  Use
 696         optab and optab_special instead.  Throw away old optab,
 697         optab_special and registernames when info->mach changes.
 698
 699 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 700
 701         PR 25377
 702         * z80-dis.c (suffix): Use .db instruction to generate double
 703         prefix.
 704
 705 2020-01-14  Alan Modra  <amodra@gmail.com>
 706
 707         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 708         values to unsigned before shifting.
 709
 710 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 711
 712         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 713         flow instructions.
 714         (print_insn_thumb16, print_insn_thumb32): Likewise.
 715         (print_insn): Initialize the insn info.
 716         * i386-dis.c (print_insn): Initialize the insn info fields, and
 717         detect jumps.
 718
 719 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 720
 721         * arc-opc.c (C_NE): Make it required.
 722
 723 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 724
 725         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 726         reserved register name.
 727
 728 2020-01-13  Alan Modra  <amodra@gmail.com>
 729
 730         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 731         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 732
 733 2020-01-13  Alan Modra  <amodra@gmail.com>
 734
 735         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 736         result of wasm_read_leb128 in a uint64_t and check that bits
 737         are not lost when copying to other locals.  Use uint32_t for
 738         most locals.  Use PRId64 when printing int64_t.
 739
 740 2020-01-13  Alan Modra  <amodra@gmail.com>
 741
 742         * score-dis.c: Formatting.
 743         * score7-dis.c: Formatting.
 744
 745 2020-01-13  Alan Modra  <amodra@gmail.com>
 746
 747         * score-dis.c (print_insn_score48): Use unsigned variables for
 748         unsigned values.  Don't left shift negative values.
 749         (print_insn_score32): Likewise.
 750         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 751
 752 2020-01-13  Alan Modra  <amodra@gmail.com>
 753
 754         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 755
 756 2020-01-13  Alan Modra  <amodra@gmail.com>
 757
 758         * fr30-ibld.c: Regenerate.
 759
 760 2020-01-13  Alan Modra  <amodra@gmail.com>
 761
 762         * xgate-dis.c (print_insn): Don't left shift signed value.
 763         (ripBits): Formatting, use 1u.
 764
 765 2020-01-10  Alan Modra  <amodra@gmail.com>
 766
 767         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 768         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 769
 770 2020-01-10  Alan Modra  <amodra@gmail.com>
 771
 772         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 773         and XRREG value earlier to avoid a shift with negative exponent.
 774         * m10200-dis.c (disassemble): Similarly.
 775
 776 2020-01-09  Nick Clifton  <nickc@redhat.com>
 777
 778         PR 25224
 779         * z80-dis.c (ld_ii_ii): Use correct cast.
 780
 781 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 782
 783         PR 25224
 784         * z80-dis.c (ld_ii_ii): Use character constant when checking
 785         opcode byte value.
 786
 787 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 788
 789         * i386-dis.c (SEP_Fixup): New.
 790         (SEP): Define.
 791         (dis386_twobyte): Use it for sysenter/sysexit.
 792         (enum x86_64_isa): Change amd64 enumerator to value 1.
 793         (OP_J): Compare isa64 against intel64 instead of amd64.
 794         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 795         forms.
 796         * i386-tbl.h: Re-generate.
 797
 798 2020-01-08  Alan Modra  <amodra@gmail.com>
 799
 800         * z8k-dis.c: Include libiberty.h
 801         (instr_data_s): Make max_fetched unsigned.
 802         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 803         Don't exceed byte_info bounds.
 804         (output_instr): Make num_bytes unsigned.
 805         (unpack_instr): Likewise for nibl_count and loop.
 806         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 807         idx unsigned.
 808         * z8k-opc.h: Regenerate.
 809
 810 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 811
 812         * arc-tbl.h (llock): Use 'LLOCK' as class.
 813         (llockd): Likewise.
 814         (scond): Use 'SCOND' as class.
 815         (scondd): Likewise.
 816         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 817         (scondd): Likewise.
 818
 819 2020-01-06  Alan Modra  <amodra@gmail.com>
 820
 821         * m32c-ibld.c: Regenerate.
 822
 823 2020-01-06  Alan Modra  <amodra@gmail.com>
 824
 825         PR 25344
 826         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 827         Peek at next byte to prevent recursion on repeated prefix bytes.
 828         Ensure uninitialised "mybuf" is not accessed.
 829         (print_insn_z80): Don't zero n_fetch and n_used here,..
 830         (print_insn_z80_buf): ..do it here instead.
 831
 832 2020-01-04  Alan Modra  <amodra@gmail.com>
 833
 834         * m32r-ibld.c: Regenerate.
 835
 836 2020-01-04  Alan Modra  <amodra@gmail.com>
 837
 838         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 839
 840 2020-01-04  Alan Modra  <amodra@gmail.com>
 841
 842         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 843
 844 2020-01-04  Alan Modra  <amodra@gmail.com>
 845
 846         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 847
 848 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 849
 850         * aarch64-tbl.h (aarch64_opcode_table): Use
 851         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 852
 853 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 854
 855         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 856         forms of SUDOT and USDOT.
 857
 858 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 859
 860         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 861         uzip{1,2}.
 862         * opcodes/aarch64-dis-2.c: Re-generate.
 863
 864 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 865
 866         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 867         FMMLA encoding.
 868         * opcodes/aarch64-dis-2.c: Re-generate.
 869
 870 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 871
 872         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 873
 874 2020-01-01  Alan Modra  <amodra@gmail.com>
 875
 876         Update year range in copyright notice of all files.
 877
 878 For older changes see ChangeLog-2019
 879 \f
 880 Copyright (C) 2020 Free Software Foundation, Inc.
 881
 882 Copying and distribution of this file, with or without modification,
 883 are permitted in any medium without royalty provided the copyright
 884 notice and this notice are preserved.
 885
 886 Local Variables:
 887 mode: change-log
 888 left-margin: 8
 889 fill-column: 74
 890 version-control: never
 891 End: