opcodes/ChangeLog

   1 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
   2
   3         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
   4         for TLBI instruction.
   5
   6 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
   7
   8         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
   9         DC instruction.
  10
  11 2021-04-19  Jan Beulich  <jbeulich@suse.com>
  12
  13         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
  14         "qualifier".
  15         (convert_mov_to_movewide): Add initializer for "value".
  16
  17 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  18
  19         * aarch64-opc.c: Add RME system registers.
  20
  21 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
  22
  23         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
  24         "addi d,CV,z" to "c.mv d,CV".
  25
  26 2021-04-12  Alan Modra  <amodra@gmail.com>
  27
  28         * configure.ac (--enable-checking): Add support.
  29         * config.in: Regenerate.
  30         * configure: Regenerate.
  31
  32 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
  33
  34         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
  35         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
  36
  37 2021-04-09  Alan Modra  <amodra@gmail.com>
  38
  39         * ppc-dis.c (struct dis_private): Add "special".
  40         (POWERPC_DIALECT): Delete.  Replace uses with..
  41         (private_data): ..this.  New inline function.
  42         (disassemble_init_powerpc): Init "special" names.
  43         (skip_optional_operands): Add is_pcrel arg, set when detecting R
  44         field of prefix instructions.
  45         (bsearch_reloc, print_got_plt): New functions.
  46         (print_insn_powerpc): For pcrel instructions, print target address
  47         and symbol if known, and decode plt and got loads too.
  48
  49 2021-04-08  Alan Modra  <amodra@gmail.com>
  50
  51         PR 27684
  52         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
  53
  54 2021-04-08  Alan Modra  <amodra@gmail.com>
  55
  56         PR 27676
  57         * ppc-opc.c (DCBT_EO): Move earlier.
  58         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
  59         (powerpc_operands): Add THCT and THDS entries.
  60         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
  61
  62 2021-04-06  Alan Modra  <amodra@gmail.com>
  63
  64         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
  65         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
  66         symbol_at_address_func.
  67
  68 2021-04-05  Alan Modra  <amodra@gmail.com>
  69
  70         * configure.ac: Don't check for limits.h, string.h, strings.h or
  71         stdlib.h.
  72         (AC_ISC_POSIX): Don't invoke.
  73         * sysdep.h: Include stdlib.h and string.h unconditionally.
  74         * i386-opc.h: Include limits.h unconditionally.
  75         * wasm32-dis.c: Likewise.
  76         * cgen-opc.c: Don't include alloca-conf.h.
  77         * config.in: Regenerate.
  78         * configure: Regenerate.
  79
  80 2021-04-01  Martin Liska  <mliska@suse.cz>
  81
  82         * arm-dis.c (strneq): Remove strneq and use startswith.
  83         * cr16-dis.c (print_insn_cr16): Likewise.
  84         * score-dis.c (streq): Likewise.
  85         (strneq): Likewise.
  86         * score7-dis.c (strneq): Likewise.
  87
  88 2021-04-01  Alan Modra  <amodra@gmail.com>
  89
  90         PR 27675
  91         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
  92
  93 2021-03-31  Alan Modra  <amodra@gmail.com>
  94
  95         * sysdep.h (POISON_BFD_BOOLEAN): Define.
  96         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
  97         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
  98         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
  99         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 100         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 101         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 102         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 103         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 104         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 105         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 106         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 107         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 108         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 109         and TRUE with true throughout.
 110
 111 2021-03-31  Alan Modra  <amodra@gmail.com>
 112
 113         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 114         * aarch64-dis.h: Likewise.
 115         * aarch64-opc.c: Likewise.
 116         * avr-dis.c: Likewise.
 117         * csky-dis.c: Likewise.
 118         * nds32-asm.c: Likewise.
 119         * nds32-dis.c: Likewise.
 120         * nfp-dis.c: Likewise.
 121         * riscv-dis.c: Likewise.
 122         * s12z-dis.c: Likewise.
 123         * wasm32-dis.c: Likewise.
 124
 125 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 126
 127         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 128         (i386_seg_prefixes): New.
 129         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 130         (i386_seg_prefixes): Declare.
 131
 132 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 133
 134         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 135
 136 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 137
 138         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 139         * i386-reg.tbl (st): Move down.
 140         (st(0)): Delete. Extend comment.
 141         * i386-tbl.h: Re-generate.
 142
 143 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 144
 145         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 146         (cmpsd): Move next to cmps.
 147         (movsd): Move next to movs.
 148         (cmpxchg16b): Move to separate section.
 149         (fisttp, fisttpll): Likewise.
 150         (monitor, mwait): Likewise.
 151         * i386-tbl.h: Re-generate.
 152
 153 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 154
 155         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 156         (vpsadbw): Add C.
 157         * i386-tbl.h: Re-generate.
 158
 159 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 160
 161         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 162         pclmul, gfni): New templates. Use them wherever possible. Move
 163         SSE4.1 pextrw into respective section.
 164         * i386-tbl.h: Re-generate.
 165
 166 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 167
 168         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 169         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 170         "length".
 171         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 172         Convert all of their uses to representation in opcode.
 173
 174 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 175
 176         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 177         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 178         value of None. Shrink operands to 3 bits.
 179
 180 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 181
 182         * i386-gen.c (process_i386_opcode_modifier): New parameter
 183         "space".
 184         (output_i386_opcode): New local variable "space". Adjust
 185         process_i386_opcode_modifier() invocation.
 186         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 187         invocation.
 188         * i386-tbl.h: Re-generate.
 189
 190 2021-03-29  Alan Modra  <amodra@gmail.com>
 191
 192         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 193         (fp_qualifier_p, get_data_pattern): Likewise.
 194         (aarch64_get_operand_modifier_from_value): Likewise.
 195         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 196         (operand_variant_qualifier_p): Likewise.
 197         (qualifier_value_in_range_constraint_p): Likewise.
 198         (aarch64_get_qualifier_esize): Likewise.
 199         (aarch64_get_qualifier_nelem): Likewise.
 200         (aarch64_get_qualifier_standard_value): Likewise.
 201         (get_lower_bound, get_upper_bound): Likewise.
 202         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 203         (aarch64_print_operand): Likewise.
 204         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 205         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 206         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 207         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 208         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 209         (print_insn_tic6x): Likewise.
 210
 211 2021-03-29  Alan Modra  <amodra@gmail.com>
 212
 213         * arc-dis.c (extract_operand_value): Correct NULL cast.
 214         * frv-opc.h: Regenerate.
 215
 216 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 217
 218         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 219         MMX form.
 220         * i386-tbl.h: Re-generate.
 221
 222 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 223
 224         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 225         immediate in br.n instruction.
 226
 227 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 228
 229         * i386-dis.c (XMGatherD, VexGatherD): New.
 230         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 231         (print_insn): Check masking for S/G insns.
 232         (OP_E_memory): New local variable check_gather. Extend mandatory
 233         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 234         Extend check for disallowed 16-bit addressing.
 235         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 236         if()s to switch(). Check register conflicts for (VEX-encoded)
 237         gathers. Drop no longer reachable cases.
 238         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 239         vgatherdp*.
 240
 241 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 242
 243         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 244         zeroing-masking without masking.
 245
 246 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 247
 248         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 249         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 250         single-operand forms as deprecated.
 251         * i386-tbl.h: Re-generate.
 252
 253 2021-03-25  Alan Modra  <amodra@gmail.com>
 254
 255         PR 27647
 256         * ppc-opc.c (XLOCB_MASK): Delete.
 257         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 258         XLBH_MASK.
 259         (powerpc_opcodes): Accept a BH field on all extended forms of
 260         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 261
 262 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 263
 264         * i386-gen.c (output_i386_opcode): Drop processing of
 265         opcode_length. Calculate length from base_opcode. Adjust prefix
 266         encoding determination.
 267         (process_i386_opcodes): Drop output of fake opcode_length.
 268         * i386-opc.h (struct insn_template): Drop opcode_length field.
 269         * i386-opc.tbl: Drop opcode length field from all templates.
 270         * i386-tbl.h: Re-generate.
 271
 272 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 273
 274         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 275         parameter "prefix". Drop local variable "regular_encoding".
 276         Record prefix setting / check for consistency.
 277         (output_i386_opcode): Parse opcode_length and base_opcode
 278         earlier. Derive prefix encoding. Drop no longer applicable
 279         consistency checking. Adjust process_i386_opcode_modifier()
 280         invocation.
 281         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 282         invocation.
 283         * i386-tbl.h: Re-generate.
 284
 285 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 286
 287         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 288         check.
 289         * i386-opc.h (Prefix_*): Move #define-s.
 290         * i386-opc.tbl: Move pseudo prefix enumerator values to
 291         extension opcode field. Introduce pseudopfx template.
 292         * i386-tbl.h: Re-generate.
 293
 294 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 295
 296         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 297         comment.
 298         * i386-tbl.h: Re-generate.
 299
 300 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 301
 302         * i386-opc.h (struct insn_template): Move cpu_flags field past
 303         opcode_modifier one.
 304         * i386-tbl.h: Re-generate.
 305
 306 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 307
 308         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 309         * i386-opc.h (OpcodeSpace): New enumerator.
 310         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 311         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 312         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 313         (struct i386_opcode_modifier): New field opcodespace. Shrink
 314         opcodeprefix field.
 315         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 316         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 317         OpcodePrefix uses.
 318         * i386-tbl.h: Re-generate.
 319
 320 2021-03-22  Martin Liska  <mliska@suse.cz>
 321
 322         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 323         * arc-dis.c (parse_option): Likewise.
 324         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 325         * cris-dis.c (print_with_operands): Likewise.
 326         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 327         * i386-dis.c (print_insn): Likewise.
 328         * ia64-gen.c (fetch_insn_class): Likewise.
 329         (parse_resource_users): Likewise.
 330         (in_iclass): Likewise.
 331         (lookup_specifier): Likewise.
 332         (insert_opcode_dependencies): Likewise.
 333         * mips-dis.c (parse_mips_ase_option): Likewise.
 334         (parse_mips_dis_option): Likewise.
 335         * s390-dis.c (disassemble_init_s390): Likewise.
 336         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 337
 338 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 339
 340         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 341
 342 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 343
 344         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 345         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 346
 347 2021-03-12  Alan Modra  <amodra@gmail.com>
 348
 349         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 350
 351 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 352
 353         * i386-dis.c (OP_XMM): Re-order checks.
 354
 355 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 356
 357         * i386-dis.c (putop): Drop need_vex check when also checking
 358         vex.evex.
 359         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 360         checking vex.b.
 361
 362 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 363
 364         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 365         checks. Move case label past broadcast check.
 366
 367 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 368
 369         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 370         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 371         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 372         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 373         EVEX_W_0F38C7_M_0_L_2): Delete.
 374         (REG_EVEX_0F38C7_M_0_L_2): New.
 375         (intel_operand_size): Handle VEX and EVEX the same for
 376         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 377         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 378         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 379         vex_vsib_q_w_d_mode uses.
 380         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 381         0F38A1, and 0F38A3 entries.
 382         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 383         entry.
 384         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 385         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 386         0F38A3 entries.
 387
 388 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 389
 390         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 391         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 392         MOD_VEX_0FXOP_09_12): Rename to ...
 393         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 394         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 395         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 396         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 397         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 398         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 399         (reg_table): Adjust comments.
 400         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 401         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 402         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 403         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 404         (vex_len_table): Adjust opcode 0A_12 entry.
 405         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 406         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 407         (rm_table): Move hreset entry.
 408
 409 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 410
 411         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 412         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 413         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 414         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 415         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 416         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 417         (get_valid_dis386): Also handle 512-bit vector length when
 418         vectoring into vex_len_table[].
 419         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 420         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 421         entries.
 422         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 423         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 424         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 425         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 426         entries.
 427
 428 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 429
 430         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 431         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 432         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 433         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 434         entries.
 435         * i386-dis-evex-len.h (evex_len_table): Likewise.
 436         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 437
 438 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 439
 440         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 441         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 442         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 443         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 444         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 445         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 446         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 447         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 448         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 449         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 450         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 451         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 452         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 453         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 454         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 455         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 456         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 457         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 458         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 459         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 460         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 461         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 462         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 463         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 464         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 465         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 466         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 467         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 468         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 469         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 470         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 471         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 472         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 473         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 474         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 475         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 476         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 477         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 478         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 479         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 480         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 481         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 482         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 483         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 484         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 485         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 486         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 487         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 488         EVEX_W_0F3A43_L_n): New.
 489         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 490         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 491         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 492         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 493         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 494         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 495         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 496         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 497         0F385B, 0F38C6, and 0F38C7 entries.
 498         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 499         0F38C6 and 0F38C7.
 500         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 501         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 502         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 503         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 504
 505 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 506
 507         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 508         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 509         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 510         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 511         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 512         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 513         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 514         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 515         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 516         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 517         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 518         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 519         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 520         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 521         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 522         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 523         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 524         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 525         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 526         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 527         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 528         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 529         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 530         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 531         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 532         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 533         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 534         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 535         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 536         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 537         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 538         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 539         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 540         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 541         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 542         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 543         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 544         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 545         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 546         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 547         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 548         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 549         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 550         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 551         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 552         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 553         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 554         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 555         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 556         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 557         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 558         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 559         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 560         VEX_W_0F99_P_2_LEN_0): Delete.
 561         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 562         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 563         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 564         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 565         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 566         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 567         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 568         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 569         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 570         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 571         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 572         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 573         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 574         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 575         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 576         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 577         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 578         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 579         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 580         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 581         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 582         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 583         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 584         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 585         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 586         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 587         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 588         (prefix_table): No longer link to vex_len_table[] for opcodes
 589         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 590         0F92, 0F93, 0F98, and 0F99.
 591         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 592         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 593         0F98, and 0F99.
 594         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 595         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 596         0F98, and 0F99.
 597         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 598         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 599         0F98, and 0F99.
 600         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 601         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 602         0F98, and 0F99.
 603
 604 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 605
 606         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 607         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 608         REG_VEX_0F73_M_0 respectively.
 609         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 610         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 611         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 612         MOD_VEX_0F73_REG_7): Delete.
 613         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 614         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 615         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 616         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 617         PREFIX_VEX_0F3AF0_L_0 respectively.
 618         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 619         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 620         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 621         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 622         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 623         VEX_LEN_0F38F7): New.
 624         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 625         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 626         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 627         0F38F3.
 628         (prefix_table): No longer link to vex_len_table[] for opcodes
 629         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 630         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 631         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 632         0F38F6, 0F38F7, and 0F3AF0.
 633         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 634         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 635         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 636         0F73.
 637
 638 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 639
 640         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 641         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 642         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 643         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 644         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 645         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 646         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 647         73.
 648         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 649         0F72, and 0F73.
 650         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 651         0F73.
 652
 653 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 654
 655         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 656         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 657         (reg_table): Don't link to mod_table[] where not needed. Add
 658         PREFIX_IGNORED to nop entries.
 659         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 660         (mod_table): Add nop entries next to prefetch ones. Drop
 661         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 662         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 663         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 664         PREFIX_OPCODE from endbr* entries.
 665         (get_valid_dis386): Also consider entry's name when zapping
 666         vindex.
 667         (print_insn): Handle PREFIX_IGNORED.
 668
 669 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 670
 671         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 672         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 673         element.
 674         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 675         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 676         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 677         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 678         (struct i386_opcode_modifier): Delete notrackprefixok,
 679         islockable, hleprefixok, and repprefixok fields. Add prefixok
 680         field.
 681         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 682         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 683         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 684         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 685         Replace HLEPrefixOk.
 686         * opcodes/i386-tbl.h: Re-generate.
 687
 688 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 689
 690         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 691         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 692         64-bit form.
 693         * opcodes/i386-tbl.h: Re-generate.
 694
 695 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 696
 697         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 698         for {} instead of {0}. Don't look for '0'.
 699         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 700         size specifiers.
 701
 702 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 703
 704         PR 27158
 705         * riscv-dis.c (print_insn_args): Updated encoding macros.
 706         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 707         (match_c_addi16sp): Updated encoding macros.
 708         (match_c_lui): Likewise.
 709         (match_c_lui_with_hint): Likewise.
 710         (match_c_addi4spn): Likewise.
 711         (match_c_slli): Likewise.
 712         (match_slli_as_c_slli): Likewise.
 713         (match_c_slli64): Likewise.
 714         (match_srxi_as_c_srxi): Likewise.
 715         (riscv_insn_types): Added .insn css/cl/cs.
 716
 717 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 718
 719         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 720         (default_priv_spec): Updated type to riscv_spec_class.
 721         (parse_riscv_dis_option): Updated.
 722         * riscv-opc.c: Moved stuff and make the file tidy.
 723
 724 2021-02-17  Alan Modra  <amodra@gmail.com>
 725
 726         * wasm32-dis.c: Include limits.h.
 727         (CHAR_BIT): Provide backup define.
 728         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 729         Correct signed overflow checking.
 730
 731 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 732
 733         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 734         * i386-tbl.h: Re-generate.
 735
 736 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 737
 738         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 739         Oword.
 740         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 741
 742 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 743
 744         * s390-mkopc.c (main): Accept arch14 as cpu string.
 745         * s390-opc.txt: Add new arch14 instructions.
 746
 747 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 748
 749         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 750         favour of LIBINTL.
 751         * configure: Regenerated.
 752
 753 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 754
 755         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 756         * tic54x-opc.c (regs): Rename to ...
 757         (tic54x_regs): ... this.
 758         (mmregs): Rename to ...
 759         (tic54x_mmregs): ... this.
 760         (condition_codes): Rename to ...
 761         (tic54x_condition_codes): ... this.
 762         (cc2_codes): Rename to ...
 763         (tic54x_cc2_codes): ... this.
 764         (cc3_codes): Rename to ...
 765         (tic54x_cc3_codes): ... this.
 766         (status_bits): Rename to ...
 767         (tic54x_status_bits): ... this.
 768         (misc_symbols): Rename to ...
 769         (tic54x_misc_symbols): ... this.
 770
 771 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 772
 773         * riscv-opc.c (MASK_RVB_IMM): Removed.
 774         (riscv_opcodes): Removed zb* instructions.
 775         (riscv_ext_version_table): Removed versions for zb*.
 776
 777 2021-01-26  Alan Modra  <amodra@gmail.com>
 778
 779         * i386-gen.c (parse_template): Ensure entire template_instance
 780         is initialised.
 781
 782 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 783
 784         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 785         (riscv_fpr_names_abi): Likewise.
 786         (riscv_opcodes): Likewise.
 787         (riscv_insn_types): Likewise.
 788
 789 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 790
 791         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 792
 793 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 794
 795         * riscv-dis.c: Comments tidy and improvement.
 796         * riscv-opc.c: Likewise.
 797
 798 2021-01-13  Alan Modra  <amodra@gmail.com>
 799
 800         * Makefile.in: Regenerate.
 801
 802 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 803
 804         PR binutils/26792
 805         * configure.ac: Use GNU_MAKE_JOBSERVER.
 806         * aclocal.m4: Regenerated.
 807         * configure: Likewise.
 808
 809 2021-01-12  Nick Clifton  <nickc@redhat.com>
 810
 811         * po/sr.po: Updated Serbian translation.
 812
 813 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 814
 815         PR ld/27173
 816         * configure: Regenerated.
 817
 818 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 819
 820         * aarch64-asm-2.c: Regenerate.
 821         * aarch64-dis-2.c: Likewise.
 822         * aarch64-opc-2.c: Likewise.
 823         * aarch64-opc.c (aarch64_print_operand):
 824         Delete handling of AARCH64_OPND_CSRE_CSR.
 825         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 826         (CSRE): Likewise.
 827         (_CSRE_INSN): Likewise.
 828         (aarch64_opcode_table): Delete csr.
 829
 830 2021-01-11  Nick Clifton  <nickc@redhat.com>
 831
 832         * po/de.po: Updated German translation.
 833         * po/fr.po: Updated French translation.
 834         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 835         * po/sv.po: Updated Swedish translation.
 836         * po/uk.po: Updated Ukranian translation.
 837
 838 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 839
 840         * configure: Regenerated.
 841
 842 2021-01-09  Nick Clifton  <nickc@redhat.com>
 843
 844         * configure: Regenerate.
 845         * po/opcodes.pot: Regenerate.
 846
 847 2021-01-09  Nick Clifton  <nickc@redhat.com>
 848
 849         * 2.36 release branch crated.
 850
 851 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 852
 853         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 854         (DW, (XRC_MASK): Define.
 855         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 856
 857 2021-01-09  Alan Modra  <amodra@gmail.com>
 858
 859         * configure: Regenerate.
 860
 861 2021-01-08  Nick Clifton  <nickc@redhat.com>
 862
 863         * po/sv.po: Updated Swedish translation.
 864
 865 2021-01-08  Nick Clifton  <nickc@redhat.com>
 866
 867         PR 27129
 868         * aarch64-dis.c (determine_disassembling_preference): Move call to
 869         aarch64_match_operands_constraint outside of the assertion.
 870         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 871         Replace with a return of FALSE.
 872
 873         PR 27139
 874         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 875         core system register.
 876
 877 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 878
 879         * configure: Regenerate.
 880
 881 2021-01-07  Nick Clifton  <nickc@redhat.com>
 882
 883         * po/fr.po: Updated French translation.
 884
 885 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 886
 887         * m68k-opc.c (chkl): Change minimum architecture requirement to
 888         m68020.
 889
 890 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 891
 892         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 893
 894 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 895             Jim Wilson  <jimw@sifive.com>
 896             Andrew Waterman  <andrew@sifive.com>
 897             Maxim Blinov  <maxim.blinov@embecosm.com>
 898             Kito Cheng  <kito.cheng@sifive.com>
 899             Nelson Chu  <nelson.chu@sifive.com>
 900
 901         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
 902         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 903
 904 2021-01-01  Alan Modra  <amodra@gmail.com>
 905
 906         Update year range in copyright notice of all files.
 907
 908 For older changes see ChangeLog-2020
 909 \f
 910 Copyright (C) 2021 Free Software Foundation, Inc.
 911
 912 Copying and distribution of this file, with or without modification,
 913 are permitted in any medium without royalty provided the copyright
 914 notice and this notice are preserved.
 915
 916 Local Variables:
 917 mode: change-log
 918 left-margin: 8
 919 fill-column: 74
 920 version-control: never
 921 End: