1 2020-07-14 Jan Beulich <jbeulich@suse.com>
3 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
4 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
5 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
6 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
7 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
8 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
9 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
10 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
11 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
12 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
13 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
14 (reg_table, prefix_table, three_byte_table, vex_table,
15 vex_len_table, mod_table, rm_table): Replace / remove respective
17 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
18 of PREFIX_DATA in used_prefixes.
20 2020-07-14 Jan Beulich <jbeulich@suse.com>
22 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
23 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
24 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
25 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
26 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
27 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
28 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
29 VEX_W_0F3A33_L_0): Delete.
30 (dis386): Adjust "BW" description.
31 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
32 0F3A31, 0F3A32, and 0F3A33.
33 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
35 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
38 2020-07-14 Jan Beulich <jbeulich@suse.com>
40 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
41 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
42 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
43 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
44 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
45 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
46 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
47 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
48 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
49 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
50 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
51 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
52 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
53 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
54 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
55 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
56 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
57 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
58 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
59 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
60 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
61 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
62 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
63 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
64 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
65 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
66 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
67 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
68 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
69 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
70 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
71 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
72 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
73 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
74 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
75 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
76 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
77 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
78 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
79 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
80 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
81 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
82 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
83 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
84 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
85 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
86 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
87 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
88 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
89 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
90 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
91 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
92 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
93 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
94 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
95 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
96 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
97 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
98 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
99 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
100 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
101 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
102 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
103 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
104 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
105 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
106 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
107 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
108 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
109 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
110 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
111 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
112 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
113 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
114 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
115 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
116 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
117 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
118 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
119 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
120 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
121 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
122 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
123 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
124 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
125 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
126 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
127 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
128 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
129 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
130 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
131 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
132 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
133 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
134 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
135 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
136 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
137 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
138 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
139 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
140 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
141 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
142 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
143 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
144 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
145 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
146 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
147 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
148 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
149 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
150 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
151 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
152 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
153 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
154 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
155 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
156 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
157 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
158 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
159 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
160 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
161 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
162 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
163 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
164 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
165 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
166 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
167 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
168 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
169 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
170 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
171 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
172 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
173 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
174 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
175 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
176 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
177 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
178 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
179 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
180 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
181 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
182 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
183 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
184 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
185 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
186 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
187 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
188 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
189 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
190 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
191 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
192 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
193 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
194 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
195 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
196 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
197 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
198 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
199 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
200 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
201 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
202 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
203 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
204 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
205 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
206 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
207 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
208 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
209 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
210 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
211 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
212 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
213 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
214 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
215 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
216 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
217 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
218 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
219 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
220 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
221 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
222 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
223 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
224 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
225 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
226 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
227 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
228 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
229 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
230 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
231 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
232 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
233 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
234 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
235 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
236 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
237 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
238 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
239 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
240 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
241 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
242 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
243 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
244 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
245 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
246 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
247 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
248 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
249 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
250 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
251 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
252 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
253 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
254 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
255 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
256 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
257 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
258 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
259 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
260 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
261 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
262 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
263 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
264 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
265 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
266 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
267 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
268 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
269 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
270 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
271 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
272 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
273 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
274 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
275 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
276 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
277 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
278 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
279 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
280 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
281 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
282 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
283 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
284 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
285 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
286 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
287 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
288 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
289 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
290 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
291 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
292 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
293 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
294 EVEX_W_0F3A72_P_2): Rename to ...
295 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
296 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
297 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
298 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
299 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
300 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
301 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
302 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
303 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
304 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
305 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
306 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
307 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
308 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
309 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
310 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
311 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
312 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
313 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
314 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
315 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
316 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
317 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
318 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
319 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
320 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
321 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
322 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
323 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
324 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
325 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
326 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
327 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
328 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
329 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
330 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
331 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
332 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
333 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
334 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
335 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
336 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
337 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
338 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
339 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
340 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
341 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
342 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
343 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
344 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
345 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
346 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
347 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
348 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
349 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
350 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
351 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
352 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
353 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
354 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
355 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
356 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
357 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
358 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
359 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
360 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
361 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
362 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
363 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
364 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
365 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
366 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
368 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
369 vex_w_table, mod_table): Replace / remove respective entries.
370 (print_insn): Move up dp->prefix_requirement handling. Handle
372 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
373 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
374 Replace / remove respective entries.
376 2020-07-14 Jan Beulich <jbeulich@suse.com>
378 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
379 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
380 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
381 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
382 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
384 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
385 0F2C, 0F2D, 0F2E, and 0F2F.
386 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
389 2020-07-14 Jan Beulich <jbeulich@suse.com>
391 * i386-dis.c (OP_VexR, VexScalarR): New.
392 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
393 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
394 need_vex_reg): Delete.
395 (prefix_table): Replace VexScalar by VexScalarR and
396 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
397 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
398 (vex_len_table): Replace EXqVexScalarS by EXqS.
399 (get_valid_dis386): Don't set need_vex_reg.
400 (print_insn): Don't initialize need_vex_reg.
401 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
402 q_scalar_swap_mode cases.
403 (OP_EX): Don't check for d_scalar_swap_mode and
405 (OP_VEX): Done check need_vex_reg.
406 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
407 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
408 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
410 2020-07-14 Jan Beulich <jbeulich@suse.com>
412 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
413 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
414 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
415 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
416 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
417 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
418 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
419 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
420 (vex_table): Replace Vex128 by Vex.
421 (vex_len_table): Likewise. Adjust referenced enum names.
422 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
423 referenced enum names.
424 (OP_VEX): Drop vex128_mode and vex256_mode cases.
425 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
427 2020-07-14 Jan Beulich <jbeulich@suse.com>
429 * i386-dis.c (dis386): "LW" description now applies to "DQ".
430 (putop): Handle "DQ". Don't handle "LW" anymore.
431 (prefix_table, mod_table): Replace %LW by %DQ.
432 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
434 2020-07-14 Jan Beulich <jbeulich@suse.com>
436 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
437 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
438 d_scalar_swap_mode case handling. Move shift adjsutment into
439 the case its applicable to.
441 2020-07-14 Jan Beulich <jbeulich@suse.com>
443 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
444 (EXbScalar, EXwScalar): Fold to ...
445 (EXbwUnit): ... this.
446 (b_scalar_mode, w_scalar_mode): Fold to ...
447 (bw_unit_mode): ... this.
448 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
449 w_scalar_mode handling by bw_unit_mode one.
450 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
452 * i386-dis-evex-prefix.h: ... here.
454 2020-07-14 Jan Beulich <jbeulich@suse.com>
456 * i386-dis.c (PCMPESTR_Fixup): Delete.
457 (dis386): Adjust "LQ" description.
458 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
459 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
460 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
461 vpcmpestrm, and vpcmpestri.
462 (putop): Honor "cond" when handling LQ.
463 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
464 vcvtsi2ss and vcvtusi2ss.
465 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
466 vcvtsi2sd and vcvtusi2sd.
468 2020-07-14 Jan Beulich <jbeulich@suse.com>
470 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
471 (simd_cmp_op): Add const.
472 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
473 (CMP_Fixup): Handle VEX case.
474 (prefix_table): Replace VCMP by CMP.
475 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
477 2020-07-14 Jan Beulich <jbeulich@suse.com>
479 * i386-dis.c (MOVBE_Fixup): Delete.
481 (prefix_table): Use Mv for movbe entries.
483 2020-07-14 Jan Beulich <jbeulich@suse.com>
485 * i386-dis.c (CRC32_Fixup): Delete.
486 (prefix_table): Use Eb/Ev for crc32 entries.
488 2020-07-14 Jan Beulich <jbeulich@suse.com>
490 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
491 Conditionalize invocations of "USED_REX (0)".
493 2020-07-14 Jan Beulich <jbeulich@suse.com>
495 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
496 CH, DH, BH, AX, DX): Delete.
497 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
498 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
499 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
501 2020-07-10 Lili Cui <lili.cui@intel.com>
503 * i386-dis.c (TMM): New.
506 (MVexSIBMEM): Likewise.
507 (tmm_mode): Likewise.
508 (vex_sibmem_mode): Likewise.
509 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
510 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
511 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
512 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
513 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
514 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
515 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
516 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
517 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
518 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
519 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
520 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
521 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
522 (PREFIX_VEX_0F3849_X86_64): Likewise.
523 (PREFIX_VEX_0F384B_X86_64): Likewise.
524 (PREFIX_VEX_0F385C_X86_64): Likewise.
525 (PREFIX_VEX_0F385E_X86_64): Likewise.
526 (X86_64_VEX_0F3849): Likewise.
527 (X86_64_VEX_0F384B): Likewise.
528 (X86_64_VEX_0F385C): Likewise.
529 (X86_64_VEX_0F385E): Likewise.
530 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
531 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
532 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
533 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
534 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
535 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
536 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
537 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
538 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
539 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
540 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
541 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
542 (VEX_W_0F3849_X86_64_P_0): Likewise.
543 (VEX_W_0F3849_X86_64_P_2): Likewise.
544 (VEX_W_0F3849_X86_64_P_3): Likewise.
545 (VEX_W_0F384B_X86_64_P_1): Likewise.
546 (VEX_W_0F384B_X86_64_P_2): Likewise.
547 (VEX_W_0F384B_X86_64_P_3): Likewise.
548 (VEX_W_0F385C_X86_64_P_1): Likewise.
549 (VEX_W_0F385E_X86_64_P_0): Likewise.
550 (VEX_W_0F385E_X86_64_P_1): Likewise.
551 (VEX_W_0F385E_X86_64_P_2): Likewise.
552 (VEX_W_0F385E_X86_64_P_3): Likewise.
553 (names_tmm): Likewise.
554 (att_names_tmm): Likewise.
555 (intel_operand_size): Handle void_mode.
556 (OP_XMM): Handle tmm_mode.
559 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
560 CpuAMX_BF16 and CpuAMX_TILE.
561 (operand_type_shorthands): Add RegTMM.
562 (operand_type_init): Likewise.
563 (operand_types): Add Tmmword.
564 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
565 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
566 * i386-opc.h (CpuAMX_INT8): New.
567 (CpuAMX_BF16): Likewise.
568 (CpuAMX_TILE): Likewise.
571 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
572 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
573 (i386_operand_type): Add tmmword.
574 * i386-opc.tbl: Add AMX instructions.
575 * i386-reg.tbl: Add AMX registers.
576 * i386-init.h: Regenerated.
577 * i386-tbl.h: Likewise.
579 2020-07-08 Jan Beulich <jbeulich@suse.com>
581 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
582 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
584 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
585 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
587 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
588 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
589 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
590 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
591 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
592 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
593 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
594 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
595 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
596 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
597 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
598 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
599 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
600 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
601 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
602 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
603 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
604 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
605 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
606 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
607 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
608 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
609 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
610 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
611 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
612 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
613 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
614 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
615 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
616 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
617 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
618 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
619 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
620 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
621 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
622 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
623 (reg_table): Re-order XOP entries. Adjust their operands.
624 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
625 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
626 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
627 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
628 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
629 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
630 entries by references ...
631 (vex_len_table): ... to resepctive new entries here. For several
632 new and existing entries reference ...
633 (vex_w_table): ... new entries here.
634 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
636 2020-07-08 Jan Beulich <jbeulich@suse.com>
638 * i386-dis.c (XMVexScalarI4): Define.
639 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
640 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
641 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
642 (vex_len_table): Move scalar FMA4 entries ...
643 (prefix_table): ... here.
644 (OP_REG_VexI4): Handle scalar_mode.
645 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
646 * i386-tbl.h: Re-generate.
648 2020-07-08 Jan Beulich <jbeulich@suse.com>
650 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
652 (OP_VexW, VexW): New.
653 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
654 for shifts and rotates by register.
656 2020-07-08 Jan Beulich <jbeulich@suse.com>
658 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
659 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
660 OP_EX_VexReg): Delete.
661 (OP_VexI4, VexI4): New.
662 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
663 (prefix_table): ... here.
664 (print_insn): Drop setting of vex_w_done.
666 2020-07-08 Jan Beulich <jbeulich@suse.com>
668 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
669 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
670 (xop_table): Replace operands of 4-operand insns.
671 (OP_REG_VexI4): Move VEX.W based operand swaping here.
673 2020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
675 * arc-opc.c (insert_rbd): New function.
678 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
681 2020-07-07 Jan Beulich <jbeulich@suse.com>
683 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
684 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
685 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
686 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
688 (putop): Handle "BW".
689 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
690 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
692 * i386-dis-evex-prefix.h: ... here.
694 2020-07-06 Jan Beulich <jbeulich@suse.com>
696 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
697 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
698 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
699 VEX_W_0FXOP_09_83): New enumerators.
700 (xop_table): Reference the above.
701 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
702 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
703 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
704 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
706 2020-07-06 Jan Beulich <jbeulich@suse.com>
708 * i386-dis.c (EVEX_W_0F3838_P_1,
709 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
710 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
711 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
712 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
713 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
714 (putop): Centralize management of last[]. Delete SAVE_LAST.
715 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
716 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
717 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
718 * i386-dis-evex-prefix.h: here.
720 2020-07-06 Jan Beulich <jbeulich@suse.com>
722 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
723 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
724 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
725 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
727 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
728 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
729 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
730 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
731 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
732 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
733 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
734 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
736 * i386-dis-evex-len.h: Adjust comments.
737 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
738 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
739 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
740 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
741 MOD_EVEX_0F385B_P_2_W_1 table entries.
742 * i386-dis-evex-w.h: Reference mod_table[] for
743 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
746 2020-07-06 Jan Beulich <jbeulich@suse.com>
748 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
749 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
751 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
752 Likewise. Mark 256-bit entries invalid.
754 2020-07-06 Jan Beulich <jbeulich@suse.com>
756 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
757 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
758 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
759 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
760 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
761 PREFIX_EVEX_0F382B): Delete.
762 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
763 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
764 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
765 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
766 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
768 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
769 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
770 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
771 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
773 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
774 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
775 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
776 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
777 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
778 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
779 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
780 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
781 PREFIX_EVEX_0F382B): Remove table entries.
782 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
783 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
784 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
786 2020-07-06 Jan Beulich <jbeulich@suse.com>
788 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
789 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
791 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
792 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
793 EVEX_LEN_0F3A01_P_2_W_1 table entries.
794 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
797 2020-07-06 Jan Beulich <jbeulich@suse.com>
799 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
800 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
801 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
802 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
803 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
804 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
805 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
806 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
807 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
810 2020-07-06 Jan Beulich <jbeulich@suse.com>
812 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
813 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
814 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
816 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
818 * i386-dis-evex.h (evex_table): Reference VEX table entry for
820 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
822 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
824 2020-07-06 Jan Beulich <jbeulich@suse.com>
826 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
827 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
828 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
829 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
830 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
831 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
832 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
833 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
834 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
835 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
836 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
837 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
838 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
839 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
840 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
841 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
842 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
843 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
844 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
845 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
846 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
847 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
848 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
849 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
850 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
851 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
852 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
853 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
854 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
855 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
856 (prefix_table): Add EXxEVexR to FMA table entries.
857 (OP_Rounding): Move abort() invocation.
858 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
859 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
860 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
861 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
862 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
863 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
864 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
865 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
866 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
867 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
869 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
870 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
871 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
872 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
873 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
874 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
875 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
876 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
877 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
878 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
879 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
880 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
881 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
882 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
883 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
884 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
885 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
886 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
887 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
888 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
889 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
890 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
891 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
892 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
893 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
894 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
895 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
896 Delete table entries.
897 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
898 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
899 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
902 2020-07-06 Jan Beulich <jbeulich@suse.com>
904 * i386-dis.c (EXqScalarS): Delete.
905 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
906 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
908 2020-07-06 Jan Beulich <jbeulich@suse.com>
910 * i386-dis.c (safe-ctype.h): Include.
911 (EXdScalar, EXqScalar): Delete.
912 (d_scalar_mode, q_scalar_mode): Delete.
913 (prefix_table, vex_len_table): Use EXxmm_md in place of
914 EXdScalar and EXxmm_mq in place of EXqScalar.
915 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
916 d_scalar_mode and q_scalar_mode.
917 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
918 (vmovsd): Use EXxmm_mq.
920 2020-07-06 Yuri Chornoivan <yurchor@ukr.net>
923 * arc-dis.c: Fix spelling mistake.
924 * po/opcodes.pot: Regenerate.
926 2020-07-06 Nick Clifton <nickc@redhat.com>
928 * po/pt_BR.po: Updated Brazilian Portugugese translation.
929 * po/uk.po: Updated Ukranian translation.
931 2020-07-04 Nick Clifton <nickc@redhat.com>
933 * configure: Regenerate.
934 * po/opcodes.pot: Regenerate.
936 2020-07-04 Nick Clifton <nickc@redhat.com>
938 Binutils 2.35 branch created.
940 2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
942 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
943 * i386-opc.h (VexSwapSources): New.
944 (i386_opcode_modifier): Add vexswapsources.
945 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
946 with two source operands swapped.
947 * i386-tbl.h: Regenerated.
949 2020-06-30 Nelson Chu <nelson.chu@sifive.com>
951 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
952 unprivileged CSR can also be initialized.
954 2020-06-29 Alan Modra <amodra@gmail.com>
956 * arm-dis.c: Use C style comments.
957 * cr16-opc.c: Likewise.
958 * ft32-dis.c: Likewise.
959 * moxie-opc.c: Likewise.
960 * tic54x-dis.c: Likewise.
961 * s12z-opc.c: Remove useless comment.
962 * xgate-dis.c: Likewise.
964 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
966 * i386-opc.tbl: Add a blank line.
968 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
970 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
971 (VecSIB128): Renamed to ...
973 (VecSIB256): Renamed to ...
975 (VecSIB512): Renamed to ...
977 (VecSIB): Renamed to ...
979 (i386_opcode_modifier): Replace vecsib with sib.
980 * i386-opc.tbl (VecSIB128): New.
981 (VecSIB256): Likewise.
982 (VecSIB512): Likewise.
983 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
984 and VecSIB512, respectively.
986 2020-06-26 Jan Beulich <jbeulich@suse.com>
988 * i386-dis.c: Adjust description of I macro.
989 (x86_64_table): Drop use of I.
990 (float_mem): Replace use of I.
991 (putop): Remove handling of I. Adjust setting/clearing of "alt".
993 2020-06-26 Jan Beulich <jbeulich@suse.com>
995 * i386-dis.c: (print_insn): Avoid straight assignment to
996 priv.orig_sizeflag when processing -M sub-options.
998 2020-06-25 Jan Beulich <jbeulich@suse.com>
1000 * i386-dis.c: Adjust description of J macro.
1001 (dis386, x86_64_table, mod_table): Replace J.
1002 (putop): Remove handling of J.
1004 2020-06-25 Jan Beulich <jbeulich@suse.com>
1006 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1008 2020-06-25 Jan Beulich <jbeulich@suse.com>
1010 * i386-dis.c: Adjust description of "LQ" macro.
1011 (dis386_twobyte): Use LQ for sysret.
1012 (putop): Adjust handling of LQ.
1014 2020-06-22 Nelson Chu <nelson.chu@sifive.com>
1016 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1017 * riscv-dis.c: Include elfxx-riscv.h.
1019 2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1021 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1023 2020-06-17 Lili Cui <lili.cui@intel.com>
1025 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1027 2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1030 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1031 * i386-opc.tbl: Likewise.
1032 * i386-tbl.h: Regenerated.
1034 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
1036 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1038 2020-06-11 Alex Coplan <alex.coplan@arm.com>
1040 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1041 (SR_CORE): Likewise.
1042 (SR_FEAT): Likewise.
1044 (SR_V8_1): Likewise.
1045 (SR_V8_2): Likewise.
1046 (SR_V8_3): Likewise.
1047 (SR_V8_4): Likewise.
1050 (SR_SSBS): Likewise.
1052 (SR_ID_PFR2): Likewise.
1053 (SR_PROFILE): Likewise.
1054 (SR_MEMTAG): Likewise.
1055 (SR_SCXTNUM): Likewise.
1056 (aarch64_sys_regs): Refactor to store feature information in the table.
1057 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1058 that now describe their own features.
1059 (aarch64_pstatefield_supported_p): Likewise.
1061 2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1063 * i386-dis.c (prefix_table): Fix a typo in comments.
1065 2020-06-09 Jan Beulich <jbeulich@suse.com>
1067 * i386-dis.c (rex_ignored): Delete.
1068 (ckprefix): Drop rex_ignored initialization.
1069 (get_valid_dis386): Drop setting of rex_ignored.
1070 (print_insn): Drop checking of rex_ignored. Don't record data
1071 size prefix as used with VEX-and-alike encodings.
1073 2020-06-09 Jan Beulich <jbeulich@suse.com>
1075 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1076 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1077 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1078 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1079 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1080 VEX_0F12, and VEX_0F16.
1081 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1082 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1083 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1084 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1085 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1086 MOD_VEX_0F16_PREFIX_2 entries.
1088 2020-06-09 Jan Beulich <jbeulich@suse.com>
1090 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1091 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1092 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1093 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1094 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1095 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1096 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1097 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1098 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1099 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1100 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1101 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1102 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1103 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1104 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1105 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1106 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1107 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1108 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1109 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1110 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1111 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1112 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1113 EVEX_W_0FC6_P_2): Delete.
1114 (print_insn): Add EVEX.W vs embedded prefix consistency check
1115 to prefix validation.
1116 * i386-dis-evex.h (evex_table): Don't further descend for
1117 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1118 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1120 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1121 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1122 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1123 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1124 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1125 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1126 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1127 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1128 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1129 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1130 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1131 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1132 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1133 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1134 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1135 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1136 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1137 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1138 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1139 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1140 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1141 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1142 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1143 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1144 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1145 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1146 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1148 2020-06-09 Jan Beulich <jbeulich@suse.com>
1150 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1151 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1152 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1154 (print_insn): Drop pointless check against bad_opcode. Split
1155 prefix validation into legacy and VEX-and-alike parts.
1156 (putop): Re-work 'X' macro handling.
1158 2020-06-09 Jan Beulich <jbeulich@suse.com>
1160 * i386-dis.c (MOD_0F51): Rename to ...
1161 (MOD_0F50): ... this.
1163 2020-06-08 Alex Coplan <alex.coplan@arm.com>
1165 * arm-dis.c (arm_opcodes): Add dfb.
1166 (thumb32_opcodes): Add dfb.
1168 2020-06-08 Jan Beulich <jbeulich@suse.com>
1170 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1172 2020-06-06 Alan Modra <amodra@gmail.com>
1174 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1176 2020-06-05 Alan Modra <amodra@gmail.com>
1178 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1179 size is large enough.
1181 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1183 * disassemble.c (disassemble_init_for_target): Set endian_code for
1185 * bpf-desc.c: Regenerate.
1186 * bpf-opc.c: Likewise.
1187 * bpf-dis.c: Likewise.
1189 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1191 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1192 (cgen_put_insn_value): Likewise.
1193 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1194 * cgen-dis.in (print_insn): Likewise.
1195 * cgen-ibld.in (insert_1): Likewise.
1196 (insert_1): Likewise.
1197 (insert_insn_normal): Likewise.
1198 (extract_1): Likewise.
1199 * bpf-dis.c: Regenerate.
1200 * bpf-ibld.c: Likewise.
1201 * bpf-ibld.c: Likewise.
1202 * cgen-dis.in: Likewise.
1203 * cgen-ibld.in: Likewise.
1204 * cgen-opc.c: Likewise.
1205 * epiphany-dis.c: Likewise.
1206 * epiphany-ibld.c: Likewise.
1207 * fr30-dis.c: Likewise.
1208 * fr30-ibld.c: Likewise.
1209 * frv-dis.c: Likewise.
1210 * frv-ibld.c: Likewise.
1211 * ip2k-dis.c: Likewise.
1212 * ip2k-ibld.c: Likewise.
1213 * iq2000-dis.c: Likewise.
1214 * iq2000-ibld.c: Likewise.
1215 * lm32-dis.c: Likewise.
1216 * lm32-ibld.c: Likewise.
1217 * m32c-dis.c: Likewise.
1218 * m32c-ibld.c: Likewise.
1219 * m32r-dis.c: Likewise.
1220 * m32r-ibld.c: Likewise.
1221 * mep-dis.c: Likewise.
1222 * mep-ibld.c: Likewise.
1223 * mt-dis.c: Likewise.
1224 * mt-ibld.c: Likewise.
1225 * or1k-dis.c: Likewise.
1226 * or1k-ibld.c: Likewise.
1227 * xc16x-dis.c: Likewise.
1228 * xc16x-ibld.c: Likewise.
1229 * xstormy16-dis.c: Likewise.
1230 * xstormy16-ibld.c: Likewise.
1232 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1234 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1235 (print_insn_): Handle instruction endian.
1236 * bpf-dis.c: Regenerate.
1237 * bpf-desc.c: Regenerate.
1238 * epiphany-dis.c: Likewise.
1239 * epiphany-desc.c: Likewise.
1240 * fr30-dis.c: Likewise.
1241 * fr30-desc.c: Likewise.
1242 * frv-dis.c: Likewise.
1243 * frv-desc.c: Likewise.
1244 * ip2k-dis.c: Likewise.
1245 * ip2k-desc.c: Likewise.
1246 * iq2000-dis.c: Likewise.
1247 * iq2000-desc.c: Likewise.
1248 * lm32-dis.c: Likewise.
1249 * lm32-desc.c: Likewise.
1250 * m32c-dis.c: Likewise.
1251 * m32c-desc.c: Likewise.
1252 * m32r-dis.c: Likewise.
1253 * m32r-desc.c: Likewise.
1254 * mep-dis.c: Likewise.
1255 * mep-desc.c: Likewise.
1256 * mt-dis.c: Likewise.
1257 * mt-desc.c: Likewise.
1258 * or1k-dis.c: Likewise.
1259 * or1k-desc.c: Likewise.
1260 * xc16x-dis.c: Likewise.
1261 * xc16x-desc.c: Likewise.
1262 * xstormy16-dis.c: Likewise.
1263 * xstormy16-desc.c: Likewise.
1265 2020-06-03 Nick Clifton <nickc@redhat.com>
1267 * po/sr.po: Updated Serbian translation.
1269 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
1271 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1272 (riscv_get_priv_spec_class): Likewise.
1274 2020-06-01 Alan Modra <amodra@gmail.com>
1276 * bpf-desc.c: Regenerate.
1278 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1279 David Faust <david.faust@oracle.com>
1281 * bpf-desc.c: Regenerate.
1282 * bpf-opc.h: Likewise.
1283 * bpf-opc.c: Likewise.
1284 * bpf-dis.c: Likewise.
1286 2020-05-28 Alan Modra <amodra@gmail.com>
1288 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1291 2020-05-28 Alan Modra <amodra@gmail.com>
1293 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1295 (print_insn_ns32k): Revert last change.
1297 2020-05-28 Nick Clifton <nickc@redhat.com>
1299 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1302 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1304 Fix extraction of signed constants in nios2 disassembler (again).
1306 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1307 extractions of signed fields.
1309 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1311 * s390-opc.txt: Relocate vector load/store instructions with
1312 additional alignment parameter and change architecture level
1313 constraint from z14 to z13.
1315 2020-05-21 Alan Modra <amodra@gmail.com>
1317 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1318 * sparc-dis.c: Likewise.
1319 * tic4x-dis.c: Likewise.
1320 * xtensa-dis.c: Likewise.
1321 * bpf-desc.c: Regenerate.
1322 * epiphany-desc.c: Regenerate.
1323 * fr30-desc.c: Regenerate.
1324 * frv-desc.c: Regenerate.
1325 * ip2k-desc.c: Regenerate.
1326 * iq2000-desc.c: Regenerate.
1327 * lm32-desc.c: Regenerate.
1328 * m32c-desc.c: Regenerate.
1329 * m32r-desc.c: Regenerate.
1330 * mep-asm.c: Regenerate.
1331 * mep-desc.c: Regenerate.
1332 * mt-desc.c: Regenerate.
1333 * or1k-desc.c: Regenerate.
1334 * xc16x-desc.c: Regenerate.
1335 * xstormy16-desc.c: Regenerate.
1337 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
1339 * riscv-opc.c (riscv_ext_version_table): The table used to store
1340 all information about the supported spec and the corresponding ISA
1341 versions. Currently, only Zicsr is supported to verify the
1342 correctness of Z sub extension settings. Others will be supported
1343 in the future patches.
1344 (struct isa_spec_t, isa_specs): List for all supported ISA spec
1345 classes and the corresponding strings.
1346 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
1347 spec class by giving a ISA spec string.
1348 * riscv-opc.c (struct priv_spec_t): New structure.
1349 (struct priv_spec_t priv_specs): List for all supported privilege spec
1350 classes and the corresponding strings.
1351 (riscv_get_priv_spec_class): New function. Get the corresponding
1352 privilege spec class by giving a spec string.
1353 (riscv_get_priv_spec_name): New function. Get the corresponding
1354 privilege spec string by giving a CSR version class.
1355 * riscv-dis.c: Updated since DECLARE_CSR is changed.
1356 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
1357 according to the chosen version. Build a hash table riscv_csr_hash to
1358 store the valid CSR for the chosen pirv verison. Dump the direct
1359 CSR address rather than it's name if it is invalid.
1360 (parse_riscv_dis_option_without_args): New function. Parse the options
1362 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
1363 parse the options without arguments first, and then handle the options
1364 with arguments. Add the new option -Mpriv-spec, which has argument.
1365 * riscv-dis.c (print_riscv_disassembler_options): Add description
1366 about the new OBJDUMP option.
1368 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
1370 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
1371 WC values on POWER10 sync, dcbf and wait instructions.
1372 (insert_pl, extract_pl): New functions.
1373 (L2OPT, LS, WC): Use insert_ls and extract_ls.
1374 (LS3): New , 3-bit L for sync.
1375 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
1376 (SC2, PL): New, 2-bit SC and PL for sync and wait.
1377 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
1378 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
1379 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
1380 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
1381 <wait>: Enable PL operand on POWER10.
1382 <dcbf>: Enable L3OPT operand on POWER10.
1383 <sync>: Enable SC2 operand on POWER10.
1385 2020-05-19 Stafford Horne <shorne@gmail.com>
1388 * or1k-asm.c: Regenerate.
1389 * or1k-desc.c: Regenerate.
1390 * or1k-desc.h: Regenerate.
1391 * or1k-dis.c: Regenerate.
1392 * or1k-ibld.c: Regenerate.
1393 * or1k-opc.c: Regenerate.
1394 * or1k-opc.h: Regenerate.
1395 * or1k-opinst.c: Regenerate.
1397 2020-05-11 Alan Modra <amodra@gmail.com>
1399 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
1402 2020-05-11 Alan Modra <amodra@gmail.com>
1404 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
1405 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
1407 2020-05-11 Alan Modra <amodra@gmail.com>
1409 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
1411 2020-05-11 Alan Modra <amodra@gmail.com>
1413 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
1414 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
1416 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1418 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
1421 2020-05-11 Alan Modra <amodra@gmail.com>
1423 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
1424 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
1425 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
1426 (prefix_opcodes): Add xxeval.
1428 2020-05-11 Alan Modra <amodra@gmail.com>
1430 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
1431 xxgenpcvwm, xxgenpcvdm.
1433 2020-05-11 Alan Modra <amodra@gmail.com>
1435 * ppc-opc.c (MP, VXVAM_MASK): Define.
1436 (VXVAPS_MASK): Use VXVA_MASK.
1437 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
1438 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
1439 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
1440 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
1442 2020-05-11 Alan Modra <amodra@gmail.com>
1443 Peter Bergner <bergner@linux.ibm.com>
1445 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
1447 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
1448 YMSK2, XA6a, XA6ap, XB6a entries.
1449 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
1450 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
1452 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
1453 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
1454 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
1455 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
1456 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
1457 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
1458 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
1459 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
1460 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
1461 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
1462 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
1463 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
1464 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
1465 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
1467 2020-05-11 Alan Modra <amodra@gmail.com>
1469 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
1470 (insert_xts, extract_xts): New functions.
1471 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
1472 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
1473 (VXRC_MASK, VXSH_MASK): Define.
1474 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
1475 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
1476 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
1477 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
1478 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
1479 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
1480 xxblendvh, xxblendvw, xxblendvd, xxpermx.
1482 2020-05-11 Alan Modra <amodra@gmail.com>
1484 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
1485 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
1486 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
1487 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
1488 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
1490 2020-05-11 Alan Modra <amodra@gmail.com>
1492 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
1493 (XTP, DQXP, DQXP_MASK): Define.
1494 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
1495 (prefix_opcodes): Add plxvp and pstxvp.
1497 2020-05-11 Alan Modra <amodra@gmail.com>
1499 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1500 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1501 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1503 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1505 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1507 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1509 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1511 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1513 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1515 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1517 2020-05-11 Alan Modra <amodra@gmail.com>
1519 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1521 2020-05-11 Alan Modra <amodra@gmail.com>
1523 * ppc-dis.c (ppc_opts): Add "power10" entry.
1524 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1525 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
1527 2020-05-11 Nick Clifton <nickc@redhat.com>
1529 * po/fr.po: Updated French translation.
1531 2020-04-30 Alex Coplan <alex.coplan@arm.com>
1533 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1534 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1535 (operand_general_constraint_met_p): validate
1536 AARCH64_OPND_UNDEFINED.
1537 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1539 * aarch64-asm-2.c: Regenerated.
1540 * aarch64-dis-2.c: Regenerated.
1541 * aarch64-opc-2.c: Regenerated.
1543 2020-04-29 Nick Clifton <nickc@redhat.com>
1546 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1549 2020-04-29 Nick Clifton <nickc@redhat.com>
1551 * po/sv.po: Updated Swedish translation.
1553 2020-04-29 Nick Clifton <nickc@redhat.com>
1556 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
1557 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
1558 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
1561 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
1564 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
1565 cmpi only on m68020up and cpu32.
1567 2020-04-20 Sudakshina Das <sudi.das@arm.com>
1569 * aarch64-asm.c (aarch64_ins_none): New.
1570 * aarch64-asm.h (ins_none): New declaration.
1571 * aarch64-dis.c (aarch64_ext_none): New.
1572 * aarch64-dis.h (ext_none): New declaration.
1573 * aarch64-opc.c (aarch64_print_operand): Update case for
1574 AARCH64_OPND_BARRIER_PSB.
1575 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
1576 (AARCH64_OPERANDS): Update inserter/extracter for
1577 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
1578 * aarch64-asm-2.c: Regenerated.
1579 * aarch64-dis-2.c: Regenerated.
1580 * aarch64-opc-2.c: Regenerated.
1582 2020-04-20 Sudakshina Das <sudi.das@arm.com>
1584 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
1585 (aarch64_feature_ras, RAS): Likewise.
1586 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
1587 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
1588 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
1589 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
1590 * aarch64-asm-2.c: Regenerated.
1591 * aarch64-dis-2.c: Regenerated.
1592 * aarch64-opc-2.c: Regenerated.
1594 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
1596 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
1597 (print_insn_neon): Support disassembly of conditional
1600 2020-02-16 David Faust <david.faust@oracle.com>
1602 * bpf-desc.c: Regenerate.
1603 * bpf-desc.h: Likewise.
1604 * bpf-opc.c: Regenerate.
1605 * bpf-opc.h: Likewise.
1607 2020-04-07 Lili Cui <lili.cui@intel.com>
1609 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
1610 (prefix_table): New instructions (see prefixes above).
1611 (rm_table): Likewise
1612 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
1613 CPU_ANY_TSXLDTRK_FLAGS.
1614 (cpu_flags): Add CpuTSXLDTRK.
1615 * i386-opc.h (enum): Add CpuTSXLDTRK.
1616 (i386_cpu_flags): Add cputsxldtrk.
1617 * i386-opc.tbl: Add XSUSPLDTRK insns.
1618 * i386-init.h: Regenerate.
1619 * i386-tbl.h: Likewise.
1621 2020-04-02 Lili Cui <lili.cui@intel.com>
1623 * i386-dis.c (prefix_table): New instructions serialize.
1624 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
1625 CPU_ANY_SERIALIZE_FLAGS.
1626 (cpu_flags): Add CpuSERIALIZE.
1627 * i386-opc.h (enum): Add CpuSERIALIZE.
1628 (i386_cpu_flags): Add cpuserialize.
1629 * i386-opc.tbl: Add SERIALIZE insns.
1630 * i386-init.h: Regenerate.
1631 * i386-tbl.h: Likewise.
1633 2020-03-26 Alan Modra <amodra@gmail.com>
1635 * disassemble.h (opcodes_assert): Declare.
1636 (OPCODES_ASSERT): Define.
1637 * disassemble.c: Don't include assert.h. Include opintl.h.
1638 (opcodes_assert): New function.
1639 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
1640 (bfd_h8_disassemble): Reduce size of data array. Correctly
1641 calculate maxlen. Omit insn decoding when insn length exceeds
1642 maxlen. Exit from nibble loop when looking for E, before
1643 accessing next data byte. Move processing of E outside loop.
1644 Replace tests of maxlen in loop with assertions.
1646 2020-03-26 Alan Modra <amodra@gmail.com>
1648 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
1650 2020-03-25 Alan Modra <amodra@gmail.com>
1652 * z80-dis.c (suffix): Init mybuf.
1654 2020-03-22 Alan Modra <amodra@gmail.com>
1656 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
1657 successflly read from section.
1659 2020-03-22 Alan Modra <amodra@gmail.com>
1661 * arc-dis.c (find_format): Use ISO C string concatenation rather
1662 than line continuation within a string. Don't access needs_limm
1663 before testing opcode != NULL.
1665 2020-03-22 Alan Modra <amodra@gmail.com>
1667 * ns32k-dis.c (print_insn_arg): Update comment.
1668 (print_insn_ns32k): Reduce size of index_offset array, and
1669 initialize, passing -1 to print_insn_arg for args that are not
1670 an index. Don't exit arg loop early. Abort on bad arg number.
1672 2020-03-22 Alan Modra <amodra@gmail.com>
1674 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
1675 * s12z-opc.c: Formatting.
1676 (operands_f): Return an int.
1677 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
1678 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
1679 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
1680 (exg_sex_discrim): Likewise.
1681 (create_immediate_operand, create_bitfield_operand),
1682 (create_register_operand_with_size, create_register_all_operand),
1683 (create_register_all16_operand, create_simple_memory_operand),
1684 (create_memory_operand, create_memory_auto_operand): Don't
1685 segfault on malloc failure.
1686 (z_ext24_decode): Return an int status, negative on fail, zero
1688 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
1689 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
1690 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
1691 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
1692 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1693 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1694 (loop_primitive_decode, shift_decode, psh_pul_decode),
1695 (bit_field_decode): Similarly.
1696 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
1697 to return value, update callers.
1698 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1699 Don't segfault on NULL operand.
1700 (decode_operation): Return OP_INVALID on first fail.
1701 (decode_s12z): Check all reads, returning -1 on fail.
1703 2020-03-20 Alan Modra <amodra@gmail.com>
1705 * metag-dis.c (print_insn_metag): Don't ignore status from
1708 2020-03-20 Alan Modra <amodra@gmail.com>
1710 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1711 Initialize parts of buffer not written when handling a possible
1712 2-byte insn at end of section. Don't attempt decoding of such
1713 an insn by the 4-byte machinery.
1715 2020-03-20 Alan Modra <amodra@gmail.com>
1717 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1718 partially filled buffer. Prevent lookup of 4-byte insns when
1719 only VLE 2-byte insns are possible due to section size. Print
1720 ".word" rather than ".long" for 2-byte leftovers.
1722 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
1725 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1727 2020-03-13 Jan Beulich <jbeulich@suse.com>
1729 * i386-dis.c (X86_64_0D): Rename to ...
1730 (X86_64_0E): ... this.
1732 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
1734 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1735 * Makefile.in: Regenerated.
1737 2020-03-09 Jan Beulich <jbeulich@suse.com>
1739 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
1741 * i386-tbl.h: Re-generate.
1743 2020-03-09 Jan Beulich <jbeulich@suse.com>
1745 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1746 vprot*, vpsha*, and vpshl*.
1747 * i386-tbl.h: Re-generate.
1749 2020-03-09 Jan Beulich <jbeulich@suse.com>
1751 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1752 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1753 * i386-tbl.h: Re-generate.
1755 2020-03-09 Jan Beulich <jbeulich@suse.com>
1757 * i386-gen.c (set_bitfield): Ignore zero-length field names.
1758 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1759 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1760 * i386-tbl.h: Re-generate.
1762 2020-03-09 Jan Beulich <jbeulich@suse.com>
1764 * i386-gen.c (struct template_arg, struct template_instance,
1765 struct template_param, struct template, templates,
1766 parse_template, expand_templates): New.
1767 (process_i386_opcodes): Various local variables moved to
1768 expand_templates. Call parse_template and expand_templates.
1769 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1770 * i386-tbl.h: Re-generate.
1772 2020-03-06 Jan Beulich <jbeulich@suse.com>
1774 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1775 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1776 register and memory source templates. Replace VexW= by VexW*
1778 * i386-tbl.h: Re-generate.
1780 2020-03-06 Jan Beulich <jbeulich@suse.com>
1782 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1783 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1784 * i386-tbl.h: Re-generate.
1786 2020-03-06 Jan Beulich <jbeulich@suse.com>
1788 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1789 * i386-tbl.h: Re-generate.
1791 2020-03-06 Jan Beulich <jbeulich@suse.com>
1793 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1794 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1795 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1796 VexW0 on SSE2AVX variants.
1797 (vmovq): Drop NoRex64 from XMM/XMM variants.
1798 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1799 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1800 applicable use VexW0.
1801 * i386-tbl.h: Re-generate.
1803 2020-03-06 Jan Beulich <jbeulich@suse.com>
1805 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1806 * i386-opc.h (Rex64): Delete.
1807 (struct i386_opcode_modifier): Remove rex64 field.
1808 * i386-opc.tbl (crc32): Drop Rex64.
1809 Replace Rex64 with Size64 everywhere else.
1810 * i386-tbl.h: Re-generate.
1812 2020-03-06 Jan Beulich <jbeulich@suse.com>
1814 * i386-dis.c (OP_E_memory): Exclude recording of used address
1815 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1816 addressed memory operands for MPX insns.
1818 2020-03-06 Jan Beulich <jbeulich@suse.com>
1820 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1821 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1822 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1823 (ptwrite): Split into non-64-bit and 64-bit forms.
1824 * i386-tbl.h: Re-generate.
1826 2020-03-06 Jan Beulich <jbeulich@suse.com>
1828 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1830 * i386-tbl.h: Re-generate.
1832 2020-03-04 Jan Beulich <jbeulich@suse.com>
1834 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1835 (prefix_table): Move vmmcall here. Add vmgexit.
1836 (rm_table): Replace vmmcall entry by prefix_table[] escape.
1837 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1838 (cpu_flags): Add CpuSEV_ES entry.
1839 * i386-opc.h (CpuSEV_ES): New.
1840 (union i386_cpu_flags): Add cpusev_es field.
1841 * i386-opc.tbl (vmgexit): New.
1842 * i386-init.h, i386-tbl.h: Re-generate.
1844 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1846 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1848 * i386-opc.h (IGNORESIZE): New.
1849 (DEFAULTSIZE): Likewise.
1850 (IgnoreSize): Removed.
1851 (DefaultSize): Likewise.
1852 (MnemonicSize): New.
1853 (i386_opcode_modifier): Replace ignoresize/defaultsize with
1855 * i386-opc.tbl (IgnoreSize): New.
1856 (DefaultSize): Likewise.
1857 * i386-tbl.h: Regenerated.
1859 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1862 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
1865 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1868 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
1869 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
1870 * i386-tbl.h: Regenerated.
1872 2020-02-26 Alan Modra <amodra@gmail.com>
1874 * aarch64-asm.c: Indent labels correctly.
1875 * aarch64-dis.c: Likewise.
1876 * aarch64-gen.c: Likewise.
1877 * aarch64-opc.c: Likewise.
1878 * alpha-dis.c: Likewise.
1879 * i386-dis.c: Likewise.
1880 * nds32-asm.c: Likewise.
1881 * nfp-dis.c: Likewise.
1882 * visium-dis.c: Likewise.
1884 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
1886 * arc-regs.h (int_vector_base): Make it available for all ARC
1889 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
1891 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
1894 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
1896 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
1897 c.mv/c.li if rs1 is zero.
1899 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
1901 * i386-gen.c (cpu_flag_init): Replace CpuABM with
1902 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
1904 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
1905 * i386-opc.h (CpuABM): Removed.
1907 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
1908 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
1909 popcnt. Remove CpuABM from lzcnt.
1910 * i386-init.h: Regenerated.
1911 * i386-tbl.h: Likewise.
1913 2020-02-17 Jan Beulich <jbeulich@suse.com>
1915 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
1916 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
1917 VexW1 instead of open-coding them.
1918 * i386-tbl.h: Re-generate.
1920 2020-02-17 Jan Beulich <jbeulich@suse.com>
1922 * i386-opc.tbl (AddrPrefixOpReg): Define.
1923 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
1924 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
1925 templates. Drop NoRex64.
1926 * i386-tbl.h: Re-generate.
1928 2020-02-17 Jan Beulich <jbeulich@suse.com>
1931 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1932 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
1933 into Intel syntax instance (with Unpsecified) and AT&T one
1935 (vcvtneps2bf16): Likewise, along with folding the two so far
1937 * i386-tbl.h: Re-generate.
1939 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1941 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1942 CPU_ANY_SSE4A_FLAGS.
1944 2020-02-17 Alan Modra <amodra@gmail.com>
1946 * i386-gen.c (cpu_flag_init): Correct last change.
1948 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1950 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
1953 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
1955 * i386-opc.tbl (movsx): Remove Intel syntax comments.
1958 2020-02-14 Jan Beulich <jbeulich@suse.com>
1961 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1962 destination for Cpu64-only variant.
1963 (movzx): Fold patterns.
1964 * i386-tbl.h: Re-generate.
1966 2020-02-13 Jan Beulich <jbeulich@suse.com>
1968 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1969 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1970 CPU_ANY_SSE4_FLAGS entry.
1971 * i386-init.h: Re-generate.
1973 2020-02-12 Jan Beulich <jbeulich@suse.com>
1975 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1976 with Unspecified, making the present one AT&T syntax only.
1977 * i386-tbl.h: Re-generate.
1979 2020-02-12 Jan Beulich <jbeulich@suse.com>
1981 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1982 * i386-tbl.h: Re-generate.
1984 2020-02-12 Jan Beulich <jbeulich@suse.com>
1987 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1988 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1989 Amd64 and Intel64 templates.
1990 (call, jmp): Likewise for far indirect variants. Dro
1992 * i386-tbl.h: Re-generate.
1994 2020-02-11 Jan Beulich <jbeulich@suse.com>
1996 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1997 * i386-opc.h (ShortForm): Delete.
1998 (struct i386_opcode_modifier): Remove shortform field.
1999 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2000 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2001 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2002 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2004 * i386-tbl.h: Re-generate.
2006 2020-02-11 Jan Beulich <jbeulich@suse.com>
2008 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2009 fucompi): Drop ShortForm from operand-less templates.
2010 * i386-tbl.h: Re-generate.
2012 2020-02-11 Alan Modra <amodra@gmail.com>
2014 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2015 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2016 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2017 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2018 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2020 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2022 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2023 (cde_opcodes): Add VCX* instructions.
2025 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2026 Matthew Malcomson <matthew.malcomson@arm.com>
2028 * arm-dis.c (struct cdeopcode32): New.
2029 (CDE_OPCODE): New macro.
2030 (cde_opcodes): New disassembly table.
2031 (regnames): New option to table.
2032 (cde_coprocs): New global variable.
2033 (print_insn_cde): New
2034 (print_insn_thumb32): Use print_insn_cde.
2035 (parse_arm_disassembler_options): Parse coprocN args.
2037 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2040 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2042 * i386-opc.h (AMD64): Removed.
2043 (Intel64): Likewose.
2045 (INTEL64): Likewise.
2046 (INTEL64ONLY): Likewise.
2047 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2048 * i386-opc.tbl (Amd64): New.
2049 (Intel64): Likewise.
2050 (Intel64Only): Likewise.
2051 Replace AMD64 with Amd64. Update sysenter/sysenter with
2052 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2053 * i386-tbl.h: Regenerated.
2055 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2058 * z80-dis.c: Add support for GBZ80 opcodes.
2060 2020-02-04 Alan Modra <amodra@gmail.com>
2062 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2064 2020-02-03 Alan Modra <amodra@gmail.com>
2066 * m32c-ibld.c: Regenerate.
2068 2020-02-01 Alan Modra <amodra@gmail.com>
2070 * frv-ibld.c: Regenerate.
2072 2020-01-31 Jan Beulich <jbeulich@suse.com>
2074 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2075 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2076 (OP_E_memory): Replace xmm_mdq_mode case label by
2077 vex_scalar_w_dq_mode one.
2078 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2080 2020-01-31 Jan Beulich <jbeulich@suse.com>
2082 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2083 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2084 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2085 (intel_operand_size): Drop vex_w_dq_mode case label.
2087 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2089 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2090 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2092 2020-01-30 Alan Modra <amodra@gmail.com>
2094 * m32c-ibld.c: Regenerate.
2096 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2098 * bpf-opc.c: Regenerate.
2100 2020-01-30 Jan Beulich <jbeulich@suse.com>
2102 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2103 (dis386): Use them to replace C2/C3 table entries.
2104 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2105 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2106 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2107 * i386-tbl.h: Re-generate.
2109 2020-01-30 Jan Beulich <jbeulich@suse.com>
2111 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2113 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2115 * i386-tbl.h: Re-generate.
2117 2020-01-30 Alan Modra <amodra@gmail.com>
2119 * tic4x-dis.c (tic4x_dp): Make unsigned.
2121 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2122 Jan Beulich <jbeulich@suse.com>
2125 * i386-dis.c (MOVSXD_Fixup): New function.
2126 (movsxd_mode): New enum.
2127 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2128 (intel_operand_size): Handle movsxd_mode.
2129 (OP_E_register): Likewise.
2131 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2132 register on movsxd. Add movsxd with 16-bit destination register
2133 for AMD64 and Intel64 ISAs.
2134 * i386-tbl.h: Regenerated.
2136 2020-01-27 Tamar Christina <tamar.christina@arm.com>
2139 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2140 * aarch64-asm-2.c: Regenerate
2141 * aarch64-dis-2.c: Likewise.
2142 * aarch64-opc-2.c: Likewise.
2144 2020-01-21 Jan Beulich <jbeulich@suse.com>
2146 * i386-opc.tbl (sysret): Drop DefaultSize.
2147 * i386-tbl.h: Re-generate.
2149 2020-01-21 Jan Beulich <jbeulich@suse.com>
2151 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2153 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2154 * i386-tbl.h: Re-generate.
2156 2020-01-20 Nick Clifton <nickc@redhat.com>
2158 * po/de.po: Updated German translation.
2159 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2160 * po/uk.po: Updated Ukranian translation.
2162 2020-01-20 Alan Modra <amodra@gmail.com>
2164 * hppa-dis.c (fput_const): Remove useless cast.
2166 2020-01-20 Alan Modra <amodra@gmail.com>
2168 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2170 2020-01-18 Nick Clifton <nickc@redhat.com>
2172 * configure: Regenerate.
2173 * po/opcodes.pot: Regenerate.
2175 2020-01-18 Nick Clifton <nickc@redhat.com>
2177 Binutils 2.34 branch created.
2179 2020-01-17 Christian Biesinger <cbiesinger@google.com>
2181 * opintl.h: Fix spelling error (seperate).
2183 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2185 * i386-opc.tbl: Add {vex} pseudo prefix.
2186 * i386-tbl.h: Regenerated.
2188 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2191 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2192 (neon_opcodes): Likewise.
2193 (select_arm_features): Make sure we enable MVE bits when selecting
2194 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2197 2020-01-16 Jan Beulich <jbeulich@suse.com>
2199 * i386-opc.tbl: Drop stale comment from XOP section.
2201 2020-01-16 Jan Beulich <jbeulich@suse.com>
2203 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2204 (extractps): Add VexWIG to SSE2AVX forms.
2205 * i386-tbl.h: Re-generate.
2207 2020-01-16 Jan Beulich <jbeulich@suse.com>
2209 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2210 Size64 from and use VexW1 on SSE2AVX forms.
2211 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2212 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2213 * i386-tbl.h: Re-generate.
2215 2020-01-15 Alan Modra <amodra@gmail.com>
2217 * tic4x-dis.c (tic4x_version): Make unsigned long.
2218 (optab, optab_special, registernames): New file scope vars.
2219 (tic4x_print_register): Set up registernames rather than
2220 malloc'd registertable.
2221 (tic4x_disassemble): Delete optable and optable_special. Use
2222 optab and optab_special instead. Throw away old optab,
2223 optab_special and registernames when info->mach changes.
2225 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2228 * z80-dis.c (suffix): Use .db instruction to generate double
2231 2020-01-14 Alan Modra <amodra@gmail.com>
2233 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2234 values to unsigned before shifting.
2236 2020-01-13 Thomas Troeger <tstroege@gmx.de>
2238 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2240 (print_insn_thumb16, print_insn_thumb32): Likewise.
2241 (print_insn): Initialize the insn info.
2242 * i386-dis.c (print_insn): Initialize the insn info fields, and
2245 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2247 * arc-opc.c (C_NE): Make it required.
2249 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2251 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2252 reserved register name.
2254 2020-01-13 Alan Modra <amodra@gmail.com>
2256 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2257 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2259 2020-01-13 Alan Modra <amodra@gmail.com>
2261 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2262 result of wasm_read_leb128 in a uint64_t and check that bits
2263 are not lost when copying to other locals. Use uint32_t for
2264 most locals. Use PRId64 when printing int64_t.
2266 2020-01-13 Alan Modra <amodra@gmail.com>
2268 * score-dis.c: Formatting.
2269 * score7-dis.c: Formatting.
2271 2020-01-13 Alan Modra <amodra@gmail.com>
2273 * score-dis.c (print_insn_score48): Use unsigned variables for
2274 unsigned values. Don't left shift negative values.
2275 (print_insn_score32): Likewise.
2276 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2278 2020-01-13 Alan Modra <amodra@gmail.com>
2280 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2282 2020-01-13 Alan Modra <amodra@gmail.com>
2284 * fr30-ibld.c: Regenerate.
2286 2020-01-13 Alan Modra <amodra@gmail.com>
2288 * xgate-dis.c (print_insn): Don't left shift signed value.
2289 (ripBits): Formatting, use 1u.
2291 2020-01-10 Alan Modra <amodra@gmail.com>
2293 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2294 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2296 2020-01-10 Alan Modra <amodra@gmail.com>
2298 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2299 and XRREG value earlier to avoid a shift with negative exponent.
2300 * m10200-dis.c (disassemble): Similarly.
2302 2020-01-09 Nick Clifton <nickc@redhat.com>
2305 * z80-dis.c (ld_ii_ii): Use correct cast.
2307 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2310 * z80-dis.c (ld_ii_ii): Use character constant when checking
2313 2020-01-09 Jan Beulich <jbeulich@suse.com>
2315 * i386-dis.c (SEP_Fixup): New.
2317 (dis386_twobyte): Use it for sysenter/sysexit.
2318 (enum x86_64_isa): Change amd64 enumerator to value 1.
2319 (OP_J): Compare isa64 against intel64 instead of amd64.
2320 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2322 * i386-tbl.h: Re-generate.
2324 2020-01-08 Alan Modra <amodra@gmail.com>
2326 * z8k-dis.c: Include libiberty.h
2327 (instr_data_s): Make max_fetched unsigned.
2328 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2329 Don't exceed byte_info bounds.
2330 (output_instr): Make num_bytes unsigned.
2331 (unpack_instr): Likewise for nibl_count and loop.
2332 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2334 * z8k-opc.h: Regenerate.
2336 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
2338 * arc-tbl.h (llock): Use 'LLOCK' as class.
2340 (scond): Use 'SCOND' as class.
2342 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
2345 2020-01-06 Alan Modra <amodra@gmail.com>
2347 * m32c-ibld.c: Regenerate.
2349 2020-01-06 Alan Modra <amodra@gmail.com>
2352 * z80-dis.c (suffix): Don't use a local struct buffer copy.
2353 Peek at next byte to prevent recursion on repeated prefix bytes.
2354 Ensure uninitialised "mybuf" is not accessed.
2355 (print_insn_z80): Don't zero n_fetch and n_used here,..
2356 (print_insn_z80_buf): ..do it here instead.
2358 2020-01-04 Alan Modra <amodra@gmail.com>
2360 * m32r-ibld.c: Regenerate.
2362 2020-01-04 Alan Modra <amodra@gmail.com>
2364 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2366 2020-01-04 Alan Modra <amodra@gmail.com>
2368 * crx-dis.c (match_opcode): Avoid shift left of signed value.
2370 2020-01-04 Alan Modra <amodra@gmail.com>
2372 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2374 2020-01-03 Jan Beulich <jbeulich@suse.com>
2376 * aarch64-tbl.h (aarch64_opcode_table): Use
2377 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2379 2020-01-03 Jan Beulich <jbeulich@suse.com>
2381 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
2382 forms of SUDOT and USDOT.
2384 2020-01-03 Jan Beulich <jbeulich@suse.com>
2386 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
2388 * opcodes/aarch64-dis-2.c: Re-generate.
2390 2020-01-03 Jan Beulich <jbeulich@suse.com>
2392 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
2394 * opcodes/aarch64-dis-2.c: Re-generate.
2396 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
2398 * z80-dis.c: Add support for eZ80 and Z80 instructions.
2400 2020-01-01 Alan Modra <amodra@gmail.com>
2402 Update year range in copyright notice of all files.
2404 For older changes see ChangeLog-2019
2406 Copyright (C) 2020 Free Software Foundation, Inc.
2408 Copying and distribution of this file, with or without modification,
2409 are permitted in any medium without royalty provided the copyright
2410 notice and this notice are preserved.
2416 version-control: never
projects / thirdparty / binutils-gdb.git / blob