1 2020-10-05 H.J. Lu <hongjiu.lu@intel.com>
4 * i386-dis.c (print_insn): Clear modrm if not needed.
5 (putop): Check need_modrm for modrm.mod != 3. Don't check
6 need_modrm for modrm.mod == 3.
8 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
10 * aarch64-opc.c: Added ETMv4 system registers TRCACATRn, TRCACVRn,
11 TRCAUTHSTATUS, TRCAUXCTLR, TRCBBCTLR, TRCCCCTLR, TRCCIDCCTLR0, TRCCIDCCTLR1,
12 TRCCIDCVRn, TRCCIDR0, TRCCIDR1, TRCCIDR2, TRCCIDR3, TRCCLAIMCLR, TRCCLAIMSET,
13 TRCCNTCTLRn, TRCCNTRLDVRn, TRCCNTVRn, TRCCONFIGR, TRCDEVAFF0, TRCDEVAFF1,
14 TRCDEVARCH, TRCDEVID, TRCDEVTYPE, TRCDVCMRn, TRCDVCVRn, TRCEVENTCTL0R,
15 TRCEVENTCTL1R, TRCEXTINSELR, TRCIDR0, TRCIDR1, TRCIDR2, TRCIDR3, TRCIDR4,
16 TRCIDR5, TRCIDR6, TRCIDR7, TRCIDR8, TRCIDR9, TRCIDR10, TRCIDR11, TRCIDR12,
17 TRCIDR13, TRCIMSPEC0, TRCIMSPECn, TRCITCTRL, TRCLAR WOTRCLSR, TRCOSLAR
18 WOTRCOSLSR, TRCPDCR, TRCPDSR, TRCPIDR0, TRCPIDR1, TRCPIDR2, TRCPIDR3,
19 TRCPIDR4, TRCPIDR[5,6,7], TRCPRGCTLR, TRCP,CSELR, TRCQCTLR, TRCRSCTLRn,
20 TRCSEQEVRn, TRCSEQRSTEVR, TRCSEQSTR, TRCSSCCRn, TRCSSCSRn, TRCSSPCICRn,
21 TRCSTALLCTLR, TRCSTATR, TRCSYNCPR, TRCTRACEIDR, TRCTSCTLR, TRCVDARCCTLR,
22 TRCVDCTLR, TRCVDSACCTLR, TRCVICTLR, TRCVIIECTLR, TRCVIPCSSCTLR, TRCVISSCTLR,
23 TRCVMIDCCTLR0, TRCVMIDCCTLR1 and TRCVMIDCVRn.
25 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
27 * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
29 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
31 * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
32 TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
34 2020-09-26 Alan Modra <amodra@gmail.com>
36 * csky-opc.h: Formatting.
37 (GENERAL_REG_BANK): Correct spelling. Update use throughout file.
38 (get_register_name): Mask arch with CSKY_ARCH_MASK for shift,
40 (get_register_number): Likewise.
41 * csky-dis.c (get_gr_name, get_cr_name): Don't mask mach_flag.
43 2020-09-24 Lili Cui <lili.cui@intel.com>
46 * i386-dis.c (enum): Put MOD_VEX_0F38* together.
48 2020-09-24 Andrew Burgess <andrew.burgess@embecosm.com>
50 * csky-dis.c (csky_output_operand): Enclose body of if in curly
53 2020-09-24 Lili Cui <lili.cui@intel.com>
55 * i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5,
56 PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7,
57 X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2,
58 X86_64_0F01_REG_1_RM_7_P_2.
59 (prefix_table): Likewise.
60 (x86_64_table): Likewise.
62 * i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS
63 and CPU_ANY_TDX_FLAGS.
64 (cpu_flags): Add CpuTDX.
65 * i386-opc.h (enum): Add CpuTDX.
66 (i386_cpu_flags): Add cputdx.
67 * i386-opc.tbl: Add TDX insns.
68 * i386-init.h: Regenerate.
69 * i386-tbl.h: Likewise.
71 2020-09-17 Cooper Qu <<cooper.qu@linux.alibaba.com>>
73 * csky-dis.c (using_abi): New.
74 (parse_csky_dis_options): New function.
75 (get_gr_name): New function.
76 (get_cr_name): New function.
77 (csky_output_operand): Use get_gr_name and get_cr_name to
78 disassemble and add handle of OPRND_TYPE_IMM5b_LS.
79 (print_insn_csky): Parse disassembler options.
80 * csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum.
81 (GENARAL_REG_BANK): Define.
82 (REG_SUPPORT_ALL): Define.
83 (REG_SUPPORT_ALL): New.
85 (REG_SUPPORT_A): Define.
86 (REG_SUPPORT_B): Define.
87 (REG_SUPPORT_C): Define.
88 (REG_SUPPORT_D): Define.
89 (REG_SUPPORT_E): Define.
90 (csky_abiv1_general_regs): New.
91 (csky_abiv1_control_regs): New.
92 (csky_abiv2_general_regs): New.
93 (csky_abiv2_control_regs): New.
94 (get_register_name): New function.
95 (get_register_number): New function.
96 (csky_get_general_reg_name): New function.
97 (csky_get_general_regno): New function.
98 (csky_get_control_reg_name): New function.
99 (csky_get_control_regno): New function.
100 (csky_v2_opcodes): Prefer two oprerans format for bclri and
101 bseti, strengthen the operands legality check of addc, zext
104 2020-09-23 Lili Cui <lili.cui@intel.com>
106 * i386-dis.c (enum): Add REG_0F38D8_PREFIX_1,
107 MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1,
108 MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1,
109 MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1,
110 PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB.
111 (reg_table): New instructions (see prefixes above).
112 (prefix_table): Likewise.
113 (three_byte_table): Likewise.
114 (mod_table): Likewise
115 * i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS,
116 CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS.
117 (cpu_flags): Likewise.
118 (operand_type_init): Likewise.
119 * i386-opc.h (enum): Add CpuKL and CpuWide_KL.
120 (i386_cpu_flags): Add cpukl and cpuwide_kl.
121 * i386-opc.tbl: Add KL and WIDE_KL insns.
122 * i386-init.h: Regenerate.
123 * i386-tbl.h: Likewise.
125 2020-09-21 Alan Modra <amodra@gmail.com>
127 * rx-dis.c (flag_names): Add missing comma.
128 (register_names, flag_names, double_register_names),
129 (double_register_high_names, double_register_low_names),
130 (double_control_register_names, double_condition_names): Remove
133 2020-09-18 David Faust <david.faust@oracle.com>
135 * bpf-desc.c: Regenerate.
136 * bpf-desc.h: Likewise.
137 * bpf-opc.c: Likewise.
138 * bpf-opc.h: Likewise.
140 2020-09-16 Andrew Burgess <andrew.burgess@embecosm.com>
142 * csky-dis.c (csky_get_disassembler): Don't return NULL when there
145 2020-09-16 Alan Modra <amodra@gmail.com>
147 * ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation.
149 2020-09-10 Nick Clifton <nickc@redhat.com>
151 * ppc-dis.c (ppc_symbol_is_valid): New function. Returns false
152 for hidden, local, no-type symbols.
153 (disassemble_init_powerpc): Point the symbol_is_valid field in the
154 info structure at the new function.
156 2020-09-10 Cooper Qu <cooper.qu@linux.alibaba.com>
158 * csky-opc.h (csky_v2_opcodes): Add L2Cache instructions.
159 * testsuite/gas/csky/cskyv2_ck860.d : Adjust to icache.iva
162 2020-09-10 Nick Clifton <nickc@redhat.com>
164 * csky-dis.c (csky_output_operand): Coerce the immediate values to
165 long before printing.
167 2020-09-10 Alan Modra <amodra@gmail.com>
169 * csky-dis.c (csky_output_operand): Don't sprintf str to itself.
171 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
173 * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
176 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
178 * csky-dis.c (csky_output_operand): Add handlers for
179 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
180 OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
181 to support FPUV3 instructions.
182 * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
183 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
184 OPRND_TYPE_DFLOAT_FMOVI.
185 (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
186 OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
187 OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
188 OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
189 OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
190 OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
191 OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
192 OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
193 OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
194 OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
195 OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
196 OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
197 OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
198 (csky_v2_opcodes): Add FPUV3 instructions.
200 2020-09-08 Alex Coplan <alex.coplan@arm.com>
202 * aarch64-dis.c (print_operands): Pass CPU features to
203 aarch64_print_operand().
204 * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
205 preferred disassembly of system registers.
206 (SR_RNG): Refactor to use new SR_FEAT2 macro.
212 (SR_EXPAND_ELx): New.
213 (SR_EXPAND_EL12): New.
214 (aarch64_sys_regs): Specify which registers are only on
215 A-profile, add R-profile system registers.
219 (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
222 2020-09-08 Alex Coplan <alex.coplan@arm.com>
224 * aarch64-tbl.h (aarch64_feature_v8_r): New.
227 (aarch64_opcode_table): Add dfb.
228 * aarch64-opc-2.c: Regenerate.
229 * aarch64-asm-2.c: Regenerate.
230 * aarch64-dis-2.c: Regenerate.
232 2020-09-08 Alex Coplan <alex.coplan@arm.com>
234 * aarch64-dis.c (arch_variant): New.
235 (determine_disassembling_preference): Disassemble according to
237 (select_aarch64_variant): New.
238 (print_insn_aarch64): Set feature set.
240 2020-09-02 Alan Modra <amodra@gmail.com>
242 * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
243 (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9),
244 (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16),
245 (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9),
246 (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID),
247 (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP),
248 (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long
249 for value parameter and update code to suit.
250 (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16),
251 (extract_d22, extract_d23, extract_i9): Use unsigned long variables.
253 2020-09-02 Alan Modra <amodra@gmail.com>
255 * i386-dis.c (OP_E_memory): Don't cast to signed type when
257 (get32, get32s): Use unsigned types in shift expressions.
259 2020-09-02 Alan Modra <amodra@gmail.com>
261 * csky-dis.c (print_insn_csky): Use unsigned type for "given".
263 2020-09-02 Alan Modra <amodra@gmail.com>
265 * crx-dis.c: Whitespace.
266 (print_arg): Use unsigned type for longdisp and mask variables,
267 and for left shift constant.
269 2020-09-02 Alan Modra <amodra@gmail.com>
271 * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
272 * bpf-ibld.c: Regenerate.
273 * epiphany-ibld.c: Regenerate.
274 * fr30-ibld.c: Regenerate.
275 * frv-ibld.c: Regenerate.
276 * ip2k-ibld.c: Regenerate.
277 * iq2000-ibld.c: Regenerate.
278 * lm32-ibld.c: Regenerate.
279 * m32c-ibld.c: Regenerate.
280 * m32r-ibld.c: Regenerate.
281 * mep-ibld.c: Regenerate.
282 * mt-ibld.c: Regenerate.
283 * or1k-ibld.c: Regenerate.
284 * xc16x-ibld.c: Regenerate.
285 * xstormy16-ibld.c: Regenerate.
287 2020-09-02 Alan Modra <amodra@gmail.com>
289 * bfin-dis.c (MASKBITS): Use SIGNBIT.
291 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
293 * csky-opc.h (csky_v2_opcodes): Move divul and divsl
294 to CSKYV2_ISA_3E3R3 instruction set.
296 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
298 * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
300 2020-09-01 Alan Modra <amodra@gmail.com>
302 * mep-ibld.c: Regenerate.
304 2020-08-31 Cooper Qu <cooper.qu@linux.alibaba.com>
306 * csky-dis.c (csky_output_operand): Assign dis_info.value for
309 2020-08-30 Alan Modra <amodra@gmail.com>
311 * cr16-dis.c: Formatting.
312 (parameter): Delete struct typedef. Use dwordU instead
314 (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
316 (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
318 2020-08-29 Alan Modra <amodra@gmail.com>
321 * csky-opc.h (MAX_OPRND_NUM): Define to 5.
322 (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
324 2020-08-28 Alan Modra <amodra@gmail.com>
328 * cgen-ibld.in (insert_1): Use 1UL in forming mask.
329 (extract_normal): Likewise.
330 (insert_normal): Likewise, and move past zero length test.
331 (put_insn_int_value): Handle mask for zero length, use 1UL.
332 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
333 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
334 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
335 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
337 2020-08-28 Cooper Qu <cooper.qu@linux.alibaba.com>
339 * csky-dis.c (CSKY_DEFAULT_ISA): Define.
340 (csky_dis_info): Add member isa.
341 (csky_find_inst_info): Skip instructions that do not belong to
343 (csky_get_disassembler): Get infomation from attribute section.
344 (print_insn_csky): Set defualt ISA flag.
345 * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
346 * csky-opc.h (struct csky_opcode): Change isa_flag16 and
347 isa_flag32'type to unsigned 64 bits.
349 2020-08-26 Jose E. Marchesi <jemarch@gnu.org>
351 * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
353 2020-08-26 David Faust <david.faust@oracle.com>
355 * bpf-desc.c: Regenerate.
356 * bpf-desc.h: Likewise.
357 * bpf-opc.c: Likewise.
358 * bpf-opc.h: Likewise.
359 * disassemble.c (disassemble_init_for_target): Set bits for xBPF
360 ISA when appropriate.
362 2020-08-25 Alan Modra <amodra@gmail.com>
365 * vax-dis.c (parse_disassembler_options): Always add at least one
366 to entry_addr_total_slots.
368 2020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
370 * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
371 in other CPUs to speed up disassembling.
372 * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
373 Change plsli.u16 to plsli.16, change sync's operand format.
375 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
377 * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
379 2020-08-21 Nick Clifton <nickc@redhat.com>
381 * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
384 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
386 * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
388 2020-08-19 Alan Modra <amodra@gmail.com>
390 * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
393 2020-08-18 Peter Bergner <bergner@linux.ibm.com>
395 * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
396 <xvcvbf16spn>: ...to this.
398 2020-08-12 Alex Coplan <alex.coplan@arm.com>
400 * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
402 2020-08-12 Nick Clifton <nickc@redhat.com>
404 * po/sr.po: Updated Serbian translation.
406 2020-08-11 Alan Modra <amodra@gmail.com>
408 * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
410 2020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
412 * aarch64-opc.c (aarch64_print_operand):
413 (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
414 (aarch64_sys_reg_supported_p): Function removed.
415 (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
416 (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
419 2020-08-10 Alan Modra <amodra@gmail.com>
421 * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
424 2020-08-10 Alan Modra <amodra@gmail.com>
426 * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
427 Enable icbt for power5, miso for power8.
429 2020-08-10 Alan Modra <amodra@gmail.com>
431 * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
432 mtvsrd, and similarly for mfvsrd.
434 2020-08-04 Christian Groessler <chris@groessler.org>
435 Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
437 * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
438 opcodes (special "out" to absolute address).
439 * z8k-opc.h: Regenerate.
441 2020-07-30 H.J. Lu <hongjiu.lu@intel.com>
444 * i386-opc.h (Prefix_Disp8): New.
445 (Prefix_Disp16): Likewise.
446 (Prefix_Disp32): Likewise.
447 (Prefix_Load): Likewise.
448 (Prefix_Store): Likewise.
449 (Prefix_VEX): Likewise.
450 (Prefix_VEX3): Likewise.
451 (Prefix_EVEX): Likewise.
452 (Prefix_REX): Likewise.
453 (Prefix_NoOptimize): Likewise.
454 * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
455 * i386-tbl.h: Regenerated.
457 2020-07-29 Andreas Arnez <arnez@linux.ibm.com>
459 * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
460 default case with abort() instead of printing an error message and
461 continuing, to avoid a maybe-uninitialized warning.
463 2020-07-24 Nick Clifton <nickc@redhat.com>
465 * po/de.po: Updated German translation.
467 2020-07-21 Jan Beulich <jbeulich@suse.com>
469 * i386-dis.c (OP_E_memory): Revert previous change.
471 2020-07-15 H.J. Lu <hongjiu.lu@intel.com>
474 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
475 without base nor index registers.
477 2020-07-15 Jan Beulich <jbeulich@suse.com>
479 * i386-dis.c (putop): Move 'V' and 'W' handling.
481 2020-07-15 Jan Beulich <jbeulich@suse.com>
483 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
484 construct for push/pop of register.
485 (putop): Honor cond when handling 'P'. Drop handling of plain
488 2020-07-15 Jan Beulich <jbeulich@suse.com>
490 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
491 description. Drop '&' description. Use P for push of immediate,
492 pushf/popf, enter, and leave. Use %LP for lret/retf.
493 (dis386_twobyte): Use P for push/pop of fs/gs.
494 (reg_table): Use P for push/pop. Use @ for near call/jmp.
495 (x86_64_table): Use P for far call/jmp.
496 (putop): Drop handling of 'U' and '&'. Move and adjust handling
497 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
499 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
500 and dqw_mode (unconditional).
502 2020-07-14 H.J. Lu <hongjiu.lu@intel.com>
505 * i386-dis.c (OP_E_memory): Without base nor index registers,
506 32-bit displacement to 64 bits.
508 2020-07-14 Claudiu Zissulescu <claziss@gmail.com>
510 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
511 faulty double register pair is detected.
513 2020-07-14 Jan Beulich <jbeulich@suse.com>
515 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
517 2020-07-14 Jan Beulich <jbeulich@suse.com>
519 * i386-dis.c (OP_R, Rm): Delete.
520 (MOD_0F24, MOD_0F26): Rename to ...
521 (X86_64_0F24, X86_64_0F26): ... respectively.
522 (dis386): Update 'L' and 'Z' comments.
523 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
525 (mod_table): Move opcode 0F24 and 0F26 entries ...
526 (x86_64_table): ... here.
527 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
530 2020-07-14 Jan Beulich <jbeulich@suse.com>
532 * i386-dis.c (Rd, Rdq, MaskR): Delete.
533 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
534 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
535 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
536 MOD_EVEX_0F387C): New enumerators.
537 (reg_table): Use Edq for rdssp.
538 (prefix_table): Use Edq for incssp.
539 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
540 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
541 ktest*, and kshift*. Use Edq / MaskE for kmov*.
542 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
543 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
544 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
545 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
546 0F3828_P_1 and 0F3838_P_1.
547 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
548 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
550 2020-07-14 Jan Beulich <jbeulich@suse.com>
552 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
553 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
554 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
555 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
556 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
557 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
558 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
559 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
560 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
561 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
562 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
563 (reg_table, prefix_table, three_byte_table, vex_table,
564 vex_len_table, mod_table, rm_table): Replace / remove respective
566 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
567 of PREFIX_DATA in used_prefixes.
569 2020-07-14 Jan Beulich <jbeulich@suse.com>
571 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
572 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
573 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
574 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
575 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
576 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
577 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
578 VEX_W_0F3A33_L_0): Delete.
579 (dis386): Adjust "BW" description.
580 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
581 0F3A31, 0F3A32, and 0F3A33.
582 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
584 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
587 2020-07-14 Jan Beulich <jbeulich@suse.com>
589 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
590 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
591 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
592 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
593 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
594 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
595 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
596 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
597 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
598 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
599 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
600 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
601 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
602 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
603 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
604 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
605 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
606 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
607 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
608 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
609 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
610 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
611 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
612 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
613 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
614 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
615 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
616 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
617 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
618 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
619 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
620 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
621 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
622 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
623 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
624 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
625 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
626 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
627 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
628 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
629 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
630 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
631 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
632 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
633 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
634 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
635 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
636 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
637 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
638 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
639 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
640 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
641 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
642 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
643 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
644 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
645 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
646 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
647 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
648 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
649 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
650 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
651 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
652 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
653 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
654 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
655 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
656 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
657 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
658 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
659 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
660 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
661 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
662 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
663 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
664 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
665 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
666 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
667 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
668 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
669 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
670 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
671 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
672 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
673 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
674 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
675 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
676 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
677 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
678 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
679 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
680 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
681 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
682 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
683 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
684 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
685 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
686 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
687 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
688 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
689 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
690 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
691 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
692 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
693 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
694 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
695 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
696 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
697 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
698 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
699 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
700 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
701 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
702 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
703 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
704 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
705 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
706 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
707 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
708 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
709 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
710 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
711 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
712 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
713 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
714 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
715 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
716 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
717 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
718 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
719 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
720 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
721 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
722 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
723 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
724 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
725 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
726 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
727 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
728 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
729 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
730 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
731 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
732 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
733 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
734 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
735 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
736 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
737 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
738 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
739 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
740 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
741 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
742 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
743 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
744 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
745 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
746 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
747 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
748 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
749 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
750 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
751 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
752 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
753 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
754 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
755 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
756 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
757 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
758 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
759 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
760 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
761 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
762 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
763 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
764 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
765 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
766 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
767 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
768 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
769 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
770 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
771 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
772 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
773 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
774 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
775 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
776 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
777 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
778 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
779 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
780 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
781 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
782 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
783 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
784 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
785 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
786 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
787 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
788 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
789 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
790 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
791 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
792 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
793 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
794 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
795 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
796 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
797 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
798 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
799 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
800 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
801 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
802 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
803 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
804 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
805 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
806 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
807 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
808 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
809 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
810 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
811 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
812 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
813 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
814 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
815 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
816 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
817 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
818 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
819 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
820 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
821 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
822 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
823 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
824 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
825 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
826 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
827 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
828 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
829 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
830 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
831 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
832 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
833 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
834 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
835 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
836 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
837 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
838 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
839 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
840 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
841 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
842 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
843 EVEX_W_0F3A72_P_2): Rename to ...
844 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
845 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
846 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
847 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
848 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
849 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
850 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
851 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
852 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
853 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
854 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
855 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
856 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
857 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
858 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
859 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
860 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
861 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
862 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
863 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
864 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
865 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
866 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
867 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
868 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
869 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
870 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
871 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
872 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
873 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
874 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
875 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
876 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
877 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
878 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
879 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
880 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
881 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
882 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
883 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
884 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
885 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
886 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
887 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
888 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
889 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
890 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
891 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
892 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
893 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
894 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
895 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
896 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
897 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
898 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
899 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
900 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
901 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
902 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
903 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
904 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
905 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
906 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
907 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
908 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
909 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
910 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
911 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
912 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
913 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
914 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
915 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
917 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
918 vex_w_table, mod_table): Replace / remove respective entries.
919 (print_insn): Move up dp->prefix_requirement handling. Handle
921 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
922 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
923 Replace / remove respective entries.
925 2020-07-14 Jan Beulich <jbeulich@suse.com>
927 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
928 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
929 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
930 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
931 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
933 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
934 0F2C, 0F2D, 0F2E, and 0F2F.
935 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
938 2020-07-14 Jan Beulich <jbeulich@suse.com>
940 * i386-dis.c (OP_VexR, VexScalarR): New.
941 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
942 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
943 need_vex_reg): Delete.
944 (prefix_table): Replace VexScalar by VexScalarR and
945 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
946 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
947 (vex_len_table): Replace EXqVexScalarS by EXqS.
948 (get_valid_dis386): Don't set need_vex_reg.
949 (print_insn): Don't initialize need_vex_reg.
950 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
951 q_scalar_swap_mode cases.
952 (OP_EX): Don't check for d_scalar_swap_mode and
954 (OP_VEX): Done check need_vex_reg.
955 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
956 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
957 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
959 2020-07-14 Jan Beulich <jbeulich@suse.com>
961 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
962 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
963 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
964 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
965 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
966 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
967 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
968 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
969 (vex_table): Replace Vex128 by Vex.
970 (vex_len_table): Likewise. Adjust referenced enum names.
971 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
972 referenced enum names.
973 (OP_VEX): Drop vex128_mode and vex256_mode cases.
974 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
976 2020-07-14 Jan Beulich <jbeulich@suse.com>
978 * i386-dis.c (dis386): "LW" description now applies to "DQ".
979 (putop): Handle "DQ". Don't handle "LW" anymore.
980 (prefix_table, mod_table): Replace %LW by %DQ.
981 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
983 2020-07-14 Jan Beulich <jbeulich@suse.com>
985 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
986 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
987 d_scalar_swap_mode case handling. Move shift adjsutment into
988 the case its applicable to.
990 2020-07-14 Jan Beulich <jbeulich@suse.com>
992 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
993 (EXbScalar, EXwScalar): Fold to ...
994 (EXbwUnit): ... this.
995 (b_scalar_mode, w_scalar_mode): Fold to ...
996 (bw_unit_mode): ... this.
997 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
998 w_scalar_mode handling by bw_unit_mode one.
999 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
1001 * i386-dis-evex-prefix.h: ... here.
1003 2020-07-14 Jan Beulich <jbeulich@suse.com>
1005 * i386-dis.c (PCMPESTR_Fixup): Delete.
1006 (dis386): Adjust "LQ" description.
1007 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
1008 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
1009 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
1010 vpcmpestrm, and vpcmpestri.
1011 (putop): Honor "cond" when handling LQ.
1012 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
1013 vcvtsi2ss and vcvtusi2ss.
1014 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
1015 vcvtsi2sd and vcvtusi2sd.
1017 2020-07-14 Jan Beulich <jbeulich@suse.com>
1019 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
1020 (simd_cmp_op): Add const.
1021 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
1022 (CMP_Fixup): Handle VEX case.
1023 (prefix_table): Replace VCMP by CMP.
1024 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
1026 2020-07-14 Jan Beulich <jbeulich@suse.com>
1028 * i386-dis.c (MOVBE_Fixup): Delete.
1030 (prefix_table): Use Mv for movbe entries.
1032 2020-07-14 Jan Beulich <jbeulich@suse.com>
1034 * i386-dis.c (CRC32_Fixup): Delete.
1035 (prefix_table): Use Eb/Ev for crc32 entries.
1037 2020-07-14 Jan Beulich <jbeulich@suse.com>
1039 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
1040 Conditionalize invocations of "USED_REX (0)".
1042 2020-07-14 Jan Beulich <jbeulich@suse.com>
1044 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
1045 CH, DH, BH, AX, DX): Delete.
1046 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
1047 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
1048 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
1050 2020-07-10 Lili Cui <lili.cui@intel.com>
1052 * i386-dis.c (TMM): New.
1055 (MVexSIBMEM): Likewise.
1056 (tmm_mode): Likewise.
1057 (vex_sibmem_mode): Likewise.
1058 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
1059 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
1060 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
1061 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
1062 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
1063 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
1064 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
1065 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
1066 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
1067 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
1068 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
1069 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
1070 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
1071 (PREFIX_VEX_0F3849_X86_64): Likewise.
1072 (PREFIX_VEX_0F384B_X86_64): Likewise.
1073 (PREFIX_VEX_0F385C_X86_64): Likewise.
1074 (PREFIX_VEX_0F385E_X86_64): Likewise.
1075 (X86_64_VEX_0F3849): Likewise.
1076 (X86_64_VEX_0F384B): Likewise.
1077 (X86_64_VEX_0F385C): Likewise.
1078 (X86_64_VEX_0F385E): Likewise.
1079 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
1080 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
1081 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
1082 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
1083 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
1084 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
1085 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
1086 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
1087 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
1088 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
1089 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
1090 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
1091 (VEX_W_0F3849_X86_64_P_0): Likewise.
1092 (VEX_W_0F3849_X86_64_P_2): Likewise.
1093 (VEX_W_0F3849_X86_64_P_3): Likewise.
1094 (VEX_W_0F384B_X86_64_P_1): Likewise.
1095 (VEX_W_0F384B_X86_64_P_2): Likewise.
1096 (VEX_W_0F384B_X86_64_P_3): Likewise.
1097 (VEX_W_0F385C_X86_64_P_1): Likewise.
1098 (VEX_W_0F385E_X86_64_P_0): Likewise.
1099 (VEX_W_0F385E_X86_64_P_1): Likewise.
1100 (VEX_W_0F385E_X86_64_P_2): Likewise.
1101 (VEX_W_0F385E_X86_64_P_3): Likewise.
1102 (names_tmm): Likewise.
1103 (att_names_tmm): Likewise.
1104 (intel_operand_size): Handle void_mode.
1105 (OP_XMM): Handle tmm_mode.
1108 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
1109 CpuAMX_BF16 and CpuAMX_TILE.
1110 (operand_type_shorthands): Add RegTMM.
1111 (operand_type_init): Likewise.
1112 (operand_types): Add Tmmword.
1113 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1114 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1115 * i386-opc.h (CpuAMX_INT8): New.
1116 (CpuAMX_BF16): Likewise.
1117 (CpuAMX_TILE): Likewise.
1119 (Tmmword): Likewise.
1120 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
1121 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
1122 (i386_operand_type): Add tmmword.
1123 * i386-opc.tbl: Add AMX instructions.
1124 * i386-reg.tbl: Add AMX registers.
1125 * i386-init.h: Regenerated.
1126 * i386-tbl.h: Likewise.
1128 2020-07-08 Jan Beulich <jbeulich@suse.com>
1130 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
1131 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
1133 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
1134 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
1136 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
1137 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
1138 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
1139 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
1140 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
1141 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
1142 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
1143 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
1144 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
1145 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
1146 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
1147 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
1148 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
1149 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
1150 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
1151 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
1152 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
1153 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
1154 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
1155 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
1156 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
1157 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
1158 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
1159 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
1160 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
1161 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
1162 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
1163 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
1164 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
1165 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
1166 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
1167 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
1168 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
1169 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
1170 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
1171 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
1172 (reg_table): Re-order XOP entries. Adjust their operands.
1173 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
1174 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
1175 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
1176 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
1177 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
1178 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
1179 entries by references ...
1180 (vex_len_table): ... to resepctive new entries here. For several
1181 new and existing entries reference ...
1182 (vex_w_table): ... new entries here.
1183 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
1185 2020-07-08 Jan Beulich <jbeulich@suse.com>
1187 * i386-dis.c (XMVexScalarI4): Define.
1188 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
1189 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
1190 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
1191 (vex_len_table): Move scalar FMA4 entries ...
1192 (prefix_table): ... here.
1193 (OP_REG_VexI4): Handle scalar_mode.
1194 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
1195 * i386-tbl.h: Re-generate.
1197 2020-07-08 Jan Beulich <jbeulich@suse.com>
1199 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
1200 Vex_2src_2): Delete.
1201 (OP_VexW, VexW): New.
1202 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
1203 for shifts and rotates by register.
1205 2020-07-08 Jan Beulich <jbeulich@suse.com>
1207 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
1208 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
1209 OP_EX_VexReg): Delete.
1210 (OP_VexI4, VexI4): New.
1211 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
1212 (prefix_table): ... here.
1213 (print_insn): Drop setting of vex_w_done.
1215 2020-07-08 Jan Beulich <jbeulich@suse.com>
1217 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
1218 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
1219 (xop_table): Replace operands of 4-operand insns.
1220 (OP_REG_VexI4): Move VEX.W based operand swaping here.
1222 2020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
1224 * arc-opc.c (insert_rbd): New function.
1227 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
1230 2020-07-07 Jan Beulich <jbeulich@suse.com>
1232 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
1233 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
1234 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
1235 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
1237 (putop): Handle "BW".
1238 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
1239 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
1241 * i386-dis-evex-prefix.h: ... here.
1243 2020-07-06 Jan Beulich <jbeulich@suse.com>
1245 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
1246 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
1247 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
1248 VEX_W_0FXOP_09_83): New enumerators.
1249 (xop_table): Reference the above.
1250 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
1251 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
1252 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
1253 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
1255 2020-07-06 Jan Beulich <jbeulich@suse.com>
1257 * i386-dis.c (EVEX_W_0F3838_P_1,
1258 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
1259 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
1260 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
1261 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
1262 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
1263 (putop): Centralize management of last[]. Delete SAVE_LAST.
1264 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
1265 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
1266 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
1267 * i386-dis-evex-prefix.h: here.
1269 2020-07-06 Jan Beulich <jbeulich@suse.com>
1271 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
1272 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
1273 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
1274 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
1276 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
1277 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
1278 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
1279 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
1280 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
1281 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
1282 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1283 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
1284 these, respectively.
1285 * i386-dis-evex-len.h: Adjust comments.
1286 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
1287 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1288 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1289 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
1290 MOD_EVEX_0F385B_P_2_W_1 table entries.
1291 * i386-dis-evex-w.h: Reference mod_table[] for
1292 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
1295 2020-07-06 Jan Beulich <jbeulich@suse.com>
1297 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
1298 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
1300 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
1301 Likewise. Mark 256-bit entries invalid.
1303 2020-07-06 Jan Beulich <jbeulich@suse.com>
1305 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1306 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1307 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1308 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1309 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1310 PREFIX_EVEX_0F382B): Delete.
1311 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
1312 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
1313 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
1314 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
1315 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
1317 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
1318 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
1319 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
1320 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
1322 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
1323 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
1324 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1325 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1326 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1327 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1328 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1329 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1330 PREFIX_EVEX_0F382B): Remove table entries.
1331 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
1332 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
1333 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1335 2020-07-06 Jan Beulich <jbeulich@suse.com>
1337 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1338 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1340 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1341 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1342 EVEX_LEN_0F3A01_P_2_W_1 table entries.
1343 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1346 2020-07-06 Jan Beulich <jbeulich@suse.com>
1348 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1349 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1350 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1351 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1352 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1353 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1354 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1355 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1356 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1359 2020-07-06 Jan Beulich <jbeulich@suse.com>
1361 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1362 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1363 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1365 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1367 * i386-dis-evex.h (evex_table): Reference VEX table entry for
1369 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1371 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1373 2020-07-06 Jan Beulich <jbeulich@suse.com>
1375 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1376 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1377 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1378 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1379 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1380 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1381 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1382 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1383 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1384 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1385 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1386 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1387 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1388 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1389 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1390 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1391 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1392 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1393 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1394 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1395 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1396 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1397 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1398 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1399 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1400 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1401 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1402 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1403 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1404 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1405 (prefix_table): Add EXxEVexR to FMA table entries.
1406 (OP_Rounding): Move abort() invocation.
1407 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1408 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1409 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1410 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1411 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1412 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1413 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1414 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1415 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1416 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1418 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1419 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1420 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1421 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1422 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1423 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1424 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1425 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1426 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1427 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1428 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1429 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1430 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1431 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1432 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1433 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1434 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1435 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1436 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1437 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1438 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1439 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1440 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1441 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1442 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1443 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1444 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1445 Delete table entries.
1446 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1447 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1448 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1451 2020-07-06 Jan Beulich <jbeulich@suse.com>
1453 * i386-dis.c (EXqScalarS): Delete.
1454 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1455 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1457 2020-07-06 Jan Beulich <jbeulich@suse.com>
1459 * i386-dis.c (safe-ctype.h): Include.
1460 (EXdScalar, EXqScalar): Delete.
1461 (d_scalar_mode, q_scalar_mode): Delete.
1462 (prefix_table, vex_len_table): Use EXxmm_md in place of
1463 EXdScalar and EXxmm_mq in place of EXqScalar.
1464 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1465 d_scalar_mode and q_scalar_mode.
1466 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1467 (vmovsd): Use EXxmm_mq.
1469 2020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1472 * arc-dis.c: Fix spelling mistake.
1473 * po/opcodes.pot: Regenerate.
1475 2020-07-06 Nick Clifton <nickc@redhat.com>
1477 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1478 * po/uk.po: Updated Ukranian translation.
1480 2020-07-04 Nick Clifton <nickc@redhat.com>
1482 * configure: Regenerate.
1483 * po/opcodes.pot: Regenerate.
1485 2020-07-04 Nick Clifton <nickc@redhat.com>
1487 Binutils 2.35 branch created.
1489 2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1491 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1492 * i386-opc.h (VexSwapSources): New.
1493 (i386_opcode_modifier): Add vexswapsources.
1494 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1495 with two source operands swapped.
1496 * i386-tbl.h: Regenerated.
1498 2020-06-30 Nelson Chu <nelson.chu@sifive.com>
1500 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1501 unprivileged CSR can also be initialized.
1503 2020-06-29 Alan Modra <amodra@gmail.com>
1505 * arm-dis.c: Use C style comments.
1506 * cr16-opc.c: Likewise.
1507 * ft32-dis.c: Likewise.
1508 * moxie-opc.c: Likewise.
1509 * tic54x-dis.c: Likewise.
1510 * s12z-opc.c: Remove useless comment.
1511 * xgate-dis.c: Likewise.
1513 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1515 * i386-opc.tbl: Add a blank line.
1517 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1519 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1520 (VecSIB128): Renamed to ...
1522 (VecSIB256): Renamed to ...
1524 (VecSIB512): Renamed to ...
1526 (VecSIB): Renamed to ...
1528 (i386_opcode_modifier): Replace vecsib with sib.
1529 * i386-opc.tbl (VecSIB128): New.
1530 (VecSIB256): Likewise.
1531 (VecSIB512): Likewise.
1532 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1533 and VecSIB512, respectively.
1535 2020-06-26 Jan Beulich <jbeulich@suse.com>
1537 * i386-dis.c: Adjust description of I macro.
1538 (x86_64_table): Drop use of I.
1539 (float_mem): Replace use of I.
1540 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1542 2020-06-26 Jan Beulich <jbeulich@suse.com>
1544 * i386-dis.c: (print_insn): Avoid straight assignment to
1545 priv.orig_sizeflag when processing -M sub-options.
1547 2020-06-25 Jan Beulich <jbeulich@suse.com>
1549 * i386-dis.c: Adjust description of J macro.
1550 (dis386, x86_64_table, mod_table): Replace J.
1551 (putop): Remove handling of J.
1553 2020-06-25 Jan Beulich <jbeulich@suse.com>
1555 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1557 2020-06-25 Jan Beulich <jbeulich@suse.com>
1559 * i386-dis.c: Adjust description of "LQ" macro.
1560 (dis386_twobyte): Use LQ for sysret.
1561 (putop): Adjust handling of LQ.
1563 2020-06-22 Nelson Chu <nelson.chu@sifive.com>
1565 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1566 * riscv-dis.c: Include elfxx-riscv.h.
1568 2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1570 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1572 2020-06-17 Lili Cui <lili.cui@intel.com>
1574 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1576 2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1579 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1580 * i386-opc.tbl: Likewise.
1581 * i386-tbl.h: Regenerated.
1583 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
1585 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1587 2020-06-11 Alex Coplan <alex.coplan@arm.com>
1589 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1590 (SR_CORE): Likewise.
1591 (SR_FEAT): Likewise.
1593 (SR_V8_1): Likewise.
1594 (SR_V8_2): Likewise.
1595 (SR_V8_3): Likewise.
1596 (SR_V8_4): Likewise.
1599 (SR_SSBS): Likewise.
1601 (SR_ID_PFR2): Likewise.
1602 (SR_PROFILE): Likewise.
1603 (SR_MEMTAG): Likewise.
1604 (SR_SCXTNUM): Likewise.
1605 (aarch64_sys_regs): Refactor to store feature information in the table.
1606 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1607 that now describe their own features.
1608 (aarch64_pstatefield_supported_p): Likewise.
1610 2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1612 * i386-dis.c (prefix_table): Fix a typo in comments.
1614 2020-06-09 Jan Beulich <jbeulich@suse.com>
1616 * i386-dis.c (rex_ignored): Delete.
1617 (ckprefix): Drop rex_ignored initialization.
1618 (get_valid_dis386): Drop setting of rex_ignored.
1619 (print_insn): Drop checking of rex_ignored. Don't record data
1620 size prefix as used with VEX-and-alike encodings.
1622 2020-06-09 Jan Beulich <jbeulich@suse.com>
1624 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1625 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1626 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1627 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1628 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1629 VEX_0F12, and VEX_0F16.
1630 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1631 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1632 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1633 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1634 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1635 MOD_VEX_0F16_PREFIX_2 entries.
1637 2020-06-09 Jan Beulich <jbeulich@suse.com>
1639 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1640 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1641 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1642 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1643 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1644 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1645 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1646 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1647 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1648 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1649 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1650 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1651 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1652 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1653 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1654 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1655 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1656 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1657 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1658 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1659 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1660 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1661 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1662 EVEX_W_0FC6_P_2): Delete.
1663 (print_insn): Add EVEX.W vs embedded prefix consistency check
1664 to prefix validation.
1665 * i386-dis-evex.h (evex_table): Don't further descend for
1666 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1667 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1669 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1670 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1671 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1672 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1673 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1674 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1675 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1676 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1677 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1678 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1679 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1680 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1681 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1682 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1683 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1684 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1685 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1686 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1687 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1688 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1689 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1690 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1691 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1692 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1693 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1694 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1695 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1697 2020-06-09 Jan Beulich <jbeulich@suse.com>
1699 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1700 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1701 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1703 (print_insn): Drop pointless check against bad_opcode. Split
1704 prefix validation into legacy and VEX-and-alike parts.
1705 (putop): Re-work 'X' macro handling.
1707 2020-06-09 Jan Beulich <jbeulich@suse.com>
1709 * i386-dis.c (MOD_0F51): Rename to ...
1710 (MOD_0F50): ... this.
1712 2020-06-08 Alex Coplan <alex.coplan@arm.com>
1714 * arm-dis.c (arm_opcodes): Add dfb.
1715 (thumb32_opcodes): Add dfb.
1717 2020-06-08 Jan Beulich <jbeulich@suse.com>
1719 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1721 2020-06-06 Alan Modra <amodra@gmail.com>
1723 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1725 2020-06-05 Alan Modra <amodra@gmail.com>
1727 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1728 size is large enough.
1730 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1732 * disassemble.c (disassemble_init_for_target): Set endian_code for
1734 * bpf-desc.c: Regenerate.
1735 * bpf-opc.c: Likewise.
1736 * bpf-dis.c: Likewise.
1738 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1740 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1741 (cgen_put_insn_value): Likewise.
1742 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1743 * cgen-dis.in (print_insn): Likewise.
1744 * cgen-ibld.in (insert_1): Likewise.
1745 (insert_1): Likewise.
1746 (insert_insn_normal): Likewise.
1747 (extract_1): Likewise.
1748 * bpf-dis.c: Regenerate.
1749 * bpf-ibld.c: Likewise.
1750 * bpf-ibld.c: Likewise.
1751 * cgen-dis.in: Likewise.
1752 * cgen-ibld.in: Likewise.
1753 * cgen-opc.c: Likewise.
1754 * epiphany-dis.c: Likewise.
1755 * epiphany-ibld.c: Likewise.
1756 * fr30-dis.c: Likewise.
1757 * fr30-ibld.c: Likewise.
1758 * frv-dis.c: Likewise.
1759 * frv-ibld.c: Likewise.
1760 * ip2k-dis.c: Likewise.
1761 * ip2k-ibld.c: Likewise.
1762 * iq2000-dis.c: Likewise.
1763 * iq2000-ibld.c: Likewise.
1764 * lm32-dis.c: Likewise.
1765 * lm32-ibld.c: Likewise.
1766 * m32c-dis.c: Likewise.
1767 * m32c-ibld.c: Likewise.
1768 * m32r-dis.c: Likewise.
1769 * m32r-ibld.c: Likewise.
1770 * mep-dis.c: Likewise.
1771 * mep-ibld.c: Likewise.
1772 * mt-dis.c: Likewise.
1773 * mt-ibld.c: Likewise.
1774 * or1k-dis.c: Likewise.
1775 * or1k-ibld.c: Likewise.
1776 * xc16x-dis.c: Likewise.
1777 * xc16x-ibld.c: Likewise.
1778 * xstormy16-dis.c: Likewise.
1779 * xstormy16-ibld.c: Likewise.
1781 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1783 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1784 (print_insn_): Handle instruction endian.
1785 * bpf-dis.c: Regenerate.
1786 * bpf-desc.c: Regenerate.
1787 * epiphany-dis.c: Likewise.
1788 * epiphany-desc.c: Likewise.
1789 * fr30-dis.c: Likewise.
1790 * fr30-desc.c: Likewise.
1791 * frv-dis.c: Likewise.
1792 * frv-desc.c: Likewise.
1793 * ip2k-dis.c: Likewise.
1794 * ip2k-desc.c: Likewise.
1795 * iq2000-dis.c: Likewise.
1796 * iq2000-desc.c: Likewise.
1797 * lm32-dis.c: Likewise.
1798 * lm32-desc.c: Likewise.
1799 * m32c-dis.c: Likewise.
1800 * m32c-desc.c: Likewise.
1801 * m32r-dis.c: Likewise.
1802 * m32r-desc.c: Likewise.
1803 * mep-dis.c: Likewise.
1804 * mep-desc.c: Likewise.
1805 * mt-dis.c: Likewise.
1806 * mt-desc.c: Likewise.
1807 * or1k-dis.c: Likewise.
1808 * or1k-desc.c: Likewise.
1809 * xc16x-dis.c: Likewise.
1810 * xc16x-desc.c: Likewise.
1811 * xstormy16-dis.c: Likewise.
1812 * xstormy16-desc.c: Likewise.
1814 2020-06-03 Nick Clifton <nickc@redhat.com>
1816 * po/sr.po: Updated Serbian translation.
1818 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
1820 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1821 (riscv_get_priv_spec_class): Likewise.
1823 2020-06-01 Alan Modra <amodra@gmail.com>
1825 * bpf-desc.c: Regenerate.
1827 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1828 David Faust <david.faust@oracle.com>
1830 * bpf-desc.c: Regenerate.
1831 * bpf-opc.h: Likewise.
1832 * bpf-opc.c: Likewise.
1833 * bpf-dis.c: Likewise.
1835 2020-05-28 Alan Modra <amodra@gmail.com>
1837 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1840 2020-05-28 Alan Modra <amodra@gmail.com>
1842 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1844 (print_insn_ns32k): Revert last change.
1846 2020-05-28 Nick Clifton <nickc@redhat.com>
1848 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1851 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1853 Fix extraction of signed constants in nios2 disassembler (again).
1855 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1856 extractions of signed fields.
1858 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1860 * s390-opc.txt: Relocate vector load/store instructions with
1861 additional alignment parameter and change architecture level
1862 constraint from z14 to z13.
1864 2020-05-21 Alan Modra <amodra@gmail.com>
1866 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1867 * sparc-dis.c: Likewise.
1868 * tic4x-dis.c: Likewise.
1869 * xtensa-dis.c: Likewise.
1870 * bpf-desc.c: Regenerate.
1871 * epiphany-desc.c: Regenerate.
1872 * fr30-desc.c: Regenerate.
1873 * frv-desc.c: Regenerate.
1874 * ip2k-desc.c: Regenerate.
1875 * iq2000-desc.c: Regenerate.
1876 * lm32-desc.c: Regenerate.
1877 * m32c-desc.c: Regenerate.
1878 * m32r-desc.c: Regenerate.
1879 * mep-asm.c: Regenerate.
1880 * mep-desc.c: Regenerate.
1881 * mt-desc.c: Regenerate.
1882 * or1k-desc.c: Regenerate.
1883 * xc16x-desc.c: Regenerate.
1884 * xstormy16-desc.c: Regenerate.
1886 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
1888 * riscv-opc.c (riscv_ext_version_table): The table used to store
1889 all information about the supported spec and the corresponding ISA
1890 versions. Currently, only Zicsr is supported to verify the
1891 correctness of Z sub extension settings. Others will be supported
1892 in the future patches.
1893 (struct isa_spec_t, isa_specs): List for all supported ISA spec
1894 classes and the corresponding strings.
1895 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
1896 spec class by giving a ISA spec string.
1897 * riscv-opc.c (struct priv_spec_t): New structure.
1898 (struct priv_spec_t priv_specs): List for all supported privilege spec
1899 classes and the corresponding strings.
1900 (riscv_get_priv_spec_class): New function. Get the corresponding
1901 privilege spec class by giving a spec string.
1902 (riscv_get_priv_spec_name): New function. Get the corresponding
1903 privilege spec string by giving a CSR version class.
1904 * riscv-dis.c: Updated since DECLARE_CSR is changed.
1905 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
1906 according to the chosen version. Build a hash table riscv_csr_hash to
1907 store the valid CSR for the chosen pirv verison. Dump the direct
1908 CSR address rather than it's name if it is invalid.
1909 (parse_riscv_dis_option_without_args): New function. Parse the options
1911 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
1912 parse the options without arguments first, and then handle the options
1913 with arguments. Add the new option -Mpriv-spec, which has argument.
1914 * riscv-dis.c (print_riscv_disassembler_options): Add description
1915 about the new OBJDUMP option.
1917 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
1919 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
1920 WC values on POWER10 sync, dcbf and wait instructions.
1921 (insert_pl, extract_pl): New functions.
1922 (L2OPT, LS, WC): Use insert_ls and extract_ls.
1923 (LS3): New , 3-bit L for sync.
1924 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
1925 (SC2, PL): New, 2-bit SC and PL for sync and wait.
1926 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
1927 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
1928 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
1929 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
1930 <wait>: Enable PL operand on POWER10.
1931 <dcbf>: Enable L3OPT operand on POWER10.
1932 <sync>: Enable SC2 operand on POWER10.
1934 2020-05-19 Stafford Horne <shorne@gmail.com>
1937 * or1k-asm.c: Regenerate.
1938 * or1k-desc.c: Regenerate.
1939 * or1k-desc.h: Regenerate.
1940 * or1k-dis.c: Regenerate.
1941 * or1k-ibld.c: Regenerate.
1942 * or1k-opc.c: Regenerate.
1943 * or1k-opc.h: Regenerate.
1944 * or1k-opinst.c: Regenerate.
1946 2020-05-11 Alan Modra <amodra@gmail.com>
1948 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
1951 2020-05-11 Alan Modra <amodra@gmail.com>
1953 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
1954 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
1956 2020-05-11 Alan Modra <amodra@gmail.com>
1958 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
1960 2020-05-11 Alan Modra <amodra@gmail.com>
1962 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
1963 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
1965 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1967 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
1970 2020-05-11 Alan Modra <amodra@gmail.com>
1972 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
1973 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
1974 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
1975 (prefix_opcodes): Add xxeval.
1977 2020-05-11 Alan Modra <amodra@gmail.com>
1979 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
1980 xxgenpcvwm, xxgenpcvdm.
1982 2020-05-11 Alan Modra <amodra@gmail.com>
1984 * ppc-opc.c (MP, VXVAM_MASK): Define.
1985 (VXVAPS_MASK): Use VXVA_MASK.
1986 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
1987 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
1988 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
1989 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
1991 2020-05-11 Alan Modra <amodra@gmail.com>
1992 Peter Bergner <bergner@linux.ibm.com>
1994 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
1996 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
1997 YMSK2, XA6a, XA6ap, XB6a entries.
1998 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
1999 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
2001 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
2002 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
2003 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
2004 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
2005 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
2006 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
2007 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
2008 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
2009 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
2010 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
2011 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
2012 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
2013 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
2014 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
2016 2020-05-11 Alan Modra <amodra@gmail.com>
2018 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
2019 (insert_xts, extract_xts): New functions.
2020 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
2021 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
2022 (VXRC_MASK, VXSH_MASK): Define.
2023 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
2024 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
2025 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
2026 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
2027 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
2028 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
2029 xxblendvh, xxblendvw, xxblendvd, xxpermx.
2031 2020-05-11 Alan Modra <amodra@gmail.com>
2033 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
2034 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
2035 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
2036 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
2037 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
2039 2020-05-11 Alan Modra <amodra@gmail.com>
2041 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
2042 (XTP, DQXP, DQXP_MASK): Define.
2043 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
2044 (prefix_opcodes): Add plxvp and pstxvp.
2046 2020-05-11 Alan Modra <amodra@gmail.com>
2048 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
2049 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
2050 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
2052 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2054 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
2056 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2058 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
2060 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
2062 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2064 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
2066 2020-05-11 Alan Modra <amodra@gmail.com>
2068 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
2070 2020-05-11 Alan Modra <amodra@gmail.com>
2072 * ppc-dis.c (ppc_opts): Add "power10" entry.
2073 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
2074 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
2076 2020-05-11 Nick Clifton <nickc@redhat.com>
2078 * po/fr.po: Updated French translation.
2080 2020-04-30 Alex Coplan <alex.coplan@arm.com>
2082 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
2083 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
2084 (operand_general_constraint_met_p): validate
2085 AARCH64_OPND_UNDEFINED.
2086 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
2088 * aarch64-asm-2.c: Regenerated.
2089 * aarch64-dis-2.c: Regenerated.
2090 * aarch64-opc-2.c: Regenerated.
2092 2020-04-29 Nick Clifton <nickc@redhat.com>
2095 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
2098 2020-04-29 Nick Clifton <nickc@redhat.com>
2100 * po/sv.po: Updated Swedish translation.
2102 2020-04-29 Nick Clifton <nickc@redhat.com>
2105 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
2106 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
2107 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
2110 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
2113 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
2114 cmpi only on m68020up and cpu32.
2116 2020-04-20 Sudakshina Das <sudi.das@arm.com>
2118 * aarch64-asm.c (aarch64_ins_none): New.
2119 * aarch64-asm.h (ins_none): New declaration.
2120 * aarch64-dis.c (aarch64_ext_none): New.
2121 * aarch64-dis.h (ext_none): New declaration.
2122 * aarch64-opc.c (aarch64_print_operand): Update case for
2123 AARCH64_OPND_BARRIER_PSB.
2124 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
2125 (AARCH64_OPERANDS): Update inserter/extracter for
2126 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
2127 * aarch64-asm-2.c: Regenerated.
2128 * aarch64-dis-2.c: Regenerated.
2129 * aarch64-opc-2.c: Regenerated.
2131 2020-04-20 Sudakshina Das <sudi.das@arm.com>
2133 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
2134 (aarch64_feature_ras, RAS): Likewise.
2135 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
2136 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
2137 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
2138 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
2139 * aarch64-asm-2.c: Regenerated.
2140 * aarch64-dis-2.c: Regenerated.
2141 * aarch64-opc-2.c: Regenerated.
2143 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
2145 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
2146 (print_insn_neon): Support disassembly of conditional
2149 2020-02-16 David Faust <david.faust@oracle.com>
2151 * bpf-desc.c: Regenerate.
2152 * bpf-desc.h: Likewise.
2153 * bpf-opc.c: Regenerate.
2154 * bpf-opc.h: Likewise.
2156 2020-04-07 Lili Cui <lili.cui@intel.com>
2158 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
2159 (prefix_table): New instructions (see prefixes above).
2160 (rm_table): Likewise
2161 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
2162 CPU_ANY_TSXLDTRK_FLAGS.
2163 (cpu_flags): Add CpuTSXLDTRK.
2164 * i386-opc.h (enum): Add CpuTSXLDTRK.
2165 (i386_cpu_flags): Add cputsxldtrk.
2166 * i386-opc.tbl: Add XSUSPLDTRK insns.
2167 * i386-init.h: Regenerate.
2168 * i386-tbl.h: Likewise.
2170 2020-04-02 Lili Cui <lili.cui@intel.com>
2172 * i386-dis.c (prefix_table): New instructions serialize.
2173 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
2174 CPU_ANY_SERIALIZE_FLAGS.
2175 (cpu_flags): Add CpuSERIALIZE.
2176 * i386-opc.h (enum): Add CpuSERIALIZE.
2177 (i386_cpu_flags): Add cpuserialize.
2178 * i386-opc.tbl: Add SERIALIZE insns.
2179 * i386-init.h: Regenerate.
2180 * i386-tbl.h: Likewise.
2182 2020-03-26 Alan Modra <amodra@gmail.com>
2184 * disassemble.h (opcodes_assert): Declare.
2185 (OPCODES_ASSERT): Define.
2186 * disassemble.c: Don't include assert.h. Include opintl.h.
2187 (opcodes_assert): New function.
2188 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
2189 (bfd_h8_disassemble): Reduce size of data array. Correctly
2190 calculate maxlen. Omit insn decoding when insn length exceeds
2191 maxlen. Exit from nibble loop when looking for E, before
2192 accessing next data byte. Move processing of E outside loop.
2193 Replace tests of maxlen in loop with assertions.
2195 2020-03-26 Alan Modra <amodra@gmail.com>
2197 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
2199 2020-03-25 Alan Modra <amodra@gmail.com>
2201 * z80-dis.c (suffix): Init mybuf.
2203 2020-03-22 Alan Modra <amodra@gmail.com>
2205 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
2206 successflly read from section.
2208 2020-03-22 Alan Modra <amodra@gmail.com>
2210 * arc-dis.c (find_format): Use ISO C string concatenation rather
2211 than line continuation within a string. Don't access needs_limm
2212 before testing opcode != NULL.
2214 2020-03-22 Alan Modra <amodra@gmail.com>
2216 * ns32k-dis.c (print_insn_arg): Update comment.
2217 (print_insn_ns32k): Reduce size of index_offset array, and
2218 initialize, passing -1 to print_insn_arg for args that are not
2219 an index. Don't exit arg loop early. Abort on bad arg number.
2221 2020-03-22 Alan Modra <amodra@gmail.com>
2223 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
2224 * s12z-opc.c: Formatting.
2225 (operands_f): Return an int.
2226 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
2227 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
2228 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
2229 (exg_sex_discrim): Likewise.
2230 (create_immediate_operand, create_bitfield_operand),
2231 (create_register_operand_with_size, create_register_all_operand),
2232 (create_register_all16_operand, create_simple_memory_operand),
2233 (create_memory_operand, create_memory_auto_operand): Don't
2234 segfault on malloc failure.
2235 (z_ext24_decode): Return an int status, negative on fail, zero
2237 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
2238 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
2239 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
2240 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
2241 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
2242 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
2243 (loop_primitive_decode, shift_decode, psh_pul_decode),
2244 (bit_field_decode): Similarly.
2245 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
2246 to return value, update callers.
2247 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
2248 Don't segfault on NULL operand.
2249 (decode_operation): Return OP_INVALID on first fail.
2250 (decode_s12z): Check all reads, returning -1 on fail.
2252 2020-03-20 Alan Modra <amodra@gmail.com>
2254 * metag-dis.c (print_insn_metag): Don't ignore status from
2257 2020-03-20 Alan Modra <amodra@gmail.com>
2259 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
2260 Initialize parts of buffer not written when handling a possible
2261 2-byte insn at end of section. Don't attempt decoding of such
2262 an insn by the 4-byte machinery.
2264 2020-03-20 Alan Modra <amodra@gmail.com>
2266 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
2267 partially filled buffer. Prevent lookup of 4-byte insns when
2268 only VLE 2-byte insns are possible due to section size. Print
2269 ".word" rather than ".long" for 2-byte leftovers.
2271 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
2274 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
2276 2020-03-13 Jan Beulich <jbeulich@suse.com>
2278 * i386-dis.c (X86_64_0D): Rename to ...
2279 (X86_64_0E): ... this.
2281 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
2283 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
2284 * Makefile.in: Regenerated.
2286 2020-03-09 Jan Beulich <jbeulich@suse.com>
2288 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
2290 * i386-tbl.h: Re-generate.
2292 2020-03-09 Jan Beulich <jbeulich@suse.com>
2294 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
2295 vprot*, vpsha*, and vpshl*.
2296 * i386-tbl.h: Re-generate.
2298 2020-03-09 Jan Beulich <jbeulich@suse.com>
2300 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
2301 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
2302 * i386-tbl.h: Re-generate.
2304 2020-03-09 Jan Beulich <jbeulich@suse.com>
2306 * i386-gen.c (set_bitfield): Ignore zero-length field names.
2307 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
2308 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
2309 * i386-tbl.h: Re-generate.
2311 2020-03-09 Jan Beulich <jbeulich@suse.com>
2313 * i386-gen.c (struct template_arg, struct template_instance,
2314 struct template_param, struct template, templates,
2315 parse_template, expand_templates): New.
2316 (process_i386_opcodes): Various local variables moved to
2317 expand_templates. Call parse_template and expand_templates.
2318 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
2319 * i386-tbl.h: Re-generate.
2321 2020-03-06 Jan Beulich <jbeulich@suse.com>
2323 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
2324 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
2325 register and memory source templates. Replace VexW= by VexW*
2327 * i386-tbl.h: Re-generate.
2329 2020-03-06 Jan Beulich <jbeulich@suse.com>
2331 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
2332 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
2333 * i386-tbl.h: Re-generate.
2335 2020-03-06 Jan Beulich <jbeulich@suse.com>
2337 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2338 * i386-tbl.h: Re-generate.
2340 2020-03-06 Jan Beulich <jbeulich@suse.com>
2342 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2343 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2344 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2345 VexW0 on SSE2AVX variants.
2346 (vmovq): Drop NoRex64 from XMM/XMM variants.
2347 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2348 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2349 applicable use VexW0.
2350 * i386-tbl.h: Re-generate.
2352 2020-03-06 Jan Beulich <jbeulich@suse.com>
2354 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2355 * i386-opc.h (Rex64): Delete.
2356 (struct i386_opcode_modifier): Remove rex64 field.
2357 * i386-opc.tbl (crc32): Drop Rex64.
2358 Replace Rex64 with Size64 everywhere else.
2359 * i386-tbl.h: Re-generate.
2361 2020-03-06 Jan Beulich <jbeulich@suse.com>
2363 * i386-dis.c (OP_E_memory): Exclude recording of used address
2364 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2365 addressed memory operands for MPX insns.
2367 2020-03-06 Jan Beulich <jbeulich@suse.com>
2369 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2370 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2371 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2372 (ptwrite): Split into non-64-bit and 64-bit forms.
2373 * i386-tbl.h: Re-generate.
2375 2020-03-06 Jan Beulich <jbeulich@suse.com>
2377 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2379 * i386-tbl.h: Re-generate.
2381 2020-03-04 Jan Beulich <jbeulich@suse.com>
2383 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2384 (prefix_table): Move vmmcall here. Add vmgexit.
2385 (rm_table): Replace vmmcall entry by prefix_table[] escape.
2386 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2387 (cpu_flags): Add CpuSEV_ES entry.
2388 * i386-opc.h (CpuSEV_ES): New.
2389 (union i386_cpu_flags): Add cpusev_es field.
2390 * i386-opc.tbl (vmgexit): New.
2391 * i386-init.h, i386-tbl.h: Re-generate.
2393 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2395 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2397 * i386-opc.h (IGNORESIZE): New.
2398 (DEFAULTSIZE): Likewise.
2399 (IgnoreSize): Removed.
2400 (DefaultSize): Likewise.
2401 (MnemonicSize): New.
2402 (i386_opcode_modifier): Replace ignoresize/defaultsize with
2404 * i386-opc.tbl (IgnoreSize): New.
2405 (DefaultSize): Likewise.
2406 * i386-tbl.h: Regenerated.
2408 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2411 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2414 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2417 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2418 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2419 * i386-tbl.h: Regenerated.
2421 2020-02-26 Alan Modra <amodra@gmail.com>
2423 * aarch64-asm.c: Indent labels correctly.
2424 * aarch64-dis.c: Likewise.
2425 * aarch64-gen.c: Likewise.
2426 * aarch64-opc.c: Likewise.
2427 * alpha-dis.c: Likewise.
2428 * i386-dis.c: Likewise.
2429 * nds32-asm.c: Likewise.
2430 * nfp-dis.c: Likewise.
2431 * visium-dis.c: Likewise.
2433 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
2435 * arc-regs.h (int_vector_base): Make it available for all ARC
2438 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
2440 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2443 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
2445 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2446 c.mv/c.li if rs1 is zero.
2448 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
2450 * i386-gen.c (cpu_flag_init): Replace CpuABM with
2451 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
2453 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
2454 * i386-opc.h (CpuABM): Removed.
2456 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
2457 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2458 popcnt. Remove CpuABM from lzcnt.
2459 * i386-init.h: Regenerated.
2460 * i386-tbl.h: Likewise.
2462 2020-02-17 Jan Beulich <jbeulich@suse.com>
2464 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2465 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2466 VexW1 instead of open-coding them.
2467 * i386-tbl.h: Re-generate.
2469 2020-02-17 Jan Beulich <jbeulich@suse.com>
2471 * i386-opc.tbl (AddrPrefixOpReg): Define.
2472 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2473 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2474 templates. Drop NoRex64.
2475 * i386-tbl.h: Re-generate.
2477 2020-02-17 Jan Beulich <jbeulich@suse.com>
2480 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2481 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2482 into Intel syntax instance (with Unpsecified) and AT&T one
2484 (vcvtneps2bf16): Likewise, along with folding the two so far
2486 * i386-tbl.h: Re-generate.
2488 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2490 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2491 CPU_ANY_SSE4A_FLAGS.
2493 2020-02-17 Alan Modra <amodra@gmail.com>
2495 * i386-gen.c (cpu_flag_init): Correct last change.
2497 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2499 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2502 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2504 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2507 2020-02-14 Jan Beulich <jbeulich@suse.com>
2510 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2511 destination for Cpu64-only variant.
2512 (movzx): Fold patterns.
2513 * i386-tbl.h: Re-generate.
2515 2020-02-13 Jan Beulich <jbeulich@suse.com>
2517 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2518 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2519 CPU_ANY_SSE4_FLAGS entry.
2520 * i386-init.h: Re-generate.
2522 2020-02-12 Jan Beulich <jbeulich@suse.com>
2524 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2525 with Unspecified, making the present one AT&T syntax only.
2526 * i386-tbl.h: Re-generate.
2528 2020-02-12 Jan Beulich <jbeulich@suse.com>
2530 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2531 * i386-tbl.h: Re-generate.
2533 2020-02-12 Jan Beulich <jbeulich@suse.com>
2536 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2537 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2538 Amd64 and Intel64 templates.
2539 (call, jmp): Likewise for far indirect variants. Dro
2541 * i386-tbl.h: Re-generate.
2543 2020-02-11 Jan Beulich <jbeulich@suse.com>
2545 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2546 * i386-opc.h (ShortForm): Delete.
2547 (struct i386_opcode_modifier): Remove shortform field.
2548 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2549 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2550 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2551 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2553 * i386-tbl.h: Re-generate.
2555 2020-02-11 Jan Beulich <jbeulich@suse.com>
2557 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2558 fucompi): Drop ShortForm from operand-less templates.
2559 * i386-tbl.h: Re-generate.
2561 2020-02-11 Alan Modra <amodra@gmail.com>
2563 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2564 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2565 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2566 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2567 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2569 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2571 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2572 (cde_opcodes): Add VCX* instructions.
2574 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2575 Matthew Malcomson <matthew.malcomson@arm.com>
2577 * arm-dis.c (struct cdeopcode32): New.
2578 (CDE_OPCODE): New macro.
2579 (cde_opcodes): New disassembly table.
2580 (regnames): New option to table.
2581 (cde_coprocs): New global variable.
2582 (print_insn_cde): New
2583 (print_insn_thumb32): Use print_insn_cde.
2584 (parse_arm_disassembler_options): Parse coprocN args.
2586 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2589 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2591 * i386-opc.h (AMD64): Removed.
2592 (Intel64): Likewose.
2594 (INTEL64): Likewise.
2595 (INTEL64ONLY): Likewise.
2596 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2597 * i386-opc.tbl (Amd64): New.
2598 (Intel64): Likewise.
2599 (Intel64Only): Likewise.
2600 Replace AMD64 with Amd64. Update sysenter/sysenter with
2601 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2602 * i386-tbl.h: Regenerated.
2604 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2607 * z80-dis.c: Add support for GBZ80 opcodes.
2609 2020-02-04 Alan Modra <amodra@gmail.com>
2611 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2613 2020-02-03 Alan Modra <amodra@gmail.com>
2615 * m32c-ibld.c: Regenerate.
2617 2020-02-01 Alan Modra <amodra@gmail.com>
2619 * frv-ibld.c: Regenerate.
2621 2020-01-31 Jan Beulich <jbeulich@suse.com>
2623 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2624 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2625 (OP_E_memory): Replace xmm_mdq_mode case label by
2626 vex_scalar_w_dq_mode one.
2627 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2629 2020-01-31 Jan Beulich <jbeulich@suse.com>
2631 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2632 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2633 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2634 (intel_operand_size): Drop vex_w_dq_mode case label.
2636 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2638 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2639 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2641 2020-01-30 Alan Modra <amodra@gmail.com>
2643 * m32c-ibld.c: Regenerate.
2645 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2647 * bpf-opc.c: Regenerate.
2649 2020-01-30 Jan Beulich <jbeulich@suse.com>
2651 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2652 (dis386): Use them to replace C2/C3 table entries.
2653 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2654 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2655 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2656 * i386-tbl.h: Re-generate.
2658 2020-01-30 Jan Beulich <jbeulich@suse.com>
2660 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2662 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2664 * i386-tbl.h: Re-generate.
2666 2020-01-30 Alan Modra <amodra@gmail.com>
2668 * tic4x-dis.c (tic4x_dp): Make unsigned.
2670 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2671 Jan Beulich <jbeulich@suse.com>
2674 * i386-dis.c (MOVSXD_Fixup): New function.
2675 (movsxd_mode): New enum.
2676 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2677 (intel_operand_size): Handle movsxd_mode.
2678 (OP_E_register): Likewise.
2680 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2681 register on movsxd. Add movsxd with 16-bit destination register
2682 for AMD64 and Intel64 ISAs.
2683 * i386-tbl.h: Regenerated.
2685 2020-01-27 Tamar Christina <tamar.christina@arm.com>
2688 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2689 * aarch64-asm-2.c: Regenerate
2690 * aarch64-dis-2.c: Likewise.
2691 * aarch64-opc-2.c: Likewise.
2693 2020-01-21 Jan Beulich <jbeulich@suse.com>
2695 * i386-opc.tbl (sysret): Drop DefaultSize.
2696 * i386-tbl.h: Re-generate.
2698 2020-01-21 Jan Beulich <jbeulich@suse.com>
2700 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2702 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2703 * i386-tbl.h: Re-generate.
2705 2020-01-20 Nick Clifton <nickc@redhat.com>
2707 * po/de.po: Updated German translation.
2708 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2709 * po/uk.po: Updated Ukranian translation.
2711 2020-01-20 Alan Modra <amodra@gmail.com>
2713 * hppa-dis.c (fput_const): Remove useless cast.
2715 2020-01-20 Alan Modra <amodra@gmail.com>
2717 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2719 2020-01-18 Nick Clifton <nickc@redhat.com>
2721 * configure: Regenerate.
2722 * po/opcodes.pot: Regenerate.
2724 2020-01-18 Nick Clifton <nickc@redhat.com>
2726 Binutils 2.34 branch created.
2728 2020-01-17 Christian Biesinger <cbiesinger@google.com>
2730 * opintl.h: Fix spelling error (seperate).
2732 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2734 * i386-opc.tbl: Add {vex} pseudo prefix.
2735 * i386-tbl.h: Regenerated.
2737 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2740 * arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2741 (neon_opcodes): Likewise.
2742 (select_arm_features): Make sure we enable MVE bits when selecting
2743 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2746 2020-01-16 Jan Beulich <jbeulich@suse.com>
2748 * i386-opc.tbl: Drop stale comment from XOP section.
2750 2020-01-16 Jan Beulich <jbeulich@suse.com>
2752 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2753 (extractps): Add VexWIG to SSE2AVX forms.
2754 * i386-tbl.h: Re-generate.
2756 2020-01-16 Jan Beulich <jbeulich@suse.com>
2758 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2759 Size64 from and use VexW1 on SSE2AVX forms.
2760 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2761 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2762 * i386-tbl.h: Re-generate.
2764 2020-01-15 Alan Modra <amodra@gmail.com>
2766 * tic4x-dis.c (tic4x_version): Make unsigned long.
2767 (optab, optab_special, registernames): New file scope vars.
2768 (tic4x_print_register): Set up registernames rather than
2769 malloc'd registertable.
2770 (tic4x_disassemble): Delete optable and optable_special. Use
2771 optab and optab_special instead. Throw away old optab,
2772 optab_special and registernames when info->mach changes.
2774 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2777 * z80-dis.c (suffix): Use .db instruction to generate double
2780 2020-01-14 Alan Modra <amodra@gmail.com>
2782 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2783 values to unsigned before shifting.
2785 2020-01-13 Thomas Troeger <tstroege@gmx.de>
2787 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2789 (print_insn_thumb16, print_insn_thumb32): Likewise.
2790 (print_insn): Initialize the insn info.
2791 * i386-dis.c (print_insn): Initialize the insn info fields, and
2794 2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
2796 * arc-opc.c (C_NE): Make it required.
2798 2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
2800 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2801 reserved register name.
2803 2020-01-13 Alan Modra <amodra@gmail.com>
2805 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2806 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2808 2020-01-13 Alan Modra <amodra@gmail.com>
2810 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2811 result of wasm_read_leb128 in a uint64_t and check that bits
2812 are not lost when copying to other locals. Use uint32_t for
2813 most locals. Use PRId64 when printing int64_t.
2815 2020-01-13 Alan Modra <amodra@gmail.com>
2817 * score-dis.c: Formatting.
2818 * score7-dis.c: Formatting.
2820 2020-01-13 Alan Modra <amodra@gmail.com>
2822 * score-dis.c (print_insn_score48): Use unsigned variables for
2823 unsigned values. Don't left shift negative values.
2824 (print_insn_score32): Likewise.
2825 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2827 2020-01-13 Alan Modra <amodra@gmail.com>
2829 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2831 2020-01-13 Alan Modra <amodra@gmail.com>
2833 * fr30-ibld.c: Regenerate.
2835 2020-01-13 Alan Modra <amodra@gmail.com>
2837 * xgate-dis.c (print_insn): Don't left shift signed value.
2838 (ripBits): Formatting, use 1u.
2840 2020-01-10 Alan Modra <amodra@gmail.com>
2842 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2843 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2845 2020-01-10 Alan Modra <amodra@gmail.com>
2847 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2848 and XRREG value earlier to avoid a shift with negative exponent.
2849 * m10200-dis.c (disassemble): Similarly.
2851 2020-01-09 Nick Clifton <nickc@redhat.com>
2854 * z80-dis.c (ld_ii_ii): Use correct cast.
2856 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2859 * z80-dis.c (ld_ii_ii): Use character constant when checking
2862 2020-01-09 Jan Beulich <jbeulich@suse.com>
2864 * i386-dis.c (SEP_Fixup): New.
2866 (dis386_twobyte): Use it for sysenter/sysexit.
2867 (enum x86_64_isa): Change amd64 enumerator to value 1.
2868 (OP_J): Compare isa64 against intel64 instead of amd64.
2869 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2871 * i386-tbl.h: Re-generate.
2873 2020-01-08 Alan Modra <amodra@gmail.com>
2875 * z8k-dis.c: Include libiberty.h
2876 (instr_data_s): Make max_fetched unsigned.
2877 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2878 Don't exceed byte_info bounds.
2879 (output_instr): Make num_bytes unsigned.
2880 (unpack_instr): Likewise for nibl_count and loop.
2881 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2883 * z8k-opc.h: Regenerate.
2885 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
2887 * arc-tbl.h (llock): Use 'LLOCK' as class.
2889 (scond): Use 'SCOND' as class.
2891 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
2894 2020-01-06 Alan Modra <amodra@gmail.com>
2896 * m32c-ibld.c: Regenerate.
2898 2020-01-06 Alan Modra <amodra@gmail.com>
2901 * z80-dis.c (suffix): Don't use a local struct buffer copy.
2902 Peek at next byte to prevent recursion on repeated prefix bytes.
2903 Ensure uninitialised "mybuf" is not accessed.
2904 (print_insn_z80): Don't zero n_fetch and n_used here,..
2905 (print_insn_z80_buf): ..do it here instead.
2907 2020-01-04 Alan Modra <amodra@gmail.com>
2909 * m32r-ibld.c: Regenerate.
2911 2020-01-04 Alan Modra <amodra@gmail.com>
2913 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2915 2020-01-04 Alan Modra <amodra@gmail.com>
2917 * crx-dis.c (match_opcode): Avoid shift left of signed value.
2919 2020-01-04 Alan Modra <amodra@gmail.com>
2921 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2923 2020-01-03 Jan Beulich <jbeulich@suse.com>
2925 * aarch64-tbl.h (aarch64_opcode_table): Use
2926 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2928 2020-01-03 Jan Beulich <jbeulich@suse.com>
2930 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
2931 forms of SUDOT and USDOT.
2933 2020-01-03 Jan Beulich <jbeulich@suse.com>
2935 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
2937 * aarch64-dis-2.c: Re-generate.
2939 2020-01-03 Jan Beulich <jbeulich@suse.com>
2941 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
2943 * aarch64-dis-2.c: Re-generate.
2945 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
2947 * z80-dis.c: Add support for eZ80 and Z80 instructions.
2949 2020-01-01 Alan Modra <amodra@gmail.com>
2951 Update year range in copyright notice of all files.
2953 For older changes see ChangeLog-2019
2955 Copyright (C) 2020 Free Software Foundation, Inc.
2957 Copying and distribution of this file, with or without modification,
2958 are permitted in any medium without royalty provided the copyright
2959 notice and this notice are preserved.
2965 version-control: never
projects / thirdparty / binutils-gdb.git / blob