1 2020-07-30 H.J. Lu <hongjiu.lu@intel.com>
4 * i386-opc.h (Prefix_Disp8): New.
5 (Prefix_Disp16): Likewise.
6 (Prefix_Disp32): Likewise.
7 (Prefix_Load): Likewise.
8 (Prefix_Store): Likewise.
9 (Prefix_VEX): Likewise.
10 (Prefix_VEX3): Likewise.
11 (Prefix_EVEX): Likewise.
12 (Prefix_REX): Likewise.
13 (Prefix_NoOptimize): Likewise.
14 * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
15 * i386-tbl.h: Regenerated.
17 2020-07-29 Andreas Arnez <arnez@linux.ibm.com>
19 * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
20 default case with abort() instead of printing an error message and
21 continuing, to avoid a maybe-uninitialized warning.
23 2020-07-24 Nick Clifton <nickc@redhat.com>
25 * po/de.po: Updated German translation.
27 2020-07-21 Jan Beulich <jbeulich@suse.com>
29 * i386-dis.c (OP_E_memory): Revert previous change.
31 2020-07-15 H.J. Lu <hongjiu.lu@intel.com>
34 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
35 without base nor index registers.
37 2020-07-15 Jan Beulich <jbeulich@suse.com>
39 * i386-dis.c (putop): Move 'V' and 'W' handling.
41 2020-07-15 Jan Beulich <jbeulich@suse.com>
43 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
44 construct for push/pop of register.
45 (putop): Honor cond when handling 'P'. Drop handling of plain
48 2020-07-15 Jan Beulich <jbeulich@suse.com>
50 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
51 description. Drop '&' description. Use P for push of immediate,
52 pushf/popf, enter, and leave. Use %LP for lret/retf.
53 (dis386_twobyte): Use P for push/pop of fs/gs.
54 (reg_table): Use P for push/pop. Use @ for near call/jmp.
55 (x86_64_table): Use P for far call/jmp.
56 (putop): Drop handling of 'U' and '&'. Move and adjust handling
57 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
59 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
60 and dqw_mode (unconditional).
62 2020-07-14 H.J. Lu <hongjiu.lu@intel.com>
65 * i386-dis.c (OP_E_memory): Without base nor index registers,
66 32-bit displacement to 64 bits.
68 2020-07-14 Claudiu Zissulescu <claziss@gmail.com>
70 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
71 faulty double register pair is detected.
73 2020-07-14 Jan Beulich <jbeulich@suse.com>
75 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
77 2020-07-14 Jan Beulich <jbeulich@suse.com>
79 * i386-dis.c (OP_R, Rm): Delete.
80 (MOD_0F24, MOD_0F26): Rename to ...
81 (X86_64_0F24, X86_64_0F26): ... respectively.
82 (dis386): Update 'L' and 'Z' comments.
83 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
85 (mod_table): Move opcode 0F24 and 0F26 entries ...
86 (x86_64_table): ... here.
87 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
90 2020-07-14 Jan Beulich <jbeulich@suse.com>
92 * i386-dis.c (Rd, Rdq, MaskR): Delete.
93 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
94 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
95 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
96 MOD_EVEX_0F387C): New enumerators.
97 (reg_table): Use Edq for rdssp.
98 (prefix_table): Use Edq for incssp.
99 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
100 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
101 ktest*, and kshift*. Use Edq / MaskE for kmov*.
102 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
103 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
104 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
105 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
106 0F3828_P_1 and 0F3838_P_1.
107 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
108 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
110 2020-07-14 Jan Beulich <jbeulich@suse.com>
112 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
113 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
114 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
115 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
116 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
117 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
118 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
119 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
120 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
121 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
122 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
123 (reg_table, prefix_table, three_byte_table, vex_table,
124 vex_len_table, mod_table, rm_table): Replace / remove respective
126 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
127 of PREFIX_DATA in used_prefixes.
129 2020-07-14 Jan Beulich <jbeulich@suse.com>
131 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
132 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
133 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
134 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
135 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
136 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
137 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
138 VEX_W_0F3A33_L_0): Delete.
139 (dis386): Adjust "BW" description.
140 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
141 0F3A31, 0F3A32, and 0F3A33.
142 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
144 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
147 2020-07-14 Jan Beulich <jbeulich@suse.com>
149 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
150 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
151 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
152 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
153 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
154 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
155 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
156 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
157 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
158 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
159 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
160 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
161 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
162 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
163 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
164 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
165 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
166 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
167 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
168 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
169 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
170 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
171 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
172 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
173 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
174 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
175 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
176 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
177 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
178 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
179 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
180 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
181 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
182 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
183 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
184 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
185 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
186 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
187 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
188 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
189 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
190 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
191 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
192 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
193 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
194 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
195 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
196 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
197 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
198 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
199 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
200 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
201 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
202 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
203 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
204 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
205 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
206 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
207 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
208 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
209 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
210 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
211 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
212 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
213 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
214 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
215 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
216 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
217 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
218 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
219 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
220 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
221 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
222 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
223 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
224 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
225 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
226 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
227 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
228 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
229 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
230 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
231 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
232 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
233 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
234 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
235 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
236 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
237 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
238 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
239 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
240 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
241 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
242 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
243 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
244 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
245 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
246 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
247 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
248 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
249 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
250 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
251 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
252 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
253 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
254 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
255 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
256 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
257 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
258 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
259 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
260 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
261 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
262 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
263 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
264 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
265 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
266 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
267 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
268 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
269 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
270 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
271 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
272 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
273 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
274 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
275 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
276 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
277 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
278 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
279 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
280 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
281 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
282 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
283 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
284 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
285 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
286 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
287 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
288 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
289 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
290 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
291 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
292 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
293 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
294 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
295 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
296 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
297 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
298 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
299 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
300 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
301 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
302 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
303 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
304 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
305 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
306 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
307 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
308 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
309 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
310 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
311 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
312 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
313 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
314 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
315 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
316 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
317 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
318 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
319 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
320 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
321 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
322 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
323 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
324 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
325 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
326 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
327 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
328 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
329 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
330 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
331 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
332 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
333 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
334 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
335 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
336 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
337 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
338 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
339 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
340 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
341 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
342 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
343 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
344 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
345 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
346 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
347 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
348 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
349 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
350 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
351 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
352 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
353 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
354 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
355 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
356 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
357 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
358 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
359 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
360 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
361 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
362 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
363 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
364 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
365 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
366 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
367 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
368 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
369 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
370 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
371 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
372 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
373 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
374 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
375 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
376 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
377 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
378 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
379 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
380 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
381 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
382 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
383 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
384 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
385 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
386 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
387 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
388 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
389 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
390 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
391 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
392 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
393 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
394 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
395 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
396 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
397 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
398 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
399 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
400 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
401 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
402 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
403 EVEX_W_0F3A72_P_2): Rename to ...
404 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
405 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
406 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
407 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
408 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
409 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
410 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
411 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
412 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
413 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
414 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
415 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
416 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
417 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
418 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
419 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
420 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
421 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
422 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
423 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
424 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
425 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
426 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
427 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
428 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
429 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
430 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
431 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
432 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
433 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
434 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
435 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
436 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
437 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
438 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
439 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
440 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
441 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
442 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
443 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
444 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
445 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
446 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
447 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
448 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
449 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
450 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
451 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
452 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
453 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
454 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
455 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
456 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
457 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
458 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
459 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
460 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
461 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
462 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
463 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
464 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
465 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
466 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
467 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
468 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
469 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
470 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
471 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
472 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
473 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
474 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
475 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
477 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
478 vex_w_table, mod_table): Replace / remove respective entries.
479 (print_insn): Move up dp->prefix_requirement handling. Handle
481 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
482 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
483 Replace / remove respective entries.
485 2020-07-14 Jan Beulich <jbeulich@suse.com>
487 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
488 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
489 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
490 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
491 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
493 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
494 0F2C, 0F2D, 0F2E, and 0F2F.
495 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
498 2020-07-14 Jan Beulich <jbeulich@suse.com>
500 * i386-dis.c (OP_VexR, VexScalarR): New.
501 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
502 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
503 need_vex_reg): Delete.
504 (prefix_table): Replace VexScalar by VexScalarR and
505 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
506 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
507 (vex_len_table): Replace EXqVexScalarS by EXqS.
508 (get_valid_dis386): Don't set need_vex_reg.
509 (print_insn): Don't initialize need_vex_reg.
510 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
511 q_scalar_swap_mode cases.
512 (OP_EX): Don't check for d_scalar_swap_mode and
514 (OP_VEX): Done check need_vex_reg.
515 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
516 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
517 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
519 2020-07-14 Jan Beulich <jbeulich@suse.com>
521 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
522 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
523 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
524 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
525 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
526 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
527 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
528 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
529 (vex_table): Replace Vex128 by Vex.
530 (vex_len_table): Likewise. Adjust referenced enum names.
531 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
532 referenced enum names.
533 (OP_VEX): Drop vex128_mode and vex256_mode cases.
534 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
536 2020-07-14 Jan Beulich <jbeulich@suse.com>
538 * i386-dis.c (dis386): "LW" description now applies to "DQ".
539 (putop): Handle "DQ". Don't handle "LW" anymore.
540 (prefix_table, mod_table): Replace %LW by %DQ.
541 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
543 2020-07-14 Jan Beulich <jbeulich@suse.com>
545 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
546 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
547 d_scalar_swap_mode case handling. Move shift adjsutment into
548 the case its applicable to.
550 2020-07-14 Jan Beulich <jbeulich@suse.com>
552 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
553 (EXbScalar, EXwScalar): Fold to ...
554 (EXbwUnit): ... this.
555 (b_scalar_mode, w_scalar_mode): Fold to ...
556 (bw_unit_mode): ... this.
557 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
558 w_scalar_mode handling by bw_unit_mode one.
559 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
561 * i386-dis-evex-prefix.h: ... here.
563 2020-07-14 Jan Beulich <jbeulich@suse.com>
565 * i386-dis.c (PCMPESTR_Fixup): Delete.
566 (dis386): Adjust "LQ" description.
567 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
568 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
569 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
570 vpcmpestrm, and vpcmpestri.
571 (putop): Honor "cond" when handling LQ.
572 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
573 vcvtsi2ss and vcvtusi2ss.
574 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
575 vcvtsi2sd and vcvtusi2sd.
577 2020-07-14 Jan Beulich <jbeulich@suse.com>
579 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
580 (simd_cmp_op): Add const.
581 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
582 (CMP_Fixup): Handle VEX case.
583 (prefix_table): Replace VCMP by CMP.
584 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
586 2020-07-14 Jan Beulich <jbeulich@suse.com>
588 * i386-dis.c (MOVBE_Fixup): Delete.
590 (prefix_table): Use Mv for movbe entries.
592 2020-07-14 Jan Beulich <jbeulich@suse.com>
594 * i386-dis.c (CRC32_Fixup): Delete.
595 (prefix_table): Use Eb/Ev for crc32 entries.
597 2020-07-14 Jan Beulich <jbeulich@suse.com>
599 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
600 Conditionalize invocations of "USED_REX (0)".
602 2020-07-14 Jan Beulich <jbeulich@suse.com>
604 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
605 CH, DH, BH, AX, DX): Delete.
606 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
607 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
608 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
610 2020-07-10 Lili Cui <lili.cui@intel.com>
612 * i386-dis.c (TMM): New.
615 (MVexSIBMEM): Likewise.
616 (tmm_mode): Likewise.
617 (vex_sibmem_mode): Likewise.
618 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
619 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
620 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
621 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
622 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
623 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
624 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
625 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
626 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
627 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
628 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
629 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
630 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
631 (PREFIX_VEX_0F3849_X86_64): Likewise.
632 (PREFIX_VEX_0F384B_X86_64): Likewise.
633 (PREFIX_VEX_0F385C_X86_64): Likewise.
634 (PREFIX_VEX_0F385E_X86_64): Likewise.
635 (X86_64_VEX_0F3849): Likewise.
636 (X86_64_VEX_0F384B): Likewise.
637 (X86_64_VEX_0F385C): Likewise.
638 (X86_64_VEX_0F385E): Likewise.
639 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
640 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
641 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
642 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
643 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
644 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
645 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
646 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
647 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
648 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
649 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
650 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
651 (VEX_W_0F3849_X86_64_P_0): Likewise.
652 (VEX_W_0F3849_X86_64_P_2): Likewise.
653 (VEX_W_0F3849_X86_64_P_3): Likewise.
654 (VEX_W_0F384B_X86_64_P_1): Likewise.
655 (VEX_W_0F384B_X86_64_P_2): Likewise.
656 (VEX_W_0F384B_X86_64_P_3): Likewise.
657 (VEX_W_0F385C_X86_64_P_1): Likewise.
658 (VEX_W_0F385E_X86_64_P_0): Likewise.
659 (VEX_W_0F385E_X86_64_P_1): Likewise.
660 (VEX_W_0F385E_X86_64_P_2): Likewise.
661 (VEX_W_0F385E_X86_64_P_3): Likewise.
662 (names_tmm): Likewise.
663 (att_names_tmm): Likewise.
664 (intel_operand_size): Handle void_mode.
665 (OP_XMM): Handle tmm_mode.
668 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
669 CpuAMX_BF16 and CpuAMX_TILE.
670 (operand_type_shorthands): Add RegTMM.
671 (operand_type_init): Likewise.
672 (operand_types): Add Tmmword.
673 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
674 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
675 * i386-opc.h (CpuAMX_INT8): New.
676 (CpuAMX_BF16): Likewise.
677 (CpuAMX_TILE): Likewise.
680 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
681 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
682 (i386_operand_type): Add tmmword.
683 * i386-opc.tbl: Add AMX instructions.
684 * i386-reg.tbl: Add AMX registers.
685 * i386-init.h: Regenerated.
686 * i386-tbl.h: Likewise.
688 2020-07-08 Jan Beulich <jbeulich@suse.com>
690 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
691 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
693 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
694 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
696 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
697 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
698 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
699 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
700 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
701 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
702 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
703 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
704 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
705 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
706 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
707 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
708 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
709 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
710 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
711 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
712 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
713 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
714 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
715 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
716 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
717 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
718 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
719 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
720 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
721 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
722 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
723 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
724 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
725 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
726 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
727 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
728 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
729 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
730 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
731 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
732 (reg_table): Re-order XOP entries. Adjust their operands.
733 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
734 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
735 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
736 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
737 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
738 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
739 entries by references ...
740 (vex_len_table): ... to resepctive new entries here. For several
741 new and existing entries reference ...
742 (vex_w_table): ... new entries here.
743 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
745 2020-07-08 Jan Beulich <jbeulich@suse.com>
747 * i386-dis.c (XMVexScalarI4): Define.
748 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
749 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
750 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
751 (vex_len_table): Move scalar FMA4 entries ...
752 (prefix_table): ... here.
753 (OP_REG_VexI4): Handle scalar_mode.
754 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
755 * i386-tbl.h: Re-generate.
757 2020-07-08 Jan Beulich <jbeulich@suse.com>
759 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
761 (OP_VexW, VexW): New.
762 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
763 for shifts and rotates by register.
765 2020-07-08 Jan Beulich <jbeulich@suse.com>
767 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
768 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
769 OP_EX_VexReg): Delete.
770 (OP_VexI4, VexI4): New.
771 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
772 (prefix_table): ... here.
773 (print_insn): Drop setting of vex_w_done.
775 2020-07-08 Jan Beulich <jbeulich@suse.com>
777 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
778 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
779 (xop_table): Replace operands of 4-operand insns.
780 (OP_REG_VexI4): Move VEX.W based operand swaping here.
782 2020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
784 * arc-opc.c (insert_rbd): New function.
787 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
790 2020-07-07 Jan Beulich <jbeulich@suse.com>
792 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
793 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
794 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
795 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
797 (putop): Handle "BW".
798 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
799 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
801 * i386-dis-evex-prefix.h: ... here.
803 2020-07-06 Jan Beulich <jbeulich@suse.com>
805 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
806 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
807 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
808 VEX_W_0FXOP_09_83): New enumerators.
809 (xop_table): Reference the above.
810 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
811 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
812 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
813 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
815 2020-07-06 Jan Beulich <jbeulich@suse.com>
817 * i386-dis.c (EVEX_W_0F3838_P_1,
818 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
819 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
820 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
821 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
822 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
823 (putop): Centralize management of last[]. Delete SAVE_LAST.
824 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
825 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
826 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
827 * i386-dis-evex-prefix.h: here.
829 2020-07-06 Jan Beulich <jbeulich@suse.com>
831 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
832 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
833 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
834 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
836 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
837 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
838 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
839 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
840 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
841 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
842 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
843 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
845 * i386-dis-evex-len.h: Adjust comments.
846 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
847 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
848 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
849 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
850 MOD_EVEX_0F385B_P_2_W_1 table entries.
851 * i386-dis-evex-w.h: Reference mod_table[] for
852 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
855 2020-07-06 Jan Beulich <jbeulich@suse.com>
857 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
858 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
860 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
861 Likewise. Mark 256-bit entries invalid.
863 2020-07-06 Jan Beulich <jbeulich@suse.com>
865 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
866 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
867 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
868 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
869 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
870 PREFIX_EVEX_0F382B): Delete.
871 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
872 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
873 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
874 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
875 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
877 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
878 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
879 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
880 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
882 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
883 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
884 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
885 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
886 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
887 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
888 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
889 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
890 PREFIX_EVEX_0F382B): Remove table entries.
891 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
892 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
893 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
895 2020-07-06 Jan Beulich <jbeulich@suse.com>
897 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
898 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
900 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
901 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
902 EVEX_LEN_0F3A01_P_2_W_1 table entries.
903 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
906 2020-07-06 Jan Beulich <jbeulich@suse.com>
908 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
909 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
910 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
911 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
912 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
913 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
914 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
915 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
916 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
919 2020-07-06 Jan Beulich <jbeulich@suse.com>
921 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
922 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
923 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
925 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
927 * i386-dis-evex.h (evex_table): Reference VEX table entry for
929 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
931 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
933 2020-07-06 Jan Beulich <jbeulich@suse.com>
935 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
936 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
937 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
938 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
939 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
940 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
941 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
942 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
943 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
944 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
945 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
946 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
947 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
948 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
949 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
950 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
951 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
952 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
953 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
954 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
955 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
956 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
957 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
958 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
959 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
960 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
961 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
962 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
963 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
964 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
965 (prefix_table): Add EXxEVexR to FMA table entries.
966 (OP_Rounding): Move abort() invocation.
967 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
968 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
969 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
970 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
971 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
972 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
973 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
974 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
975 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
976 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
978 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
979 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
980 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
981 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
982 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
983 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
984 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
985 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
986 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
987 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
988 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
989 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
990 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
991 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
992 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
993 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
994 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
995 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
996 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
997 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
998 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
999 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1000 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1001 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1002 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1003 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1004 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1005 Delete table entries.
1006 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1007 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1008 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1011 2020-07-06 Jan Beulich <jbeulich@suse.com>
1013 * i386-dis.c (EXqScalarS): Delete.
1014 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1015 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1017 2020-07-06 Jan Beulich <jbeulich@suse.com>
1019 * i386-dis.c (safe-ctype.h): Include.
1020 (EXdScalar, EXqScalar): Delete.
1021 (d_scalar_mode, q_scalar_mode): Delete.
1022 (prefix_table, vex_len_table): Use EXxmm_md in place of
1023 EXdScalar and EXxmm_mq in place of EXqScalar.
1024 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1025 d_scalar_mode and q_scalar_mode.
1026 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1027 (vmovsd): Use EXxmm_mq.
1029 2020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1032 * arc-dis.c: Fix spelling mistake.
1033 * po/opcodes.pot: Regenerate.
1035 2020-07-06 Nick Clifton <nickc@redhat.com>
1037 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1038 * po/uk.po: Updated Ukranian translation.
1040 2020-07-04 Nick Clifton <nickc@redhat.com>
1042 * configure: Regenerate.
1043 * po/opcodes.pot: Regenerate.
1045 2020-07-04 Nick Clifton <nickc@redhat.com>
1047 Binutils 2.35 branch created.
1049 2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1051 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1052 * i386-opc.h (VexSwapSources): New.
1053 (i386_opcode_modifier): Add vexswapsources.
1054 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1055 with two source operands swapped.
1056 * i386-tbl.h: Regenerated.
1058 2020-06-30 Nelson Chu <nelson.chu@sifive.com>
1060 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1061 unprivileged CSR can also be initialized.
1063 2020-06-29 Alan Modra <amodra@gmail.com>
1065 * arm-dis.c: Use C style comments.
1066 * cr16-opc.c: Likewise.
1067 * ft32-dis.c: Likewise.
1068 * moxie-opc.c: Likewise.
1069 * tic54x-dis.c: Likewise.
1070 * s12z-opc.c: Remove useless comment.
1071 * xgate-dis.c: Likewise.
1073 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1075 * i386-opc.tbl: Add a blank line.
1077 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1079 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1080 (VecSIB128): Renamed to ...
1082 (VecSIB256): Renamed to ...
1084 (VecSIB512): Renamed to ...
1086 (VecSIB): Renamed to ...
1088 (i386_opcode_modifier): Replace vecsib with sib.
1089 * i386-opc.tbl (VecSIB128): New.
1090 (VecSIB256): Likewise.
1091 (VecSIB512): Likewise.
1092 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1093 and VecSIB512, respectively.
1095 2020-06-26 Jan Beulich <jbeulich@suse.com>
1097 * i386-dis.c: Adjust description of I macro.
1098 (x86_64_table): Drop use of I.
1099 (float_mem): Replace use of I.
1100 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1102 2020-06-26 Jan Beulich <jbeulich@suse.com>
1104 * i386-dis.c: (print_insn): Avoid straight assignment to
1105 priv.orig_sizeflag when processing -M sub-options.
1107 2020-06-25 Jan Beulich <jbeulich@suse.com>
1109 * i386-dis.c: Adjust description of J macro.
1110 (dis386, x86_64_table, mod_table): Replace J.
1111 (putop): Remove handling of J.
1113 2020-06-25 Jan Beulich <jbeulich@suse.com>
1115 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1117 2020-06-25 Jan Beulich <jbeulich@suse.com>
1119 * i386-dis.c: Adjust description of "LQ" macro.
1120 (dis386_twobyte): Use LQ for sysret.
1121 (putop): Adjust handling of LQ.
1123 2020-06-22 Nelson Chu <nelson.chu@sifive.com>
1125 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1126 * riscv-dis.c: Include elfxx-riscv.h.
1128 2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1130 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1132 2020-06-17 Lili Cui <lili.cui@intel.com>
1134 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1136 2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1139 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1140 * i386-opc.tbl: Likewise.
1141 * i386-tbl.h: Regenerated.
1143 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
1145 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1147 2020-06-11 Alex Coplan <alex.coplan@arm.com>
1149 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1150 (SR_CORE): Likewise.
1151 (SR_FEAT): Likewise.
1153 (SR_V8_1): Likewise.
1154 (SR_V8_2): Likewise.
1155 (SR_V8_3): Likewise.
1156 (SR_V8_4): Likewise.
1159 (SR_SSBS): Likewise.
1161 (SR_ID_PFR2): Likewise.
1162 (SR_PROFILE): Likewise.
1163 (SR_MEMTAG): Likewise.
1164 (SR_SCXTNUM): Likewise.
1165 (aarch64_sys_regs): Refactor to store feature information in the table.
1166 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1167 that now describe their own features.
1168 (aarch64_pstatefield_supported_p): Likewise.
1170 2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1172 * i386-dis.c (prefix_table): Fix a typo in comments.
1174 2020-06-09 Jan Beulich <jbeulich@suse.com>
1176 * i386-dis.c (rex_ignored): Delete.
1177 (ckprefix): Drop rex_ignored initialization.
1178 (get_valid_dis386): Drop setting of rex_ignored.
1179 (print_insn): Drop checking of rex_ignored. Don't record data
1180 size prefix as used with VEX-and-alike encodings.
1182 2020-06-09 Jan Beulich <jbeulich@suse.com>
1184 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1185 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1186 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1187 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1188 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1189 VEX_0F12, and VEX_0F16.
1190 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1191 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1192 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1193 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1194 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1195 MOD_VEX_0F16_PREFIX_2 entries.
1197 2020-06-09 Jan Beulich <jbeulich@suse.com>
1199 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1200 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1201 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1202 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1203 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1204 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1205 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1206 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1207 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1208 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1209 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1210 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1211 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1212 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1213 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1214 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1215 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1216 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1217 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1218 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1219 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1220 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1221 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1222 EVEX_W_0FC6_P_2): Delete.
1223 (print_insn): Add EVEX.W vs embedded prefix consistency check
1224 to prefix validation.
1225 * i386-dis-evex.h (evex_table): Don't further descend for
1226 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1227 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1229 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1230 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1231 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1232 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1233 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1234 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1235 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1236 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1237 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1238 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1239 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1240 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1241 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1242 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1243 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1244 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1245 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1246 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1247 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1248 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1249 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1250 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1251 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1252 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1253 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1254 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1255 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1257 2020-06-09 Jan Beulich <jbeulich@suse.com>
1259 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1260 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1261 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1263 (print_insn): Drop pointless check against bad_opcode. Split
1264 prefix validation into legacy and VEX-and-alike parts.
1265 (putop): Re-work 'X' macro handling.
1267 2020-06-09 Jan Beulich <jbeulich@suse.com>
1269 * i386-dis.c (MOD_0F51): Rename to ...
1270 (MOD_0F50): ... this.
1272 2020-06-08 Alex Coplan <alex.coplan@arm.com>
1274 * arm-dis.c (arm_opcodes): Add dfb.
1275 (thumb32_opcodes): Add dfb.
1277 2020-06-08 Jan Beulich <jbeulich@suse.com>
1279 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1281 2020-06-06 Alan Modra <amodra@gmail.com>
1283 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1285 2020-06-05 Alan Modra <amodra@gmail.com>
1287 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1288 size is large enough.
1290 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1292 * disassemble.c (disassemble_init_for_target): Set endian_code for
1294 * bpf-desc.c: Regenerate.
1295 * bpf-opc.c: Likewise.
1296 * bpf-dis.c: Likewise.
1298 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1300 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1301 (cgen_put_insn_value): Likewise.
1302 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1303 * cgen-dis.in (print_insn): Likewise.
1304 * cgen-ibld.in (insert_1): Likewise.
1305 (insert_1): Likewise.
1306 (insert_insn_normal): Likewise.
1307 (extract_1): Likewise.
1308 * bpf-dis.c: Regenerate.
1309 * bpf-ibld.c: Likewise.
1310 * bpf-ibld.c: Likewise.
1311 * cgen-dis.in: Likewise.
1312 * cgen-ibld.in: Likewise.
1313 * cgen-opc.c: Likewise.
1314 * epiphany-dis.c: Likewise.
1315 * epiphany-ibld.c: Likewise.
1316 * fr30-dis.c: Likewise.
1317 * fr30-ibld.c: Likewise.
1318 * frv-dis.c: Likewise.
1319 * frv-ibld.c: Likewise.
1320 * ip2k-dis.c: Likewise.
1321 * ip2k-ibld.c: Likewise.
1322 * iq2000-dis.c: Likewise.
1323 * iq2000-ibld.c: Likewise.
1324 * lm32-dis.c: Likewise.
1325 * lm32-ibld.c: Likewise.
1326 * m32c-dis.c: Likewise.
1327 * m32c-ibld.c: Likewise.
1328 * m32r-dis.c: Likewise.
1329 * m32r-ibld.c: Likewise.
1330 * mep-dis.c: Likewise.
1331 * mep-ibld.c: Likewise.
1332 * mt-dis.c: Likewise.
1333 * mt-ibld.c: Likewise.
1334 * or1k-dis.c: Likewise.
1335 * or1k-ibld.c: Likewise.
1336 * xc16x-dis.c: Likewise.
1337 * xc16x-ibld.c: Likewise.
1338 * xstormy16-dis.c: Likewise.
1339 * xstormy16-ibld.c: Likewise.
1341 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1343 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1344 (print_insn_): Handle instruction endian.
1345 * bpf-dis.c: Regenerate.
1346 * bpf-desc.c: Regenerate.
1347 * epiphany-dis.c: Likewise.
1348 * epiphany-desc.c: Likewise.
1349 * fr30-dis.c: Likewise.
1350 * fr30-desc.c: Likewise.
1351 * frv-dis.c: Likewise.
1352 * frv-desc.c: Likewise.
1353 * ip2k-dis.c: Likewise.
1354 * ip2k-desc.c: Likewise.
1355 * iq2000-dis.c: Likewise.
1356 * iq2000-desc.c: Likewise.
1357 * lm32-dis.c: Likewise.
1358 * lm32-desc.c: Likewise.
1359 * m32c-dis.c: Likewise.
1360 * m32c-desc.c: Likewise.
1361 * m32r-dis.c: Likewise.
1362 * m32r-desc.c: Likewise.
1363 * mep-dis.c: Likewise.
1364 * mep-desc.c: Likewise.
1365 * mt-dis.c: Likewise.
1366 * mt-desc.c: Likewise.
1367 * or1k-dis.c: Likewise.
1368 * or1k-desc.c: Likewise.
1369 * xc16x-dis.c: Likewise.
1370 * xc16x-desc.c: Likewise.
1371 * xstormy16-dis.c: Likewise.
1372 * xstormy16-desc.c: Likewise.
1374 2020-06-03 Nick Clifton <nickc@redhat.com>
1376 * po/sr.po: Updated Serbian translation.
1378 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
1380 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1381 (riscv_get_priv_spec_class): Likewise.
1383 2020-06-01 Alan Modra <amodra@gmail.com>
1385 * bpf-desc.c: Regenerate.
1387 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1388 David Faust <david.faust@oracle.com>
1390 * bpf-desc.c: Regenerate.
1391 * bpf-opc.h: Likewise.
1392 * bpf-opc.c: Likewise.
1393 * bpf-dis.c: Likewise.
1395 2020-05-28 Alan Modra <amodra@gmail.com>
1397 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1400 2020-05-28 Alan Modra <amodra@gmail.com>
1402 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1404 (print_insn_ns32k): Revert last change.
1406 2020-05-28 Nick Clifton <nickc@redhat.com>
1408 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1411 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1413 Fix extraction of signed constants in nios2 disassembler (again).
1415 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1416 extractions of signed fields.
1418 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1420 * s390-opc.txt: Relocate vector load/store instructions with
1421 additional alignment parameter and change architecture level
1422 constraint from z14 to z13.
1424 2020-05-21 Alan Modra <amodra@gmail.com>
1426 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1427 * sparc-dis.c: Likewise.
1428 * tic4x-dis.c: Likewise.
1429 * xtensa-dis.c: Likewise.
1430 * bpf-desc.c: Regenerate.
1431 * epiphany-desc.c: Regenerate.
1432 * fr30-desc.c: Regenerate.
1433 * frv-desc.c: Regenerate.
1434 * ip2k-desc.c: Regenerate.
1435 * iq2000-desc.c: Regenerate.
1436 * lm32-desc.c: Regenerate.
1437 * m32c-desc.c: Regenerate.
1438 * m32r-desc.c: Regenerate.
1439 * mep-asm.c: Regenerate.
1440 * mep-desc.c: Regenerate.
1441 * mt-desc.c: Regenerate.
1442 * or1k-desc.c: Regenerate.
1443 * xc16x-desc.c: Regenerate.
1444 * xstormy16-desc.c: Regenerate.
1446 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
1448 * riscv-opc.c (riscv_ext_version_table): The table used to store
1449 all information about the supported spec and the corresponding ISA
1450 versions. Currently, only Zicsr is supported to verify the
1451 correctness of Z sub extension settings. Others will be supported
1452 in the future patches.
1453 (struct isa_spec_t, isa_specs): List for all supported ISA spec
1454 classes and the corresponding strings.
1455 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
1456 spec class by giving a ISA spec string.
1457 * riscv-opc.c (struct priv_spec_t): New structure.
1458 (struct priv_spec_t priv_specs): List for all supported privilege spec
1459 classes and the corresponding strings.
1460 (riscv_get_priv_spec_class): New function. Get the corresponding
1461 privilege spec class by giving a spec string.
1462 (riscv_get_priv_spec_name): New function. Get the corresponding
1463 privilege spec string by giving a CSR version class.
1464 * riscv-dis.c: Updated since DECLARE_CSR is changed.
1465 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
1466 according to the chosen version. Build a hash table riscv_csr_hash to
1467 store the valid CSR for the chosen pirv verison. Dump the direct
1468 CSR address rather than it's name if it is invalid.
1469 (parse_riscv_dis_option_without_args): New function. Parse the options
1471 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
1472 parse the options without arguments first, and then handle the options
1473 with arguments. Add the new option -Mpriv-spec, which has argument.
1474 * riscv-dis.c (print_riscv_disassembler_options): Add description
1475 about the new OBJDUMP option.
1477 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
1479 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
1480 WC values on POWER10 sync, dcbf and wait instructions.
1481 (insert_pl, extract_pl): New functions.
1482 (L2OPT, LS, WC): Use insert_ls and extract_ls.
1483 (LS3): New , 3-bit L for sync.
1484 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
1485 (SC2, PL): New, 2-bit SC and PL for sync and wait.
1486 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
1487 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
1488 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
1489 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
1490 <wait>: Enable PL operand on POWER10.
1491 <dcbf>: Enable L3OPT operand on POWER10.
1492 <sync>: Enable SC2 operand on POWER10.
1494 2020-05-19 Stafford Horne <shorne@gmail.com>
1497 * or1k-asm.c: Regenerate.
1498 * or1k-desc.c: Regenerate.
1499 * or1k-desc.h: Regenerate.
1500 * or1k-dis.c: Regenerate.
1501 * or1k-ibld.c: Regenerate.
1502 * or1k-opc.c: Regenerate.
1503 * or1k-opc.h: Regenerate.
1504 * or1k-opinst.c: Regenerate.
1506 2020-05-11 Alan Modra <amodra@gmail.com>
1508 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
1511 2020-05-11 Alan Modra <amodra@gmail.com>
1513 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
1514 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
1516 2020-05-11 Alan Modra <amodra@gmail.com>
1518 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
1520 2020-05-11 Alan Modra <amodra@gmail.com>
1522 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
1523 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
1525 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1527 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
1530 2020-05-11 Alan Modra <amodra@gmail.com>
1532 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
1533 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
1534 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
1535 (prefix_opcodes): Add xxeval.
1537 2020-05-11 Alan Modra <amodra@gmail.com>
1539 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
1540 xxgenpcvwm, xxgenpcvdm.
1542 2020-05-11 Alan Modra <amodra@gmail.com>
1544 * ppc-opc.c (MP, VXVAM_MASK): Define.
1545 (VXVAPS_MASK): Use VXVA_MASK.
1546 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
1547 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
1548 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
1549 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
1551 2020-05-11 Alan Modra <amodra@gmail.com>
1552 Peter Bergner <bergner@linux.ibm.com>
1554 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
1556 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
1557 YMSK2, XA6a, XA6ap, XB6a entries.
1558 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
1559 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
1561 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
1562 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
1563 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
1564 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
1565 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
1566 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
1567 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
1568 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
1569 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
1570 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
1571 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
1572 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
1573 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
1574 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
1576 2020-05-11 Alan Modra <amodra@gmail.com>
1578 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
1579 (insert_xts, extract_xts): New functions.
1580 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
1581 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
1582 (VXRC_MASK, VXSH_MASK): Define.
1583 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
1584 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
1585 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
1586 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
1587 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
1588 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
1589 xxblendvh, xxblendvw, xxblendvd, xxpermx.
1591 2020-05-11 Alan Modra <amodra@gmail.com>
1593 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
1594 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
1595 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
1596 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
1597 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
1599 2020-05-11 Alan Modra <amodra@gmail.com>
1601 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
1602 (XTP, DQXP, DQXP_MASK): Define.
1603 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
1604 (prefix_opcodes): Add plxvp and pstxvp.
1606 2020-05-11 Alan Modra <amodra@gmail.com>
1608 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1609 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1610 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1612 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1614 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1616 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1618 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1620 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1622 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1624 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1626 2020-05-11 Alan Modra <amodra@gmail.com>
1628 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1630 2020-05-11 Alan Modra <amodra@gmail.com>
1632 * ppc-dis.c (ppc_opts): Add "power10" entry.
1633 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1634 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
1636 2020-05-11 Nick Clifton <nickc@redhat.com>
1638 * po/fr.po: Updated French translation.
1640 2020-04-30 Alex Coplan <alex.coplan@arm.com>
1642 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1643 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1644 (operand_general_constraint_met_p): validate
1645 AARCH64_OPND_UNDEFINED.
1646 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1648 * aarch64-asm-2.c: Regenerated.
1649 * aarch64-dis-2.c: Regenerated.
1650 * aarch64-opc-2.c: Regenerated.
1652 2020-04-29 Nick Clifton <nickc@redhat.com>
1655 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1658 2020-04-29 Nick Clifton <nickc@redhat.com>
1660 * po/sv.po: Updated Swedish translation.
1662 2020-04-29 Nick Clifton <nickc@redhat.com>
1665 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
1666 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
1667 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
1670 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
1673 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
1674 cmpi only on m68020up and cpu32.
1676 2020-04-20 Sudakshina Das <sudi.das@arm.com>
1678 * aarch64-asm.c (aarch64_ins_none): New.
1679 * aarch64-asm.h (ins_none): New declaration.
1680 * aarch64-dis.c (aarch64_ext_none): New.
1681 * aarch64-dis.h (ext_none): New declaration.
1682 * aarch64-opc.c (aarch64_print_operand): Update case for
1683 AARCH64_OPND_BARRIER_PSB.
1684 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
1685 (AARCH64_OPERANDS): Update inserter/extracter for
1686 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
1687 * aarch64-asm-2.c: Regenerated.
1688 * aarch64-dis-2.c: Regenerated.
1689 * aarch64-opc-2.c: Regenerated.
1691 2020-04-20 Sudakshina Das <sudi.das@arm.com>
1693 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
1694 (aarch64_feature_ras, RAS): Likewise.
1695 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
1696 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
1697 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
1698 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
1699 * aarch64-asm-2.c: Regenerated.
1700 * aarch64-dis-2.c: Regenerated.
1701 * aarch64-opc-2.c: Regenerated.
1703 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
1705 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
1706 (print_insn_neon): Support disassembly of conditional
1709 2020-02-16 David Faust <david.faust@oracle.com>
1711 * bpf-desc.c: Regenerate.
1712 * bpf-desc.h: Likewise.
1713 * bpf-opc.c: Regenerate.
1714 * bpf-opc.h: Likewise.
1716 2020-04-07 Lili Cui <lili.cui@intel.com>
1718 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
1719 (prefix_table): New instructions (see prefixes above).
1720 (rm_table): Likewise
1721 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
1722 CPU_ANY_TSXLDTRK_FLAGS.
1723 (cpu_flags): Add CpuTSXLDTRK.
1724 * i386-opc.h (enum): Add CpuTSXLDTRK.
1725 (i386_cpu_flags): Add cputsxldtrk.
1726 * i386-opc.tbl: Add XSUSPLDTRK insns.
1727 * i386-init.h: Regenerate.
1728 * i386-tbl.h: Likewise.
1730 2020-04-02 Lili Cui <lili.cui@intel.com>
1732 * i386-dis.c (prefix_table): New instructions serialize.
1733 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
1734 CPU_ANY_SERIALIZE_FLAGS.
1735 (cpu_flags): Add CpuSERIALIZE.
1736 * i386-opc.h (enum): Add CpuSERIALIZE.
1737 (i386_cpu_flags): Add cpuserialize.
1738 * i386-opc.tbl: Add SERIALIZE insns.
1739 * i386-init.h: Regenerate.
1740 * i386-tbl.h: Likewise.
1742 2020-03-26 Alan Modra <amodra@gmail.com>
1744 * disassemble.h (opcodes_assert): Declare.
1745 (OPCODES_ASSERT): Define.
1746 * disassemble.c: Don't include assert.h. Include opintl.h.
1747 (opcodes_assert): New function.
1748 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
1749 (bfd_h8_disassemble): Reduce size of data array. Correctly
1750 calculate maxlen. Omit insn decoding when insn length exceeds
1751 maxlen. Exit from nibble loop when looking for E, before
1752 accessing next data byte. Move processing of E outside loop.
1753 Replace tests of maxlen in loop with assertions.
1755 2020-03-26 Alan Modra <amodra@gmail.com>
1757 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
1759 2020-03-25 Alan Modra <amodra@gmail.com>
1761 * z80-dis.c (suffix): Init mybuf.
1763 2020-03-22 Alan Modra <amodra@gmail.com>
1765 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
1766 successflly read from section.
1768 2020-03-22 Alan Modra <amodra@gmail.com>
1770 * arc-dis.c (find_format): Use ISO C string concatenation rather
1771 than line continuation within a string. Don't access needs_limm
1772 before testing opcode != NULL.
1774 2020-03-22 Alan Modra <amodra@gmail.com>
1776 * ns32k-dis.c (print_insn_arg): Update comment.
1777 (print_insn_ns32k): Reduce size of index_offset array, and
1778 initialize, passing -1 to print_insn_arg for args that are not
1779 an index. Don't exit arg loop early. Abort on bad arg number.
1781 2020-03-22 Alan Modra <amodra@gmail.com>
1783 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
1784 * s12z-opc.c: Formatting.
1785 (operands_f): Return an int.
1786 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
1787 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
1788 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
1789 (exg_sex_discrim): Likewise.
1790 (create_immediate_operand, create_bitfield_operand),
1791 (create_register_operand_with_size, create_register_all_operand),
1792 (create_register_all16_operand, create_simple_memory_operand),
1793 (create_memory_operand, create_memory_auto_operand): Don't
1794 segfault on malloc failure.
1795 (z_ext24_decode): Return an int status, negative on fail, zero
1797 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
1798 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
1799 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
1800 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
1801 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1802 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1803 (loop_primitive_decode, shift_decode, psh_pul_decode),
1804 (bit_field_decode): Similarly.
1805 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
1806 to return value, update callers.
1807 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1808 Don't segfault on NULL operand.
1809 (decode_operation): Return OP_INVALID on first fail.
1810 (decode_s12z): Check all reads, returning -1 on fail.
1812 2020-03-20 Alan Modra <amodra@gmail.com>
1814 * metag-dis.c (print_insn_metag): Don't ignore status from
1817 2020-03-20 Alan Modra <amodra@gmail.com>
1819 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1820 Initialize parts of buffer not written when handling a possible
1821 2-byte insn at end of section. Don't attempt decoding of such
1822 an insn by the 4-byte machinery.
1824 2020-03-20 Alan Modra <amodra@gmail.com>
1826 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1827 partially filled buffer. Prevent lookup of 4-byte insns when
1828 only VLE 2-byte insns are possible due to section size. Print
1829 ".word" rather than ".long" for 2-byte leftovers.
1831 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
1834 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1836 2020-03-13 Jan Beulich <jbeulich@suse.com>
1838 * i386-dis.c (X86_64_0D): Rename to ...
1839 (X86_64_0E): ... this.
1841 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
1843 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1844 * Makefile.in: Regenerated.
1846 2020-03-09 Jan Beulich <jbeulich@suse.com>
1848 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
1850 * i386-tbl.h: Re-generate.
1852 2020-03-09 Jan Beulich <jbeulich@suse.com>
1854 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1855 vprot*, vpsha*, and vpshl*.
1856 * i386-tbl.h: Re-generate.
1858 2020-03-09 Jan Beulich <jbeulich@suse.com>
1860 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1861 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1862 * i386-tbl.h: Re-generate.
1864 2020-03-09 Jan Beulich <jbeulich@suse.com>
1866 * i386-gen.c (set_bitfield): Ignore zero-length field names.
1867 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1868 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1869 * i386-tbl.h: Re-generate.
1871 2020-03-09 Jan Beulich <jbeulich@suse.com>
1873 * i386-gen.c (struct template_arg, struct template_instance,
1874 struct template_param, struct template, templates,
1875 parse_template, expand_templates): New.
1876 (process_i386_opcodes): Various local variables moved to
1877 expand_templates. Call parse_template and expand_templates.
1878 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1879 * i386-tbl.h: Re-generate.
1881 2020-03-06 Jan Beulich <jbeulich@suse.com>
1883 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1884 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1885 register and memory source templates. Replace VexW= by VexW*
1887 * i386-tbl.h: Re-generate.
1889 2020-03-06 Jan Beulich <jbeulich@suse.com>
1891 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1892 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1893 * i386-tbl.h: Re-generate.
1895 2020-03-06 Jan Beulich <jbeulich@suse.com>
1897 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1898 * i386-tbl.h: Re-generate.
1900 2020-03-06 Jan Beulich <jbeulich@suse.com>
1902 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1903 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1904 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1905 VexW0 on SSE2AVX variants.
1906 (vmovq): Drop NoRex64 from XMM/XMM variants.
1907 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1908 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1909 applicable use VexW0.
1910 * i386-tbl.h: Re-generate.
1912 2020-03-06 Jan Beulich <jbeulich@suse.com>
1914 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1915 * i386-opc.h (Rex64): Delete.
1916 (struct i386_opcode_modifier): Remove rex64 field.
1917 * i386-opc.tbl (crc32): Drop Rex64.
1918 Replace Rex64 with Size64 everywhere else.
1919 * i386-tbl.h: Re-generate.
1921 2020-03-06 Jan Beulich <jbeulich@suse.com>
1923 * i386-dis.c (OP_E_memory): Exclude recording of used address
1924 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1925 addressed memory operands for MPX insns.
1927 2020-03-06 Jan Beulich <jbeulich@suse.com>
1929 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1930 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1931 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1932 (ptwrite): Split into non-64-bit and 64-bit forms.
1933 * i386-tbl.h: Re-generate.
1935 2020-03-06 Jan Beulich <jbeulich@suse.com>
1937 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1939 * i386-tbl.h: Re-generate.
1941 2020-03-04 Jan Beulich <jbeulich@suse.com>
1943 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1944 (prefix_table): Move vmmcall here. Add vmgexit.
1945 (rm_table): Replace vmmcall entry by prefix_table[] escape.
1946 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1947 (cpu_flags): Add CpuSEV_ES entry.
1948 * i386-opc.h (CpuSEV_ES): New.
1949 (union i386_cpu_flags): Add cpusev_es field.
1950 * i386-opc.tbl (vmgexit): New.
1951 * i386-init.h, i386-tbl.h: Re-generate.
1953 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1955 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1957 * i386-opc.h (IGNORESIZE): New.
1958 (DEFAULTSIZE): Likewise.
1959 (IgnoreSize): Removed.
1960 (DefaultSize): Likewise.
1961 (MnemonicSize): New.
1962 (i386_opcode_modifier): Replace ignoresize/defaultsize with
1964 * i386-opc.tbl (IgnoreSize): New.
1965 (DefaultSize): Likewise.
1966 * i386-tbl.h: Regenerated.
1968 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1971 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
1974 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1977 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
1978 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
1979 * i386-tbl.h: Regenerated.
1981 2020-02-26 Alan Modra <amodra@gmail.com>
1983 * aarch64-asm.c: Indent labels correctly.
1984 * aarch64-dis.c: Likewise.
1985 * aarch64-gen.c: Likewise.
1986 * aarch64-opc.c: Likewise.
1987 * alpha-dis.c: Likewise.
1988 * i386-dis.c: Likewise.
1989 * nds32-asm.c: Likewise.
1990 * nfp-dis.c: Likewise.
1991 * visium-dis.c: Likewise.
1993 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
1995 * arc-regs.h (int_vector_base): Make it available for all ARC
1998 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
2000 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2003 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
2005 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2006 c.mv/c.li if rs1 is zero.
2008 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
2010 * i386-gen.c (cpu_flag_init): Replace CpuABM with
2011 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
2013 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
2014 * i386-opc.h (CpuABM): Removed.
2016 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
2017 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2018 popcnt. Remove CpuABM from lzcnt.
2019 * i386-init.h: Regenerated.
2020 * i386-tbl.h: Likewise.
2022 2020-02-17 Jan Beulich <jbeulich@suse.com>
2024 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2025 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2026 VexW1 instead of open-coding them.
2027 * i386-tbl.h: Re-generate.
2029 2020-02-17 Jan Beulich <jbeulich@suse.com>
2031 * i386-opc.tbl (AddrPrefixOpReg): Define.
2032 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2033 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2034 templates. Drop NoRex64.
2035 * i386-tbl.h: Re-generate.
2037 2020-02-17 Jan Beulich <jbeulich@suse.com>
2040 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2041 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2042 into Intel syntax instance (with Unpsecified) and AT&T one
2044 (vcvtneps2bf16): Likewise, along with folding the two so far
2046 * i386-tbl.h: Re-generate.
2048 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2050 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2051 CPU_ANY_SSE4A_FLAGS.
2053 2020-02-17 Alan Modra <amodra@gmail.com>
2055 * i386-gen.c (cpu_flag_init): Correct last change.
2057 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2059 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2062 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2064 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2067 2020-02-14 Jan Beulich <jbeulich@suse.com>
2070 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2071 destination for Cpu64-only variant.
2072 (movzx): Fold patterns.
2073 * i386-tbl.h: Re-generate.
2075 2020-02-13 Jan Beulich <jbeulich@suse.com>
2077 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2078 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2079 CPU_ANY_SSE4_FLAGS entry.
2080 * i386-init.h: Re-generate.
2082 2020-02-12 Jan Beulich <jbeulich@suse.com>
2084 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2085 with Unspecified, making the present one AT&T syntax only.
2086 * i386-tbl.h: Re-generate.
2088 2020-02-12 Jan Beulich <jbeulich@suse.com>
2090 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2091 * i386-tbl.h: Re-generate.
2093 2020-02-12 Jan Beulich <jbeulich@suse.com>
2096 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2097 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2098 Amd64 and Intel64 templates.
2099 (call, jmp): Likewise for far indirect variants. Dro
2101 * i386-tbl.h: Re-generate.
2103 2020-02-11 Jan Beulich <jbeulich@suse.com>
2105 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2106 * i386-opc.h (ShortForm): Delete.
2107 (struct i386_opcode_modifier): Remove shortform field.
2108 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2109 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2110 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2111 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2113 * i386-tbl.h: Re-generate.
2115 2020-02-11 Jan Beulich <jbeulich@suse.com>
2117 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2118 fucompi): Drop ShortForm from operand-less templates.
2119 * i386-tbl.h: Re-generate.
2121 2020-02-11 Alan Modra <amodra@gmail.com>
2123 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2124 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2125 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2126 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2127 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2129 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2131 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2132 (cde_opcodes): Add VCX* instructions.
2134 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2135 Matthew Malcomson <matthew.malcomson@arm.com>
2137 * arm-dis.c (struct cdeopcode32): New.
2138 (CDE_OPCODE): New macro.
2139 (cde_opcodes): New disassembly table.
2140 (regnames): New option to table.
2141 (cde_coprocs): New global variable.
2142 (print_insn_cde): New
2143 (print_insn_thumb32): Use print_insn_cde.
2144 (parse_arm_disassembler_options): Parse coprocN args.
2146 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2149 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2151 * i386-opc.h (AMD64): Removed.
2152 (Intel64): Likewose.
2154 (INTEL64): Likewise.
2155 (INTEL64ONLY): Likewise.
2156 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2157 * i386-opc.tbl (Amd64): New.
2158 (Intel64): Likewise.
2159 (Intel64Only): Likewise.
2160 Replace AMD64 with Amd64. Update sysenter/sysenter with
2161 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2162 * i386-tbl.h: Regenerated.
2164 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2167 * z80-dis.c: Add support for GBZ80 opcodes.
2169 2020-02-04 Alan Modra <amodra@gmail.com>
2171 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2173 2020-02-03 Alan Modra <amodra@gmail.com>
2175 * m32c-ibld.c: Regenerate.
2177 2020-02-01 Alan Modra <amodra@gmail.com>
2179 * frv-ibld.c: Regenerate.
2181 2020-01-31 Jan Beulich <jbeulich@suse.com>
2183 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2184 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2185 (OP_E_memory): Replace xmm_mdq_mode case label by
2186 vex_scalar_w_dq_mode one.
2187 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2189 2020-01-31 Jan Beulich <jbeulich@suse.com>
2191 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2192 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2193 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2194 (intel_operand_size): Drop vex_w_dq_mode case label.
2196 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2198 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2199 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2201 2020-01-30 Alan Modra <amodra@gmail.com>
2203 * m32c-ibld.c: Regenerate.
2205 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2207 * bpf-opc.c: Regenerate.
2209 2020-01-30 Jan Beulich <jbeulich@suse.com>
2211 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2212 (dis386): Use them to replace C2/C3 table entries.
2213 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2214 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2215 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2216 * i386-tbl.h: Re-generate.
2218 2020-01-30 Jan Beulich <jbeulich@suse.com>
2220 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2222 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2224 * i386-tbl.h: Re-generate.
2226 2020-01-30 Alan Modra <amodra@gmail.com>
2228 * tic4x-dis.c (tic4x_dp): Make unsigned.
2230 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2231 Jan Beulich <jbeulich@suse.com>
2234 * i386-dis.c (MOVSXD_Fixup): New function.
2235 (movsxd_mode): New enum.
2236 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2237 (intel_operand_size): Handle movsxd_mode.
2238 (OP_E_register): Likewise.
2240 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2241 register on movsxd. Add movsxd with 16-bit destination register
2242 for AMD64 and Intel64 ISAs.
2243 * i386-tbl.h: Regenerated.
2245 2020-01-27 Tamar Christina <tamar.christina@arm.com>
2248 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2249 * aarch64-asm-2.c: Regenerate
2250 * aarch64-dis-2.c: Likewise.
2251 * aarch64-opc-2.c: Likewise.
2253 2020-01-21 Jan Beulich <jbeulich@suse.com>
2255 * i386-opc.tbl (sysret): Drop DefaultSize.
2256 * i386-tbl.h: Re-generate.
2258 2020-01-21 Jan Beulich <jbeulich@suse.com>
2260 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2262 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2263 * i386-tbl.h: Re-generate.
2265 2020-01-20 Nick Clifton <nickc@redhat.com>
2267 * po/de.po: Updated German translation.
2268 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2269 * po/uk.po: Updated Ukranian translation.
2271 2020-01-20 Alan Modra <amodra@gmail.com>
2273 * hppa-dis.c (fput_const): Remove useless cast.
2275 2020-01-20 Alan Modra <amodra@gmail.com>
2277 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2279 2020-01-18 Nick Clifton <nickc@redhat.com>
2281 * configure: Regenerate.
2282 * po/opcodes.pot: Regenerate.
2284 2020-01-18 Nick Clifton <nickc@redhat.com>
2286 Binutils 2.34 branch created.
2288 2020-01-17 Christian Biesinger <cbiesinger@google.com>
2290 * opintl.h: Fix spelling error (seperate).
2292 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2294 * i386-opc.tbl: Add {vex} pseudo prefix.
2295 * i386-tbl.h: Regenerated.
2297 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2300 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2301 (neon_opcodes): Likewise.
2302 (select_arm_features): Make sure we enable MVE bits when selecting
2303 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2306 2020-01-16 Jan Beulich <jbeulich@suse.com>
2308 * i386-opc.tbl: Drop stale comment from XOP section.
2310 2020-01-16 Jan Beulich <jbeulich@suse.com>
2312 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2313 (extractps): Add VexWIG to SSE2AVX forms.
2314 * i386-tbl.h: Re-generate.
2316 2020-01-16 Jan Beulich <jbeulich@suse.com>
2318 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2319 Size64 from and use VexW1 on SSE2AVX forms.
2320 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2321 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2322 * i386-tbl.h: Re-generate.
2324 2020-01-15 Alan Modra <amodra@gmail.com>
2326 * tic4x-dis.c (tic4x_version): Make unsigned long.
2327 (optab, optab_special, registernames): New file scope vars.
2328 (tic4x_print_register): Set up registernames rather than
2329 malloc'd registertable.
2330 (tic4x_disassemble): Delete optable and optable_special. Use
2331 optab and optab_special instead. Throw away old optab,
2332 optab_special and registernames when info->mach changes.
2334 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2337 * z80-dis.c (suffix): Use .db instruction to generate double
2340 2020-01-14 Alan Modra <amodra@gmail.com>
2342 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2343 values to unsigned before shifting.
2345 2020-01-13 Thomas Troeger <tstroege@gmx.de>
2347 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2349 (print_insn_thumb16, print_insn_thumb32): Likewise.
2350 (print_insn): Initialize the insn info.
2351 * i386-dis.c (print_insn): Initialize the insn info fields, and
2354 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2356 * arc-opc.c (C_NE): Make it required.
2358 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2360 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2361 reserved register name.
2363 2020-01-13 Alan Modra <amodra@gmail.com>
2365 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2366 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2368 2020-01-13 Alan Modra <amodra@gmail.com>
2370 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2371 result of wasm_read_leb128 in a uint64_t and check that bits
2372 are not lost when copying to other locals. Use uint32_t for
2373 most locals. Use PRId64 when printing int64_t.
2375 2020-01-13 Alan Modra <amodra@gmail.com>
2377 * score-dis.c: Formatting.
2378 * score7-dis.c: Formatting.
2380 2020-01-13 Alan Modra <amodra@gmail.com>
2382 * score-dis.c (print_insn_score48): Use unsigned variables for
2383 unsigned values. Don't left shift negative values.
2384 (print_insn_score32): Likewise.
2385 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2387 2020-01-13 Alan Modra <amodra@gmail.com>
2389 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2391 2020-01-13 Alan Modra <amodra@gmail.com>
2393 * fr30-ibld.c: Regenerate.
2395 2020-01-13 Alan Modra <amodra@gmail.com>
2397 * xgate-dis.c (print_insn): Don't left shift signed value.
2398 (ripBits): Formatting, use 1u.
2400 2020-01-10 Alan Modra <amodra@gmail.com>
2402 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2403 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2405 2020-01-10 Alan Modra <amodra@gmail.com>
2407 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2408 and XRREG value earlier to avoid a shift with negative exponent.
2409 * m10200-dis.c (disassemble): Similarly.
2411 2020-01-09 Nick Clifton <nickc@redhat.com>
2414 * z80-dis.c (ld_ii_ii): Use correct cast.
2416 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2419 * z80-dis.c (ld_ii_ii): Use character constant when checking
2422 2020-01-09 Jan Beulich <jbeulich@suse.com>
2424 * i386-dis.c (SEP_Fixup): New.
2426 (dis386_twobyte): Use it for sysenter/sysexit.
2427 (enum x86_64_isa): Change amd64 enumerator to value 1.
2428 (OP_J): Compare isa64 against intel64 instead of amd64.
2429 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2431 * i386-tbl.h: Re-generate.
2433 2020-01-08 Alan Modra <amodra@gmail.com>
2435 * z8k-dis.c: Include libiberty.h
2436 (instr_data_s): Make max_fetched unsigned.
2437 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2438 Don't exceed byte_info bounds.
2439 (output_instr): Make num_bytes unsigned.
2440 (unpack_instr): Likewise for nibl_count and loop.
2441 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2443 * z8k-opc.h: Regenerate.
2445 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
2447 * arc-tbl.h (llock): Use 'LLOCK' as class.
2449 (scond): Use 'SCOND' as class.
2451 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
2454 2020-01-06 Alan Modra <amodra@gmail.com>
2456 * m32c-ibld.c: Regenerate.
2458 2020-01-06 Alan Modra <amodra@gmail.com>
2461 * z80-dis.c (suffix): Don't use a local struct buffer copy.
2462 Peek at next byte to prevent recursion on repeated prefix bytes.
2463 Ensure uninitialised "mybuf" is not accessed.
2464 (print_insn_z80): Don't zero n_fetch and n_used here,..
2465 (print_insn_z80_buf): ..do it here instead.
2467 2020-01-04 Alan Modra <amodra@gmail.com>
2469 * m32r-ibld.c: Regenerate.
2471 2020-01-04 Alan Modra <amodra@gmail.com>
2473 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2475 2020-01-04 Alan Modra <amodra@gmail.com>
2477 * crx-dis.c (match_opcode): Avoid shift left of signed value.
2479 2020-01-04 Alan Modra <amodra@gmail.com>
2481 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2483 2020-01-03 Jan Beulich <jbeulich@suse.com>
2485 * aarch64-tbl.h (aarch64_opcode_table): Use
2486 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2488 2020-01-03 Jan Beulich <jbeulich@suse.com>
2490 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
2491 forms of SUDOT and USDOT.
2493 2020-01-03 Jan Beulich <jbeulich@suse.com>
2495 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
2497 * opcodes/aarch64-dis-2.c: Re-generate.
2499 2020-01-03 Jan Beulich <jbeulich@suse.com>
2501 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
2503 * opcodes/aarch64-dis-2.c: Re-generate.
2505 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
2507 * z80-dis.c: Add support for eZ80 and Z80 instructions.
2509 2020-01-01 Alan Modra <amodra@gmail.com>
2511 Update year range in copyright notice of all files.
2513 For older changes see ChangeLog-2019
2515 Copyright (C) 2020 Free Software Foundation, Inc.
2517 Copying and distribution of this file, with or without modification,
2518 are permitted in any medium without royalty provided the copyright
2519 notice and this notice are preserved.
2525 version-control: never
projects / thirdparty / binutils-gdb.git / blob