opcodes/ChangeLog

   1 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
   2
   3         * mips-dis.c (mips_cp0_names_r3900): New variable.
   4         (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
   5         for "r3900".
   6
   7 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
   8
   9         * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
  10         and "mtthc2" to using the `G' rather than `g' operand code for
  11         the coprocessor control register referred.
  12
  13 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  14
  15         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
  16         entries with each other.
  17
  18 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
  19
  20         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
  21
  22 2021-05-25  Alan Modra  <amodra@gmail.com>
  23
  24         * cris-desc.c: Regenerate.
  25         * cris-desc.h: Regenerate.
  26         * cris-opc.h: Regenerate.
  27         * po/POTFILES.in: Regenerate.
  28
  29 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
  30
  31         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
  32         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
  33         (CGEN_CPUS): Add cris.
  34         (CRIS_DEPS): Define.
  35         (stamp-cris): New rule.
  36         * cgen.sh: Handle desc action.
  37         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
  38         * Makefile.in, configure: Regenerate.
  39
  40 2021-05-18  Job Noorman  <mtvec@pm.me>
  41
  42         PR 27814
  43         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
  44         the elf objects.
  45
  46 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
  47
  48         * arm-dis.c (mve_opcodes): Fix disassembly of
  49         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
  50         (is_mve_encoding_conflict): MVE vector loads should not match
  51         when P = W = 0.
  52         (is_mve_unpredictable): It's not unpredictable to use the same
  53         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
  54
  55 2021-05-11  Nick Clifton  <nickc@redhat.com>
  56
  57         PR 27840
  58         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
  59         the end of the code buffer.
  60
  61 2021-05-06  Stafford Horne  <shorne@gmail.com>
  62
  63         PR 21464
  64         * or1k-asm.c: Regenerate.
  65
  66 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
  67
  68         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
  69         info->insn_info_valid.
  70
  71 2021-04-26  Jan Beulich  <jbeulich@suse.com>
  72
  73         * i386-opc.tbl (lea): Add Optimize.
  74         * opcodes/i386-tbl.h: Re-generate.
  75
  76 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
  77
  78         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
  79         of l32r fetch and display referenced literal value.
  80
  81 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
  82
  83         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
  84         to 4 for literal disassembly.
  85
  86 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  87
  88         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
  89         for TLBI instruction.
  90
  91 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  92
  93         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
  94         DC instruction.
  95
  96 2021-04-19  Jan Beulich  <jbeulich@suse.com>
  97
  98         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
  99         "qualifier".
 100         (convert_mov_to_movewide): Add initializer for "value".
 101
 102 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 103
 104         * aarch64-opc.c: Add RME system registers.
 105
 106 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 107
 108         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
 109         "addi d,CV,z" to "c.mv d,CV".
 110
 111 2021-04-12  Alan Modra  <amodra@gmail.com>
 112
 113         * configure.ac (--enable-checking): Add support.
 114         * config.in: Regenerate.
 115         * configure: Regenerate.
 116
 117 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 118
 119         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 120         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 121
 122 2021-04-09  Alan Modra  <amodra@gmail.com>
 123
 124         * ppc-dis.c (struct dis_private): Add "special".
 125         (POWERPC_DIALECT): Delete.  Replace uses with..
 126         (private_data): ..this.  New inline function.
 127         (disassemble_init_powerpc): Init "special" names.
 128         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 129         field of prefix instructions.
 130         (bsearch_reloc, print_got_plt): New functions.
 131         (print_insn_powerpc): For pcrel instructions, print target address
 132         and symbol if known, and decode plt and got loads too.
 133
 134 2021-04-08  Alan Modra  <amodra@gmail.com>
 135
 136         PR 27684
 137         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 138
 139 2021-04-08  Alan Modra  <amodra@gmail.com>
 140
 141         PR 27676
 142         * ppc-opc.c (DCBT_EO): Move earlier.
 143         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 144         (powerpc_operands): Add THCT and THDS entries.
 145         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 146
 147 2021-04-06  Alan Modra  <amodra@gmail.com>
 148
 149         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 150         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 151         symbol_at_address_func.
 152
 153 2021-04-05  Alan Modra  <amodra@gmail.com>
 154
 155         * configure.ac: Don't check for limits.h, string.h, strings.h or
 156         stdlib.h.
 157         (AC_ISC_POSIX): Don't invoke.
 158         * sysdep.h: Include stdlib.h and string.h unconditionally.
 159         * i386-opc.h: Include limits.h unconditionally.
 160         * wasm32-dis.c: Likewise.
 161         * cgen-opc.c: Don't include alloca-conf.h.
 162         * config.in: Regenerate.
 163         * configure: Regenerate.
 164
 165 2021-04-01  Martin Liska  <mliska@suse.cz>
 166
 167         * arm-dis.c (strneq): Remove strneq and use startswith.
 168         * cr16-dis.c (print_insn_cr16): Likewise.
 169         * score-dis.c (streq): Likewise.
 170         (strneq): Likewise.
 171         * score7-dis.c (strneq): Likewise.
 172
 173 2021-04-01  Alan Modra  <amodra@gmail.com>
 174
 175         PR 27675
 176         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 177
 178 2021-03-31  Alan Modra  <amodra@gmail.com>
 179
 180         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 181         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 182         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 183         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 184         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 185         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 186         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 187         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 188         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 189         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 190         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 191         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 192         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 193         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 194         and TRUE with true throughout.
 195
 196 2021-03-31  Alan Modra  <amodra@gmail.com>
 197
 198         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 199         * aarch64-dis.h: Likewise.
 200         * aarch64-opc.c: Likewise.
 201         * avr-dis.c: Likewise.
 202         * csky-dis.c: Likewise.
 203         * nds32-asm.c: Likewise.
 204         * nds32-dis.c: Likewise.
 205         * nfp-dis.c: Likewise.
 206         * riscv-dis.c: Likewise.
 207         * s12z-dis.c: Likewise.
 208         * wasm32-dis.c: Likewise.
 209
 210 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 211
 212         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 213         (i386_seg_prefixes): New.
 214         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 215         (i386_seg_prefixes): Declare.
 216
 217 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 218
 219         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 220
 221 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 222
 223         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 224         * i386-reg.tbl (st): Move down.
 225         (st(0)): Delete. Extend comment.
 226         * i386-tbl.h: Re-generate.
 227
 228 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 229
 230         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 231         (cmpsd): Move next to cmps.
 232         (movsd): Move next to movs.
 233         (cmpxchg16b): Move to separate section.
 234         (fisttp, fisttpll): Likewise.
 235         (monitor, mwait): Likewise.
 236         * i386-tbl.h: Re-generate.
 237
 238 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 239
 240         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 241         (vpsadbw): Add C.
 242         * i386-tbl.h: Re-generate.
 243
 244 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 245
 246         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 247         pclmul, gfni): New templates. Use them wherever possible. Move
 248         SSE4.1 pextrw into respective section.
 249         * i386-tbl.h: Re-generate.
 250
 251 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 252
 253         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 254         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 255         "length".
 256         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 257         Convert all of their uses to representation in opcode.
 258
 259 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 260
 261         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 262         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 263         value of None. Shrink operands to 3 bits.
 264
 265 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 266
 267         * i386-gen.c (process_i386_opcode_modifier): New parameter
 268         "space".
 269         (output_i386_opcode): New local variable "space". Adjust
 270         process_i386_opcode_modifier() invocation.
 271         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 272         invocation.
 273         * i386-tbl.h: Re-generate.
 274
 275 2021-03-29  Alan Modra  <amodra@gmail.com>
 276
 277         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 278         (fp_qualifier_p, get_data_pattern): Likewise.
 279         (aarch64_get_operand_modifier_from_value): Likewise.
 280         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 281         (operand_variant_qualifier_p): Likewise.
 282         (qualifier_value_in_range_constraint_p): Likewise.
 283         (aarch64_get_qualifier_esize): Likewise.
 284         (aarch64_get_qualifier_nelem): Likewise.
 285         (aarch64_get_qualifier_standard_value): Likewise.
 286         (get_lower_bound, get_upper_bound): Likewise.
 287         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 288         (aarch64_print_operand): Likewise.
 289         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 290         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 291         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 292         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 293         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 294         (print_insn_tic6x): Likewise.
 295
 296 2021-03-29  Alan Modra  <amodra@gmail.com>
 297
 298         * arc-dis.c (extract_operand_value): Correct NULL cast.
 299         * frv-opc.h: Regenerate.
 300
 301 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 302
 303         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 304         MMX form.
 305         * i386-tbl.h: Re-generate.
 306
 307 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 308
 309         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 310         immediate in br.n instruction.
 311
 312 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 313
 314         * i386-dis.c (XMGatherD, VexGatherD): New.
 315         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 316         (print_insn): Check masking for S/G insns.
 317         (OP_E_memory): New local variable check_gather. Extend mandatory
 318         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 319         Extend check for disallowed 16-bit addressing.
 320         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 321         if()s to switch(). Check register conflicts for (VEX-encoded)
 322         gathers. Drop no longer reachable cases.
 323         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 324         vgatherdp*.
 325
 326 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 327
 328         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 329         zeroing-masking without masking.
 330
 331 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 332
 333         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 334         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 335         single-operand forms as deprecated.
 336         * i386-tbl.h: Re-generate.
 337
 338 2021-03-25  Alan Modra  <amodra@gmail.com>
 339
 340         PR 27647
 341         * ppc-opc.c (XLOCB_MASK): Delete.
 342         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 343         XLBH_MASK.
 344         (powerpc_opcodes): Accept a BH field on all extended forms of
 345         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 346
 347 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 348
 349         * i386-gen.c (output_i386_opcode): Drop processing of
 350         opcode_length. Calculate length from base_opcode. Adjust prefix
 351         encoding determination.
 352         (process_i386_opcodes): Drop output of fake opcode_length.
 353         * i386-opc.h (struct insn_template): Drop opcode_length field.
 354         * i386-opc.tbl: Drop opcode length field from all templates.
 355         * i386-tbl.h: Re-generate.
 356
 357 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 358
 359         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 360         parameter "prefix". Drop local variable "regular_encoding".
 361         Record prefix setting / check for consistency.
 362         (output_i386_opcode): Parse opcode_length and base_opcode
 363         earlier. Derive prefix encoding. Drop no longer applicable
 364         consistency checking. Adjust process_i386_opcode_modifier()
 365         invocation.
 366         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 367         invocation.
 368         * i386-tbl.h: Re-generate.
 369
 370 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 371
 372         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 373         check.
 374         * i386-opc.h (Prefix_*): Move #define-s.
 375         * i386-opc.tbl: Move pseudo prefix enumerator values to
 376         extension opcode field. Introduce pseudopfx template.
 377         * i386-tbl.h: Re-generate.
 378
 379 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 380
 381         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 382         comment.
 383         * i386-tbl.h: Re-generate.
 384
 385 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 386
 387         * i386-opc.h (struct insn_template): Move cpu_flags field past
 388         opcode_modifier one.
 389         * i386-tbl.h: Re-generate.
 390
 391 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 392
 393         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 394         * i386-opc.h (OpcodeSpace): New enumerator.
 395         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 396         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 397         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 398         (struct i386_opcode_modifier): New field opcodespace. Shrink
 399         opcodeprefix field.
 400         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 401         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 402         OpcodePrefix uses.
 403         * i386-tbl.h: Re-generate.
 404
 405 2021-03-22  Martin Liska  <mliska@suse.cz>
 406
 407         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 408         * arc-dis.c (parse_option): Likewise.
 409         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 410         * cris-dis.c (print_with_operands): Likewise.
 411         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 412         * i386-dis.c (print_insn): Likewise.
 413         * ia64-gen.c (fetch_insn_class): Likewise.
 414         (parse_resource_users): Likewise.
 415         (in_iclass): Likewise.
 416         (lookup_specifier): Likewise.
 417         (insert_opcode_dependencies): Likewise.
 418         * mips-dis.c (parse_mips_ase_option): Likewise.
 419         (parse_mips_dis_option): Likewise.
 420         * s390-dis.c (disassemble_init_s390): Likewise.
 421         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 422
 423 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 424
 425         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 426
 427 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 428
 429         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 430         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 431
 432 2021-03-12  Alan Modra  <amodra@gmail.com>
 433
 434         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 435
 436 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 437
 438         * i386-dis.c (OP_XMM): Re-order checks.
 439
 440 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 441
 442         * i386-dis.c (putop): Drop need_vex check when also checking
 443         vex.evex.
 444         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 445         checking vex.b.
 446
 447 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 448
 449         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 450         checks. Move case label past broadcast check.
 451
 452 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 453
 454         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 455         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 456         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 457         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 458         EVEX_W_0F38C7_M_0_L_2): Delete.
 459         (REG_EVEX_0F38C7_M_0_L_2): New.
 460         (intel_operand_size): Handle VEX and EVEX the same for
 461         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 462         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 463         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 464         vex_vsib_q_w_d_mode uses.
 465         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 466         0F38A1, and 0F38A3 entries.
 467         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 468         entry.
 469         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 470         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 471         0F38A3 entries.
 472
 473 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 474
 475         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 476         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 477         MOD_VEX_0FXOP_09_12): Rename to ...
 478         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 479         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 480         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 481         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 482         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 483         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 484         (reg_table): Adjust comments.
 485         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 486         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 487         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 488         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 489         (vex_len_table): Adjust opcode 0A_12 entry.
 490         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 491         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 492         (rm_table): Move hreset entry.
 493
 494 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 495
 496         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 497         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 498         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 499         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 500         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 501         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 502         (get_valid_dis386): Also handle 512-bit vector length when
 503         vectoring into vex_len_table[].
 504         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 505         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 506         entries.
 507         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 508         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 509         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 510         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 511         entries.
 512
 513 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 514
 515         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 516         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 517         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 518         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 519         entries.
 520         * i386-dis-evex-len.h (evex_len_table): Likewise.
 521         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 522
 523 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 524
 525         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 526         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 527         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 528         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 529         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 530         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 531         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 532         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 533         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 534         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 535         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 536         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 537         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 538         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 539         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 540         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 541         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 542         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 543         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 544         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 545         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 546         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 547         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 548         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 549         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 550         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 551         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 552         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 553         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 554         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 555         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 556         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 557         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 558         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 559         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 560         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 561         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 562         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 563         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 564         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 565         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 566         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 567         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 568         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 569         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 570         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 571         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 572         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 573         EVEX_W_0F3A43_L_n): New.
 574         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 575         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 576         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 577         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 578         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 579         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 580         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 581         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 582         0F385B, 0F38C6, and 0F38C7 entries.
 583         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 584         0F38C6 and 0F38C7.
 585         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 586         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 587         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 588         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 589
 590 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 591
 592         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 593         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 594         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 595         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 596         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 597         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 598         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 599         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 600         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 601         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 602         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 603         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 604         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 605         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 606         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 607         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 608         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 609         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 610         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 611         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 612         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 613         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 614         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 615         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 616         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 617         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 618         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 619         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 620         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 621         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 622         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 623         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 624         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 625         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 626         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 627         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 628         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 629         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 630         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 631         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 632         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 633         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 634         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 635         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 636         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 637         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 638         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 639         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 640         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 641         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 642         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 643         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 644         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 645         VEX_W_0F99_P_2_LEN_0): Delete.
 646         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 647         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 648         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 649         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 650         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 651         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 652         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 653         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 654         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 655         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 656         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 657         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 658         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 659         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 660         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 661         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 662         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 663         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 664         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 665         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 666         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 667         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 668         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 669         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 670         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 671         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 672         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 673         (prefix_table): No longer link to vex_len_table[] for opcodes
 674         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 675         0F92, 0F93, 0F98, and 0F99.
 676         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 677         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 678         0F98, and 0F99.
 679         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 680         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 681         0F98, and 0F99.
 682         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 683         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 684         0F98, and 0F99.
 685         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 686         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 687         0F98, and 0F99.
 688
 689 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 690
 691         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 692         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 693         REG_VEX_0F73_M_0 respectively.
 694         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 695         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 696         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 697         MOD_VEX_0F73_REG_7): Delete.
 698         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 699         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 700         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 701         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 702         PREFIX_VEX_0F3AF0_L_0 respectively.
 703         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 704         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 705         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 706         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 707         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 708         VEX_LEN_0F38F7): New.
 709         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 710         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 711         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 712         0F38F3.
 713         (prefix_table): No longer link to vex_len_table[] for opcodes
 714         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 715         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 716         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 717         0F38F6, 0F38F7, and 0F3AF0.
 718         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 719         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 720         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 721         0F73.
 722
 723 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 724
 725         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 726         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 727         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 728         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 729         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 730         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 731         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 732         73.
 733         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 734         0F72, and 0F73.
 735         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 736         0F73.
 737
 738 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 739
 740         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 741         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 742         (reg_table): Don't link to mod_table[] where not needed. Add
 743         PREFIX_IGNORED to nop entries.
 744         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 745         (mod_table): Add nop entries next to prefetch ones. Drop
 746         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 747         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 748         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 749         PREFIX_OPCODE from endbr* entries.
 750         (get_valid_dis386): Also consider entry's name when zapping
 751         vindex.
 752         (print_insn): Handle PREFIX_IGNORED.
 753
 754 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 755
 756         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 757         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 758         element.
 759         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 760         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 761         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 762         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 763         (struct i386_opcode_modifier): Delete notrackprefixok,
 764         islockable, hleprefixok, and repprefixok fields. Add prefixok
 765         field.
 766         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 767         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 768         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 769         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 770         Replace HLEPrefixOk.
 771         * opcodes/i386-tbl.h: Re-generate.
 772
 773 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 774
 775         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 776         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 777         64-bit form.
 778         * opcodes/i386-tbl.h: Re-generate.
 779
 780 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 781
 782         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 783         for {} instead of {0}. Don't look for '0'.
 784         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 785         size specifiers.
 786
 787 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 788
 789         PR 27158
 790         * riscv-dis.c (print_insn_args): Updated encoding macros.
 791         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 792         (match_c_addi16sp): Updated encoding macros.
 793         (match_c_lui): Likewise.
 794         (match_c_lui_with_hint): Likewise.
 795         (match_c_addi4spn): Likewise.
 796         (match_c_slli): Likewise.
 797         (match_slli_as_c_slli): Likewise.
 798         (match_c_slli64): Likewise.
 799         (match_srxi_as_c_srxi): Likewise.
 800         (riscv_insn_types): Added .insn css/cl/cs.
 801
 802 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 803
 804         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 805         (default_priv_spec): Updated type to riscv_spec_class.
 806         (parse_riscv_dis_option): Updated.
 807         * riscv-opc.c: Moved stuff and make the file tidy.
 808
 809 2021-02-17  Alan Modra  <amodra@gmail.com>
 810
 811         * wasm32-dis.c: Include limits.h.
 812         (CHAR_BIT): Provide backup define.
 813         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 814         Correct signed overflow checking.
 815
 816 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 817
 818         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 819         * i386-tbl.h: Re-generate.
 820
 821 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 822
 823         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 824         Oword.
 825         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 826
 827 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 828
 829         * s390-mkopc.c (main): Accept arch14 as cpu string.
 830         * s390-opc.txt: Add new arch14 instructions.
 831
 832 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 833
 834         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 835         favour of LIBINTL.
 836         * configure: Regenerated.
 837
 838 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 839
 840         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 841         * tic54x-opc.c (regs): Rename to ...
 842         (tic54x_regs): ... this.
 843         (mmregs): Rename to ...
 844         (tic54x_mmregs): ... this.
 845         (condition_codes): Rename to ...
 846         (tic54x_condition_codes): ... this.
 847         (cc2_codes): Rename to ...
 848         (tic54x_cc2_codes): ... this.
 849         (cc3_codes): Rename to ...
 850         (tic54x_cc3_codes): ... this.
 851         (status_bits): Rename to ...
 852         (tic54x_status_bits): ... this.
 853         (misc_symbols): Rename to ...
 854         (tic54x_misc_symbols): ... this.
 855
 856 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 857
 858         * riscv-opc.c (MASK_RVB_IMM): Removed.
 859         (riscv_opcodes): Removed zb* instructions.
 860         (riscv_ext_version_table): Removed versions for zb*.
 861
 862 2021-01-26  Alan Modra  <amodra@gmail.com>
 863
 864         * i386-gen.c (parse_template): Ensure entire template_instance
 865         is initialised.
 866
 867 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 868
 869         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 870         (riscv_fpr_names_abi): Likewise.
 871         (riscv_opcodes): Likewise.
 872         (riscv_insn_types): Likewise.
 873
 874 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 875
 876         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 877
 878 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 879
 880         * riscv-dis.c: Comments tidy and improvement.
 881         * riscv-opc.c: Likewise.
 882
 883 2021-01-13  Alan Modra  <amodra@gmail.com>
 884
 885         * Makefile.in: Regenerate.
 886
 887 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 888
 889         PR binutils/26792
 890         * configure.ac: Use GNU_MAKE_JOBSERVER.
 891         * aclocal.m4: Regenerated.
 892         * configure: Likewise.
 893
 894 2021-01-12  Nick Clifton  <nickc@redhat.com>
 895
 896         * po/sr.po: Updated Serbian translation.
 897
 898 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 899
 900         PR ld/27173
 901         * configure: Regenerated.
 902
 903 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 904
 905         * aarch64-asm-2.c: Regenerate.
 906         * aarch64-dis-2.c: Likewise.
 907         * aarch64-opc-2.c: Likewise.
 908         * aarch64-opc.c (aarch64_print_operand):
 909         Delete handling of AARCH64_OPND_CSRE_CSR.
 910         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 911         (CSRE): Likewise.
 912         (_CSRE_INSN): Likewise.
 913         (aarch64_opcode_table): Delete csr.
 914
 915 2021-01-11  Nick Clifton  <nickc@redhat.com>
 916
 917         * po/de.po: Updated German translation.
 918         * po/fr.po: Updated French translation.
 919         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 920         * po/sv.po: Updated Swedish translation.
 921         * po/uk.po: Updated Ukranian translation.
 922
 923 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 924
 925         * configure: Regenerated.
 926
 927 2021-01-09  Nick Clifton  <nickc@redhat.com>
 928
 929         * configure: Regenerate.
 930         * po/opcodes.pot: Regenerate.
 931
 932 2021-01-09  Nick Clifton  <nickc@redhat.com>
 933
 934         * 2.36 release branch crated.
 935
 936 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 937
 938         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 939         (DW, (XRC_MASK): Define.
 940         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 941
 942 2021-01-09  Alan Modra  <amodra@gmail.com>
 943
 944         * configure: Regenerate.
 945
 946 2021-01-08  Nick Clifton  <nickc@redhat.com>
 947
 948         * po/sv.po: Updated Swedish translation.
 949
 950 2021-01-08  Nick Clifton  <nickc@redhat.com>
 951
 952         PR 27129
 953         * aarch64-dis.c (determine_disassembling_preference): Move call to
 954         aarch64_match_operands_constraint outside of the assertion.
 955         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 956         Replace with a return of FALSE.
 957
 958         PR 27139
 959         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 960         core system register.
 961
 962 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 963
 964         * configure: Regenerate.
 965
 966 2021-01-07  Nick Clifton  <nickc@redhat.com>
 967
 968         * po/fr.po: Updated French translation.
 969
 970 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 971
 972         * m68k-opc.c (chkl): Change minimum architecture requirement to
 973         m68020.
 974
 975 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 976
 977         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 978
 979 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 980             Jim Wilson  <jimw@sifive.com>
 981             Andrew Waterman  <andrew@sifive.com>
 982             Maxim Blinov  <maxim.blinov@embecosm.com>
 983             Kito Cheng  <kito.cheng@sifive.com>
 984             Nelson Chu  <nelson.chu@sifive.com>
 985
 986         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
 987         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 988
 989 2021-01-01  Alan Modra  <amodra@gmail.com>
 990
 991         Update year range in copyright notice of all files.
 992
 993 For older changes see ChangeLog-2020
 994 \f
 995 Copyright (C) 2021 Free Software Foundation, Inc.
 996
 997 Copying and distribution of this file, with or without modification,
 998 are permitted in any medium without royalty provided the copyright
 999 notice and this notice are preserved.
1000
1001 Local Variables:
1002 mode: change-log
1003 left-margin: 8
1004 fill-column: 74
1005 version-control: never
1006 End: