1 2020-09-02 Alan Modra <amodra@gmail.com>
3 * csky-dis.c (print_insn_csky): Use unsigned type for "given".
5 2020-09-02 Alan Modra <amodra@gmail.com>
7 * crx-dis.c: Whitespace.
8 (print_arg): Use unsigned type for longdisp and mask variables,
9 and for left shift constant.
11 2020-09-02 Alan Modra <amodra@gmail.com>
13 * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
14 * bpf-ibld.c: Regenerate.
15 * epiphany-ibld.c: Regenerate.
16 * fr30-ibld.c: Regenerate.
17 * frv-ibld.c: Regenerate.
18 * ip2k-ibld.c: Regenerate.
19 * iq2000-ibld.c: Regenerate.
20 * lm32-ibld.c: Regenerate.
21 * m32c-ibld.c: Regenerate.
22 * m32r-ibld.c: Regenerate.
23 * mep-ibld.c: Regenerate.
24 * mt-ibld.c: Regenerate.
25 * or1k-ibld.c: Regenerate.
26 * xc16x-ibld.c: Regenerate.
27 * xstormy16-ibld.c: Regenerate.
29 2020-09-02 Alan Modra <amodra@gmail.com>
31 * bfin-dis.c (MASKBITS): Use SIGNBIT.
33 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
35 * csky-opc.h (csky_v2_opcodes): Move divul and divsl
36 to CSKYV2_ISA_3E3R3 instruction set.
38 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
40 * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
42 2020-09-01 Alan Modra <amodra@gmail.com>
44 * mep-ibld.c: Regenerate.
46 2020-08-31 Cooper Qu <cooper.qu@linux.alibaba.com>
48 * csky-dis.c (csky_output_operand): Assign dis_info.value for
51 2020-08-30 Alan Modra <amodra@gmail.com>
53 * cr16-dis.c: Formatting.
54 (parameter): Delete struct typedef. Use dwordU instead
56 (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
58 (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
60 2020-08-29 Alan Modra <amodra@gmail.com>
63 * csky-opc.h (MAX_OPRND_NUM): Define to 5.
64 (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
66 2020-08-28 Alan Modra <amodra@gmail.com>
70 * cgen-ibld.in (insert_1): Use 1UL in forming mask.
71 (extract_normal): Likewise.
72 (insert_normal): Likewise, and move past zero length test.
73 (put_insn_int_value): Handle mask for zero length, use 1UL.
74 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
75 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
76 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
77 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
79 2020-08-28 Cooper Qu <cooper.qu@linux.alibaba.com>
81 * csky-dis.c (CSKY_DEFAULT_ISA): Define.
82 (csky_dis_info): Add member isa.
83 (csky_find_inst_info): Skip instructions that do not belong to
85 (csky_get_disassembler): Get infomation from attribute section.
86 (print_insn_csky): Set defualt ISA flag.
87 * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
88 * csky-opc.h (struct csky_opcode): Change isa_flag16 and
89 isa_flag32'type to unsigned 64 bits.
91 2020-08-26 Jose E. Marchesi <jemarch@gnu.org>
93 * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
95 2020-08-26 David Faust <david.faust@oracle.com>
97 * bpf-desc.c: Regenerate.
98 * bpf-desc.h: Likewise.
99 * bpf-opc.c: Likewise.
100 * bpf-opc.h: Likewise.
101 * disassemble.c (disassemble_init_for_target): Set bits for xBPF
102 ISA when appropriate.
104 2020-08-25 Alan Modra <amodra@gmail.com>
107 * vax-dis.c (parse_disassembler_options): Always add at least one
108 to entry_addr_total_slots.
110 2020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
112 * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
113 in other CPUs to speed up disassembling.
114 * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
115 Change plsli.u16 to plsli.16, change sync's operand format.
117 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
119 * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
121 2020-08-21 Nick Clifton <nickc@redhat.com>
123 * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
126 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
128 * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
130 2020-08-19 Alan Modra <amodra@gmail.com>
132 * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
135 2020-08-18 Peter Bergner <bergner@linux.ibm.com>
137 * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
138 <xvcvbf16spn>: ...to this.
140 2020-08-12 Alex Coplan <alex.coplan@arm.com>
142 * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
144 2020-08-12 Nick Clifton <nickc@redhat.com>
146 * po/sr.po: Updated Serbian translation.
148 2020-08-11 Alan Modra <amodra@gmail.com>
150 * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
152 2020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
154 * aarch64-opc.c (aarch64_print_operand):
155 (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
156 (aarch64_sys_reg_supported_p): Function removed.
157 (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
158 (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
161 2020-08-10 Alan Modra <amodra@gmail.com>
163 * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
166 2020-08-10 Alan Modra <amodra@gmail.com>
168 * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
169 Enable icbt for power5, miso for power8.
171 2020-08-10 Alan Modra <amodra@gmail.com>
173 * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
174 mtvsrd, and similarly for mfvsrd.
176 2020-08-04 Christian Groessler <chris@groessler.org>
177 Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
179 * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
180 opcodes (special "out" to absolute address).
181 * z8k-opc.h: Regenerate.
183 2020-07-30 H.J. Lu <hongjiu.lu@intel.com>
186 * i386-opc.h (Prefix_Disp8): New.
187 (Prefix_Disp16): Likewise.
188 (Prefix_Disp32): Likewise.
189 (Prefix_Load): Likewise.
190 (Prefix_Store): Likewise.
191 (Prefix_VEX): Likewise.
192 (Prefix_VEX3): Likewise.
193 (Prefix_EVEX): Likewise.
194 (Prefix_REX): Likewise.
195 (Prefix_NoOptimize): Likewise.
196 * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
197 * i386-tbl.h: Regenerated.
199 2020-07-29 Andreas Arnez <arnez@linux.ibm.com>
201 * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
202 default case with abort() instead of printing an error message and
203 continuing, to avoid a maybe-uninitialized warning.
205 2020-07-24 Nick Clifton <nickc@redhat.com>
207 * po/de.po: Updated German translation.
209 2020-07-21 Jan Beulich <jbeulich@suse.com>
211 * i386-dis.c (OP_E_memory): Revert previous change.
213 2020-07-15 H.J. Lu <hongjiu.lu@intel.com>
216 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
217 without base nor index registers.
219 2020-07-15 Jan Beulich <jbeulich@suse.com>
221 * i386-dis.c (putop): Move 'V' and 'W' handling.
223 2020-07-15 Jan Beulich <jbeulich@suse.com>
225 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
226 construct for push/pop of register.
227 (putop): Honor cond when handling 'P'. Drop handling of plain
230 2020-07-15 Jan Beulich <jbeulich@suse.com>
232 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
233 description. Drop '&' description. Use P for push of immediate,
234 pushf/popf, enter, and leave. Use %LP for lret/retf.
235 (dis386_twobyte): Use P for push/pop of fs/gs.
236 (reg_table): Use P for push/pop. Use @ for near call/jmp.
237 (x86_64_table): Use P for far call/jmp.
238 (putop): Drop handling of 'U' and '&'. Move and adjust handling
239 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
241 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
242 and dqw_mode (unconditional).
244 2020-07-14 H.J. Lu <hongjiu.lu@intel.com>
247 * i386-dis.c (OP_E_memory): Without base nor index registers,
248 32-bit displacement to 64 bits.
250 2020-07-14 Claudiu Zissulescu <claziss@gmail.com>
252 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
253 faulty double register pair is detected.
255 2020-07-14 Jan Beulich <jbeulich@suse.com>
257 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
259 2020-07-14 Jan Beulich <jbeulich@suse.com>
261 * i386-dis.c (OP_R, Rm): Delete.
262 (MOD_0F24, MOD_0F26): Rename to ...
263 (X86_64_0F24, X86_64_0F26): ... respectively.
264 (dis386): Update 'L' and 'Z' comments.
265 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
267 (mod_table): Move opcode 0F24 and 0F26 entries ...
268 (x86_64_table): ... here.
269 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
272 2020-07-14 Jan Beulich <jbeulich@suse.com>
274 * i386-dis.c (Rd, Rdq, MaskR): Delete.
275 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
276 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
277 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
278 MOD_EVEX_0F387C): New enumerators.
279 (reg_table): Use Edq for rdssp.
280 (prefix_table): Use Edq for incssp.
281 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
282 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
283 ktest*, and kshift*. Use Edq / MaskE for kmov*.
284 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
285 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
286 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
287 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
288 0F3828_P_1 and 0F3838_P_1.
289 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
290 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
292 2020-07-14 Jan Beulich <jbeulich@suse.com>
294 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
295 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
296 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
297 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
298 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
299 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
300 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
301 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
302 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
303 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
304 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
305 (reg_table, prefix_table, three_byte_table, vex_table,
306 vex_len_table, mod_table, rm_table): Replace / remove respective
308 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
309 of PREFIX_DATA in used_prefixes.
311 2020-07-14 Jan Beulich <jbeulich@suse.com>
313 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
314 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
315 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
316 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
317 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
318 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
319 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
320 VEX_W_0F3A33_L_0): Delete.
321 (dis386): Adjust "BW" description.
322 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
323 0F3A31, 0F3A32, and 0F3A33.
324 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
326 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
329 2020-07-14 Jan Beulich <jbeulich@suse.com>
331 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
332 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
333 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
334 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
335 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
336 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
337 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
338 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
339 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
340 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
341 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
342 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
343 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
344 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
345 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
346 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
347 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
348 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
349 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
350 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
351 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
352 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
353 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
354 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
355 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
356 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
357 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
358 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
359 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
360 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
361 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
362 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
363 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
364 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
365 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
366 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
367 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
368 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
369 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
370 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
371 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
372 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
373 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
374 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
375 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
376 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
377 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
378 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
379 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
380 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
381 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
382 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
383 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
384 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
385 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
386 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
387 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
388 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
389 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
390 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
391 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
392 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
393 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
394 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
395 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
396 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
397 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
398 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
399 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
400 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
401 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
402 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
403 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
404 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
405 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
406 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
407 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
408 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
409 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
410 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
411 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
412 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
413 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
414 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
415 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
416 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
417 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
418 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
419 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
420 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
421 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
422 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
423 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
424 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
425 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
426 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
427 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
428 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
429 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
430 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
431 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
432 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
433 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
434 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
435 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
436 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
437 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
438 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
439 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
440 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
441 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
442 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
443 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
444 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
445 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
446 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
447 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
448 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
449 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
450 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
451 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
452 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
453 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
454 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
455 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
456 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
457 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
458 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
459 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
460 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
461 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
462 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
463 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
464 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
465 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
466 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
467 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
468 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
469 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
470 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
471 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
472 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
473 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
474 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
475 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
476 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
477 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
478 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
479 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
480 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
481 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
482 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
483 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
484 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
485 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
486 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
487 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
488 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
489 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
490 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
491 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
492 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
493 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
494 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
495 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
496 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
497 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
498 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
499 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
500 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
501 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
502 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
503 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
504 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
505 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
506 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
507 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
508 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
509 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
510 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
511 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
512 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
513 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
514 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
515 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
516 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
517 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
518 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
519 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
520 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
521 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
522 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
523 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
524 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
525 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
526 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
527 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
528 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
529 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
530 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
531 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
532 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
533 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
534 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
535 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
536 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
537 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
538 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
539 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
540 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
541 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
542 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
543 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
544 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
545 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
546 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
547 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
548 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
549 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
550 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
551 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
552 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
553 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
554 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
555 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
556 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
557 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
558 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
559 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
560 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
561 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
562 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
563 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
564 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
565 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
566 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
567 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
568 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
569 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
570 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
571 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
572 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
573 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
574 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
575 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
576 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
577 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
578 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
579 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
580 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
581 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
582 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
583 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
584 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
585 EVEX_W_0F3A72_P_2): Rename to ...
586 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
587 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
588 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
589 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
590 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
591 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
592 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
593 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
594 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
595 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
596 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
597 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
598 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
599 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
600 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
601 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
602 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
603 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
604 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
605 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
606 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
607 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
608 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
609 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
610 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
611 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
612 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
613 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
614 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
615 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
616 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
617 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
618 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
619 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
620 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
621 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
622 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
623 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
624 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
625 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
626 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
627 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
628 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
629 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
630 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
631 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
632 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
633 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
634 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
635 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
636 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
637 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
638 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
639 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
640 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
641 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
642 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
643 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
644 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
645 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
646 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
647 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
648 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
649 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
650 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
651 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
652 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
653 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
654 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
655 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
656 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
657 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
659 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
660 vex_w_table, mod_table): Replace / remove respective entries.
661 (print_insn): Move up dp->prefix_requirement handling. Handle
663 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
664 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
665 Replace / remove respective entries.
667 2020-07-14 Jan Beulich <jbeulich@suse.com>
669 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
670 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
671 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
672 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
673 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
675 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
676 0F2C, 0F2D, 0F2E, and 0F2F.
677 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
680 2020-07-14 Jan Beulich <jbeulich@suse.com>
682 * i386-dis.c (OP_VexR, VexScalarR): New.
683 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
684 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
685 need_vex_reg): Delete.
686 (prefix_table): Replace VexScalar by VexScalarR and
687 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
688 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
689 (vex_len_table): Replace EXqVexScalarS by EXqS.
690 (get_valid_dis386): Don't set need_vex_reg.
691 (print_insn): Don't initialize need_vex_reg.
692 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
693 q_scalar_swap_mode cases.
694 (OP_EX): Don't check for d_scalar_swap_mode and
696 (OP_VEX): Done check need_vex_reg.
697 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
698 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
699 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
701 2020-07-14 Jan Beulich <jbeulich@suse.com>
703 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
704 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
705 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
706 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
707 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
708 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
709 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
710 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
711 (vex_table): Replace Vex128 by Vex.
712 (vex_len_table): Likewise. Adjust referenced enum names.
713 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
714 referenced enum names.
715 (OP_VEX): Drop vex128_mode and vex256_mode cases.
716 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
718 2020-07-14 Jan Beulich <jbeulich@suse.com>
720 * i386-dis.c (dis386): "LW" description now applies to "DQ".
721 (putop): Handle "DQ". Don't handle "LW" anymore.
722 (prefix_table, mod_table): Replace %LW by %DQ.
723 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
725 2020-07-14 Jan Beulich <jbeulich@suse.com>
727 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
728 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
729 d_scalar_swap_mode case handling. Move shift adjsutment into
730 the case its applicable to.
732 2020-07-14 Jan Beulich <jbeulich@suse.com>
734 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
735 (EXbScalar, EXwScalar): Fold to ...
736 (EXbwUnit): ... this.
737 (b_scalar_mode, w_scalar_mode): Fold to ...
738 (bw_unit_mode): ... this.
739 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
740 w_scalar_mode handling by bw_unit_mode one.
741 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
743 * i386-dis-evex-prefix.h: ... here.
745 2020-07-14 Jan Beulich <jbeulich@suse.com>
747 * i386-dis.c (PCMPESTR_Fixup): Delete.
748 (dis386): Adjust "LQ" description.
749 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
750 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
751 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
752 vpcmpestrm, and vpcmpestri.
753 (putop): Honor "cond" when handling LQ.
754 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
755 vcvtsi2ss and vcvtusi2ss.
756 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
757 vcvtsi2sd and vcvtusi2sd.
759 2020-07-14 Jan Beulich <jbeulich@suse.com>
761 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
762 (simd_cmp_op): Add const.
763 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
764 (CMP_Fixup): Handle VEX case.
765 (prefix_table): Replace VCMP by CMP.
766 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
768 2020-07-14 Jan Beulich <jbeulich@suse.com>
770 * i386-dis.c (MOVBE_Fixup): Delete.
772 (prefix_table): Use Mv for movbe entries.
774 2020-07-14 Jan Beulich <jbeulich@suse.com>
776 * i386-dis.c (CRC32_Fixup): Delete.
777 (prefix_table): Use Eb/Ev for crc32 entries.
779 2020-07-14 Jan Beulich <jbeulich@suse.com>
781 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
782 Conditionalize invocations of "USED_REX (0)".
784 2020-07-14 Jan Beulich <jbeulich@suse.com>
786 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
787 CH, DH, BH, AX, DX): Delete.
788 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
789 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
790 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
792 2020-07-10 Lili Cui <lili.cui@intel.com>
794 * i386-dis.c (TMM): New.
797 (MVexSIBMEM): Likewise.
798 (tmm_mode): Likewise.
799 (vex_sibmem_mode): Likewise.
800 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
801 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
802 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
803 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
804 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
805 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
806 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
807 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
808 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
809 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
810 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
811 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
812 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
813 (PREFIX_VEX_0F3849_X86_64): Likewise.
814 (PREFIX_VEX_0F384B_X86_64): Likewise.
815 (PREFIX_VEX_0F385C_X86_64): Likewise.
816 (PREFIX_VEX_0F385E_X86_64): Likewise.
817 (X86_64_VEX_0F3849): Likewise.
818 (X86_64_VEX_0F384B): Likewise.
819 (X86_64_VEX_0F385C): Likewise.
820 (X86_64_VEX_0F385E): Likewise.
821 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
822 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
823 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
824 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
825 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
826 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
827 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
828 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
829 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
830 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
831 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
832 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
833 (VEX_W_0F3849_X86_64_P_0): Likewise.
834 (VEX_W_0F3849_X86_64_P_2): Likewise.
835 (VEX_W_0F3849_X86_64_P_3): Likewise.
836 (VEX_W_0F384B_X86_64_P_1): Likewise.
837 (VEX_W_0F384B_X86_64_P_2): Likewise.
838 (VEX_W_0F384B_X86_64_P_3): Likewise.
839 (VEX_W_0F385C_X86_64_P_1): Likewise.
840 (VEX_W_0F385E_X86_64_P_0): Likewise.
841 (VEX_W_0F385E_X86_64_P_1): Likewise.
842 (VEX_W_0F385E_X86_64_P_2): Likewise.
843 (VEX_W_0F385E_X86_64_P_3): Likewise.
844 (names_tmm): Likewise.
845 (att_names_tmm): Likewise.
846 (intel_operand_size): Handle void_mode.
847 (OP_XMM): Handle tmm_mode.
850 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
851 CpuAMX_BF16 and CpuAMX_TILE.
852 (operand_type_shorthands): Add RegTMM.
853 (operand_type_init): Likewise.
854 (operand_types): Add Tmmword.
855 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
856 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
857 * i386-opc.h (CpuAMX_INT8): New.
858 (CpuAMX_BF16): Likewise.
859 (CpuAMX_TILE): Likewise.
862 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
863 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
864 (i386_operand_type): Add tmmword.
865 * i386-opc.tbl: Add AMX instructions.
866 * i386-reg.tbl: Add AMX registers.
867 * i386-init.h: Regenerated.
868 * i386-tbl.h: Likewise.
870 2020-07-08 Jan Beulich <jbeulich@suse.com>
872 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
873 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
875 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
876 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
878 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
879 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
880 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
881 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
882 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
883 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
884 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
885 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
886 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
887 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
888 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
889 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
890 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
891 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
892 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
893 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
894 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
895 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
896 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
897 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
898 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
899 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
900 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
901 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
902 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
903 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
904 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
905 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
906 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
907 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
908 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
909 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
910 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
911 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
912 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
913 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
914 (reg_table): Re-order XOP entries. Adjust their operands.
915 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
916 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
917 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
918 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
919 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
920 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
921 entries by references ...
922 (vex_len_table): ... to resepctive new entries here. For several
923 new and existing entries reference ...
924 (vex_w_table): ... new entries here.
925 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
927 2020-07-08 Jan Beulich <jbeulich@suse.com>
929 * i386-dis.c (XMVexScalarI4): Define.
930 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
931 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
932 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
933 (vex_len_table): Move scalar FMA4 entries ...
934 (prefix_table): ... here.
935 (OP_REG_VexI4): Handle scalar_mode.
936 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
937 * i386-tbl.h: Re-generate.
939 2020-07-08 Jan Beulich <jbeulich@suse.com>
941 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
943 (OP_VexW, VexW): New.
944 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
945 for shifts and rotates by register.
947 2020-07-08 Jan Beulich <jbeulich@suse.com>
949 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
950 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
951 OP_EX_VexReg): Delete.
952 (OP_VexI4, VexI4): New.
953 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
954 (prefix_table): ... here.
955 (print_insn): Drop setting of vex_w_done.
957 2020-07-08 Jan Beulich <jbeulich@suse.com>
959 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
960 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
961 (xop_table): Replace operands of 4-operand insns.
962 (OP_REG_VexI4): Move VEX.W based operand swaping here.
964 2020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
966 * arc-opc.c (insert_rbd): New function.
969 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
972 2020-07-07 Jan Beulich <jbeulich@suse.com>
974 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
975 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
976 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
977 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
979 (putop): Handle "BW".
980 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
981 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
983 * i386-dis-evex-prefix.h: ... here.
985 2020-07-06 Jan Beulich <jbeulich@suse.com>
987 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
988 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
989 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
990 VEX_W_0FXOP_09_83): New enumerators.
991 (xop_table): Reference the above.
992 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
993 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
994 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
995 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
997 2020-07-06 Jan Beulich <jbeulich@suse.com>
999 * i386-dis.c (EVEX_W_0F3838_P_1,
1000 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
1001 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
1002 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
1003 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
1004 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
1005 (putop): Centralize management of last[]. Delete SAVE_LAST.
1006 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
1007 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
1008 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
1009 * i386-dis-evex-prefix.h: here.
1011 2020-07-06 Jan Beulich <jbeulich@suse.com>
1013 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
1014 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
1015 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
1016 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
1018 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
1019 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
1020 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
1021 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
1022 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
1023 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
1024 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1025 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
1026 these, respectively.
1027 * i386-dis-evex-len.h: Adjust comments.
1028 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
1029 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1030 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1031 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
1032 MOD_EVEX_0F385B_P_2_W_1 table entries.
1033 * i386-dis-evex-w.h: Reference mod_table[] for
1034 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
1037 2020-07-06 Jan Beulich <jbeulich@suse.com>
1039 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
1040 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
1042 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
1043 Likewise. Mark 256-bit entries invalid.
1045 2020-07-06 Jan Beulich <jbeulich@suse.com>
1047 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1048 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1049 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1050 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1051 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1052 PREFIX_EVEX_0F382B): Delete.
1053 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
1054 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
1055 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
1056 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
1057 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
1059 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
1060 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
1061 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
1062 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
1064 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
1065 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
1066 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1067 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1068 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1069 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1070 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1071 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1072 PREFIX_EVEX_0F382B): Remove table entries.
1073 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
1074 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
1075 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1077 2020-07-06 Jan Beulich <jbeulich@suse.com>
1079 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1080 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1082 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1083 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1084 EVEX_LEN_0F3A01_P_2_W_1 table entries.
1085 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1088 2020-07-06 Jan Beulich <jbeulich@suse.com>
1090 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1091 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1092 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1093 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1094 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1095 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1096 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1097 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1098 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1101 2020-07-06 Jan Beulich <jbeulich@suse.com>
1103 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1104 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1105 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1107 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1109 * i386-dis-evex.h (evex_table): Reference VEX table entry for
1111 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1113 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1115 2020-07-06 Jan Beulich <jbeulich@suse.com>
1117 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1118 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1119 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1120 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1121 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1122 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1123 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1124 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1125 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1126 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1127 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1128 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1129 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1130 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1131 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1132 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1133 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1134 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1135 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1136 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1137 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1138 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1139 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1140 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1141 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1142 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1143 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1144 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1145 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1146 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1147 (prefix_table): Add EXxEVexR to FMA table entries.
1148 (OP_Rounding): Move abort() invocation.
1149 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1150 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1151 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1152 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1153 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1154 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1155 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1156 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1157 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1158 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1160 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1161 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1162 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1163 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1164 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1165 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1166 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1167 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1168 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1169 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1170 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1171 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1172 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1173 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1174 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1175 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1176 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1177 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1178 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1179 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1180 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1181 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1182 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1183 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1184 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1185 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1186 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1187 Delete table entries.
1188 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1189 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1190 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1193 2020-07-06 Jan Beulich <jbeulich@suse.com>
1195 * i386-dis.c (EXqScalarS): Delete.
1196 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1197 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1199 2020-07-06 Jan Beulich <jbeulich@suse.com>
1201 * i386-dis.c (safe-ctype.h): Include.
1202 (EXdScalar, EXqScalar): Delete.
1203 (d_scalar_mode, q_scalar_mode): Delete.
1204 (prefix_table, vex_len_table): Use EXxmm_md in place of
1205 EXdScalar and EXxmm_mq in place of EXqScalar.
1206 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1207 d_scalar_mode and q_scalar_mode.
1208 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1209 (vmovsd): Use EXxmm_mq.
1211 2020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1214 * arc-dis.c: Fix spelling mistake.
1215 * po/opcodes.pot: Regenerate.
1217 2020-07-06 Nick Clifton <nickc@redhat.com>
1219 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1220 * po/uk.po: Updated Ukranian translation.
1222 2020-07-04 Nick Clifton <nickc@redhat.com>
1224 * configure: Regenerate.
1225 * po/opcodes.pot: Regenerate.
1227 2020-07-04 Nick Clifton <nickc@redhat.com>
1229 Binutils 2.35 branch created.
1231 2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1233 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1234 * i386-opc.h (VexSwapSources): New.
1235 (i386_opcode_modifier): Add vexswapsources.
1236 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1237 with two source operands swapped.
1238 * i386-tbl.h: Regenerated.
1240 2020-06-30 Nelson Chu <nelson.chu@sifive.com>
1242 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1243 unprivileged CSR can also be initialized.
1245 2020-06-29 Alan Modra <amodra@gmail.com>
1247 * arm-dis.c: Use C style comments.
1248 * cr16-opc.c: Likewise.
1249 * ft32-dis.c: Likewise.
1250 * moxie-opc.c: Likewise.
1251 * tic54x-dis.c: Likewise.
1252 * s12z-opc.c: Remove useless comment.
1253 * xgate-dis.c: Likewise.
1255 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1257 * i386-opc.tbl: Add a blank line.
1259 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1261 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1262 (VecSIB128): Renamed to ...
1264 (VecSIB256): Renamed to ...
1266 (VecSIB512): Renamed to ...
1268 (VecSIB): Renamed to ...
1270 (i386_opcode_modifier): Replace vecsib with sib.
1271 * i386-opc.tbl (VecSIB128): New.
1272 (VecSIB256): Likewise.
1273 (VecSIB512): Likewise.
1274 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1275 and VecSIB512, respectively.
1277 2020-06-26 Jan Beulich <jbeulich@suse.com>
1279 * i386-dis.c: Adjust description of I macro.
1280 (x86_64_table): Drop use of I.
1281 (float_mem): Replace use of I.
1282 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1284 2020-06-26 Jan Beulich <jbeulich@suse.com>
1286 * i386-dis.c: (print_insn): Avoid straight assignment to
1287 priv.orig_sizeflag when processing -M sub-options.
1289 2020-06-25 Jan Beulich <jbeulich@suse.com>
1291 * i386-dis.c: Adjust description of J macro.
1292 (dis386, x86_64_table, mod_table): Replace J.
1293 (putop): Remove handling of J.
1295 2020-06-25 Jan Beulich <jbeulich@suse.com>
1297 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1299 2020-06-25 Jan Beulich <jbeulich@suse.com>
1301 * i386-dis.c: Adjust description of "LQ" macro.
1302 (dis386_twobyte): Use LQ for sysret.
1303 (putop): Adjust handling of LQ.
1305 2020-06-22 Nelson Chu <nelson.chu@sifive.com>
1307 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1308 * riscv-dis.c: Include elfxx-riscv.h.
1310 2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1312 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1314 2020-06-17 Lili Cui <lili.cui@intel.com>
1316 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1318 2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1321 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1322 * i386-opc.tbl: Likewise.
1323 * i386-tbl.h: Regenerated.
1325 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
1327 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1329 2020-06-11 Alex Coplan <alex.coplan@arm.com>
1331 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1332 (SR_CORE): Likewise.
1333 (SR_FEAT): Likewise.
1335 (SR_V8_1): Likewise.
1336 (SR_V8_2): Likewise.
1337 (SR_V8_3): Likewise.
1338 (SR_V8_4): Likewise.
1341 (SR_SSBS): Likewise.
1343 (SR_ID_PFR2): Likewise.
1344 (SR_PROFILE): Likewise.
1345 (SR_MEMTAG): Likewise.
1346 (SR_SCXTNUM): Likewise.
1347 (aarch64_sys_regs): Refactor to store feature information in the table.
1348 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1349 that now describe their own features.
1350 (aarch64_pstatefield_supported_p): Likewise.
1352 2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1354 * i386-dis.c (prefix_table): Fix a typo in comments.
1356 2020-06-09 Jan Beulich <jbeulich@suse.com>
1358 * i386-dis.c (rex_ignored): Delete.
1359 (ckprefix): Drop rex_ignored initialization.
1360 (get_valid_dis386): Drop setting of rex_ignored.
1361 (print_insn): Drop checking of rex_ignored. Don't record data
1362 size prefix as used with VEX-and-alike encodings.
1364 2020-06-09 Jan Beulich <jbeulich@suse.com>
1366 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1367 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1368 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1369 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1370 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1371 VEX_0F12, and VEX_0F16.
1372 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1373 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1374 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1375 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1376 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1377 MOD_VEX_0F16_PREFIX_2 entries.
1379 2020-06-09 Jan Beulich <jbeulich@suse.com>
1381 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1382 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1383 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1384 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1385 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1386 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1387 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1388 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1389 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1390 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1391 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1392 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1393 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1394 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1395 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1396 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1397 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1398 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1399 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1400 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1401 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1402 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1403 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1404 EVEX_W_0FC6_P_2): Delete.
1405 (print_insn): Add EVEX.W vs embedded prefix consistency check
1406 to prefix validation.
1407 * i386-dis-evex.h (evex_table): Don't further descend for
1408 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1409 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1411 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1412 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1413 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1414 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1415 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1416 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1417 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1418 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1419 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1420 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1421 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1422 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1423 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1424 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1425 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1426 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1427 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1428 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1429 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1430 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1431 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1432 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1433 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1434 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1435 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1436 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1437 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1439 2020-06-09 Jan Beulich <jbeulich@suse.com>
1441 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1442 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1443 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1445 (print_insn): Drop pointless check against bad_opcode. Split
1446 prefix validation into legacy and VEX-and-alike parts.
1447 (putop): Re-work 'X' macro handling.
1449 2020-06-09 Jan Beulich <jbeulich@suse.com>
1451 * i386-dis.c (MOD_0F51): Rename to ...
1452 (MOD_0F50): ... this.
1454 2020-06-08 Alex Coplan <alex.coplan@arm.com>
1456 * arm-dis.c (arm_opcodes): Add dfb.
1457 (thumb32_opcodes): Add dfb.
1459 2020-06-08 Jan Beulich <jbeulich@suse.com>
1461 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1463 2020-06-06 Alan Modra <amodra@gmail.com>
1465 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1467 2020-06-05 Alan Modra <amodra@gmail.com>
1469 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1470 size is large enough.
1472 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1474 * disassemble.c (disassemble_init_for_target): Set endian_code for
1476 * bpf-desc.c: Regenerate.
1477 * bpf-opc.c: Likewise.
1478 * bpf-dis.c: Likewise.
1480 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1482 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1483 (cgen_put_insn_value): Likewise.
1484 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1485 * cgen-dis.in (print_insn): Likewise.
1486 * cgen-ibld.in (insert_1): Likewise.
1487 (insert_1): Likewise.
1488 (insert_insn_normal): Likewise.
1489 (extract_1): Likewise.
1490 * bpf-dis.c: Regenerate.
1491 * bpf-ibld.c: Likewise.
1492 * bpf-ibld.c: Likewise.
1493 * cgen-dis.in: Likewise.
1494 * cgen-ibld.in: Likewise.
1495 * cgen-opc.c: Likewise.
1496 * epiphany-dis.c: Likewise.
1497 * epiphany-ibld.c: Likewise.
1498 * fr30-dis.c: Likewise.
1499 * fr30-ibld.c: Likewise.
1500 * frv-dis.c: Likewise.
1501 * frv-ibld.c: Likewise.
1502 * ip2k-dis.c: Likewise.
1503 * ip2k-ibld.c: Likewise.
1504 * iq2000-dis.c: Likewise.
1505 * iq2000-ibld.c: Likewise.
1506 * lm32-dis.c: Likewise.
1507 * lm32-ibld.c: Likewise.
1508 * m32c-dis.c: Likewise.
1509 * m32c-ibld.c: Likewise.
1510 * m32r-dis.c: Likewise.
1511 * m32r-ibld.c: Likewise.
1512 * mep-dis.c: Likewise.
1513 * mep-ibld.c: Likewise.
1514 * mt-dis.c: Likewise.
1515 * mt-ibld.c: Likewise.
1516 * or1k-dis.c: Likewise.
1517 * or1k-ibld.c: Likewise.
1518 * xc16x-dis.c: Likewise.
1519 * xc16x-ibld.c: Likewise.
1520 * xstormy16-dis.c: Likewise.
1521 * xstormy16-ibld.c: Likewise.
1523 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1525 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1526 (print_insn_): Handle instruction endian.
1527 * bpf-dis.c: Regenerate.
1528 * bpf-desc.c: Regenerate.
1529 * epiphany-dis.c: Likewise.
1530 * epiphany-desc.c: Likewise.
1531 * fr30-dis.c: Likewise.
1532 * fr30-desc.c: Likewise.
1533 * frv-dis.c: Likewise.
1534 * frv-desc.c: Likewise.
1535 * ip2k-dis.c: Likewise.
1536 * ip2k-desc.c: Likewise.
1537 * iq2000-dis.c: Likewise.
1538 * iq2000-desc.c: Likewise.
1539 * lm32-dis.c: Likewise.
1540 * lm32-desc.c: Likewise.
1541 * m32c-dis.c: Likewise.
1542 * m32c-desc.c: Likewise.
1543 * m32r-dis.c: Likewise.
1544 * m32r-desc.c: Likewise.
1545 * mep-dis.c: Likewise.
1546 * mep-desc.c: Likewise.
1547 * mt-dis.c: Likewise.
1548 * mt-desc.c: Likewise.
1549 * or1k-dis.c: Likewise.
1550 * or1k-desc.c: Likewise.
1551 * xc16x-dis.c: Likewise.
1552 * xc16x-desc.c: Likewise.
1553 * xstormy16-dis.c: Likewise.
1554 * xstormy16-desc.c: Likewise.
1556 2020-06-03 Nick Clifton <nickc@redhat.com>
1558 * po/sr.po: Updated Serbian translation.
1560 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
1562 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1563 (riscv_get_priv_spec_class): Likewise.
1565 2020-06-01 Alan Modra <amodra@gmail.com>
1567 * bpf-desc.c: Regenerate.
1569 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1570 David Faust <david.faust@oracle.com>
1572 * bpf-desc.c: Regenerate.
1573 * bpf-opc.h: Likewise.
1574 * bpf-opc.c: Likewise.
1575 * bpf-dis.c: Likewise.
1577 2020-05-28 Alan Modra <amodra@gmail.com>
1579 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1582 2020-05-28 Alan Modra <amodra@gmail.com>
1584 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1586 (print_insn_ns32k): Revert last change.
1588 2020-05-28 Nick Clifton <nickc@redhat.com>
1590 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1593 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1595 Fix extraction of signed constants in nios2 disassembler (again).
1597 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1598 extractions of signed fields.
1600 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1602 * s390-opc.txt: Relocate vector load/store instructions with
1603 additional alignment parameter and change architecture level
1604 constraint from z14 to z13.
1606 2020-05-21 Alan Modra <amodra@gmail.com>
1608 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1609 * sparc-dis.c: Likewise.
1610 * tic4x-dis.c: Likewise.
1611 * xtensa-dis.c: Likewise.
1612 * bpf-desc.c: Regenerate.
1613 * epiphany-desc.c: Regenerate.
1614 * fr30-desc.c: Regenerate.
1615 * frv-desc.c: Regenerate.
1616 * ip2k-desc.c: Regenerate.
1617 * iq2000-desc.c: Regenerate.
1618 * lm32-desc.c: Regenerate.
1619 * m32c-desc.c: Regenerate.
1620 * m32r-desc.c: Regenerate.
1621 * mep-asm.c: Regenerate.
1622 * mep-desc.c: Regenerate.
1623 * mt-desc.c: Regenerate.
1624 * or1k-desc.c: Regenerate.
1625 * xc16x-desc.c: Regenerate.
1626 * xstormy16-desc.c: Regenerate.
1628 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
1630 * riscv-opc.c (riscv_ext_version_table): The table used to store
1631 all information about the supported spec and the corresponding ISA
1632 versions. Currently, only Zicsr is supported to verify the
1633 correctness of Z sub extension settings. Others will be supported
1634 in the future patches.
1635 (struct isa_spec_t, isa_specs): List for all supported ISA spec
1636 classes and the corresponding strings.
1637 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
1638 spec class by giving a ISA spec string.
1639 * riscv-opc.c (struct priv_spec_t): New structure.
1640 (struct priv_spec_t priv_specs): List for all supported privilege spec
1641 classes and the corresponding strings.
1642 (riscv_get_priv_spec_class): New function. Get the corresponding
1643 privilege spec class by giving a spec string.
1644 (riscv_get_priv_spec_name): New function. Get the corresponding
1645 privilege spec string by giving a CSR version class.
1646 * riscv-dis.c: Updated since DECLARE_CSR is changed.
1647 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
1648 according to the chosen version. Build a hash table riscv_csr_hash to
1649 store the valid CSR for the chosen pirv verison. Dump the direct
1650 CSR address rather than it's name if it is invalid.
1651 (parse_riscv_dis_option_without_args): New function. Parse the options
1653 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
1654 parse the options without arguments first, and then handle the options
1655 with arguments. Add the new option -Mpriv-spec, which has argument.
1656 * riscv-dis.c (print_riscv_disassembler_options): Add description
1657 about the new OBJDUMP option.
1659 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
1661 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
1662 WC values on POWER10 sync, dcbf and wait instructions.
1663 (insert_pl, extract_pl): New functions.
1664 (L2OPT, LS, WC): Use insert_ls and extract_ls.
1665 (LS3): New , 3-bit L for sync.
1666 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
1667 (SC2, PL): New, 2-bit SC and PL for sync and wait.
1668 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
1669 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
1670 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
1671 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
1672 <wait>: Enable PL operand on POWER10.
1673 <dcbf>: Enable L3OPT operand on POWER10.
1674 <sync>: Enable SC2 operand on POWER10.
1676 2020-05-19 Stafford Horne <shorne@gmail.com>
1679 * or1k-asm.c: Regenerate.
1680 * or1k-desc.c: Regenerate.
1681 * or1k-desc.h: Regenerate.
1682 * or1k-dis.c: Regenerate.
1683 * or1k-ibld.c: Regenerate.
1684 * or1k-opc.c: Regenerate.
1685 * or1k-opc.h: Regenerate.
1686 * or1k-opinst.c: Regenerate.
1688 2020-05-11 Alan Modra <amodra@gmail.com>
1690 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
1693 2020-05-11 Alan Modra <amodra@gmail.com>
1695 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
1696 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
1698 2020-05-11 Alan Modra <amodra@gmail.com>
1700 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
1702 2020-05-11 Alan Modra <amodra@gmail.com>
1704 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
1705 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
1707 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1709 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
1712 2020-05-11 Alan Modra <amodra@gmail.com>
1714 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
1715 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
1716 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
1717 (prefix_opcodes): Add xxeval.
1719 2020-05-11 Alan Modra <amodra@gmail.com>
1721 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
1722 xxgenpcvwm, xxgenpcvdm.
1724 2020-05-11 Alan Modra <amodra@gmail.com>
1726 * ppc-opc.c (MP, VXVAM_MASK): Define.
1727 (VXVAPS_MASK): Use VXVA_MASK.
1728 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
1729 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
1730 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
1731 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
1733 2020-05-11 Alan Modra <amodra@gmail.com>
1734 Peter Bergner <bergner@linux.ibm.com>
1736 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
1738 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
1739 YMSK2, XA6a, XA6ap, XB6a entries.
1740 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
1741 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
1743 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
1744 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
1745 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
1746 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
1747 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
1748 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
1749 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
1750 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
1751 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
1752 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
1753 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
1754 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
1755 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
1756 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
1758 2020-05-11 Alan Modra <amodra@gmail.com>
1760 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
1761 (insert_xts, extract_xts): New functions.
1762 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
1763 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
1764 (VXRC_MASK, VXSH_MASK): Define.
1765 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
1766 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
1767 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
1768 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
1769 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
1770 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
1771 xxblendvh, xxblendvw, xxblendvd, xxpermx.
1773 2020-05-11 Alan Modra <amodra@gmail.com>
1775 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
1776 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
1777 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
1778 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
1779 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
1781 2020-05-11 Alan Modra <amodra@gmail.com>
1783 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
1784 (XTP, DQXP, DQXP_MASK): Define.
1785 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
1786 (prefix_opcodes): Add plxvp and pstxvp.
1788 2020-05-11 Alan Modra <amodra@gmail.com>
1790 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1791 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1792 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1794 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1796 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1798 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1800 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1802 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1804 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1806 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1808 2020-05-11 Alan Modra <amodra@gmail.com>
1810 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1812 2020-05-11 Alan Modra <amodra@gmail.com>
1814 * ppc-dis.c (ppc_opts): Add "power10" entry.
1815 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1816 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
1818 2020-05-11 Nick Clifton <nickc@redhat.com>
1820 * po/fr.po: Updated French translation.
1822 2020-04-30 Alex Coplan <alex.coplan@arm.com>
1824 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1825 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1826 (operand_general_constraint_met_p): validate
1827 AARCH64_OPND_UNDEFINED.
1828 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1830 * aarch64-asm-2.c: Regenerated.
1831 * aarch64-dis-2.c: Regenerated.
1832 * aarch64-opc-2.c: Regenerated.
1834 2020-04-29 Nick Clifton <nickc@redhat.com>
1837 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1840 2020-04-29 Nick Clifton <nickc@redhat.com>
1842 * po/sv.po: Updated Swedish translation.
1844 2020-04-29 Nick Clifton <nickc@redhat.com>
1847 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
1848 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
1849 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
1852 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
1855 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
1856 cmpi only on m68020up and cpu32.
1858 2020-04-20 Sudakshina Das <sudi.das@arm.com>
1860 * aarch64-asm.c (aarch64_ins_none): New.
1861 * aarch64-asm.h (ins_none): New declaration.
1862 * aarch64-dis.c (aarch64_ext_none): New.
1863 * aarch64-dis.h (ext_none): New declaration.
1864 * aarch64-opc.c (aarch64_print_operand): Update case for
1865 AARCH64_OPND_BARRIER_PSB.
1866 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
1867 (AARCH64_OPERANDS): Update inserter/extracter for
1868 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
1869 * aarch64-asm-2.c: Regenerated.
1870 * aarch64-dis-2.c: Regenerated.
1871 * aarch64-opc-2.c: Regenerated.
1873 2020-04-20 Sudakshina Das <sudi.das@arm.com>
1875 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
1876 (aarch64_feature_ras, RAS): Likewise.
1877 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
1878 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
1879 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
1880 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
1881 * aarch64-asm-2.c: Regenerated.
1882 * aarch64-dis-2.c: Regenerated.
1883 * aarch64-opc-2.c: Regenerated.
1885 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
1887 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
1888 (print_insn_neon): Support disassembly of conditional
1891 2020-02-16 David Faust <david.faust@oracle.com>
1893 * bpf-desc.c: Regenerate.
1894 * bpf-desc.h: Likewise.
1895 * bpf-opc.c: Regenerate.
1896 * bpf-opc.h: Likewise.
1898 2020-04-07 Lili Cui <lili.cui@intel.com>
1900 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
1901 (prefix_table): New instructions (see prefixes above).
1902 (rm_table): Likewise
1903 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
1904 CPU_ANY_TSXLDTRK_FLAGS.
1905 (cpu_flags): Add CpuTSXLDTRK.
1906 * i386-opc.h (enum): Add CpuTSXLDTRK.
1907 (i386_cpu_flags): Add cputsxldtrk.
1908 * i386-opc.tbl: Add XSUSPLDTRK insns.
1909 * i386-init.h: Regenerate.
1910 * i386-tbl.h: Likewise.
1912 2020-04-02 Lili Cui <lili.cui@intel.com>
1914 * i386-dis.c (prefix_table): New instructions serialize.
1915 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
1916 CPU_ANY_SERIALIZE_FLAGS.
1917 (cpu_flags): Add CpuSERIALIZE.
1918 * i386-opc.h (enum): Add CpuSERIALIZE.
1919 (i386_cpu_flags): Add cpuserialize.
1920 * i386-opc.tbl: Add SERIALIZE insns.
1921 * i386-init.h: Regenerate.
1922 * i386-tbl.h: Likewise.
1924 2020-03-26 Alan Modra <amodra@gmail.com>
1926 * disassemble.h (opcodes_assert): Declare.
1927 (OPCODES_ASSERT): Define.
1928 * disassemble.c: Don't include assert.h. Include opintl.h.
1929 (opcodes_assert): New function.
1930 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
1931 (bfd_h8_disassemble): Reduce size of data array. Correctly
1932 calculate maxlen. Omit insn decoding when insn length exceeds
1933 maxlen. Exit from nibble loop when looking for E, before
1934 accessing next data byte. Move processing of E outside loop.
1935 Replace tests of maxlen in loop with assertions.
1937 2020-03-26 Alan Modra <amodra@gmail.com>
1939 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
1941 2020-03-25 Alan Modra <amodra@gmail.com>
1943 * z80-dis.c (suffix): Init mybuf.
1945 2020-03-22 Alan Modra <amodra@gmail.com>
1947 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
1948 successflly read from section.
1950 2020-03-22 Alan Modra <amodra@gmail.com>
1952 * arc-dis.c (find_format): Use ISO C string concatenation rather
1953 than line continuation within a string. Don't access needs_limm
1954 before testing opcode != NULL.
1956 2020-03-22 Alan Modra <amodra@gmail.com>
1958 * ns32k-dis.c (print_insn_arg): Update comment.
1959 (print_insn_ns32k): Reduce size of index_offset array, and
1960 initialize, passing -1 to print_insn_arg for args that are not
1961 an index. Don't exit arg loop early. Abort on bad arg number.
1963 2020-03-22 Alan Modra <amodra@gmail.com>
1965 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
1966 * s12z-opc.c: Formatting.
1967 (operands_f): Return an int.
1968 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
1969 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
1970 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
1971 (exg_sex_discrim): Likewise.
1972 (create_immediate_operand, create_bitfield_operand),
1973 (create_register_operand_with_size, create_register_all_operand),
1974 (create_register_all16_operand, create_simple_memory_operand),
1975 (create_memory_operand, create_memory_auto_operand): Don't
1976 segfault on malloc failure.
1977 (z_ext24_decode): Return an int status, negative on fail, zero
1979 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
1980 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
1981 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
1982 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
1983 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1984 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1985 (loop_primitive_decode, shift_decode, psh_pul_decode),
1986 (bit_field_decode): Similarly.
1987 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
1988 to return value, update callers.
1989 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1990 Don't segfault on NULL operand.
1991 (decode_operation): Return OP_INVALID on first fail.
1992 (decode_s12z): Check all reads, returning -1 on fail.
1994 2020-03-20 Alan Modra <amodra@gmail.com>
1996 * metag-dis.c (print_insn_metag): Don't ignore status from
1999 2020-03-20 Alan Modra <amodra@gmail.com>
2001 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
2002 Initialize parts of buffer not written when handling a possible
2003 2-byte insn at end of section. Don't attempt decoding of such
2004 an insn by the 4-byte machinery.
2006 2020-03-20 Alan Modra <amodra@gmail.com>
2008 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
2009 partially filled buffer. Prevent lookup of 4-byte insns when
2010 only VLE 2-byte insns are possible due to section size. Print
2011 ".word" rather than ".long" for 2-byte leftovers.
2013 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
2016 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
2018 2020-03-13 Jan Beulich <jbeulich@suse.com>
2020 * i386-dis.c (X86_64_0D): Rename to ...
2021 (X86_64_0E): ... this.
2023 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
2025 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
2026 * Makefile.in: Regenerated.
2028 2020-03-09 Jan Beulich <jbeulich@suse.com>
2030 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
2032 * i386-tbl.h: Re-generate.
2034 2020-03-09 Jan Beulich <jbeulich@suse.com>
2036 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
2037 vprot*, vpsha*, and vpshl*.
2038 * i386-tbl.h: Re-generate.
2040 2020-03-09 Jan Beulich <jbeulich@suse.com>
2042 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
2043 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
2044 * i386-tbl.h: Re-generate.
2046 2020-03-09 Jan Beulich <jbeulich@suse.com>
2048 * i386-gen.c (set_bitfield): Ignore zero-length field names.
2049 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
2050 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
2051 * i386-tbl.h: Re-generate.
2053 2020-03-09 Jan Beulich <jbeulich@suse.com>
2055 * i386-gen.c (struct template_arg, struct template_instance,
2056 struct template_param, struct template, templates,
2057 parse_template, expand_templates): New.
2058 (process_i386_opcodes): Various local variables moved to
2059 expand_templates. Call parse_template and expand_templates.
2060 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
2061 * i386-tbl.h: Re-generate.
2063 2020-03-06 Jan Beulich <jbeulich@suse.com>
2065 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
2066 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
2067 register and memory source templates. Replace VexW= by VexW*
2069 * i386-tbl.h: Re-generate.
2071 2020-03-06 Jan Beulich <jbeulich@suse.com>
2073 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
2074 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
2075 * i386-tbl.h: Re-generate.
2077 2020-03-06 Jan Beulich <jbeulich@suse.com>
2079 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2080 * i386-tbl.h: Re-generate.
2082 2020-03-06 Jan Beulich <jbeulich@suse.com>
2084 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2085 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2086 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2087 VexW0 on SSE2AVX variants.
2088 (vmovq): Drop NoRex64 from XMM/XMM variants.
2089 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2090 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2091 applicable use VexW0.
2092 * i386-tbl.h: Re-generate.
2094 2020-03-06 Jan Beulich <jbeulich@suse.com>
2096 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2097 * i386-opc.h (Rex64): Delete.
2098 (struct i386_opcode_modifier): Remove rex64 field.
2099 * i386-opc.tbl (crc32): Drop Rex64.
2100 Replace Rex64 with Size64 everywhere else.
2101 * i386-tbl.h: Re-generate.
2103 2020-03-06 Jan Beulich <jbeulich@suse.com>
2105 * i386-dis.c (OP_E_memory): Exclude recording of used address
2106 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2107 addressed memory operands for MPX insns.
2109 2020-03-06 Jan Beulich <jbeulich@suse.com>
2111 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2112 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2113 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2114 (ptwrite): Split into non-64-bit and 64-bit forms.
2115 * i386-tbl.h: Re-generate.
2117 2020-03-06 Jan Beulich <jbeulich@suse.com>
2119 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2121 * i386-tbl.h: Re-generate.
2123 2020-03-04 Jan Beulich <jbeulich@suse.com>
2125 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2126 (prefix_table): Move vmmcall here. Add vmgexit.
2127 (rm_table): Replace vmmcall entry by prefix_table[] escape.
2128 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2129 (cpu_flags): Add CpuSEV_ES entry.
2130 * i386-opc.h (CpuSEV_ES): New.
2131 (union i386_cpu_flags): Add cpusev_es field.
2132 * i386-opc.tbl (vmgexit): New.
2133 * i386-init.h, i386-tbl.h: Re-generate.
2135 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2137 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2139 * i386-opc.h (IGNORESIZE): New.
2140 (DEFAULTSIZE): Likewise.
2141 (IgnoreSize): Removed.
2142 (DefaultSize): Likewise.
2143 (MnemonicSize): New.
2144 (i386_opcode_modifier): Replace ignoresize/defaultsize with
2146 * i386-opc.tbl (IgnoreSize): New.
2147 (DefaultSize): Likewise.
2148 * i386-tbl.h: Regenerated.
2150 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2153 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2156 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2159 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2160 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2161 * i386-tbl.h: Regenerated.
2163 2020-02-26 Alan Modra <amodra@gmail.com>
2165 * aarch64-asm.c: Indent labels correctly.
2166 * aarch64-dis.c: Likewise.
2167 * aarch64-gen.c: Likewise.
2168 * aarch64-opc.c: Likewise.
2169 * alpha-dis.c: Likewise.
2170 * i386-dis.c: Likewise.
2171 * nds32-asm.c: Likewise.
2172 * nfp-dis.c: Likewise.
2173 * visium-dis.c: Likewise.
2175 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
2177 * arc-regs.h (int_vector_base): Make it available for all ARC
2180 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
2182 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2185 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
2187 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2188 c.mv/c.li if rs1 is zero.
2190 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
2192 * i386-gen.c (cpu_flag_init): Replace CpuABM with
2193 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
2195 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
2196 * i386-opc.h (CpuABM): Removed.
2198 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
2199 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2200 popcnt. Remove CpuABM from lzcnt.
2201 * i386-init.h: Regenerated.
2202 * i386-tbl.h: Likewise.
2204 2020-02-17 Jan Beulich <jbeulich@suse.com>
2206 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2207 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2208 VexW1 instead of open-coding them.
2209 * i386-tbl.h: Re-generate.
2211 2020-02-17 Jan Beulich <jbeulich@suse.com>
2213 * i386-opc.tbl (AddrPrefixOpReg): Define.
2214 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2215 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2216 templates. Drop NoRex64.
2217 * i386-tbl.h: Re-generate.
2219 2020-02-17 Jan Beulich <jbeulich@suse.com>
2222 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2223 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2224 into Intel syntax instance (with Unpsecified) and AT&T one
2226 (vcvtneps2bf16): Likewise, along with folding the two so far
2228 * i386-tbl.h: Re-generate.
2230 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2232 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2233 CPU_ANY_SSE4A_FLAGS.
2235 2020-02-17 Alan Modra <amodra@gmail.com>
2237 * i386-gen.c (cpu_flag_init): Correct last change.
2239 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2241 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2244 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2246 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2249 2020-02-14 Jan Beulich <jbeulich@suse.com>
2252 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2253 destination for Cpu64-only variant.
2254 (movzx): Fold patterns.
2255 * i386-tbl.h: Re-generate.
2257 2020-02-13 Jan Beulich <jbeulich@suse.com>
2259 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2260 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2261 CPU_ANY_SSE4_FLAGS entry.
2262 * i386-init.h: Re-generate.
2264 2020-02-12 Jan Beulich <jbeulich@suse.com>
2266 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2267 with Unspecified, making the present one AT&T syntax only.
2268 * i386-tbl.h: Re-generate.
2270 2020-02-12 Jan Beulich <jbeulich@suse.com>
2272 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2273 * i386-tbl.h: Re-generate.
2275 2020-02-12 Jan Beulich <jbeulich@suse.com>
2278 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2279 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2280 Amd64 and Intel64 templates.
2281 (call, jmp): Likewise for far indirect variants. Dro
2283 * i386-tbl.h: Re-generate.
2285 2020-02-11 Jan Beulich <jbeulich@suse.com>
2287 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2288 * i386-opc.h (ShortForm): Delete.
2289 (struct i386_opcode_modifier): Remove shortform field.
2290 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2291 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2292 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2293 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2295 * i386-tbl.h: Re-generate.
2297 2020-02-11 Jan Beulich <jbeulich@suse.com>
2299 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2300 fucompi): Drop ShortForm from operand-less templates.
2301 * i386-tbl.h: Re-generate.
2303 2020-02-11 Alan Modra <amodra@gmail.com>
2305 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2306 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2307 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2308 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2309 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2311 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2313 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2314 (cde_opcodes): Add VCX* instructions.
2316 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2317 Matthew Malcomson <matthew.malcomson@arm.com>
2319 * arm-dis.c (struct cdeopcode32): New.
2320 (CDE_OPCODE): New macro.
2321 (cde_opcodes): New disassembly table.
2322 (regnames): New option to table.
2323 (cde_coprocs): New global variable.
2324 (print_insn_cde): New
2325 (print_insn_thumb32): Use print_insn_cde.
2326 (parse_arm_disassembler_options): Parse coprocN args.
2328 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2331 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2333 * i386-opc.h (AMD64): Removed.
2334 (Intel64): Likewose.
2336 (INTEL64): Likewise.
2337 (INTEL64ONLY): Likewise.
2338 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2339 * i386-opc.tbl (Amd64): New.
2340 (Intel64): Likewise.
2341 (Intel64Only): Likewise.
2342 Replace AMD64 with Amd64. Update sysenter/sysenter with
2343 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2344 * i386-tbl.h: Regenerated.
2346 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2349 * z80-dis.c: Add support for GBZ80 opcodes.
2351 2020-02-04 Alan Modra <amodra@gmail.com>
2353 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2355 2020-02-03 Alan Modra <amodra@gmail.com>
2357 * m32c-ibld.c: Regenerate.
2359 2020-02-01 Alan Modra <amodra@gmail.com>
2361 * frv-ibld.c: Regenerate.
2363 2020-01-31 Jan Beulich <jbeulich@suse.com>
2365 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2366 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2367 (OP_E_memory): Replace xmm_mdq_mode case label by
2368 vex_scalar_w_dq_mode one.
2369 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2371 2020-01-31 Jan Beulich <jbeulich@suse.com>
2373 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2374 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2375 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2376 (intel_operand_size): Drop vex_w_dq_mode case label.
2378 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2380 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2381 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2383 2020-01-30 Alan Modra <amodra@gmail.com>
2385 * m32c-ibld.c: Regenerate.
2387 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2389 * bpf-opc.c: Regenerate.
2391 2020-01-30 Jan Beulich <jbeulich@suse.com>
2393 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2394 (dis386): Use them to replace C2/C3 table entries.
2395 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2396 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2397 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2398 * i386-tbl.h: Re-generate.
2400 2020-01-30 Jan Beulich <jbeulich@suse.com>
2402 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2404 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2406 * i386-tbl.h: Re-generate.
2408 2020-01-30 Alan Modra <amodra@gmail.com>
2410 * tic4x-dis.c (tic4x_dp): Make unsigned.
2412 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2413 Jan Beulich <jbeulich@suse.com>
2416 * i386-dis.c (MOVSXD_Fixup): New function.
2417 (movsxd_mode): New enum.
2418 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2419 (intel_operand_size): Handle movsxd_mode.
2420 (OP_E_register): Likewise.
2422 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2423 register on movsxd. Add movsxd with 16-bit destination register
2424 for AMD64 and Intel64 ISAs.
2425 * i386-tbl.h: Regenerated.
2427 2020-01-27 Tamar Christina <tamar.christina@arm.com>
2430 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2431 * aarch64-asm-2.c: Regenerate
2432 * aarch64-dis-2.c: Likewise.
2433 * aarch64-opc-2.c: Likewise.
2435 2020-01-21 Jan Beulich <jbeulich@suse.com>
2437 * i386-opc.tbl (sysret): Drop DefaultSize.
2438 * i386-tbl.h: Re-generate.
2440 2020-01-21 Jan Beulich <jbeulich@suse.com>
2442 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2444 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2445 * i386-tbl.h: Re-generate.
2447 2020-01-20 Nick Clifton <nickc@redhat.com>
2449 * po/de.po: Updated German translation.
2450 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2451 * po/uk.po: Updated Ukranian translation.
2453 2020-01-20 Alan Modra <amodra@gmail.com>
2455 * hppa-dis.c (fput_const): Remove useless cast.
2457 2020-01-20 Alan Modra <amodra@gmail.com>
2459 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2461 2020-01-18 Nick Clifton <nickc@redhat.com>
2463 * configure: Regenerate.
2464 * po/opcodes.pot: Regenerate.
2466 2020-01-18 Nick Clifton <nickc@redhat.com>
2468 Binutils 2.34 branch created.
2470 2020-01-17 Christian Biesinger <cbiesinger@google.com>
2472 * opintl.h: Fix spelling error (seperate).
2474 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2476 * i386-opc.tbl: Add {vex} pseudo prefix.
2477 * i386-tbl.h: Regenerated.
2479 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2482 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2483 (neon_opcodes): Likewise.
2484 (select_arm_features): Make sure we enable MVE bits when selecting
2485 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2488 2020-01-16 Jan Beulich <jbeulich@suse.com>
2490 * i386-opc.tbl: Drop stale comment from XOP section.
2492 2020-01-16 Jan Beulich <jbeulich@suse.com>
2494 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2495 (extractps): Add VexWIG to SSE2AVX forms.
2496 * i386-tbl.h: Re-generate.
2498 2020-01-16 Jan Beulich <jbeulich@suse.com>
2500 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2501 Size64 from and use VexW1 on SSE2AVX forms.
2502 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2503 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2504 * i386-tbl.h: Re-generate.
2506 2020-01-15 Alan Modra <amodra@gmail.com>
2508 * tic4x-dis.c (tic4x_version): Make unsigned long.
2509 (optab, optab_special, registernames): New file scope vars.
2510 (tic4x_print_register): Set up registernames rather than
2511 malloc'd registertable.
2512 (tic4x_disassemble): Delete optable and optable_special. Use
2513 optab and optab_special instead. Throw away old optab,
2514 optab_special and registernames when info->mach changes.
2516 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2519 * z80-dis.c (suffix): Use .db instruction to generate double
2522 2020-01-14 Alan Modra <amodra@gmail.com>
2524 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2525 values to unsigned before shifting.
2527 2020-01-13 Thomas Troeger <tstroege@gmx.de>
2529 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2531 (print_insn_thumb16, print_insn_thumb32): Likewise.
2532 (print_insn): Initialize the insn info.
2533 * i386-dis.c (print_insn): Initialize the insn info fields, and
2536 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2538 * arc-opc.c (C_NE): Make it required.
2540 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2542 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2543 reserved register name.
2545 2020-01-13 Alan Modra <amodra@gmail.com>
2547 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2548 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2550 2020-01-13 Alan Modra <amodra@gmail.com>
2552 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2553 result of wasm_read_leb128 in a uint64_t and check that bits
2554 are not lost when copying to other locals. Use uint32_t for
2555 most locals. Use PRId64 when printing int64_t.
2557 2020-01-13 Alan Modra <amodra@gmail.com>
2559 * score-dis.c: Formatting.
2560 * score7-dis.c: Formatting.
2562 2020-01-13 Alan Modra <amodra@gmail.com>
2564 * score-dis.c (print_insn_score48): Use unsigned variables for
2565 unsigned values. Don't left shift negative values.
2566 (print_insn_score32): Likewise.
2567 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2569 2020-01-13 Alan Modra <amodra@gmail.com>
2571 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2573 2020-01-13 Alan Modra <amodra@gmail.com>
2575 * fr30-ibld.c: Regenerate.
2577 2020-01-13 Alan Modra <amodra@gmail.com>
2579 * xgate-dis.c (print_insn): Don't left shift signed value.
2580 (ripBits): Formatting, use 1u.
2582 2020-01-10 Alan Modra <amodra@gmail.com>
2584 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2585 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2587 2020-01-10 Alan Modra <amodra@gmail.com>
2589 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2590 and XRREG value earlier to avoid a shift with negative exponent.
2591 * m10200-dis.c (disassemble): Similarly.
2593 2020-01-09 Nick Clifton <nickc@redhat.com>
2596 * z80-dis.c (ld_ii_ii): Use correct cast.
2598 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2601 * z80-dis.c (ld_ii_ii): Use character constant when checking
2604 2020-01-09 Jan Beulich <jbeulich@suse.com>
2606 * i386-dis.c (SEP_Fixup): New.
2608 (dis386_twobyte): Use it for sysenter/sysexit.
2609 (enum x86_64_isa): Change amd64 enumerator to value 1.
2610 (OP_J): Compare isa64 against intel64 instead of amd64.
2611 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2613 * i386-tbl.h: Re-generate.
2615 2020-01-08 Alan Modra <amodra@gmail.com>
2617 * z8k-dis.c: Include libiberty.h
2618 (instr_data_s): Make max_fetched unsigned.
2619 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2620 Don't exceed byte_info bounds.
2621 (output_instr): Make num_bytes unsigned.
2622 (unpack_instr): Likewise for nibl_count and loop.
2623 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2625 * z8k-opc.h: Regenerate.
2627 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
2629 * arc-tbl.h (llock): Use 'LLOCK' as class.
2631 (scond): Use 'SCOND' as class.
2633 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
2636 2020-01-06 Alan Modra <amodra@gmail.com>
2638 * m32c-ibld.c: Regenerate.
2640 2020-01-06 Alan Modra <amodra@gmail.com>
2643 * z80-dis.c (suffix): Don't use a local struct buffer copy.
2644 Peek at next byte to prevent recursion on repeated prefix bytes.
2645 Ensure uninitialised "mybuf" is not accessed.
2646 (print_insn_z80): Don't zero n_fetch and n_used here,..
2647 (print_insn_z80_buf): ..do it here instead.
2649 2020-01-04 Alan Modra <amodra@gmail.com>
2651 * m32r-ibld.c: Regenerate.
2653 2020-01-04 Alan Modra <amodra@gmail.com>
2655 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2657 2020-01-04 Alan Modra <amodra@gmail.com>
2659 * crx-dis.c (match_opcode): Avoid shift left of signed value.
2661 2020-01-04 Alan Modra <amodra@gmail.com>
2663 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2665 2020-01-03 Jan Beulich <jbeulich@suse.com>
2667 * aarch64-tbl.h (aarch64_opcode_table): Use
2668 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2670 2020-01-03 Jan Beulich <jbeulich@suse.com>
2672 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
2673 forms of SUDOT and USDOT.
2675 2020-01-03 Jan Beulich <jbeulich@suse.com>
2677 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
2679 * opcodes/aarch64-dis-2.c: Re-generate.
2681 2020-01-03 Jan Beulich <jbeulich@suse.com>
2683 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
2685 * opcodes/aarch64-dis-2.c: Re-generate.
2687 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
2689 * z80-dis.c: Add support for eZ80 and Z80 instructions.
2691 2020-01-01 Alan Modra <amodra@gmail.com>
2693 Update year range in copyright notice of all files.
2695 For older changes see ChangeLog-2019
2697 Copyright (C) 2020 Free Software Foundation, Inc.
2699 Copying and distribution of this file, with or without modification,
2700 are permitted in any medium without royalty provided the copyright
2701 notice and this notice are preserved.
2707 version-control: never
projects / thirdparty / binutils-gdb.git / blob