opcodes/ChangeLog

   1 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
   2             Michael Collison <michael.collison@arm.com>
   3
   4         * arm-dis.c (enum mve_instructions): Add new instructions.
   5         (enum mve_undefined): Add new reasons.
   6         (is_mve_encoding_conflict): Handle new instructions.
   7         (is_mve_undefined): Likewise.
   8         (is_mve_unpredictable): Likewise.
   9         (print_mve_undefined): Likewise.
  10         (print_mve_size): Likewise.
  11         (print_insn_mve): Likewise.
  12
  13 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  14             Michael Collison <michael.collison@arm.com>
  15
  16         * arm-dis.c (enum mve_instructions): Add new instructions.
  17         (is_mve_encoding_conflict): Handle new instructions.
  18         (is_mve_undefined): Likewise.
  19         (is_mve_unpredictable): Likewise.
  20         (print_mve_size): Likewise.
  21         (print_insn_mve): Likewise.
  22
  23 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  24             Michael Collison <michael.collison@arm.com>
  25
  26         * arm-dis.c (enum mve_instructions): Add new instructions.
  27         (enum mve_unpredictable): Add new reasons.
  28         (enum mve_undefined): Likewise.
  29         (is_mve_okay_in_it): Handle new isntructions.
  30         (is_mve_encoding_conflict): Likewise.
  31         (is_mve_undefined): Likewise.
  32         (is_mve_unpredictable): Likewise.
  33         (print_mve_vmov_index): Likewise.
  34         (print_simd_imm8): Likewise.
  35         (print_mve_undefined): Likewise.
  36         (print_mve_unpredictable): Likewise.
  37         (print_mve_size): Likewise.
  38         (print_insn_mve): Likewise.
  39
  40 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  41             Michael Collison <michael.collison@arm.com>
  42
  43         * arm-dis.c (enum mve_instructions): Add new instructions.
  44         (enum mve_unpredictable): Add new reasons.
  45         (enum mve_undefined): Likewise.
  46         (is_mve_encoding_conflict): Handle new instructions.
  47         (is_mve_undefined): Likewise.
  48         (is_mve_unpredictable): Likewise.
  49         (print_mve_undefined): Likewise.
  50         (print_mve_unpredictable): Likewise.
  51         (print_mve_rounding_mode): Likewise.
  52         (print_mve_vcvt_size): Likewise.
  53         (print_mve_size): Likewise.
  54         (print_insn_mve): Likewise.
  55
  56 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  57             Michael Collison <michael.collison@arm.com>
  58
  59         * arm-dis.c (enum mve_instructions): Add new instructions.
  60         (enum mve_unpredictable): Add new reasons.
  61         (enum mve_undefined): Likewise.
  62         (is_mve_undefined): Handle new instructions.
  63         (is_mve_unpredictable): Likewise.
  64         (print_mve_undefined): Likewise.
  65         (print_mve_unpredictable): Likewise.
  66         (print_mve_size): Likewise.
  67         (print_insn_mve): Likewise.
  68
  69 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  70             Michael Collison <michael.collison@arm.com>
  71
  72         * arm-dis.c (enum mve_instructions): Add new instructions.
  73         (enum mve_undefined): Add new reasons.
  74         (insns): Add new instructions.
  75         (is_mve_encoding_conflict):
  76         (print_mve_vld_str_addr): New print function.
  77         (is_mve_undefined): Handle new instructions.
  78         (is_mve_unpredictable): Likewise.
  79         (print_mve_undefined): Likewise.
  80         (print_mve_size): Likewise.
  81         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
  82         (print_insn_mve):  Handle new operands.
  83
  84 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  85             Michael Collison <michael.collison@arm.com>
  86
  87         * arm-dis.c (enum mve_instructions): Add new instructions.
  88         (enum mve_unpredictable): Add new reasons.
  89         (is_mve_encoding_conflict): Handle new instructions.
  90         (is_mve_unpredictable): Likewise.
  91         (mve_opcodes): Add new instructions.
  92         (print_mve_unpredictable): Handle new reasons.
  93         (print_mve_register_blocks): New print function.
  94         (print_mve_size): Handle new instructions.
  95         (print_insn_mve): Likewise.
  96
  97 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  98             Michael Collison <michael.collison@arm.com>
  99
 100         * arm-dis.c (enum mve_instructions): Add new instructions.
 101         (enum mve_unpredictable): Add new reasons.
 102         (enum mve_undefined): Likewise.
 103         (is_mve_encoding_conflict): Handle new instructions.
 104         (is_mve_undefined): Likewise.
 105         (is_mve_unpredictable): Likewise.
 106         (coprocessor_opcodes): Move NEON VDUP from here...
 107         (neon_opcodes): ... to here.
 108         (mve_opcodes): Add new instructions.
 109         (print_mve_undefined):  Handle new reasons.
 110         (print_mve_unpredictable): Likewise.
 111         (print_mve_size): Handle new instructions.
 112         (print_insn_neon): Handle vdup.
 113         (print_insn_mve): Handle new operands.
 114
 115 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 116             Michael Collison <michael.collison@arm.com>
 117
 118         * arm-dis.c (enum mve_instructions): Add new instructions.
 119         (enum mve_unpredictable): Add new values.
 120         (mve_opcodes): Add new instructions.
 121         (vec_condnames): New array with vector conditions.
 122         (mve_predicatenames): New array with predicate suffixes.
 123         (mve_vec_sizename): New array with vector sizes.
 124         (enum vpt_pred_state): New enum with vector predication states.
 125         (struct vpt_block): New struct type for vpt blocks.
 126         (vpt_block_state): Global struct to keep track of state.
 127         (mve_extract_pred_mask): New helper function.
 128         (num_instructions_vpt_block): Likewise.
 129         (mark_outside_vpt_block): Likewise.
 130         (mark_inside_vpt_block): Likewise.
 131         (invert_next_predicate_state): Likewise.
 132         (update_next_predicate_state): Likewise.
 133         (update_vpt_block_state): Likewise.
 134         (is_vpt_instruction): Likewise.
 135         (is_mve_encoding_conflict): Add entries for new instructions.
 136         (is_mve_unpredictable): Likewise.
 137         (print_mve_unpredictable): Handle new cases.
 138         (print_instruction_predicate): Likewise.
 139         (print_mve_size): New function.
 140         (print_vec_condition): New function.
 141         (print_insn_mve): Handle vpt blocks and new print operands.
 142
 143 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 144
 145         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 146         8, 14 and 15 for Armv8.1-M Mainline.
 147
 148 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 149             Michael Collison <michael.collison@arm.com>
 150
 151         * arm-dis.c (enum mve_instructions): New enum.
 152         (enum mve_unpredictable): Likewise.
 153         (enum mve_undefined): Likewise.
 154         (struct mopcode32): New struct.
 155         (is_mve_okay_in_it): New function.
 156         (is_mve_architecture): Likewise.
 157         (arm_decode_field): Likewise.
 158         (arm_decode_field_multiple): Likewise.
 159         (is_mve_encoding_conflict): Likewise.
 160         (is_mve_undefined): Likewise.
 161         (is_mve_unpredictable): Likewise.
 162         (print_mve_undefined): Likewise.
 163         (print_mve_unpredictable): Likewise.
 164         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 165         (print_insn_mve): New function.
 166         (print_insn_thumb32): Handle MVE architecture.
 167         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 168
 169 2019-05-10  Nick Clifton  <nickc@redhat.com>
 170
 171         PR 24538
 172         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 173         end of the table prematurely.
 174
 175 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 176
 177         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 178         macros for R6.
 179
 180 2019-05-11  Alan Modra  <amodra@gmail.com>
 181
 182         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 183         when -Mraw is in effect.
 184
 185 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 186
 187         * aarch64-dis-2.c: Regenerate.
 188         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 189         (OP_SVE_BBB): New variant set.
 190         (OP_SVE_DDDD): New variant set.
 191         (OP_SVE_HHH): New variant set.
 192         (OP_SVE_HHHU): New variant set.
 193         (OP_SVE_SSS): New variant set.
 194         (OP_SVE_SSSU): New variant set.
 195         (OP_SVE_SHH): New variant set.
 196         (OP_SVE_SBBU): New variant set.
 197         (OP_SVE_DSS): New variant set.
 198         (OP_SVE_DHHU): New variant set.
 199         (OP_SVE_VMV_HSD_BHS): New variant set.
 200         (OP_SVE_VVU_HSD_BHS): New variant set.
 201         (OP_SVE_VVVU_SD_BH): New variant set.
 202         (OP_SVE_VVVU_BHSD): New variant set.
 203         (OP_SVE_VVV_QHD_DBS): New variant set.
 204         (OP_SVE_VVV_HSD_BHS): New variant set.
 205         (OP_SVE_VVV_HSD_BHS2): New variant set.
 206         (OP_SVE_VVV_BHS_HSD): New variant set.
 207         (OP_SVE_VV_BHS_HSD): New variant set.
 208         (OP_SVE_VVV_SD): New variant set.
 209         (OP_SVE_VVU_BHS_HSD): New variant set.
 210         (OP_SVE_VZVV_SD): New variant set.
 211         (OP_SVE_VZVV_BH): New variant set.
 212         (OP_SVE_VZV_SD): New variant set.
 213         (aarch64_opcode_table): Add sve2 instructions.
 214
 215 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 216
 217         * aarch64-asm-2.c: Regenerated.
 218         * aarch64-dis-2.c: Regenerated.
 219         * aarch64-opc-2.c: Regenerated.
 220         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 221         for SVE_SHLIMM_UNPRED_22.
 222         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 223         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 224         operand.
 225
 226 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 227
 228         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 229         sve_size_tsz_bhs iclass encode.
 230         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 231         sve_size_tsz_bhs iclass decode.
 232
 233 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 234
 235         * aarch64-asm-2.c: Regenerated.
 236         * aarch64-dis-2.c: Regenerated.
 237         * aarch64-opc-2.c: Regenerated.
 238         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 239         for SVE_Zm4_11_INDEX.
 240         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 241         (fields): Handle SVE_i2h field.
 242         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 243         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 244
 245 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 246
 247         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 248         sve_shift_tsz_bhsd iclass encode.
 249         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 250         sve_shift_tsz_bhsd iclass decode.
 251
 252 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 253
 254         * aarch64-asm-2.c: Regenerated.
 255         * aarch64-dis-2.c: Regenerated.
 256         * aarch64-opc-2.c: Regenerated.
 257         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 258         (aarch64_encode_variant_using_iclass): Handle
 259         sve_shift_tsz_hsd iclass encode.
 260         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 261         sve_shift_tsz_hsd iclass decode.
 262         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 263         for SVE_SHRIMM_UNPRED_22.
 264         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 265         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 266         operand.
 267
 268 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 269
 270         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 271         sve_size_013 iclass encode.
 272         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 273         sve_size_013 iclass decode.
 274
 275 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 276
 277         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 278         sve_size_bh iclass encode.
 279         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 280         sve_size_bh iclass decode.
 281
 282 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 283
 284         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 285         sve_size_sd2 iclass encode.
 286         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 287         sve_size_sd2 iclass decode.
 288         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 289         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 290
 291 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 292
 293         * aarch64-asm-2.c: Regenerated.
 294         * aarch64-dis-2.c: Regenerated.
 295         * aarch64-opc-2.c: Regenerated.
 296         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 297         for SVE_ADDR_ZX.
 298         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 299         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 300
 301 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 302
 303         * aarch64-asm-2.c: Regenerated.
 304         * aarch64-dis-2.c: Regenerated.
 305         * aarch64-opc-2.c: Regenerated.
 306         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 307         for SVE_Zm3_11_INDEX.
 308         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 309         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 310         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 311         fields.
 312         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 313
 314 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 315
 316         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 317         sve_size_hsd2 iclass encode.
 318         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 319         sve_size_hsd2 iclass decode.
 320         * aarch64-opc.c (fields): Handle SVE_size field.
 321         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 322
 323 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 324
 325         * aarch64-asm-2.c: Regenerated.
 326         * aarch64-dis-2.c: Regenerated.
 327         * aarch64-opc-2.c: Regenerated.
 328         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 329         for SVE_IMM_ROT3.
 330         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 331         (fields): Handle SVE_rot3 field.
 332         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 333         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 334
 335 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 336
 337         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 338         instructions.
 339
 340 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 341
 342         * aarch64-tbl.h
 343         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 344         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 345         aarch64_feature_sve2bitperm): New feature sets.
 346         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 347         for feature set addresses.
 348         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 349         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 350
 351 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 352             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 353
 354         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 355         argument and set ASE_EVA_R6 appropriately.
 356         (set_default_mips_dis_options): Pass ISA to above.
 357         (parse_mips_dis_option): Likewise.
 358         * mips-opc.c (EVAR6): New macro.
 359         (mips_builtin_opcodes): Add llwpe, scwpe.
 360
 361 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 362
 363         * aarch64-asm-2.c: Regenerated.
 364         * aarch64-dis-2.c: Regenerated.
 365         * aarch64-opc-2.c: Regenerated.
 366         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 367         AARCH64_OPND_TME_UIMM16.
 368         (aarch64_print_operand): Likewise.
 369         * aarch64-tbl.h (QL_IMM_NIL): New.
 370         (TME): New.
 371         (_TME_INSN): New.
 372         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 373
 374 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 375
 376         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 377
 378 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 379             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 380
 381         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 382
 383 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 384
 385         * s12z-opc.h: Add extern "C" bracketing to help
 386         users who wish to use this interface in c++ code.
 387
 388 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 389
 390         * s12z-opc.c (bm_decode): Handle bit map operations with the
 391         "reserved0" mode.
 392
 393 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 394
 395         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 396         specifier.  Add entries for VLDR and VSTR of system registers.
 397         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 398         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 399         of %J and %K format specifier.
 400
 401 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 402
 403         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 404         Add new entries for VSCCLRM instruction.
 405         (print_insn_coprocessor): Handle new %C format control code.
 406
 407 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 408
 409         * arm-dis.c (enum isa): New enum.
 410         (struct sopcode32): New structure.
 411         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 412         set isa field of all current entries to ANY.
 413         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 414         Only match an entry if its isa field allows the current mode.
 415
 416 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 417
 418         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 419         CLRM.
 420         (print_insn_thumb32): Add logic to print %n CLRM register list.
 421
 422 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 423
 424         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 425         and %Q patterns.
 426
 427 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 428
 429         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 430         (print_insn_thumb32): Edit the switch case for %Z.
 431
 432 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 433
 434         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 435
 436 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 437
 438         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 439
 440 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 441
 442         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 443
 444 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 445
 446         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 447         Arm register with r13 and r15 unpredictable.
 448         (thumb32_opcodes): New instructions for bfx and bflx.
 449
 450 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 451
 452         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 453
 454 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 455
 456         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 457
 458 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 459
 460         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 461
 462 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 463
 464         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 465
 466 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 467
 468         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 469         "optr". ("operator" is a reserved word in c++).
 470
 471 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 472
 473         * aarch64-opc.c (aarch64_print_operand): Add case for
 474         AARCH64_OPND_Rt_SP.
 475         (verify_constraints): Likewise.
 476         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 477         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 478         to accept Rt|SP as first operand.
 479         (AARCH64_OPERANDS): Add new Rt_SP.
 480         * aarch64-asm-2.c: Regenerated.
 481         * aarch64-dis-2.c: Regenerated.
 482         * aarch64-opc-2.c: Regenerated.
 483
 484 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 485
 486         * aarch64-asm-2.c: Regenerated.
 487         * aarch64-dis-2.c: Likewise.
 488         * aarch64-opc-2.c: Likewise.
 489         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 490
 491 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 492
 493         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 494
 495 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 496
 497         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 498         * i386-init.h: Regenerated.
 499
 500 2019-04-07  Alan Modra  <amodra@gmail.com>
 501
 502         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 503         op_separator to control printing of spaces, comma and parens
 504         rather than need_comma, need_paren and spaces vars.
 505
 506 2019-04-07  Alan Modra  <amodra@gmail.com>
 507
 508         PR 24421
 509         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 510         (print_insn_neon, print_insn_arm): Likewise.
 511
 512 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 513
 514         * i386-dis-evex.h (evex_table): Updated to support BF16
 515         instructions.
 516         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 517         and EVEX_W_0F3872_P_3.
 518         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 519         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 520         * i386-opc.h (enum): Add CpuAVX512_BF16.
 521         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 522         * i386-opc.tbl: Add AVX512 BF16 instructions.
 523         * i386-init.h: Regenerated.
 524         * i386-tbl.h: Likewise.
 525
 526 2019-04-05  Alan Modra  <amodra@gmail.com>
 527
 528         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 529         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 530         to favour printing of "-" branch hint when using the "y" bit.
 531         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 532
 533 2019-04-05  Alan Modra  <amodra@gmail.com>
 534
 535         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 536         opcode until first operand is output.
 537
 538 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 539
 540         PR gas/24349
 541         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 542         (valid_bo_post_v2): Add support for 'at' branch hints.
 543         (insert_bo): Only error on branch on ctr.
 544         (get_bo_hint_mask): New function.
 545         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 546         for inserting 'at' branch hints.
 547         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 548         for extracting 'at' branch hints.
 549         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 550         (BOE): Delete operand.
 551         (BOM, BOP): New operands.
 552         (RM): Update value.
 553         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 554         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 555         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 556         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 557         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 558         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 559         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 560         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 561         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 562         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 563         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 564         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 565         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 566         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 567         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 568         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 569         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 570         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 571         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 572         bttarl+>: New extended mnemonics.
 573
 574 2019-03-28  Alan Modra  <amodra@gmail.com>
 575
 576         PR 24390
 577         * ppc-opc.c (BTF): Define.
 578         (powerpc_opcodes): Use for mtfsb*.
 579         * ppc-dis.c (print_insn_powerpc): Print fields with both
 580         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 581
 582 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 583
 584         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 585         (mapping_symbol_for_insn): Implement new algorithm.
 586         (print_insn): Remove duplicate code.
 587
 588 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 589
 590         * aarch64-dis.c (print_insn_aarch64):
 591         Implement override.
 592
 593 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 594
 595         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 596         order.
 597
 598 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 599
 600         * aarch64-dis.c (last_stop_offset): New.
 601         (print_insn_aarch64): Use stop_offset.
 602
 603 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 604
 605         PR gas/24359
 606         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 607         CPU_ANY_AVX2_FLAGS.
 608         * i386-init.h: Regenerated.
 609
 610 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 611
 612         PR gas/24348
 613         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 614         vmovdqu16, vmovdqu32 and vmovdqu64.
 615         * i386-tbl.h: Regenerated.
 616
 617 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 618
 619         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 620         from vstrszb, vstrszh, and vstrszf.
 621
 622 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 623
 624         * s390-opc.txt: Add instruction descriptions.
 625
 626 2019-02-08  Jim Wilson  <jimw@sifive.com>
 627
 628         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 629         <bne>: Likewise.
 630
 631 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 632
 633         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
 634
 635 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 636
 637         PR binutils/23212
 638         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
 639         * aarch64-opc.c (verify_elem_sd): New.
 640         (fields): Add FLD_sz entr.
 641         * aarch64-tbl.h (_SIMD_INSN): New.
 642         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
 643         fmulx scalar and vector by element isns.
 644
 645 2019-02-07  Nick Clifton  <nickc@redhat.com>
 646
 647         * po/sv.po: Updated Swedish translation.
 648
 649 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
 650
 651         * s390-mkopc.c (main): Accept arch13 as cpu string.
 652         * s390-opc.c: Add new instruction formats and instruction opcode
 653         masks.
 654         * s390-opc.txt: Add new arch13 instructions.
 655
 656 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 657
 658         * aarch64-tbl.h (QL_LDST_AT): Update macro.
 659         (aarch64_opcode): Change encoding for stg, stzg
 660         st2g and st2zg.
 661         * aarch64-asm-2.c: Regenerated.
 662         * aarch64-dis-2.c: Regenerated.
 663         * aarch64-opc-2.c: Regenerated.
 664
 665 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 666
 667         * aarch64-asm-2.c: Regenerated.
 668         * aarch64-dis-2.c: Likewise.
 669         * aarch64-opc-2.c: Likewise.
 670         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
 671
 672 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 673             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 674
 675         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
 676         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
 677         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
 678         * aarch64-dis.h (ext_addr_simple_2): Likewise.
 679         * aarch64-opc.c (operand_general_constraint_met_p): Remove
 680         case for ldstgv_indexed.
 681         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
 682         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
 683         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
 684         * aarch64-asm-2.c: Regenerated.
 685         * aarch64-dis-2.c: Regenerated.
 686         * aarch64-opc-2.c: Regenerated.
 687
 688 2019-01-23  Nick Clifton  <nickc@redhat.com>
 689
 690         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 691
 692 2019-01-21  Nick Clifton  <nickc@redhat.com>
 693
 694         * po/de.po: Updated German translation.
 695         * po/uk.po: Updated Ukranian translation.
 696
 697 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 698         * mips-dis.c (mips_arch_choices): Fix typo in
 699         gs464, gs464e and gs264e descriptors.
 700
 701 2019-01-19  Nick Clifton  <nickc@redhat.com>
 702
 703         * configure: Regenerate.
 704         * po/opcodes.pot: Regenerate.
 705
 706 2018-06-24  Nick Clifton  <nickc@redhat.com>
 707
 708         2.32 branch created.
 709
 710 2019-01-09  John Darrington <john@darrington.wattle.id.au>
 711
 712         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
 713         if it is null.
 714         -dis.c (opr_emit_disassembly): Do not omit an index if it is
 715         zero.
 716
 717 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
 718
 719         * configure: Regenerate.
 720
 721 2019-01-07  Alan Modra  <amodra@gmail.com>
 722
 723         * configure: Regenerate.
 724         * po/POTFILES.in: Regenerate.
 725
 726 2019-01-03  John Darrington <john@darrington.wattle.id.au>
 727
 728         * s12z-opc.c: New file.
 729         * s12z-opc.h: New file.
 730         * s12z-dis.c: Removed all code not directly related to display
 731         of instructions.  Used the interface provided by the new files
 732         instead.
 733         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
 734         * Makefile.in: Regenerate.
 735         * configure.ac (bfd_s12z_arch): Correct the dependencies.
 736         * configure: Regenerate.
 737
 738 2019-01-01  Alan Modra  <amodra@gmail.com>
 739
 740         Update year range in copyright notice of all files.
 741
 742 For older changes see ChangeLog-2018
 743 \f
 744 Copyright (C) 2019 Free Software Foundation, Inc.
 745
 746 Copying and distribution of this file, with or without modification,
 747 are permitted in any medium without royalty provided the copyright
 748 notice and this notice are preserved.
 749
 750 Local Variables:
 751 mode: change-log
 752 left-margin: 8
 753 fill-column: 74
 754 version-control: never
 755 End: