1 2020-07-04 Nick Clifton <nickc@redhat.com>
3 * configure: Regenerate.
4 * po/opcodes.pot: Regenerate.
6 2020-07-04 Nick Clifton <nickc@redhat.com>
8 Binutils 2.35 branch created.
10 2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
12 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
13 * i386-opc.h (VexSwapSources): New.
14 (i386_opcode_modifier): Add vexswapsources.
15 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
16 with two source operands swapped.
17 * i386-tbl.h: Regenerated.
19 2020-06-30 Nelson Chu <nelson.chu@sifive.com>
21 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
22 unprivileged CSR can also be initialized.
24 2020-06-29 Alan Modra <amodra@gmail.com>
26 * arm-dis.c: Use C style comments.
27 * cr16-opc.c: Likewise.
28 * ft32-dis.c: Likewise.
29 * moxie-opc.c: Likewise.
30 * tic54x-dis.c: Likewise.
31 * s12z-opc.c: Remove useless comment.
32 * xgate-dis.c: Likewise.
34 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
36 * i386-opc.tbl: Add a blank line.
38 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
40 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
41 (VecSIB128): Renamed to ...
43 (VecSIB256): Renamed to ...
45 (VecSIB512): Renamed to ...
47 (VecSIB): Renamed to ...
49 (i386_opcode_modifier): Replace vecsib with sib.
50 * i386-opc.tbl (VecSIB128): New.
51 (VecSIB256): Likewise.
52 (VecSIB512): Likewise.
53 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
54 and VecSIB512, respectively.
56 2020-06-26 Jan Beulich <jbeulich@suse.com>
58 * i386-dis.c: Adjust description of I macro.
59 (x86_64_table): Drop use of I.
60 (float_mem): Replace use of I.
61 (putop): Remove handling of I. Adjust setting/clearing of "alt".
63 2020-06-26 Jan Beulich <jbeulich@suse.com>
65 * i386-dis.c: (print_insn): Avoid straight assignment to
66 priv.orig_sizeflag when processing -M sub-options.
68 2020-06-25 Jan Beulich <jbeulich@suse.com>
70 * i386-dis.c: Adjust description of J macro.
71 (dis386, x86_64_table, mod_table): Replace J.
72 (putop): Remove handling of J.
74 2020-06-25 Jan Beulich <jbeulich@suse.com>
76 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
78 2020-06-25 Jan Beulich <jbeulich@suse.com>
80 * i386-dis.c: Adjust description of "LQ" macro.
81 (dis386_twobyte): Use LQ for sysret.
82 (putop): Adjust handling of LQ.
84 2020-06-22 Nelson Chu <nelson.chu@sifive.com>
86 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
87 * riscv-dis.c: Include elfxx-riscv.h.
89 2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
91 * i386-dis.c (prefix_table): Revert the last vmgexit change.
93 2020-06-17 Lili Cui <lili.cui@intel.com>
95 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
97 2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
100 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
101 * i386-opc.tbl: Likewise.
102 * i386-tbl.h: Regenerated.
104 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
106 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
108 2020-06-11 Alex Coplan <alex.coplan@arm.com>
110 * aarch64-opc.c (SYSREG): New macro for describing system registers.
122 (SR_ID_PFR2): Likewise.
123 (SR_PROFILE): Likewise.
124 (SR_MEMTAG): Likewise.
125 (SR_SCXTNUM): Likewise.
126 (aarch64_sys_regs): Refactor to store feature information in the table.
127 (aarch64_sys_reg_supported_p): Collapse logic for system registers
128 that now describe their own features.
129 (aarch64_pstatefield_supported_p): Likewise.
131 2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
133 * i386-dis.c (prefix_table): Fix a typo in comments.
135 2020-06-09 Jan Beulich <jbeulich@suse.com>
137 * i386-dis.c (rex_ignored): Delete.
138 (ckprefix): Drop rex_ignored initialization.
139 (get_valid_dis386): Drop setting of rex_ignored.
140 (print_insn): Drop checking of rex_ignored. Don't record data
141 size prefix as used with VEX-and-alike encodings.
143 2020-06-09 Jan Beulich <jbeulich@suse.com>
145 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
146 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
147 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
148 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
149 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
150 VEX_0F12, and VEX_0F16.
151 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
152 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
153 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
154 from movlps and movhlps. New MOD_0F12_PREFIX_2,
155 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
156 MOD_VEX_0F16_PREFIX_2 entries.
158 2020-06-09 Jan Beulich <jbeulich@suse.com>
160 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
161 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
162 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
163 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
164 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
165 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
166 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
167 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
168 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
169 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
170 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
171 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
172 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
173 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
174 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
175 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
176 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
177 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
178 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
179 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
180 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
181 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
182 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
183 EVEX_W_0FC6_P_2): Delete.
184 (print_insn): Add EVEX.W vs embedded prefix consistency check
185 to prefix validation.
186 * i386-dis-evex.h (evex_table): Don't further descend for
187 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
188 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
190 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
191 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
192 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
193 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
194 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
195 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
196 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
197 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
198 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
199 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
200 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
201 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
202 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
203 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
204 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
205 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
206 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
207 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
208 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
209 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
210 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
211 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
212 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
213 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
214 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
215 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
216 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
218 2020-06-09 Jan Beulich <jbeulich@suse.com>
220 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
221 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
222 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
224 (print_insn): Drop pointless check against bad_opcode. Split
225 prefix validation into legacy and VEX-and-alike parts.
226 (putop): Re-work 'X' macro handling.
228 2020-06-09 Jan Beulich <jbeulich@suse.com>
230 * i386-dis.c (MOD_0F51): Rename to ...
231 (MOD_0F50): ... this.
233 2020-06-08 Alex Coplan <alex.coplan@arm.com>
235 * arm-dis.c (arm_opcodes): Add dfb.
236 (thumb32_opcodes): Add dfb.
238 2020-06-08 Jan Beulich <jbeulich@suse.com>
240 * i386-opc.h (reg_entry): Const-qualify reg_name field.
242 2020-06-06 Alan Modra <amodra@gmail.com>
244 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
246 2020-06-05 Alan Modra <amodra@gmail.com>
248 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
249 size is large enough.
251 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
253 * disassemble.c (disassemble_init_for_target): Set endian_code for
255 * bpf-desc.c: Regenerate.
256 * bpf-opc.c: Likewise.
257 * bpf-dis.c: Likewise.
259 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
261 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
262 (cgen_put_insn_value): Likewise.
263 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
264 * cgen-dis.in (print_insn): Likewise.
265 * cgen-ibld.in (insert_1): Likewise.
266 (insert_1): Likewise.
267 (insert_insn_normal): Likewise.
268 (extract_1): Likewise.
269 * bpf-dis.c: Regenerate.
270 * bpf-ibld.c: Likewise.
271 * bpf-ibld.c: Likewise.
272 * cgen-dis.in: Likewise.
273 * cgen-ibld.in: Likewise.
274 * cgen-opc.c: Likewise.
275 * epiphany-dis.c: Likewise.
276 * epiphany-ibld.c: Likewise.
277 * fr30-dis.c: Likewise.
278 * fr30-ibld.c: Likewise.
279 * frv-dis.c: Likewise.
280 * frv-ibld.c: Likewise.
281 * ip2k-dis.c: Likewise.
282 * ip2k-ibld.c: Likewise.
283 * iq2000-dis.c: Likewise.
284 * iq2000-ibld.c: Likewise.
285 * lm32-dis.c: Likewise.
286 * lm32-ibld.c: Likewise.
287 * m32c-dis.c: Likewise.
288 * m32c-ibld.c: Likewise.
289 * m32r-dis.c: Likewise.
290 * m32r-ibld.c: Likewise.
291 * mep-dis.c: Likewise.
292 * mep-ibld.c: Likewise.
293 * mt-dis.c: Likewise.
294 * mt-ibld.c: Likewise.
295 * or1k-dis.c: Likewise.
296 * or1k-ibld.c: Likewise.
297 * xc16x-dis.c: Likewise.
298 * xc16x-ibld.c: Likewise.
299 * xstormy16-dis.c: Likewise.
300 * xstormy16-ibld.c: Likewise.
302 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
304 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
305 (print_insn_): Handle instruction endian.
306 * bpf-dis.c: Regenerate.
307 * bpf-desc.c: Regenerate.
308 * epiphany-dis.c: Likewise.
309 * epiphany-desc.c: Likewise.
310 * fr30-dis.c: Likewise.
311 * fr30-desc.c: Likewise.
312 * frv-dis.c: Likewise.
313 * frv-desc.c: Likewise.
314 * ip2k-dis.c: Likewise.
315 * ip2k-desc.c: Likewise.
316 * iq2000-dis.c: Likewise.
317 * iq2000-desc.c: Likewise.
318 * lm32-dis.c: Likewise.
319 * lm32-desc.c: Likewise.
320 * m32c-dis.c: Likewise.
321 * m32c-desc.c: Likewise.
322 * m32r-dis.c: Likewise.
323 * m32r-desc.c: Likewise.
324 * mep-dis.c: Likewise.
325 * mep-desc.c: Likewise.
326 * mt-dis.c: Likewise.
327 * mt-desc.c: Likewise.
328 * or1k-dis.c: Likewise.
329 * or1k-desc.c: Likewise.
330 * xc16x-dis.c: Likewise.
331 * xc16x-desc.c: Likewise.
332 * xstormy16-dis.c: Likewise.
333 * xstormy16-desc.c: Likewise.
335 2020-06-03 Nick Clifton <nickc@redhat.com>
337 * po/sr.po: Updated Serbian translation.
339 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
341 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
342 (riscv_get_priv_spec_class): Likewise.
344 2020-06-01 Alan Modra <amodra@gmail.com>
346 * bpf-desc.c: Regenerate.
348 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
349 David Faust <david.faust@oracle.com>
351 * bpf-desc.c: Regenerate.
352 * bpf-opc.h: Likewise.
353 * bpf-opc.c: Likewise.
354 * bpf-dis.c: Likewise.
356 2020-05-28 Alan Modra <amodra@gmail.com>
358 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
361 2020-05-28 Alan Modra <amodra@gmail.com>
363 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
365 (print_insn_ns32k): Revert last change.
367 2020-05-28 Nick Clifton <nickc@redhat.com>
369 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
372 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
374 Fix extraction of signed constants in nios2 disassembler (again).
376 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
377 extractions of signed fields.
379 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
381 * s390-opc.txt: Relocate vector load/store instructions with
382 additional alignment parameter and change architecture level
383 constraint from z14 to z13.
385 2020-05-21 Alan Modra <amodra@gmail.com>
387 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
388 * sparc-dis.c: Likewise.
389 * tic4x-dis.c: Likewise.
390 * xtensa-dis.c: Likewise.
391 * bpf-desc.c: Regenerate.
392 * epiphany-desc.c: Regenerate.
393 * fr30-desc.c: Regenerate.
394 * frv-desc.c: Regenerate.
395 * ip2k-desc.c: Regenerate.
396 * iq2000-desc.c: Regenerate.
397 * lm32-desc.c: Regenerate.
398 * m32c-desc.c: Regenerate.
399 * m32r-desc.c: Regenerate.
400 * mep-asm.c: Regenerate.
401 * mep-desc.c: Regenerate.
402 * mt-desc.c: Regenerate.
403 * or1k-desc.c: Regenerate.
404 * xc16x-desc.c: Regenerate.
405 * xstormy16-desc.c: Regenerate.
407 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
409 * riscv-opc.c (riscv_ext_version_table): The table used to store
410 all information about the supported spec and the corresponding ISA
411 versions. Currently, only Zicsr is supported to verify the
412 correctness of Z sub extension settings. Others will be supported
413 in the future patches.
414 (struct isa_spec_t, isa_specs): List for all supported ISA spec
415 classes and the corresponding strings.
416 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
417 spec class by giving a ISA spec string.
418 * riscv-opc.c (struct priv_spec_t): New structure.
419 (struct priv_spec_t priv_specs): List for all supported privilege spec
420 classes and the corresponding strings.
421 (riscv_get_priv_spec_class): New function. Get the corresponding
422 privilege spec class by giving a spec string.
423 (riscv_get_priv_spec_name): New function. Get the corresponding
424 privilege spec string by giving a CSR version class.
425 * riscv-dis.c: Updated since DECLARE_CSR is changed.
426 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
427 according to the chosen version. Build a hash table riscv_csr_hash to
428 store the valid CSR for the chosen pirv verison. Dump the direct
429 CSR address rather than it's name if it is invalid.
430 (parse_riscv_dis_option_without_args): New function. Parse the options
432 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
433 parse the options without arguments first, and then handle the options
434 with arguments. Add the new option -Mpriv-spec, which has argument.
435 * riscv-dis.c (print_riscv_disassembler_options): Add description
436 about the new OBJDUMP option.
438 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
440 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
441 WC values on POWER10 sync, dcbf and wait instructions.
442 (insert_pl, extract_pl): New functions.
443 (L2OPT, LS, WC): Use insert_ls and extract_ls.
444 (LS3): New , 3-bit L for sync.
445 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
446 (SC2, PL): New, 2-bit SC and PL for sync and wait.
447 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
448 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
449 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
450 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
451 <wait>: Enable PL operand on POWER10.
452 <dcbf>: Enable L3OPT operand on POWER10.
453 <sync>: Enable SC2 operand on POWER10.
455 2020-05-19 Stafford Horne <shorne@gmail.com>
458 * or1k-asm.c: Regenerate.
459 * or1k-desc.c: Regenerate.
460 * or1k-desc.h: Regenerate.
461 * or1k-dis.c: Regenerate.
462 * or1k-ibld.c: Regenerate.
463 * or1k-opc.c: Regenerate.
464 * or1k-opc.h: Regenerate.
465 * or1k-opinst.c: Regenerate.
467 2020-05-11 Alan Modra <amodra@gmail.com>
469 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
472 2020-05-11 Alan Modra <amodra@gmail.com>
474 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
475 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
477 2020-05-11 Alan Modra <amodra@gmail.com>
479 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
481 2020-05-11 Alan Modra <amodra@gmail.com>
483 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
484 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
486 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
488 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
491 2020-05-11 Alan Modra <amodra@gmail.com>
493 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
494 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
495 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
496 (prefix_opcodes): Add xxeval.
498 2020-05-11 Alan Modra <amodra@gmail.com>
500 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
501 xxgenpcvwm, xxgenpcvdm.
503 2020-05-11 Alan Modra <amodra@gmail.com>
505 * ppc-opc.c (MP, VXVAM_MASK): Define.
506 (VXVAPS_MASK): Use VXVA_MASK.
507 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
508 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
509 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
510 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
512 2020-05-11 Alan Modra <amodra@gmail.com>
513 Peter Bergner <bergner@linux.ibm.com>
515 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
517 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
518 YMSK2, XA6a, XA6ap, XB6a entries.
519 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
520 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
522 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
523 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
524 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
525 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
526 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
527 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
528 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
529 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
530 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
531 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
532 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
533 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
534 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
535 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
537 2020-05-11 Alan Modra <amodra@gmail.com>
539 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
540 (insert_xts, extract_xts): New functions.
541 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
542 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
543 (VXRC_MASK, VXSH_MASK): Define.
544 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
545 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
546 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
547 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
548 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
549 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
550 xxblendvh, xxblendvw, xxblendvd, xxpermx.
552 2020-05-11 Alan Modra <amodra@gmail.com>
554 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
555 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
556 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
557 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
558 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
560 2020-05-11 Alan Modra <amodra@gmail.com>
562 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
563 (XTP, DQXP, DQXP_MASK): Define.
564 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
565 (prefix_opcodes): Add plxvp and pstxvp.
567 2020-05-11 Alan Modra <amodra@gmail.com>
569 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
570 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
571 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
573 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
575 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
577 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
579 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
581 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
583 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
585 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
587 2020-05-11 Alan Modra <amodra@gmail.com>
589 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
591 2020-05-11 Alan Modra <amodra@gmail.com>
593 * ppc-dis.c (ppc_opts): Add "power10" entry.
594 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
595 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
597 2020-05-11 Nick Clifton <nickc@redhat.com>
599 * po/fr.po: Updated French translation.
601 2020-04-30 Alex Coplan <alex.coplan@arm.com>
603 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
604 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
605 (operand_general_constraint_met_p): validate
606 AARCH64_OPND_UNDEFINED.
607 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
609 * aarch64-asm-2.c: Regenerated.
610 * aarch64-dis-2.c: Regenerated.
611 * aarch64-opc-2.c: Regenerated.
613 2020-04-29 Nick Clifton <nickc@redhat.com>
616 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
619 2020-04-29 Nick Clifton <nickc@redhat.com>
621 * po/sv.po: Updated Swedish translation.
623 2020-04-29 Nick Clifton <nickc@redhat.com>
626 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
627 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
628 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
631 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
634 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
635 cmpi only on m68020up and cpu32.
637 2020-04-20 Sudakshina Das <sudi.das@arm.com>
639 * aarch64-asm.c (aarch64_ins_none): New.
640 * aarch64-asm.h (ins_none): New declaration.
641 * aarch64-dis.c (aarch64_ext_none): New.
642 * aarch64-dis.h (ext_none): New declaration.
643 * aarch64-opc.c (aarch64_print_operand): Update case for
644 AARCH64_OPND_BARRIER_PSB.
645 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
646 (AARCH64_OPERANDS): Update inserter/extracter for
647 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
648 * aarch64-asm-2.c: Regenerated.
649 * aarch64-dis-2.c: Regenerated.
650 * aarch64-opc-2.c: Regenerated.
652 2020-04-20 Sudakshina Das <sudi.das@arm.com>
654 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
655 (aarch64_feature_ras, RAS): Likewise.
656 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
657 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
658 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
659 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
660 * aarch64-asm-2.c: Regenerated.
661 * aarch64-dis-2.c: Regenerated.
662 * aarch64-opc-2.c: Regenerated.
664 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
666 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
667 (print_insn_neon): Support disassembly of conditional
670 2020-02-16 David Faust <david.faust@oracle.com>
672 * bpf-desc.c: Regenerate.
673 * bpf-desc.h: Likewise.
674 * bpf-opc.c: Regenerate.
675 * bpf-opc.h: Likewise.
677 2020-04-07 Lili Cui <lili.cui@intel.com>
679 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
680 (prefix_table): New instructions (see prefixes above).
682 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
683 CPU_ANY_TSXLDTRK_FLAGS.
684 (cpu_flags): Add CpuTSXLDTRK.
685 * i386-opc.h (enum): Add CpuTSXLDTRK.
686 (i386_cpu_flags): Add cputsxldtrk.
687 * i386-opc.tbl: Add XSUSPLDTRK insns.
688 * i386-init.h: Regenerate.
689 * i386-tbl.h: Likewise.
691 2020-04-02 Lili Cui <lili.cui@intel.com>
693 * i386-dis.c (prefix_table): New instructions serialize.
694 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
695 CPU_ANY_SERIALIZE_FLAGS.
696 (cpu_flags): Add CpuSERIALIZE.
697 * i386-opc.h (enum): Add CpuSERIALIZE.
698 (i386_cpu_flags): Add cpuserialize.
699 * i386-opc.tbl: Add SERIALIZE insns.
700 * i386-init.h: Regenerate.
701 * i386-tbl.h: Likewise.
703 2020-03-26 Alan Modra <amodra@gmail.com>
705 * disassemble.h (opcodes_assert): Declare.
706 (OPCODES_ASSERT): Define.
707 * disassemble.c: Don't include assert.h. Include opintl.h.
708 (opcodes_assert): New function.
709 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
710 (bfd_h8_disassemble): Reduce size of data array. Correctly
711 calculate maxlen. Omit insn decoding when insn length exceeds
712 maxlen. Exit from nibble loop when looking for E, before
713 accessing next data byte. Move processing of E outside loop.
714 Replace tests of maxlen in loop with assertions.
716 2020-03-26 Alan Modra <amodra@gmail.com>
718 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
720 2020-03-25 Alan Modra <amodra@gmail.com>
722 * z80-dis.c (suffix): Init mybuf.
724 2020-03-22 Alan Modra <amodra@gmail.com>
726 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
727 successflly read from section.
729 2020-03-22 Alan Modra <amodra@gmail.com>
731 * arc-dis.c (find_format): Use ISO C string concatenation rather
732 than line continuation within a string. Don't access needs_limm
733 before testing opcode != NULL.
735 2020-03-22 Alan Modra <amodra@gmail.com>
737 * ns32k-dis.c (print_insn_arg): Update comment.
738 (print_insn_ns32k): Reduce size of index_offset array, and
739 initialize, passing -1 to print_insn_arg for args that are not
740 an index. Don't exit arg loop early. Abort on bad arg number.
742 2020-03-22 Alan Modra <amodra@gmail.com>
744 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
745 * s12z-opc.c: Formatting.
746 (operands_f): Return an int.
747 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
748 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
749 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
750 (exg_sex_discrim): Likewise.
751 (create_immediate_operand, create_bitfield_operand),
752 (create_register_operand_with_size, create_register_all_operand),
753 (create_register_all16_operand, create_simple_memory_operand),
754 (create_memory_operand, create_memory_auto_operand): Don't
755 segfault on malloc failure.
756 (z_ext24_decode): Return an int status, negative on fail, zero
758 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
759 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
760 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
761 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
762 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
763 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
764 (loop_primitive_decode, shift_decode, psh_pul_decode),
765 (bit_field_decode): Similarly.
766 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
767 to return value, update callers.
768 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
769 Don't segfault on NULL operand.
770 (decode_operation): Return OP_INVALID on first fail.
771 (decode_s12z): Check all reads, returning -1 on fail.
773 2020-03-20 Alan Modra <amodra@gmail.com>
775 * metag-dis.c (print_insn_metag): Don't ignore status from
778 2020-03-20 Alan Modra <amodra@gmail.com>
780 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
781 Initialize parts of buffer not written when handling a possible
782 2-byte insn at end of section. Don't attempt decoding of such
783 an insn by the 4-byte machinery.
785 2020-03-20 Alan Modra <amodra@gmail.com>
787 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
788 partially filled buffer. Prevent lookup of 4-byte insns when
789 only VLE 2-byte insns are possible due to section size. Print
790 ".word" rather than ".long" for 2-byte leftovers.
792 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
795 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
797 2020-03-13 Jan Beulich <jbeulich@suse.com>
799 * i386-dis.c (X86_64_0D): Rename to ...
800 (X86_64_0E): ... this.
802 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
804 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
805 * Makefile.in: Regenerated.
807 2020-03-09 Jan Beulich <jbeulich@suse.com>
809 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
811 * i386-tbl.h: Re-generate.
813 2020-03-09 Jan Beulich <jbeulich@suse.com>
815 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
816 vprot*, vpsha*, and vpshl*.
817 * i386-tbl.h: Re-generate.
819 2020-03-09 Jan Beulich <jbeulich@suse.com>
821 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
822 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
823 * i386-tbl.h: Re-generate.
825 2020-03-09 Jan Beulich <jbeulich@suse.com>
827 * i386-gen.c (set_bitfield): Ignore zero-length field names.
828 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
829 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
830 * i386-tbl.h: Re-generate.
832 2020-03-09 Jan Beulich <jbeulich@suse.com>
834 * i386-gen.c (struct template_arg, struct template_instance,
835 struct template_param, struct template, templates,
836 parse_template, expand_templates): New.
837 (process_i386_opcodes): Various local variables moved to
838 expand_templates. Call parse_template and expand_templates.
839 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
840 * i386-tbl.h: Re-generate.
842 2020-03-06 Jan Beulich <jbeulich@suse.com>
844 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
845 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
846 register and memory source templates. Replace VexW= by VexW*
848 * i386-tbl.h: Re-generate.
850 2020-03-06 Jan Beulich <jbeulich@suse.com>
852 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
853 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
854 * i386-tbl.h: Re-generate.
856 2020-03-06 Jan Beulich <jbeulich@suse.com>
858 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
859 * i386-tbl.h: Re-generate.
861 2020-03-06 Jan Beulich <jbeulich@suse.com>
863 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
864 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
865 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
866 VexW0 on SSE2AVX variants.
867 (vmovq): Drop NoRex64 from XMM/XMM variants.
868 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
869 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
870 applicable use VexW0.
871 * i386-tbl.h: Re-generate.
873 2020-03-06 Jan Beulich <jbeulich@suse.com>
875 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
876 * i386-opc.h (Rex64): Delete.
877 (struct i386_opcode_modifier): Remove rex64 field.
878 * i386-opc.tbl (crc32): Drop Rex64.
879 Replace Rex64 with Size64 everywhere else.
880 * i386-tbl.h: Re-generate.
882 2020-03-06 Jan Beulich <jbeulich@suse.com>
884 * i386-dis.c (OP_E_memory): Exclude recording of used address
885 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
886 addressed memory operands for MPX insns.
888 2020-03-06 Jan Beulich <jbeulich@suse.com>
890 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
891 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
892 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
893 (ptwrite): Split into non-64-bit and 64-bit forms.
894 * i386-tbl.h: Re-generate.
896 2020-03-06 Jan Beulich <jbeulich@suse.com>
898 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
900 * i386-tbl.h: Re-generate.
902 2020-03-04 Jan Beulich <jbeulich@suse.com>
904 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
905 (prefix_table): Move vmmcall here. Add vmgexit.
906 (rm_table): Replace vmmcall entry by prefix_table[] escape.
907 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
908 (cpu_flags): Add CpuSEV_ES entry.
909 * i386-opc.h (CpuSEV_ES): New.
910 (union i386_cpu_flags): Add cpusev_es field.
911 * i386-opc.tbl (vmgexit): New.
912 * i386-init.h, i386-tbl.h: Re-generate.
914 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
916 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
918 * i386-opc.h (IGNORESIZE): New.
919 (DEFAULTSIZE): Likewise.
920 (IgnoreSize): Removed.
921 (DefaultSize): Likewise.
923 (i386_opcode_modifier): Replace ignoresize/defaultsize with
925 * i386-opc.tbl (IgnoreSize): New.
926 (DefaultSize): Likewise.
927 * i386-tbl.h: Regenerated.
929 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
932 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
935 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
938 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
939 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
940 * i386-tbl.h: Regenerated.
942 2020-02-26 Alan Modra <amodra@gmail.com>
944 * aarch64-asm.c: Indent labels correctly.
945 * aarch64-dis.c: Likewise.
946 * aarch64-gen.c: Likewise.
947 * aarch64-opc.c: Likewise.
948 * alpha-dis.c: Likewise.
949 * i386-dis.c: Likewise.
950 * nds32-asm.c: Likewise.
951 * nfp-dis.c: Likewise.
952 * visium-dis.c: Likewise.
954 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
956 * arc-regs.h (int_vector_base): Make it available for all ARC
959 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
961 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
964 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
966 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
967 c.mv/c.li if rs1 is zero.
969 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
971 * i386-gen.c (cpu_flag_init): Replace CpuABM with
972 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
974 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
975 * i386-opc.h (CpuABM): Removed.
977 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
978 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
979 popcnt. Remove CpuABM from lzcnt.
980 * i386-init.h: Regenerated.
981 * i386-tbl.h: Likewise.
983 2020-02-17 Jan Beulich <jbeulich@suse.com>
985 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
986 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
987 VexW1 instead of open-coding them.
988 * i386-tbl.h: Re-generate.
990 2020-02-17 Jan Beulich <jbeulich@suse.com>
992 * i386-opc.tbl (AddrPrefixOpReg): Define.
993 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
994 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
995 templates. Drop NoRex64.
996 * i386-tbl.h: Re-generate.
998 2020-02-17 Jan Beulich <jbeulich@suse.com>
1001 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1002 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
1003 into Intel syntax instance (with Unpsecified) and AT&T one
1005 (vcvtneps2bf16): Likewise, along with folding the two so far
1007 * i386-tbl.h: Re-generate.
1009 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1011 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1012 CPU_ANY_SSE4A_FLAGS.
1014 2020-02-17 Alan Modra <amodra@gmail.com>
1016 * i386-gen.c (cpu_flag_init): Correct last change.
1018 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1020 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
1023 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
1025 * i386-opc.tbl (movsx): Remove Intel syntax comments.
1028 2020-02-14 Jan Beulich <jbeulich@suse.com>
1031 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1032 destination for Cpu64-only variant.
1033 (movzx): Fold patterns.
1034 * i386-tbl.h: Re-generate.
1036 2020-02-13 Jan Beulich <jbeulich@suse.com>
1038 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1039 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1040 CPU_ANY_SSE4_FLAGS entry.
1041 * i386-init.h: Re-generate.
1043 2020-02-12 Jan Beulich <jbeulich@suse.com>
1045 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1046 with Unspecified, making the present one AT&T syntax only.
1047 * i386-tbl.h: Re-generate.
1049 2020-02-12 Jan Beulich <jbeulich@suse.com>
1051 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1052 * i386-tbl.h: Re-generate.
1054 2020-02-12 Jan Beulich <jbeulich@suse.com>
1057 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1058 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1059 Amd64 and Intel64 templates.
1060 (call, jmp): Likewise for far indirect variants. Dro
1062 * i386-tbl.h: Re-generate.
1064 2020-02-11 Jan Beulich <jbeulich@suse.com>
1066 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1067 * i386-opc.h (ShortForm): Delete.
1068 (struct i386_opcode_modifier): Remove shortform field.
1069 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1070 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1071 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1072 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1074 * i386-tbl.h: Re-generate.
1076 2020-02-11 Jan Beulich <jbeulich@suse.com>
1078 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1079 fucompi): Drop ShortForm from operand-less templates.
1080 * i386-tbl.h: Re-generate.
1082 2020-02-11 Alan Modra <amodra@gmail.com>
1084 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1085 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1086 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1087 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1088 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1090 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
1092 * arm-dis.c (print_insn_cde): Define 'V' parse character.
1093 (cde_opcodes): Add VCX* instructions.
1095 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
1096 Matthew Malcomson <matthew.malcomson@arm.com>
1098 * arm-dis.c (struct cdeopcode32): New.
1099 (CDE_OPCODE): New macro.
1100 (cde_opcodes): New disassembly table.
1101 (regnames): New option to table.
1102 (cde_coprocs): New global variable.
1103 (print_insn_cde): New
1104 (print_insn_thumb32): Use print_insn_cde.
1105 (parse_arm_disassembler_options): Parse coprocN args.
1107 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
1110 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1112 * i386-opc.h (AMD64): Removed.
1113 (Intel64): Likewose.
1115 (INTEL64): Likewise.
1116 (INTEL64ONLY): Likewise.
1117 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1118 * i386-opc.tbl (Amd64): New.
1119 (Intel64): Likewise.
1120 (Intel64Only): Likewise.
1121 Replace AMD64 with Amd64. Update sysenter/sysenter with
1122 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
1123 * i386-tbl.h: Regenerated.
1125 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
1128 * z80-dis.c: Add support for GBZ80 opcodes.
1130 2020-02-04 Alan Modra <amodra@gmail.com>
1132 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1134 2020-02-03 Alan Modra <amodra@gmail.com>
1136 * m32c-ibld.c: Regenerate.
1138 2020-02-01 Alan Modra <amodra@gmail.com>
1140 * frv-ibld.c: Regenerate.
1142 2020-01-31 Jan Beulich <jbeulich@suse.com>
1144 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1145 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1146 (OP_E_memory): Replace xmm_mdq_mode case label by
1147 vex_scalar_w_dq_mode one.
1148 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1150 2020-01-31 Jan Beulich <jbeulich@suse.com>
1152 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1153 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1154 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1155 (intel_operand_size): Drop vex_w_dq_mode case label.
1157 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
1159 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1160 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1162 2020-01-30 Alan Modra <amodra@gmail.com>
1164 * m32c-ibld.c: Regenerate.
1166 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
1168 * bpf-opc.c: Regenerate.
1170 2020-01-30 Jan Beulich <jbeulich@suse.com>
1172 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1173 (dis386): Use them to replace C2/C3 table entries.
1174 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1175 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1176 ones. Use Size64 instead of DefaultSize on Intel64 ones.
1177 * i386-tbl.h: Re-generate.
1179 2020-01-30 Jan Beulich <jbeulich@suse.com>
1181 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1183 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1185 * i386-tbl.h: Re-generate.
1187 2020-01-30 Alan Modra <amodra@gmail.com>
1189 * tic4x-dis.c (tic4x_dp): Make unsigned.
1191 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
1192 Jan Beulich <jbeulich@suse.com>
1195 * i386-dis.c (MOVSXD_Fixup): New function.
1196 (movsxd_mode): New enum.
1197 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1198 (intel_operand_size): Handle movsxd_mode.
1199 (OP_E_register): Likewise.
1201 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1202 register on movsxd. Add movsxd with 16-bit destination register
1203 for AMD64 and Intel64 ISAs.
1204 * i386-tbl.h: Regenerated.
1206 2020-01-27 Tamar Christina <tamar.christina@arm.com>
1209 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1210 * aarch64-asm-2.c: Regenerate
1211 * aarch64-dis-2.c: Likewise.
1212 * aarch64-opc-2.c: Likewise.
1214 2020-01-21 Jan Beulich <jbeulich@suse.com>
1216 * i386-opc.tbl (sysret): Drop DefaultSize.
1217 * i386-tbl.h: Re-generate.
1219 2020-01-21 Jan Beulich <jbeulich@suse.com>
1221 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1223 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1224 * i386-tbl.h: Re-generate.
1226 2020-01-20 Nick Clifton <nickc@redhat.com>
1228 * po/de.po: Updated German translation.
1229 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1230 * po/uk.po: Updated Ukranian translation.
1232 2020-01-20 Alan Modra <amodra@gmail.com>
1234 * hppa-dis.c (fput_const): Remove useless cast.
1236 2020-01-20 Alan Modra <amodra@gmail.com>
1238 * arm-dis.c (print_insn_arm): Wrap 'T' value.
1240 2020-01-18 Nick Clifton <nickc@redhat.com>
1242 * configure: Regenerate.
1243 * po/opcodes.pot: Regenerate.
1245 2020-01-18 Nick Clifton <nickc@redhat.com>
1247 Binutils 2.34 branch created.
1249 2020-01-17 Christian Biesinger <cbiesinger@google.com>
1251 * opintl.h: Fix spelling error (seperate).
1253 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
1255 * i386-opc.tbl: Add {vex} pseudo prefix.
1256 * i386-tbl.h: Regenerated.
1258 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1261 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1262 (neon_opcodes): Likewise.
1263 (select_arm_features): Make sure we enable MVE bits when selecting
1264 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
1267 2020-01-16 Jan Beulich <jbeulich@suse.com>
1269 * i386-opc.tbl: Drop stale comment from XOP section.
1271 2020-01-16 Jan Beulich <jbeulich@suse.com>
1273 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1274 (extractps): Add VexWIG to SSE2AVX forms.
1275 * i386-tbl.h: Re-generate.
1277 2020-01-16 Jan Beulich <jbeulich@suse.com>
1279 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1280 Size64 from and use VexW1 on SSE2AVX forms.
1281 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1282 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1283 * i386-tbl.h: Re-generate.
1285 2020-01-15 Alan Modra <amodra@gmail.com>
1287 * tic4x-dis.c (tic4x_version): Make unsigned long.
1288 (optab, optab_special, registernames): New file scope vars.
1289 (tic4x_print_register): Set up registernames rather than
1290 malloc'd registertable.
1291 (tic4x_disassemble): Delete optable and optable_special. Use
1292 optab and optab_special instead. Throw away old optab,
1293 optab_special and registernames when info->mach changes.
1295 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
1298 * z80-dis.c (suffix): Use .db instruction to generate double
1301 2020-01-14 Alan Modra <amodra@gmail.com>
1303 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
1304 values to unsigned before shifting.
1306 2020-01-13 Thomas Troeger <tstroege@gmx.de>
1308 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1310 (print_insn_thumb16, print_insn_thumb32): Likewise.
1311 (print_insn): Initialize the insn info.
1312 * i386-dis.c (print_insn): Initialize the insn info fields, and
1315 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1317 * arc-opc.c (C_NE): Make it required.
1319 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1321 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1322 reserved register name.
1324 2020-01-13 Alan Modra <amodra@gmail.com>
1326 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1327 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1329 2020-01-13 Alan Modra <amodra@gmail.com>
1331 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
1332 result of wasm_read_leb128 in a uint64_t and check that bits
1333 are not lost when copying to other locals. Use uint32_t for
1334 most locals. Use PRId64 when printing int64_t.
1336 2020-01-13 Alan Modra <amodra@gmail.com>
1338 * score-dis.c: Formatting.
1339 * score7-dis.c: Formatting.
1341 2020-01-13 Alan Modra <amodra@gmail.com>
1343 * score-dis.c (print_insn_score48): Use unsigned variables for
1344 unsigned values. Don't left shift negative values.
1345 (print_insn_score32): Likewise.
1346 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1348 2020-01-13 Alan Modra <amodra@gmail.com>
1350 * tic4x-dis.c (tic4x_print_register): Remove dead code.
1352 2020-01-13 Alan Modra <amodra@gmail.com>
1354 * fr30-ibld.c: Regenerate.
1356 2020-01-13 Alan Modra <amodra@gmail.com>
1358 * xgate-dis.c (print_insn): Don't left shift signed value.
1359 (ripBits): Formatting, use 1u.
1361 2020-01-10 Alan Modra <amodra@gmail.com>
1363 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1364 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
1366 2020-01-10 Alan Modra <amodra@gmail.com>
1368 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1369 and XRREG value earlier to avoid a shift with negative exponent.
1370 * m10200-dis.c (disassemble): Similarly.
1372 2020-01-09 Nick Clifton <nickc@redhat.com>
1375 * z80-dis.c (ld_ii_ii): Use correct cast.
1377 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1380 * z80-dis.c (ld_ii_ii): Use character constant when checking
1383 2020-01-09 Jan Beulich <jbeulich@suse.com>
1385 * i386-dis.c (SEP_Fixup): New.
1387 (dis386_twobyte): Use it for sysenter/sysexit.
1388 (enum x86_64_isa): Change amd64 enumerator to value 1.
1389 (OP_J): Compare isa64 against intel64 instead of amd64.
1390 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1392 * i386-tbl.h: Re-generate.
1394 2020-01-08 Alan Modra <amodra@gmail.com>
1396 * z8k-dis.c: Include libiberty.h
1397 (instr_data_s): Make max_fetched unsigned.
1398 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1399 Don't exceed byte_info bounds.
1400 (output_instr): Make num_bytes unsigned.
1401 (unpack_instr): Likewise for nibl_count and loop.
1402 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1404 * z8k-opc.h: Regenerate.
1406 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
1408 * arc-tbl.h (llock): Use 'LLOCK' as class.
1410 (scond): Use 'SCOND' as class.
1412 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1415 2020-01-06 Alan Modra <amodra@gmail.com>
1417 * m32c-ibld.c: Regenerate.
1419 2020-01-06 Alan Modra <amodra@gmail.com>
1422 * z80-dis.c (suffix): Don't use a local struct buffer copy.
1423 Peek at next byte to prevent recursion on repeated prefix bytes.
1424 Ensure uninitialised "mybuf" is not accessed.
1425 (print_insn_z80): Don't zero n_fetch and n_used here,..
1426 (print_insn_z80_buf): ..do it here instead.
1428 2020-01-04 Alan Modra <amodra@gmail.com>
1430 * m32r-ibld.c: Regenerate.
1432 2020-01-04 Alan Modra <amodra@gmail.com>
1434 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1436 2020-01-04 Alan Modra <amodra@gmail.com>
1438 * crx-dis.c (match_opcode): Avoid shift left of signed value.
1440 2020-01-04 Alan Modra <amodra@gmail.com>
1442 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1444 2020-01-03 Jan Beulich <jbeulich@suse.com>
1446 * aarch64-tbl.h (aarch64_opcode_table): Use
1447 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1449 2020-01-03 Jan Beulich <jbeulich@suse.com>
1451 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1452 forms of SUDOT and USDOT.
1454 2020-01-03 Jan Beulich <jbeulich@suse.com>
1456 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1458 * opcodes/aarch64-dis-2.c: Re-generate.
1460 2020-01-03 Jan Beulich <jbeulich@suse.com>
1462 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1464 * opcodes/aarch64-dis-2.c: Re-generate.
1466 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
1468 * z80-dis.c: Add support for eZ80 and Z80 instructions.
1470 2020-01-01 Alan Modra <amodra@gmail.com>
1472 Update year range in copyright notice of all files.
1474 For older changes see ChangeLog-2019
1476 Copyright (C) 2020 Free Software Foundation, Inc.
1478 Copying and distribution of this file, with or without modification,
1479 are permitted in any medium without royalty provided the copyright
1480 notice and this notice are preserved.
1486 version-control: never