opcodes/ChangeLog

   1 2020-06-12  Nelson Chu  <nelson.chu@sifive.com>
   2
   3         * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
   4
   5 2020-06-11  Alex Coplan  <alex.coplan@arm.com>
   6
   7         * aarch64-opc.c (SYSREG): New macro for describing system registers.
   8         (SR_CORE): Likewise.
   9         (SR_FEAT): Likewise.
  10         (SR_RNG): Likewise.
  11         (SR_V8_1): Likewise.
  12         (SR_V8_2): Likewise.
  13         (SR_V8_3): Likewise.
  14         (SR_V8_4): Likewise.
  15         (SR_PAN): Likewise.
  16         (SR_RAS): Likewise.
  17         (SR_SSBS): Likewise.
  18         (SR_SVE): Likewise.
  19         (SR_ID_PFR2): Likewise.
  20         (SR_PROFILE): Likewise.
  21         (SR_MEMTAG): Likewise.
  22         (SR_SCXTNUM): Likewise.
  23         (aarch64_sys_regs): Refactor to store feature information in the table.
  24         (aarch64_sys_reg_supported_p): Collapse logic for system registers
  25         that now describe their own features.
  26         (aarch64_pstatefield_supported_p): Likewise.
  27
  28 2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>
  29
  30         * i386-dis.c (prefix_table): Fix a typo in comments.
  31
  32 2020-06-09  Jan Beulich  <jbeulich@suse.com>
  33
  34         * i386-dis.c (rex_ignored): Delete.
  35         (ckprefix): Drop rex_ignored initialization.
  36         (get_valid_dis386): Drop setting of rex_ignored.
  37         (print_insn): Drop checking of rex_ignored. Don't record data
  38         size prefix as used with VEX-and-alike encodings.
  39
  40 2020-06-09  Jan Beulich  <jbeulich@suse.com>
  41
  42         * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
  43         MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
  44         (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
  45         (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
  46         (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
  47         VEX_0F12, and VEX_0F16.
  48         (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
  49         VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
  50         (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
  51         from movlps and movhlps. New MOD_0F12_PREFIX_2,
  52         MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
  53         MOD_VEX_0F16_PREFIX_2 entries.
  54
  55 2020-06-09  Jan Beulich  <jbeulich@suse.com>
  56
  57         * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
  58         MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
  59         (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
  60         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
  61         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
  62         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
  63         EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
  64         EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
  65         EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
  66         EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
  67         EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
  68         EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
  69         EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
  70         EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
  71         EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
  72         EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
  73         EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
  74         EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
  75         EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
  76         EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
  77         EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
  78         EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
  79         EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
  80         EVEX_W_0FC6_P_2): Delete.
  81         (print_insn): Add EVEX.W vs embedded prefix consistency check
  82         to prefix validation.
  83         * i386-dis-evex.h (evex_table): Don't further descend for
  84         vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
  85         and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
  86         and 0F2B.
  87         * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
  88         * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
  89         vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
  90         vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
  91         2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
  92         Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
  93         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
  94         PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
  95         PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
  96         * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
  97         EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
  98         EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
  99         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
 100         EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
 101         EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 102         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
 103         EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 104         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
 105         EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
 106         EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 107         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
 108         EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
 109         EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
 110         EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
 111         EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
 112         EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
 113         EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
 114
 115 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 116
 117         * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
 118         vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
 119         (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
 120         vmovmskpX.
 121         (print_insn): Drop pointless check against bad_opcode. Split
 122         prefix validation into legacy and VEX-and-alike parts.
 123         (putop): Re-work 'X' macro handling.
 124
 125 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 126
 127         * i386-dis.c (MOD_0F51): Rename to ...
 128         (MOD_0F50): ... this.
 129
 130 2020-06-08  Alex Coplan  <alex.coplan@arm.com>
 131
 132         * arm-dis.c (arm_opcodes): Add dfb.
 133         (thumb32_opcodes): Add dfb.
 134
 135 2020-06-08  Jan Beulich  <jbeulich@suse.com>
 136
 137         * i386-opc.h (reg_entry): Const-qualify reg_name field.
 138
 139 2020-06-06  Alan Modra  <amodra@gmail.com>
 140
 141         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
 142
 143 2020-06-05  Alan Modra  <amodra@gmail.com>
 144
 145         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
 146         size is large enough.
 147
 148 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
 149
 150         * disassemble.c (disassemble_init_for_target): Set endian_code for
 151         bpf targets.
 152         * bpf-desc.c: Regenerate.
 153         * bpf-opc.c: Likewise.
 154         * bpf-dis.c: Likewise.
 155
 156 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
 157
 158         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
 159         (cgen_put_insn_value): Likewise.
 160         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
 161         * cgen-dis.in (print_insn): Likewise.
 162         * cgen-ibld.in (insert_1): Likewise.
 163         (insert_1): Likewise.
 164         (insert_insn_normal): Likewise.
 165         (extract_1): Likewise.
 166         * bpf-dis.c: Regenerate.
 167         * bpf-ibld.c: Likewise.
 168         * bpf-ibld.c: Likewise.
 169         * cgen-dis.in: Likewise.
 170         * cgen-ibld.in: Likewise.
 171         * cgen-opc.c: Likewise.
 172         * epiphany-dis.c: Likewise.
 173         * epiphany-ibld.c: Likewise.
 174         * fr30-dis.c: Likewise.
 175         * fr30-ibld.c: Likewise.
 176         * frv-dis.c: Likewise.
 177         * frv-ibld.c: Likewise.
 178         * ip2k-dis.c: Likewise.
 179         * ip2k-ibld.c: Likewise.
 180         * iq2000-dis.c: Likewise.
 181         * iq2000-ibld.c: Likewise.
 182         * lm32-dis.c: Likewise.
 183         * lm32-ibld.c: Likewise.
 184         * m32c-dis.c: Likewise.
 185         * m32c-ibld.c: Likewise.
 186         * m32r-dis.c: Likewise.
 187         * m32r-ibld.c: Likewise.
 188         * mep-dis.c: Likewise.
 189         * mep-ibld.c: Likewise.
 190         * mt-dis.c: Likewise.
 191         * mt-ibld.c: Likewise.
 192         * or1k-dis.c: Likewise.
 193         * or1k-ibld.c: Likewise.
 194         * xc16x-dis.c: Likewise.
 195         * xc16x-ibld.c: Likewise.
 196         * xstormy16-dis.c: Likewise.
 197         * xstormy16-ibld.c: Likewise.
 198
 199 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
 200
 201         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
 202         (print_insn_): Handle instruction endian.
 203         * bpf-dis.c: Regenerate.
 204         * bpf-desc.c: Regenerate.
 205         * epiphany-dis.c: Likewise.
 206         * epiphany-desc.c: Likewise.
 207         * fr30-dis.c: Likewise.
 208         * fr30-desc.c: Likewise.
 209         * frv-dis.c: Likewise.
 210         * frv-desc.c: Likewise.
 211         * ip2k-dis.c: Likewise.
 212         * ip2k-desc.c: Likewise.
 213         * iq2000-dis.c: Likewise.
 214         * iq2000-desc.c: Likewise.
 215         * lm32-dis.c: Likewise.
 216         * lm32-desc.c: Likewise.
 217         * m32c-dis.c: Likewise.
 218         * m32c-desc.c: Likewise.
 219         * m32r-dis.c: Likewise.
 220         * m32r-desc.c: Likewise.
 221         * mep-dis.c: Likewise.
 222         * mep-desc.c: Likewise.
 223         * mt-dis.c: Likewise.
 224         * mt-desc.c: Likewise.
 225         * or1k-dis.c: Likewise.
 226         * or1k-desc.c: Likewise.
 227         * xc16x-dis.c: Likewise.
 228         * xc16x-desc.c: Likewise.
 229         * xstormy16-dis.c: Likewise.
 230         * xstormy16-desc.c: Likewise.
 231
 232 2020-06-03  Nick Clifton  <nickc@redhat.com>
 233
 234         * po/sr.po: Updated Serbian translation.
 235
 236 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
 237
 238         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
 239         (riscv_get_priv_spec_class): Likewise.
 240
 241 2020-06-01  Alan Modra  <amodra@gmail.com>
 242
 243         * bpf-desc.c: Regenerate.
 244
 245 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
 246             David Faust <david.faust@oracle.com>
 247
 248         * bpf-desc.c: Regenerate.
 249         * bpf-opc.h: Likewise.
 250         * bpf-opc.c: Likewise.
 251         * bpf-dis.c: Likewise.
 252
 253 2020-05-28  Alan Modra  <amodra@gmail.com>
 254
 255         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
 256         values.
 257
 258 2020-05-28  Alan Modra  <amodra@gmail.com>
 259
 260         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
 261         immediates.
 262         (print_insn_ns32k): Revert last change.
 263
 264 2020-05-28  Nick Clifton  <nickc@redhat.com>
 265
 266         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
 267         static.
 268
 269 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
 270
 271         Fix extraction of signed constants in nios2 disassembler (again).
 272
 273         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
 274         extractions of signed fields.
 275
 276 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
 277
 278         * s390-opc.txt: Relocate vector load/store instructions with
 279         additional alignment parameter and change architecture level
 280         constraint from z14 to z13.
 281
 282 2020-05-21  Alan Modra  <amodra@gmail.com>
 283
 284         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
 285         * sparc-dis.c: Likewise.
 286         * tic4x-dis.c: Likewise.
 287         * xtensa-dis.c: Likewise.
 288         * bpf-desc.c: Regenerate.
 289         * epiphany-desc.c: Regenerate.
 290         * fr30-desc.c: Regenerate.
 291         * frv-desc.c: Regenerate.
 292         * ip2k-desc.c: Regenerate.
 293         * iq2000-desc.c: Regenerate.
 294         * lm32-desc.c: Regenerate.
 295         * m32c-desc.c: Regenerate.
 296         * m32r-desc.c: Regenerate.
 297         * mep-asm.c: Regenerate.
 298         * mep-desc.c: Regenerate.
 299         * mt-desc.c: Regenerate.
 300         * or1k-desc.c: Regenerate.
 301         * xc16x-desc.c: Regenerate.
 302         * xstormy16-desc.c: Regenerate.
 303
 304 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
 305
 306         * riscv-opc.c (riscv_ext_version_table): The table used to store
 307         all information about the supported spec and the corresponding ISA
 308         versions.  Currently, only Zicsr is supported to verify the
 309         correctness of Z sub extension settings.  Others will be supported
 310         in the future patches.
 311         (struct isa_spec_t, isa_specs): List for all supported ISA spec
 312         classes and the corresponding strings.
 313         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
 314         spec class by giving a ISA spec string.
 315         * riscv-opc.c (struct priv_spec_t): New structure.
 316         (struct priv_spec_t priv_specs): List for all supported privilege spec
 317         classes and the corresponding strings.
 318         (riscv_get_priv_spec_class): New function.  Get the corresponding
 319         privilege spec class by giving a spec string.
 320         (riscv_get_priv_spec_name): New function.  Get the corresponding
 321         privilege spec string by giving a CSR version class.
 322         * riscv-dis.c: Updated since DECLARE_CSR is changed.
 323         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
 324         according to the chosen version.  Build a hash table riscv_csr_hash to
 325         store the valid CSR for the chosen pirv verison.  Dump the direct
 326         CSR address rather than it's name if it is invalid.
 327         (parse_riscv_dis_option_without_args): New function.  Parse the options
 328         without arguments.
 329         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
 330         parse the options without arguments first, and then handle the options
 331         with arguments.  Add the new option -Mpriv-spec, which has argument.
 332         * riscv-dis.c (print_riscv_disassembler_options): Add description
 333         about the new OBJDUMP option.
 334
 335 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
 336
 337         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
 338         WC values on POWER10 sync, dcbf  and wait instructions.
 339         (insert_pl, extract_pl): New functions.
 340         (L2OPT, LS, WC): Use insert_ls and extract_ls.
 341         (LS3): New , 3-bit L for sync.
 342         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
 343         (SC2, PL): New, 2-bit SC and PL for sync and wait.
 344         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
 345         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
 346         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
 347         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
 348         <wait>: Enable PL operand on POWER10.
 349         <dcbf>: Enable L3OPT operand on POWER10.
 350         <sync>: Enable SC2 operand on POWER10.
 351
 352 2020-05-19  Stafford Horne  <shorne@gmail.com>
 353
 354         PR 25184
 355         * or1k-asm.c: Regenerate.
 356         * or1k-desc.c: Regenerate.
 357         * or1k-desc.h: Regenerate.
 358         * or1k-dis.c: Regenerate.
 359         * or1k-ibld.c: Regenerate.
 360         * or1k-opc.c: Regenerate.
 361         * or1k-opc.h: Regenerate.
 362         * or1k-opinst.c: Regenerate.
 363
 364 2020-05-11  Alan Modra  <amodra@gmail.com>
 365
 366         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
 367         xsmaxcqp, xsmincqp.
 368
 369 2020-05-11  Alan Modra  <amodra@gmail.com>
 370
 371         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
 372         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
 373
 374 2020-05-11  Alan Modra  <amodra@gmail.com>
 375
 376         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
 377
 378 2020-05-11  Alan Modra  <amodra@gmail.com>
 379
 380         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
 381         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
 382
 383 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 384
 385         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
 386         mnemonics.
 387
 388 2020-05-11  Alan Modra  <amodra@gmail.com>
 389
 390         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
 391         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
 392         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
 393         (prefix_opcodes): Add xxeval.
 394
 395 2020-05-11  Alan Modra  <amodra@gmail.com>
 396
 397         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
 398         xxgenpcvwm, xxgenpcvdm.
 399
 400 2020-05-11  Alan Modra  <amodra@gmail.com>
 401
 402         * ppc-opc.c (MP, VXVAM_MASK): Define.
 403         (VXVAPS_MASK): Use VXVA_MASK.
 404         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
 405         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
 406         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
 407         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
 408
 409 2020-05-11  Alan Modra  <amodra@gmail.com>
 410             Peter Bergner  <bergner@linux.ibm.com>
 411
 412         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
 413         New functions.
 414         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
 415         YMSK2, XA6a, XA6ap, XB6a entries.
 416         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
 417         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
 418         (PPCVSX4): Define.
 419         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
 420         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
 421         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
 422         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
 423         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
 424         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
 425         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
 426         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
 427         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
 428         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
 429         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
 430         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
 431         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
 432         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
 433
 434 2020-05-11  Alan Modra  <amodra@gmail.com>
 435
 436         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
 437         (insert_xts, extract_xts): New functions.
 438         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
 439         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
 440         (VXRC_MASK, VXSH_MASK): Define.
 441         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
 442         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
 443         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
 444         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
 445         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
 446         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
 447         xxblendvh, xxblendvw, xxblendvd, xxpermx.
 448
 449 2020-05-11  Alan Modra  <amodra@gmail.com>
 450
 451         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
 452         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
 453         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
 454         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
 455         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
 456
 457 2020-05-11  Alan Modra  <amodra@gmail.com>
 458
 459         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
 460         (XTP, DQXP, DQXP_MASK): Define.
 461         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
 462         (prefix_opcodes): Add plxvp and pstxvp.
 463
 464 2020-05-11  Alan Modra  <amodra@gmail.com>
 465
 466         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
 467         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
 468         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
 469
 470 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 471
 472         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
 473
 474 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 475
 476         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
 477         (L1OPT): Define.
 478         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
 479
 480 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 481
 482         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 483
 484 2020-05-11  Alan Modra  <amodra@gmail.com>
 485
 486         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 487
 488 2020-05-11  Alan Modra  <amodra@gmail.com>
 489
 490         * ppc-dis.c (ppc_opts): Add "power10" entry.
 491         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 492         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 493
 494 2020-05-11  Nick Clifton  <nickc@redhat.com>
 495
 496         * po/fr.po: Updated French translation.
 497
 498 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 499
 500         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 501         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 502         (operand_general_constraint_met_p): validate
 503         AARCH64_OPND_UNDEFINED.
 504         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 505         for FLD_imm16_2.
 506         * aarch64-asm-2.c: Regenerated.
 507         * aarch64-dis-2.c: Regenerated.
 508         * aarch64-opc-2.c: Regenerated.
 509
 510 2020-04-29  Nick Clifton  <nickc@redhat.com>
 511
 512         PR 22699
 513         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 514         and SETRC insns.
 515
 516 2020-04-29  Nick Clifton  <nickc@redhat.com>
 517
 518         * po/sv.po: Updated Swedish translation.
 519
 520 2020-04-29  Nick Clifton  <nickc@redhat.com>
 521
 522         PR 22699
 523         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 524         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 525         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 526         IMM0_8U case.
 527
 528 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 529
 530         PR 25848
 531         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 532         cmpi only on m68020up and cpu32.
 533
 534 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 535
 536         * aarch64-asm.c (aarch64_ins_none): New.
 537         * aarch64-asm.h (ins_none): New declaration.
 538         * aarch64-dis.c (aarch64_ext_none): New.
 539         * aarch64-dis.h (ext_none): New declaration.
 540         * aarch64-opc.c (aarch64_print_operand): Update case for
 541         AARCH64_OPND_BARRIER_PSB.
 542         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 543         (AARCH64_OPERANDS): Update inserter/extracter for
 544         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 545         * aarch64-asm-2.c: Regenerated.
 546         * aarch64-dis-2.c: Regenerated.
 547         * aarch64-opc-2.c: Regenerated.
 548
 549 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 550
 551         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 552         (aarch64_feature_ras, RAS): Likewise.
 553         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 554         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 555         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 556         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 557         * aarch64-asm-2.c: Regenerated.
 558         * aarch64-dis-2.c: Regenerated.
 559         * aarch64-opc-2.c: Regenerated.
 560
 561 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 562
 563         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 564         (print_insn_neon): Support disassembly of conditional
 565         instructions.
 566
 567 2020-02-16  David Faust  <david.faust@oracle.com>
 568
 569         * bpf-desc.c: Regenerate.
 570         * bpf-desc.h: Likewise.
 571         * bpf-opc.c: Regenerate.
 572         * bpf-opc.h: Likewise.
 573
 574 2020-04-07  Lili Cui  <lili.cui@intel.com>
 575
 576         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 577         (prefix_table): New instructions (see prefixes above).
 578         (rm_table): Likewise
 579         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 580         CPU_ANY_TSXLDTRK_FLAGS.
 581         (cpu_flags): Add CpuTSXLDTRK.
 582         * i386-opc.h (enum): Add CpuTSXLDTRK.
 583         (i386_cpu_flags): Add cputsxldtrk.
 584         * i386-opc.tbl: Add XSUSPLDTRK insns.
 585         * i386-init.h: Regenerate.
 586         * i386-tbl.h: Likewise.
 587
 588 2020-04-02  Lili Cui  <lili.cui@intel.com>
 589
 590         * i386-dis.c (prefix_table): New instructions serialize.
 591         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 592         CPU_ANY_SERIALIZE_FLAGS.
 593         (cpu_flags): Add CpuSERIALIZE.
 594         * i386-opc.h (enum): Add CpuSERIALIZE.
 595         (i386_cpu_flags): Add cpuserialize.
 596         * i386-opc.tbl: Add SERIALIZE insns.
 597         * i386-init.h: Regenerate.
 598         * i386-tbl.h: Likewise.
 599
 600 2020-03-26  Alan Modra  <amodra@gmail.com>
 601
 602         * disassemble.h (opcodes_assert): Declare.
 603         (OPCODES_ASSERT): Define.
 604         * disassemble.c: Don't include assert.h.  Include opintl.h.
 605         (opcodes_assert): New function.
 606         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 607         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 608         calculate maxlen.  Omit insn decoding when insn length exceeds
 609         maxlen.  Exit from nibble loop when looking for E, before
 610         accessing next data byte.  Move processing of E outside loop.
 611         Replace tests of maxlen in loop with assertions.
 612
 613 2020-03-26  Alan Modra  <amodra@gmail.com>
 614
 615         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 616
 617 2020-03-25  Alan Modra  <amodra@gmail.com>
 618
 619         * z80-dis.c (suffix): Init mybuf.
 620
 621 2020-03-22  Alan Modra  <amodra@gmail.com>
 622
 623         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 624         successflly read from section.
 625
 626 2020-03-22  Alan Modra  <amodra@gmail.com>
 627
 628         * arc-dis.c (find_format): Use ISO C string concatenation rather
 629         than line continuation within a string.  Don't access needs_limm
 630         before testing opcode != NULL.
 631
 632 2020-03-22  Alan Modra  <amodra@gmail.com>
 633
 634         * ns32k-dis.c (print_insn_arg): Update comment.
 635         (print_insn_ns32k): Reduce size of index_offset array, and
 636         initialize, passing -1 to print_insn_arg for args that are not
 637         an index.  Don't exit arg loop early.  Abort on bad arg number.
 638
 639 2020-03-22  Alan Modra  <amodra@gmail.com>
 640
 641         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 642         * s12z-opc.c: Formatting.
 643         (operands_f): Return an int.
 644         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 645         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 646         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 647         (exg_sex_discrim): Likewise.
 648         (create_immediate_operand, create_bitfield_operand),
 649         (create_register_operand_with_size, create_register_all_operand),
 650         (create_register_all16_operand, create_simple_memory_operand),
 651         (create_memory_operand, create_memory_auto_operand): Don't
 652         segfault on malloc failure.
 653         (z_ext24_decode): Return an int status, negative on fail, zero
 654         on success.
 655         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 656         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 657         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 658         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 659         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 660         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 661         (loop_primitive_decode, shift_decode, psh_pul_decode),
 662         (bit_field_decode): Similarly.
 663         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 664         to return value, update callers.
 665         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 666         Don't segfault on NULL operand.
 667         (decode_operation): Return OP_INVALID on first fail.
 668         (decode_s12z): Check all reads, returning -1 on fail.
 669
 670 2020-03-20  Alan Modra  <amodra@gmail.com>
 671
 672         * metag-dis.c (print_insn_metag): Don't ignore status from
 673         read_memory_func.
 674
 675 2020-03-20  Alan Modra  <amodra@gmail.com>
 676
 677         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 678         Initialize parts of buffer not written when handling a possible
 679         2-byte insn at end of section.  Don't attempt decoding of such
 680         an insn by the 4-byte machinery.
 681
 682 2020-03-20  Alan Modra  <amodra@gmail.com>
 683
 684         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 685         partially filled buffer.  Prevent lookup of 4-byte insns when
 686         only VLE 2-byte insns are possible due to section size.  Print
 687         ".word" rather than ".long" for 2-byte leftovers.
 688
 689 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 690
 691         PR 25641
 692         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 693
 694 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 695
 696         * i386-dis.c (X86_64_0D): Rename to ...
 697         (X86_64_0E): ... this.
 698
 699 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 700
 701         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 702         * Makefile.in: Regenerated.
 703
 704 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 705
 706         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 707         3-operand pseudos.
 708         * i386-tbl.h: Re-generate.
 709
 710 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 711
 712         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 713         vprot*, vpsha*, and vpshl*.
 714         * i386-tbl.h: Re-generate.
 715
 716 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 717
 718         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 719         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 720         * i386-tbl.h: Re-generate.
 721
 722 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 723
 724         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 725         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 726         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 727         * i386-tbl.h: Re-generate.
 728
 729 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 730
 731         * i386-gen.c (struct template_arg, struct template_instance,
 732         struct template_param, struct template, templates,
 733         parse_template, expand_templates): New.
 734         (process_i386_opcodes): Various local variables moved to
 735         expand_templates. Call parse_template and expand_templates.
 736         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 737         * i386-tbl.h: Re-generate.
 738
 739 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 740
 741         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 742         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 743         register and memory source templates. Replace VexW= by VexW*
 744         where applicable.
 745         * i386-tbl.h: Re-generate.
 746
 747 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 748
 749         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 750         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 751         * i386-tbl.h: Re-generate.
 752
 753 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 754
 755         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 756         * i386-tbl.h: Re-generate.
 757
 758 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 759
 760         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 761         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 762         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 763         VexW0 on SSE2AVX variants.
 764         (vmovq): Drop NoRex64 from XMM/XMM variants.
 765         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 766         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 767         applicable use VexW0.
 768         * i386-tbl.h: Re-generate.
 769
 770 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 771
 772         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 773         * i386-opc.h (Rex64): Delete.
 774         (struct i386_opcode_modifier): Remove rex64 field.
 775         * i386-opc.tbl (crc32): Drop Rex64.
 776         Replace Rex64 with Size64 everywhere else.
 777         * i386-tbl.h: Re-generate.
 778
 779 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 780
 781         * i386-dis.c (OP_E_memory): Exclude recording of used address
 782         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 783         addressed memory operands for MPX insns.
 784
 785 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 786
 787         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 788         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 789         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 790         (ptwrite): Split into non-64-bit and 64-bit forms.
 791         * i386-tbl.h: Re-generate.
 792
 793 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 794
 795         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 796         template.
 797         * i386-tbl.h: Re-generate.
 798
 799 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 800
 801         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 802         (prefix_table): Move vmmcall here. Add vmgexit.
 803         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 804         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 805         (cpu_flags): Add CpuSEV_ES entry.
 806         * i386-opc.h (CpuSEV_ES): New.
 807         (union i386_cpu_flags): Add cpusev_es field.
 808         * i386-opc.tbl (vmgexit): New.
 809         * i386-init.h, i386-tbl.h: Re-generate.
 810
 811 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 812
 813         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 814         with MnemonicSize.
 815         * i386-opc.h (IGNORESIZE): New.
 816         (DEFAULTSIZE): Likewise.
 817         (IgnoreSize): Removed.
 818         (DefaultSize): Likewise.
 819         (MnemonicSize): New.
 820         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 821         mnemonicsize.
 822         * i386-opc.tbl (IgnoreSize): New.
 823         (DefaultSize): Likewise.
 824         * i386-tbl.h: Regenerated.
 825
 826 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 827
 828         PR 25627
 829         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 830         instructions.
 831
 832 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 833
 834         PR gas/25622
 835         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 836         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 837         * i386-tbl.h: Regenerated.
 838
 839 2020-02-26  Alan Modra  <amodra@gmail.com>
 840
 841         * aarch64-asm.c: Indent labels correctly.
 842         * aarch64-dis.c: Likewise.
 843         * aarch64-gen.c: Likewise.
 844         * aarch64-opc.c: Likewise.
 845         * alpha-dis.c: Likewise.
 846         * i386-dis.c: Likewise.
 847         * nds32-asm.c: Likewise.
 848         * nfp-dis.c: Likewise.
 849         * visium-dis.c: Likewise.
 850
 851 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 852
 853         * arc-regs.h (int_vector_base): Make it available for all ARC
 854         CPUs.
 855
 856 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 857
 858         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 859         changed.
 860
 861 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 862
 863         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 864         c.mv/c.li if rs1 is zero.
 865
 866 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 867
 868         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 869         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 870         CPU_POPCNT_FLAGS.
 871         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 872         * i386-opc.h (CpuABM): Removed.
 873         (CpuPOPCNT): New.
 874         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 875         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 876         popcnt.  Remove CpuABM from lzcnt.
 877         * i386-init.h: Regenerated.
 878         * i386-tbl.h: Likewise.
 879
 880 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 881
 882         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 883         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 884         VexW1 instead of open-coding them.
 885         * i386-tbl.h: Re-generate.
 886
 887 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 888
 889         * i386-opc.tbl (AddrPrefixOpReg): Define.
 890         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 891         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 892         templates. Drop NoRex64.
 893         * i386-tbl.h: Re-generate.
 894
 895 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 896
 897         PR gas/6518
 898         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 899         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 900         into Intel syntax instance (with Unpsecified) and AT&T one
 901         (without).
 902         (vcvtneps2bf16): Likewise, along with folding the two so far
 903         separate ones.
 904         * i386-tbl.h: Re-generate.
 905
 906 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 907
 908         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 909         CPU_ANY_SSE4A_FLAGS.
 910
 911 2020-02-17  Alan Modra  <amodra@gmail.com>
 912
 913         * i386-gen.c (cpu_flag_init): Correct last change.
 914
 915 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 916
 917         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 918         CPU_ANY_SSE4_FLAGS.
 919
 920 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 921
 922         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 923         (movzx): Likewise.
 924
 925 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 926
 927         PR gas/25438
 928         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 929         destination for Cpu64-only variant.
 930         (movzx): Fold patterns.
 931         * i386-tbl.h: Re-generate.
 932
 933 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 934
 935         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 936         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 937         CPU_ANY_SSE4_FLAGS entry.
 938         * i386-init.h: Re-generate.
 939
 940 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 941
 942         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 943         with Unspecified, making the present one AT&T syntax only.
 944         * i386-tbl.h: Re-generate.
 945
 946 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 947
 948         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 949         * i386-tbl.h: Re-generate.
 950
 951 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 952
 953         PR gas/24546
 954         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 955         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 956         Amd64 and Intel64 templates.
 957         (call, jmp): Likewise for far indirect variants. Dro
 958         Unspecified.
 959         * i386-tbl.h: Re-generate.
 960
 961 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 962
 963         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 964         * i386-opc.h (ShortForm): Delete.
 965         (struct i386_opcode_modifier): Remove shortform field.
 966         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 967         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 968         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 969         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 970         Drop ShortForm.
 971         * i386-tbl.h: Re-generate.
 972
 973 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 974
 975         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 976         fucompi): Drop ShortForm from operand-less templates.
 977         * i386-tbl.h: Re-generate.
 978
 979 2020-02-11  Alan Modra  <amodra@gmail.com>
 980
 981         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 982         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 983         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 984         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 985         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 986
 987 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 988
 989         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 990         (cde_opcodes): Add VCX* instructions.
 991
 992 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 993             Matthew Malcomson  <matthew.malcomson@arm.com>
 994
 995         * arm-dis.c (struct cdeopcode32): New.
 996         (CDE_OPCODE): New macro.
 997         (cde_opcodes): New disassembly table.
 998         (regnames): New option to table.
 999         (cde_coprocs): New global variable.
1000         (print_insn_cde): New
1001         (print_insn_thumb32): Use print_insn_cde.
1002         (parse_arm_disassembler_options): Parse coprocN args.
1003
1004 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
1005
1006         PR gas/25516
1007         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1008         with ISA64.
1009         * i386-opc.h (AMD64): Removed.
1010         (Intel64): Likewose.
1011         (AMD64): New.
1012         (INTEL64): Likewise.
1013         (INTEL64ONLY): Likewise.
1014         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1015         * i386-opc.tbl (Amd64): New.
1016         (Intel64): Likewise.
1017         (Intel64Only): Likewise.
1018         Replace AMD64 with Amd64.  Update sysenter/sysenter with
1019         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
1020         * i386-tbl.h: Regenerated.
1021
1022 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
1023
1024         PR 25469
1025         * z80-dis.c: Add support for GBZ80 opcodes.
1026
1027 2020-02-04  Alan Modra  <amodra@gmail.com>
1028
1029         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1030
1031 2020-02-03  Alan Modra  <amodra@gmail.com>
1032
1033         * m32c-ibld.c: Regenerate.
1034
1035 2020-02-01  Alan Modra  <amodra@gmail.com>
1036
1037         * frv-ibld.c: Regenerate.
1038
1039 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1040
1041         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1042         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1043         (OP_E_memory): Replace xmm_mdq_mode case label by
1044         vex_scalar_w_dq_mode one.
1045         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1046
1047 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1048
1049         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1050         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1051         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1052         (intel_operand_size): Drop vex_w_dq_mode case label.
1053
1054 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
1055
1056         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1057         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1058
1059 2020-01-30  Alan Modra  <amodra@gmail.com>
1060
1061         * m32c-ibld.c: Regenerate.
1062
1063 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
1064
1065         * bpf-opc.c: Regenerate.
1066
1067 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1068
1069         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1070         (dis386): Use them to replace C2/C3 table entries.
1071         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1072         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1073         ones. Use Size64 instead of DefaultSize on Intel64 ones.
1074         * i386-tbl.h: Re-generate.
1075
1076 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1077
1078         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1079         forms.
1080         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1081         DefaultSize.
1082         * i386-tbl.h: Re-generate.
1083
1084 2020-01-30  Alan Modra  <amodra@gmail.com>
1085
1086         * tic4x-dis.c (tic4x_dp): Make unsigned.
1087
1088 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
1089             Jan Beulich  <jbeulich@suse.com>
1090
1091         PR binutils/25445
1092         * i386-dis.c (MOVSXD_Fixup): New function.
1093         (movsxd_mode): New enum.
1094         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1095         (intel_operand_size): Handle movsxd_mode.
1096         (OP_E_register): Likewise.
1097         (OP_G): Likewise.
1098         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1099         register on movsxd.  Add movsxd with 16-bit destination register
1100         for AMD64 and Intel64 ISAs.
1101         * i386-tbl.h: Regenerated.
1102
1103 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
1104
1105         PR 25403
1106         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1107         * aarch64-asm-2.c: Regenerate
1108         * aarch64-dis-2.c: Likewise.
1109         * aarch64-opc-2.c: Likewise.
1110
1111 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1112
1113         * i386-opc.tbl (sysret): Drop DefaultSize.
1114         * i386-tbl.h: Re-generate.
1115
1116 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1117
1118         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1119         Dword.
1120         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1121         * i386-tbl.h: Re-generate.
1122
1123 2020-01-20  Nick Clifton  <nickc@redhat.com>
1124
1125         * po/de.po: Updated German translation.
1126         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1127         * po/uk.po: Updated Ukranian translation.
1128
1129 2020-01-20  Alan Modra  <amodra@gmail.com>
1130
1131         * hppa-dis.c (fput_const): Remove useless cast.
1132
1133 2020-01-20  Alan Modra  <amodra@gmail.com>
1134
1135         * arm-dis.c (print_insn_arm): Wrap 'T' value.
1136
1137 2020-01-18  Nick Clifton  <nickc@redhat.com>
1138
1139         * configure: Regenerate.
1140         * po/opcodes.pot: Regenerate.
1141
1142 2020-01-18  Nick Clifton  <nickc@redhat.com>
1143
1144         Binutils 2.34 branch created.
1145
1146 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
1147
1148         * opintl.h: Fix spelling error (seperate).
1149
1150 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
1151
1152         * i386-opc.tbl: Add {vex} pseudo prefix.
1153         * i386-tbl.h: Regenerated.
1154
1155 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1156
1157         PR 25376
1158         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1159         (neon_opcodes): Likewise.
1160         (select_arm_features): Make sure we enable MVE bits when selecting
1161         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
1162         any architecture.
1163
1164 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1165
1166         * i386-opc.tbl: Drop stale comment from XOP section.
1167
1168 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1169
1170         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1171         (extractps): Add VexWIG to SSE2AVX forms.
1172         * i386-tbl.h: Re-generate.
1173
1174 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1175
1176         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1177         Size64 from and use VexW1 on SSE2AVX forms.
1178         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1179         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1180         * i386-tbl.h: Re-generate.
1181
1182 2020-01-15  Alan Modra  <amodra@gmail.com>
1183
1184         * tic4x-dis.c (tic4x_version): Make unsigned long.
1185         (optab, optab_special, registernames): New file scope vars.
1186         (tic4x_print_register): Set up registernames rather than
1187         malloc'd registertable.
1188         (tic4x_disassemble): Delete optable and optable_special.  Use
1189         optab and optab_special instead.  Throw away old optab,
1190         optab_special and registernames when info->mach changes.
1191
1192 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
1193
1194         PR 25377
1195         * z80-dis.c (suffix): Use .db instruction to generate double
1196         prefix.
1197
1198 2020-01-14  Alan Modra  <amodra@gmail.com>
1199
1200         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
1201         values to unsigned before shifting.
1202
1203 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
1204
1205         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1206         flow instructions.
1207         (print_insn_thumb16, print_insn_thumb32): Likewise.
1208         (print_insn): Initialize the insn info.
1209         * i386-dis.c (print_insn): Initialize the insn info fields, and
1210         detect jumps.
1211
1212 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1213
1214         * arc-opc.c (C_NE): Make it required.
1215
1216 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1217
1218         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1219         reserved register name.
1220
1221 2020-01-13  Alan Modra  <amodra@gmail.com>
1222
1223         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1224         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1225
1226 2020-01-13  Alan Modra  <amodra@gmail.com>
1227
1228         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
1229         result of wasm_read_leb128 in a uint64_t and check that bits
1230         are not lost when copying to other locals.  Use uint32_t for
1231         most locals.  Use PRId64 when printing int64_t.
1232
1233 2020-01-13  Alan Modra  <amodra@gmail.com>
1234
1235         * score-dis.c: Formatting.
1236         * score7-dis.c: Formatting.
1237
1238 2020-01-13  Alan Modra  <amodra@gmail.com>
1239
1240         * score-dis.c (print_insn_score48): Use unsigned variables for
1241         unsigned values.  Don't left shift negative values.
1242         (print_insn_score32): Likewise.
1243         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1244
1245 2020-01-13  Alan Modra  <amodra@gmail.com>
1246
1247         * tic4x-dis.c (tic4x_print_register): Remove dead code.
1248
1249 2020-01-13  Alan Modra  <amodra@gmail.com>
1250
1251         * fr30-ibld.c: Regenerate.
1252
1253 2020-01-13  Alan Modra  <amodra@gmail.com>
1254
1255         * xgate-dis.c (print_insn): Don't left shift signed value.
1256         (ripBits): Formatting, use 1u.
1257
1258 2020-01-10  Alan Modra  <amodra@gmail.com>
1259
1260         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1261         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
1262
1263 2020-01-10  Alan Modra  <amodra@gmail.com>
1264
1265         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1266         and XRREG value earlier to avoid a shift with negative exponent.
1267         * m10200-dis.c (disassemble): Similarly.
1268
1269 2020-01-09  Nick Clifton  <nickc@redhat.com>
1270
1271         PR 25224
1272         * z80-dis.c (ld_ii_ii): Use correct cast.
1273
1274 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1275
1276         PR 25224
1277         * z80-dis.c (ld_ii_ii): Use character constant when checking
1278         opcode byte value.
1279
1280 2020-01-09  Jan Beulich  <jbeulich@suse.com>
1281
1282         * i386-dis.c (SEP_Fixup): New.
1283         (SEP): Define.
1284         (dis386_twobyte): Use it for sysenter/sysexit.
1285         (enum x86_64_isa): Change amd64 enumerator to value 1.
1286         (OP_J): Compare isa64 against intel64 instead of amd64.
1287         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1288         forms.
1289         * i386-tbl.h: Re-generate.
1290
1291 2020-01-08  Alan Modra  <amodra@gmail.com>
1292
1293         * z8k-dis.c: Include libiberty.h
1294         (instr_data_s): Make max_fetched unsigned.
1295         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1296         Don't exceed byte_info bounds.
1297         (output_instr): Make num_bytes unsigned.
1298         (unpack_instr): Likewise for nibl_count and loop.
1299         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1300         idx unsigned.
1301         * z8k-opc.h: Regenerate.
1302
1303 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
1304
1305         * arc-tbl.h (llock): Use 'LLOCK' as class.
1306         (llockd): Likewise.
1307         (scond): Use 'SCOND' as class.
1308         (scondd): Likewise.
1309         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1310         (scondd): Likewise.
1311
1312 2020-01-06  Alan Modra  <amodra@gmail.com>
1313
1314         * m32c-ibld.c: Regenerate.
1315
1316 2020-01-06  Alan Modra  <amodra@gmail.com>
1317
1318         PR 25344
1319         * z80-dis.c (suffix): Don't use a local struct buffer copy.
1320         Peek at next byte to prevent recursion on repeated prefix bytes.
1321         Ensure uninitialised "mybuf" is not accessed.
1322         (print_insn_z80): Don't zero n_fetch and n_used here,..
1323         (print_insn_z80_buf): ..do it here instead.
1324
1325 2020-01-04  Alan Modra  <amodra@gmail.com>
1326
1327         * m32r-ibld.c: Regenerate.
1328
1329 2020-01-04  Alan Modra  <amodra@gmail.com>
1330
1331         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1332
1333 2020-01-04  Alan Modra  <amodra@gmail.com>
1334
1335         * crx-dis.c (match_opcode): Avoid shift left of signed value.
1336
1337 2020-01-04  Alan Modra  <amodra@gmail.com>
1338
1339         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1340
1341 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1342
1343         * aarch64-tbl.h (aarch64_opcode_table): Use
1344         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1345
1346 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1347
1348         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1349         forms of SUDOT and USDOT.
1350
1351 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1352
1353         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1354         uzip{1,2}.
1355         * opcodes/aarch64-dis-2.c: Re-generate.
1356
1357 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1358
1359         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1360         FMMLA encoding.
1361         * opcodes/aarch64-dis-2.c: Re-generate.
1362
1363 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
1364
1365         * z80-dis.c: Add support for eZ80 and Z80 instructions.
1366
1367 2020-01-01  Alan Modra  <amodra@gmail.com>
1368
1369         Update year range in copyright notice of all files.
1370
1371 For older changes see ChangeLog-2019
1372 \f
1373 Copyright (C) 2020 Free Software Foundation, Inc.
1374
1375 Copying and distribution of this file, with or without modification,
1376 are permitted in any medium without royalty provided the copyright
1377 notice and this notice are preserved.
1378
1379 Local Variables:
1380 mode: change-log
1381 left-margin: 8
1382 fill-column: 74
1383 version-control: never
1384 End: