opcodes/ChangeLog

   1 2022-10-31  Yoshinori Sato  <ysato@users.sourceforge.jp>
   2
   3         * rx-decode.opc: Switch arguments of the MVTACGU insn.
   4         * rx-decode.c: Regenerate.
   5
   6 2022-09-22  Yoshinori Sato  <ysato@users.sourceforge.jp>
   7
   8         * sh-dis.c (print_insn_sh): Enforce bit7 of LDC Rm,Rn_BANK and STC
   9         Rm_BANK,Rn is always 1.
  10
  11 2022-07-21  Peter Bergner  <bergner@linux.ibm.com>
  12
  13         * ppc-opc.c (XACC_MASK, XX3ACC_MASK): New defines.
  14         (P_GER_MASK, xxmfacc, xxmtacc, xxsetaccz, xvi8ger4pp, xvi8ger4,
  15         xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger, xvi4ger8pp, xvi4ger8,
  16         xvi16ger2spp, xvi16ger2s, xvbf16ger2pp, xvbf16ger2, xvf64gerpp,
  17         xvf64ger, xvi16ger2, xvf16ger2np, xvf32gernp, xvi8ger4spp, xvi16ger2pp,
  18         xvbf16ger2np, xvf64gernp, xvf16ger2pn, xvf32gerpn, xvbf16ger2pn,
  19         xvf64gerpn, xvf16ger2nn, xvf32gernn, xvbf16ger2nn, xvf64gernn: Use them.
  20
  21 2022-07-18  Claudiu Zissulescu  <claziss@synopsys.com>
  22
  23         * disassemble.c (disassemble_init_for_target): Set
  24         created_styled_output for ARC based targets.
  25         * arc-dis.c (find_format_from_table): Use fprintf_styled_ftype
  26         instead of fprintf_ftype throughout.
  27         (find_format): Likewise.
  28         (print_flags): Likewise.
  29         (print_insn_arc): Likewise.
  30
  31 2022-07-08  Nick Clifton  <nickc@redhat.com>
  32
  33         * 2.39 branch created.
  34
  35 2022-07-04  Marcus Nilsson  <brainbomb@gmail.com>
  36
  37         * disassemble.c: (disassemble_init_for_target): Set
  38         created_styled_output for AVR based targets.
  39         * avr-dis.c: (print_insn_avr): Use fprintf_styled_ftype
  40         instead of fprintf_ftype throughout.
  41         (avr_operand): Pass in and fill disassembler_style when
  42         parsing operands.
  43
  44 2022-04-07  Andreas Krebbel  <krebbel@linux.ibm.com>
  45
  46         * s390-mkopc.c (main): Enable z16 as CPU string in the opcode
  47         table.
  48
  49 2022-03-16  Simon Marchi  <simon.marchi@efficios.com>
  50
  51         * configure.ac: Handle bfd_amdgcn_arch.
  52         * configure: Re-generate.
  53
  54 2022-03-06  Sagar Patel  <sagarmp@cs.unc.edu>
  55             Maciej W. Rozycki  <macro@orcam.me.uk>
  56
  57         * mips-opc.c (mips_builtin_opcodes): Fix INSN2_ALIAS annotation
  58         for "bal", "beqz", "beqzl", "bnez" and "bnezl" instructions.
  59         * micromips-opc.c (micromips_opcodes): Likewise for "beqz" and
  60         "bnez" instructions.
  61
  62 2022-02-17  Nick Clifton  <nickc@redhat.com>
  63
  64         * po/sr.po: Updated Serbian translation.
  65
  66 2022-02-14  Sergei Trofimovich  <siarheit@google.com>
  67
  68         * microblaze-opcm.h: Renamed 'fsqrt' to 'microblaze_fsqrt'.
  69         * microblaze-opc.h: Follow 'fsqrt' rename.
  70
  71 2022-01-24  Nick Clifton  <nickc@redhat.com>
  72
  73         * po/ro.po: Updated Romanian translation.
  74         * po/uk.po: Updated Ukranian translation.
  75
  76 2022-01-22  Nick Clifton  <nickc@redhat.com>
  77
  78         * configure: Regenerate.
  79         * po/opcodes.pot: Regenerate.
  80
  81 2022-01-22  Nick Clifton  <nickc@redhat.com>
  82
  83         * 2.38 release branch created.
  84
  85 2022-01-17  Nick Clifton  <nickc@redhat.com>
  86
  87         * Makefile.in: Regenerate.
  88         * po/opcodes.pot: Regenerate.
  89
  90 2021-12-02  Marcus Nilsson  <brainbomb@gmail.com>
  91
  92         * avr-dis.c (avr_operand); Pass in disassemble_info and fill
  93         in insn_type on branching instructions.
  94
  95 2021-11-25  Andrew Burgess  <aburgess@redhat.com>
  96             Simon Cook  <simon.cook@embecosm.com>
  97
  98         * riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
  99         (riscv_options): New static global.
 100         (disassembler_options_riscv): New function.
 101         (print_riscv_disassembler_options): Rewrite to use
 102         disassembler_options_riscv.
 103
 104 2021-11-25  Nick Clifton  <nickc@redhat.com>
 105
 106         PR 28614
 107         * aarch64-asm.c: Replace assert(0) with real code.
 108         * aarch64-dis.c: Likewise.
 109         * aarch64-opc.c: Likewise.
 110
 111 2021-11-25  Nick Clifton  <nickc@redhat.com>
 112
 113         * po/fr.po; Updated French translation.
 114
 115 2021-10-27  Maciej W. Rozycki  <macro@embecosm.com>
 116
 117         * Makefile.am: Remove obsolete comment.
 118         * configure.ac: Refer `libbfd.la' to link shared BFD library
 119         except for Cygwin.
 120         * Makefile.in: Regenerate.
 121         * configure: Regenerate.
 122
 123 2021-09-27  Nick Alcock  <nick.alcock@oracle.com>
 124
 125         * configure: Regenerate.
 126
 127 2021-09-25  Peter Bergner  <bergner@linux.ibm.com>
 128
 129         * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
 130         on POWER5 and later.
 131
 132 2021-09-20  Andrew Burgess  <andrew.burgess@embecosm.com>
 133
 134         * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
 135         before an unknown instruction, '%d' is replaced with the
 136         instruction length.
 137
 138 2021-09-02  Nick Clifton  <nickc@redhat.com>
 139
 140         PR 28292
 141         * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
 142         of BFD_RELOC_16.
 143
 144 2021-08-17  Shahab Vahedi <shahab@synopsys.com>
 145
 146         * arc-regs.h (DEF): Fix the register numbers.
 147
 148 2021-08-10  Nick Clifton  <nickc@redhat.com>
 149
 150         * po/sr.po: Updated Serbian translation.
 151
 152 2021-07-26  Chenghua Xu  <xuchenghua@loongson.cn>
 153
 154         * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
 155
 156 2021-06-07  Andreas Krebbel  <krebbel@linux.ibm.com>
 157
 158         * s390-opc.txt: Add qpaci.
 159
 160 2021-07-03  Nick Clifton  <nickc@redhat.com>
 161
 162         * configure: Regenerate.
 163         * po/opcodes.pot: Regenerate.
 164
 165 2021-07-03  Nick Clifton  <nickc@redhat.com>
 166
 167         * 2.37 release branch created.
 168
 169 2021-07-02  Alan Modra  <amodra@gmail.com>
 170
 171         * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
 172         (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
 173         (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
 174         (nds32_opcodes, nds32_operand_fields, nds32_keywords),
 175         (nds32_keyword_gpr): Move declarations to..
 176         * nds32-asm.h: ..here, constifying to match definitions.
 177
 178 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 179
 180         * Makefile.am (GUILE): New variable.
 181         (CGEN): Use $(GUILE).
 182         * Makefile.in: Regenerate.
 183
 184 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 185
 186         * mep-asm.c (macros): Mark static & const.
 187         (lookup_macro): Change return & m to const.
 188         (expand_macro): Change mac to const.
 189         (expand_string): Change pmacro to const.
 190
 191 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 192
 193         * nds32-asm.c (operand_fields): Rename to ...
 194         (nds32_operand_fields): ... this.
 195         (keyword_gpr): Rename to ...
 196         (nds32_keyword_gpr): ... this.
 197         (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
 198         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
 199         keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
 200         keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
 201         keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
 202         Mark static.
 203         (keywords): Rename to ...
 204         (nds32_keywords): ... this.
 205         * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
 206         keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
 207
 208 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 209
 210         * z80-dis.c (opc_ed): Make const.
 211         (pref_ed): Make p const.
 212
 213 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 214
 215         * microblaze-dis.c (get_field_special): Make op const.
 216         (read_insn_microblaze): Make opr & op const.  Rename opcodes to
 217         microblaze_opcodes.
 218         (print_insn_microblaze): Make op & pop const.
 219         (get_insn_microblaze): Make op const.  Rename opcodes to
 220         microblaze_opcodes.
 221         (microblaze_get_target_address): Likewise.
 222         * microblaze-opc.h (struct op_code_struct): Make const.
 223         Rename opcodes to microblaze_opcodes.
 224
 225 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 226
 227         * aarch64-gen.c (aarch64_opcode_table): Add const.
 228         * aarch64-tbl.h (aarch64_opcode_table): Likewise.
 229
 230 2021-06-22  Andrew Burgess  <andrew.burgess@embecosm.com>
 231
 232         * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
 233         available.
 234
 235 2021-06-22  Alan Modra  <amodra@gmail.com>
 236
 237         * pj-dis.c (print_insn_pj): Don't print trailing tab.  Do
 238         print separator for pcrel insns.
 239
 240 2021-06-19  Alan Modra  <amodra@gmail.com>
 241
 242         * vax-dis.c (print_insn_vax): Avoid pointer overflow.
 243
 244 2021-06-19  Alan Modra  <amodra@gmail.com>
 245
 246         * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
 247         entire buffer.
 248
 249 2021-06-17  Alan Modra  <amodra@gmail.com>
 250
 251         * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
 252         in table.
 253
 254 2021-06-03  Alan Modra  <amodra@gmail.com>
 255
 256         PR 1202
 257         * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
 258         Use unsigned int for inst.
 259
 260 2021-06-02  Shahab Vahedi  <shahab@synopsys.com>
 261
 262         * arc-dis.c (arc_option_arg_t): New enumeration.
 263         (arc_options): New variable.
 264         (disassembler_options_arc): New function.
 265         (print_arc_disassembler_options): Reimplement in terms of
 266         "disassembler_options_arc".
 267
 268 2021-05-29  Alan Modra  <amodra@gmail.com>
 269
 270         * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
 271         Don't special case PPC_OPCODE_RAW.
 272         (lookup_prefix): Likewise.
 273         (lookup_vle, lookup_spe2): Similarly.  Add dialect parameter and..
 274         (print_insn_powerpc): ..update caller.
 275         * ppc-opc.c (EXT): Define.
 276         (powerpc_opcodes): Mark extended mnemonics with EXT.
 277         (prefix_opcodes, vle_opcodes): Likewise.
 278         (XISEL, XISEL_MASK): Add cr field and simplify.
 279         (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
 280         all isel variants to where the base mnemonic belongs.  Sort dstt,
 281         dststt and dssall.
 282
 283 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 284
 285         * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
 286         COP3 opcode instructions.
 287
 288 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 289
 290         * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
 291         "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
 292         "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
 293         "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
 294         "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
 295         "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
 296         "cop2", and "cop3" entries.
 297
 298 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 299
 300         * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
 301         entries and associated comments.
 302
 303 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 304
 305         * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
 306         of "c0".
 307
 308 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 309
 310         * mips-dis.c (mips_cp1_names_mips): New variable.
 311         (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
 312         for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
 313         "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
 314         "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
 315         "r12000", "r14000", "r16000", "mips5", "loongson2e", and
 316         "loongson2f".
 317
 318 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 319
 320         * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
 321         handling code over to...
 322         <OP_REG_CONTROL>: ... this new case.
 323         * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
 324         (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
 325         "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
 326         replacing the `G' operand code with `g'.  Update "cftc1" and
 327         "cftc2" entries replacing the `E' operand code with `y'.
 328         * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
 329         (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
 330         entries replacing the `G' operand code with `g'.
 331
 332 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 333
 334         * mips-dis.c (mips_cp0_names_r3900): New variable.
 335         (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
 336         for "r3900".
 337
 338 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 339
 340         * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
 341         and "mtthc2" to using the `G' rather than `g' operand code for
 342         the coprocessor control register referred.
 343
 344 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 345
 346         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
 347         entries with each other.
 348
 349 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
 350
 351         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
 352
 353 2021-05-25  Alan Modra  <amodra@gmail.com>
 354
 355         * cris-desc.c: Regenerate.
 356         * cris-desc.h: Regenerate.
 357         * cris-opc.h: Regenerate.
 358         * po/POTFILES.in: Regenerate.
 359
 360 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
 361
 362         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
 363         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
 364         (CGEN_CPUS): Add cris.
 365         (CRIS_DEPS): Define.
 366         (stamp-cris): New rule.
 367         * cgen.sh: Handle desc action.
 368         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
 369         * Makefile.in, configure: Regenerate.
 370
 371 2021-05-18  Job Noorman  <mtvec@pm.me>
 372
 373         PR 27814
 374         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
 375         the elf objects.
 376
 377 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
 378
 379         * arm-dis.c (mve_opcodes): Fix disassembly of
 380         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
 381         (is_mve_encoding_conflict): MVE vector loads should not match
 382         when P = W = 0.
 383         (is_mve_unpredictable): It's not unpredictable to use the same
 384         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
 385
 386 2021-05-11  Nick Clifton  <nickc@redhat.com>
 387
 388         PR 27840
 389         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
 390         the end of the code buffer.
 391
 392 2021-05-06  Stafford Horne  <shorne@gmail.com>
 393
 394         PR 21464
 395         * or1k-asm.c: Regenerate.
 396
 397 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
 398
 399         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
 400         info->insn_info_valid.
 401
 402 2021-04-26  Jan Beulich  <jbeulich@suse.com>
 403
 404         * i386-opc.tbl (lea): Add Optimize.
 405         * opcodes/i386-tbl.h: Re-generate.
 406
 407 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 408
 409         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
 410         of l32r fetch and display referenced literal value.
 411
 412 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 413
 414         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
 415         to 4 for literal disassembly.
 416
 417 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 418
 419         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
 420         for TLBI instruction.
 421
 422 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 423
 424         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
 425         DC instruction.
 426
 427 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 428
 429         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
 430         "qualifier".
 431         (convert_mov_to_movewide): Add initializer for "value".
 432
 433 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 434
 435         * aarch64-opc.c: Add RME system registers.
 436
 437 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 438
 439         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
 440         "addi d,CV,z" to "c.mv d,CV".
 441
 442 2021-04-12  Alan Modra  <amodra@gmail.com>
 443
 444         * configure.ac (--enable-checking): Add support.
 445         * config.in: Regenerate.
 446         * configure: Regenerate.
 447
 448 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 449
 450         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 451         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 452
 453 2021-04-09  Alan Modra  <amodra@gmail.com>
 454
 455         * ppc-dis.c (struct dis_private): Add "special".
 456         (POWERPC_DIALECT): Delete.  Replace uses with..
 457         (private_data): ..this.  New inline function.
 458         (disassemble_init_powerpc): Init "special" names.
 459         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 460         field of prefix instructions.
 461         (bsearch_reloc, print_got_plt): New functions.
 462         (print_insn_powerpc): For pcrel instructions, print target address
 463         and symbol if known, and decode plt and got loads too.
 464
 465 2021-04-08  Alan Modra  <amodra@gmail.com>
 466
 467         PR 27684
 468         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 469
 470 2021-04-08  Alan Modra  <amodra@gmail.com>
 471
 472         PR 27676
 473         * ppc-opc.c (DCBT_EO): Move earlier.
 474         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 475         (powerpc_operands): Add THCT and THDS entries.
 476         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 477
 478 2021-04-06  Alan Modra  <amodra@gmail.com>
 479
 480         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 481         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 482         symbol_at_address_func.
 483
 484 2021-04-05  Alan Modra  <amodra@gmail.com>
 485
 486         * configure.ac: Don't check for limits.h, string.h, strings.h or
 487         stdlib.h.
 488         (AC_ISC_POSIX): Don't invoke.
 489         * sysdep.h: Include stdlib.h and string.h unconditionally.
 490         * i386-opc.h: Include limits.h unconditionally.
 491         * wasm32-dis.c: Likewise.
 492         * cgen-opc.c: Don't include alloca-conf.h.
 493         * config.in: Regenerate.
 494         * configure: Regenerate.
 495
 496 2021-04-01  Martin Liska  <mliska@suse.cz>
 497
 498         * arm-dis.c (strneq): Remove strneq and use startswith.
 499         * cr16-dis.c (print_insn_cr16): Likewise.
 500         * score-dis.c (streq): Likewise.
 501         (strneq): Likewise.
 502         * score7-dis.c (strneq): Likewise.
 503
 504 2021-04-01  Alan Modra  <amodra@gmail.com>
 505
 506         PR 27675
 507         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 508
 509 2021-03-31  Alan Modra  <amodra@gmail.com>
 510
 511         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 512         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 513         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 514         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 515         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 516         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 517         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 518         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 519         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 520         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 521         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 522         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 523         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 524         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 525         and TRUE with true throughout.
 526
 527 2021-03-31  Alan Modra  <amodra@gmail.com>
 528
 529         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 530         * aarch64-dis.h: Likewise.
 531         * aarch64-opc.c: Likewise.
 532         * avr-dis.c: Likewise.
 533         * csky-dis.c: Likewise.
 534         * nds32-asm.c: Likewise.
 535         * nds32-dis.c: Likewise.
 536         * nfp-dis.c: Likewise.
 537         * riscv-dis.c: Likewise.
 538         * s12z-dis.c: Likewise.
 539         * wasm32-dis.c: Likewise.
 540
 541 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 542
 543         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 544         (i386_seg_prefixes): New.
 545         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 546         (i386_seg_prefixes): Declare.
 547
 548 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 549
 550         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 551
 552 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 553
 554         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 555         * i386-reg.tbl (st): Move down.
 556         (st(0)): Delete. Extend comment.
 557         * i386-tbl.h: Re-generate.
 558
 559 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 560
 561         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 562         (cmpsd): Move next to cmps.
 563         (movsd): Move next to movs.
 564         (cmpxchg16b): Move to separate section.
 565         (fisttp, fisttpll): Likewise.
 566         (monitor, mwait): Likewise.
 567         * i386-tbl.h: Re-generate.
 568
 569 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 570
 571         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 572         (vpsadbw): Add C.
 573         * i386-tbl.h: Re-generate.
 574
 575 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 576
 577         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 578         pclmul, gfni): New templates. Use them wherever possible. Move
 579         SSE4.1 pextrw into respective section.
 580         * i386-tbl.h: Re-generate.
 581
 582 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 583
 584         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 585         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 586         "length".
 587         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 588         Convert all of their uses to representation in opcode.
 589
 590 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 591
 592         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 593         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 594         value of None. Shrink operands to 3 bits.
 595
 596 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 597
 598         * i386-gen.c (process_i386_opcode_modifier): New parameter
 599         "space".
 600         (output_i386_opcode): New local variable "space". Adjust
 601         process_i386_opcode_modifier() invocation.
 602         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 603         invocation.
 604         * i386-tbl.h: Re-generate.
 605
 606 2021-03-29  Alan Modra  <amodra@gmail.com>
 607
 608         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 609         (fp_qualifier_p, get_data_pattern): Likewise.
 610         (aarch64_get_operand_modifier_from_value): Likewise.
 611         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 612         (operand_variant_qualifier_p): Likewise.
 613         (qualifier_value_in_range_constraint_p): Likewise.
 614         (aarch64_get_qualifier_esize): Likewise.
 615         (aarch64_get_qualifier_nelem): Likewise.
 616         (aarch64_get_qualifier_standard_value): Likewise.
 617         (get_lower_bound, get_upper_bound): Likewise.
 618         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 619         (aarch64_print_operand): Likewise.
 620         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 621         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 622         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 623         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 624         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 625         (print_insn_tic6x): Likewise.
 626
 627 2021-03-29  Alan Modra  <amodra@gmail.com>
 628
 629         * arc-dis.c (extract_operand_value): Correct NULL cast.
 630         * frv-opc.h: Regenerate.
 631
 632 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 633
 634         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 635         MMX form.
 636         * i386-tbl.h: Re-generate.
 637
 638 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 639
 640         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 641         immediate in br.n instruction.
 642
 643 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 644
 645         * i386-dis.c (XMGatherD, VexGatherD): New.
 646         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 647         (print_insn): Check masking for S/G insns.
 648         (OP_E_memory): New local variable check_gather. Extend mandatory
 649         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 650         Extend check for disallowed 16-bit addressing.
 651         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 652         if()s to switch(). Check register conflicts for (VEX-encoded)
 653         gathers. Drop no longer reachable cases.
 654         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 655         vgatherdp*.
 656
 657 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 658
 659         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 660         zeroing-masking without masking.
 661
 662 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 663
 664         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 665         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 666         single-operand forms as deprecated.
 667         * i386-tbl.h: Re-generate.
 668
 669 2021-03-25  Alan Modra  <amodra@gmail.com>
 670
 671         PR 27647
 672         * ppc-opc.c (XLOCB_MASK): Delete.
 673         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 674         XLBH_MASK.
 675         (powerpc_opcodes): Accept a BH field on all extended forms of
 676         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 677
 678 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 679
 680         * i386-gen.c (output_i386_opcode): Drop processing of
 681         opcode_length. Calculate length from base_opcode. Adjust prefix
 682         encoding determination.
 683         (process_i386_opcodes): Drop output of fake opcode_length.
 684         * i386-opc.h (struct insn_template): Drop opcode_length field.
 685         * i386-opc.tbl: Drop opcode length field from all templates.
 686         * i386-tbl.h: Re-generate.
 687
 688 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 689
 690         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 691         parameter "prefix". Drop local variable "regular_encoding".
 692         Record prefix setting / check for consistency.
 693         (output_i386_opcode): Parse opcode_length and base_opcode
 694         earlier. Derive prefix encoding. Drop no longer applicable
 695         consistency checking. Adjust process_i386_opcode_modifier()
 696         invocation.
 697         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 698         invocation.
 699         * i386-tbl.h: Re-generate.
 700
 701 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 702
 703         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 704         check.
 705         * i386-opc.h (Prefix_*): Move #define-s.
 706         * i386-opc.tbl: Move pseudo prefix enumerator values to
 707         extension opcode field. Introduce pseudopfx template.
 708         * i386-tbl.h: Re-generate.
 709
 710 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 711
 712         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 713         comment.
 714         * i386-tbl.h: Re-generate.
 715
 716 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 717
 718         * i386-opc.h (struct insn_template): Move cpu_flags field past
 719         opcode_modifier one.
 720         * i386-tbl.h: Re-generate.
 721
 722 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 723
 724         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 725         * i386-opc.h (OpcodeSpace): New enumerator.
 726         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 727         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 728         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 729         (struct i386_opcode_modifier): New field opcodespace. Shrink
 730         opcodeprefix field.
 731         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 732         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 733         OpcodePrefix uses.
 734         * i386-tbl.h: Re-generate.
 735
 736 2021-03-22  Martin Liska  <mliska@suse.cz>
 737
 738         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 739         * arc-dis.c (parse_option): Likewise.
 740         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 741         * cris-dis.c (print_with_operands): Likewise.
 742         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 743         * i386-dis.c (print_insn): Likewise.
 744         * ia64-gen.c (fetch_insn_class): Likewise.
 745         (parse_resource_users): Likewise.
 746         (in_iclass): Likewise.
 747         (lookup_specifier): Likewise.
 748         (insert_opcode_dependencies): Likewise.
 749         * mips-dis.c (parse_mips_ase_option): Likewise.
 750         (parse_mips_dis_option): Likewise.
 751         * s390-dis.c (disassemble_init_s390): Likewise.
 752         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 753
 754 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 755
 756         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 757
 758 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 759
 760         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 761         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 762
 763 2021-03-12  Alan Modra  <amodra@gmail.com>
 764
 765         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 766
 767 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 768
 769         * i386-dis.c (OP_XMM): Re-order checks.
 770
 771 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 772
 773         * i386-dis.c (putop): Drop need_vex check when also checking
 774         vex.evex.
 775         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 776         checking vex.b.
 777
 778 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 779
 780         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 781         checks. Move case label past broadcast check.
 782
 783 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 784
 785         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 786         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 787         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 788         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 789         EVEX_W_0F38C7_M_0_L_2): Delete.
 790         (REG_EVEX_0F38C7_M_0_L_2): New.
 791         (intel_operand_size): Handle VEX and EVEX the same for
 792         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 793         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 794         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 795         vex_vsib_q_w_d_mode uses.
 796         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 797         0F38A1, and 0F38A3 entries.
 798         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 799         entry.
 800         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 801         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 802         0F38A3 entries.
 803
 804 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 805
 806         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 807         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 808         MOD_VEX_0FXOP_09_12): Rename to ...
 809         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 810         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 811         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 812         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 813         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 814         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 815         (reg_table): Adjust comments.
 816         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 817         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 818         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 819         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 820         (vex_len_table): Adjust opcode 0A_12 entry.
 821         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 822         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 823         (rm_table): Move hreset entry.
 824
 825 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 826
 827         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 828         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 829         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 830         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 831         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 832         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 833         (get_valid_dis386): Also handle 512-bit vector length when
 834         vectoring into vex_len_table[].
 835         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 836         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 837         entries.
 838         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 839         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 840         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 841         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 842         entries.
 843
 844 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 845
 846         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 847         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 848         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 849         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 850         entries.
 851         * i386-dis-evex-len.h (evex_len_table): Likewise.
 852         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 853
 854 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 855
 856         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 857         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 858         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 859         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 860         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 861         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 862         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 863         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 864         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 865         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 866         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 867         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 868         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 869         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 870         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 871         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 872         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 873         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 874         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 875         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 876         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 877         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 878         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 879         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 880         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 881         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 882         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 883         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 884         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 885         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 886         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 887         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 888         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 889         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 890         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 891         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 892         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 893         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 894         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 895         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 896         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 897         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 898         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 899         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 900         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 901         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 902         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 903         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 904         EVEX_W_0F3A43_L_n): New.
 905         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 906         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 907         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 908         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 909         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 910         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 911         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 912         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 913         0F385B, 0F38C6, and 0F38C7 entries.
 914         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 915         0F38C6 and 0F38C7.
 916         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 917         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 918         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 919         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 920
 921 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 922
 923         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 924         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 925         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 926         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 927         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 928         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 929         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 930         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 931         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 932         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 933         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 934         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 935         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 936         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 937         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 938         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 939         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 940         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 941         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 942         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 943         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 944         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 945         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 946         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 947         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 948         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 949         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 950         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 951         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 952         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 953         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 954         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 955         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 956         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 957         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 958         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 959         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 960         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 961         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 962         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 963         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 964         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 965         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 966         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 967         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 968         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 969         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 970         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 971         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 972         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 973         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 974         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 975         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 976         VEX_W_0F99_P_2_LEN_0): Delete.
 977         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 978         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 979         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 980         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 981         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 982         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 983         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 984         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 985         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 986         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 987         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 988         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 989         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 990         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 991         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 992         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 993         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 994         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 995         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 996         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 997         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 998         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 999         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
1000         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
1001         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
1002         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
1003         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
1004         (prefix_table): No longer link to vex_len_table[] for opcodes
1005         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
1006         0F92, 0F93, 0F98, and 0F99.
1007         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
1008         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1009         0F98, and 0F99.
1010         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
1011         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1012         0F98, and 0F99.
1013         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
1014         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1015         0F98, and 0F99.
1016         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
1017         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1018         0F98, and 0F99.
1019
1020 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1021
1022         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
1023         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
1024         REG_VEX_0F73_M_0 respectively.
1025         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
1026         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
1027         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
1028         MOD_VEX_0F73_REG_7): Delete.
1029         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
1030         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
1031         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
1032         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
1033         PREFIX_VEX_0F3AF0_L_0 respectively.
1034         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
1035         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
1036         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
1037         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
1038         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
1039         VEX_LEN_0F38F7): New.
1040         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
1041         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
1042         0F72, and 0F73. No longer link to vex_len_table[] for opcode
1043         0F38F3.
1044         (prefix_table): No longer link to vex_len_table[] for opcodes
1045         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1046         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
1047         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
1048         0F38F6, 0F38F7, and 0F3AF0.
1049         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
1050         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1051         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
1052         0F73.
1053
1054 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1055
1056         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
1057         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
1058         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
1059         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
1060         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
1061         (MOD_0F71, MOD_0F72, MOD_0F73): New.
1062         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
1063         73.
1064         (reg_table): No longer link to mod_table[] for opcodes 0F71,
1065         0F72, and 0F73.
1066         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
1067         0F73.
1068
1069 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1070
1071         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
1072         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
1073         (reg_table): Don't link to mod_table[] where not needed. Add
1074         PREFIX_IGNORED to nop entries.
1075         (prefix_table): Replace PREFIX_OPCODE in nop entries.
1076         (mod_table): Add nop entries next to prefetch ones. Drop
1077         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
1078         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
1079         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
1080         PREFIX_OPCODE from endbr* entries.
1081         (get_valid_dis386): Also consider entry's name when zapping
1082         vindex.
1083         (print_insn): Handle PREFIX_IGNORED.
1084
1085 2021-03-09  Jan Beulich  <jbeulich@suse.com>
1086
1087         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
1088         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
1089         element.
1090         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
1091         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
1092         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
1093         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
1094         (struct i386_opcode_modifier): Delete notrackprefixok,
1095         islockable, hleprefixok, and repprefixok fields. Add prefixok
1096         field.
1097         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
1098         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
1099         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
1100         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
1101         Replace HLEPrefixOk.
1102         * opcodes/i386-tbl.h: Re-generate.
1103
1104 2021-03-09  Jan Beulich  <jbeulich@suse.com>
1105
1106         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
1107         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
1108         64-bit form.
1109         * opcodes/i386-tbl.h: Re-generate.
1110
1111 2021-03-03  Jan Beulich  <jbeulich@suse.com>
1112
1113         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
1114         for {} instead of {0}. Don't look for '0'.
1115         * i386-opc.tbl: Drop operand count field. Drop redundant operand
1116         size specifiers.
1117
1118 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
1119
1120         PR 27158
1121         * riscv-dis.c (print_insn_args): Updated encoding macros.
1122         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1123         (match_c_addi16sp): Updated encoding macros.
1124         (match_c_lui): Likewise.
1125         (match_c_lui_with_hint): Likewise.
1126         (match_c_addi4spn): Likewise.
1127         (match_c_slli): Likewise.
1128         (match_slli_as_c_slli): Likewise.
1129         (match_c_slli64): Likewise.
1130         (match_srxi_as_c_srxi): Likewise.
1131         (riscv_insn_types): Added .insn css/cl/cs.
1132
1133 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
1134
1135         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1136         (default_priv_spec): Updated type to riscv_spec_class.
1137         (parse_riscv_dis_option): Updated.
1138         * riscv-opc.c: Moved stuff and make the file tidy.
1139
1140 2021-02-17  Alan Modra  <amodra@gmail.com>
1141
1142         * wasm32-dis.c: Include limits.h.
1143         (CHAR_BIT): Provide backup define.
1144         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1145         Correct signed overflow checking.
1146
1147 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1148
1149         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1150         * i386-tbl.h: Re-generate.
1151
1152 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1153
1154         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1155         Oword.
1156         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1157
1158 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
1159
1160         * s390-mkopc.c (main): Accept arch14 as cpu string.
1161         * s390-opc.txt: Add new arch14 instructions.
1162
1163 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
1164
1165         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1166         favour of LIBINTL.
1167         * configure: Regenerated.
1168
1169 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
1170
1171         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1172         * tic54x-opc.c (regs): Rename to ...
1173         (tic54x_regs): ... this.
1174         (mmregs): Rename to ...
1175         (tic54x_mmregs): ... this.
1176         (condition_codes): Rename to ...
1177         (tic54x_condition_codes): ... this.
1178         (cc2_codes): Rename to ...
1179         (tic54x_cc2_codes): ... this.
1180         (cc3_codes): Rename to ...
1181         (tic54x_cc3_codes): ... this.
1182         (status_bits): Rename to ...
1183         (tic54x_status_bits): ... this.
1184         (misc_symbols): Rename to ...
1185         (tic54x_misc_symbols): ... this.
1186
1187 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
1188
1189         * riscv-opc.c (MASK_RVB_IMM): Removed.
1190         (riscv_opcodes): Removed zb* instructions.
1191         (riscv_ext_version_table): Removed versions for zb*.
1192
1193 2021-01-26  Alan Modra  <amodra@gmail.com>
1194
1195         * i386-gen.c (parse_template): Ensure entire template_instance
1196         is initialised.
1197
1198 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1199
1200         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1201         (riscv_fpr_names_abi): Likewise.
1202         (riscv_opcodes): Likewise.
1203         (riscv_insn_types): Likewise.
1204
1205 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1206
1207         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1208
1209 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1210
1211         * riscv-dis.c: Comments tidy and improvement.
1212         * riscv-opc.c: Likewise.
1213
1214 2021-01-13  Alan Modra  <amodra@gmail.com>
1215
1216         * Makefile.in: Regenerate.
1217
1218 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
1219
1220         PR binutils/26792
1221         * configure.ac: Use GNU_MAKE_JOBSERVER.
1222         * aclocal.m4: Regenerated.
1223         * configure: Likewise.
1224
1225 2021-01-12  Nick Clifton  <nickc@redhat.com>
1226
1227         * po/sr.po: Updated Serbian translation.
1228
1229 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
1230
1231         PR ld/27173
1232         * configure: Regenerated.
1233
1234 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1235
1236         * aarch64-asm-2.c: Regenerate.
1237         * aarch64-dis-2.c: Likewise.
1238         * aarch64-opc-2.c: Likewise.
1239         * aarch64-opc.c (aarch64_print_operand):
1240         Delete handling of AARCH64_OPND_CSRE_CSR.
1241         * aarch64-tbl.h (aarch64_feature_csre): Delete.
1242         (CSRE): Likewise.
1243         (_CSRE_INSN): Likewise.
1244         (aarch64_opcode_table): Delete csr.
1245
1246 2021-01-11  Nick Clifton  <nickc@redhat.com>
1247
1248         * po/de.po: Updated German translation.
1249         * po/fr.po: Updated French translation.
1250         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1251         * po/sv.po: Updated Swedish translation.
1252         * po/uk.po: Updated Ukranian translation.
1253
1254 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
1255
1256         * configure: Regenerated.
1257
1258 2021-01-09  Nick Clifton  <nickc@redhat.com>
1259
1260         * configure: Regenerate.
1261         * po/opcodes.pot: Regenerate.
1262
1263 2021-01-09  Nick Clifton  <nickc@redhat.com>
1264
1265         * 2.36 release branch crated.
1266
1267 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
1268
1269         * ppc-opc.c (insert_dw, (extract_dw): New functions.
1270         (DW, (XRC_MASK): Define.
1271         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1272
1273 2021-01-09  Alan Modra  <amodra@gmail.com>
1274
1275         * configure: Regenerate.
1276
1277 2021-01-08  Nick Clifton  <nickc@redhat.com>
1278
1279         * po/sv.po: Updated Swedish translation.
1280
1281 2021-01-08  Nick Clifton  <nickc@redhat.com>
1282
1283         PR 27129
1284         * aarch64-dis.c (determine_disassembling_preference): Move call to
1285         aarch64_match_operands_constraint outside of the assertion.
1286         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1287         Replace with a return of FALSE.
1288
1289         PR 27139
1290         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1291         core system register.
1292
1293 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
1294
1295         * configure: Regenerate.
1296
1297 2021-01-07  Nick Clifton  <nickc@redhat.com>
1298
1299         * po/fr.po: Updated French translation.
1300
1301 2021-01-07  Fredrik Noring  <noring@nocrew.org>
1302
1303         * m68k-opc.c (chkl): Change minimum architecture requirement to
1304         m68020.
1305
1306 2021-01-07  Philipp Tomsich  <prt@gnu.org>
1307
1308         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1309
1310 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
1311             Jim Wilson  <jimw@sifive.com>
1312             Andrew Waterman  <andrew@sifive.com>
1313             Maxim Blinov  <maxim.blinov@embecosm.com>
1314             Kito Cheng  <kito.cheng@sifive.com>
1315             Nelson Chu  <nelson.chu@sifive.com>
1316
1317         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1318         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1319
1320 2021-01-01  Alan Modra  <amodra@gmail.com>
1321
1322         Update year range in copyright notice of all files.
1323
1324 For older changes see ChangeLog-2020
1325 \f
1326 Copyright (C) 2021-2022 Free Software Foundation, Inc.
1327
1328 Copying and distribution of this file, with or without modification,
1329 are permitted in any medium without royalty provided the copyright
1330 notice and this notice are preserved.
1331
1332 Local Variables:
1333 mode: change-log
1334 left-margin: 8
1335 fill-column: 74
1336 version-control: never
1337 End: