opcodes/ChangeLog

   1 2022-01-22  Nick Clifton  <nickc@redhat.com>
   2
   3         * configure: Regenerate.
   4         * po/opcodes.pot: Regenerate.
   5
   6 2022-01-22  Nick Clifton  <nickc@redhat.com>
   7
   8         * 2.38 release branch created.
   9
  10 2022-01-17  Nick Clifton  <nickc@redhat.com>
  11
  12         * Makefile.in: Regenerate.
  13         * po/opcodes.pot: Regenerate.
  14
  15 2021-12-02  Marcus Nilsson  <brainbomb@gmail.com>
  16
  17         * avr-dis.c (avr_operand); Pass in disassemble_info and fill
  18         in insn_type on branching instructions.
  19
  20 2021-11-25  Andrew Burgess  <aburgess@redhat.com>
  21             Simon Cook  <simon.cook@embecosm.com>
  22
  23         * riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
  24         (riscv_options): New static global.
  25         (disassembler_options_riscv): New function.
  26         (print_riscv_disassembler_options): Rewrite to use
  27         disassembler_options_riscv.
  28
  29 2021-11-25  Nick Clifton  <nickc@redhat.com>
  30
  31         PR 28614
  32         * aarch64-asm.c: Replace assert(0) with real code.
  33         * aarch64-dis.c: Likewise.
  34         * aarch64-opc.c: Likewise.
  35
  36 2021-11-25  Nick Clifton  <nickc@redhat.com>
  37
  38         * po/fr.po; Updated French translation.
  39
  40 2021-10-27  Maciej W. Rozycki  <macro@embecosm.com>
  41
  42         * Makefile.am: Remove obsolete comment.
  43         * configure.ac: Refer `libbfd.la' to link shared BFD library
  44         except for Cygwin.
  45         * Makefile.in: Regenerate.
  46         * configure: Regenerate.
  47
  48 2021-09-27  Nick Alcock  <nick.alcock@oracle.com>
  49
  50         * configure: Regenerate.
  51
  52 2021-09-25  Peter Bergner  <bergner@linux.ibm.com>
  53
  54         * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
  55         on POWER5 and later.
  56
  57 2021-09-20  Andrew Burgess  <andrew.burgess@embecosm.com>
  58
  59         * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
  60         before an unknown instruction, '%d' is replaced with the
  61         instruction length.
  62
  63 2021-09-02  Nick Clifton  <nickc@redhat.com>
  64
  65         PR 28292
  66         * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
  67         of BFD_RELOC_16.
  68
  69 2021-08-17  Shahab Vahedi <shahab@synopsys.com>
  70
  71         * arc-regs.h (DEF): Fix the register numbers.
  72
  73 2021-08-10  Nick Clifton  <nickc@redhat.com>
  74
  75         * po/sr.po: Updated Serbian translation.
  76
  77 2021-07-26  Chenghua Xu  <xuchenghua@loongson.cn>
  78
  79         * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
  80
  81 2021-06-07  Andreas Krebbel  <krebbel@linux.ibm.com>
  82
  83         * s390-opc.txt: Add qpaci.
  84
  85 2021-07-03  Nick Clifton  <nickc@redhat.com>
  86
  87         * configure: Regenerate.
  88         * po/opcodes.pot: Regenerate.
  89
  90 2021-07-03  Nick Clifton  <nickc@redhat.com>
  91
  92         * 2.37 release branch created.
  93
  94 2021-07-02  Alan Modra  <amodra@gmail.com>
  95
  96         * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
  97         (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
  98         (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
  99         (nds32_opcodes, nds32_operand_fields, nds32_keywords),
 100         (nds32_keyword_gpr): Move declarations to..
 101         * nds32-asm.h: ..here, constifying to match definitions.
 102
 103 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 104
 105         * Makefile.am (GUILE): New variable.
 106         (CGEN): Use $(GUILE).
 107         * Makefile.in: Regenerate.
 108
 109 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 110
 111         * mep-asm.c (macros): Mark static & const.
 112         (lookup_macro): Change return & m to const.
 113         (expand_macro): Change mac to const.
 114         (expand_string): Change pmacro to const.
 115
 116 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 117
 118         * nds32-asm.c (operand_fields): Rename to ...
 119         (nds32_operand_fields): ... this.
 120         (keyword_gpr): Rename to ...
 121         (nds32_keyword_gpr): ... this.
 122         (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
 123         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
 124         keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
 125         keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
 126         keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
 127         Mark static.
 128         (keywords): Rename to ...
 129         (nds32_keywords): ... this.
 130         * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
 131         keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
 132
 133 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 134
 135         * z80-dis.c (opc_ed): Make const.
 136         (pref_ed): Make p const.
 137
 138 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 139
 140         * microblaze-dis.c (get_field_special): Make op const.
 141         (read_insn_microblaze): Make opr & op const.  Rename opcodes to
 142         microblaze_opcodes.
 143         (print_insn_microblaze): Make op & pop const.
 144         (get_insn_microblaze): Make op const.  Rename opcodes to
 145         microblaze_opcodes.
 146         (microblaze_get_target_address): Likewise.
 147         * microblaze-opc.h (struct op_code_struct): Make const.
 148         Rename opcodes to microblaze_opcodes.
 149
 150 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 151
 152         * aarch64-gen.c (aarch64_opcode_table): Add const.
 153         * aarch64-tbl.h (aarch64_opcode_table): Likewise.
 154
 155 2021-06-22  Andrew Burgess  <andrew.burgess@embecosm.com>
 156
 157         * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
 158         available.
 159
 160 2021-06-22  Alan Modra  <amodra@gmail.com>
 161
 162         * pj-dis.c (print_insn_pj): Don't print trailing tab.  Do
 163         print separator for pcrel insns.
 164
 165 2021-06-19  Alan Modra  <amodra@gmail.com>
 166
 167         * vax-dis.c (print_insn_vax): Avoid pointer overflow.
 168
 169 2021-06-19  Alan Modra  <amodra@gmail.com>
 170
 171         * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
 172         entire buffer.
 173
 174 2021-06-17  Alan Modra  <amodra@gmail.com>
 175
 176         * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
 177         in table.
 178
 179 2021-06-03  Alan Modra  <amodra@gmail.com>
 180
 181         PR 1202
 182         * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
 183         Use unsigned int for inst.
 184
 185 2021-06-02  Shahab Vahedi  <shahab@synopsys.com>
 186
 187         * arc-dis.c (arc_option_arg_t): New enumeration.
 188         (arc_options): New variable.
 189         (disassembler_options_arc): New function.
 190         (print_arc_disassembler_options): Reimplement in terms of
 191         "disassembler_options_arc".
 192
 193 2021-05-29  Alan Modra  <amodra@gmail.com>
 194
 195         * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
 196         Don't special case PPC_OPCODE_RAW.
 197         (lookup_prefix): Likewise.
 198         (lookup_vle, lookup_spe2): Similarly.  Add dialect parameter and..
 199         (print_insn_powerpc): ..update caller.
 200         * ppc-opc.c (EXT): Define.
 201         (powerpc_opcodes): Mark extended mnemonics with EXT.
 202         (prefix_opcodes, vle_opcodes): Likewise.
 203         (XISEL, XISEL_MASK): Add cr field and simplify.
 204         (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
 205         all isel variants to where the base mnemonic belongs.  Sort dstt,
 206         dststt and dssall.
 207
 208 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 209
 210         * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
 211         COP3 opcode instructions.
 212
 213 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 214
 215         * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
 216         "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
 217         "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
 218         "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
 219         "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
 220         "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
 221         "cop2", and "cop3" entries.
 222
 223 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 224
 225         * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
 226         entries and associated comments.
 227
 228 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 229
 230         * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
 231         of "c0".
 232
 233 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 234
 235         * mips-dis.c (mips_cp1_names_mips): New variable.
 236         (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
 237         for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
 238         "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
 239         "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
 240         "r12000", "r14000", "r16000", "mips5", "loongson2e", and
 241         "loongson2f".
 242
 243 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 244
 245         * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
 246         handling code over to...
 247         <OP_REG_CONTROL>: ... this new case.
 248         * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
 249         (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
 250         "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
 251         replacing the `G' operand code with `g'.  Update "cftc1" and
 252         "cftc2" entries replacing the `E' operand code with `y'.
 253         * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
 254         (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
 255         entries replacing the `G' operand code with `g'.
 256
 257 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 258
 259         * mips-dis.c (mips_cp0_names_r3900): New variable.
 260         (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
 261         for "r3900".
 262
 263 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 264
 265         * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
 266         and "mtthc2" to using the `G' rather than `g' operand code for
 267         the coprocessor control register referred.
 268
 269 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 270
 271         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
 272         entries with each other.
 273
 274 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
 275
 276         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
 277
 278 2021-05-25  Alan Modra  <amodra@gmail.com>
 279
 280         * cris-desc.c: Regenerate.
 281         * cris-desc.h: Regenerate.
 282         * cris-opc.h: Regenerate.
 283         * po/POTFILES.in: Regenerate.
 284
 285 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
 286
 287         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
 288         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
 289         (CGEN_CPUS): Add cris.
 290         (CRIS_DEPS): Define.
 291         (stamp-cris): New rule.
 292         * cgen.sh: Handle desc action.
 293         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
 294         * Makefile.in, configure: Regenerate.
 295
 296 2021-05-18  Job Noorman  <mtvec@pm.me>
 297
 298         PR 27814
 299         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
 300         the elf objects.
 301
 302 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
 303
 304         * arm-dis.c (mve_opcodes): Fix disassembly of
 305         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
 306         (is_mve_encoding_conflict): MVE vector loads should not match
 307         when P = W = 0.
 308         (is_mve_unpredictable): It's not unpredictable to use the same
 309         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
 310
 311 2021-05-11  Nick Clifton  <nickc@redhat.com>
 312
 313         PR 27840
 314         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
 315         the end of the code buffer.
 316
 317 2021-05-06  Stafford Horne  <shorne@gmail.com>
 318
 319         PR 21464
 320         * or1k-asm.c: Regenerate.
 321
 322 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
 323
 324         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
 325         info->insn_info_valid.
 326
 327 2021-04-26  Jan Beulich  <jbeulich@suse.com>
 328
 329         * i386-opc.tbl (lea): Add Optimize.
 330         * opcodes/i386-tbl.h: Re-generate.
 331
 332 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 333
 334         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
 335         of l32r fetch and display referenced literal value.
 336
 337 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 338
 339         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
 340         to 4 for literal disassembly.
 341
 342 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 343
 344         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
 345         for TLBI instruction.
 346
 347 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 348
 349         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
 350         DC instruction.
 351
 352 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 353
 354         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
 355         "qualifier".
 356         (convert_mov_to_movewide): Add initializer for "value".
 357
 358 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 359
 360         * aarch64-opc.c: Add RME system registers.
 361
 362 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 363
 364         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
 365         "addi d,CV,z" to "c.mv d,CV".
 366
 367 2021-04-12  Alan Modra  <amodra@gmail.com>
 368
 369         * configure.ac (--enable-checking): Add support.
 370         * config.in: Regenerate.
 371         * configure: Regenerate.
 372
 373 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 374
 375         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 376         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 377
 378 2021-04-09  Alan Modra  <amodra@gmail.com>
 379
 380         * ppc-dis.c (struct dis_private): Add "special".
 381         (POWERPC_DIALECT): Delete.  Replace uses with..
 382         (private_data): ..this.  New inline function.
 383         (disassemble_init_powerpc): Init "special" names.
 384         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 385         field of prefix instructions.
 386         (bsearch_reloc, print_got_plt): New functions.
 387         (print_insn_powerpc): For pcrel instructions, print target address
 388         and symbol if known, and decode plt and got loads too.
 389
 390 2021-04-08  Alan Modra  <amodra@gmail.com>
 391
 392         PR 27684
 393         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 394
 395 2021-04-08  Alan Modra  <amodra@gmail.com>
 396
 397         PR 27676
 398         * ppc-opc.c (DCBT_EO): Move earlier.
 399         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 400         (powerpc_operands): Add THCT and THDS entries.
 401         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 402
 403 2021-04-06  Alan Modra  <amodra@gmail.com>
 404
 405         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 406         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 407         symbol_at_address_func.
 408
 409 2021-04-05  Alan Modra  <amodra@gmail.com>
 410
 411         * configure.ac: Don't check for limits.h, string.h, strings.h or
 412         stdlib.h.
 413         (AC_ISC_POSIX): Don't invoke.
 414         * sysdep.h: Include stdlib.h and string.h unconditionally.
 415         * i386-opc.h: Include limits.h unconditionally.
 416         * wasm32-dis.c: Likewise.
 417         * cgen-opc.c: Don't include alloca-conf.h.
 418         * config.in: Regenerate.
 419         * configure: Regenerate.
 420
 421 2021-04-01  Martin Liska  <mliska@suse.cz>
 422
 423         * arm-dis.c (strneq): Remove strneq and use startswith.
 424         * cr16-dis.c (print_insn_cr16): Likewise.
 425         * score-dis.c (streq): Likewise.
 426         (strneq): Likewise.
 427         * score7-dis.c (strneq): Likewise.
 428
 429 2021-04-01  Alan Modra  <amodra@gmail.com>
 430
 431         PR 27675
 432         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 433
 434 2021-03-31  Alan Modra  <amodra@gmail.com>
 435
 436         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 437         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 438         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 439         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 440         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 441         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 442         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 443         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 444         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 445         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 446         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 447         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 448         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 449         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 450         and TRUE with true throughout.
 451
 452 2021-03-31  Alan Modra  <amodra@gmail.com>
 453
 454         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 455         * aarch64-dis.h: Likewise.
 456         * aarch64-opc.c: Likewise.
 457         * avr-dis.c: Likewise.
 458         * csky-dis.c: Likewise.
 459         * nds32-asm.c: Likewise.
 460         * nds32-dis.c: Likewise.
 461         * nfp-dis.c: Likewise.
 462         * riscv-dis.c: Likewise.
 463         * s12z-dis.c: Likewise.
 464         * wasm32-dis.c: Likewise.
 465
 466 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 467
 468         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 469         (i386_seg_prefixes): New.
 470         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 471         (i386_seg_prefixes): Declare.
 472
 473 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 474
 475         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 476
 477 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 478
 479         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 480         * i386-reg.tbl (st): Move down.
 481         (st(0)): Delete. Extend comment.
 482         * i386-tbl.h: Re-generate.
 483
 484 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 485
 486         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 487         (cmpsd): Move next to cmps.
 488         (movsd): Move next to movs.
 489         (cmpxchg16b): Move to separate section.
 490         (fisttp, fisttpll): Likewise.
 491         (monitor, mwait): Likewise.
 492         * i386-tbl.h: Re-generate.
 493
 494 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 495
 496         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 497         (vpsadbw): Add C.
 498         * i386-tbl.h: Re-generate.
 499
 500 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 501
 502         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 503         pclmul, gfni): New templates. Use them wherever possible. Move
 504         SSE4.1 pextrw into respective section.
 505         * i386-tbl.h: Re-generate.
 506
 507 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 508
 509         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 510         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 511         "length".
 512         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 513         Convert all of their uses to representation in opcode.
 514
 515 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 516
 517         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 518         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 519         value of None. Shrink operands to 3 bits.
 520
 521 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 522
 523         * i386-gen.c (process_i386_opcode_modifier): New parameter
 524         "space".
 525         (output_i386_opcode): New local variable "space". Adjust
 526         process_i386_opcode_modifier() invocation.
 527         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 528         invocation.
 529         * i386-tbl.h: Re-generate.
 530
 531 2021-03-29  Alan Modra  <amodra@gmail.com>
 532
 533         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 534         (fp_qualifier_p, get_data_pattern): Likewise.
 535         (aarch64_get_operand_modifier_from_value): Likewise.
 536         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 537         (operand_variant_qualifier_p): Likewise.
 538         (qualifier_value_in_range_constraint_p): Likewise.
 539         (aarch64_get_qualifier_esize): Likewise.
 540         (aarch64_get_qualifier_nelem): Likewise.
 541         (aarch64_get_qualifier_standard_value): Likewise.
 542         (get_lower_bound, get_upper_bound): Likewise.
 543         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 544         (aarch64_print_operand): Likewise.
 545         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 546         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 547         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 548         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 549         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 550         (print_insn_tic6x): Likewise.
 551
 552 2021-03-29  Alan Modra  <amodra@gmail.com>
 553
 554         * arc-dis.c (extract_operand_value): Correct NULL cast.
 555         * frv-opc.h: Regenerate.
 556
 557 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 558
 559         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 560         MMX form.
 561         * i386-tbl.h: Re-generate.
 562
 563 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 564
 565         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 566         immediate in br.n instruction.
 567
 568 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 569
 570         * i386-dis.c (XMGatherD, VexGatherD): New.
 571         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 572         (print_insn): Check masking for S/G insns.
 573         (OP_E_memory): New local variable check_gather. Extend mandatory
 574         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 575         Extend check for disallowed 16-bit addressing.
 576         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 577         if()s to switch(). Check register conflicts for (VEX-encoded)
 578         gathers. Drop no longer reachable cases.
 579         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 580         vgatherdp*.
 581
 582 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 583
 584         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 585         zeroing-masking without masking.
 586
 587 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 588
 589         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 590         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 591         single-operand forms as deprecated.
 592         * i386-tbl.h: Re-generate.
 593
 594 2021-03-25  Alan Modra  <amodra@gmail.com>
 595
 596         PR 27647
 597         * ppc-opc.c (XLOCB_MASK): Delete.
 598         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 599         XLBH_MASK.
 600         (powerpc_opcodes): Accept a BH field on all extended forms of
 601         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 602
 603 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 604
 605         * i386-gen.c (output_i386_opcode): Drop processing of
 606         opcode_length. Calculate length from base_opcode. Adjust prefix
 607         encoding determination.
 608         (process_i386_opcodes): Drop output of fake opcode_length.
 609         * i386-opc.h (struct insn_template): Drop opcode_length field.
 610         * i386-opc.tbl: Drop opcode length field from all templates.
 611         * i386-tbl.h: Re-generate.
 612
 613 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 614
 615         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 616         parameter "prefix". Drop local variable "regular_encoding".
 617         Record prefix setting / check for consistency.
 618         (output_i386_opcode): Parse opcode_length and base_opcode
 619         earlier. Derive prefix encoding. Drop no longer applicable
 620         consistency checking. Adjust process_i386_opcode_modifier()
 621         invocation.
 622         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 623         invocation.
 624         * i386-tbl.h: Re-generate.
 625
 626 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 627
 628         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 629         check.
 630         * i386-opc.h (Prefix_*): Move #define-s.
 631         * i386-opc.tbl: Move pseudo prefix enumerator values to
 632         extension opcode field. Introduce pseudopfx template.
 633         * i386-tbl.h: Re-generate.
 634
 635 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 636
 637         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 638         comment.
 639         * i386-tbl.h: Re-generate.
 640
 641 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 642
 643         * i386-opc.h (struct insn_template): Move cpu_flags field past
 644         opcode_modifier one.
 645         * i386-tbl.h: Re-generate.
 646
 647 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 648
 649         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 650         * i386-opc.h (OpcodeSpace): New enumerator.
 651         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 652         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 653         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 654         (struct i386_opcode_modifier): New field opcodespace. Shrink
 655         opcodeprefix field.
 656         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 657         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 658         OpcodePrefix uses.
 659         * i386-tbl.h: Re-generate.
 660
 661 2021-03-22  Martin Liska  <mliska@suse.cz>
 662
 663         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 664         * arc-dis.c (parse_option): Likewise.
 665         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 666         * cris-dis.c (print_with_operands): Likewise.
 667         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 668         * i386-dis.c (print_insn): Likewise.
 669         * ia64-gen.c (fetch_insn_class): Likewise.
 670         (parse_resource_users): Likewise.
 671         (in_iclass): Likewise.
 672         (lookup_specifier): Likewise.
 673         (insert_opcode_dependencies): Likewise.
 674         * mips-dis.c (parse_mips_ase_option): Likewise.
 675         (parse_mips_dis_option): Likewise.
 676         * s390-dis.c (disassemble_init_s390): Likewise.
 677         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 678
 679 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 680
 681         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 682
 683 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 684
 685         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 686         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 687
 688 2021-03-12  Alan Modra  <amodra@gmail.com>
 689
 690         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 691
 692 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 693
 694         * i386-dis.c (OP_XMM): Re-order checks.
 695
 696 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 697
 698         * i386-dis.c (putop): Drop need_vex check when also checking
 699         vex.evex.
 700         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 701         checking vex.b.
 702
 703 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 704
 705         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 706         checks. Move case label past broadcast check.
 707
 708 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 709
 710         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 711         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 712         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 713         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 714         EVEX_W_0F38C7_M_0_L_2): Delete.
 715         (REG_EVEX_0F38C7_M_0_L_2): New.
 716         (intel_operand_size): Handle VEX and EVEX the same for
 717         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 718         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 719         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 720         vex_vsib_q_w_d_mode uses.
 721         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 722         0F38A1, and 0F38A3 entries.
 723         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 724         entry.
 725         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 726         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 727         0F38A3 entries.
 728
 729 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 730
 731         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 732         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 733         MOD_VEX_0FXOP_09_12): Rename to ...
 734         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 735         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 736         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 737         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 738         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 739         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 740         (reg_table): Adjust comments.
 741         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 742         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 743         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 744         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 745         (vex_len_table): Adjust opcode 0A_12 entry.
 746         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 747         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 748         (rm_table): Move hreset entry.
 749
 750 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 751
 752         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 753         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 754         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 755         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 756         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 757         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 758         (get_valid_dis386): Also handle 512-bit vector length when
 759         vectoring into vex_len_table[].
 760         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 761         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 762         entries.
 763         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 764         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 765         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 766         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 767         entries.
 768
 769 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 770
 771         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 772         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 773         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 774         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 775         entries.
 776         * i386-dis-evex-len.h (evex_len_table): Likewise.
 777         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 778
 779 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 780
 781         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 782         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 783         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 784         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 785         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 786         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 787         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 788         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 789         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 790         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 791         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 792         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 793         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 794         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 795         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 796         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 797         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 798         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 799         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 800         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 801         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 802         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 803         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 804         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 805         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 806         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 807         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 808         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 809         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 810         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 811         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 812         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 813         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 814         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 815         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 816         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 817         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 818         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 819         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 820         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 821         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 822         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 823         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 824         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 825         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 826         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 827         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 828         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 829         EVEX_W_0F3A43_L_n): New.
 830         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 831         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 832         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 833         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 834         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 835         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 836         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 837         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 838         0F385B, 0F38C6, and 0F38C7 entries.
 839         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 840         0F38C6 and 0F38C7.
 841         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 842         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 843         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 844         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 845
 846 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 847
 848         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 849         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 850         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 851         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 852         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 853         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 854         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 855         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 856         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 857         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 858         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 859         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 860         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 861         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 862         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 863         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 864         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 865         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 866         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 867         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 868         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 869         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 870         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 871         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 872         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 873         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 874         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 875         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 876         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 877         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 878         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 879         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 880         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 881         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 882         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 883         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 884         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 885         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 886         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 887         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 888         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 889         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 890         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 891         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 892         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 893         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 894         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 895         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 896         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 897         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 898         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 899         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 900         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 901         VEX_W_0F99_P_2_LEN_0): Delete.
 902         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 903         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 904         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 905         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 906         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 907         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 908         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 909         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 910         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 911         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 912         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 913         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 914         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 915         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 916         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 917         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 918         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 919         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 920         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 921         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 922         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 923         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 924         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 925         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 926         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 927         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 928         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 929         (prefix_table): No longer link to vex_len_table[] for opcodes
 930         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 931         0F92, 0F93, 0F98, and 0F99.
 932         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 933         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 934         0F98, and 0F99.
 935         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 936         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 937         0F98, and 0F99.
 938         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 939         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 940         0F98, and 0F99.
 941         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 942         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 943         0F98, and 0F99.
 944
 945 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 946
 947         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 948         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 949         REG_VEX_0F73_M_0 respectively.
 950         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 951         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 952         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 953         MOD_VEX_0F73_REG_7): Delete.
 954         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 955         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 956         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 957         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 958         PREFIX_VEX_0F3AF0_L_0 respectively.
 959         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 960         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 961         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 962         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 963         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 964         VEX_LEN_0F38F7): New.
 965         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 966         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 967         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 968         0F38F3.
 969         (prefix_table): No longer link to vex_len_table[] for opcodes
 970         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 971         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 972         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 973         0F38F6, 0F38F7, and 0F3AF0.
 974         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 975         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 976         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 977         0F73.
 978
 979 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 980
 981         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 982         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 983         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 984         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 985         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 986         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 987         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 988         73.
 989         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 990         0F72, and 0F73.
 991         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 992         0F73.
 993
 994 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 995
 996         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 997         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 998         (reg_table): Don't link to mod_table[] where not needed. Add
 999         PREFIX_IGNORED to nop entries.
1000         (prefix_table): Replace PREFIX_OPCODE in nop entries.
1001         (mod_table): Add nop entries next to prefetch ones. Drop
1002         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
1003         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
1004         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
1005         PREFIX_OPCODE from endbr* entries.
1006         (get_valid_dis386): Also consider entry's name when zapping
1007         vindex.
1008         (print_insn): Handle PREFIX_IGNORED.
1009
1010 2021-03-09  Jan Beulich  <jbeulich@suse.com>
1011
1012         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
1013         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
1014         element.
1015         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
1016         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
1017         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
1018         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
1019         (struct i386_opcode_modifier): Delete notrackprefixok,
1020         islockable, hleprefixok, and repprefixok fields. Add prefixok
1021         field.
1022         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
1023         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
1024         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
1025         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
1026         Replace HLEPrefixOk.
1027         * opcodes/i386-tbl.h: Re-generate.
1028
1029 2021-03-09  Jan Beulich  <jbeulich@suse.com>
1030
1031         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
1032         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
1033         64-bit form.
1034         * opcodes/i386-tbl.h: Re-generate.
1035
1036 2021-03-03  Jan Beulich  <jbeulich@suse.com>
1037
1038         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
1039         for {} instead of {0}. Don't look for '0'.
1040         * i386-opc.tbl: Drop operand count field. Drop redundant operand
1041         size specifiers.
1042
1043 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
1044
1045         PR 27158
1046         * riscv-dis.c (print_insn_args): Updated encoding macros.
1047         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1048         (match_c_addi16sp): Updated encoding macros.
1049         (match_c_lui): Likewise.
1050         (match_c_lui_with_hint): Likewise.
1051         (match_c_addi4spn): Likewise.
1052         (match_c_slli): Likewise.
1053         (match_slli_as_c_slli): Likewise.
1054         (match_c_slli64): Likewise.
1055         (match_srxi_as_c_srxi): Likewise.
1056         (riscv_insn_types): Added .insn css/cl/cs.
1057
1058 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
1059
1060         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1061         (default_priv_spec): Updated type to riscv_spec_class.
1062         (parse_riscv_dis_option): Updated.
1063         * riscv-opc.c: Moved stuff and make the file tidy.
1064
1065 2021-02-17  Alan Modra  <amodra@gmail.com>
1066
1067         * wasm32-dis.c: Include limits.h.
1068         (CHAR_BIT): Provide backup define.
1069         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1070         Correct signed overflow checking.
1071
1072 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1073
1074         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1075         * i386-tbl.h: Re-generate.
1076
1077 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1078
1079         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1080         Oword.
1081         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1082
1083 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
1084
1085         * s390-mkopc.c (main): Accept arch14 as cpu string.
1086         * s390-opc.txt: Add new arch14 instructions.
1087
1088 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
1089
1090         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1091         favour of LIBINTL.
1092         * configure: Regenerated.
1093
1094 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
1095
1096         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1097         * tic54x-opc.c (regs): Rename to ...
1098         (tic54x_regs): ... this.
1099         (mmregs): Rename to ...
1100         (tic54x_mmregs): ... this.
1101         (condition_codes): Rename to ...
1102         (tic54x_condition_codes): ... this.
1103         (cc2_codes): Rename to ...
1104         (tic54x_cc2_codes): ... this.
1105         (cc3_codes): Rename to ...
1106         (tic54x_cc3_codes): ... this.
1107         (status_bits): Rename to ...
1108         (tic54x_status_bits): ... this.
1109         (misc_symbols): Rename to ...
1110         (tic54x_misc_symbols): ... this.
1111
1112 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
1113
1114         * riscv-opc.c (MASK_RVB_IMM): Removed.
1115         (riscv_opcodes): Removed zb* instructions.
1116         (riscv_ext_version_table): Removed versions for zb*.
1117
1118 2021-01-26  Alan Modra  <amodra@gmail.com>
1119
1120         * i386-gen.c (parse_template): Ensure entire template_instance
1121         is initialised.
1122
1123 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1124
1125         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1126         (riscv_fpr_names_abi): Likewise.
1127         (riscv_opcodes): Likewise.
1128         (riscv_insn_types): Likewise.
1129
1130 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1131
1132         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1133
1134 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1135
1136         * riscv-dis.c: Comments tidy and improvement.
1137         * riscv-opc.c: Likewise.
1138
1139 2021-01-13  Alan Modra  <amodra@gmail.com>
1140
1141         * Makefile.in: Regenerate.
1142
1143 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
1144
1145         PR binutils/26792
1146         * configure.ac: Use GNU_MAKE_JOBSERVER.
1147         * aclocal.m4: Regenerated.
1148         * configure: Likewise.
1149
1150 2021-01-12  Nick Clifton  <nickc@redhat.com>
1151
1152         * po/sr.po: Updated Serbian translation.
1153
1154 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
1155
1156         PR ld/27173
1157         * configure: Regenerated.
1158
1159 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1160
1161         * aarch64-asm-2.c: Regenerate.
1162         * aarch64-dis-2.c: Likewise.
1163         * aarch64-opc-2.c: Likewise.
1164         * aarch64-opc.c (aarch64_print_operand):
1165         Delete handling of AARCH64_OPND_CSRE_CSR.
1166         * aarch64-tbl.h (aarch64_feature_csre): Delete.
1167         (CSRE): Likewise.
1168         (_CSRE_INSN): Likewise.
1169         (aarch64_opcode_table): Delete csr.
1170
1171 2021-01-11  Nick Clifton  <nickc@redhat.com>
1172
1173         * po/de.po: Updated German translation.
1174         * po/fr.po: Updated French translation.
1175         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1176         * po/sv.po: Updated Swedish translation.
1177         * po/uk.po: Updated Ukranian translation.
1178
1179 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
1180
1181         * configure: Regenerated.
1182
1183 2021-01-09  Nick Clifton  <nickc@redhat.com>
1184
1185         * configure: Regenerate.
1186         * po/opcodes.pot: Regenerate.
1187
1188 2021-01-09  Nick Clifton  <nickc@redhat.com>
1189
1190         * 2.36 release branch crated.
1191
1192 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
1193
1194         * ppc-opc.c (insert_dw, (extract_dw): New functions.
1195         (DW, (XRC_MASK): Define.
1196         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1197
1198 2021-01-09  Alan Modra  <amodra@gmail.com>
1199
1200         * configure: Regenerate.
1201
1202 2021-01-08  Nick Clifton  <nickc@redhat.com>
1203
1204         * po/sv.po: Updated Swedish translation.
1205
1206 2021-01-08  Nick Clifton  <nickc@redhat.com>
1207
1208         PR 27129
1209         * aarch64-dis.c (determine_disassembling_preference): Move call to
1210         aarch64_match_operands_constraint outside of the assertion.
1211         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1212         Replace with a return of FALSE.
1213
1214         PR 27139
1215         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1216         core system register.
1217
1218 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
1219
1220         * configure: Regenerate.
1221
1222 2021-01-07  Nick Clifton  <nickc@redhat.com>
1223
1224         * po/fr.po: Updated French translation.
1225
1226 2021-01-07  Fredrik Noring  <noring@nocrew.org>
1227
1228         * m68k-opc.c (chkl): Change minimum architecture requirement to
1229         m68020.
1230
1231 2021-01-07  Philipp Tomsich  <prt@gnu.org>
1232
1233         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1234
1235 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
1236             Jim Wilson  <jimw@sifive.com>
1237             Andrew Waterman  <andrew@sifive.com>
1238             Maxim Blinov  <maxim.blinov@embecosm.com>
1239             Kito Cheng  <kito.cheng@sifive.com>
1240             Nelson Chu  <nelson.chu@sifive.com>
1241
1242         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1243         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1244
1245 2021-01-01  Alan Modra  <amodra@gmail.com>
1246
1247         Update year range in copyright notice of all files.
1248
1249 For older changes see ChangeLog-2020
1250 \f
1251 Copyright (C) 2021-2022 Free Software Foundation, Inc.
1252
1253 Copying and distribution of this file, with or without modification,
1254 are permitted in any medium without royalty provided the copyright
1255 notice and this notice are preserved.
1256
1257 Local Variables:
1258 mode: change-log
1259 left-margin: 8
1260 fill-column: 74
1261 version-control: never
1262 End: