opcodes/aarch64-opc.h

   1 /* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.
   2    Copyright (C) 2012-2019 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; see the file COPYING3. If not,
  19    see <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef OPCODES_AARCH64_OPC_H
  22 #define OPCODES_AARCH64_OPC_H
  23
  24 #include <string.h>
  25 #include "opcode/aarch64.h"
  26
  27 /* Instruction fields.
  28    Keep synced with fields.  */
  29 enum aarch64_field_kind
  30 {
  31   FLD_NIL,
  32   FLD_cond2,
  33   FLD_nzcv,
  34   FLD_defgh,
  35   FLD_abc,
  36   FLD_imm19,
  37   FLD_immhi,
  38   FLD_immlo,
  39   FLD_size,
  40   FLD_vldst_size,
  41   FLD_op,
  42   FLD_Q,
  43   FLD_Rt,
  44   FLD_Rd,
  45   FLD_Rn,
  46   FLD_Rt2,
  47   FLD_Ra,
  48   FLD_op2,
  49   FLD_CRm,
  50   FLD_CRn,
  51   FLD_op1,
  52   FLD_op0,
  53   FLD_imm3,
  54   FLD_cond,
  55   FLD_opcode,
  56   FLD_cmode,
  57   FLD_asisdlso_opcode,
  58   FLD_len,
  59   FLD_Rm,
  60   FLD_Rs,
  61   FLD_option,
  62   FLD_S,
  63   FLD_hw,
  64   FLD_opc,
  65   FLD_opc1,
  66   FLD_shift,
  67   FLD_type,
  68   FLD_ldst_size,
  69   FLD_imm6,
  70   FLD_imm6_2,
  71   FLD_imm4,
  72   FLD_imm4_2,
  73   FLD_imm4_3,
  74   FLD_imm5,
  75   FLD_imm7,
  76   FLD_imm8,
  77   FLD_imm9,
  78   FLD_imm12,
  79   FLD_imm14,
  80   FLD_imm16,
  81   FLD_imm26,
  82   FLD_imms,
  83   FLD_immr,
  84   FLD_immb,
  85   FLD_immh,
  86   FLD_S_imm10,
  87   FLD_N,
  88   FLD_index,
  89   FLD_index2,
  90   FLD_sf,
  91   FLD_lse_sz,
  92   FLD_H,
  93   FLD_L,
  94   FLD_M,
  95   FLD_b5,
  96   FLD_b40,
  97   FLD_scale,
  98   FLD_SVE_M_4,
  99   FLD_SVE_M_14,
 100   FLD_SVE_M_16,
 101   FLD_SVE_N,
 102   FLD_SVE_Pd,
 103   FLD_SVE_Pg3,
 104   FLD_SVE_Pg4_5,
 105   FLD_SVE_Pg4_10,
 106   FLD_SVE_Pg4_16,
 107   FLD_SVE_Pm,
 108   FLD_SVE_Pn,
 109   FLD_SVE_Pt,
 110   FLD_SVE_Rm,
 111   FLD_SVE_Rn,
 112   FLD_SVE_Vd,
 113   FLD_SVE_Vm,
 114   FLD_SVE_Vn,
 115   FLD_SVE_Za_5,
 116   FLD_SVE_Za_16,
 117   FLD_SVE_Zd,
 118   FLD_SVE_Zm_5,
 119   FLD_SVE_Zm_16,
 120   FLD_SVE_Zn,
 121   FLD_SVE_Zt,
 122   FLD_SVE_i1,
 123   FLD_SVE_i3h,
 124   FLD_SVE_imm3,
 125   FLD_SVE_imm4,
 126   FLD_SVE_imm5,
 127   FLD_SVE_imm5b,
 128   FLD_SVE_imm6,
 129   FLD_SVE_imm7,
 130   FLD_SVE_imm8,
 131   FLD_SVE_imm9,
 132   FLD_SVE_immr,
 133   FLD_SVE_imms,
 134   FLD_SVE_msz,
 135   FLD_SVE_pattern,
 136   FLD_SVE_prfop,
 137   FLD_SVE_rot1,
 138   FLD_SVE_rot2,
 139   FLD_SVE_rot3,
 140   FLD_SVE_sz,
 141   FLD_SVE_size,
 142   FLD_SVE_tsz,
 143   FLD_SVE_tszh,
 144   FLD_SVE_tszl_8,
 145   FLD_SVE_tszl_19,
 146   FLD_SVE_xs_14,
 147   FLD_SVE_xs_22,
 148   FLD_rotate1,
 149   FLD_rotate2,
 150   FLD_rotate3,
 151   FLD_SM3_imm2,
 152   FLD_sz
 153 };
 154
 155 /* Field description.  */
 156 struct aarch64_field
 157 {
 158   int lsb;
 159   int width;
 160 };
 161
 162 typedef struct aarch64_field aarch64_field;
 163
 164 extern const aarch64_field fields[];
 165 \f
 166 /* Operand description.  */
 167
 168 struct aarch64_operand
 169 {
 170   enum aarch64_operand_class op_class;
 171
 172   /* Name of the operand code; used mainly for the purpose of internal
 173      debugging.  */
 174   const char *name;
 175
 176   unsigned int flags;
 177
 178   /* The associated instruction bit-fields; no operand has more than 4
 179      bit-fields */
 180   enum aarch64_field_kind fields[4];
 181
 182   /* Brief description */
 183   const char *desc;
 184 };
 185
 186 typedef struct aarch64_operand aarch64_operand;
 187
 188 extern const aarch64_operand aarch64_operands[];
 189
 190 enum err_type
 191 verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
 192                     bfd_boolean, aarch64_operand_error *, aarch64_instr_sequence*);
 193
 194 /* Operand flags.  */
 195
 196 #define OPD_F_HAS_INSERTER      0x00000001
 197 #define OPD_F_HAS_EXTRACTOR     0x00000002
 198 #define OPD_F_SEXT              0x00000004      /* Require sign-extension.  */
 199 #define OPD_F_SHIFT_BY_2        0x00000008      /* Need to left shift the field
 200                                                    value by 2 to get the value
 201                                                    of an immediate operand.  */
 202 #define OPD_F_MAYBE_SP          0x00000010      /* May potentially be SP.  */
 203 #define OPD_F_OD_MASK           0x000000e0      /* Operand-dependent data.  */
 204 #define OPD_F_OD_LSB            5
 205 #define OPD_F_NO_ZR             0x00000100      /* ZR index not allowed.  */
 206 #define OPD_F_SHIFT_BY_4        0x00000200      /* Need to left shift the field
 207                                                    value by 4 to get the value
 208                                                    of an immediate operand.  */
 209
 210
 211 /* Register flags.  */
 212
 213 #undef F_DEPRECATED
 214 #define F_DEPRECATED    (1 << 0)  /* Deprecated system register.  */
 215
 216 #undef F_ARCHEXT
 217 #define F_ARCHEXT       (1 << 1)  /* Architecture dependent system register.  */
 218
 219 #undef F_HASXT
 220 #define F_HASXT         (1 << 2)  /* System instruction register <Xt>
 221                                      operand.  */
 222
 223 #undef F_REG_READ
 224 #define F_REG_READ      (1 << 3)  /* Register can only be used to read values
 225                                      out of.  */
 226
 227 #undef F_REG_WRITE
 228 #define F_REG_WRITE     (1 << 4)  /* Register can only be written to but not
 229                                      read from.  */
 230
 231 /* HINT operand flags.  */
 232 #define HINT_OPD_F_NOPRINT      (1 << 0)  /* Should not be printed.  */
 233
 234 /* Encode 7-bit HINT #imm in the lower 8 bits.  Use higher bits for flags.  */
 235 #define HINT_ENCODE(flag, val) ((flag << 8) | val)
 236 #define HINT_FLAG(val) (val >> 8)
 237 #define HINT_VAL(val) (val & 0xff)
 238
 239 static inline bfd_boolean
 240 operand_has_inserter (const aarch64_operand *operand)
 241 {
 242   return (operand->flags & OPD_F_HAS_INSERTER) ? TRUE : FALSE;
 243 }
 244
 245 static inline bfd_boolean
 246 operand_has_extractor (const aarch64_operand *operand)
 247 {
 248   return (operand->flags & OPD_F_HAS_EXTRACTOR) ? TRUE : FALSE;
 249 }
 250
 251 static inline bfd_boolean
 252 operand_need_sign_extension (const aarch64_operand *operand)
 253 {
 254   return (operand->flags & OPD_F_SEXT) ? TRUE : FALSE;
 255 }
 256
 257 static inline bfd_boolean
 258 operand_need_shift_by_two (const aarch64_operand *operand)
 259 {
 260   return (operand->flags & OPD_F_SHIFT_BY_2) ? TRUE : FALSE;
 261 }
 262
 263 static inline bfd_boolean
 264 operand_need_shift_by_four (const aarch64_operand *operand)
 265 {
 266   return (operand->flags & OPD_F_SHIFT_BY_4) ? TRUE : FALSE;
 267 }
 268
 269 static inline bfd_boolean
 270 operand_maybe_stack_pointer (const aarch64_operand *operand)
 271 {
 272   return (operand->flags & OPD_F_MAYBE_SP) ? TRUE : FALSE;
 273 }
 274
 275 /* Return the value of the operand-specific data field (OPD_F_OD_MASK).  */
 276 static inline unsigned int
 277 get_operand_specific_data (const aarch64_operand *operand)
 278 {
 279   return (operand->flags & OPD_F_OD_MASK) >> OPD_F_OD_LSB;
 280 }
 281
 282 /* Return the width of field number N of operand *OPERAND.  */
 283 static inline unsigned
 284 get_operand_field_width (const aarch64_operand *operand, unsigned n)
 285 {
 286   assert (operand->fields[n] != FLD_NIL);
 287   return fields[operand->fields[n]].width;
 288 }
 289
 290 /* Return the total width of the operand *OPERAND.  */
 291 static inline unsigned
 292 get_operand_fields_width (const aarch64_operand *operand)
 293 {
 294   int i = 0;
 295   unsigned width = 0;
 296   while (operand->fields[i] != FLD_NIL)
 297     width += fields[operand->fields[i++]].width;
 298   assert (width > 0 && width < 32);
 299   return width;
 300 }
 301
 302 static inline const aarch64_operand *
 303 get_operand_from_code (enum aarch64_opnd code)
 304 {
 305   return aarch64_operands + code;
 306 }
 307 \f
 308 /* Operand qualifier and operand constraint checking.  */
 309
 310 int aarch64_match_operands_constraint (aarch64_inst *,
 311                                        aarch64_operand_error *);
 312
 313 /* Operand qualifier related functions.  */
 314 const char* aarch64_get_qualifier_name (aarch64_opnd_qualifier_t);
 315 unsigned char aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t);
 316 aarch64_insn aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t);
 317 int aarch64_find_best_match (const aarch64_inst *,
 318                              const aarch64_opnd_qualifier_seq_t *,
 319                              int, aarch64_opnd_qualifier_t *);
 320
 321 static inline void
 322 reset_operand_qualifier (aarch64_inst *inst, int idx)
 323 {
 324   assert (idx >=0 && idx < aarch64_num_of_operands (inst->opcode));
 325   inst->operands[idx].qualifier = AARCH64_OPND_QLF_NIL;
 326 }
 327 \f
 328 /* Inline functions operating on instruction bit-field(s).  */
 329
 330 /* Generate a mask that has WIDTH number of consecutive 1s.  */
 331
 332 static inline aarch64_insn
 333 gen_mask (int width)
 334 {
 335   return ((aarch64_insn) 1 << width) - 1;
 336 }
 337
 338 /* LSB_REL is the relative location of the lsb in the sub field, starting from 0.  */
 339 static inline int
 340 gen_sub_field (enum aarch64_field_kind kind, int lsb_rel, int width, aarch64_field *ret)
 341 {
 342   const aarch64_field *field = &fields[kind];
 343   if (lsb_rel < 0 || width <= 0 || lsb_rel + width > field->width)
 344     return 0;
 345   ret->lsb = field->lsb + lsb_rel;
 346   ret->width = width;
 347   return 1;
 348 }
 349
 350 /* Insert VALUE into FIELD of CODE.  MASK can be zero or the base mask
 351    of the opcode.  */
 352
 353 static inline void
 354 insert_field_2 (const aarch64_field *field, aarch64_insn *code,
 355                 aarch64_insn value, aarch64_insn mask)
 356 {
 357   assert (field->width < 32 && field->width >= 1 && field->lsb >= 0
 358           && field->lsb + field->width <= 32);
 359   value &= gen_mask (field->width);
 360   value <<= field->lsb;
 361   /* In some opcodes, field can be part of the base opcode, e.g. the size
 362      field in FADD.  The following helps avoid corrupt the base opcode.  */
 363   value &= ~mask;
 364   *code |= value;
 365 }
 366
 367 /* Extract FIELD of CODE and return the value.  MASK can be zero or the base
 368    mask of the opcode.  */
 369
 370 static inline aarch64_insn
 371 extract_field_2 (const aarch64_field *field, aarch64_insn code,
 372                  aarch64_insn mask)
 373 {
 374   aarch64_insn value;
 375   /* Clear any bit that is a part of the base opcode.  */
 376   code &= ~mask;
 377   value = (code >> field->lsb) & gen_mask (field->width);
 378   return value;
 379 }
 380
 381 /* Insert VALUE into field KIND of CODE.  MASK can be zero or the base mask
 382    of the opcode.  */
 383
 384 static inline void
 385 insert_field (enum aarch64_field_kind kind, aarch64_insn *code,
 386               aarch64_insn value, aarch64_insn mask)
 387 {
 388   insert_field_2 (&fields[kind], code, value, mask);
 389 }
 390
 391 /* Extract field KIND of CODE and return the value.  MASK can be zero or the
 392    base mask of the opcode.  */
 393
 394 static inline aarch64_insn
 395 extract_field (enum aarch64_field_kind kind, aarch64_insn code,
 396                aarch64_insn mask)
 397 {
 398   return extract_field_2 (&fields[kind], code, mask);
 399 }
 400
 401 extern aarch64_insn
 402 extract_fields (aarch64_insn code, aarch64_insn mask, ...);
 403 \f
 404 /* Inline functions selecting operand to do the encoding/decoding for a
 405    certain instruction bit-field.  */
 406
 407 /* Select the operand to do the encoding/decoding of the 'sf' field.
 408    The heuristic-based rule is that the result operand is respected more.  */
 409
 410 static inline int
 411 select_operand_for_sf_field_coding (const aarch64_opcode *opcode)
 412 {
 413   int idx = -1;
 414   if (aarch64_get_operand_class (opcode->operands[0])
 415       == AARCH64_OPND_CLASS_INT_REG)
 416     /* normal case.  */
 417     idx = 0;
 418   else if (aarch64_get_operand_class (opcode->operands[1])
 419            == AARCH64_OPND_CLASS_INT_REG)
 420     /* e.g. float2fix.  */
 421     idx = 1;
 422   else
 423     { assert (0); abort (); }
 424   return idx;
 425 }
 426
 427 /* Select the operand to do the encoding/decoding of the 'type' field in
 428    the floating-point instructions.
 429    The heuristic-based rule is that the source operand is respected more.  */
 430
 431 static inline int
 432 select_operand_for_fptype_field_coding (const aarch64_opcode *opcode)
 433 {
 434   int idx;
 435   if (aarch64_get_operand_class (opcode->operands[1])
 436       == AARCH64_OPND_CLASS_FP_REG)
 437     /* normal case.  */
 438     idx = 1;
 439   else if (aarch64_get_operand_class (opcode->operands[0])
 440            == AARCH64_OPND_CLASS_FP_REG)
 441     /* e.g. float2fix.  */
 442     idx = 0;
 443   else
 444     { assert (0); abort (); }
 445   return idx;
 446 }
 447
 448 /* Select the operand to do the encoding/decoding of the 'size' field in
 449    the AdvSIMD scalar instructions.
 450    The heuristic-based rule is that the destination operand is respected
 451    more.  */
 452
 453 static inline int
 454 select_operand_for_scalar_size_field_coding (const aarch64_opcode *opcode)
 455 {
 456   int src_size = 0, dst_size = 0;
 457   if (aarch64_get_operand_class (opcode->operands[0])
 458       == AARCH64_OPND_CLASS_SISD_REG)
 459     dst_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][0]);
 460   if (aarch64_get_operand_class (opcode->operands[1])
 461       == AARCH64_OPND_CLASS_SISD_REG)
 462     src_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][1]);
 463   if (src_size == dst_size && src_size == 0)
 464     { assert (0); abort (); }
 465   /* When the result is not a sisd register or it is a long operantion.  */
 466   if (dst_size == 0 || dst_size == src_size << 1)
 467     return 1;
 468   else
 469     return 0;
 470 }
 471
 472 /* Select the operand to do the encoding/decoding of the 'size:Q' fields in
 473    the AdvSIMD instructions.  */
 474
 475 int aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *);
 476 \f
 477 /* Miscellaneous.  */
 478
 479 aarch64_insn aarch64_get_operand_modifier_value (enum aarch64_modifier_kind);
 480 enum aarch64_modifier_kind
 481 aarch64_get_operand_modifier_from_value (aarch64_insn, bfd_boolean);
 482
 483
 484 bfd_boolean aarch64_wide_constant_p (int64_t, int, unsigned int *);
 485 bfd_boolean aarch64_logical_immediate_p (uint64_t, int, aarch64_insn *);
 486 int aarch64_shrink_expanded_imm8 (uint64_t);
 487
 488 /* Copy the content of INST->OPERANDS[SRC] to INST->OPERANDS[DST].  */
 489 static inline void
 490 copy_operand_info (aarch64_inst *inst, int dst, int src)
 491 {
 492   assert (dst >= 0 && src >= 0 && dst < AARCH64_MAX_OPND_NUM
 493           && src < AARCH64_MAX_OPND_NUM);
 494   memcpy (&inst->operands[dst], &inst->operands[src],
 495           sizeof (aarch64_opnd_info));
 496   inst->operands[dst].idx = dst;
 497 }
 498
 499 /* A primitive log caculator.  */
 500
 501 static inline unsigned int
 502 get_logsz (unsigned int size)
 503 {
 504   const unsigned char ls[16] =
 505     {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
 506   if (size > 16)
 507     {
 508       assert (0);
 509       return -1;
 510     }
 511   assert (ls[size - 1] != (unsigned char)-1);
 512   return ls[size - 1];
 513 }
 514
 515 #endif /* OPCODES_AARCH64_OPC_H */