opcodes/arm-dis.c

   1 /* Instruction printing code for the ARM
   2    Copyright (C) 1994-2019 Free Software Foundation, Inc.
   3    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
   4    Modification by James G. Smith (jsmith@cygnus.co.uk)
   5
   6    This file is part of libopcodes.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23 #include "sysdep.h"
  24
  25 #include "disassemble.h"
  26 #include "opcode/arm.h"
  27 #include "opintl.h"
  28 #include "safe-ctype.h"
  29 #include "libiberty.h"
  30 #include "floatformat.h"
  31
  32 /* FIXME: This shouldn't be done here.  */
  33 #include "coff/internal.h"
  34 #include "libcoff.h"
  35 #include "bfd.h"
  36 #include "elf-bfd.h"
  37 #include "elf/internal.h"
  38 #include "elf/arm.h"
  39 #include "mach-o.h"
  40
  41 /* FIXME: Belongs in global header.  */
  42 #ifndef strneq
  43 #define strneq(a,b,n)   (strncmp ((a), (b), (n)) == 0)
  44 #endif
  45
  46 /* Cached mapping symbol state.  */
  47 enum map_type
  48 {
  49   MAP_ARM,
  50   MAP_THUMB,
  51   MAP_DATA
  52 };
  53
  54 struct arm_private_data
  55 {
  56   /* The features to use when disassembling optional instructions.  */
  57   arm_feature_set features;
  58
  59   /* Track the last type (although this doesn't seem to be useful) */
  60   enum map_type last_type;
  61
  62   /* Tracking symbol table information */
  63   int last_mapping_sym;
  64
  65   /* The end range of the current range being disassembled.  */
  66   bfd_vma last_stop_offset;
  67   bfd_vma last_mapping_addr;
  68 };
  69
  70 struct opcode32
  71 {
  72   arm_feature_set arch;         /* Architecture defining this insn.  */
  73   unsigned long value;          /* If arch is 0 then value is a sentinel.  */
  74   unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
  75   const char *  assembler;      /* How to disassemble this insn.  */
  76 };
  77
  78 struct opcode16
  79 {
  80   arm_feature_set arch;         /* Architecture defining this insn.  */
  81   unsigned short value, mask;   /* Recognise insn if (op & mask) == value.  */
  82   const char *assembler;        /* How to disassemble this insn.  */
  83 };
  84
  85 /* print_insn_coprocessor recognizes the following format control codes:
  86
  87    %%                   %
  88
  89    %c                   print condition code (always bits 28-31 in ARM mode)
  90    %q                   print shifter argument
  91    %u                   print condition code (unconditional in ARM mode,
  92                           UNPREDICTABLE if not AL in Thumb)
  93    %A                   print address for ldc/stc/ldf/stf instruction
  94    %B                   print vstm/vldm register list
  95    %I                   print cirrus signed shift immediate: bits 0..3|4..6
  96    %F                   print the COUNT field of a LFM/SFM instruction.
  97    %P                   print floating point precision in arithmetic insn
  98    %Q                   print floating point precision in ldf/stf insn
  99    %R                   print floating point rounding mode
 100
 101    %<bitfield>c         print as a condition code (for vsel)
 102    %<bitfield>r         print as an ARM register
 103    %<bitfield>R         as %<>r but r15 is UNPREDICTABLE
 104    %<bitfield>ru        as %<>r but each u register must be unique.
 105    %<bitfield>d         print the bitfield in decimal
 106    %<bitfield>k         print immediate for VFPv3 conversion instruction
 107    %<bitfield>x         print the bitfield in hex
 108    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
 109    %<bitfield>f         print a floating point constant if >7 else a
 110                         floating point register
 111    %<bitfield>w         print as an iWMMXt width field - [bhwd]ss/us
 112    %<bitfield>g         print as an iWMMXt 64-bit register
 113    %<bitfield>G         print as an iWMMXt general purpose or control register
 114    %<bitfield>D         print as a NEON D register
 115    %<bitfield>Q         print as a NEON Q register
 116    %<bitfield>V         print as a NEON D or Q register
 117    %<bitfield>E         print a quarter-float immediate value
 118
 119    %y<code>             print a single precision VFP reg.
 120                           Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
 121    %z<code>             print a double precision VFP reg
 122                           Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
 123
 124    %<bitfield>'c        print specified char iff bitfield is all ones
 125    %<bitfield>`c        print specified char iff bitfield is all zeroes
 126    %<bitfield>?ab...    select from array of values in big endian order
 127
 128    %L                   print as an iWMMXt N/M width field.
 129    %Z                   print the Immediate of a WSHUFH instruction.
 130    %l                   like 'A' except use byte offsets for 'B' & 'H'
 131                         versions.
 132    %i                   print 5-bit immediate in bits 8,3..0
 133                         (print "32" when 0)
 134    %r                   print register offset address for wldt/wstr instruction.  */
 135
 136 enum opcode_sentinel_enum
 137 {
 138   SENTINEL_IWMMXT_START = 1,
 139   SENTINEL_IWMMXT_END,
 140   SENTINEL_GENERIC_START
 141 } opcode_sentinels;
 142
 143 #define UNDEFINED_INSTRUCTION      "\t\t; <UNDEFINED> instruction: %0-31x"
 144 #define UNKNOWN_INSTRUCTION_32BIT  "\t\t; <UNDEFINED> instruction: %08x"
 145 #define UNKNOWN_INSTRUCTION_16BIT  "\t\t; <UNDEFINED> instruction: %04x"
 146 #define UNPREDICTABLE_INSTRUCTION  "\t; <UNPREDICTABLE>"
 147
 148 /* Common coprocessor opcodes shared between Arm and Thumb-2.  */
 149
 150 static const struct opcode32 coprocessor_opcodes[] =
 151 {
 152   /* XScale instructions.  */
 153   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 154     0x0e200010, 0x0fff0ff0,
 155     "mia%c\tacc0, %0-3r, %12-15r"},
 156   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 157     0x0e280010, 0x0fff0ff0,
 158     "miaph%c\tacc0, %0-3r, %12-15r"},
 159   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 160     0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
 161   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 162     0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
 163   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 164     0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
 165
 166   /* Intel Wireless MMX technology instructions.  */
 167   {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
 168   {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
 169     0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
 170   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 171     0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
 172   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 173     0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
 174   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 175     0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
 176   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 177     0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
 178   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 179     0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
 180   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 181     0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
 182   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 183     0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
 184   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 185     0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
 186   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 187     0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
 188   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 189     0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
 190   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 191     0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
 192   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 193     0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
 194   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 195     0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
 196   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 197     0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
 198   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 199     0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
 200   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 201     0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
 202   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 203     0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 204   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 205     0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
 206   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 207     0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
 208   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 209     0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
 210   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 211     0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
 212   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 213     0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
 214   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 215     0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
 216   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 217     0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
 218   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 219     0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 220   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 221     0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 222   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 223     0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
 224   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 225     0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
 226   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 227     0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
 228   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 229     0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
 230   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 231     0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
 232   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 233     0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
 234   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 235     0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 236   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 237     0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
 238   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 239     0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 240   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 241     0x0e800120, 0x0f800ff0,
 242     "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 243   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 244     0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 245   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 246     0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
 247   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 248     0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
 249   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 250     0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
 251   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 252     0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
 253   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 254     0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
 255   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 256     0x0e8000a0, 0x0f800ff0,
 257     "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 258   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 259     0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 260   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 261     0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 262   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 263     0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
 264   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 265     0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 266   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 267     0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
 268   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 269     0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 270   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 271     0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
 272   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 273     0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
 274   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 275     0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
 276   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 277     0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
 278   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 279     0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 280   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 281     0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 282   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 283     0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
 284   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 285     0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 286   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 287     0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 288   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 289     0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
 290   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 291     0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 292   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 293     0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 294   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 295     0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
 296   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 297     0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
 298   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 299     0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
 300   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 301     0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 302   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 303     0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
 304   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 305     0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 306   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 307     0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
 308   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 309     0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
 310   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 311     0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
 312   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 313     0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
 314   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 315     0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 316   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 317     0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 318   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 319     0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
 320   {ARM_FEATURE_CORE_LOW (0),
 321     SENTINEL_IWMMXT_END, 0, "" },
 322
 323   /* Floating point coprocessor (FPA) instructions.  */
 324   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 325     0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 326   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 327     0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 328   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 329     0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 330   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 331     0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 332   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 333     0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 334   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 335     0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 336   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 337     0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
 338   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 339     0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
 340   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 341     0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 342   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 343     0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
 344   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 345     0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
 346   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 347     0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
 348   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 349     0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
 350   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 351     0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
 352   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 353     0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
 354   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 355     0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
 356   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 357     0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
 358   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 359     0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
 360   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 361     0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
 362   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 363     0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
 364   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 365     0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
 366   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 367     0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
 368   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 369     0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
 370   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 371     0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
 372   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 373     0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
 374   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 375     0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
 376   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 377     0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
 378   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 379     0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
 380   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 381     0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
 382   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 383     0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
 384   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 385     0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
 386   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 387     0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
 388   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 389     0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
 390   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 391     0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
 392   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 393     0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
 394   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 395     0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
 396   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 397     0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
 398   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 399     0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
 400   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 401     0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
 402   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 403     0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
 404   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 405     0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
 406   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
 407     0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
 408   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
 409     0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
 410
 411   /* ARMv8-M Mainline Security Extensions instructions.  */
 412   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
 413     0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
 414   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
 415     0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
 416
 417   /* Register load/store.  */
 418   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 419     0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
 420   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 421     0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
 422   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 423     0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
 424   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 425     0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
 426   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 427     0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
 428   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 429     0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
 430   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 431     0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
 432   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 433     0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
 434   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 435     0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
 436   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 437     0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
 438   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 439     0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
 440   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 441     0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
 442   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 443     0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
 444   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 445     0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
 446   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 447     0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
 448   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 449     0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
 450
 451   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 452     0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 453   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 454     0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 455   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 456     0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 457   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 458     0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 459
 460   /* Data transfer between ARM and NEON registers.  */
 461   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 462     0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
 463   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 464     0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
 465   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 466     0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
 467   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 468     0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
 469   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 470     0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
 471   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 472     0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
 473   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 474     0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
 475   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 476     0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
 477   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 478     0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
 479   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 480     0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
 481   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 482     0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
 483   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 484     0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
 485   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 486     0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
 487   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 488     0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
 489   /* Half-precision conversion instructions.  */
 490   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 491     0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
 492   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 493     0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
 494   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
 495     0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
 496   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
 497     0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
 498
 499   /* Floating point coprocessor (VFP) instructions.  */
 500   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 501     0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
 502   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 503     0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
 504   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 505     0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
 506   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 507     0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
 508   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 509     0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
 510   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 511     0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
 512   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 513     0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
 514   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 515     0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
 516   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 517     0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
 518   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 519     0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
 520   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 521     0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
 522   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 523     0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
 524   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 525     0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
 526   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 527     0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
 528   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 529     0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
 530   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 531     0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
 532   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 533     0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
 534   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 535     0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
 536   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 537     0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
 538   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 539     0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
 540   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 541     0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
 542   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 543     0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
 544   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 545     0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
 546   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 547     0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
 548   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 549     0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
 550   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 551     0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
 552   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 553     0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
 554   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 555     0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
 556   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 557     0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
 558   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 559     0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
 560   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 561     0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
 562   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 563     0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
 564   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 565     0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
 566   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 567     0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
 568   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 569     0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
 570   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 571     0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
 572   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 573     0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
 574   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 575     0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
 576   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 577     0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
 578   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 579     0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
 580   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 581     0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
 582   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 583     0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
 584   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 585     0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
 586   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 587     0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
 588   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 589     0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
 590   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 591     0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
 592   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 593     0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
 594   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 595     0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
 596   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 597     0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
 598   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 599     0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
 600   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 601     0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
 602   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 603     0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
 604   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 605     0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
 606   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 607     0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
 608   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 609     0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
 610   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 611     0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
 612   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 613     0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
 614   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 615     0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
 616   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 617     0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
 618   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 619     0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
 620   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 621     0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
 622   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 623     0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
 624   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 625     0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
 626   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 627     0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
 628   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 629     0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
 630   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 631     0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
 632   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 633     0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
 634   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 635     0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
 636   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 637     0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
 638
 639   /* Cirrus coprocessor instructions.  */
 640   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 641     0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
 642   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 643     0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
 644   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 645     0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
 646   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 647     0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
 648   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 649     0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
 650   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 651     0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
 652   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 653     0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
 654   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 655     0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
 656   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 657     0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
 658   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 659     0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
 660   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 661     0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
 662   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 663     0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
 664   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 665     0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
 666   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 667     0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
 668   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 669     0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
 670   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 671     0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
 672   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 673     0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
 674   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 675     0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
 676   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 677     0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
 678   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 679     0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
 680   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 681     0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
 682   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 683     0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
 684   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 685     0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
 686   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 687     0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
 688   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 689     0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
 690   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 691     0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
 692   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 693     0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
 694   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 695     0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
 696   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 697     0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
 698   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 699     0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
 700   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 701     0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
 702   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 703     0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
 704   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 705     0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
 706   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 707     0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
 708   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 709     0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
 710   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 711     0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
 712   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 713     0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
 714   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 715     0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
 716   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 717     0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
 718   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 719     0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
 720   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 721     0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
 722   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 723     0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
 724   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 725     0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
 726   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 727     0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
 728   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 729     0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
 730   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 731     0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
 732   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 733     0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
 734   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 735     0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
 736   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 737     0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
 738   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 739     0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
 740   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 741     0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
 742   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 743     0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
 744   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 745     0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
 746   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 747     0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
 748   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 749     0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
 750   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 751     0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
 752   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 753     0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
 754   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 755     0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
 756   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 757     0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
 758   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 759     0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
 760   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 761     0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
 762   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 763     0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
 764   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 765     0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 766   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 767     0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 768   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 769     0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 770   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 771     0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 772   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 773     0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 774   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 775     0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 776   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 777     0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
 778   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 779     0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
 780   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 781     0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
 782   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 783     0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
 784   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 785     0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 786   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 787     0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 788   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 789     0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 790   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 791     0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 792   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 793     0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 794   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 795     0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 796   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 797     0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 798   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 799     0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 800   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 801     0x0e000600, 0x0ff00f10,
 802     "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 803   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 804     0x0e100600, 0x0ff00f10,
 805     "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 806   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 807     0x0e200600, 0x0ff00f10,
 808     "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
 809   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 810     0x0e300600, 0x0ff00f10,
 811     "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
 812
 813   /* VFP Fused multiply add instructions.  */
 814   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 815     0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
 816   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 817     0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
 818   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 819     0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
 820   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 821     0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
 822   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 823     0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
 824   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 825     0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
 826   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 827     0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
 828   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 829     0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
 830
 831   /* FP v5.  */
 832   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 833     0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
 834   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 835     0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
 836   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 837     0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
 838   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 839     0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
 840   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 841     0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
 842   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 843     0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
 844   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 845     0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
 846   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 847     0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
 848   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 849     0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
 850   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 851     0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
 852   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 853     0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
 854   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 855     0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
 856
 857   /* Generic coprocessor instructions.  */
 858   {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
 859   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
 860     0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
 861   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
 862     0x0c500000, 0x0ff00000,
 863     "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
 864   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 865     0x0e000000, 0x0f000010,
 866     "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
 867   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 868     0x0e10f010, 0x0f10f010,
 869     "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
 870   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 871     0x0e100010, 0x0f100010,
 872     "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 873   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 874     0x0e000010, 0x0f100010,
 875     "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
 876   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 877     0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
 878   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 879     0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
 880
 881   /* V6 coprocessor instructions.  */
 882   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
 883     0xfc500000, 0xfff00000,
 884     "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
 885   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
 886     0xfc400000, 0xfff00000,
 887     "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
 888
 889   /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8.  */
 890   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 891     0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
 892   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 893     0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
 894   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 895     0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
 896   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 897     0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
 898   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 899     0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
 900   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 901     0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
 902   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 903     0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
 904   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 905     0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
 906   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 907     0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
 908   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 909     0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
 910
 911   /* Dot Product instructions in the space of coprocessor 13.  */
 912   {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
 913     0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
 914   {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
 915     0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
 916
 917   /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8.  */
 918   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 919     0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
 920   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 921     0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
 922   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 923     0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
 924   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 925     0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
 926   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 927     0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
 928   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 929     0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
 930   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 931     0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
 932   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 933     0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
 934
 935   /* V5 coprocessor instructions.  */
 936   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 937     0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
 938   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 939     0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
 940   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 941     0xfe000000, 0xff000010,
 942     "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
 943   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 944     0xfe000010, 0xff100010,
 945     "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
 946   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 947     0xfe100010, 0xff100010,
 948     "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 949
 950   /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
 951      cp_num: bit <11:8> == 0b1001.
 952      cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE.  */
 953   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 954     0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
 955   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 956     0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
 957   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 958     0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
 959   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 960     0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
 961   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 962     0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
 963   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 964     0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
 965   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 966     0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
 967   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 968     0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
 969   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 970     0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
 971   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 972     0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
 973   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 974     0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
 975   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 976     0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
 977   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 978     0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
 979   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 980     0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
 981   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 982     0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
 983   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 984     0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
 985   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 986     0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
 987   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 988     0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
 989   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 990     0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
 991   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 992     0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
 993   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 994     0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
 995   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 996     0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
 997   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 998     0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
 999   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1000     0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1001   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1002     0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1003   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1004     0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1005   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1006     0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1007   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1008     0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1009   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1010     0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1011   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1012     0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1013   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1014     0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1015   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1016     0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1017   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1018     0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1019   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1020     0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1021   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1022     0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1023
1024   /* ARMv8.3 javascript conversion instruction.  */
1025   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1026     0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1027
1028   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1029 };
1030
1031 /* Neon opcode table:  This does not encode the top byte -- that is
1032    checked by the print_insn_neon routine, as it depends on whether we are
1033    doing thumb32 or arm32 disassembly.  */
1034
1035 /* print_insn_neon recognizes the following format control codes:
1036
1037    %%                   %
1038
1039    %c                   print condition code
1040    %u                   print condition code (unconditional in ARM mode,
1041                           UNPREDICTABLE if not AL in Thumb)
1042    %A                   print v{st,ld}[1234] operands
1043    %B                   print v{st,ld}[1234] any one operands
1044    %C                   print v{st,ld}[1234] single->all operands
1045    %D                   print scalar
1046    %E                   print vmov, vmvn, vorr, vbic encoded constant
1047    %F                   print vtbl,vtbx register list
1048
1049    %<bitfield>r         print as an ARM register
1050    %<bitfield>d         print the bitfield in decimal
1051    %<bitfield>e         print the 2^N - bitfield in decimal
1052    %<bitfield>D         print as a NEON D register
1053    %<bitfield>Q         print as a NEON Q register
1054    %<bitfield>R         print as a NEON D or Q register
1055    %<bitfield>Sn        print byte scaled width limited by n
1056    %<bitfield>Tn        print short scaled width limited by n
1057    %<bitfield>Un        print long scaled width limited by n
1058
1059    %<bitfield>'c        print specified char iff bitfield is all ones
1060    %<bitfield>`c        print specified char iff bitfield is all zeroes
1061    %<bitfield>?ab...    select from array of values in big endian order.  */
1062
1063 static const struct opcode32 neon_opcodes[] =
1064 {
1065   /* Extract.  */
1066   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1067     0xf2b00840, 0xffb00850,
1068     "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1069   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1070     0xf2b00000, 0xffb00810,
1071     "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1072
1073   /* Move data element to all lanes.  */
1074   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1075     0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1076   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1077     0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1078   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1079     0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1080
1081   /* Table lookup.  */
1082   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1083     0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1084   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1085     0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1086
1087   /* Half-precision conversions.  */
1088   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1089     0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1090   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1091     0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1092
1093   /* NEON fused multiply add instructions.  */
1094   {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1095     0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1096   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1097     0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1098   {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1099     0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1100   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1101     0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1102
1103   /* Two registers, miscellaneous.  */
1104   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1105     0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1106   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1107     0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1108   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1109     0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1110   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1111     0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1112   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1113     0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1114   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1115     0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1116   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1117     0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1118   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1119     0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1120   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1121     0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1122   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1123     0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1124   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1125     0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1126   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1127     0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1128   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1129     0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1130   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1131     0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1132   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1133     0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1134   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1135     0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1136   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1137     0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1138   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1139     0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1140   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1141     0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1142   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1143     0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1144   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1145     0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1146   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1147     0xf3b20300, 0xffb30fd0,
1148     "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1149   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1150     0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1151   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1152     0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1153   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1154     0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1155   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1156     0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1157   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1158     0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1159   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1160     0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1161   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1162     0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1163   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1164     0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1165   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1166     0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1167   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1168     0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1169   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1170     0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1171   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1172     0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1173   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1174     0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1175   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1176     0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1177   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1178     0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1179   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1180     0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1181   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1182     0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1183   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1184     0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1185   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1186     0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1187   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1188     0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1189   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1190     0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1191   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1192     0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1193   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1194     0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1195   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1196     0xf3bb0600, 0xffbf0e10,
1197     "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1198   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1199     0xf3b70600, 0xffbf0e10,
1200     "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1201
1202   /* Three registers of the same length.  */
1203   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1204     0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1205   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1206     0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1207   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1208     0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1209   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1210     0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1211   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1212     0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1213   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1214     0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1215   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1216     0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1217   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1218     0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1219   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1220     0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1221   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1222     0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1223   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1224     0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1225   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1226     0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1227   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1228     0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1229   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1230     0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1231   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1232     0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1233   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1234     0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1235   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1236     0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1237   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1238     0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1239   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1240     0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1241   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1242     0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1243   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1244     0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1245   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1246     0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1247   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1248     0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1249   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1250     0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1251   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1252     0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1253   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1254     0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1255   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1256     0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1257   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1258     0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1259   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1260     0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1261   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1262     0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1263   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1264     0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1265   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1266     0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1267   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1268     0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1269   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1270     0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1271   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1272     0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1273   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1274     0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1275   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1276     0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1277   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1278     0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1279   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1280     0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1281   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1282     0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1283   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1284     0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1285   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1286     0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1287   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1288     0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1289   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1290     0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1291   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1292     0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1293   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1294     0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1295   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1296     0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1297   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1298     0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1299   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1300     0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1301   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1302     0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1303   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1304     0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1305   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1306     0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1307   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1308     0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1309   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1310     0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1311   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1312     0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1313   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1314     0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1315   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1316     0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1317   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1318     0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1319   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1320     0xf2000b00, 0xff800f10,
1321     "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1322   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1323     0xf2000b10, 0xff800f10,
1324     "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1325   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1326     0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1327   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1328     0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1329   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1330     0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1331   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1332     0xf3000b00, 0xff800f10,
1333     "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1334   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1335     0xf2000000, 0xfe800f10,
1336     "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1337   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1338     0xf2000010, 0xfe800f10,
1339     "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1340   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1341     0xf2000100, 0xfe800f10,
1342     "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1343   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1344     0xf2000200, 0xfe800f10,
1345     "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1346   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1347     0xf2000210, 0xfe800f10,
1348     "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1349   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1350     0xf2000300, 0xfe800f10,
1351     "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1352   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1353     0xf2000310, 0xfe800f10,
1354     "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1355   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1356     0xf2000400, 0xfe800f10,
1357     "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1358   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1359     0xf2000410, 0xfe800f10,
1360     "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1361   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1362     0xf2000500, 0xfe800f10,
1363     "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1364   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1365     0xf2000510, 0xfe800f10,
1366     "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1367   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1368     0xf2000600, 0xfe800f10,
1369     "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1370   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1371     0xf2000610, 0xfe800f10,
1372     "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1373   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1374     0xf2000700, 0xfe800f10,
1375     "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1376   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1377     0xf2000710, 0xfe800f10,
1378     "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1379   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1380     0xf2000910, 0xfe800f10,
1381     "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1382   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1383     0xf2000a00, 0xfe800f10,
1384     "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1385   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1386     0xf2000a10, 0xfe800f10,
1387     "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1388   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1389     0xf3000b10, 0xff800f10,
1390     "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1391   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1392     0xf3000c10, 0xff800f10,
1393     "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1394
1395   /* One register and an immediate value.  */
1396   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1397     0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1398   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1399     0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1400   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1401     0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1402   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1403     0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1404   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1405     0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1406   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1407     0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1408   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1409     0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1410   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1411     0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1412   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1413     0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1414   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1415     0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1416   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1417     0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1418   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1419     0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1420   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1421     0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1422
1423   /* Two registers and a shift amount.  */
1424   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1425     0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1426   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1427     0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1428   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1429     0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1430   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1431     0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1432   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1433     0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1434   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1435     0xf2880950, 0xfeb80fd0,
1436     "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1437   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1438     0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1439   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1440     0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1441   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1442     0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1443   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1444     0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1445   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1446     0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1447   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1448     0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1449   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1450     0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1451   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1452     0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1453   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1454     0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1455   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1456     0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1457   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1458     0xf2900950, 0xfeb00fd0,
1459     "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1460   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1461     0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1462   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1463     0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1464   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1465     0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1466   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1467     0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1468   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1469     0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1470   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1471     0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1472   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1473     0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1474   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1475     0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1476   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1477     0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1478   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1479     0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1480   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1481     0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1482   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1483     0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1484   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1485     0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1486   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1487     0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1488   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1489     0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1490   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1491     0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1492   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1493     0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1494   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1495     0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1496   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1497     0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1498   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1499     0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1500   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1501     0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1502   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1503     0xf2a00950, 0xfea00fd0,
1504     "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1505   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506     0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1507   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508     0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1509   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510     0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1511   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1512     0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1513   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1514     0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1515   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516     0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1517   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1518     0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1519   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1520     0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1521   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1522     0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1523   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1524     0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1525   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1526     0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1527   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1528     0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1529   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1530     0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1531   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1532     0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1533   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1534     0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1535   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1536     0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1537   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1538     0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1539   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1540     0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1541   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1542     0xf2a00e10, 0xfea00e90,
1543     "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1544   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1545     0xf2a00c10, 0xfea00e90,
1546     "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
1547
1548   /* Three registers of different lengths.  */
1549   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1550     0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1551   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1552     0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1553   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1554     0xf2800400, 0xff800f50,
1555     "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1556   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1557     0xf2800600, 0xff800f50,
1558     "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1559   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1560     0xf2800900, 0xff800f50,
1561     "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1562   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1563     0xf2800b00, 0xff800f50,
1564     "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1565   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1566     0xf2800d00, 0xff800f50,
1567     "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1568   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1569     0xf3800400, 0xff800f50,
1570     "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1571   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1572     0xf3800600, 0xff800f50,
1573     "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1574   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1575     0xf2800000, 0xfe800f50,
1576     "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1577   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1578     0xf2800100, 0xfe800f50,
1579     "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1580   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1581     0xf2800200, 0xfe800f50,
1582     "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1583   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1584     0xf2800300, 0xfe800f50,
1585     "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1586   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1587     0xf2800500, 0xfe800f50,
1588     "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1589   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1590     0xf2800700, 0xfe800f50,
1591     "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1592   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1593     0xf2800800, 0xfe800f50,
1594     "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1595   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1596     0xf2800a00, 0xfe800f50,
1597     "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1598   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1599     0xf2800c00, 0xfe800f50,
1600     "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1601
1602   /* Two registers and a scalar.  */
1603   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1604     0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1605   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1606     0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1607   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1608     0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1609   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1610     0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1611   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1612     0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1613   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1614     0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1615   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1616     0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1617   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1618     0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1619   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1620     0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1621   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1622     0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1623   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1624     0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1625   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1626     0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1627   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1628     0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1629   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1630     0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1631   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1632     0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1633   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1634     0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1635   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1636     0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1637   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1638     0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1639   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1640     0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1641   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1642     0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1643   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1644     0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1645   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1646     0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1647   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1648     0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1649   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1650     0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1651   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1652     0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1653   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1654     0xf2800240, 0xfe800f50,
1655     "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1656   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1657     0xf2800640, 0xfe800f50,
1658     "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1659   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1660     0xf2800a40, 0xfe800f50,
1661     "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1662   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1663     0xf2800e40, 0xff800f50,
1664    "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1665   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1666     0xf2800f40, 0xff800f50,
1667    "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1668   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1669     0xf3800e40, 0xff800f50,
1670    "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1671   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1672     0xf3800f40, 0xff800f50,
1673    "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1674   },
1675
1676   /* Element and structure load/store.  */
1677   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1678     0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1679   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1680     0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1681   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1682     0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1683   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1684     0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1685   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1686     0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1687   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1688     0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1689   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1690     0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1691   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1692     0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1693   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1694     0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1695   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1696     0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1697   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1698     0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1699   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1700     0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1701   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1702     0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1703   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1704     0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1705   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1706     0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1707   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1708     0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1709   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1710     0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1711   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1712     0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1713   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1714     0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1715
1716   {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
1717 };
1718
1719 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb.  All three are partially
1720    ordered: they must be searched linearly from the top to obtain a correct
1721    match.  */
1722
1723 /* print_insn_arm recognizes the following format control codes:
1724
1725    %%                   %
1726
1727    %a                   print address for ldr/str instruction
1728    %s                   print address for ldr/str halfword/signextend instruction
1729    %S                   like %s but allow UNPREDICTABLE addressing
1730    %b                   print branch destination
1731    %c                   print condition code (always bits 28-31)
1732    %m                   print register mask for ldm/stm instruction
1733    %o                   print operand2 (immediate or register + shift)
1734    %p                   print 'p' iff bits 12-15 are 15
1735    %t                   print 't' iff bit 21 set and bit 24 clear
1736    %B                   print arm BLX(1) destination
1737    %C                   print the PSR sub type.
1738    %U                   print barrier type.
1739    %P                   print address for pli instruction.
1740
1741    %<bitfield>r         print as an ARM register
1742    %<bitfield>T         print as an ARM register + 1
1743    %<bitfield>R         as %r but r15 is UNPREDICTABLE
1744    %<bitfield>{r|R}u    as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1745    %<bitfield>{r|R}U    as %{r|R} but if matches the other %U field then is UNPREDICTABLE
1746    %<bitfield>d         print the bitfield in decimal
1747    %<bitfield>W         print the bitfield plus one in decimal
1748    %<bitfield>x         print the bitfield in hex
1749    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
1750
1751    %<bitfield>'c        print specified char iff bitfield is all ones
1752    %<bitfield>`c        print specified char iff bitfield is all zeroes
1753    %<bitfield>?ab...    select from array of values in big endian order
1754
1755    %e                   print arm SMI operand (bits 0..7,8..19).
1756    %E                   print the LSB and WIDTH fields of a BFI or BFC instruction.
1757    %V                   print the 16-bit immediate field of a MOVT or MOVW instruction.
1758    %R                   print the SPSR/CPSR or banked register of an MRS.  */
1759
1760 static const struct opcode32 arm_opcodes[] =
1761 {
1762   /* ARM instructions.  */
1763   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1764     0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1765   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1766     0xe7f000f0, 0xfff000f0, "udf\t#%e"},
1767
1768   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
1769     0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1770   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1771     0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1772   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1773     0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1774   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
1775     0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1776   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1777     0x00800090, 0x0fa000f0,
1778     "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1779   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1780     0x00a00090, 0x0fa000f0,
1781     "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1782
1783   /* V8.2 RAS extension instructions.  */
1784   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
1785     0xe320f010, 0xffffffff, "esb"},
1786
1787   /* V8 instructions.  */
1788   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1789     0x0320f005, 0x0fffffff, "sevl"},
1790   /* Defined in V8 but is in NOP space so available to all arch.  */
1791   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1792     0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
1793   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
1794     0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
1795   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1796     0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1797   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1798     0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
1799   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1800     0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
1801   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1802     0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
1803   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1804     0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
1805   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1806     0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
1807   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1808     0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
1809   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1810     0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
1811   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1812     0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
1813   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1814     0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
1815   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1816     0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
1817   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1818     0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
1819   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1820     0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
1821   /* CRC32 instructions.  */
1822   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1823     0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
1824   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1825     0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
1826   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1827     0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
1828   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1829     0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
1830   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1831     0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
1832   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1833     0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
1834
1835   /* Privileged Access Never extension instructions.  */
1836   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
1837     0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
1838
1839   /* Virtualization Extension instructions.  */
1840   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
1841   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
1842
1843   /* Integer Divide Extension instructions.  */
1844   {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1845     0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
1846   {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1847     0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
1848
1849   /* MP Extension instructions.  */
1850   {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
1851
1852   /* Speculation Barriers.  */
1853   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
1854   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
1855   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
1856
1857   /* V7 instructions.  */
1858   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
1859   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
1860   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
1861   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
1862   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
1863   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
1864   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
1865    {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
1866     0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
1867
1868   /* ARM V6T2 instructions.  */
1869   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1870     0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
1871   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1872     0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
1873   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1874     0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1875   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1876     0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
1877
1878   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1879     0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
1880   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1881     0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
1882
1883   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
1884     0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
1885   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
1886     0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
1887   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1888     0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
1889   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1890     0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
1891
1892   /* ARM Security extension instructions.  */
1893   {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
1894     0x01600070, 0x0ff000f0, "smc%c\t%e"},
1895
1896   /* ARM V6K instructions.  */
1897   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1898     0xf57ff01f, 0xffffffff, "clrex"},
1899   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1900     0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
1901   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1902     0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
1903   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1904     0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
1905   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1906     0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
1907   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1908     0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
1909   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1910     0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
1911
1912   /* ARMv8.5-A instructions.  */
1913   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
1914
1915   /* ARM V6K NOP hints.  */
1916   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1917     0x0320f001, 0x0fffffff, "yield%c"},
1918   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1919     0x0320f002, 0x0fffffff, "wfe%c"},
1920   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1921     0x0320f003, 0x0fffffff, "wfi%c"},
1922   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1923     0x0320f004, 0x0fffffff, "sev%c"},
1924   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1925     0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
1926
1927   /* ARM V6 instructions.  */
1928   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1929     0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
1930   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1931     0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
1932   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1933     0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
1934   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1935     0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
1936   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1937     0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
1938   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1939     0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
1940   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1941     0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
1942   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1943     0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
1944   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1945     0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
1946   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1947     0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
1948   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1949     0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
1950   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1951     0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
1952   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1953     0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
1954   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1955     0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
1956   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1957     0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
1958   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1959     0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
1960   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1961     0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
1962   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1963     0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
1964   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1965     0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
1966   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1967     0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
1968   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1969     0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
1970   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1971     0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
1972   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1973     0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
1974   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1975     0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
1976   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1977     0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
1978   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1979     0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
1980   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1981     0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
1982   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1983     0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
1984   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1985     0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
1986   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1987     0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
1988   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1989     0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
1990   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1991     0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
1992   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1993     0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
1994   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1995     0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
1996   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1997     0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
1998   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1999     0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
2000   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2001     0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
2002   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2003     0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
2004   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2005     0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
2006   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2007     0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
2008   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2009     0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
2010   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2011     0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
2012   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2013     0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
2014   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2015     0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
2016   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2017     0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
2018   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2019     0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
2020   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2021     0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
2022   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2023     0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
2024   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2025     0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
2026   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2027     0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
2028   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2029     0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
2030   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2031     0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
2032   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2033     0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
2034   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2035     0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
2036   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2037     0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
2038   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2039     0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
2040   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2041     0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
2042   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2043     0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
2044   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2045     0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
2046   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2047     0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
2048   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2049     0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
2050   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2051     0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
2052   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2053     0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
2054   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2055     0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
2056   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2057     0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
2058   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2059     0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
2060   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2061     0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
2062   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2063     0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
2064   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2065     0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
2066   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2067     0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
2068   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2069     0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
2070   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2071     0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
2072   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2073     0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
2074   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2075     0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
2076   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2077     0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
2078   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2079     0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2080   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2081     0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2082   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2083     0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2084   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2085     0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
2086   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2087     0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2088   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2089     0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2090   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2091     0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2092   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2093     0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
2094   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2095     0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2096   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2097     0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2098   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2099     0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2100   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2101     0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
2102   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2103     0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2104   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2105     0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2106   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2107     0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2108   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2109     0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
2110   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2111     0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2112   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2113     0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2114   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2115     0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
2116   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2117     0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
2118   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2119     0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2120   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2121     0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2122   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2123     0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2124   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2125     0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
2126   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2127     0xf1010000, 0xfffffc00, "setend\t%9?ble"},
2128   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2129     0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
2130   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2131     0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
2132   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2133     0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2134   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2135     0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2136   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2137     0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2138   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2139     0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2140   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2141     0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
2142   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2143     0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2144   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2145     0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2146   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2147     0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
2148   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2149     0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
2150   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2151     0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
2152   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2153     0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
2154   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2155     0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
2156   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2157     0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
2158   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2159     0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
2160   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2161     0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
2162   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2163     0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2164   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2165     0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
2166   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2167     0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
2168   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2169     0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
2170   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2171     0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
2172
2173   /* V5J instruction.  */
2174   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
2175     0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
2176
2177   /* V5 Instructions.  */
2178   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2179     0xe1200070, 0xfff000f0,
2180     "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
2181   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2182     0xfa000000, 0xfe000000, "blx\t%B"},
2183   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2184     0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
2185   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2186     0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
2187
2188   /* V5E "El Segundo" Instructions.  */
2189   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2190     0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
2191   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2192     0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
2193   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2194     0xf450f000, 0xfc70f000, "pld\t%a"},
2195   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2196     0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2197   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2198     0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2199   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2200     0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2201   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2202     0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
2203
2204   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2205     0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2206   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2207     0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
2208
2209   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2210     0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2211   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2212     0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2213   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2214     0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2215   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2216     0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2217
2218   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2219     0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2220   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2221     0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2222   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2223     0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2224   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2225     0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2226
2227   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2228     0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2229   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2230     0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2231
2232   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2233     0x01000050, 0x0ff00ff0,  "qadd%c\t%12-15R, %0-3R, %16-19R"},
2234   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2235     0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2236   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2237     0x01200050, 0x0ff00ff0,  "qsub%c\t%12-15R, %0-3R, %16-19R"},
2238   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2239     0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
2240
2241   /* ARM Instructions.  */
2242   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2243     0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2244
2245   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2246     0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2247   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2248     0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2249   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2250     0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2251   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2252     0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2253   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2254     0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2255   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2256     0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2257
2258   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2259     0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2260   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2261     0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2262   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2263     0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2264   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2265     0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2266
2267   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2268     0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2269   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2270     0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2271   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2272     0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2273   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2274     0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2275
2276   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2277     0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2278   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2279     0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2280   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2281     0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2282
2283   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2284     0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2285   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2286     0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2287   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2288     0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2289
2290   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2291     0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2292   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2293     0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2294   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2295     0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2296
2297   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2298     0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2299   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2300     0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2301   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2302     0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2303
2304   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2305     0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2306   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2307     0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2308   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2309     0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2310
2311   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2312     0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2313   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2314     0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2315   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2316     0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2317
2318   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2319     0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2320   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2321     0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2322   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2323     0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2324
2325   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2326     0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2327   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2328     0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2329   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2330     0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2331
2332   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2333     0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2334   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2335     0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2336   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2337     0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2338
2339   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2340     0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2341   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2342     0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2343   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2344     0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2345
2346   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2347     0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
2348   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2349     0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
2350   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2351     0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
2352
2353   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2354     0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2355   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2356     0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2357   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2358     0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2359
2360   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2361     0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2362   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2363     0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2364   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2365     0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2366
2367   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2368     0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2369   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2370     0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2371   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2372     0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2373
2374   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2375     0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2376   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2377     0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2378   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2379     0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2380   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2381     0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2382   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2383     0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2384   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2385     0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2386   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2387     0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2388
2389   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2390     0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2391   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2392     0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2393   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2394     0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2395
2396   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2397     0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2398   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2399     0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2400   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2401     0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2402
2403   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2404     0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2405   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2406     0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2407
2408   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2409     0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2410
2411   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2412     0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2413   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2414     0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2415
2416   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2417     0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2418   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2419     0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2420   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2421     0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2422   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2423     0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2424   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2425     0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2426   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2427     0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2428   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2429     0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2430   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2431     0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2432   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2433     0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2434   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2435     0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2436   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2437     0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2438   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2439     0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2440   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2441     0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2442   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2443     0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2444   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2445     0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2446   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2447     0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2448   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2449     0x092d0000, 0x0fff0000, "push%c\t%m"},
2450   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2451     0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2452   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2453     0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2454
2455   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2456     0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2457   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2458     0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2459   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2460     0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2461   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2462     0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2463   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2464     0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2465   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2466     0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2467   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2468     0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2469   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2470     0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2471   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2472     0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2473   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2474     0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2475   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2476     0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2477   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2478     0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2479   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2480     0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2481   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2482     0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2483   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2484     0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2485   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2486     0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2487   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2488     0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2489   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2490     0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2491   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2492     0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2493
2494   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2495     0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2496   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2497     0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
2498
2499   /* The rest.  */
2500   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2501     0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
2502   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2503     0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2504   {ARM_FEATURE_CORE_LOW (0),
2505     0x00000000, 0x00000000, 0}
2506 };
2507
2508 /* print_insn_thumb16 recognizes the following format control codes:
2509
2510    %S                   print Thumb register (bits 3..5 as high number if bit 6 set)
2511    %D                   print Thumb register (bits 0..2 as high number if bit 7 set)
2512    %<bitfield>I         print bitfield as a signed decimal
2513                                 (top bit of range being the sign bit)
2514    %N                   print Thumb register mask (with LR)
2515    %O                   print Thumb register mask (with PC)
2516    %M                   print Thumb register mask
2517    %b                   print CZB's 6-bit unsigned branch destination
2518    %s                   print Thumb right-shift immediate (6..10; 0 == 32).
2519    %c                   print the condition code
2520    %C                   print the condition code, or "s" if not conditional
2521    %x                   print warning if conditional an not at end of IT block"
2522    %X                   print "\t; unpredictable <IT:code>" if conditional
2523    %I                   print IT instruction suffix and operands
2524    %W                   print Thumb Writeback indicator for LDMIA
2525    %<bitfield>r         print bitfield as an ARM register
2526    %<bitfield>d         print bitfield as a decimal
2527    %<bitfield>H         print (bitfield * 2) as a decimal
2528    %<bitfield>W         print (bitfield * 4) as a decimal
2529    %<bitfield>a         print (bitfield * 4) as a pc-rel offset + decoded symbol
2530    %<bitfield>B         print Thumb branch destination (signed displacement)
2531    %<bitfield>c         print bitfield as a condition code
2532    %<bitnum>'c          print specified char iff bit is one
2533    %<bitnum>?ab         print a if bit is one else print b.  */
2534
2535 static const struct opcode16 thumb_opcodes[] =
2536 {
2537   /* Thumb instructions.  */
2538
2539   /* ARMv8-M Security Extensions instructions.  */
2540   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
2541   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
2542
2543   /* ARM V8 instructions.  */
2544   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xbf50, 0xffff, "sevl%c"},
2545   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xba80, 0xffc0, "hlt\t%0-5x"},
2546   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),  0xb610, 0xfff7, "setpan\t#%3-3d"},
2547
2548   /* ARM V6K no-argument instructions.  */
2549   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2550   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2551   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2552   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2553   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2554   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
2555
2556   /* ARM V6T2 instructions.  */
2557   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2558     0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2559   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2560     0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
2561   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
2562
2563   /* ARM V6.  */
2564   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2565   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2566   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2567   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2568   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2569   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2570   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2571   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2572   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2573   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2574   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
2575
2576   /* ARM V5 ISA extends Thumb.  */
2577   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2578     0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional.  */
2579   /* This is BLX(2).  BLX(1) is a 32-bit instruction.  */
2580   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2581     0x4780, 0xff87, "blx%c\t%3-6r%x"},  /* note: 4 bit register number.  */
2582   /* ARM V4T ISA (Thumb v1).  */
2583   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2584     0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
2585   /* Format 4.  */
2586   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2587   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2588   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2589   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2590   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2591   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2592   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2593   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2594   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2595   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2596   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2597   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2598   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2599   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2600   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2601   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
2602   /* format 13 */
2603   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2604   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
2605   /* format 5 */
2606   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
2607   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
2608   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2609   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
2610   /* format 14 */
2611   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
2612   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
2613   /* format 2 */
2614   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2615     0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2616   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2617     0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2618   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2619     0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2620   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2621     0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
2622   /* format 8 */
2623   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2624     0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2625   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2626     0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2627   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2628     0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
2629   /* format 7 */
2630   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2631     0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2632   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2633     0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2634   /* format 1 */
2635   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2636   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2637     0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2638   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2639   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
2640   /* format 3 */
2641   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2642   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2643   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2644   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
2645   /* format 6 */
2646   /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2647   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2648     0x4800, 0xF800,
2649     "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
2650   /* format 9 */
2651   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2652     0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2653   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2654     0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2655   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2656     0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2657   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2658     0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
2659   /* format 10 */
2660   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2661     0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2662   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2663     0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
2664   /* format 11 */
2665   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2666     0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2667   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2668     0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
2669   /* format 12 */
2670   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2671     0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2672   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2673     0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
2674   /* format 15 */
2675   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2676   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
2677   /* format 17 */
2678   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
2679   /* format 16 */
2680   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2681   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
2682   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
2683   /* format 18 */
2684   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
2685
2686   /* The E800 .. FFFF range is unconditionally redirected to the
2687      32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2688      are processed via that table.  Thus, we can never encounter a
2689      bare "second half of BL/BLX(1)" instruction here.  */
2690   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),  0x0000, 0x0000, UNDEFINED_INSTRUCTION},
2691   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2692 };
2693
2694 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
2695    We adopt the convention that hw1 is the high 16 bits of .value and
2696    .mask, hw2 the low 16 bits.
2697
2698    print_insn_thumb32 recognizes the following format control codes:
2699
2700        %%               %
2701
2702        %I               print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2703        %M               print a modified 12-bit immediate (same location)
2704        %J               print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2705        %K               print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
2706        %H               print a 16-bit immediate from hw2[3:0],hw1[11:0]
2707        %S               print a possibly-shifted Rm
2708
2709        %L               print address for a ldrd/strd instruction
2710        %a               print the address of a plain load/store
2711        %w               print the width and signedness of a core load/store
2712        %m               print register mask for ldm/stm
2713        %n               print register mask for clrm
2714
2715        %E               print the lsb and width fields of a bfc/bfi instruction
2716        %F               print the lsb and width fields of a sbfx/ubfx instruction
2717        %G               print a fallback offset for Branch Future instructions
2718        %W               print an offset for BF instruction
2719        %Y               print an offset for BFL instruction
2720        %Z               print an offset for BFCSEL instruction
2721        %Q               print an offset for Low Overhead Loop instructions
2722        %P               print an offset for Low Overhead Loop end instructions
2723        %b               print a conditional branch offset
2724        %B               print an unconditional branch offset
2725        %s               print the shift field of an SSAT instruction
2726        %R               print the rotation field of an SXT instruction
2727        %U               print barrier type.
2728        %P               print address for pli instruction.
2729        %c               print the condition code
2730        %x               print warning if conditional an not at end of IT block"
2731        %X               print "\t; unpredictable <IT:code>" if conditional
2732
2733        %<bitfield>d     print bitfield in decimal
2734        %<bitfield>D     print bitfield plus one in decimal
2735        %<bitfield>W     print bitfield*4 in decimal
2736        %<bitfield>r     print bitfield as an ARM register
2737        %<bitfield>R     as %<>r but r15 is UNPREDICTABLE
2738        %<bitfield>S     as %<>r but r13 and r15 is UNPREDICTABLE
2739        %<bitfield>c     print bitfield as a condition code
2740
2741        %<bitfield>'c    print specified char iff bitfield is all ones
2742        %<bitfield>`c    print specified char iff bitfield is all zeroes
2743        %<bitfield>?ab... select from array of values in big endian order
2744
2745    With one exception at the bottom (done because BL and BLX(1) need
2746    to come dead last), this table was machine-sorted first in
2747    decreasing order of number of bits set in the mask, then in
2748    increasing numeric order of mask, then in increasing numeric order
2749    of opcode.  This order is not the clearest for a human reader, but
2750    is guaranteed never to catch a special-case bit pattern with a more
2751    general mask, which is important, because this instruction encoding
2752    makes heavy use of special-case bit patterns.  */
2753 static const struct opcode32 thumb32_opcodes[] =
2754 {
2755   /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
2756      instructions.  */
2757   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2758     0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
2759   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2760     0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
2761   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2762     0xf02fc001, 0xfffff001, "le\t%P"},
2763   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2764     0xf00fc001, 0xfffff001, "le\tlr, %P"},
2765
2766   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2767     0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
2768   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2769     0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
2770   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2771     0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
2772   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2773     0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
2774   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2775     0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
2776
2777   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2778     0xe89f0000, 0xffff2000, "clrm%c\t%n"},
2779
2780   /* ARMv8-M and ARMv8-M Security Extensions instructions.  */
2781   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
2782   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2783     0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
2784   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2785     0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
2786   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2787     0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
2788   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2789     0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
2790
2791   /* ARM V8.2 RAS extension instructions.  */
2792   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
2793     0xf3af8010, 0xffffffff, "esb"},
2794
2795   /* V8 instructions.  */
2796   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2797     0xf3af8005, 0xffffffff, "sevl%c.w"},
2798   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2799     0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2800   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2801     0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
2802   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2803     0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
2804   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2805     0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
2806   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2807     0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
2808   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2809     0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
2810   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2811     0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
2812   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2813     0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
2814   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2815     0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2816   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2817     0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2818   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2819     0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
2820   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2821     0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2822   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2823     0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2824   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2825     0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2826   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2827     0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
2828
2829   /* CRC32 instructions.  */
2830   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2831     0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
2832   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2833     0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
2834   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2835     0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
2836   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2837     0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
2838   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2839     0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
2840   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2841     0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
2842
2843   /* Speculation Barriers.  */
2844   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
2845   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
2846   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
2847
2848   /* V7 instructions.  */
2849   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
2850   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
2851   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
2852   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
2853   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
2854   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
2855   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
2856   {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2857     0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
2858   {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2859     0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
2860
2861   /* Virtualization Extension instructions.  */
2862   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
2863   /* We skip ERET as that is SUBS pc, lr, #0.  */
2864
2865   /* MP Extension instructions.  */
2866   {ARM_FEATURE_CORE_LOW (ARM_EXT_MP),   0xf830f000, 0xff70f000, "pldw%c\t%a"},
2867
2868   /* Security extension instructions.  */
2869   {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),  0xf7f08000, 0xfff0f000, "smc%c\t%K"},
2870
2871   /* ARMv8.5-A instructions.  */
2872   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
2873
2874   /* Instructions defined in the basic V6T2 set.  */
2875   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
2876   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
2877   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
2878   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
2879   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
2880   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2881     0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
2882   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
2883
2884   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2885     0xf3bf8f2f, 0xffffffff, "clrex%c"},
2886   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2887     0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
2888   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2889     0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
2890   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2891     0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
2892   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2893     0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
2894   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2895     0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
2896   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2897     0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
2898   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2899     0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
2900   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2901     0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
2902   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2903     0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
2904   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2905     0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
2906   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2907     0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
2908   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2909     0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
2910   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2911     0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
2912   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2913     0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
2914   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2915     0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
2916   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2917     0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
2918   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2919     0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
2920   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2921     0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
2922   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2923     0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
2924   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2925     0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
2926   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2927     0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
2928   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2929     0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
2930   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2931     0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
2932   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2933     0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
2934   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2935     0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
2936   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2937     0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
2938   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2939     0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
2940   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2941     0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
2942   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2943     0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
2944   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2945     0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
2946   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2947     0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
2948   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2949     0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
2950   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2951     0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
2952   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2953     0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
2954   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2955     0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
2956   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2957     0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
2958   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2959     0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
2960   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2961     0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
2962   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2963     0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
2964   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2965     0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
2966   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2967     0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
2968   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2969     0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
2970   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2971     0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
2972   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2973     0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
2974   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2975     0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
2976   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2977     0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
2978   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2979     0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
2980   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2981     0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
2982   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2983     0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
2984   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2985     0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
2986   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2987     0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
2988   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2989     0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
2990   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2991     0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
2992   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2993     0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
2994   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2995     0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
2996   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2997     0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
2998   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2999     0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
3000   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3001     0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
3002   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3003     0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
3004   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3005     0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
3006   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3007     0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
3008   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3009     0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
3010   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3011     0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
3012   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3013     0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
3014   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3015     0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
3016   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3017     0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
3018   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3019     0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
3020   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3021     0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
3022   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3023     0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
3024   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3025     0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
3026   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3027     0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
3028   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3029     0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
3030   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3031     0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
3032   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3033     0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3034   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3035     0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3036   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3037     0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3038   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3039     0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
3040   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3041     0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
3042   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3043     0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
3044   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3045     0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
3046   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3047     0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
3048   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3049     0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3050   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3051     0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
3052   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3053     0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
3054   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3055     0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3056   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3057     0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3058   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3059     0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3060   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3061     0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3062   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3063     0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3064   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3065     0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3066   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3067     0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3068   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3069     0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
3070   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3071     0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
3072   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3073     0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
3074   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3075     0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
3076   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3077     0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
3078   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3079     0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
3080   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3081     0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
3082   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3083     0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
3084   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3085     0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
3086   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3087     0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
3088   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3089     0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
3090   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3091     0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
3092   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3093     0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3094   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3095     0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3096   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3097     0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3098   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3099     0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3100   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3101     0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3102   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3103     0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3104   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3105     0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3106   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3107     0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3108   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3109     0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
3110   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3111     0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
3112   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3113     0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
3114   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3115     0xf810f000, 0xff70f000, "pld%c\t%a"},
3116   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3117     0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3118   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3119     0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3120   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3121     0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3122   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3123     0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3124   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3125     0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3126   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3127     0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3128   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3129     0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3130   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3131     0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
3132   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3133     0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
3134   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3135     0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
3136   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3137     0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
3138   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3139     0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
3140   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3141     0xfb100000, 0xfff000c0,
3142     "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3143   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3144     0xfbc00080, 0xfff000c0,
3145     "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
3146   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3147     0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
3148   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3149     0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
3150   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3151     0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
3152   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3153     0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
3154   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3155     0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
3156   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3157     0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
3158   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3159     0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
3160   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3161     0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
3162   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3163     0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
3164   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3165     0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
3166   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3167     0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
3168   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3169     0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
3170   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3171     0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
3172   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3173     0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
3174   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3175     0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
3176   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3177     0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
3178   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3179     0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
3180   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3181     0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
3182   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3183     0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
3184   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3185     0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
3186   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3187     0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
3188   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3189     0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
3190   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3191     0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
3192   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3193     0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
3194   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3195     0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
3196   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3197     0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
3198   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3199     0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
3200   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3201     0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
3202   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3203     0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
3204   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3205     0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
3206   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3207     0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
3208   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3209     0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
3210   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3211     0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
3212   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3213     0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
3214   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3215     0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
3216   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3217     0xe9400000, 0xff500000,
3218     "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3219   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3220     0xe9500000, 0xff500000,
3221     "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3222   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3223     0xe8600000, 0xff700000,
3224     "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3225   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3226     0xe8700000, 0xff700000,
3227     "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3228   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3229     0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
3230   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3231     0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
3232
3233   /* Filter out Bcc with cond=E or F, which are used for other instructions.  */
3234   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3235     0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
3236   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3237     0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
3238   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3239     0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
3240   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3241     0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
3242
3243   /* These have been 32-bit since the invention of Thumb.  */
3244   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3245      0xf000c000, 0xf800d001, "blx%c\t%B%x"},
3246   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3247      0xf000d000, 0xf800d000, "bl%c\t%B%x"},
3248
3249   /* Fallback.  */
3250   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3251       0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3252   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
3253 };
3254
3255 static const char *const arm_conditional[] =
3256 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
3257  "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
3258
3259 static const char *const arm_fp_const[] =
3260 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
3261
3262 static const char *const arm_shift[] =
3263 {"lsl", "lsr", "asr", "ror"};
3264
3265 typedef struct
3266 {
3267   const char *name;
3268   const char *description;
3269   const char *reg_names[16];
3270 }
3271 arm_regname;
3272
3273 static const arm_regname regnames[] =
3274 {
3275   { "reg-names-raw", N_("Select raw register names"),
3276     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
3277   { "reg-names-gcc", N_("Select register names used by GCC"),
3278     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
3279   { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
3280     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp",  "lr",  "pc" }},
3281   { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
3282   { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
3283   { "reg-names-apcs", N_("Select register names used in the APCS"),
3284     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
3285   { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
3286     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7",  "v8",  "IP",  "SP",  "LR",  "PC" }},
3287   { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
3288     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL",  "FP",  "IP",  "SP",  "LR",  "PC" }}
3289 };
3290
3291 static const char *const iwmmxt_wwnames[] =
3292 {"b", "h", "w", "d"};
3293
3294 static const char *const iwmmxt_wwssnames[] =
3295 {"b", "bus", "bc", "bss",
3296  "h", "hus", "hc", "hss",
3297  "w", "wus", "wc", "wss",
3298  "d", "dus", "dc", "dss"
3299 };
3300
3301 static const char *const iwmmxt_regnames[] =
3302 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3303   "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3304 };
3305
3306 static const char *const iwmmxt_cregnames[] =
3307 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3308   "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3309 };
3310
3311 /* Default to GCC register name set.  */
3312 static unsigned int regname_selected = 1;
3313
3314 #define NUM_ARM_OPTIONS   ARRAY_SIZE (regnames)
3315 #define arm_regnames      regnames[regname_selected].reg_names
3316
3317 static bfd_boolean force_thumb = FALSE;
3318
3319 /* Current IT instruction state.  This contains the same state as the IT
3320    bits in the CPSR.  */
3321 static unsigned int ifthen_state;
3322 /* IT state for the next instruction.  */
3323 static unsigned int ifthen_next_state;
3324 /* The address of the insn for which the IT state is valid.  */
3325 static bfd_vma ifthen_address;
3326 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
3327 /* Indicates that the current Conditional state is unconditional or outside
3328    an IT block.  */
3329 #define COND_UNCOND 16
3330
3331 \f
3332 /* Functions.  */
3333
3334 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3335    Returns pointer to following character of the format string and
3336    fills in *VALUEP and *WIDTHP with the extracted value and number of
3337    bits extracted.  WIDTHP can be NULL.  */
3338
3339 static const char *
3340 arm_decode_bitfield (const char *ptr,
3341                      unsigned long insn,
3342                      unsigned long *valuep,
3343                      int *widthp)
3344 {
3345   unsigned long value = 0;
3346   int width = 0;
3347
3348   do
3349     {
3350       int start, end;
3351       int bits;
3352
3353       for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3354         start = start * 10 + *ptr - '0';
3355       if (*ptr == '-')
3356         for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3357           end = end * 10 + *ptr - '0';
3358       else
3359         end = start;
3360       bits = end - start;
3361       if (bits < 0)
3362         abort ();
3363       value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3364       width += bits + 1;
3365     }
3366   while (*ptr++ == ',');
3367   *valuep = value;
3368   if (widthp)
3369     *widthp = width;
3370   return ptr - 1;
3371 }
3372
3373 static void
3374 arm_decode_shift (long given, fprintf_ftype func, void *stream,
3375                   bfd_boolean print_shift)
3376 {
3377   func (stream, "%s", arm_regnames[given & 0xf]);
3378
3379   if ((given & 0xff0) != 0)
3380     {
3381       if ((given & 0x10) == 0)
3382         {
3383           int amount = (given & 0xf80) >> 7;
3384           int shift = (given & 0x60) >> 5;
3385
3386           if (amount == 0)
3387             {
3388               if (shift == 3)
3389                 {
3390                   func (stream, ", rrx");
3391                   return;
3392                 }
3393
3394               amount = 32;
3395             }
3396
3397           if (print_shift)
3398             func (stream, ", %s #%d", arm_shift[shift], amount);
3399           else
3400             func (stream, ", #%d", amount);
3401         }
3402       else if ((given & 0x80) == 0x80)
3403         func (stream, "\t; <illegal shifter operand>");
3404       else if (print_shift)
3405         func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3406               arm_regnames[(given & 0xf00) >> 8]);
3407       else
3408         func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
3409     }
3410 }
3411
3412 #define W_BIT 21
3413 #define I_BIT 22
3414 #define U_BIT 23
3415 #define P_BIT 24
3416
3417 #define WRITEBACK_BIT_SET   (given & (1 << W_BIT))
3418 #define IMMEDIATE_BIT_SET   (given & (1 << I_BIT))
3419 #define NEGATIVE_BIT_SET   ((given & (1 << U_BIT)) == 0)
3420 #define PRE_BIT_SET         (given & (1 << P_BIT))
3421
3422 /* Print one coprocessor instruction on INFO->STREAM.
3423    Return TRUE if the instuction matched, FALSE if this is not a
3424    recognised coprocessor instruction.  */
3425
3426 static bfd_boolean
3427 print_insn_coprocessor (bfd_vma pc,
3428                         struct disassemble_info *info,
3429                         long given,
3430                         bfd_boolean thumb)
3431 {
3432   const struct opcode32 *insn;
3433   void *stream = info->stream;
3434   fprintf_ftype func = info->fprintf_func;
3435   unsigned long mask;
3436   unsigned long value = 0;
3437   int cond;
3438   int cp_num;
3439   struct arm_private_data *private_data = info->private_data;
3440   arm_feature_set allowed_arches = ARM_ARCH_NONE;
3441
3442   allowed_arches = private_data->features;
3443
3444   for (insn = coprocessor_opcodes; insn->assembler; insn++)
3445     {
3446       unsigned long u_reg = 16;
3447       bfd_boolean is_unpredictable = FALSE;
3448       signed long value_in_comment = 0;
3449       const char *c;
3450
3451       if (ARM_FEATURE_ZERO (insn->arch))
3452         switch (insn->value)
3453           {
3454           case SENTINEL_IWMMXT_START:
3455             if (info->mach != bfd_mach_arm_XScale
3456                 && info->mach != bfd_mach_arm_iWMMXt
3457                 && info->mach != bfd_mach_arm_iWMMXt2)
3458               do
3459                 insn++;
3460               while ((! ARM_FEATURE_ZERO (insn->arch))
3461                      && insn->value != SENTINEL_IWMMXT_END);
3462             continue;
3463
3464           case SENTINEL_IWMMXT_END:
3465             continue;
3466
3467           case SENTINEL_GENERIC_START:
3468             allowed_arches = private_data->features;
3469             continue;
3470
3471           default:
3472             abort ();
3473           }
3474
3475       mask = insn->mask;
3476       value = insn->value;
3477       cp_num = (given >> 8) & 0xf;
3478
3479       if (thumb)
3480         {
3481           /* The high 4 bits are 0xe for Arm conditional instructions, and
3482              0xe for arm unconditional instructions.  The rest of the
3483              encoding is the same.  */
3484           mask |= 0xf0000000;
3485           value |= 0xe0000000;
3486           if (ifthen_state)
3487             cond = IFTHEN_COND;
3488           else
3489             cond = COND_UNCOND;
3490         }
3491       else
3492         {
3493           /* Only match unconditional instuctions against unconditional
3494              patterns.  */
3495           if ((given & 0xf0000000) == 0xf0000000)
3496             {
3497               mask |= 0xf0000000;
3498               cond = COND_UNCOND;
3499             }
3500           else
3501             {
3502               cond = (given >> 28) & 0xf;
3503               if (cond == 0xe)
3504                 cond = COND_UNCOND;
3505             }
3506         }
3507
3508       if ((given & mask) != value)
3509         continue;
3510
3511       if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
3512         continue;
3513
3514       if (insn->value == 0xfe000010     /* mcr2  */
3515           || insn->value == 0xfe100010  /* mrc2  */
3516           || insn->value == 0xfc100000  /* ldc2  */
3517           || insn->value == 0xfc000000) /* stc2  */
3518         {
3519           if (cp_num == 9 || cp_num == 10 || cp_num == 11)
3520             is_unpredictable = TRUE;
3521         }
3522       else if (insn->value == 0x0e000000     /* cdp  */
3523                || insn->value == 0xfe000000  /* cdp2  */
3524                || insn->value == 0x0e000010  /* mcr  */
3525                || insn->value == 0x0e100010  /* mrc  */
3526                || insn->value == 0x0c100000  /* ldc  */
3527                || insn->value == 0x0c000000) /* stc  */
3528         {
3529           /* Floating-point instructions.  */
3530           if (cp_num == 9 || cp_num == 10 || cp_num == 11)
3531             continue;
3532         }
3533
3534       for (c = insn->assembler; *c; c++)
3535         {
3536           if (*c == '%')
3537             {
3538               switch (*++c)
3539                 {
3540                 case '%':
3541                   func (stream, "%%");
3542                   break;
3543
3544                 case 'A':
3545                   {
3546                     int rn = (given >> 16) & 0xf;
3547                     bfd_vma offset = given & 0xff;
3548
3549                     func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3550
3551                     if (PRE_BIT_SET || WRITEBACK_BIT_SET)
3552                       {
3553                         /* Not unindexed.  The offset is scaled.  */
3554                         if (cp_num == 9)
3555                           /* vldr.16/vstr.16 will shift the address
3556                              left by 1 bit only.  */
3557                           offset = offset * 2;
3558                         else
3559                           offset = offset * 4;
3560
3561                         if (NEGATIVE_BIT_SET)
3562                           offset = - offset;
3563                         if (rn != 15)
3564                           value_in_comment = offset;
3565                       }
3566
3567                     if (PRE_BIT_SET)
3568                       {
3569                         if (offset)
3570                           func (stream, ", #%d]%s",
3571                                 (int) offset,
3572                                 WRITEBACK_BIT_SET ? "!" : "");
3573                         else if (NEGATIVE_BIT_SET)
3574                           func (stream, ", #-0]");
3575                         else
3576                           func (stream, "]");
3577                       }
3578                     else
3579                       {
3580                         func (stream, "]");
3581
3582                         if (WRITEBACK_BIT_SET)
3583                           {
3584                             if (offset)
3585                               func (stream, ", #%d", (int) offset);
3586                             else if (NEGATIVE_BIT_SET)
3587                               func (stream, ", #-0");
3588                           }
3589                         else
3590                           {
3591                             func (stream, ", {%s%d}",
3592                                   (NEGATIVE_BIT_SET && !offset) ? "-" : "",
3593                                   (int) offset);
3594                             value_in_comment = offset;
3595                           }
3596                       }
3597                     if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
3598                       {
3599                         func (stream, "\t; ");
3600                         /* For unaligned PCs, apply off-by-alignment
3601                            correction.  */
3602                         info->print_address_func (offset + pc
3603                                                   + info->bytes_per_chunk * 2
3604                                                   - (pc & 3),
3605                                                   info);
3606                       }
3607                   }
3608                   break;
3609
3610                 case 'B':
3611                   {
3612                     int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
3613                     int offset = (given >> 1) & 0x3f;
3614
3615                     if (offset == 1)
3616                       func (stream, "{d%d}", regno);
3617                     else if (regno + offset > 32)
3618                       func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
3619                     else
3620                       func (stream, "{d%d-d%d}", regno, regno + offset - 1);
3621                   }
3622                   break;
3623
3624                 case 'u':
3625                   if (cond != COND_UNCOND)
3626                     is_unpredictable = TRUE;
3627
3628                   /* Fall through.  */
3629                 case 'c':
3630                   if (cond != COND_UNCOND && cp_num == 9)
3631                     is_unpredictable = TRUE;
3632
3633                   func (stream, "%s", arm_conditional[cond]);
3634                   break;
3635
3636                 case 'I':
3637                   /* Print a Cirrus/DSP shift immediate.  */
3638                   /* Immediates are 7bit signed ints with bits 0..3 in
3639                      bits 0..3 of opcode and bits 4..6 in bits 5..7
3640                      of opcode.  */
3641                   {
3642                     int imm;
3643
3644                     imm = (given & 0xf) | ((given & 0xe0) >> 1);
3645
3646                     /* Is ``imm'' a negative number?  */
3647                     if (imm & 0x40)
3648                       imm -= 0x80;
3649
3650                     func (stream, "%d", imm);
3651                   }
3652
3653                   break;
3654
3655                 case 'F':
3656                   switch (given & 0x00408000)
3657                     {
3658                     case 0:
3659                       func (stream, "4");
3660                       break;
3661                     case 0x8000:
3662                       func (stream, "1");
3663                       break;
3664                     case 0x00400000:
3665                       func (stream, "2");
3666                       break;
3667                     default:
3668                       func (stream, "3");
3669                     }
3670                   break;
3671
3672                 case 'P':
3673                   switch (given & 0x00080080)
3674                     {
3675                     case 0:
3676                       func (stream, "s");
3677                       break;
3678                     case 0x80:
3679                       func (stream, "d");
3680                       break;
3681                     case 0x00080000:
3682                       func (stream, "e");
3683                       break;
3684                     default:
3685                       func (stream, _("<illegal precision>"));
3686                       break;
3687                     }
3688                   break;
3689
3690                 case 'Q':
3691                   switch (given & 0x00408000)
3692                     {
3693                     case 0:
3694                       func (stream, "s");
3695                       break;
3696                     case 0x8000:
3697                       func (stream, "d");
3698                       break;
3699                     case 0x00400000:
3700                       func (stream, "e");
3701                       break;
3702                     default:
3703                       func (stream, "p");
3704                       break;
3705                     }
3706                   break;
3707
3708                 case 'R':
3709                   switch (given & 0x60)
3710                     {
3711                     case 0:
3712                       break;
3713                     case 0x20:
3714                       func (stream, "p");
3715                       break;
3716                     case 0x40:
3717                       func (stream, "m");
3718                       break;
3719                     default:
3720                       func (stream, "z");
3721                       break;
3722                     }
3723                   break;
3724
3725                 case '0': case '1': case '2': case '3': case '4':
3726                 case '5': case '6': case '7': case '8': case '9':
3727                   {
3728                     int width;
3729
3730                     c = arm_decode_bitfield (c, given, &value, &width);
3731
3732                     switch (*c)
3733                       {
3734                       case 'R':
3735                         if (value == 15)
3736                           is_unpredictable = TRUE;
3737                         /* Fall through.  */
3738                       case 'r':
3739                         if (c[1] == 'u')
3740                           {
3741                             /* Eat the 'u' character.  */
3742                             ++ c;
3743
3744                             if (u_reg == value)
3745                               is_unpredictable = TRUE;
3746                             u_reg = value;
3747                           }
3748                         func (stream, "%s", arm_regnames[value]);
3749                         break;
3750                       case 'V':
3751                         if (given & (1 << 6))
3752                           goto Q;
3753                         /* FALLTHROUGH */
3754                       case 'D':
3755                         func (stream, "d%ld", value);
3756                         break;
3757                       case 'Q':
3758                       Q:
3759                         if (value & 1)
3760                           func (stream, "<illegal reg q%ld.5>", value >> 1);
3761                         else
3762                           func (stream, "q%ld", value >> 1);
3763                         break;
3764                       case 'd':
3765                         func (stream, "%ld", value);
3766                         value_in_comment = value;
3767                         break;
3768                       case 'E':
3769                         {
3770                           /* Converts immediate 8 bit back to float value.  */
3771                           unsigned floatVal = (value & 0x80) << 24
3772                             | (value & 0x3F) << 19
3773                             | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
3774
3775                           /* Quarter float have a maximum value of 31.0.
3776                              Get floating point value multiplied by 1e7.
3777                              The maximum value stays in limit of a 32-bit int.  */
3778                           unsigned decVal =
3779                             (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
3780                             (16 + (value & 0xF));
3781
3782                           if (!(decVal % 1000000))
3783                             func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
3784                                   floatVal, value & 0x80 ? '-' : ' ',
3785                                   decVal / 10000000,
3786                                   decVal % 10000000 / 1000000);
3787                           else if (!(decVal % 10000))
3788                             func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
3789                                   floatVal, value & 0x80 ? '-' : ' ',
3790                                   decVal / 10000000,
3791                                   decVal % 10000000 / 10000);
3792                           else
3793                             func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
3794                                   floatVal, value & 0x80 ? '-' : ' ',
3795                                   decVal / 10000000, decVal % 10000000);
3796                           break;
3797                         }
3798                       case 'k':
3799                         {
3800                           int from = (given & (1 << 7)) ? 32 : 16;
3801                           func (stream, "%ld", from - value);
3802                         }
3803                         break;
3804
3805                       case 'f':
3806                         if (value > 7)
3807                           func (stream, "#%s", arm_fp_const[value & 7]);
3808                         else
3809                           func (stream, "f%ld", value);
3810                         break;
3811
3812                       case 'w':
3813                         if (width == 2)
3814                           func (stream, "%s", iwmmxt_wwnames[value]);
3815                         else
3816                           func (stream, "%s", iwmmxt_wwssnames[value]);
3817                         break;
3818
3819                       case 'g':
3820                         func (stream, "%s", iwmmxt_regnames[value]);
3821                         break;
3822                       case 'G':
3823                         func (stream, "%s", iwmmxt_cregnames[value]);
3824                         break;
3825
3826                       case 'x':
3827                         func (stream, "0x%lx", (value & 0xffffffffUL));
3828                         break;
3829
3830                       case 'c':
3831                         switch (value)
3832                           {
3833                           case 0:
3834                             func (stream, "eq");
3835                             break;
3836
3837                           case 1:
3838                             func (stream, "vs");
3839                             break;
3840
3841                           case 2:
3842                             func (stream, "ge");
3843                             break;
3844
3845                           case 3:
3846                             func (stream, "gt");
3847                             break;
3848
3849                           default:
3850                             func (stream, "??");
3851                             break;
3852                           }
3853                         break;
3854
3855                       case '`':
3856                         c++;
3857                         if (value == 0)
3858                           func (stream, "%c", *c);
3859                         break;
3860                       case '\'':
3861                         c++;
3862                         if (value == ((1ul << width) - 1))
3863                           func (stream, "%c", *c);
3864                         break;
3865                       case '?':
3866                         func (stream, "%c", c[(1 << width) - (int) value]);
3867                         c += 1 << width;
3868                         break;
3869                       default:
3870                         abort ();
3871                       }
3872                   }
3873                   break;
3874
3875                 case 'y':
3876                 case 'z':
3877                   {
3878                     int single = *c++ == 'y';
3879                     int regno;
3880
3881                     switch (*c)
3882                       {
3883                       case '4': /* Sm pair */
3884                       case '0': /* Sm, Dm */
3885                         regno = given & 0x0000000f;
3886                         if (single)
3887                           {
3888                             regno <<= 1;
3889                             regno += (given >> 5) & 1;
3890                           }
3891                         else
3892                           regno += ((given >> 5) & 1) << 4;
3893                         break;
3894
3895                       case '1': /* Sd, Dd */
3896                         regno = (given >> 12) & 0x0000000f;
3897                         if (single)
3898                           {
3899                             regno <<= 1;
3900                             regno += (given >> 22) & 1;
3901                           }
3902                         else
3903                           regno += ((given >> 22) & 1) << 4;
3904                         break;
3905
3906                       case '2': /* Sn, Dn */
3907                         regno = (given >> 16) & 0x0000000f;
3908                         if (single)
3909                           {
3910                             regno <<= 1;
3911                             regno += (given >> 7) & 1;
3912                           }
3913                         else
3914                           regno += ((given >> 7) & 1) << 4;
3915                         break;
3916
3917                       case '3': /* List */
3918                         func (stream, "{");
3919                         regno = (given >> 12) & 0x0000000f;
3920                         if (single)
3921                           {
3922                             regno <<= 1;
3923                             regno += (given >> 22) & 1;
3924                           }
3925                         else
3926                           regno += ((given >> 22) & 1) << 4;
3927                         break;
3928
3929                       default:
3930                         abort ();
3931                       }
3932
3933                     func (stream, "%c%d", single ? 's' : 'd', regno);
3934
3935                     if (*c == '3')
3936                       {
3937                         int count = given & 0xff;
3938
3939                         if (single == 0)
3940                           count >>= 1;
3941
3942                         if (--count)
3943                           {
3944                             func (stream, "-%c%d",
3945                                   single ? 's' : 'd',
3946                                   regno + count);
3947                           }
3948
3949                         func (stream, "}");
3950                       }
3951                     else if (*c == '4')
3952                       func (stream, ", %c%d", single ? 's' : 'd',
3953                             regno + 1);
3954                   }
3955                   break;
3956
3957                 case 'L':
3958                   switch (given & 0x00400100)
3959                     {
3960                     case 0x00000000: func (stream, "b"); break;
3961                     case 0x00400000: func (stream, "h"); break;
3962                     case 0x00000100: func (stream, "w"); break;
3963                     case 0x00400100: func (stream, "d"); break;
3964                     default:
3965                       break;
3966                     }
3967                   break;
3968
3969                 case 'Z':
3970                   {
3971                     /* given (20, 23) | given (0, 3) */
3972                     value = ((given >> 16) & 0xf0) | (given & 0xf);
3973                     func (stream, "%d", (int) value);
3974                   }
3975                   break;
3976
3977                 case 'l':
3978                   /* This is like the 'A' operator, except that if
3979                      the width field "M" is zero, then the offset is
3980                      *not* multiplied by four.  */
3981                   {
3982                     int offset = given & 0xff;
3983                     int multiplier = (given & 0x00000100) ? 4 : 1;
3984
3985                     func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3986
3987                     if (multiplier > 1)
3988                       {
3989                         value_in_comment = offset * multiplier;
3990                         if (NEGATIVE_BIT_SET)
3991                           value_in_comment = - value_in_comment;
3992                       }
3993
3994                     if (offset)
3995                       {
3996                         if (PRE_BIT_SET)
3997                           func (stream, ", #%s%d]%s",
3998                                 NEGATIVE_BIT_SET ? "-" : "",
3999                                 offset * multiplier,
4000                                 WRITEBACK_BIT_SET ? "!" : "");
4001                         else
4002                           func (stream, "], #%s%d",
4003                                 NEGATIVE_BIT_SET ? "-" : "",
4004                                 offset * multiplier);
4005                       }
4006                     else
4007                       func (stream, "]");
4008                   }
4009                   break;
4010
4011                 case 'r':
4012                   {
4013                     int imm4 = (given >> 4) & 0xf;
4014                     int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
4015                     int ubit = ! NEGATIVE_BIT_SET;
4016                     const char *rm = arm_regnames [given & 0xf];
4017                     const char *rn = arm_regnames [(given >> 16) & 0xf];
4018
4019                     switch (puw_bits)
4020                       {
4021                       case 1:
4022                       case 3:
4023                         func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
4024                         if (imm4)
4025                           func (stream, ", lsl #%d", imm4);
4026                         break;
4027
4028                       case 4:
4029                       case 5:
4030                       case 6:
4031                       case 7:
4032                         func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
4033                         if (imm4 > 0)
4034                           func (stream, ", lsl #%d", imm4);
4035                         func (stream, "]");
4036                         if (puw_bits == 5 || puw_bits == 7)
4037                           func (stream, "!");
4038                         break;
4039
4040                       default:
4041                         func (stream, "INVALID");
4042                       }
4043                   }
4044                   break;
4045
4046                 case 'i':
4047                   {
4048                     long imm5;
4049                     imm5 = ((given & 0x100) >> 4) | (given & 0xf);
4050                     func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
4051                   }
4052                   break;
4053
4054                 default:
4055                   abort ();
4056                 }
4057             }
4058           else
4059             func (stream, "%c", *c);
4060         }
4061
4062       if (value_in_comment > 32 || value_in_comment < -16)
4063         func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
4064
4065       if (is_unpredictable)
4066         func (stream, UNPREDICTABLE_INSTRUCTION);
4067
4068       return TRUE;
4069     }
4070   return FALSE;
4071 }
4072
4073 /* Decodes and prints ARM addressing modes.  Returns the offset
4074    used in the address, if any, if it is worthwhile printing the
4075    offset as a hexadecimal value in a comment at the end of the
4076    line of disassembly.  */
4077
4078 static signed long
4079 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
4080 {
4081   void *stream = info->stream;
4082   fprintf_ftype func = info->fprintf_func;
4083   bfd_vma offset = 0;
4084
4085   if (((given & 0x000f0000) == 0x000f0000)
4086       && ((given & 0x02000000) == 0))
4087     {
4088       offset = given & 0xfff;
4089
4090       func (stream, "[pc");
4091
4092       if (PRE_BIT_SET)
4093         {
4094           /* Pre-indexed.  Elide offset of positive zero when
4095              non-writeback.  */
4096           if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
4097             func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4098
4099           if (NEGATIVE_BIT_SET)
4100             offset = -offset;
4101
4102           offset += pc + 8;
4103
4104           /* Cope with the possibility of write-back
4105              being used.  Probably a very dangerous thing
4106              for the programmer to do, but who are we to
4107              argue ?  */
4108           func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
4109         }
4110       else  /* Post indexed.  */
4111         {
4112           func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4113
4114           /* Ie ignore the offset.  */
4115           offset = pc + 8;
4116         }
4117
4118       func (stream, "\t; ");
4119       info->print_address_func (offset, info);
4120       offset = 0;
4121     }
4122   else
4123     {
4124       func (stream, "[%s",
4125             arm_regnames[(given >> 16) & 0xf]);
4126
4127       if (PRE_BIT_SET)
4128         {
4129           if ((given & 0x02000000) == 0)
4130             {
4131               /* Elide offset of positive zero when non-writeback.  */
4132               offset = given & 0xfff;
4133               if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
4134                 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4135             }
4136           else
4137             {
4138               func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
4139               arm_decode_shift (given, func, stream, TRUE);
4140             }
4141
4142           func (stream, "]%s",
4143                 WRITEBACK_BIT_SET ? "!" : "");
4144         }
4145       else
4146         {
4147           if ((given & 0x02000000) == 0)
4148             {
4149               /* Always show offset.  */
4150               offset = given & 0xfff;
4151               func (stream, "], #%s%d",
4152                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4153             }
4154           else
4155             {
4156               func (stream, "], %s",
4157                     NEGATIVE_BIT_SET ? "-" : "");
4158               arm_decode_shift (given, func, stream, TRUE);
4159             }
4160         }
4161       if (NEGATIVE_BIT_SET)
4162         offset = -offset;
4163     }
4164
4165   return (signed long) offset;
4166 }
4167
4168 /* Print one neon instruction on INFO->STREAM.
4169    Return TRUE if the instuction matched, FALSE if this is not a
4170    recognised neon instruction.  */
4171
4172 static bfd_boolean
4173 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
4174 {
4175   const struct opcode32 *insn;
4176   void *stream = info->stream;
4177   fprintf_ftype func = info->fprintf_func;
4178
4179   if (thumb)
4180     {
4181       if ((given & 0xef000000) == 0xef000000)
4182         {
4183           /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding.  */
4184           unsigned long bit28 = given & (1 << 28);
4185
4186           given &= 0x00ffffff;
4187           if (bit28)
4188             given |= 0xf3000000;
4189           else
4190             given |= 0xf2000000;
4191         }
4192       else if ((given & 0xff000000) == 0xf9000000)
4193         given ^= 0xf9000000 ^ 0xf4000000;
4194       else
4195         return FALSE;
4196     }
4197
4198   for (insn = neon_opcodes; insn->assembler; insn++)
4199     {
4200       if ((given & insn->mask) == insn->value)
4201         {
4202           signed long value_in_comment = 0;
4203           bfd_boolean is_unpredictable = FALSE;
4204           const char *c;
4205
4206           for (c = insn->assembler; *c; c++)
4207             {
4208               if (*c == '%')
4209                 {
4210                   switch (*++c)
4211                     {
4212                     case '%':
4213                       func (stream, "%%");
4214                       break;
4215
4216                     case 'u':
4217                       if (thumb && ifthen_state)
4218                         is_unpredictable = TRUE;
4219
4220                       /* Fall through.  */
4221                     case 'c':
4222                       if (thumb && ifthen_state)
4223                         func (stream, "%s", arm_conditional[IFTHEN_COND]);
4224                       break;
4225
4226                     case 'A':
4227                       {
4228                         static const unsigned char enc[16] =
4229                         {
4230                           0x4, 0x14, /* st4 0,1 */
4231                           0x4, /* st1 2 */
4232                           0x4, /* st2 3 */
4233                           0x3, /* st3 4 */
4234                           0x13, /* st3 5 */
4235                           0x3, /* st1 6 */
4236                           0x1, /* st1 7 */
4237                           0x2, /* st2 8 */
4238                           0x12, /* st2 9 */
4239                           0x2, /* st1 10 */
4240                           0, 0, 0, 0, 0
4241                         };
4242                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4243                         int rn = ((given >> 16) & 0xf);
4244                         int rm = ((given >> 0) & 0xf);
4245                         int align = ((given >> 4) & 0x3);
4246                         int type = ((given >> 8) & 0xf);
4247                         int n = enc[type] & 0xf;
4248                         int stride = (enc[type] >> 4) + 1;
4249                         int ix;
4250
4251                         func (stream, "{");
4252                         if (stride > 1)
4253                           for (ix = 0; ix != n; ix++)
4254                             func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
4255                         else if (n == 1)
4256                           func (stream, "d%d", rd);
4257                         else
4258                           func (stream, "d%d-d%d", rd, rd + n - 1);
4259                         func (stream, "}, [%s", arm_regnames[rn]);
4260                         if (align)
4261                           func (stream, " :%d", 32 << align);
4262                         func (stream, "]");
4263                         if (rm == 0xd)
4264                           func (stream, "!");
4265                         else if (rm != 0xf)
4266                           func (stream, ", %s", arm_regnames[rm]);
4267                       }
4268                       break;
4269
4270                     case 'B':
4271                       {
4272                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4273                         int rn = ((given >> 16) & 0xf);
4274                         int rm = ((given >> 0) & 0xf);
4275                         int idx_align = ((given >> 4) & 0xf);
4276                         int align = 0;
4277                         int size = ((given >> 10) & 0x3);
4278                         int idx = idx_align >> (size + 1);
4279                         int length = ((given >> 8) & 3) + 1;
4280                         int stride = 1;
4281                         int i;
4282
4283                         if (length > 1 && size > 0)
4284                           stride = (idx_align & (1 << size)) ? 2 : 1;
4285
4286                         switch (length)
4287                           {
4288                           case 1:
4289                             {
4290                               int amask = (1 << size) - 1;
4291                               if ((idx_align & (1 << size)) != 0)
4292                                 return FALSE;
4293                               if (size > 0)
4294                                 {
4295                                   if ((idx_align & amask) == amask)
4296                                     align = 8 << size;
4297                                   else if ((idx_align & amask) != 0)
4298                                     return FALSE;
4299                                 }
4300                               }
4301                             break;
4302
4303                           case 2:
4304                             if (size == 2 && (idx_align & 2) != 0)
4305                               return FALSE;
4306                             align = (idx_align & 1) ? 16 << size : 0;
4307                             break;
4308
4309                           case 3:
4310                             if ((size == 2 && (idx_align & 3) != 0)
4311                                 || (idx_align & 1) != 0)
4312                               return FALSE;
4313                             break;
4314
4315                           case 4:
4316                             if (size == 2)
4317                               {
4318                                 if ((idx_align & 3) == 3)
4319                                   return FALSE;
4320                                 align = (idx_align & 3) * 64;
4321                               }
4322                             else
4323                               align = (idx_align & 1) ? 32 << size : 0;
4324                             break;
4325
4326                           default:
4327                             abort ();
4328                           }
4329
4330                         func (stream, "{");
4331                         for (i = 0; i < length; i++)
4332                           func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
4333                             rd + i * stride, idx);
4334                         func (stream, "}, [%s", arm_regnames[rn]);
4335                         if (align)
4336                           func (stream, " :%d", align);
4337                         func (stream, "]");
4338                         if (rm == 0xd)
4339                           func (stream, "!");
4340                         else if (rm != 0xf)
4341                           func (stream, ", %s", arm_regnames[rm]);
4342                       }
4343                       break;
4344
4345                     case 'C':
4346                       {
4347                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4348                         int rn = ((given >> 16) & 0xf);
4349                         int rm = ((given >> 0) & 0xf);
4350                         int align = ((given >> 4) & 0x1);
4351                         int size = ((given >> 6) & 0x3);
4352                         int type = ((given >> 8) & 0x3);
4353                         int n = type + 1;
4354                         int stride = ((given >> 5) & 0x1);
4355                         int ix;
4356
4357                         if (stride && (n == 1))
4358                           n++;
4359                         else
4360                           stride++;
4361
4362                         func (stream, "{");
4363                         if (stride > 1)
4364                           for (ix = 0; ix != n; ix++)
4365                             func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
4366                         else if (n == 1)
4367                           func (stream, "d%d[]", rd);
4368                         else
4369                           func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
4370                         func (stream, "}, [%s", arm_regnames[rn]);
4371                         if (align)
4372                           {
4373                             align = (8 * (type + 1)) << size;
4374                             if (type == 3)
4375                               align = (size > 1) ? align >> 1 : align;
4376                             if (type == 2 || (type == 0 && !size))
4377                               func (stream, " :<bad align %d>", align);
4378                             else
4379                               func (stream, " :%d", align);
4380                           }
4381                         func (stream, "]");
4382                         if (rm == 0xd)
4383                           func (stream, "!");
4384                         else if (rm != 0xf)
4385                           func (stream, ", %s", arm_regnames[rm]);
4386                       }
4387                       break;
4388
4389                     case 'D':
4390                       {
4391                         int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
4392                         int size = (given >> 20) & 3;
4393                         int reg = raw_reg & ((4 << size) - 1);
4394                         int ix = raw_reg >> size >> 2;
4395
4396                         func (stream, "d%d[%d]", reg, ix);
4397                       }
4398                       break;
4399
4400                     case 'E':
4401                       /* Neon encoded constant for mov, mvn, vorr, vbic.  */
4402                       {
4403                         int bits = 0;
4404                         int cmode = (given >> 8) & 0xf;
4405                         int op = (given >> 5) & 0x1;
4406                         unsigned long value = 0, hival = 0;
4407                         unsigned shift;
4408                         int size = 0;
4409                         int isfloat = 0;
4410
4411                         bits |= ((given >> 24) & 1) << 7;
4412                         bits |= ((given >> 16) & 7) << 4;
4413                         bits |= ((given >> 0) & 15) << 0;
4414
4415                         if (cmode < 8)
4416                           {
4417                             shift = (cmode >> 1) & 3;
4418                             value = (unsigned long) bits << (8 * shift);
4419                             size = 32;
4420                           }
4421                         else if (cmode < 12)
4422                           {
4423                             shift = (cmode >> 1) & 1;
4424                             value = (unsigned long) bits << (8 * shift);
4425                             size = 16;
4426                           }
4427                         else if (cmode < 14)
4428                           {
4429                             shift = (cmode & 1) + 1;
4430                             value = (unsigned long) bits << (8 * shift);
4431                             value |= (1ul << (8 * shift)) - 1;
4432                             size = 32;
4433                           }
4434                         else if (cmode == 14)
4435                           {
4436                             if (op)
4437                               {
4438                                 /* Bit replication into bytes.  */
4439                                 int ix;
4440                                 unsigned long mask;
4441
4442                                 value = 0;
4443                                 hival = 0;
4444                                 for (ix = 7; ix >= 0; ix--)
4445                                   {
4446                                     mask = ((bits >> ix) & 1) ? 0xff : 0;
4447                                     if (ix <= 3)
4448                                       value = (value << 8) | mask;
4449                                     else
4450                                       hival = (hival << 8) | mask;
4451                                   }
4452                                 size = 64;
4453                               }
4454                             else
4455                               {
4456                                 /* Byte replication.  */
4457                                 value = (unsigned long) bits;
4458                                 size = 8;
4459                               }
4460                           }
4461                         else if (!op)
4462                           {
4463                             /* Floating point encoding.  */
4464                             int tmp;
4465
4466                             value = (unsigned long)  (bits & 0x7f) << 19;
4467                             value |= (unsigned long) (bits & 0x80) << 24;
4468                             tmp = bits & 0x40 ? 0x3c : 0x40;
4469                             value |= (unsigned long) tmp << 24;
4470                             size = 32;
4471                             isfloat = 1;
4472                           }
4473                         else
4474                           {
4475                             func (stream, "<illegal constant %.8x:%x:%x>",
4476                                   bits, cmode, op);
4477                             size = 32;
4478                             break;
4479                           }
4480                         switch (size)
4481                           {
4482                           case 8:
4483                             func (stream, "#%ld\t; 0x%.2lx", value, value);
4484                             break;
4485
4486                           case 16:
4487                             func (stream, "#%ld\t; 0x%.4lx", value, value);
4488                             break;
4489
4490                           case 32:
4491                             if (isfloat)
4492                               {
4493                                 unsigned char valbytes[4];
4494                                 double fvalue;
4495
4496                                 /* Do this a byte at a time so we don't have to
4497                                    worry about the host's endianness.  */
4498                                 valbytes[0] = value & 0xff;
4499                                 valbytes[1] = (value >> 8) & 0xff;
4500                                 valbytes[2] = (value >> 16) & 0xff;
4501                                 valbytes[3] = (value >> 24) & 0xff;
4502
4503                                 floatformat_to_double
4504                                   (& floatformat_ieee_single_little, valbytes,
4505                                   & fvalue);
4506
4507                                 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
4508                                       value);
4509                               }
4510                             else
4511                               func (stream, "#%ld\t; 0x%.8lx",
4512                                     (long) (((value & 0x80000000L) != 0)
4513                                             ? value | ~0xffffffffL : value),
4514                                     value);
4515                             break;
4516
4517                           case 64:
4518                             func (stream, "#0x%.8lx%.8lx", hival, value);
4519                             break;
4520
4521                           default:
4522                             abort ();
4523                           }
4524                       }
4525                       break;
4526
4527                     case 'F':
4528                       {
4529                         int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
4530                         int num = (given >> 8) & 0x3;
4531
4532                         if (!num)
4533                           func (stream, "{d%d}", regno);
4534                         else if (num + regno >= 32)
4535                           func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
4536                         else
4537                           func (stream, "{d%d-d%d}", regno, regno + num);
4538                       }
4539                       break;
4540
4541
4542                     case '0': case '1': case '2': case '3': case '4':
4543                     case '5': case '6': case '7': case '8': case '9':
4544                       {
4545                         int width;
4546                         unsigned long value;
4547
4548                         c = arm_decode_bitfield (c, given, &value, &width);
4549
4550                         switch (*c)
4551                           {
4552                           case 'r':
4553                             func (stream, "%s", arm_regnames[value]);
4554                             break;
4555                           case 'd':
4556                             func (stream, "%ld", value);
4557                             value_in_comment = value;
4558                             break;
4559                           case 'e':
4560                             func (stream, "%ld", (1ul << width) - value);
4561                             break;
4562
4563                           case 'S':
4564                           case 'T':
4565                           case 'U':
4566                             /* Various width encodings.  */
4567                             {
4568                               int base = 8 << (*c - 'S'); /* 8,16 or 32 */
4569                               int limit;
4570                               unsigned low, high;
4571
4572                               c++;
4573                               if (*c >= '0' && *c <= '9')
4574                                 limit = *c - '0';
4575                               else if (*c >= 'a' && *c <= 'f')
4576                                 limit = *c - 'a' + 10;
4577                               else
4578                                 abort ();
4579                               low = limit >> 2;
4580                               high = limit & 3;
4581
4582                               if (value < low || value > high)
4583                                 func (stream, "<illegal width %d>", base << value);
4584                               else
4585                                 func (stream, "%d", base << value);
4586                             }
4587                             break;
4588                           case 'R':
4589                             if (given & (1 << 6))
4590                               goto Q;
4591                             /* FALLTHROUGH */
4592                           case 'D':
4593                             func (stream, "d%ld", value);
4594                             break;
4595                           case 'Q':
4596                           Q:
4597                             if (value & 1)
4598                               func (stream, "<illegal reg q%ld.5>", value >> 1);
4599                             else
4600                               func (stream, "q%ld", value >> 1);
4601                             break;
4602
4603                           case '`':
4604                             c++;
4605                             if (value == 0)
4606                               func (stream, "%c", *c);
4607                             break;
4608                           case '\'':
4609                             c++;
4610                             if (value == ((1ul << width) - 1))
4611                               func (stream, "%c", *c);
4612                             break;
4613                           case '?':
4614                             func (stream, "%c", c[(1 << width) - (int) value]);
4615                             c += 1 << width;
4616                             break;
4617                           default:
4618                             abort ();
4619                           }
4620                       }
4621                       break;
4622
4623                     default:
4624                       abort ();
4625                     }
4626                 }
4627               else
4628                 func (stream, "%c", *c);
4629             }
4630
4631           if (value_in_comment > 32 || value_in_comment < -16)
4632             func (stream, "\t; 0x%lx", value_in_comment);
4633
4634           if (is_unpredictable)
4635             func (stream, UNPREDICTABLE_INSTRUCTION);
4636
4637           return TRUE;
4638         }
4639     }
4640   return FALSE;
4641 }
4642
4643 /* Return the name of a v7A special register.  */
4644
4645 static const char *
4646 banked_regname (unsigned reg)
4647 {
4648   switch (reg)
4649     {
4650       case 15: return "CPSR";
4651       case 32: return "R8_usr";
4652       case 33: return "R9_usr";
4653       case 34: return "R10_usr";
4654       case 35: return "R11_usr";
4655       case 36: return "R12_usr";
4656       case 37: return "SP_usr";
4657       case 38: return "LR_usr";
4658       case 40: return "R8_fiq";
4659       case 41: return "R9_fiq";
4660       case 42: return "R10_fiq";
4661       case 43: return "R11_fiq";
4662       case 44: return "R12_fiq";
4663       case 45: return "SP_fiq";
4664       case 46: return "LR_fiq";
4665       case 48: return "LR_irq";
4666       case 49: return "SP_irq";
4667       case 50: return "LR_svc";
4668       case 51: return "SP_svc";
4669       case 52: return "LR_abt";
4670       case 53: return "SP_abt";
4671       case 54: return "LR_und";
4672       case 55: return "SP_und";
4673       case 60: return "LR_mon";
4674       case 61: return "SP_mon";
4675       case 62: return "ELR_hyp";
4676       case 63: return "SP_hyp";
4677       case 79: return "SPSR";
4678       case 110: return "SPSR_fiq";
4679       case 112: return "SPSR_irq";
4680       case 114: return "SPSR_svc";
4681       case 116: return "SPSR_abt";
4682       case 118: return "SPSR_und";
4683       case 124: return "SPSR_mon";
4684       case 126: return "SPSR_hyp";
4685       default: return NULL;
4686     }
4687 }
4688
4689 /* Return the name of the DMB/DSB option.  */
4690 static const char *
4691 data_barrier_option (unsigned option)
4692 {
4693   switch (option & 0xf)
4694     {
4695     case 0xf: return "sy";
4696     case 0xe: return "st";
4697     case 0xd: return "ld";
4698     case 0xb: return "ish";
4699     case 0xa: return "ishst";
4700     case 0x9: return "ishld";
4701     case 0x7: return "un";
4702     case 0x6: return "unst";
4703     case 0x5: return "nshld";
4704     case 0x3: return "osh";
4705     case 0x2: return "oshst";
4706     case 0x1: return "oshld";
4707     default:  return NULL;
4708     }
4709 }
4710
4711 /* Print one ARM instruction from PC on INFO->STREAM.  */
4712
4713 static void
4714 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
4715 {
4716   const struct opcode32 *insn;
4717   void *stream = info->stream;
4718   fprintf_ftype func = info->fprintf_func;
4719   struct arm_private_data *private_data = info->private_data;
4720
4721   if (print_insn_coprocessor (pc, info, given, FALSE))
4722     return;
4723
4724   if (print_insn_neon (info, given, FALSE))
4725     return;
4726
4727   for (insn = arm_opcodes; insn->assembler; insn++)
4728     {
4729       if ((given & insn->mask) != insn->value)
4730         continue;
4731
4732       if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
4733         continue;
4734
4735       /* Special case: an instruction with all bits set in the condition field
4736          (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
4737          or by the catchall at the end of the table.  */
4738       if ((given & 0xF0000000) != 0xF0000000
4739           || (insn->mask & 0xF0000000) == 0xF0000000
4740           || (insn->mask == 0 && insn->value == 0))
4741         {
4742           unsigned long u_reg = 16;
4743           unsigned long U_reg = 16;
4744           bfd_boolean is_unpredictable = FALSE;
4745           signed long value_in_comment = 0;
4746           const char *c;
4747
4748           for (c = insn->assembler; *c; c++)
4749             {
4750               if (*c == '%')
4751                 {
4752                   bfd_boolean allow_unpredictable = FALSE;
4753
4754                   switch (*++c)
4755                     {
4756                     case '%':
4757                       func (stream, "%%");
4758                       break;
4759
4760                     case 'a':
4761                       value_in_comment = print_arm_address (pc, info, given);
4762                       break;
4763
4764                     case 'P':
4765                       /* Set P address bit and use normal address
4766                          printing routine.  */
4767                       value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
4768                       break;
4769
4770                     case 'S':
4771                       allow_unpredictable = TRUE;
4772                       /* Fall through.  */
4773                     case 's':
4774                       if ((given & 0x004f0000) == 0x004f0000)
4775                         {
4776                           /* PC relative with immediate offset.  */
4777                           bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
4778
4779                           if (PRE_BIT_SET)
4780                             {
4781                               /* Elide positive zero offset.  */
4782                               if (offset || NEGATIVE_BIT_SET)
4783                                 func (stream, "[pc, #%s%d]\t; ",
4784                                       NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4785                               else
4786                                 func (stream, "[pc]\t; ");
4787                               if (NEGATIVE_BIT_SET)
4788                                 offset = -offset;
4789                               info->print_address_func (offset + pc + 8, info);
4790                             }
4791                           else
4792                             {
4793                               /* Always show the offset.  */
4794                               func (stream, "[pc], #%s%d",
4795                                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4796                               if (! allow_unpredictable)
4797                                 is_unpredictable = TRUE;
4798                             }
4799                         }
4800                       else
4801                         {
4802                           int offset = ((given & 0xf00) >> 4) | (given & 0xf);
4803
4804                           func (stream, "[%s",
4805                                 arm_regnames[(given >> 16) & 0xf]);
4806
4807                           if (PRE_BIT_SET)
4808                             {
4809                               if (IMMEDIATE_BIT_SET)
4810                                 {
4811                                   /* Elide offset for non-writeback
4812                                      positive zero.  */
4813                                   if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
4814                                       || offset)
4815                                     func (stream, ", #%s%d",
4816                                           NEGATIVE_BIT_SET ? "-" : "", offset);
4817
4818                                   if (NEGATIVE_BIT_SET)
4819                                     offset = -offset;
4820
4821                                   value_in_comment = offset;
4822                                 }
4823                               else
4824                                 {
4825                                   /* Register Offset or Register Pre-Indexed.  */
4826                                   func (stream, ", %s%s",
4827                                         NEGATIVE_BIT_SET ? "-" : "",
4828                                         arm_regnames[given & 0xf]);
4829
4830                                   /* Writing back to the register that is the source/
4831                                      destination of the load/store is unpredictable.  */
4832                                   if (! allow_unpredictable
4833                                       && WRITEBACK_BIT_SET
4834                                       && ((given & 0xf) == ((given >> 12) & 0xf)))
4835                                     is_unpredictable = TRUE;
4836                                 }
4837
4838                               func (stream, "]%s",
4839                                     WRITEBACK_BIT_SET ? "!" : "");
4840                             }
4841                           else
4842                             {
4843                               if (IMMEDIATE_BIT_SET)
4844                                 {
4845                                   /* Immediate Post-indexed.  */
4846                                   /* PR 10924: Offset must be printed, even if it is zero.  */
4847                                   func (stream, "], #%s%d",
4848                                         NEGATIVE_BIT_SET ? "-" : "", offset);
4849                                   if (NEGATIVE_BIT_SET)
4850                                     offset = -offset;
4851                                   value_in_comment = offset;
4852                                 }
4853                               else
4854                                 {
4855                                   /* Register Post-indexed.  */
4856                                   func (stream, "], %s%s",
4857                                         NEGATIVE_BIT_SET ? "-" : "",
4858                                         arm_regnames[given & 0xf]);
4859
4860                                   /* Writing back to the register that is the source/
4861                                      destination of the load/store is unpredictable.  */
4862                                   if (! allow_unpredictable
4863                                       && (given & 0xf) == ((given >> 12) & 0xf))
4864                                     is_unpredictable = TRUE;
4865                                 }
4866
4867                               if (! allow_unpredictable)
4868                                 {
4869                                   /* Writeback is automatically implied by post- addressing.
4870                                      Setting the W bit is unnecessary and ARM specify it as
4871                                      being unpredictable.  */
4872                                   if (WRITEBACK_BIT_SET
4873                                       /* Specifying the PC register as the post-indexed
4874                                          registers is also unpredictable.  */
4875                                       || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
4876                                     is_unpredictable = TRUE;
4877                                 }
4878                             }
4879                         }
4880                       break;
4881
4882                     case 'b':
4883                       {
4884                         bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
4885                         info->print_address_func (disp * 4 + pc + 8, info);
4886                       }
4887                       break;
4888
4889                     case 'c':
4890                       if (((given >> 28) & 0xf) != 0xe)
4891                         func (stream, "%s",
4892                               arm_conditional [(given >> 28) & 0xf]);
4893                       break;
4894
4895                     case 'm':
4896                       {
4897                         int started = 0;
4898                         int reg;
4899
4900                         func (stream, "{");
4901                         for (reg = 0; reg < 16; reg++)
4902                           if ((given & (1 << reg)) != 0)
4903                             {
4904                               if (started)
4905                                 func (stream, ", ");
4906                               started = 1;
4907                               func (stream, "%s", arm_regnames[reg]);
4908                             }
4909                         func (stream, "}");
4910                         if (! started)
4911                           is_unpredictable = TRUE;
4912                       }
4913                       break;
4914
4915                     case 'q':
4916                       arm_decode_shift (given, func, stream, FALSE);
4917                       break;
4918
4919                     case 'o':
4920                       if ((given & 0x02000000) != 0)
4921                         {
4922                           unsigned int rotate = (given & 0xf00) >> 7;
4923                           unsigned int immed = (given & 0xff);
4924                           unsigned int a, i;
4925
4926                           a = (((immed << (32 - rotate))
4927                                 | (immed >> rotate)) & 0xffffffff);
4928                           /* If there is another encoding with smaller rotate,
4929                              the rotate should be specified directly.  */
4930                           for (i = 0; i < 32; i += 2)
4931                             if ((a << i | a >> (32 - i)) <= 0xff)
4932                               break;
4933
4934                           if (i != rotate)
4935                             func (stream, "#%d, %d", immed, rotate);
4936                           else
4937                             func (stream, "#%d", a);
4938                           value_in_comment = a;
4939                         }
4940                       else
4941                         arm_decode_shift (given, func, stream, TRUE);
4942                       break;
4943
4944                     case 'p':
4945                       if ((given & 0x0000f000) == 0x0000f000)
4946                         {
4947                           arm_feature_set arm_ext_v6 =
4948                             ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
4949
4950                           /* The p-variants of tst/cmp/cmn/teq are the pre-V6
4951                              mechanism for setting PSR flag bits.  They are
4952                              obsolete in V6 onwards.  */
4953                           if (! ARM_CPU_HAS_FEATURE (private_data->features, \
4954                                                      arm_ext_v6))
4955                             func (stream, "p");
4956                           else
4957                             is_unpredictable = TRUE;
4958                         }
4959                       break;
4960
4961                     case 't':
4962                       if ((given & 0x01200000) == 0x00200000)
4963                         func (stream, "t");
4964                       break;
4965
4966                     case 'A':
4967                       {
4968                         int offset = given & 0xff;
4969
4970                         value_in_comment = offset * 4;
4971                         if (NEGATIVE_BIT_SET)
4972                           value_in_comment = - value_in_comment;
4973
4974                         func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
4975
4976                         if (PRE_BIT_SET)
4977                           {
4978                             if (offset)
4979                               func (stream, ", #%d]%s",
4980                                     (int) value_in_comment,
4981                                     WRITEBACK_BIT_SET ? "!" : "");
4982                             else
4983                               func (stream, "]");
4984                           }
4985                         else
4986                           {
4987                             func (stream, "]");
4988
4989                             if (WRITEBACK_BIT_SET)
4990                               {
4991                                 if (offset)
4992                                   func (stream, ", #%d", (int) value_in_comment);
4993                               }
4994                             else
4995                               {
4996                                 func (stream, ", {%d}", (int) offset);
4997                                 value_in_comment = offset;
4998                               }
4999                           }
5000                       }
5001                       break;
5002
5003                     case 'B':
5004                       /* Print ARM V5 BLX(1) address: pc+25 bits.  */
5005                       {
5006                         bfd_vma address;
5007                         bfd_vma offset = 0;
5008
5009                         if (! NEGATIVE_BIT_SET)
5010                           /* Is signed, hi bits should be ones.  */
5011                           offset = (-1) ^ 0x00ffffff;
5012
5013                         /* Offset is (SignExtend(offset field)<<2).  */
5014                         offset += given & 0x00ffffff;
5015                         offset <<= 2;
5016                         address = offset + pc + 8;
5017
5018                         if (given & 0x01000000)
5019                           /* H bit allows addressing to 2-byte boundaries.  */
5020                           address += 2;
5021
5022                         info->print_address_func (address, info);
5023                       }
5024                       break;
5025
5026                     case 'C':
5027                       if ((given & 0x02000200) == 0x200)
5028                         {
5029                           const char * name;
5030                           unsigned sysm = (given & 0x004f0000) >> 16;
5031
5032                           sysm |= (given & 0x300) >> 4;
5033                           name = banked_regname (sysm);
5034
5035                           if (name != NULL)
5036                             func (stream, "%s", name);
5037                           else
5038                             func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
5039                         }
5040                       else
5041                         {
5042                           func (stream, "%cPSR_",
5043                                 (given & 0x00400000) ? 'S' : 'C');
5044                           if (given & 0x80000)
5045                             func (stream, "f");
5046                           if (given & 0x40000)
5047                             func (stream, "s");
5048                           if (given & 0x20000)
5049                             func (stream, "x");
5050                           if (given & 0x10000)
5051                             func (stream, "c");
5052                         }
5053                       break;
5054
5055                     case 'U':
5056                       if ((given & 0xf0) == 0x60)
5057                         {
5058                           switch (given & 0xf)
5059                             {
5060                             case 0xf: func (stream, "sy"); break;
5061                             default:
5062                               func (stream, "#%d", (int) given & 0xf);
5063                               break;
5064                             }
5065                         }
5066                       else
5067                         {
5068                           const char * opt = data_barrier_option (given & 0xf);
5069                           if (opt != NULL)
5070                             func (stream, "%s", opt);
5071                           else
5072                               func (stream, "#%d", (int) given & 0xf);
5073                         }
5074                       break;
5075
5076                     case '0': case '1': case '2': case '3': case '4':
5077                     case '5': case '6': case '7': case '8': case '9':
5078                       {
5079                         int width;
5080                         unsigned long value;
5081
5082                         c = arm_decode_bitfield (c, given, &value, &width);
5083
5084                         switch (*c)
5085                           {
5086                           case 'R':
5087                             if (value == 15)
5088                               is_unpredictable = TRUE;
5089                             /* Fall through.  */
5090                           case 'r':
5091                           case 'T':
5092                             /* We want register + 1 when decoding T.  */
5093                             if (*c == 'T')
5094                               ++value;
5095
5096                             if (c[1] == 'u')
5097                               {
5098                                 /* Eat the 'u' character.  */
5099                                 ++ c;
5100
5101                                 if (u_reg == value)
5102                                   is_unpredictable = TRUE;
5103                                 u_reg = value;
5104                               }
5105                             if (c[1] == 'U')
5106                               {
5107                                 /* Eat the 'U' character.  */
5108                                 ++ c;
5109
5110                                 if (U_reg == value)
5111                                   is_unpredictable = TRUE;
5112                                 U_reg = value;
5113                               }
5114                             func (stream, "%s", arm_regnames[value]);
5115                             break;
5116                           case 'd':
5117                             func (stream, "%ld", value);
5118                             value_in_comment = value;
5119                             break;
5120                           case 'b':
5121                             func (stream, "%ld", value * 8);
5122                             value_in_comment = value * 8;
5123                             break;
5124                           case 'W':
5125                             func (stream, "%ld", value + 1);
5126                             value_in_comment = value + 1;
5127                             break;
5128                           case 'x':
5129                             func (stream, "0x%08lx", value);
5130
5131                             /* Some SWI instructions have special
5132                                meanings.  */
5133                             if ((given & 0x0fffffff) == 0x0FF00000)
5134                               func (stream, "\t; IMB");
5135                             else if ((given & 0x0fffffff) == 0x0FF00001)
5136                               func (stream, "\t; IMBRange");
5137                             break;
5138                           case 'X':
5139                             func (stream, "%01lx", value & 0xf);
5140                             value_in_comment = value;
5141                             break;
5142                           case '`':
5143                             c++;
5144                             if (value == 0)
5145                               func (stream, "%c", *c);
5146                             break;
5147                           case '\'':
5148                             c++;
5149                             if (value == ((1ul << width) - 1))
5150                               func (stream, "%c", *c);
5151                             break;
5152                           case '?':
5153                             func (stream, "%c", c[(1 << width) - (int) value]);
5154                             c += 1 << width;
5155                             break;
5156                           default:
5157                             abort ();
5158                           }
5159                       }
5160                       break;
5161
5162                     case 'e':
5163                       {
5164                         int imm;
5165
5166                         imm = (given & 0xf) | ((given & 0xfff00) >> 4);
5167                         func (stream, "%d", imm);
5168                         value_in_comment = imm;
5169                       }
5170                       break;
5171
5172                     case 'E':
5173                       /* LSB and WIDTH fields of BFI or BFC.  The machine-
5174                          language instruction encodes LSB and MSB.  */
5175                       {
5176                         long msb = (given & 0x001f0000) >> 16;
5177                         long lsb = (given & 0x00000f80) >> 7;
5178                         long w = msb - lsb + 1;
5179
5180                         if (w > 0)
5181                           func (stream, "#%lu, #%lu", lsb, w);
5182                         else
5183                           func (stream, "(invalid: %lu:%lu)", lsb, msb);
5184                       }
5185                       break;
5186
5187                     case 'R':
5188                       /* Get the PSR/banked register name.  */
5189                       {
5190                         const char * name;
5191                         unsigned sysm = (given & 0x004f0000) >> 16;
5192
5193                         sysm |= (given & 0x300) >> 4;
5194                         name = banked_regname (sysm);
5195
5196                         if (name != NULL)
5197                           func (stream, "%s", name);
5198                         else
5199                           func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
5200                       }
5201                       break;
5202
5203                     case 'V':
5204                       /* 16-bit unsigned immediate from a MOVT or MOVW
5205                          instruction, encoded in bits 0:11 and 15:19.  */
5206                       {
5207                         long hi = (given & 0x000f0000) >> 4;
5208                         long lo = (given & 0x00000fff);
5209                         long imm16 = hi | lo;
5210
5211                         func (stream, "#%lu", imm16);
5212                         value_in_comment = imm16;
5213                       }
5214                       break;
5215
5216                     default:
5217                       abort ();
5218                     }
5219                 }
5220               else
5221                 func (stream, "%c", *c);
5222             }
5223
5224           if (value_in_comment > 32 || value_in_comment < -16)
5225             func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
5226
5227           if (is_unpredictable)
5228             func (stream, UNPREDICTABLE_INSTRUCTION);
5229
5230           return;
5231         }
5232     }
5233   func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
5234   return;
5235 }
5236
5237 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM.  */
5238
5239 static void
5240 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
5241 {
5242   const struct opcode16 *insn;
5243   void *stream = info->stream;
5244   fprintf_ftype func = info->fprintf_func;
5245
5246   for (insn = thumb_opcodes; insn->assembler; insn++)
5247     if ((given & insn->mask) == insn->value)
5248       {
5249         signed long value_in_comment = 0;
5250         const char *c = insn->assembler;
5251
5252         for (; *c; c++)
5253           {
5254             int domaskpc = 0;
5255             int domasklr = 0;
5256
5257             if (*c != '%')
5258               {
5259                 func (stream, "%c", *c);
5260                 continue;
5261               }
5262
5263             switch (*++c)
5264               {
5265               case '%':
5266                 func (stream, "%%");
5267                 break;
5268
5269               case 'c':
5270                 if (ifthen_state)
5271                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
5272                 break;
5273
5274               case 'C':
5275                 if (ifthen_state)
5276                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
5277                 else
5278                   func (stream, "s");
5279                 break;
5280
5281               case 'I':
5282                 {
5283                   unsigned int tmp;
5284
5285                   ifthen_next_state = given & 0xff;
5286                   for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
5287                     func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
5288                   func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
5289                 }
5290                 break;
5291
5292               case 'x':
5293                 if (ifthen_next_state)
5294                   func (stream, "\t; unpredictable branch in IT block\n");
5295                 break;
5296
5297               case 'X':
5298                 if (ifthen_state)
5299                   func (stream, "\t; unpredictable <IT:%s>",
5300                         arm_conditional[IFTHEN_COND]);
5301                 break;
5302
5303               case 'S':
5304                 {
5305                   long reg;
5306
5307                   reg = (given >> 3) & 0x7;
5308                   if (given & (1 << 6))
5309                     reg += 8;
5310
5311                   func (stream, "%s", arm_regnames[reg]);
5312                 }
5313                 break;
5314
5315               case 'D':
5316                 {
5317                   long reg;
5318
5319                   reg = given & 0x7;
5320                   if (given & (1 << 7))
5321                     reg += 8;
5322
5323                   func (stream, "%s", arm_regnames[reg]);
5324                 }
5325                 break;
5326
5327               case 'N':
5328                 if (given & (1 << 8))
5329                   domasklr = 1;
5330                 /* Fall through.  */
5331               case 'O':
5332                 if (*c == 'O' && (given & (1 << 8)))
5333                   domaskpc = 1;
5334                 /* Fall through.  */
5335               case 'M':
5336                 {
5337                   int started = 0;
5338                   int reg;
5339
5340                   func (stream, "{");
5341
5342                   /* It would be nice if we could spot
5343                      ranges, and generate the rS-rE format: */
5344                   for (reg = 0; (reg < 8); reg++)
5345                     if ((given & (1 << reg)) != 0)
5346                       {
5347                         if (started)
5348                           func (stream, ", ");
5349                         started = 1;
5350                         func (stream, "%s", arm_regnames[reg]);
5351                       }
5352
5353                   if (domasklr)
5354                     {
5355                       if (started)
5356                         func (stream, ", ");
5357                       started = 1;
5358                       func (stream, "%s", arm_regnames[14] /* "lr" */);
5359                     }
5360
5361                   if (domaskpc)
5362                     {
5363                       if (started)
5364                         func (stream, ", ");
5365                       func (stream, "%s", arm_regnames[15] /* "pc" */);
5366                     }
5367
5368                   func (stream, "}");
5369                 }
5370                 break;
5371
5372               case 'W':
5373                 /* Print writeback indicator for a LDMIA.  We are doing a
5374                    writeback if the base register is not in the register
5375                    mask.  */
5376                 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
5377                   func (stream, "!");
5378                 break;
5379
5380               case 'b':
5381                 /* Print ARM V6T2 CZB address: pc+4+6 bits.  */
5382                 {
5383                   bfd_vma address = (pc + 4
5384                                      + ((given & 0x00f8) >> 2)
5385                                      + ((given & 0x0200) >> 3));
5386                   info->print_address_func (address, info);
5387                 }
5388                 break;
5389
5390               case 's':
5391                 /* Right shift immediate -- bits 6..10; 1-31 print
5392                    as themselves, 0 prints as 32.  */
5393                 {
5394                   long imm = (given & 0x07c0) >> 6;
5395                   if (imm == 0)
5396                     imm = 32;
5397                   func (stream, "#%ld", imm);
5398                 }
5399                 break;
5400
5401               case '0': case '1': case '2': case '3': case '4':
5402               case '5': case '6': case '7': case '8': case '9':
5403                 {
5404                   int bitstart = *c++ - '0';
5405                   int bitend = 0;
5406
5407                   while (*c >= '0' && *c <= '9')
5408                     bitstart = (bitstart * 10) + *c++ - '0';
5409
5410                   switch (*c)
5411                     {
5412                     case '-':
5413                       {
5414                         bfd_vma reg;
5415
5416                         c++;
5417                         while (*c >= '0' && *c <= '9')
5418                           bitend = (bitend * 10) + *c++ - '0';
5419                         if (!bitend)
5420                           abort ();
5421                         reg = given >> bitstart;
5422                         reg &= (2 << (bitend - bitstart)) - 1;
5423
5424                         switch (*c)
5425                           {
5426                           case 'r':
5427                             func (stream, "%s", arm_regnames[reg]);
5428                             break;
5429
5430                           case 'd':
5431                             func (stream, "%ld", (long) reg);
5432                             value_in_comment = reg;
5433                             break;
5434
5435                           case 'H':
5436                             func (stream, "%ld", (long) (reg << 1));
5437                             value_in_comment = reg << 1;
5438                             break;
5439
5440                           case 'W':
5441                             func (stream, "%ld", (long) (reg << 2));
5442                             value_in_comment = reg << 2;
5443                             break;
5444
5445                           case 'a':
5446                             /* PC-relative address -- the bottom two
5447                                bits of the address are dropped
5448                                before the calculation.  */
5449                             info->print_address_func
5450                               (((pc + 4) & ~3) + (reg << 2), info);
5451                             value_in_comment = 0;
5452                             break;
5453
5454                           case 'x':
5455                             func (stream, "0x%04lx", (long) reg);
5456                             break;
5457
5458                           case 'B':
5459                             reg = ((reg ^ (1 << bitend)) - (1 << bitend));
5460                             info->print_address_func (reg * 2 + pc + 4, info);
5461                             value_in_comment = 0;
5462                             break;
5463
5464                           case 'c':
5465                             func (stream, "%s", arm_conditional [reg]);
5466                             break;
5467
5468                           default:
5469                             abort ();
5470                           }
5471                       }
5472                       break;
5473
5474                     case '\'':
5475                       c++;
5476                       if ((given & (1 << bitstart)) != 0)
5477                         func (stream, "%c", *c);
5478                       break;
5479
5480                     case '?':
5481                       ++c;
5482                       if ((given & (1 << bitstart)) != 0)
5483                         func (stream, "%c", *c++);
5484                       else
5485                         func (stream, "%c", *++c);
5486                       break;
5487
5488                     default:
5489                       abort ();
5490                     }
5491                 }
5492                 break;
5493
5494               default:
5495                 abort ();
5496               }
5497           }
5498
5499         if (value_in_comment > 32 || value_in_comment < -16)
5500           func (stream, "\t; 0x%lx", value_in_comment);
5501         return;
5502       }
5503
5504   /* No match.  */
5505   func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
5506   return;
5507 }
5508
5509 /* Return the name of an V7M special register.  */
5510
5511 static const char *
5512 psr_name (int regno)
5513 {
5514   switch (regno)
5515     {
5516     case 0x0: return "APSR";
5517     case 0x1: return "IAPSR";
5518     case 0x2: return "EAPSR";
5519     case 0x3: return "PSR";
5520     case 0x5: return "IPSR";
5521     case 0x6: return "EPSR";
5522     case 0x7: return "IEPSR";
5523     case 0x8: return "MSP";
5524     case 0x9: return "PSP";
5525     case 0xa: return "MSPLIM";
5526     case 0xb: return "PSPLIM";
5527     case 0x10: return "PRIMASK";
5528     case 0x11: return "BASEPRI";
5529     case 0x12: return "BASEPRI_MAX";
5530     case 0x13: return "FAULTMASK";
5531     case 0x14: return "CONTROL";
5532     case 0x88: return "MSP_NS";
5533     case 0x89: return "PSP_NS";
5534     case 0x8a: return "MSPLIM_NS";
5535     case 0x8b: return "PSPLIM_NS";
5536     case 0x90: return "PRIMASK_NS";
5537     case 0x91: return "BASEPRI_NS";
5538     case 0x93: return "FAULTMASK_NS";
5539     case 0x94: return "CONTROL_NS";
5540     case 0x98: return "SP_NS";
5541     default: return "<unknown>";
5542     }
5543 }
5544
5545 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM.  */
5546
5547 static void
5548 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
5549 {
5550   const struct opcode32 *insn;
5551   void *stream = info->stream;
5552   fprintf_ftype func = info->fprintf_func;
5553
5554   if (print_insn_coprocessor (pc, info, given, TRUE))
5555     return;
5556
5557   if (print_insn_neon (info, given, TRUE))
5558     return;
5559
5560   for (insn = thumb32_opcodes; insn->assembler; insn++)
5561     if ((given & insn->mask) == insn->value)
5562       {
5563         bfd_boolean is_clrm = FALSE;
5564         bfd_boolean is_unpredictable = FALSE;
5565         signed long value_in_comment = 0;
5566         const char *c = insn->assembler;
5567
5568         for (; *c; c++)
5569           {
5570             if (*c != '%')
5571               {
5572                 func (stream, "%c", *c);
5573                 continue;
5574               }
5575
5576             switch (*++c)
5577               {
5578               case '%':
5579                 func (stream, "%%");
5580                 break;
5581
5582               case 'c':
5583                 if (ifthen_state)
5584                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
5585                 break;
5586
5587               case 'x':
5588                 if (ifthen_next_state)
5589                   func (stream, "\t; unpredictable branch in IT block\n");
5590                 break;
5591
5592               case 'X':
5593                 if (ifthen_state)
5594                   func (stream, "\t; unpredictable <IT:%s>",
5595                         arm_conditional[IFTHEN_COND]);
5596                 break;
5597
5598               case 'I':
5599                 {
5600                   unsigned int imm12 = 0;
5601
5602                   imm12 |= (given & 0x000000ffu);
5603                   imm12 |= (given & 0x00007000u) >> 4;
5604                   imm12 |= (given & 0x04000000u) >> 15;
5605                   func (stream, "#%u", imm12);
5606                   value_in_comment = imm12;
5607                 }
5608                 break;
5609
5610               case 'M':
5611                 {
5612                   unsigned int bits = 0, imm, imm8, mod;
5613
5614                   bits |= (given & 0x000000ffu);
5615                   bits |= (given & 0x00007000u) >> 4;
5616                   bits |= (given & 0x04000000u) >> 15;
5617                   imm8 = (bits & 0x0ff);
5618                   mod = (bits & 0xf00) >> 8;
5619                   switch (mod)
5620                     {
5621                     case 0: imm = imm8; break;
5622                     case 1: imm = ((imm8 << 16) | imm8); break;
5623                     case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
5624                     case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
5625                     default:
5626                       mod  = (bits & 0xf80) >> 7;
5627                       imm8 = (bits & 0x07f) | 0x80;
5628                       imm  = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
5629                     }
5630                   func (stream, "#%u", imm);
5631                   value_in_comment = imm;
5632                 }
5633                 break;
5634
5635               case 'J':
5636                 {
5637                   unsigned int imm = 0;
5638
5639                   imm |= (given & 0x000000ffu);
5640                   imm |= (given & 0x00007000u) >> 4;
5641                   imm |= (given & 0x04000000u) >> 15;
5642                   imm |= (given & 0x000f0000u) >> 4;
5643                   func (stream, "#%u", imm);
5644                   value_in_comment = imm;
5645                 }
5646                 break;
5647
5648               case 'K':
5649                 {
5650                   unsigned int imm = 0;
5651
5652                   imm |= (given & 0x000f0000u) >> 16;
5653                   imm |= (given & 0x00000ff0u) >> 0;
5654                   imm |= (given & 0x0000000fu) << 12;
5655                   func (stream, "#%u", imm);
5656                   value_in_comment = imm;
5657                 }
5658                 break;
5659
5660               case 'H':
5661                 {
5662                   unsigned int imm = 0;
5663
5664                   imm |= (given & 0x000f0000u) >> 4;
5665                   imm |= (given & 0x00000fffu) >> 0;
5666                   func (stream, "#%u", imm);
5667                   value_in_comment = imm;
5668                 }
5669                 break;
5670
5671               case 'V':
5672                 {
5673                   unsigned int imm = 0;
5674
5675                   imm |= (given & 0x00000fffu);
5676                   imm |= (given & 0x000f0000u) >> 4;
5677                   func (stream, "#%u", imm);
5678                   value_in_comment = imm;
5679                 }
5680                 break;
5681
5682               case 'S':
5683                 {
5684                   unsigned int reg = (given & 0x0000000fu);
5685                   unsigned int stp = (given & 0x00000030u) >> 4;
5686                   unsigned int imm = 0;
5687                   imm |= (given & 0x000000c0u) >> 6;
5688                   imm |= (given & 0x00007000u) >> 10;
5689
5690                   func (stream, "%s", arm_regnames[reg]);
5691                   switch (stp)
5692                     {
5693                     case 0:
5694                       if (imm > 0)
5695                         func (stream, ", lsl #%u", imm);
5696                       break;
5697
5698                     case 1:
5699                       if (imm == 0)
5700                         imm = 32;
5701                       func (stream, ", lsr #%u", imm);
5702                       break;
5703
5704                     case 2:
5705                       if (imm == 0)
5706                         imm = 32;
5707                       func (stream, ", asr #%u", imm);
5708                       break;
5709
5710                     case 3:
5711                       if (imm == 0)
5712                         func (stream, ", rrx");
5713                       else
5714                         func (stream, ", ror #%u", imm);
5715                     }
5716                 }
5717                 break;
5718
5719               case 'a':
5720                 {
5721                   unsigned int Rn  = (given & 0x000f0000) >> 16;
5722                   unsigned int U   = ! NEGATIVE_BIT_SET;
5723                   unsigned int op  = (given & 0x00000f00) >> 8;
5724                   unsigned int i12 = (given & 0x00000fff);
5725                   unsigned int i8  = (given & 0x000000ff);
5726                   bfd_boolean writeback = FALSE, postind = FALSE;
5727                   bfd_vma offset = 0;
5728
5729                   func (stream, "[%s", arm_regnames[Rn]);
5730                   if (U) /* 12-bit positive immediate offset.  */
5731                     {
5732                       offset = i12;
5733                       if (Rn != 15)
5734                         value_in_comment = offset;
5735                     }
5736                   else if (Rn == 15) /* 12-bit negative immediate offset.  */
5737                     offset = - (int) i12;
5738                   else if (op == 0x0) /* Shifted register offset.  */
5739                     {
5740                       unsigned int Rm = (i8 & 0x0f);
5741                       unsigned int sh = (i8 & 0x30) >> 4;
5742
5743                       func (stream, ", %s", arm_regnames[Rm]);
5744                       if (sh)
5745                         func (stream, ", lsl #%u", sh);
5746                       func (stream, "]");
5747                       break;
5748                     }
5749                   else switch (op)
5750                     {
5751                     case 0xE:  /* 8-bit positive immediate offset.  */
5752                       offset = i8;
5753                       break;
5754
5755                     case 0xC:  /* 8-bit negative immediate offset.  */
5756                       offset = -i8;
5757                       break;
5758
5759                     case 0xF:  /* 8-bit + preindex with wb.  */
5760                       offset = i8;
5761                       writeback = TRUE;
5762                       break;
5763
5764                     case 0xD:  /* 8-bit - preindex with wb.  */
5765                       offset = -i8;
5766                       writeback = TRUE;
5767                       break;
5768
5769                     case 0xB:  /* 8-bit + postindex.  */
5770                       offset = i8;
5771                       postind = TRUE;
5772                       break;
5773
5774                     case 0x9:  /* 8-bit - postindex.  */
5775                       offset = -i8;
5776                       postind = TRUE;
5777                       break;
5778
5779                     default:
5780                       func (stream, ", <undefined>]");
5781                       goto skip;
5782                     }
5783
5784                   if (postind)
5785                     func (stream, "], #%d", (int) offset);
5786                   else
5787                     {
5788                       if (offset)
5789                         func (stream, ", #%d", (int) offset);
5790                       func (stream, writeback ? "]!" : "]");
5791                     }
5792
5793                   if (Rn == 15)
5794                     {
5795                       func (stream, "\t; ");
5796                       info->print_address_func (((pc + 4) & ~3) + offset, info);
5797                     }
5798                 }
5799               skip:
5800                 break;
5801
5802               case 'A':
5803                 {
5804                   unsigned int U   = ! NEGATIVE_BIT_SET;
5805                   unsigned int W   = WRITEBACK_BIT_SET;
5806                   unsigned int Rn  = (given & 0x000f0000) >> 16;
5807                   unsigned int off = (given & 0x000000ff);
5808
5809                   func (stream, "[%s", arm_regnames[Rn]);
5810
5811                   if (PRE_BIT_SET)
5812                     {
5813                       if (off || !U)
5814                         {
5815                           func (stream, ", #%c%u", U ? '+' : '-', off * 4);
5816                           value_in_comment = off * 4 * (U ? 1 : -1);
5817                         }
5818                       func (stream, "]");
5819                       if (W)
5820                         func (stream, "!");
5821                     }
5822                   else
5823                     {
5824                       func (stream, "], ");
5825                       if (W)
5826                         {
5827                           func (stream, "#%c%u", U ? '+' : '-', off * 4);
5828                           value_in_comment = off * 4 * (U ? 1 : -1);
5829                         }
5830                       else
5831                         {
5832                           func (stream, "{%u}", off);
5833                           value_in_comment = off;
5834                         }
5835                     }
5836                 }
5837                 break;
5838
5839               case 'w':
5840                 {
5841                   unsigned int Sbit = (given & 0x01000000) >> 24;
5842                   unsigned int type = (given & 0x00600000) >> 21;
5843
5844                   switch (type)
5845                     {
5846                     case 0: func (stream, Sbit ? "sb" : "b"); break;
5847                     case 1: func (stream, Sbit ? "sh" : "h"); break;
5848                     case 2:
5849                       if (Sbit)
5850                         func (stream, "??");
5851                       break;
5852                     case 3:
5853                       func (stream, "??");
5854                       break;
5855                     }
5856                 }
5857                 break;
5858
5859               case 'n':
5860                 is_clrm = TRUE;
5861                 /* Fall through.  */
5862               case 'm':
5863                 {
5864                   int started = 0;
5865                   int reg;
5866
5867                   func (stream, "{");
5868                   for (reg = 0; reg < 16; reg++)
5869                     if ((given & (1 << reg)) != 0)
5870                       {
5871                         if (started)
5872                           func (stream, ", ");
5873                         started = 1;
5874                         if (is_clrm && reg == 13)
5875                           func (stream, "(invalid: %s)", arm_regnames[reg]);
5876                         else if (is_clrm && reg == 15)
5877                           func (stream, "%s", "APSR");
5878                         else
5879                           func (stream, "%s", arm_regnames[reg]);
5880                       }
5881                   func (stream, "}");
5882                 }
5883                 break;
5884
5885               case 'E':
5886                 {
5887                   unsigned int msb = (given & 0x0000001f);
5888                   unsigned int lsb = 0;
5889
5890                   lsb |= (given & 0x000000c0u) >> 6;
5891                   lsb |= (given & 0x00007000u) >> 10;
5892                   func (stream, "#%u, #%u", lsb, msb - lsb + 1);
5893                 }
5894                 break;
5895
5896               case 'F':
5897                 {
5898                   unsigned int width = (given & 0x0000001f) + 1;
5899                   unsigned int lsb = 0;
5900
5901                   lsb |= (given & 0x000000c0u) >> 6;
5902                   lsb |= (given & 0x00007000u) >> 10;
5903                   func (stream, "#%u, #%u", lsb, width);
5904                 }
5905                 break;
5906
5907               case 'G':
5908                 {
5909                   unsigned int boff = (((given & 0x07800000) >> 23) << 1);
5910                   func (stream, "%x", boff);
5911                 }
5912                 break;
5913
5914               case 'W':
5915                 {
5916                   unsigned int immA = (given & 0x001f0000u) >> 16;
5917                   unsigned int immB = (given & 0x000007feu) >> 1;
5918                   unsigned int immC = (given & 0x00000800u) >> 11;
5919                   bfd_vma offset = 0;
5920
5921                   offset |= immA << 12;
5922                   offset |= immB << 2;
5923                   offset |= immC << 1;
5924                   /* Sign extend.  */
5925                   offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
5926
5927                   info->print_address_func (pc + 4 + offset, info);
5928                 }
5929                 break;
5930
5931               case 'Y':
5932                 {
5933                   unsigned int immA = (given & 0x007f0000u) >> 16;
5934                   unsigned int immB = (given & 0x000007feu) >> 1;
5935                   unsigned int immC = (given & 0x00000800u) >> 11;
5936                   bfd_vma offset = 0;
5937
5938                   offset |= immA << 12;
5939                   offset |= immB << 2;
5940                   offset |= immC << 1;
5941                   /* Sign extend.  */
5942                   offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
5943
5944                   info->print_address_func (pc + 4 + offset, info);
5945                 }
5946                 break;
5947
5948               case 'Z':
5949                 {
5950                   unsigned int immA = (given & 0x00010000u) >> 16;
5951                   unsigned int immB = (given & 0x000007feu) >> 1;
5952                   unsigned int immC = (given & 0x00000800u) >> 11;
5953                   bfd_vma offset = 0;
5954
5955                   offset |= immA << 12;
5956                   offset |= immB << 2;
5957                   offset |= immC << 1;
5958                   /* Sign extend.  */
5959                   offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
5960
5961                   info->print_address_func (pc + 4 + offset, info);
5962
5963                   unsigned int T    = (given & 0x00020000u) >> 17;
5964                   unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
5965                   unsigned int boffset   = (T == 1) ? 4 : 2;
5966                   func (stream, ", ");
5967                   func (stream, "%x", endoffset + boffset);
5968                 }
5969                 break;
5970
5971               case 'Q':
5972                 {
5973                   unsigned int immh = (given & 0x000007feu) >> 1;
5974                   unsigned int imml = (given & 0x00000800u) >> 11;
5975                   bfd_vma imm32 = 0;
5976
5977                   imm32 |= immh << 2;
5978                   imm32 |= imml << 1;
5979
5980                   info->print_address_func (pc + 4 + imm32, info);
5981                 }
5982                 break;
5983
5984               case 'P':
5985                 {
5986                   unsigned int immh = (given & 0x000007feu) >> 1;
5987                   unsigned int imml = (given & 0x00000800u) >> 11;
5988                   bfd_vma imm32 = 0;
5989
5990                   imm32 |= immh << 2;
5991                   imm32 |= imml << 1;
5992
5993                   info->print_address_func (pc + 4 - imm32, info);
5994                 }
5995                 break;
5996
5997               case 'b':
5998                 {
5999                   unsigned int S = (given & 0x04000000u) >> 26;
6000                   unsigned int J1 = (given & 0x00002000u) >> 13;
6001                   unsigned int J2 = (given & 0x00000800u) >> 11;
6002                   bfd_vma offset = 0;
6003
6004                   offset |= !S << 20;
6005                   offset |= J2 << 19;
6006                   offset |= J1 << 18;
6007                   offset |= (given & 0x003f0000) >> 4;
6008                   offset |= (given & 0x000007ff) << 1;
6009                   offset -= (1 << 20);
6010
6011                   info->print_address_func (pc + 4 + offset, info);
6012                 }
6013                 break;
6014
6015               case 'B':
6016                 {
6017                   unsigned int S = (given & 0x04000000u) >> 26;
6018                   unsigned int I1 = (given & 0x00002000u) >> 13;
6019                   unsigned int I2 = (given & 0x00000800u) >> 11;
6020                   bfd_vma offset = 0;
6021
6022                   offset |= !S << 24;
6023                   offset |= !(I1 ^ S) << 23;
6024                   offset |= !(I2 ^ S) << 22;
6025                   offset |= (given & 0x03ff0000u) >> 4;
6026                   offset |= (given & 0x000007ffu) << 1;
6027                   offset -= (1 << 24);
6028                   offset += pc + 4;
6029
6030                   /* BLX target addresses are always word aligned.  */
6031                   if ((given & 0x00001000u) == 0)
6032                       offset &= ~2u;
6033
6034                   info->print_address_func (offset, info);
6035                 }
6036                 break;
6037
6038               case 's':
6039                 {
6040                   unsigned int shift = 0;
6041
6042                   shift |= (given & 0x000000c0u) >> 6;
6043                   shift |= (given & 0x00007000u) >> 10;
6044                   if (WRITEBACK_BIT_SET)
6045                     func (stream, ", asr #%u", shift);
6046                   else if (shift)
6047                     func (stream, ", lsl #%u", shift);
6048                   /* else print nothing - lsl #0 */
6049                 }
6050                 break;
6051
6052               case 'R':
6053                 {
6054                   unsigned int rot = (given & 0x00000030) >> 4;
6055
6056                   if (rot)
6057                     func (stream, ", ror #%u", rot * 8);
6058                 }
6059                 break;
6060
6061               case 'U':
6062                 if ((given & 0xf0) == 0x60)
6063                   {
6064                     switch (given & 0xf)
6065                       {
6066                         case 0xf: func (stream, "sy"); break;
6067                         default:
6068                           func (stream, "#%d", (int) given & 0xf);
6069                               break;
6070                       }
6071                   }
6072                 else
6073                   {
6074                     const char * opt = data_barrier_option (given & 0xf);
6075                     if (opt != NULL)
6076                       func (stream, "%s", opt);
6077                     else
6078                       func (stream, "#%d", (int) given & 0xf);
6079                    }
6080                 break;
6081
6082               case 'C':
6083                 if ((given & 0xff) == 0)
6084                   {
6085                     func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
6086                     if (given & 0x800)
6087                       func (stream, "f");
6088                     if (given & 0x400)
6089                       func (stream, "s");
6090                     if (given & 0x200)
6091                       func (stream, "x");
6092                     if (given & 0x100)
6093                       func (stream, "c");
6094                   }
6095                 else if ((given & 0x20) == 0x20)
6096                   {
6097                     char const* name;
6098                     unsigned sysm = (given & 0xf00) >> 8;
6099
6100                     sysm |= (given & 0x30);
6101                     sysm |= (given & 0x00100000) >> 14;
6102                     name = banked_regname (sysm);
6103
6104                     if (name != NULL)
6105                       func (stream, "%s", name);
6106                     else
6107                       func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
6108                   }
6109                 else
6110                   {
6111                     func (stream, "%s", psr_name (given & 0xff));
6112                   }
6113                 break;
6114
6115               case 'D':
6116                 if (((given & 0xff) == 0)
6117                     || ((given & 0x20) == 0x20))
6118                   {
6119                     char const* name;
6120                     unsigned sm = (given & 0xf0000) >> 16;
6121
6122                     sm |= (given & 0x30);
6123                     sm |= (given & 0x00100000) >> 14;
6124                     name = banked_regname (sm);
6125
6126                     if (name != NULL)
6127                       func (stream, "%s", name);
6128                     else
6129                       func (stream, "(UNDEF: %lu)", (unsigned long) sm);
6130                   }
6131                 else
6132                   func (stream, "%s", psr_name (given & 0xff));
6133                 break;
6134
6135               case '0': case '1': case '2': case '3': case '4':
6136               case '5': case '6': case '7': case '8': case '9':
6137                 {
6138                   int width;
6139                   unsigned long val;
6140
6141                   c = arm_decode_bitfield (c, given, &val, &width);
6142
6143                   switch (*c)
6144                     {
6145                     case 'd':
6146                       func (stream, "%lu", val);
6147                       value_in_comment = val;
6148                       break;
6149
6150                     case 'D':
6151                       func (stream, "%lu", val + 1);
6152                       value_in_comment = val + 1;
6153                       break;
6154
6155                     case 'W':
6156                       func (stream, "%lu", val * 4);
6157                       value_in_comment = val * 4;
6158                       break;
6159
6160                     case 'S':
6161                       if (val == 13)
6162                         is_unpredictable = TRUE;
6163                       /* Fall through.  */
6164                     case 'R':
6165                       if (val == 15)
6166                         is_unpredictable = TRUE;
6167                       /* Fall through.  */
6168                     case 'r':
6169                       func (stream, "%s", arm_regnames[val]);
6170                       break;
6171
6172                     case 'c':
6173                       func (stream, "%s", arm_conditional[val]);
6174                       break;
6175
6176                     case '\'':
6177                       c++;
6178                       if (val == ((1ul << width) - 1))
6179                         func (stream, "%c", *c);
6180                       break;
6181
6182                     case '`':
6183                       c++;
6184                       if (val == 0)
6185                         func (stream, "%c", *c);
6186                       break;
6187
6188                     case '?':
6189                       func (stream, "%c", c[(1 << width) - (int) val]);
6190                       c += 1 << width;
6191                       break;
6192
6193                     case 'x':
6194                       func (stream, "0x%lx", val & 0xffffffffUL);
6195                       break;
6196
6197                     default:
6198                       abort ();
6199                     }
6200                 }
6201                 break;
6202
6203               case 'L':
6204                 /* PR binutils/12534
6205                    If we have a PC relative offset in an LDRD or STRD
6206                    instructions then display the decoded address.  */
6207                 if (((given >> 16) & 0xf) == 0xf)
6208                   {
6209                     bfd_vma offset = (given & 0xff) * 4;
6210
6211                     if ((given & (1 << 23)) == 0)
6212                       offset = - offset;
6213                     func (stream, "\t; ");
6214                     info->print_address_func ((pc & ~3) + 4 + offset, info);
6215                   }
6216                 break;
6217
6218               default:
6219                 abort ();
6220               }
6221           }
6222
6223         if (value_in_comment > 32 || value_in_comment < -16)
6224           func (stream, "\t; 0x%lx", value_in_comment);
6225
6226         if (is_unpredictable)
6227           func (stream, UNPREDICTABLE_INSTRUCTION);
6228
6229         return;
6230       }
6231
6232   /* No match.  */
6233   func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
6234   return;
6235 }
6236
6237 /* Print data bytes on INFO->STREAM.  */
6238
6239 static void
6240 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
6241                  struct disassemble_info *info,
6242                  long given)
6243 {
6244   switch (info->bytes_per_chunk)
6245     {
6246     case 1:
6247       info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
6248       break;
6249     case 2:
6250       info->fprintf_func (info->stream, ".short\t0x%04lx", given);
6251       break;
6252     case 4:
6253       info->fprintf_func (info->stream, ".word\t0x%08lx", given);
6254       break;
6255     default:
6256       abort ();
6257     }
6258 }
6259
6260 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
6261    being displayed in symbol relative addresses.
6262
6263    Also disallow private symbol, with __tagsym$$ prefix,
6264    from ARM RVCT toolchain being displayed.  */
6265
6266 bfd_boolean
6267 arm_symbol_is_valid (asymbol * sym,
6268                      struct disassemble_info * info ATTRIBUTE_UNUSED)
6269 {
6270   const char * name;
6271
6272   if (sym == NULL)
6273     return FALSE;
6274
6275   name = bfd_asymbol_name (sym);
6276
6277   return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
6278 }
6279
6280 /* Parse the string of disassembler options.  */
6281
6282 static void
6283 parse_arm_disassembler_options (const char *options)
6284 {
6285   const char *opt;
6286
6287   FOR_EACH_DISASSEMBLER_OPTION (opt, options)
6288     {
6289       if (CONST_STRNEQ (opt, "reg-names-"))
6290         {
6291           unsigned int i;
6292           for (i = 0; i < NUM_ARM_OPTIONS; i++)
6293             if (disassembler_options_cmp (opt, regnames[i].name) == 0)
6294               {
6295                 regname_selected = i;
6296                 break;
6297               }
6298
6299           if (i >= NUM_ARM_OPTIONS)
6300             /* xgettext: c-format */
6301             opcodes_error_handler (_("unrecognised register name set: %s"),
6302                                    opt);
6303         }
6304       else if (CONST_STRNEQ (opt, "force-thumb"))
6305         force_thumb = 1;
6306       else if (CONST_STRNEQ (opt, "no-force-thumb"))
6307         force_thumb = 0;
6308       else
6309         /* xgettext: c-format */
6310         opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
6311     }
6312
6313   return;
6314 }
6315
6316 static bfd_boolean
6317 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6318                          enum map_type *map_symbol);
6319
6320 /* Search back through the insn stream to determine if this instruction is
6321    conditionally executed.  */
6322
6323 static void
6324 find_ifthen_state (bfd_vma pc,
6325                    struct disassemble_info *info,
6326                    bfd_boolean little)
6327 {
6328   unsigned char b[2];
6329   unsigned int insn;
6330   int status;
6331   /* COUNT is twice the number of instructions seen.  It will be odd if we
6332      just crossed an instruction boundary.  */
6333   int count;
6334   int it_count;
6335   unsigned int seen_it;
6336   bfd_vma addr;
6337
6338   ifthen_address = pc;
6339   ifthen_state = 0;
6340
6341   addr = pc;
6342   count = 1;
6343   it_count = 0;
6344   seen_it = 0;
6345   /* Scan backwards looking for IT instructions, keeping track of where
6346      instruction boundaries are.  We don't know if something is actually an
6347      IT instruction until we find a definite instruction boundary.  */
6348   for (;;)
6349     {
6350       if (addr == 0 || info->symbol_at_address_func (addr, info))
6351         {
6352           /* A symbol must be on an instruction boundary, and will not
6353              be within an IT block.  */
6354           if (seen_it && (count & 1))
6355             break;
6356
6357           return;
6358         }
6359       addr -= 2;
6360       status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
6361       if (status)
6362         return;
6363
6364       if (little)
6365         insn = (b[0]) | (b[1] << 8);
6366       else
6367         insn = (b[1]) | (b[0] << 8);
6368       if (seen_it)
6369         {
6370           if ((insn & 0xf800) < 0xe800)
6371             {
6372               /* Addr + 2 is an instruction boundary.  See if this matches
6373                  the expected boundary based on the position of the last
6374                  IT candidate.  */
6375               if (count & 1)
6376                 break;
6377               seen_it = 0;
6378             }
6379         }
6380       if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
6381         {
6382           enum map_type type = MAP_ARM;
6383           bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
6384
6385           if (!found || (found && type == MAP_THUMB))
6386             {
6387               /* This could be an IT instruction.  */
6388               seen_it = insn;
6389               it_count = count >> 1;
6390             }
6391         }
6392       if ((insn & 0xf800) >= 0xe800)
6393         count++;
6394       else
6395         count = (count + 2) | 1;
6396       /* IT blocks contain at most 4 instructions.  */
6397       if (count >= 8 && !seen_it)
6398         return;
6399     }
6400   /* We found an IT instruction.  */
6401   ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
6402   if ((ifthen_state & 0xf) == 0)
6403     ifthen_state = 0;
6404 }
6405
6406 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
6407    mapping symbol.  */
6408
6409 static int
6410 is_mapping_symbol (struct disassemble_info *info, int n,
6411                    enum map_type *map_type)
6412 {
6413   const char *name;
6414
6415   name = bfd_asymbol_name (info->symtab[n]);
6416   if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
6417       && (name[2] == 0 || name[2] == '.'))
6418     {
6419       *map_type = ((name[1] == 'a') ? MAP_ARM
6420                    : (name[1] == 't') ? MAP_THUMB
6421                    : MAP_DATA);
6422       return TRUE;
6423     }
6424
6425   return FALSE;
6426 }
6427
6428 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
6429    Returns nonzero if *MAP_TYPE was set.  */
6430
6431 static int
6432 get_map_sym_type (struct disassemble_info *info,
6433                   int n,
6434                   enum map_type *map_type)
6435 {
6436   /* If the symbol is in a different section, ignore it.  */
6437   if (info->section != NULL && info->section != info->symtab[n]->section)
6438     return FALSE;
6439
6440   return is_mapping_symbol (info, n, map_type);
6441 }
6442
6443 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
6444    Returns nonzero if *MAP_TYPE was set.  */
6445
6446 static int
6447 get_sym_code_type (struct disassemble_info *info,
6448                    int n,
6449                    enum map_type *map_type)
6450 {
6451   elf_symbol_type *es;
6452   unsigned int type;
6453
6454   /* If the symbol is in a different section, ignore it.  */
6455   if (info->section != NULL && info->section != info->symtab[n]->section)
6456     return FALSE;
6457
6458   es = *(elf_symbol_type **)(info->symtab + n);
6459   type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6460
6461   /* If the symbol has function type then use that.  */
6462   if (type == STT_FUNC || type == STT_GNU_IFUNC)
6463     {
6464       if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6465           == ST_BRANCH_TO_THUMB)
6466         *map_type = MAP_THUMB;
6467       else
6468         *map_type = MAP_ARM;
6469       return TRUE;
6470     }
6471
6472   return FALSE;
6473 }
6474
6475 /* Search the mapping symbol state for instruction at pc.  This is only
6476    applicable for elf target.
6477
6478    There is an assumption Here, info->private_data contains the correct AND
6479    up-to-date information about current scan process.  The information will be
6480    used to speed this search process.
6481
6482    Return TRUE if the mapping state can be determined, and map_symbol
6483    will be updated accordingly.  Otherwise, return FALSE.  */
6484
6485 static bfd_boolean
6486 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6487                          enum map_type *map_symbol)
6488 {
6489   bfd_vma addr, section_vma = 0;
6490   int n, last_sym = -1;
6491   bfd_boolean found = FALSE;
6492   bfd_boolean can_use_search_opt_p = FALSE;
6493
6494   /* Default to DATA.  A text section is required by the ABI to contain an
6495      INSN mapping symbol at the start.  A data section has no such
6496      requirement, hence if no mapping symbol is found the section must
6497      contain only data.  This however isn't very useful if the user has
6498      fully stripped the binaries.  If this is the case use the section
6499      attributes to determine the default.  If we have no section default to
6500      INSN as well, as we may be disassembling some raw bytes on a baremetal
6501      HEX file or similar.  */
6502   enum map_type type = MAP_DATA;
6503   if ((info->section && info->section->flags & SEC_CODE) || !info->section)
6504     type = MAP_ARM;
6505   struct arm_private_data *private_data;
6506
6507   if (info->private_data == NULL
6508       || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
6509     return FALSE;
6510
6511   private_data = info->private_data;
6512
6513   /* First, look for mapping symbols.  */
6514   if (info->symtab_size != 0)
6515   {
6516     if (pc <= private_data->last_mapping_addr)
6517       private_data->last_mapping_sym = -1;
6518
6519     /* Start scanning at the start of the function, or wherever
6520        we finished last time.  */
6521     n = info->symtab_pos + 1;
6522
6523     /* If the last stop offset is different from the current one it means we
6524        are disassembling a different glob of bytes.  As such the optimization
6525        would not be safe and we should start over.  */
6526     can_use_search_opt_p
6527       = private_data->last_mapping_sym >= 0
6528         && info->stop_offset == private_data->last_stop_offset;
6529
6530     if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
6531       n = private_data->last_mapping_sym;
6532
6533     /* Look down while we haven't passed the location being disassembled.
6534        The reason for this is that there's no defined order between a symbol
6535        and an mapping symbol that may be at the same address.  We may have to
6536        look at least one position ahead.  */
6537     for (; n < info->symtab_size; n++)
6538       {
6539         addr = bfd_asymbol_value (info->symtab[n]);
6540         if (addr > pc)
6541           break;
6542         if (get_map_sym_type (info, n, &type))
6543           {
6544             last_sym = n;
6545             found = TRUE;
6546           }
6547       }
6548
6549     if (!found)
6550       {
6551         n = info->symtab_pos;
6552         if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
6553           n = private_data->last_mapping_sym;
6554
6555         /* No mapping symbol found at this address.  Look backwards
6556            for a preceeding one, but don't go pass the section start
6557            otherwise a data section with no mapping symbol can pick up
6558            a text mapping symbol of a preceeding section.  The documentation
6559            says section can be NULL, in which case we will seek up all the
6560            way to the top.  */
6561         if (info->section)
6562           section_vma = info->section->vma;
6563
6564         for (; n >= 0; n--)
6565           {
6566             addr = bfd_asymbol_value (info->symtab[n]);
6567             if (addr < section_vma)
6568               break;
6569
6570             if (get_map_sym_type (info, n, &type))
6571               {
6572                 last_sym = n;
6573                 found = TRUE;
6574                 break;
6575               }
6576           }
6577       }
6578   }
6579
6580   /* If no mapping symbol was found, try looking up without a mapping
6581      symbol.  This is done by walking up from the current PC to the nearest
6582      symbol.  We don't actually have to loop here since symtab_pos will
6583      contain the nearest symbol already.  */
6584   if (!found)
6585     {
6586       n = info->symtab_pos;
6587       if (n >= 0 && get_sym_code_type (info, n, &type))
6588         {
6589           last_sym = n;
6590           found = TRUE;
6591         }
6592     }
6593
6594   private_data->last_mapping_sym = last_sym;
6595   private_data->last_type = type;
6596   private_data->last_stop_offset = info->stop_offset;
6597
6598   *map_symbol = type;
6599   return found;
6600 }
6601
6602 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
6603    of the supplied arm_feature_set structure with bitmasks indicating
6604    the supported base architectures and coprocessor extensions.
6605
6606    FIXME: This could more efficiently implemented as a constant array,
6607    although it would also be less robust.  */
6608
6609 static void
6610 select_arm_features (unsigned long mach,
6611                      arm_feature_set * features)
6612 {
6613   arm_feature_set arch_fset;
6614   const arm_feature_set fpu_any = FPU_ANY;
6615
6616 #undef ARM_SET_FEATURES
6617 #define ARM_SET_FEATURES(FSET) \
6618   {                                                     \
6619     const arm_feature_set fset = FSET;                  \
6620     arch_fset = fset;                                   \
6621   }
6622
6623   /* When several architecture versions share the same bfd_mach_arm_XXX value
6624      the most featureful is chosen.  */
6625   switch (mach)
6626     {
6627     case bfd_mach_arm_2:         ARM_SET_FEATURES (ARM_ARCH_V2); break;
6628     case bfd_mach_arm_2a:        ARM_SET_FEATURES (ARM_ARCH_V2S); break;
6629     case bfd_mach_arm_3:         ARM_SET_FEATURES (ARM_ARCH_V3); break;
6630     case bfd_mach_arm_3M:        ARM_SET_FEATURES (ARM_ARCH_V3M); break;
6631     case bfd_mach_arm_4:         ARM_SET_FEATURES (ARM_ARCH_V4); break;
6632     case bfd_mach_arm_4T:        ARM_SET_FEATURES (ARM_ARCH_V4T); break;
6633     case bfd_mach_arm_5:         ARM_SET_FEATURES (ARM_ARCH_V5); break;
6634     case bfd_mach_arm_5T:        ARM_SET_FEATURES (ARM_ARCH_V5T); break;
6635     case bfd_mach_arm_5TE:       ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
6636     case bfd_mach_arm_XScale:    ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
6637     case bfd_mach_arm_ep9312:
6638         ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
6639                                            ARM_CEXT_MAVERICK | FPU_MAVERICK));
6640        break;
6641     case bfd_mach_arm_iWMMXt:    ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
6642     case bfd_mach_arm_iWMMXt2:   ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
6643     case bfd_mach_arm_5TEJ:      ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
6644     case bfd_mach_arm_6:         ARM_SET_FEATURES (ARM_ARCH_V6); break;
6645     case bfd_mach_arm_6KZ:       ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
6646     case bfd_mach_arm_6T2:       ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
6647     case bfd_mach_arm_6K:        ARM_SET_FEATURES (ARM_ARCH_V6K); break;
6648     case bfd_mach_arm_7:         ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
6649     case bfd_mach_arm_6M:        ARM_SET_FEATURES (ARM_ARCH_V6M); break;
6650     case bfd_mach_arm_6SM:       ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
6651     case bfd_mach_arm_7EM:       ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
6652     case bfd_mach_arm_8:
6653         {
6654           /* Add bits for extensions that Armv8.5-A recognizes.  */
6655           arm_feature_set armv8_5_ext_fset
6656             = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
6657           ARM_SET_FEATURES (ARM_ARCH_V8_5A);
6658           ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset);
6659           break;
6660         }
6661     case bfd_mach_arm_8R:        ARM_SET_FEATURES (ARM_ARCH_V8R); break;
6662     case bfd_mach_arm_8M_BASE:   ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
6663     case bfd_mach_arm_8M_MAIN:   ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
6664     case bfd_mach_arm_8_1M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN); break;
6665       /* If the machine type is unknown allow all architecture types and all
6666          extensions.  */
6667     case bfd_mach_arm_unknown:   ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
6668     default:
6669       abort ();
6670     }
6671 #undef ARM_SET_FEATURES
6672
6673   /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
6674      and thus on bfd_mach_arm_XXX value.  Therefore for a given
6675      bfd_mach_arm_XXX value all coprocessor feature bits should be allowed.  */
6676   ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
6677 }
6678
6679
6680 /* NOTE: There are no checks in these routines that
6681    the relevant number of data bytes exist.  */
6682
6683 static int
6684 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
6685 {
6686   unsigned char b[4];
6687   long          given;
6688   int           status;
6689   int           is_thumb = FALSE;
6690   int           is_data = FALSE;
6691   int           little_code;
6692   unsigned int  size = 4;
6693   void          (*printer) (bfd_vma, struct disassemble_info *, long);
6694   bfd_boolean   found = FALSE;
6695   struct arm_private_data *private_data;
6696
6697   if (info->disassembler_options)
6698     {
6699       parse_arm_disassembler_options (info->disassembler_options);
6700
6701       /* To avoid repeated parsing of these options, we remove them here.  */
6702       info->disassembler_options = NULL;
6703     }
6704
6705   /* PR 10288: Control which instructions will be disassembled.  */
6706   if (info->private_data == NULL)
6707     {
6708       static struct arm_private_data private;
6709
6710       if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
6711         /* If the user did not use the -m command line switch then default to
6712            disassembling all types of ARM instruction.
6713
6714            The info->mach value has to be ignored as this will be based on
6715            the default archictecture for the target and/or hints in the notes
6716            section, but it will never be greater than the current largest arm
6717            machine value (iWMMXt2), which is only equivalent to the V5TE
6718            architecture.  ARM architectures have advanced beyond the machine
6719            value encoding, and these newer architectures would be ignored if
6720            the machine value was used.
6721
6722            Ie the -m switch is used to restrict which instructions will be
6723            disassembled.  If it is necessary to use the -m switch to tell
6724            objdump that an ARM binary is being disassembled, eg because the
6725            input is a raw binary file, but it is also desired to disassemble
6726            all ARM instructions then use "-marm".  This will select the
6727            "unknown" arm architecture which is compatible with any ARM
6728            instruction.  */
6729           info->mach = bfd_mach_arm_unknown;
6730
6731       /* Compute the architecture bitmask from the machine number.
6732          Note: This assumes that the machine number will not change
6733          during disassembly....  */
6734       select_arm_features (info->mach, & private.features);
6735
6736       private.last_mapping_sym = -1;
6737       private.last_mapping_addr = 0;
6738       private.last_stop_offset = 0;
6739
6740       info->private_data = & private;
6741     }
6742
6743   private_data = info->private_data;
6744
6745   /* Decide if our code is going to be little-endian, despite what the
6746      function argument might say.  */
6747   little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
6748
6749   /* For ELF, consult the symbol table to determine what kind of code
6750      or data we have.  */
6751   if (info->symtab_size != 0
6752       && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
6753     {
6754       bfd_vma addr;
6755       int n;
6756       int last_sym = -1;
6757       enum map_type type = MAP_ARM;
6758
6759       found = mapping_symbol_for_insn (pc, info, &type);
6760       last_sym = private_data->last_mapping_sym;
6761
6762       is_thumb = (private_data->last_type == MAP_THUMB);
6763       is_data = (private_data->last_type == MAP_DATA);
6764
6765       /* Look a little bit ahead to see if we should print out
6766          two or four bytes of data.  If there's a symbol,
6767          mapping or otherwise, after two bytes then don't
6768          print more.  */
6769       if (is_data)
6770         {
6771           size = 4 - (pc & 3);
6772           for (n = last_sym + 1; n < info->symtab_size; n++)
6773             {
6774               addr = bfd_asymbol_value (info->symtab[n]);
6775               if (addr > pc
6776                   && (info->section == NULL
6777                       || info->section == info->symtab[n]->section))
6778                 {
6779                   if (addr - pc < size)
6780                     size = addr - pc;
6781                   break;
6782                 }
6783             }
6784           /* If the next symbol is after three bytes, we need to
6785              print only part of the data, so that we can use either
6786              .byte or .short.  */
6787           if (size == 3)
6788             size = (pc & 1) ? 1 : 2;
6789         }
6790     }
6791
6792   if (info->symbols != NULL)
6793     {
6794       if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
6795         {
6796           coff_symbol_type * cs;
6797
6798           cs = coffsymbol (*info->symbols);
6799           is_thumb = (   cs->native->u.syment.n_sclass == C_THUMBEXT
6800                       || cs->native->u.syment.n_sclass == C_THUMBSTAT
6801                       || cs->native->u.syment.n_sclass == C_THUMBLABEL
6802                       || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
6803                       || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
6804         }
6805       else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
6806                && !found)
6807         {
6808           /* If no mapping symbol has been found then fall back to the type
6809              of the function symbol.  */
6810           elf_symbol_type *  es;
6811           unsigned int       type;
6812
6813           es = *(elf_symbol_type **)(info->symbols);
6814           type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6815
6816           is_thumb =
6817             ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6818               == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
6819         }
6820       else if (bfd_asymbol_flavour (*info->symbols)
6821                == bfd_target_mach_o_flavour)
6822         {
6823           bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
6824
6825           is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
6826         }
6827     }
6828
6829   if (force_thumb)
6830     is_thumb = TRUE;
6831
6832   if (is_data)
6833     info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6834   else
6835     info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6836
6837   info->bytes_per_line = 4;
6838
6839   /* PR 10263: Disassemble data if requested to do so by the user.  */
6840   if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
6841     {
6842       int i;
6843
6844       /* Size was already set above.  */
6845       info->bytes_per_chunk = size;
6846       printer = print_insn_data;
6847
6848       status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
6849       given = 0;
6850       if (little)
6851         for (i = size - 1; i >= 0; i--)
6852           given = b[i] | (given << 8);
6853       else
6854         for (i = 0; i < (int) size; i++)
6855           given = b[i] | (given << 8);
6856     }
6857   else if (!is_thumb)
6858     {
6859       /* In ARM mode endianness is a straightforward issue: the instruction
6860          is four bytes long and is either ordered 0123 or 3210.  */
6861       printer = print_insn_arm;
6862       info->bytes_per_chunk = 4;
6863       size = 4;
6864
6865       status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
6866       if (little_code)
6867         given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
6868       else
6869         given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
6870     }
6871   else
6872     {
6873       /* In Thumb mode we have the additional wrinkle of two
6874          instruction lengths.  Fortunately, the bits that determine
6875          the length of the current instruction are always to be found
6876          in the first two bytes.  */
6877       printer = print_insn_thumb16;
6878       info->bytes_per_chunk = 2;
6879       size = 2;
6880
6881       status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
6882       if (little_code)
6883         given = (b[0]) | (b[1] << 8);
6884       else
6885         given = (b[1]) | (b[0] << 8);
6886
6887       if (!status)
6888         {
6889           /* These bit patterns signal a four-byte Thumb
6890              instruction.  */
6891           if ((given & 0xF800) == 0xF800
6892               || (given & 0xF800) == 0xF000
6893               || (given & 0xF800) == 0xE800)
6894             {
6895               status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
6896               if (little_code)
6897                 given = (b[0]) | (b[1] << 8) | (given << 16);
6898               else
6899                 given = (b[1]) | (b[0] << 8) | (given << 16);
6900
6901               printer = print_insn_thumb32;
6902               size = 4;
6903             }
6904         }
6905
6906       if (ifthen_address != pc)
6907         find_ifthen_state (pc, info, little_code);
6908
6909       if (ifthen_state)
6910         {
6911           if ((ifthen_state & 0xf) == 0x8)
6912             ifthen_next_state = 0;
6913           else
6914             ifthen_next_state = (ifthen_state & 0xe0)
6915                                 | ((ifthen_state & 0xf) << 1);
6916         }
6917     }
6918
6919   if (status)
6920     {
6921       info->memory_error_func (status, pc, info);
6922       return -1;
6923     }
6924   if (info->flags & INSN_HAS_RELOC)
6925     /* If the instruction has a reloc associated with it, then
6926        the offset field in the instruction will actually be the
6927        addend for the reloc.  (We are using REL type relocs).
6928        In such cases, we can ignore the pc when computing
6929        addresses, since the addend is not currently pc-relative.  */
6930     pc = 0;
6931
6932   printer (pc, info, given);
6933
6934   if (is_thumb)
6935     {
6936       ifthen_state = ifthen_next_state;
6937       ifthen_address += size;
6938     }
6939   return size;
6940 }
6941
6942 int
6943 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
6944 {
6945   /* Detect BE8-ness and record it in the disassembler info.  */
6946   if (info->flavour == bfd_target_elf_flavour
6947       && info->section != NULL
6948       && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
6949     info->endian_code = BFD_ENDIAN_LITTLE;
6950
6951   return print_insn (pc, info, FALSE);
6952 }
6953
6954 int
6955 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
6956 {
6957   return print_insn (pc, info, TRUE);
6958 }
6959
6960 const disasm_options_and_args_t *
6961 disassembler_options_arm (void)
6962 {
6963   static disasm_options_and_args_t *opts_and_args;
6964
6965   if (opts_and_args == NULL)
6966     {
6967       disasm_options_t *opts;
6968       unsigned int i;
6969
6970       opts_and_args = XNEW (disasm_options_and_args_t);
6971       opts_and_args->args = NULL;
6972
6973       opts = &opts_and_args->options;
6974       opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
6975       opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
6976       opts->arg = NULL;
6977       for (i = 0; i < NUM_ARM_OPTIONS; i++)
6978         {
6979           opts->name[i] = regnames[i].name;
6980           if (regnames[i].description != NULL)
6981             opts->description[i] = _(regnames[i].description);
6982           else
6983             opts->description[i] = NULL;
6984         }
6985       /* The array we return must be NULL terminated.  */
6986       opts->name[i] = NULL;
6987       opts->description[i] = NULL;
6988     }
6989
6990   return opts_and_args;
6991 }
6992
6993 void
6994 print_arm_disassembler_options (FILE *stream)
6995 {
6996   unsigned int i, max_len = 0;
6997   fprintf (stream, _("\n\
6998 The following ARM specific disassembler options are supported for use with\n\
6999 the -M switch:\n"));
7000
7001   for (i = 0; i < NUM_ARM_OPTIONS; i++)
7002     {
7003       unsigned int len = strlen (regnames[i].name);
7004       if (max_len < len)
7005         max_len = len;
7006     }
7007
7008   for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
7009     fprintf (stream, "  %s%*c %s\n",
7010              regnames[i].name,
7011              (int)(max_len - strlen (regnames[i].name)), ' ',
7012              _(regnames[i].description));
7013 }