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Add assembler support for ARMv8-M Mainline
[thirdparty/binutils-gdb.git] / opcodes / arm-dis.c
1 /* Instruction printing code for the ARM
2 Copyright (C) 1994-2015 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
6 This file is part of libopcodes.
7
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
22
23 #include "sysdep.h"
24
25 #include "dis-asm.h"
26 #include "opcode/arm.h"
27 #include "opintl.h"
28 #include "safe-ctype.h"
29 #include "floatformat.h"
30
31 /* FIXME: This shouldn't be done here. */
32 #include "coff/internal.h"
33 #include "libcoff.h"
34 #include "elf-bfd.h"
35 #include "elf/internal.h"
36 #include "elf/arm.h"
37 #include "mach-o.h"
38
39 /* FIXME: Belongs in global header. */
40 #ifndef strneq
41 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
42 #endif
43
44 #ifndef NUM_ELEM
45 #define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
46 #endif
47
48 /* Cached mapping symbol state. */
49 enum map_type
50 {
51 MAP_ARM,
52 MAP_THUMB,
53 MAP_DATA
54 };
55
56 struct arm_private_data
57 {
58 /* The features to use when disassembling optional instructions. */
59 arm_feature_set features;
60
61 /* Whether any mapping symbols are present in the provided symbol
62 table. -1 if we do not know yet, otherwise 0 or 1. */
63 int has_mapping_symbols;
64
65 /* Track the last type (although this doesn't seem to be useful) */
66 enum map_type last_type;
67
68 /* Tracking symbol table information */
69 int last_mapping_sym;
70 bfd_vma last_mapping_addr;
71 };
72
73 struct opcode32
74 {
75 arm_feature_set arch; /* Architecture defining this insn. */
76 unsigned long value; /* If arch is 0 then value is a sentinel. */
77 unsigned long mask; /* Recognise insn if (op & mask) == value. */
78 const char * assembler; /* How to disassemble this insn. */
79 };
80
81 struct opcode16
82 {
83 arm_feature_set arch; /* Architecture defining this insn. */
84 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
85 const char *assembler; /* How to disassemble this insn. */
86 };
87
88 /* print_insn_coprocessor recognizes the following format control codes:
89
90 %% %
91
92 %c print condition code (always bits 28-31 in ARM mode)
93 %q print shifter argument
94 %u print condition code (unconditional in ARM mode,
95 UNPREDICTABLE if not AL in Thumb)
96 %A print address for ldc/stc/ldf/stf instruction
97 %B print vstm/vldm register list
98 %I print cirrus signed shift immediate: bits 0..3|4..6
99 %F print the COUNT field of a LFM/SFM instruction.
100 %P print floating point precision in arithmetic insn
101 %Q print floating point precision in ldf/stf insn
102 %R print floating point rounding mode
103
104 %<bitfield>c print as a condition code (for vsel)
105 %<bitfield>r print as an ARM register
106 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
107 %<bitfield>ru as %<>r but each u register must be unique.
108 %<bitfield>d print the bitfield in decimal
109 %<bitfield>k print immediate for VFPv3 conversion instruction
110 %<bitfield>x print the bitfield in hex
111 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
112 %<bitfield>f print a floating point constant if >7 else a
113 floating point register
114 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
115 %<bitfield>g print as an iWMMXt 64-bit register
116 %<bitfield>G print as an iWMMXt general purpose or control register
117 %<bitfield>D print as a NEON D register
118 %<bitfield>Q print as a NEON Q register
119 %<bitfield>E print a quarter-float immediate value
120
121 %y<code> print a single precision VFP reg.
122 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
123 %z<code> print a double precision VFP reg
124 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
125
126 %<bitfield>'c print specified char iff bitfield is all ones
127 %<bitfield>`c print specified char iff bitfield is all zeroes
128 %<bitfield>?ab... select from array of values in big endian order
129
130 %L print as an iWMMXt N/M width field.
131 %Z print the Immediate of a WSHUFH instruction.
132 %l like 'A' except use byte offsets for 'B' & 'H'
133 versions.
134 %i print 5-bit immediate in bits 8,3..0
135 (print "32" when 0)
136 %r print register offset address for wldt/wstr instruction. */
137
138 enum opcode_sentinel_enum
139 {
140 SENTINEL_IWMMXT_START = 1,
141 SENTINEL_IWMMXT_END,
142 SENTINEL_GENERIC_START
143 } opcode_sentinels;
144
145 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
146 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
147
148 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
149
150 static const struct opcode32 coprocessor_opcodes[] =
151 {
152 /* XScale instructions. */
153 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
154 0x0e200010, 0x0fff0ff0,
155 "mia%c\tacc0, %0-3r, %12-15r"},
156 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
157 0x0e280010, 0x0fff0ff0,
158 "miaph%c\tacc0, %0-3r, %12-15r"},
159 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
160 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
161 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
162 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
163 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
164 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
165
166 /* Intel Wireless MMX technology instructions. */
167 {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
168 {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
169 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
170 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
171 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
172 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
173 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
174 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
175 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
176 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
177 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
178 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
179 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
180 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
181 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
182 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
183 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
184 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
185 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
186 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
187 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
188 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
189 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
190 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
191 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
192 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
193 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
194 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
195 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
196 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
197 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
198 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
199 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
200 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
201 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
202 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
203 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
204 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
205 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
206 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
207 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
208 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
209 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
210 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
211 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
212 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
213 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
214 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
215 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
216 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
217 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
218 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
219 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
220 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
221 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
222 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
223 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
224 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
225 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
226 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
227 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
228 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
229 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
230 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
231 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
232 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
233 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
234 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
235 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
236 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
237 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
238 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
239 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
240 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
241 0x0e800120, 0x0f800ff0,
242 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
243 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
244 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
245 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
246 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
247 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
248 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
249 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
250 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
251 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
252 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
253 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
254 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
255 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
256 0x0e8000a0, 0x0f800ff0,
257 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
258 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
259 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
260 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
261 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
262 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
263 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
264 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
265 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
266 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
267 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
268 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
269 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
270 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
271 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
272 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
273 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
274 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
275 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
276 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
277 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
278 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
279 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
280 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
281 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
282 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
283 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
284 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
285 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
286 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
287 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
288 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
289 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
290 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
291 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
292 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
293 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
294 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
295 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
296 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
297 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
298 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
299 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
300 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
301 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
302 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
303 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
304 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
305 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
306 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
307 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
308 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
309 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
310 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
311 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
312 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
313 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
314 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
315 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
316 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
317 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
318 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
319 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
320 {ARM_FEATURE_CORE_LOW (0),
321 SENTINEL_IWMMXT_END, 0, "" },
322
323 /* Floating point coprocessor (FPA) instructions. */
324 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
325 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
326 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
327 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
328 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
329 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
330 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
331 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
332 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
333 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
334 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
335 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
336 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
337 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
338 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
339 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
340 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
341 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
342 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
343 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
344 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
345 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
346 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
347 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
348 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
349 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
350 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
351 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
352 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
353 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
354 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
355 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
356 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
357 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
358 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
359 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
360 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
361 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
362 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
363 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
364 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
365 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
366 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
367 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
368 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
369 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
370 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
371 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
372 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
373 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
374 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
375 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
376 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
377 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
378 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
379 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
380 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
381 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
382 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
383 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
384 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
385 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
386 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
387 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
388 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
389 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
390 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
391 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
392 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
393 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
394 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
395 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
396 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
397 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
398 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
399 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
400 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
401 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
402 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
403 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
404 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
405 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
406 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
407 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
408 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
409 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
410
411 /* Register load/store. */
412 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
413 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
414 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
415 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
416 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
417 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
418 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
419 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
420 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
421 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
422 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
423 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
424 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
425 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
426 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
427 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
428 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
429 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
430 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
431 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
432 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
433 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
434 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
435 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
436 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
437 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
438 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
439 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
440 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
441 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
442 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
443 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
444
445 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
446 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
447 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
448 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
449 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
450 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
451 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
452 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
453
454 /* Data transfer between ARM and NEON registers. */
455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
456 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
457 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
458 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
459 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
460 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
462 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
464 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
466 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
468 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
470 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
472 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
474 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
476 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
478 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
480 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
482 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
483 /* Half-precision conversion instructions. */
484 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
485 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
486 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
487 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
488 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
489 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
490 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
491 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
492
493 /* Floating point coprocessor (VFP) instructions. */
494 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
495 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
496 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
497 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
498 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
499 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
500 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
501 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
502 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
503 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
504 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
505 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
506 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
507 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
508 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
509 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
510 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
511 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
512 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
513 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
514 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
515 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
516 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
517 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
518 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
519 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
520 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
521 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
522 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
523 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
524 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
525 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
526 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
527 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
528 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
529 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
530 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
531 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
532 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
533 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
534 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
535 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
536 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
537 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
538 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
539 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
540 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
541 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
542 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
543 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
544 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
545 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
546 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
547 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
548 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
549 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
550 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
551 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
552 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
553 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
554 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
555 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
556 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
557 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
558 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
559 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
560 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
561 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
562 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
563 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
564 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
565 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
566 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
567 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
568 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
569 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
570 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
571 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
572 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
573 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
574 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
575 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
576 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
577 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
578 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
579 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
580 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
581 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
582 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
583 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
584 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
585 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
586 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
587 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
588 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
589 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
590 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
591 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
592 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
593 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
594 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
595 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
596 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
597 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
598 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
599 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
600 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
601 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
602 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
603 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
604 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
605 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
606 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
607 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
608 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
609 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
610 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
611 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
612 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
613 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
614 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
615 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
616 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
617 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
618 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
619 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
620 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
621 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
622 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
623 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
624 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
625 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
626 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
627 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
628
629 /* Cirrus coprocessor instructions. */
630 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
631 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
632 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
633 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
634 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
635 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
636 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
637 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
638 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
639 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
640 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
641 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
642 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
643 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
644 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
645 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
646 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
647 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
648 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
649 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
650 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
651 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
652 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
653 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
654 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
655 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
656 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
657 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
658 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
659 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
660 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
661 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
662 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
663 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
664 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
665 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
666 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
667 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
668 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
669 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
670 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
671 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
672 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
673 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
674 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
675 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
676 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
677 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
678 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
679 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
680 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
681 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
682 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
683 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
684 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
685 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
686 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
687 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
688 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
689 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
690 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
691 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
692 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
693 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
694 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
695 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
696 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
697 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
698 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
699 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
700 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
701 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
702 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
703 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
704 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
705 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
706 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
707 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
708 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
709 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
710 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
711 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
712 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
713 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
714 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
715 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
716 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
717 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
718 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
719 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
720 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
721 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
722 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
723 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
724 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
725 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
726 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
727 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
728 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
729 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
730 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
731 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
732 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
733 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
734 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
735 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
736 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
737 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
738 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
739 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
740 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
741 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
742 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
743 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
744 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
745 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
746 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
747 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
748 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
749 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
750 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
751 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
752 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
753 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
754 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
755 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
756 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
757 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
758 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
759 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
760 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
761 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
762 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
763 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
764 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
765 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
766 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
767 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
768 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
769 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
770 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
771 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
772 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
773 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
774 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
775 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
776 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
777 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
778 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
779 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
780 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
781 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
782 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
783 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
784 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
785 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
786 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
787 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
788 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
789 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
790 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
791 0x0e000600, 0x0ff00f10,
792 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
793 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
794 0x0e100600, 0x0ff00f10,
795 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
796 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
797 0x0e200600, 0x0ff00f10,
798 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
799 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
800 0x0e300600, 0x0ff00f10,
801 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
802
803 /* VFP Fused multiply add instructions. */
804 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
805 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
806 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
807 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
808 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
809 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
810 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
811 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
812 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
813 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
814 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
815 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
816 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
817 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
818 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
819 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
820
821 /* FP v5. */
822 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823 0xfe000a00, 0xff800f00, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
824 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
825 0xfe000b00, 0xff800f00, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
826 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
827 0xfe800a00, 0xffb00f40, "vmaxnm%u.f32\t%y1, %y2, %y0"},
828 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
829 0xfe800b00, 0xffb00f40, "vmaxnm%u.f64\t%z1, %z2, %z0"},
830 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
831 0xfe800a40, 0xffb00f40, "vminnm%u.f32\t%y1, %y2, %y0"},
832 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
833 0xfe800b40, 0xffb00f40, "vminnm%u.f64\t%z1, %z2, %z0"},
834 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
835 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
836 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
837 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
838 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
839 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
840 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
841 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
842 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
843 0xfeb80a40, 0xffbc0f50, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
844 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
845 0xfeb80b40, 0xffbc0f50, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
846
847 /* Generic coprocessor instructions. */
848 {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
850 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
852 0x0c500000, 0x0ff00000,
853 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
855 0x0e000000, 0x0f000010,
856 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
858 0x0e10f010, 0x0f10f010,
859 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
861 0x0e100010, 0x0f100010,
862 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
864 0x0e000010, 0x0f100010,
865 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
867 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
869 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
870
871 /* V6 coprocessor instructions. */
872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
873 0xfc500000, 0xfff00000,
874 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
876 0xfc400000, 0xfff00000,
877 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
878
879 /* V5 coprocessor instructions. */
880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
881 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
883 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
885 0xfe000000, 0xff000010,
886 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
888 0xfe000010, 0xff100010,
889 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
891 0xfe100010, 0xff100010,
892 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
893
894 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
895 };
896
897 /* Neon opcode table: This does not encode the top byte -- that is
898 checked by the print_insn_neon routine, as it depends on whether we are
899 doing thumb32 or arm32 disassembly. */
900
901 /* print_insn_neon recognizes the following format control codes:
902
903 %% %
904
905 %c print condition code
906 %u print condition code (unconditional in ARM mode,
907 UNPREDICTABLE if not AL in Thumb)
908 %A print v{st,ld}[1234] operands
909 %B print v{st,ld}[1234] any one operands
910 %C print v{st,ld}[1234] single->all operands
911 %D print scalar
912 %E print vmov, vmvn, vorr, vbic encoded constant
913 %F print vtbl,vtbx register list
914
915 %<bitfield>r print as an ARM register
916 %<bitfield>d print the bitfield in decimal
917 %<bitfield>e print the 2^N - bitfield in decimal
918 %<bitfield>D print as a NEON D register
919 %<bitfield>Q print as a NEON Q register
920 %<bitfield>R print as a NEON D or Q register
921 %<bitfield>Sn print byte scaled width limited by n
922 %<bitfield>Tn print short scaled width limited by n
923 %<bitfield>Un print long scaled width limited by n
924
925 %<bitfield>'c print specified char iff bitfield is all ones
926 %<bitfield>`c print specified char iff bitfield is all zeroes
927 %<bitfield>?ab... select from array of values in big endian order. */
928
929 static const struct opcode32 neon_opcodes[] =
930 {
931 /* Extract. */
932 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
933 0xf2b00840, 0xffb00850,
934 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
935 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
936 0xf2b00000, 0xffb00810,
937 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
938
939 /* Move data element to all lanes. */
940 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
941 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
942 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
943 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
944 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
945 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
946
947 /* Table lookup. */
948 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
949 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
950 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
951 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
952
953 /* Half-precision conversions. */
954 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
955 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
956 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
957 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
958
959 /* NEON fused multiply add instructions. */
960 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
961 0xf2000c10, 0xffa00f10, "vfma%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
962 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
963 0xf2200c10, 0xffa00f10, "vfms%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
964
965 /* Two registers, miscellaneous. */
966 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
967 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
968 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
969 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
970 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
971 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
972 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
973 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
974 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
975 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
976 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
977 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
978 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
979 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
980 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
981 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
982 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
983 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
984 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
985 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
986 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
987 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
988 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
989 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
990 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
991 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
992 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
993 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
994 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
995 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
996 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
997 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
998 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
999 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1000 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1001 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1002 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1003 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1004 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1005 0xf3b20300, 0xffb30fd0,
1006 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1007 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1008 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1009 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1010 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1011 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1012 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1013 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1014 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1015 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1016 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1017 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1018 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1019 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1020 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1021 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1022 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1023 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1024 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1025 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1026 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1027 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1028 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1029 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1030 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1031 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1032 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1033 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1034 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1035 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1036 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1037 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1038 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1039 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1040 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1041 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1042 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1043 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1044 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1045 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1046 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1047 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1048 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1049 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1050 0xf3b30600, 0xffb30e10,
1051 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1052
1053 /* Three registers of the same length. */
1054 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1055 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1056 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1057 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1058 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1059 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1060 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1061 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1062 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1063 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1064 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1065 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1066 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1067 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1068 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1069 0xf3000f10, 0xffa00f10, "vmaxnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1070 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1071 0xf3200f10, 0xffa00f10, "vminnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1072 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1073 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1074 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1075 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1076 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1077 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1078 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1079 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1080 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1081 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1082 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1083 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1084 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1085 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1086 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1087 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1088 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1089 0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1090 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1091 0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1092 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1093 0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1094 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1095 0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1096 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1097 0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1098 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1099 0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1100 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1101 0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1102 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1103 0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1104 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1105 0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1106 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1107 0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1108 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1109 0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1110 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1111 0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1112 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1113 0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1114 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1115 0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1116 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1117 0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1118 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1119 0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1120 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1121 0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1122 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1123 0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1124 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1125 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1126 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1127 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1128 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1129 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1130 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1131 0xf2000b00, 0xff800f10,
1132 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1133 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1134 0xf2000b10, 0xff800f10,
1135 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1136 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1137 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1138 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1139 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1140 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1141 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1142 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1143 0xf3000b00, 0xff800f10,
1144 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1145 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1146 0xf2000000, 0xfe800f10,
1147 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1148 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1149 0xf2000010, 0xfe800f10,
1150 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1151 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1152 0xf2000100, 0xfe800f10,
1153 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1154 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1155 0xf2000200, 0xfe800f10,
1156 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1157 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1158 0xf2000210, 0xfe800f10,
1159 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1160 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1161 0xf2000300, 0xfe800f10,
1162 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1163 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1164 0xf2000310, 0xfe800f10,
1165 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1166 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1167 0xf2000400, 0xfe800f10,
1168 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1169 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1170 0xf2000410, 0xfe800f10,
1171 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1172 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1173 0xf2000500, 0xfe800f10,
1174 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1175 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1176 0xf2000510, 0xfe800f10,
1177 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1178 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1179 0xf2000600, 0xfe800f10,
1180 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1181 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1182 0xf2000610, 0xfe800f10,
1183 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1184 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1185 0xf2000700, 0xfe800f10,
1186 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1187 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1188 0xf2000710, 0xfe800f10,
1189 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1190 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1191 0xf2000910, 0xfe800f10,
1192 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1193 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1194 0xf2000a00, 0xfe800f10,
1195 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1196 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1197 0xf2000a10, 0xfe800f10,
1198 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1199 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1200 0xf3000b10, 0xff800f10,
1201 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1202 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1203 0xf3000c10, 0xff800f10,
1204 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1205
1206 /* One register and an immediate value. */
1207 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1208 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1209 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1210 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1211 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1212 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1213 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1214 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1215 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1216 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1217 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1218 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1219 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1220 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1221 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1222 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1223 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1224 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1225 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1226 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1227 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1228 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1229 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1230 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1231 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1232 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1233
1234 /* Two registers and a shift amount. */
1235 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1236 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1237 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1238 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1239 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1240 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1241 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1242 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1243 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1244 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1245 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1246 0xf2880950, 0xfeb80fd0,
1247 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1248 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1249 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1250 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1251 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1252 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1253 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1254 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1255 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1256 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1257 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1258 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1259 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1260 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1261 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1262 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1263 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1264 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1265 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1266 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1267 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1268 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1269 0xf2900950, 0xfeb00fd0,
1270 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1271 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1272 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1273 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1274 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1275 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1276 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1277 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1278 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1279 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1280 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1281 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1282 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1283 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1284 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1285 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1286 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1287 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1288 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1289 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1290 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1291 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1292 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1293 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1294 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1295 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1296 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1297 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1298 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1299 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1300 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1301 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1302 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1303 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1304 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1305 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1306 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1307 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1308 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1309 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1310 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1311 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1312 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1313 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1314 0xf2a00950, 0xfea00fd0,
1315 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1316 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1317 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1318 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1319 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1320 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1321 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1322 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1323 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1324 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1325 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1326 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1327 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1328 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1329 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1330 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1331 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1332 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1333 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1334 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1335 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1336 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1337 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1338 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1339 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1340 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1341 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1342 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1343 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1344 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1345 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1346 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1347 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1348 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1349 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1350 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1351 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1352 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1353 0xf2a00e10, 0xfea00e90,
1354 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1355
1356 /* Three registers of different lengths. */
1357 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1358 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1359 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1360 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1361 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1362 0xf2800400, 0xff800f50,
1363 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1364 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1365 0xf2800600, 0xff800f50,
1366 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1367 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1368 0xf2800900, 0xff800f50,
1369 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1370 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1371 0xf2800b00, 0xff800f50,
1372 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1373 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1374 0xf2800d00, 0xff800f50,
1375 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1376 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1377 0xf3800400, 0xff800f50,
1378 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1379 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1380 0xf3800600, 0xff800f50,
1381 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1382 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1383 0xf2800000, 0xfe800f50,
1384 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1385 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1386 0xf2800100, 0xfe800f50,
1387 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1388 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1389 0xf2800200, 0xfe800f50,
1390 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1391 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1392 0xf2800300, 0xfe800f50,
1393 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1394 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1395 0xf2800500, 0xfe800f50,
1396 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1397 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1398 0xf2800700, 0xfe800f50,
1399 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1400 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1401 0xf2800800, 0xfe800f50,
1402 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1403 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1404 0xf2800a00, 0xfe800f50,
1405 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1406 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1407 0xf2800c00, 0xfe800f50,
1408 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1409
1410 /* Two registers and a scalar. */
1411 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1412 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1413 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1414 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1415 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1416 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1417 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1418 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1419 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1420 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1421 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1422 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1423 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1424 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1425 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1426 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1427 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1428 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1429 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1430 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1431 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1432 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1433 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1434 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1435 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1436 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1437 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1438 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1439 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1440 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1441 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1442 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1443 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1444 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1445 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1446 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1447 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1448 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1449 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1450 0xf2800240, 0xfe800f50,
1451 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1452 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1453 0xf2800640, 0xfe800f50,
1454 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1456 0xf2800a40, 0xfe800f50,
1457 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1458 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1459 0xf2800e40, 0xff800f50,
1460 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1462 0xf2800f40, 0xff800f50,
1463 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1464 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1465 0xf3800e40, 0xff800f50,
1466 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1468 0xf3800f40, 0xff800f50,
1469 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1470 },
1471
1472 /* Element and structure load/store. */
1473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1474 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1476 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1478 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1480 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1482 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1484 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1486 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1487 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1488 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1489 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1490 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1492 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1494 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1495 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1496 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1498 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1499 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1500 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1502 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1503 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1504 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1507 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1511
1512 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
1513 };
1514
1515 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
1516 ordered: they must be searched linearly from the top to obtain a correct
1517 match. */
1518
1519 /* print_insn_arm recognizes the following format control codes:
1520
1521 %% %
1522
1523 %a print address for ldr/str instruction
1524 %s print address for ldr/str halfword/signextend instruction
1525 %S like %s but allow UNPREDICTABLE addressing
1526 %b print branch destination
1527 %c print condition code (always bits 28-31)
1528 %m print register mask for ldm/stm instruction
1529 %o print operand2 (immediate or register + shift)
1530 %p print 'p' iff bits 12-15 are 15
1531 %t print 't' iff bit 21 set and bit 24 clear
1532 %B print arm BLX(1) destination
1533 %C print the PSR sub type.
1534 %U print barrier type.
1535 %P print address for pli instruction.
1536
1537 %<bitfield>r print as an ARM register
1538 %<bitfield>T print as an ARM register + 1
1539 %<bitfield>R as %r but r15 is UNPREDICTABLE
1540 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1541 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
1542 %<bitfield>d print the bitfield in decimal
1543 %<bitfield>W print the bitfield plus one in decimal
1544 %<bitfield>x print the bitfield in hex
1545 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
1546
1547 %<bitfield>'c print specified char iff bitfield is all ones
1548 %<bitfield>`c print specified char iff bitfield is all zeroes
1549 %<bitfield>?ab... select from array of values in big endian order
1550
1551 %e print arm SMI operand (bits 0..7,8..19).
1552 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
1553 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
1554 %R print the SPSR/CPSR or banked register of an MRS. */
1555
1556 static const struct opcode32 arm_opcodes[] =
1557 {
1558 /* ARM instructions. */
1559 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1560 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1562 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
1563
1564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
1565 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1567 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1569 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
1571 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1573 0x00800090, 0x0fa000f0,
1574 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1576 0x00a00090, 0x0fa000f0,
1577 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1578
1579 /* V8 instructions. */
1580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1581 0x0320f005, 0x0fffffff, "sevl"},
1582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1583 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
1584 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
1585 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
1586 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1587 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1589 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
1590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1591 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
1592 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1593 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
1594 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1595 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
1596 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1597 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
1598 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1599 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
1600 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1601 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
1602 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1603 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
1604 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1605 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
1606 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1607 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
1608 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1609 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
1610 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1611 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
1612 /* CRC32 instructions. */
1613 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1614 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
1615 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1616 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
1617 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1618 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
1619 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1620 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
1621 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1622 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
1623 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1624 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
1625
1626 /* Privileged Access Never extension instructions. */
1627 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
1628 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
1629
1630 /* Virtualization Extension instructions. */
1631 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
1632 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
1633
1634 /* Integer Divide Extension instructions. */
1635 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1636 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
1637 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1638 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
1639
1640 /* MP Extension instructions. */
1641 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
1642
1643 /* V7 instructions. */
1644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
1645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
1646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
1647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
1648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
1649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
1650 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
1651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
1652 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
1653
1654 /* ARM V6T2 instructions. */
1655 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1656 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
1657 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1658 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
1659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1660 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1662 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
1663
1664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1665 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
1666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1667 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
1668
1669 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1670 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
1671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1672 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
1673 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1674 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
1675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1676 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
1677
1678 /* ARM Security extension instructions. */
1679 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
1680 0x01600070, 0x0ff000f0, "smc%c\t%e"},
1681
1682 /* ARM V6K instructions. */
1683 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1684 0xf57ff01f, 0xffffffff, "clrex"},
1685 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1686 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
1687 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1688 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
1689 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1690 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
1691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1692 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
1693 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1694 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
1695 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1696 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
1697
1698 /* ARM V6K NOP hints. */
1699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1700 0x0320f001, 0x0fffffff, "yield%c"},
1701 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1702 0x0320f002, 0x0fffffff, "wfe%c"},
1703 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1704 0x0320f003, 0x0fffffff, "wfi%c"},
1705 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1706 0x0320f004, 0x0fffffff, "sev%c"},
1707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1708 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
1709
1710 /* ARM V6 instructions. */
1711 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1712 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
1713 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1714 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
1715 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1716 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
1717 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1718 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
1719 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1720 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
1721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1722 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
1723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1724 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
1725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1726 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
1727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1728 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
1729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1730 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
1731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1732 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
1733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1734 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
1735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1736 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
1737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1738 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
1739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1740 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
1741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1742 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
1743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1744 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
1745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1746 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
1747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1748 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
1749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1750 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
1751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1752 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
1753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1754 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
1755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1756 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
1757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1758 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
1759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1760 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
1761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1762 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
1763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1764 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
1765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1766 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
1767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1768 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
1769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1770 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
1771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1772 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
1773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1774 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
1775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1776 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
1777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1778 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
1779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1780 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
1781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1782 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
1783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1784 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
1785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1786 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
1787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1788 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
1789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1790 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
1791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1792 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
1793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1794 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
1795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1796 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
1797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1798 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
1799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1800 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
1801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1802 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
1803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1804 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
1805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1806 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
1807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1808 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
1809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1810 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
1811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1812 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
1813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1814 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
1815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1816 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
1817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1818 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
1819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1820 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
1821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1822 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
1823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1824 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
1825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1826 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
1827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1828 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
1829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1830 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
1831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1832 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
1833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1834 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
1835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1836 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
1837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1838 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
1839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1840 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
1841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1842 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
1843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1844 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
1845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1846 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
1847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1848 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
1849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1850 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
1851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1852 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
1853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1854 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
1855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1856 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
1857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1858 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
1859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1860 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
1861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1862 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1864 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1866 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1868 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
1869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1870 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1872 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1874 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1876 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
1877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1878 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1880 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1882 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1884 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
1885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1886 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1888 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1890 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1892 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
1893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1894 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1896 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1898 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
1899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1900 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
1901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1902 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1904 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1906 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1908 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
1909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1910 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
1911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1912 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
1913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1914 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
1915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1916 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1918 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1920 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1922 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1924 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
1925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1926 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1928 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1930 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
1931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1932 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
1933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1934 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
1935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1936 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
1937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1938 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
1939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1940 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
1941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1942 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
1943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1944 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
1945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1946 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1948 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
1949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1950 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
1951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1952 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
1953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1954 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
1955
1956 /* V5J instruction. */
1957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
1958 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
1959
1960 /* V5 Instructions. */
1961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1962 0xe1200070, 0xfff000f0,
1963 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
1964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1965 0xfa000000, 0xfe000000, "blx\t%B"},
1966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1967 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
1968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1969 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
1970
1971 /* V5E "El Segundo" Instructions. */
1972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1973 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
1974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1975 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
1976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1977 0xf450f000, 0xfc70f000, "pld\t%a"},
1978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1979 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1981 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1983 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1985 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
1986
1987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1988 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1990 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
1991
1992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1993 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1995 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1997 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1999 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2000
2001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2002 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2004 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2006 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2008 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2009
2010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2011 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2013 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2014
2015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2016 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
2017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2018 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2020 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
2021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2022 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
2023
2024 /* ARM Instructions. */
2025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2026 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2027
2028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2029 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2031 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2033 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2035 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2037 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2039 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2040
2041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2042 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2044 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2046 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2048 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2049
2050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2051 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2053 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2055 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2057 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2058
2059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2060 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2062 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2064 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2065
2066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2067 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2069 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2071 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2072
2073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2074 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2076 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2078 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2079
2080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2081 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2083 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2085 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2086
2087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2088 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2090 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2092 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2093
2094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2095 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2097 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2099 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2100
2101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2102 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2104 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2106 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2107
2108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2109 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2111 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2113 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2114
2115 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2116 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2118 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2120 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2121
2122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2123 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2125 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2127 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2128
2129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2130 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
2131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2132 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
2133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2134 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
2135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2136 0x0130f000, 0x0ff0f010, "bx%c\t%0-3r"},
2137
2138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2139 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2141 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2143 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2144
2145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2146 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2148 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2150 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2151
2152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2153 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2155 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2157 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2158
2159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2160 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2162 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2164 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2166 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2168 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2170 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2172 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2173
2174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2175 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2177 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2179 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2180
2181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2182 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2184 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2186 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2187
2188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2189 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2191 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2192
2193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2194 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2195
2196 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2197 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2199 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2200
2201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2202 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2203 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2204 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2206 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2208 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2210 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2212 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2214 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2216 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2217 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2218 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2220 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2222 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2224 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2226 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2228 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2230 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2232 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2234 0x092d0000, 0x0fff0000, "push%c\t%m"},
2235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2236 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2238 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2239
2240 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2241 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2242 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2243 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2245 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2247 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2249 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2250 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2251 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2252 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2253 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2255 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2257 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2259 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2261 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2263 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2265 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2266 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2267 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2269 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2271 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2273 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2275 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2277 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2278
2279 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2280 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2281 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2282 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
2283
2284 /* The rest. */
2285 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2286 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
2287 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2288 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2289 {ARM_FEATURE_CORE_LOW (0),
2290 0x00000000, 0x00000000, 0}
2291 };
2292
2293 /* print_insn_thumb16 recognizes the following format control codes:
2294
2295 %S print Thumb register (bits 3..5 as high number if bit 6 set)
2296 %D print Thumb register (bits 0..2 as high number if bit 7 set)
2297 %<bitfield>I print bitfield as a signed decimal
2298 (top bit of range being the sign bit)
2299 %N print Thumb register mask (with LR)
2300 %O print Thumb register mask (with PC)
2301 %M print Thumb register mask
2302 %b print CZB's 6-bit unsigned branch destination
2303 %s print Thumb right-shift immediate (6..10; 0 == 32).
2304 %c print the condition code
2305 %C print the condition code, or "s" if not conditional
2306 %x print warning if conditional an not at end of IT block"
2307 %X print "\t; unpredictable <IT:code>" if conditional
2308 %I print IT instruction suffix and operands
2309 %W print Thumb Writeback indicator for LDMIA
2310 %<bitfield>r print bitfield as an ARM register
2311 %<bitfield>d print bitfield as a decimal
2312 %<bitfield>H print (bitfield * 2) as a decimal
2313 %<bitfield>W print (bitfield * 4) as a decimal
2314 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
2315 %<bitfield>B print Thumb branch destination (signed displacement)
2316 %<bitfield>c print bitfield as a condition code
2317 %<bitnum>'c print specified char iff bit is one
2318 %<bitnum>?ab print a if bit is one else print b. */
2319
2320 static const struct opcode16 thumb_opcodes[] =
2321 {
2322 /* Thumb instructions. */
2323
2324 /* ARM V8 instructions. */
2325 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
2326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
2327 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
2328
2329 /* ARM V6K no-argument instructions. */
2330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2331 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
2336
2337 /* ARM V6T2 instructions. */
2338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2339 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
2340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
2341
2342 /* ARM V6. */
2343 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2345 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
2354
2355 /* ARM V5 ISA extends Thumb. */
2356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2357 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
2358 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
2359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2360 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
2361 /* ARM V4T ISA (Thumb v1). */
2362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2363 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
2364 /* Format 4. */
2365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
2381 /* format 13 */
2382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
2384 /* format 5 */
2385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
2386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
2387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
2389 /* format 14 */
2390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
2391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
2392 /* format 2 */
2393 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2394 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2395 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2396 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2397 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2398 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2399 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2400 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
2401 /* format 8 */
2402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2403 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2405 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2407 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
2408 /* format 7 */
2409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2410 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2411 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2412 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2413 /* format 1 */
2414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2415 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2416 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2418 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
2419 /* format 3 */
2420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2421 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2422 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
2424 /* format 6 */
2425 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2427 0x4800, 0xF800,
2428 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
2429 /* format 9 */
2430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2431 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2433 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2434 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2435 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2437 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
2438 /* format 10 */
2439 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2440 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2441 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2442 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
2443 /* format 11 */
2444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2445 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2447 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
2448 /* format 12 */
2449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2450 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2451 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2452 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
2453 /* format 15 */
2454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2455 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
2456 /* format 17 */
2457 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
2458 /* format 16 */
2459 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
2461 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
2462 /* format 18 */
2463 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
2464
2465 /* The E800 .. FFFF range is unconditionally redirected to the
2466 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2467 are processed via that table. Thus, we can never encounter a
2468 bare "second half of BL/BLX(1)" instruction here. */
2469 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
2470 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2471 };
2472
2473 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
2474 We adopt the convention that hw1 is the high 16 bits of .value and
2475 .mask, hw2 the low 16 bits.
2476
2477 print_insn_thumb32 recognizes the following format control codes:
2478
2479 %% %
2480
2481 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2482 %M print a modified 12-bit immediate (same location)
2483 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2484 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
2485 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
2486 %S print a possibly-shifted Rm
2487
2488 %L print address for a ldrd/strd instruction
2489 %a print the address of a plain load/store
2490 %w print the width and signedness of a core load/store
2491 %m print register mask for ldm/stm
2492
2493 %E print the lsb and width fields of a bfc/bfi instruction
2494 %F print the lsb and width fields of a sbfx/ubfx instruction
2495 %b print a conditional branch offset
2496 %B print an unconditional branch offset
2497 %s print the shift field of an SSAT instruction
2498 %R print the rotation field of an SXT instruction
2499 %U print barrier type.
2500 %P print address for pli instruction.
2501 %c print the condition code
2502 %x print warning if conditional an not at end of IT block"
2503 %X print "\t; unpredictable <IT:code>" if conditional
2504
2505 %<bitfield>d print bitfield in decimal
2506 %<bitfield>D print bitfield plus one in decimal
2507 %<bitfield>W print bitfield*4 in decimal
2508 %<bitfield>r print bitfield as an ARM register
2509 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
2510 %<bitfield>S as %<>R but r13 is UNPREDICTABLE
2511 %<bitfield>c print bitfield as a condition code
2512
2513 %<bitfield>'c print specified char iff bitfield is all ones
2514 %<bitfield>`c print specified char iff bitfield is all zeroes
2515 %<bitfield>?ab... select from array of values in big endian order
2516
2517 With one exception at the bottom (done because BL and BLX(1) need
2518 to come dead last), this table was machine-sorted first in
2519 decreasing order of number of bits set in the mask, then in
2520 increasing numeric order of mask, then in increasing numeric order
2521 of opcode. This order is not the clearest for a human reader, but
2522 is guaranteed never to catch a special-case bit pattern with a more
2523 general mask, which is important, because this instruction encoding
2524 makes heavy use of special-case bit patterns. */
2525 static const struct opcode32 thumb32_opcodes[] =
2526 {
2527 /* V8-M instructions. */
2528 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2529 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
2530 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2531 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
2532
2533 /* V8 instructions. */
2534 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2535 0xf3af8005, 0xffffffff, "sevl%c.w"},
2536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2537 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2539 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
2540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2541 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
2542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2543 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
2544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2545 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
2546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2547 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
2548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2549 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
2550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2551 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
2552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2553 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2555 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2557 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
2558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2559 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2561 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2563 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2565 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
2566
2567 /* CRC32 instructions. */
2568 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2569 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11S, %16-19S, %0-3S"},
2570 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2571 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11S, %16-19S, %0-3S"},
2572 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2573 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11S, %16-19S, %0-3S"},
2574 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2575 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11S, %16-19S, %0-3S"},
2576 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2577 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11S, %16-19S, %0-3S"},
2578 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2579 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11S, %16-19S, %0-3S"},
2580
2581 /* V7 instructions. */
2582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
2583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
2584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
2585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
2586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
2587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
2588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
2589 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2590 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
2591 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2592 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
2593
2594 /* Virtualization Extension instructions. */
2595 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
2596 /* We skip ERET as that is SUBS pc, lr, #0. */
2597
2598 /* MP Extension instructions. */
2599 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
2600
2601 /* Security extension instructions. */
2602 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
2603
2604 /* Instructions defined in the basic V6T2 set. */
2605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
2606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
2607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
2608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
2609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
2610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2611 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
2612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
2613
2614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2615 0xf3bf8f2f, 0xffffffff, "clrex%c"},
2616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2617 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
2618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2619 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
2620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2621 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
2622 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2623 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
2624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2625 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
2626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2627 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
2628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2629 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
2630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2631 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
2632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2633 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
2634 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2635 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
2636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2637 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
2638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2639 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
2640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2641 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
2642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2643 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
2644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2645 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
2646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2647 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
2648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2649 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
2650 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2651 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
2652 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2653 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
2654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2655 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
2656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2657 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
2658 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2659 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
2660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2661 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
2662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2663 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
2664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2665 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
2666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2667 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
2668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2669 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
2670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2671 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
2672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2673 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
2674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2675 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
2676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2677 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
2678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2679 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
2680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2681 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
2682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2683 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
2684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2685 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
2686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2687 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
2688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2689 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
2690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2691 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
2692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2693 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
2694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2695 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
2696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2697 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
2698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2699 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
2700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2701 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
2702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2703 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
2704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2705 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
2706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2707 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
2708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2709 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
2710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2711 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
2712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2713 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
2714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2715 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
2716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2717 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
2718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2719 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
2720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2721 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
2722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2723 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
2724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2725 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
2726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2727 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
2728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2729 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
2730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2731 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
2732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2733 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
2734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2735 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
2736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2737 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
2738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2739 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
2740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2741 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
2742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2743 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
2744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2745 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
2746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2747 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
2748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2749 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
2750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2751 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
2752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2753 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
2754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2755 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
2756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2757 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
2758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2759 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
2760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2761 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
2762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2763 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2765 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2767 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2769 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
2770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2771 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
2772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2773 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
2774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2775 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
2776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2777 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
2778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2779 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2781 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
2782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2783 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
2784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2785 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2787 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2789 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2791 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2793 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2795 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2797 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2799 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
2800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2801 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
2802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2803 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
2804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2805 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
2806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2807 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
2808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2809 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
2810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2811 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
2812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2813 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
2814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2815 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
2816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2817 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
2818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2819 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
2820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2821 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
2822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2823 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2825 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2827 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2829 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2831 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2833 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2835 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2837 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2839 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
2840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2841 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
2842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2843 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
2844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2845 0xf810f000, 0xff70f000, "pld%c\t%a"},
2846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2847 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2849 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2851 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2853 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2855 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2857 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2859 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2861 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
2862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2863 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
2864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2865 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
2866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2867 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
2868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2869 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
2870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2871 0xfb100000, 0xfff000c0,
2872 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2874 0xfbc00080, 0xfff000c0,
2875 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
2876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2877 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
2878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2879 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
2880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2881 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
2882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2883 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
2884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2885 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
2886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2887 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
2888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2889 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
2890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2891 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
2892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2893 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
2894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2895 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
2896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2897 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
2898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2899 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
2900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2901 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
2902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2903 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
2904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2905 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
2906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2907 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
2908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2909 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
2910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2911 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
2912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2913 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
2914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2915 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
2916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2917 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
2918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2919 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
2920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2921 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
2922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2923 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
2924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2925 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
2926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2927 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
2928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2929 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
2930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2931 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
2932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2933 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
2934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2935 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
2936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2937 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
2938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2939 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
2940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2941 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
2942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2943 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
2944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2945 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
2946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2947 0xe9400000, 0xff500000,
2948 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
2949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2950 0xe9500000, 0xff500000,
2951 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
2952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2953 0xe8600000, 0xff700000,
2954 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
2955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2956 0xe8700000, 0xff700000,
2957 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
2958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2959 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
2960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2961 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
2962
2963 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
2964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2965 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
2966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2967 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
2968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2969 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
2970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2971 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
2972
2973 /* These have been 32-bit since the invention of Thumb. */
2974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2975 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
2976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2977 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
2978
2979 /* Fallback. */
2980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2981 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2982 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2983 };
2984
2985 static const char *const arm_conditional[] =
2986 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
2987 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
2988
2989 static const char *const arm_fp_const[] =
2990 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
2991
2992 static const char *const arm_shift[] =
2993 {"lsl", "lsr", "asr", "ror"};
2994
2995 typedef struct
2996 {
2997 const char *name;
2998 const char *description;
2999 const char *reg_names[16];
3000 }
3001 arm_regname;
3002
3003 static const arm_regname regnames[] =
3004 {
3005 { "raw" , "Select raw register names",
3006 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
3007 { "gcc", "Select register names used by GCC",
3008 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
3009 { "std", "Select register names used in ARM's ISA documentation",
3010 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
3011 { "apcs", "Select register names used in the APCS",
3012 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
3013 { "atpcs", "Select register names used in the ATPCS",
3014 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
3015 { "special-atpcs", "Select special register names used in the ATPCS",
3016 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
3017 };
3018
3019 static const char *const iwmmxt_wwnames[] =
3020 {"b", "h", "w", "d"};
3021
3022 static const char *const iwmmxt_wwssnames[] =
3023 {"b", "bus", "bc", "bss",
3024 "h", "hus", "hc", "hss",
3025 "w", "wus", "wc", "wss",
3026 "d", "dus", "dc", "dss"
3027 };
3028
3029 static const char *const iwmmxt_regnames[] =
3030 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3031 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3032 };
3033
3034 static const char *const iwmmxt_cregnames[] =
3035 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3036 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3037 };
3038
3039 /* Default to GCC register name set. */
3040 static unsigned int regname_selected = 1;
3041
3042 #define NUM_ARM_REGNAMES NUM_ELEM (regnames)
3043 #define arm_regnames regnames[regname_selected].reg_names
3044
3045 static bfd_boolean force_thumb = FALSE;
3046
3047 /* Current IT instruction state. This contains the same state as the IT
3048 bits in the CPSR. */
3049 static unsigned int ifthen_state;
3050 /* IT state for the next instruction. */
3051 static unsigned int ifthen_next_state;
3052 /* The address of the insn for which the IT state is valid. */
3053 static bfd_vma ifthen_address;
3054 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
3055 /* Indicates that the current Conditional state is unconditional or outside
3056 an IT block. */
3057 #define COND_UNCOND 16
3058
3059 \f
3060 /* Functions. */
3061 int
3062 get_arm_regname_num_options (void)
3063 {
3064 return NUM_ARM_REGNAMES;
3065 }
3066
3067 int
3068 set_arm_regname_option (int option)
3069 {
3070 int old = regname_selected;
3071 regname_selected = option;
3072 return old;
3073 }
3074
3075 int
3076 get_arm_regnames (int option,
3077 const char **setname,
3078 const char **setdescription,
3079 const char *const **register_names)
3080 {
3081 *setname = regnames[option].name;
3082 *setdescription = regnames[option].description;
3083 *register_names = regnames[option].reg_names;
3084 return 16;
3085 }
3086
3087 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3088 Returns pointer to following character of the format string and
3089 fills in *VALUEP and *WIDTHP with the extracted value and number of
3090 bits extracted. WIDTHP can be NULL. */
3091
3092 static const char *
3093 arm_decode_bitfield (const char *ptr,
3094 unsigned long insn,
3095 unsigned long *valuep,
3096 int *widthp)
3097 {
3098 unsigned long value = 0;
3099 int width = 0;
3100
3101 do
3102 {
3103 int start, end;
3104 int bits;
3105
3106 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3107 start = start * 10 + *ptr - '0';
3108 if (*ptr == '-')
3109 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3110 end = end * 10 + *ptr - '0';
3111 else
3112 end = start;
3113 bits = end - start;
3114 if (bits < 0)
3115 abort ();
3116 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3117 width += bits + 1;
3118 }
3119 while (*ptr++ == ',');
3120 *valuep = value;
3121 if (widthp)
3122 *widthp = width;
3123 return ptr - 1;
3124 }
3125
3126 static void
3127 arm_decode_shift (long given, fprintf_ftype func, void *stream,
3128 bfd_boolean print_shift)
3129 {
3130 func (stream, "%s", arm_regnames[given & 0xf]);
3131
3132 if ((given & 0xff0) != 0)
3133 {
3134 if ((given & 0x10) == 0)
3135 {
3136 int amount = (given & 0xf80) >> 7;
3137 int shift = (given & 0x60) >> 5;
3138
3139 if (amount == 0)
3140 {
3141 if (shift == 3)
3142 {
3143 func (stream, ", rrx");
3144 return;
3145 }
3146
3147 amount = 32;
3148 }
3149
3150 if (print_shift)
3151 func (stream, ", %s #%d", arm_shift[shift], amount);
3152 else
3153 func (stream, ", #%d", amount);
3154 }
3155 else if ((given & 0x80) == 0x80)
3156 func (stream, "\t; <illegal shifter operand>");
3157 else if (print_shift)
3158 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3159 arm_regnames[(given & 0xf00) >> 8]);
3160 else
3161 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
3162 }
3163 }
3164
3165 #define W_BIT 21
3166 #define I_BIT 22
3167 #define U_BIT 23
3168 #define P_BIT 24
3169
3170 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
3171 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
3172 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
3173 #define PRE_BIT_SET (given & (1 << P_BIT))
3174
3175 /* Print one coprocessor instruction on INFO->STREAM.
3176 Return TRUE if the instuction matched, FALSE if this is not a
3177 recognised coprocessor instruction. */
3178
3179 static bfd_boolean
3180 print_insn_coprocessor (bfd_vma pc,
3181 struct disassemble_info *info,
3182 long given,
3183 bfd_boolean thumb)
3184 {
3185 const struct opcode32 *insn;
3186 void *stream = info->stream;
3187 fprintf_ftype func = info->fprintf_func;
3188 unsigned long mask;
3189 unsigned long value = 0;
3190 int cond;
3191 struct arm_private_data *private_data = info->private_data;
3192 arm_feature_set allowed_arches = ARM_ARCH_NONE;
3193
3194 ARM_FEATURE_COPY (allowed_arches, private_data->features);
3195
3196 for (insn = coprocessor_opcodes; insn->assembler; insn++)
3197 {
3198 unsigned long u_reg = 16;
3199 bfd_boolean is_unpredictable = FALSE;
3200 signed long value_in_comment = 0;
3201 const char *c;
3202
3203 if (ARM_FEATURE_ZERO (insn->arch))
3204 switch (insn->value)
3205 {
3206 case SENTINEL_IWMMXT_START:
3207 if (info->mach != bfd_mach_arm_XScale
3208 && info->mach != bfd_mach_arm_iWMMXt
3209 && info->mach != bfd_mach_arm_iWMMXt2)
3210 do
3211 insn++;
3212 while ((! ARM_FEATURE_ZERO (insn->arch))
3213 && insn->value != SENTINEL_IWMMXT_END);
3214 continue;
3215
3216 case SENTINEL_IWMMXT_END:
3217 continue;
3218
3219 case SENTINEL_GENERIC_START:
3220 ARM_FEATURE_COPY (allowed_arches, private_data->features);
3221 continue;
3222
3223 default:
3224 abort ();
3225 }
3226
3227 mask = insn->mask;
3228 value = insn->value;
3229 if (thumb)
3230 {
3231 /* The high 4 bits are 0xe for Arm conditional instructions, and
3232 0xe for arm unconditional instructions. The rest of the
3233 encoding is the same. */
3234 mask |= 0xf0000000;
3235 value |= 0xe0000000;
3236 if (ifthen_state)
3237 cond = IFTHEN_COND;
3238 else
3239 cond = COND_UNCOND;
3240 }
3241 else
3242 {
3243 /* Only match unconditional instuctions against unconditional
3244 patterns. */
3245 if ((given & 0xf0000000) == 0xf0000000)
3246 {
3247 mask |= 0xf0000000;
3248 cond = COND_UNCOND;
3249 }
3250 else
3251 {
3252 cond = (given >> 28) & 0xf;
3253 if (cond == 0xe)
3254 cond = COND_UNCOND;
3255 }
3256 }
3257
3258 if ((given & mask) != value)
3259 continue;
3260
3261 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
3262 continue;
3263
3264 for (c = insn->assembler; *c; c++)
3265 {
3266 if (*c == '%')
3267 {
3268 switch (*++c)
3269 {
3270 case '%':
3271 func (stream, "%%");
3272 break;
3273
3274 case 'A':
3275 {
3276 int rn = (given >> 16) & 0xf;
3277 bfd_vma offset = given & 0xff;
3278
3279 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3280
3281 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
3282 {
3283 /* Not unindexed. The offset is scaled. */
3284 offset = offset * 4;
3285 if (NEGATIVE_BIT_SET)
3286 offset = - offset;
3287 if (rn != 15)
3288 value_in_comment = offset;
3289 }
3290
3291 if (PRE_BIT_SET)
3292 {
3293 if (offset)
3294 func (stream, ", #%d]%s",
3295 (int) offset,
3296 WRITEBACK_BIT_SET ? "!" : "");
3297 else if (NEGATIVE_BIT_SET)
3298 func (stream, ", #-0]");
3299 else
3300 func (stream, "]");
3301 }
3302 else
3303 {
3304 func (stream, "]");
3305
3306 if (WRITEBACK_BIT_SET)
3307 {
3308 if (offset)
3309 func (stream, ", #%d", (int) offset);
3310 else if (NEGATIVE_BIT_SET)
3311 func (stream, ", #-0");
3312 }
3313 else
3314 {
3315 func (stream, ", {%s%d}",
3316 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
3317 (int) offset);
3318 value_in_comment = offset;
3319 }
3320 }
3321 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
3322 {
3323 func (stream, "\t; ");
3324 /* For unaligned PCs, apply off-by-alignment
3325 correction. */
3326 info->print_address_func (offset + pc
3327 + info->bytes_per_chunk * 2
3328 - (pc & 3),
3329 info);
3330 }
3331 }
3332 break;
3333
3334 case 'B':
3335 {
3336 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
3337 int offset = (given >> 1) & 0x3f;
3338
3339 if (offset == 1)
3340 func (stream, "{d%d}", regno);
3341 else if (regno + offset > 32)
3342 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
3343 else
3344 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
3345 }
3346 break;
3347
3348 case 'u':
3349 if (cond != COND_UNCOND)
3350 is_unpredictable = TRUE;
3351
3352 /* Fall through. */
3353 case 'c':
3354 func (stream, "%s", arm_conditional[cond]);
3355 break;
3356
3357 case 'I':
3358 /* Print a Cirrus/DSP shift immediate. */
3359 /* Immediates are 7bit signed ints with bits 0..3 in
3360 bits 0..3 of opcode and bits 4..6 in bits 5..7
3361 of opcode. */
3362 {
3363 int imm;
3364
3365 imm = (given & 0xf) | ((given & 0xe0) >> 1);
3366
3367 /* Is ``imm'' a negative number? */
3368 if (imm & 0x40)
3369 imm -= 0x80;
3370
3371 func (stream, "%d", imm);
3372 }
3373
3374 break;
3375
3376 case 'F':
3377 switch (given & 0x00408000)
3378 {
3379 case 0:
3380 func (stream, "4");
3381 break;
3382 case 0x8000:
3383 func (stream, "1");
3384 break;
3385 case 0x00400000:
3386 func (stream, "2");
3387 break;
3388 default:
3389 func (stream, "3");
3390 }
3391 break;
3392
3393 case 'P':
3394 switch (given & 0x00080080)
3395 {
3396 case 0:
3397 func (stream, "s");
3398 break;
3399 case 0x80:
3400 func (stream, "d");
3401 break;
3402 case 0x00080000:
3403 func (stream, "e");
3404 break;
3405 default:
3406 func (stream, _("<illegal precision>"));
3407 break;
3408 }
3409 break;
3410
3411 case 'Q':
3412 switch (given & 0x00408000)
3413 {
3414 case 0:
3415 func (stream, "s");
3416 break;
3417 case 0x8000:
3418 func (stream, "d");
3419 break;
3420 case 0x00400000:
3421 func (stream, "e");
3422 break;
3423 default:
3424 func (stream, "p");
3425 break;
3426 }
3427 break;
3428
3429 case 'R':
3430 switch (given & 0x60)
3431 {
3432 case 0:
3433 break;
3434 case 0x20:
3435 func (stream, "p");
3436 break;
3437 case 0x40:
3438 func (stream, "m");
3439 break;
3440 default:
3441 func (stream, "z");
3442 break;
3443 }
3444 break;
3445
3446 case '0': case '1': case '2': case '3': case '4':
3447 case '5': case '6': case '7': case '8': case '9':
3448 {
3449 int width;
3450
3451 c = arm_decode_bitfield (c, given, &value, &width);
3452
3453 switch (*c)
3454 {
3455 case 'R':
3456 if (value == 15)
3457 is_unpredictable = TRUE;
3458 /* Fall through. */
3459 case 'r':
3460 if (c[1] == 'u')
3461 {
3462 /* Eat the 'u' character. */
3463 ++ c;
3464
3465 if (u_reg == value)
3466 is_unpredictable = TRUE;
3467 u_reg = value;
3468 }
3469 func (stream, "%s", arm_regnames[value]);
3470 break;
3471 case 'D':
3472 func (stream, "d%ld", value);
3473 break;
3474 case 'Q':
3475 if (value & 1)
3476 func (stream, "<illegal reg q%ld.5>", value >> 1);
3477 else
3478 func (stream, "q%ld", value >> 1);
3479 break;
3480 case 'd':
3481 func (stream, "%ld", value);
3482 value_in_comment = value;
3483 break;
3484 case 'E':
3485 {
3486 /* Converts immediate 8 bit back to float value. */
3487 unsigned floatVal = (value & 0x80) << 24
3488 | (value & 0x3F) << 19
3489 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
3490
3491 /* Quarter float have a maximum value of 31.0.
3492 Get floating point value multiplied by 1e7.
3493 The maximum value stays in limit of a 32-bit int. */
3494 unsigned decVal =
3495 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
3496 (16 + (value & 0xF));
3497
3498 if (!(decVal % 1000000))
3499 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
3500 floatVal, value & 0x80 ? '-' : ' ',
3501 decVal / 10000000,
3502 decVal % 10000000 / 1000000);
3503 else if (!(decVal % 10000))
3504 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
3505 floatVal, value & 0x80 ? '-' : ' ',
3506 decVal / 10000000,
3507 decVal % 10000000 / 10000);
3508 else
3509 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
3510 floatVal, value & 0x80 ? '-' : ' ',
3511 decVal / 10000000, decVal % 10000000);
3512 break;
3513 }
3514 case 'k':
3515 {
3516 int from = (given & (1 << 7)) ? 32 : 16;
3517 func (stream, "%ld", from - value);
3518 }
3519 break;
3520
3521 case 'f':
3522 if (value > 7)
3523 func (stream, "#%s", arm_fp_const[value & 7]);
3524 else
3525 func (stream, "f%ld", value);
3526 break;
3527
3528 case 'w':
3529 if (width == 2)
3530 func (stream, "%s", iwmmxt_wwnames[value]);
3531 else
3532 func (stream, "%s", iwmmxt_wwssnames[value]);
3533 break;
3534
3535 case 'g':
3536 func (stream, "%s", iwmmxt_regnames[value]);
3537 break;
3538 case 'G':
3539 func (stream, "%s", iwmmxt_cregnames[value]);
3540 break;
3541
3542 case 'x':
3543 func (stream, "0x%lx", (value & 0xffffffffUL));
3544 break;
3545
3546 case 'c':
3547 switch (value)
3548 {
3549 case 0:
3550 func (stream, "eq");
3551 break;
3552
3553 case 1:
3554 func (stream, "vs");
3555 break;
3556
3557 case 2:
3558 func (stream, "ge");
3559 break;
3560
3561 case 3:
3562 func (stream, "gt");
3563 break;
3564
3565 default:
3566 func (stream, "??");
3567 break;
3568 }
3569 break;
3570
3571 case '`':
3572 c++;
3573 if (value == 0)
3574 func (stream, "%c", *c);
3575 break;
3576 case '\'':
3577 c++;
3578 if (value == ((1ul << width) - 1))
3579 func (stream, "%c", *c);
3580 break;
3581 case '?':
3582 func (stream, "%c", c[(1 << width) - (int) value]);
3583 c += 1 << width;
3584 break;
3585 default:
3586 abort ();
3587 }
3588 break;
3589
3590 case 'y':
3591 case 'z':
3592 {
3593 int single = *c++ == 'y';
3594 int regno;
3595
3596 switch (*c)
3597 {
3598 case '4': /* Sm pair */
3599 case '0': /* Sm, Dm */
3600 regno = given & 0x0000000f;
3601 if (single)
3602 {
3603 regno <<= 1;
3604 regno += (given >> 5) & 1;
3605 }
3606 else
3607 regno += ((given >> 5) & 1) << 4;
3608 break;
3609
3610 case '1': /* Sd, Dd */
3611 regno = (given >> 12) & 0x0000000f;
3612 if (single)
3613 {
3614 regno <<= 1;
3615 regno += (given >> 22) & 1;
3616 }
3617 else
3618 regno += ((given >> 22) & 1) << 4;
3619 break;
3620
3621 case '2': /* Sn, Dn */
3622 regno = (given >> 16) & 0x0000000f;
3623 if (single)
3624 {
3625 regno <<= 1;
3626 regno += (given >> 7) & 1;
3627 }
3628 else
3629 regno += ((given >> 7) & 1) << 4;
3630 break;
3631
3632 case '3': /* List */
3633 func (stream, "{");
3634 regno = (given >> 12) & 0x0000000f;
3635 if (single)
3636 {
3637 regno <<= 1;
3638 regno += (given >> 22) & 1;
3639 }
3640 else
3641 regno += ((given >> 22) & 1) << 4;
3642 break;
3643
3644 default:
3645 abort ();
3646 }
3647
3648 func (stream, "%c%d", single ? 's' : 'd', regno);
3649
3650 if (*c == '3')
3651 {
3652 int count = given & 0xff;
3653
3654 if (single == 0)
3655 count >>= 1;
3656
3657 if (--count)
3658 {
3659 func (stream, "-%c%d",
3660 single ? 's' : 'd',
3661 regno + count);
3662 }
3663
3664 func (stream, "}");
3665 }
3666 else if (*c == '4')
3667 func (stream, ", %c%d", single ? 's' : 'd',
3668 regno + 1);
3669 }
3670 break;
3671
3672 case 'L':
3673 switch (given & 0x00400100)
3674 {
3675 case 0x00000000: func (stream, "b"); break;
3676 case 0x00400000: func (stream, "h"); break;
3677 case 0x00000100: func (stream, "w"); break;
3678 case 0x00400100: func (stream, "d"); break;
3679 default:
3680 break;
3681 }
3682 break;
3683
3684 case 'Z':
3685 {
3686 /* given (20, 23) | given (0, 3) */
3687 value = ((given >> 16) & 0xf0) | (given & 0xf);
3688 func (stream, "%d", (int) value);
3689 }
3690 break;
3691
3692 case 'l':
3693 /* This is like the 'A' operator, except that if
3694 the width field "M" is zero, then the offset is
3695 *not* multiplied by four. */
3696 {
3697 int offset = given & 0xff;
3698 int multiplier = (given & 0x00000100) ? 4 : 1;
3699
3700 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3701
3702 if (multiplier > 1)
3703 {
3704 value_in_comment = offset * multiplier;
3705 if (NEGATIVE_BIT_SET)
3706 value_in_comment = - value_in_comment;
3707 }
3708
3709 if (offset)
3710 {
3711 if (PRE_BIT_SET)
3712 func (stream, ", #%s%d]%s",
3713 NEGATIVE_BIT_SET ? "-" : "",
3714 offset * multiplier,
3715 WRITEBACK_BIT_SET ? "!" : "");
3716 else
3717 func (stream, "], #%s%d",
3718 NEGATIVE_BIT_SET ? "-" : "",
3719 offset * multiplier);
3720 }
3721 else
3722 func (stream, "]");
3723 }
3724 break;
3725
3726 case 'r':
3727 {
3728 int imm4 = (given >> 4) & 0xf;
3729 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
3730 int ubit = ! NEGATIVE_BIT_SET;
3731 const char *rm = arm_regnames [given & 0xf];
3732 const char *rn = arm_regnames [(given >> 16) & 0xf];
3733
3734 switch (puw_bits)
3735 {
3736 case 1:
3737 case 3:
3738 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
3739 if (imm4)
3740 func (stream, ", lsl #%d", imm4);
3741 break;
3742
3743 case 4:
3744 case 5:
3745 case 6:
3746 case 7:
3747 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
3748 if (imm4 > 0)
3749 func (stream, ", lsl #%d", imm4);
3750 func (stream, "]");
3751 if (puw_bits == 5 || puw_bits == 7)
3752 func (stream, "!");
3753 break;
3754
3755 default:
3756 func (stream, "INVALID");
3757 }
3758 }
3759 break;
3760
3761 case 'i':
3762 {
3763 long imm5;
3764 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
3765 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
3766 }
3767 break;
3768
3769 default:
3770 abort ();
3771 }
3772 }
3773 }
3774 else
3775 func (stream, "%c", *c);
3776 }
3777
3778 if (value_in_comment > 32 || value_in_comment < -16)
3779 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
3780
3781 if (is_unpredictable)
3782 func (stream, UNPREDICTABLE_INSTRUCTION);
3783
3784 return TRUE;
3785 }
3786 return FALSE;
3787 }
3788
3789 /* Decodes and prints ARM addressing modes. Returns the offset
3790 used in the address, if any, if it is worthwhile printing the
3791 offset as a hexadecimal value in a comment at the end of the
3792 line of disassembly. */
3793
3794 static signed long
3795 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
3796 {
3797 void *stream = info->stream;
3798 fprintf_ftype func = info->fprintf_func;
3799 bfd_vma offset = 0;
3800
3801 if (((given & 0x000f0000) == 0x000f0000)
3802 && ((given & 0x02000000) == 0))
3803 {
3804 offset = given & 0xfff;
3805
3806 func (stream, "[pc");
3807
3808 if (PRE_BIT_SET)
3809 {
3810 /* Pre-indexed. Elide offset of positive zero when
3811 non-writeback. */
3812 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
3813 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
3814
3815 if (NEGATIVE_BIT_SET)
3816 offset = -offset;
3817
3818 offset += pc + 8;
3819
3820 /* Cope with the possibility of write-back
3821 being used. Probably a very dangerous thing
3822 for the programmer to do, but who are we to
3823 argue ? */
3824 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
3825 }
3826 else /* Post indexed. */
3827 {
3828 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
3829
3830 /* Ie ignore the offset. */
3831 offset = pc + 8;
3832 }
3833
3834 func (stream, "\t; ");
3835 info->print_address_func (offset, info);
3836 offset = 0;
3837 }
3838 else
3839 {
3840 func (stream, "[%s",
3841 arm_regnames[(given >> 16) & 0xf]);
3842
3843 if (PRE_BIT_SET)
3844 {
3845 if ((given & 0x02000000) == 0)
3846 {
3847 /* Elide offset of positive zero when non-writeback. */
3848 offset = given & 0xfff;
3849 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
3850 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
3851 }
3852 else
3853 {
3854 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
3855 arm_decode_shift (given, func, stream, TRUE);
3856 }
3857
3858 func (stream, "]%s",
3859 WRITEBACK_BIT_SET ? "!" : "");
3860 }
3861 else
3862 {
3863 if ((given & 0x02000000) == 0)
3864 {
3865 /* Always show offset. */
3866 offset = given & 0xfff;
3867 func (stream, "], #%s%d",
3868 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
3869 }
3870 else
3871 {
3872 func (stream, "], %s",
3873 NEGATIVE_BIT_SET ? "-" : "");
3874 arm_decode_shift (given, func, stream, TRUE);
3875 }
3876 }
3877 if (NEGATIVE_BIT_SET)
3878 offset = -offset;
3879 }
3880
3881 return (signed long) offset;
3882 }
3883
3884 /* Print one neon instruction on INFO->STREAM.
3885 Return TRUE if the instuction matched, FALSE if this is not a
3886 recognised neon instruction. */
3887
3888 static bfd_boolean
3889 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
3890 {
3891 const struct opcode32 *insn;
3892 void *stream = info->stream;
3893 fprintf_ftype func = info->fprintf_func;
3894
3895 if (thumb)
3896 {
3897 if ((given & 0xef000000) == 0xef000000)
3898 {
3899 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
3900 unsigned long bit28 = given & (1 << 28);
3901
3902 given &= 0x00ffffff;
3903 if (bit28)
3904 given |= 0xf3000000;
3905 else
3906 given |= 0xf2000000;
3907 }
3908 else if ((given & 0xff000000) == 0xf9000000)
3909 given ^= 0xf9000000 ^ 0xf4000000;
3910 else
3911 return FALSE;
3912 }
3913
3914 for (insn = neon_opcodes; insn->assembler; insn++)
3915 {
3916 if ((given & insn->mask) == insn->value)
3917 {
3918 signed long value_in_comment = 0;
3919 bfd_boolean is_unpredictable = FALSE;
3920 const char *c;
3921
3922 for (c = insn->assembler; *c; c++)
3923 {
3924 if (*c == '%')
3925 {
3926 switch (*++c)
3927 {
3928 case '%':
3929 func (stream, "%%");
3930 break;
3931
3932 case 'u':
3933 if (thumb && ifthen_state)
3934 is_unpredictable = TRUE;
3935
3936 /* Fall through. */
3937 case 'c':
3938 if (thumb && ifthen_state)
3939 func (stream, "%s", arm_conditional[IFTHEN_COND]);
3940 break;
3941
3942 case 'A':
3943 {
3944 static const unsigned char enc[16] =
3945 {
3946 0x4, 0x14, /* st4 0,1 */
3947 0x4, /* st1 2 */
3948 0x4, /* st2 3 */
3949 0x3, /* st3 4 */
3950 0x13, /* st3 5 */
3951 0x3, /* st1 6 */
3952 0x1, /* st1 7 */
3953 0x2, /* st2 8 */
3954 0x12, /* st2 9 */
3955 0x2, /* st1 10 */
3956 0, 0, 0, 0, 0
3957 };
3958 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
3959 int rn = ((given >> 16) & 0xf);
3960 int rm = ((given >> 0) & 0xf);
3961 int align = ((given >> 4) & 0x3);
3962 int type = ((given >> 8) & 0xf);
3963 int n = enc[type] & 0xf;
3964 int stride = (enc[type] >> 4) + 1;
3965 int ix;
3966
3967 func (stream, "{");
3968 if (stride > 1)
3969 for (ix = 0; ix != n; ix++)
3970 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
3971 else if (n == 1)
3972 func (stream, "d%d", rd);
3973 else
3974 func (stream, "d%d-d%d", rd, rd + n - 1);
3975 func (stream, "}, [%s", arm_regnames[rn]);
3976 if (align)
3977 func (stream, " :%d", 32 << align);
3978 func (stream, "]");
3979 if (rm == 0xd)
3980 func (stream, "!");
3981 else if (rm != 0xf)
3982 func (stream, ", %s", arm_regnames[rm]);
3983 }
3984 break;
3985
3986 case 'B':
3987 {
3988 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
3989 int rn = ((given >> 16) & 0xf);
3990 int rm = ((given >> 0) & 0xf);
3991 int idx_align = ((given >> 4) & 0xf);
3992 int align = 0;
3993 int size = ((given >> 10) & 0x3);
3994 int idx = idx_align >> (size + 1);
3995 int length = ((given >> 8) & 3) + 1;
3996 int stride = 1;
3997 int i;
3998
3999 if (length > 1 && size > 0)
4000 stride = (idx_align & (1 << size)) ? 2 : 1;
4001
4002 switch (length)
4003 {
4004 case 1:
4005 {
4006 int amask = (1 << size) - 1;
4007 if ((idx_align & (1 << size)) != 0)
4008 return FALSE;
4009 if (size > 0)
4010 {
4011 if ((idx_align & amask) == amask)
4012 align = 8 << size;
4013 else if ((idx_align & amask) != 0)
4014 return FALSE;
4015 }
4016 }
4017 break;
4018
4019 case 2:
4020 if (size == 2 && (idx_align & 2) != 0)
4021 return FALSE;
4022 align = (idx_align & 1) ? 16 << size : 0;
4023 break;
4024
4025 case 3:
4026 if ((size == 2 && (idx_align & 3) != 0)
4027 || (idx_align & 1) != 0)
4028 return FALSE;
4029 break;
4030
4031 case 4:
4032 if (size == 2)
4033 {
4034 if ((idx_align & 3) == 3)
4035 return FALSE;
4036 align = (idx_align & 3) * 64;
4037 }
4038 else
4039 align = (idx_align & 1) ? 32 << size : 0;
4040 break;
4041
4042 default:
4043 abort ();
4044 }
4045
4046 func (stream, "{");
4047 for (i = 0; i < length; i++)
4048 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
4049 rd + i * stride, idx);
4050 func (stream, "}, [%s", arm_regnames[rn]);
4051 if (align)
4052 func (stream, " :%d", align);
4053 func (stream, "]");
4054 if (rm == 0xd)
4055 func (stream, "!");
4056 else if (rm != 0xf)
4057 func (stream, ", %s", arm_regnames[rm]);
4058 }
4059 break;
4060
4061 case 'C':
4062 {
4063 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4064 int rn = ((given >> 16) & 0xf);
4065 int rm = ((given >> 0) & 0xf);
4066 int align = ((given >> 4) & 0x1);
4067 int size = ((given >> 6) & 0x3);
4068 int type = ((given >> 8) & 0x3);
4069 int n = type + 1;
4070 int stride = ((given >> 5) & 0x1);
4071 int ix;
4072
4073 if (stride && (n == 1))
4074 n++;
4075 else
4076 stride++;
4077
4078 func (stream, "{");
4079 if (stride > 1)
4080 for (ix = 0; ix != n; ix++)
4081 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
4082 else if (n == 1)
4083 func (stream, "d%d[]", rd);
4084 else
4085 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
4086 func (stream, "}, [%s", arm_regnames[rn]);
4087 if (align)
4088 {
4089 align = (8 * (type + 1)) << size;
4090 if (type == 3)
4091 align = (size > 1) ? align >> 1 : align;
4092 if (type == 2 || (type == 0 && !size))
4093 func (stream, " :<bad align %d>", align);
4094 else
4095 func (stream, " :%d", align);
4096 }
4097 func (stream, "]");
4098 if (rm == 0xd)
4099 func (stream, "!");
4100 else if (rm != 0xf)
4101 func (stream, ", %s", arm_regnames[rm]);
4102 }
4103 break;
4104
4105 case 'D':
4106 {
4107 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
4108 int size = (given >> 20) & 3;
4109 int reg = raw_reg & ((4 << size) - 1);
4110 int ix = raw_reg >> size >> 2;
4111
4112 func (stream, "d%d[%d]", reg, ix);
4113 }
4114 break;
4115
4116 case 'E':
4117 /* Neon encoded constant for mov, mvn, vorr, vbic. */
4118 {
4119 int bits = 0;
4120 int cmode = (given >> 8) & 0xf;
4121 int op = (given >> 5) & 0x1;
4122 unsigned long value = 0, hival = 0;
4123 unsigned shift;
4124 int size = 0;
4125 int isfloat = 0;
4126
4127 bits |= ((given >> 24) & 1) << 7;
4128 bits |= ((given >> 16) & 7) << 4;
4129 bits |= ((given >> 0) & 15) << 0;
4130
4131 if (cmode < 8)
4132 {
4133 shift = (cmode >> 1) & 3;
4134 value = (unsigned long) bits << (8 * shift);
4135 size = 32;
4136 }
4137 else if (cmode < 12)
4138 {
4139 shift = (cmode >> 1) & 1;
4140 value = (unsigned long) bits << (8 * shift);
4141 size = 16;
4142 }
4143 else if (cmode < 14)
4144 {
4145 shift = (cmode & 1) + 1;
4146 value = (unsigned long) bits << (8 * shift);
4147 value |= (1ul << (8 * shift)) - 1;
4148 size = 32;
4149 }
4150 else if (cmode == 14)
4151 {
4152 if (op)
4153 {
4154 /* Bit replication into bytes. */
4155 int ix;
4156 unsigned long mask;
4157
4158 value = 0;
4159 hival = 0;
4160 for (ix = 7; ix >= 0; ix--)
4161 {
4162 mask = ((bits >> ix) & 1) ? 0xff : 0;
4163 if (ix <= 3)
4164 value = (value << 8) | mask;
4165 else
4166 hival = (hival << 8) | mask;
4167 }
4168 size = 64;
4169 }
4170 else
4171 {
4172 /* Byte replication. */
4173 value = (unsigned long) bits;
4174 size = 8;
4175 }
4176 }
4177 else if (!op)
4178 {
4179 /* Floating point encoding. */
4180 int tmp;
4181
4182 value = (unsigned long) (bits & 0x7f) << 19;
4183 value |= (unsigned long) (bits & 0x80) << 24;
4184 tmp = bits & 0x40 ? 0x3c : 0x40;
4185 value |= (unsigned long) tmp << 24;
4186 size = 32;
4187 isfloat = 1;
4188 }
4189 else
4190 {
4191 func (stream, "<illegal constant %.8x:%x:%x>",
4192 bits, cmode, op);
4193 size = 32;
4194 break;
4195 }
4196 switch (size)
4197 {
4198 case 8:
4199 func (stream, "#%ld\t; 0x%.2lx", value, value);
4200 break;
4201
4202 case 16:
4203 func (stream, "#%ld\t; 0x%.4lx", value, value);
4204 break;
4205
4206 case 32:
4207 if (isfloat)
4208 {
4209 unsigned char valbytes[4];
4210 double fvalue;
4211
4212 /* Do this a byte at a time so we don't have to
4213 worry about the host's endianness. */
4214 valbytes[0] = value & 0xff;
4215 valbytes[1] = (value >> 8) & 0xff;
4216 valbytes[2] = (value >> 16) & 0xff;
4217 valbytes[3] = (value >> 24) & 0xff;
4218
4219 floatformat_to_double
4220 (& floatformat_ieee_single_little, valbytes,
4221 & fvalue);
4222
4223 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
4224 value);
4225 }
4226 else
4227 func (stream, "#%ld\t; 0x%.8lx",
4228 (long) (((value & 0x80000000L) != 0)
4229 ? value | ~0xffffffffL : value),
4230 value);
4231 break;
4232
4233 case 64:
4234 func (stream, "#0x%.8lx%.8lx", hival, value);
4235 break;
4236
4237 default:
4238 abort ();
4239 }
4240 }
4241 break;
4242
4243 case 'F':
4244 {
4245 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
4246 int num = (given >> 8) & 0x3;
4247
4248 if (!num)
4249 func (stream, "{d%d}", regno);
4250 else if (num + regno >= 32)
4251 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
4252 else
4253 func (stream, "{d%d-d%d}", regno, regno + num);
4254 }
4255 break;
4256
4257
4258 case '0': case '1': case '2': case '3': case '4':
4259 case '5': case '6': case '7': case '8': case '9':
4260 {
4261 int width;
4262 unsigned long value;
4263
4264 c = arm_decode_bitfield (c, given, &value, &width);
4265
4266 switch (*c)
4267 {
4268 case 'r':
4269 func (stream, "%s", arm_regnames[value]);
4270 break;
4271 case 'd':
4272 func (stream, "%ld", value);
4273 value_in_comment = value;
4274 break;
4275 case 'e':
4276 func (stream, "%ld", (1ul << width) - value);
4277 break;
4278
4279 case 'S':
4280 case 'T':
4281 case 'U':
4282 /* Various width encodings. */
4283 {
4284 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
4285 int limit;
4286 unsigned low, high;
4287
4288 c++;
4289 if (*c >= '0' && *c <= '9')
4290 limit = *c - '0';
4291 else if (*c >= 'a' && *c <= 'f')
4292 limit = *c - 'a' + 10;
4293 else
4294 abort ();
4295 low = limit >> 2;
4296 high = limit & 3;
4297
4298 if (value < low || value > high)
4299 func (stream, "<illegal width %d>", base << value);
4300 else
4301 func (stream, "%d", base << value);
4302 }
4303 break;
4304 case 'R':
4305 if (given & (1 << 6))
4306 goto Q;
4307 /* FALLTHROUGH */
4308 case 'D':
4309 func (stream, "d%ld", value);
4310 break;
4311 case 'Q':
4312 Q:
4313 if (value & 1)
4314 func (stream, "<illegal reg q%ld.5>", value >> 1);
4315 else
4316 func (stream, "q%ld", value >> 1);
4317 break;
4318
4319 case '`':
4320 c++;
4321 if (value == 0)
4322 func (stream, "%c", *c);
4323 break;
4324 case '\'':
4325 c++;
4326 if (value == ((1ul << width) - 1))
4327 func (stream, "%c", *c);
4328 break;
4329 case '?':
4330 func (stream, "%c", c[(1 << width) - (int) value]);
4331 c += 1 << width;
4332 break;
4333 default:
4334 abort ();
4335 }
4336 break;
4337
4338 default:
4339 abort ();
4340 }
4341 }
4342 }
4343 else
4344 func (stream, "%c", *c);
4345 }
4346
4347 if (value_in_comment > 32 || value_in_comment < -16)
4348 func (stream, "\t; 0x%lx", value_in_comment);
4349
4350 if (is_unpredictable)
4351 func (stream, UNPREDICTABLE_INSTRUCTION);
4352
4353 return TRUE;
4354 }
4355 }
4356 return FALSE;
4357 }
4358
4359 /* Return the name of a v7A special register. */
4360
4361 static const char *
4362 banked_regname (unsigned reg)
4363 {
4364 switch (reg)
4365 {
4366 case 15: return "CPSR";
4367 case 32: return "R8_usr";
4368 case 33: return "R9_usr";
4369 case 34: return "R10_usr";
4370 case 35: return "R11_usr";
4371 case 36: return "R12_usr";
4372 case 37: return "SP_usr";
4373 case 38: return "LR_usr";
4374 case 40: return "R8_fiq";
4375 case 41: return "R9_fiq";
4376 case 42: return "R10_fiq";
4377 case 43: return "R11_fiq";
4378 case 44: return "R12_fiq";
4379 case 45: return "SP_fiq";
4380 case 46: return "LR_fiq";
4381 case 48: return "LR_irq";
4382 case 49: return "SP_irq";
4383 case 50: return "LR_svc";
4384 case 51: return "SP_svc";
4385 case 52: return "LR_abt";
4386 case 53: return "SP_abt";
4387 case 54: return "LR_und";
4388 case 55: return "SP_und";
4389 case 60: return "LR_mon";
4390 case 61: return "SP_mon";
4391 case 62: return "ELR_hyp";
4392 case 63: return "SP_hyp";
4393 case 79: return "SPSR";
4394 case 110: return "SPSR_fiq";
4395 case 112: return "SPSR_irq";
4396 case 114: return "SPSR_svc";
4397 case 116: return "SPSR_abt";
4398 case 118: return "SPSR_und";
4399 case 124: return "SPSR_mon";
4400 case 126: return "SPSR_hyp";
4401 default: return NULL;
4402 }
4403 }
4404
4405 /* Return the name of the DMB/DSB option. */
4406 static const char *
4407 data_barrier_option (unsigned option)
4408 {
4409 switch (option & 0xf)
4410 {
4411 case 0xf: return "sy";
4412 case 0xe: return "st";
4413 case 0xd: return "ld";
4414 case 0xb: return "ish";
4415 case 0xa: return "ishst";
4416 case 0x9: return "ishld";
4417 case 0x7: return "un";
4418 case 0x6: return "unst";
4419 case 0x5: return "nshld";
4420 case 0x3: return "osh";
4421 case 0x2: return "oshst";
4422 case 0x1: return "oshld";
4423 default: return NULL;
4424 }
4425 }
4426
4427 /* Print one ARM instruction from PC on INFO->STREAM. */
4428
4429 static void
4430 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
4431 {
4432 const struct opcode32 *insn;
4433 void *stream = info->stream;
4434 fprintf_ftype func = info->fprintf_func;
4435 struct arm_private_data *private_data = info->private_data;
4436
4437 if (print_insn_coprocessor (pc, info, given, FALSE))
4438 return;
4439
4440 if (print_insn_neon (info, given, FALSE))
4441 return;
4442
4443 for (insn = arm_opcodes; insn->assembler; insn++)
4444 {
4445 if ((given & insn->mask) != insn->value)
4446 continue;
4447
4448 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
4449 continue;
4450
4451 /* Special case: an instruction with all bits set in the condition field
4452 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
4453 or by the catchall at the end of the table. */
4454 if ((given & 0xF0000000) != 0xF0000000
4455 || (insn->mask & 0xF0000000) == 0xF0000000
4456 || (insn->mask == 0 && insn->value == 0))
4457 {
4458 unsigned long u_reg = 16;
4459 unsigned long U_reg = 16;
4460 bfd_boolean is_unpredictable = FALSE;
4461 signed long value_in_comment = 0;
4462 const char *c;
4463
4464 for (c = insn->assembler; *c; c++)
4465 {
4466 if (*c == '%')
4467 {
4468 bfd_boolean allow_unpredictable = FALSE;
4469
4470 switch (*++c)
4471 {
4472 case '%':
4473 func (stream, "%%");
4474 break;
4475
4476 case 'a':
4477 value_in_comment = print_arm_address (pc, info, given);
4478 break;
4479
4480 case 'P':
4481 /* Set P address bit and use normal address
4482 printing routine. */
4483 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
4484 break;
4485
4486 case 'S':
4487 allow_unpredictable = TRUE;
4488 case 's':
4489 if ((given & 0x004f0000) == 0x004f0000)
4490 {
4491 /* PC relative with immediate offset. */
4492 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
4493
4494 if (PRE_BIT_SET)
4495 {
4496 /* Elide positive zero offset. */
4497 if (offset || NEGATIVE_BIT_SET)
4498 func (stream, "[pc, #%s%d]\t; ",
4499 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4500 else
4501 func (stream, "[pc]\t; ");
4502 if (NEGATIVE_BIT_SET)
4503 offset = -offset;
4504 info->print_address_func (offset + pc + 8, info);
4505 }
4506 else
4507 {
4508 /* Always show the offset. */
4509 func (stream, "[pc], #%s%d",
4510 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4511 if (! allow_unpredictable)
4512 is_unpredictable = TRUE;
4513 }
4514 }
4515 else
4516 {
4517 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
4518
4519 func (stream, "[%s",
4520 arm_regnames[(given >> 16) & 0xf]);
4521
4522 if (PRE_BIT_SET)
4523 {
4524 if (IMMEDIATE_BIT_SET)
4525 {
4526 /* Elide offset for non-writeback
4527 positive zero. */
4528 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
4529 || offset)
4530 func (stream, ", #%s%d",
4531 NEGATIVE_BIT_SET ? "-" : "", offset);
4532
4533 if (NEGATIVE_BIT_SET)
4534 offset = -offset;
4535
4536 value_in_comment = offset;
4537 }
4538 else
4539 {
4540 /* Register Offset or Register Pre-Indexed. */
4541 func (stream, ", %s%s",
4542 NEGATIVE_BIT_SET ? "-" : "",
4543 arm_regnames[given & 0xf]);
4544
4545 /* Writing back to the register that is the source/
4546 destination of the load/store is unpredictable. */
4547 if (! allow_unpredictable
4548 && WRITEBACK_BIT_SET
4549 && ((given & 0xf) == ((given >> 12) & 0xf)))
4550 is_unpredictable = TRUE;
4551 }
4552
4553 func (stream, "]%s",
4554 WRITEBACK_BIT_SET ? "!" : "");
4555 }
4556 else
4557 {
4558 if (IMMEDIATE_BIT_SET)
4559 {
4560 /* Immediate Post-indexed. */
4561 /* PR 10924: Offset must be printed, even if it is zero. */
4562 func (stream, "], #%s%d",
4563 NEGATIVE_BIT_SET ? "-" : "", offset);
4564 if (NEGATIVE_BIT_SET)
4565 offset = -offset;
4566 value_in_comment = offset;
4567 }
4568 else
4569 {
4570 /* Register Post-indexed. */
4571 func (stream, "], %s%s",
4572 NEGATIVE_BIT_SET ? "-" : "",
4573 arm_regnames[given & 0xf]);
4574
4575 /* Writing back to the register that is the source/
4576 destination of the load/store is unpredictable. */
4577 if (! allow_unpredictable
4578 && (given & 0xf) == ((given >> 12) & 0xf))
4579 is_unpredictable = TRUE;
4580 }
4581
4582 if (! allow_unpredictable)
4583 {
4584 /* Writeback is automatically implied by post- addressing.
4585 Setting the W bit is unnecessary and ARM specify it as
4586 being unpredictable. */
4587 if (WRITEBACK_BIT_SET
4588 /* Specifying the PC register as the post-indexed
4589 registers is also unpredictable. */
4590 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
4591 is_unpredictable = TRUE;
4592 }
4593 }
4594 }
4595 break;
4596
4597 case 'b':
4598 {
4599 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
4600 info->print_address_func (disp * 4 + pc + 8, info);
4601 }
4602 break;
4603
4604 case 'c':
4605 if (((given >> 28) & 0xf) != 0xe)
4606 func (stream, "%s",
4607 arm_conditional [(given >> 28) & 0xf]);
4608 break;
4609
4610 case 'm':
4611 {
4612 int started = 0;
4613 int reg;
4614
4615 func (stream, "{");
4616 for (reg = 0; reg < 16; reg++)
4617 if ((given & (1 << reg)) != 0)
4618 {
4619 if (started)
4620 func (stream, ", ");
4621 started = 1;
4622 func (stream, "%s", arm_regnames[reg]);
4623 }
4624 func (stream, "}");
4625 if (! started)
4626 is_unpredictable = TRUE;
4627 }
4628 break;
4629
4630 case 'q':
4631 arm_decode_shift (given, func, stream, FALSE);
4632 break;
4633
4634 case 'o':
4635 if ((given & 0x02000000) != 0)
4636 {
4637 unsigned int rotate = (given & 0xf00) >> 7;
4638 unsigned int immed = (given & 0xff);
4639 unsigned int a, i;
4640
4641 a = (((immed << (32 - rotate))
4642 | (immed >> rotate)) & 0xffffffff);
4643 /* If there is another encoding with smaller rotate,
4644 the rotate should be specified directly. */
4645 for (i = 0; i < 32; i += 2)
4646 if ((a << i | a >> (32 - i)) <= 0xff)
4647 break;
4648
4649 if (i != rotate)
4650 func (stream, "#%d, %d", immed, rotate);
4651 else
4652 func (stream, "#%d", a);
4653 value_in_comment = a;
4654 }
4655 else
4656 arm_decode_shift (given, func, stream, TRUE);
4657 break;
4658
4659 case 'p':
4660 if ((given & 0x0000f000) == 0x0000f000)
4661 {
4662 arm_feature_set arm_ext_v6 =
4663 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
4664
4665 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
4666 mechanism for setting PSR flag bits. They are
4667 obsolete in V6 onwards. */
4668 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
4669 arm_ext_v6))
4670 func (stream, "p");
4671 else
4672 is_unpredictable = TRUE;
4673 }
4674 break;
4675
4676 case 't':
4677 if ((given & 0x01200000) == 0x00200000)
4678 func (stream, "t");
4679 break;
4680
4681 case 'A':
4682 {
4683 int offset = given & 0xff;
4684
4685 value_in_comment = offset * 4;
4686 if (NEGATIVE_BIT_SET)
4687 value_in_comment = - value_in_comment;
4688
4689 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
4690
4691 if (PRE_BIT_SET)
4692 {
4693 if (offset)
4694 func (stream, ", #%d]%s",
4695 (int) value_in_comment,
4696 WRITEBACK_BIT_SET ? "!" : "");
4697 else
4698 func (stream, "]");
4699 }
4700 else
4701 {
4702 func (stream, "]");
4703
4704 if (WRITEBACK_BIT_SET)
4705 {
4706 if (offset)
4707 func (stream, ", #%d", (int) value_in_comment);
4708 }
4709 else
4710 {
4711 func (stream, ", {%d}", (int) offset);
4712 value_in_comment = offset;
4713 }
4714 }
4715 }
4716 break;
4717
4718 case 'B':
4719 /* Print ARM V5 BLX(1) address: pc+25 bits. */
4720 {
4721 bfd_vma address;
4722 bfd_vma offset = 0;
4723
4724 if (! NEGATIVE_BIT_SET)
4725 /* Is signed, hi bits should be ones. */
4726 offset = (-1) ^ 0x00ffffff;
4727
4728 /* Offset is (SignExtend(offset field)<<2). */
4729 offset += given & 0x00ffffff;
4730 offset <<= 2;
4731 address = offset + pc + 8;
4732
4733 if (given & 0x01000000)
4734 /* H bit allows addressing to 2-byte boundaries. */
4735 address += 2;
4736
4737 info->print_address_func (address, info);
4738 }
4739 break;
4740
4741 case 'C':
4742 if ((given & 0x02000200) == 0x200)
4743 {
4744 const char * name;
4745 unsigned sysm = (given & 0x004f0000) >> 16;
4746
4747 sysm |= (given & 0x300) >> 4;
4748 name = banked_regname (sysm);
4749
4750 if (name != NULL)
4751 func (stream, "%s", name);
4752 else
4753 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
4754 }
4755 else
4756 {
4757 func (stream, "%cPSR_",
4758 (given & 0x00400000) ? 'S' : 'C');
4759 if (given & 0x80000)
4760 func (stream, "f");
4761 if (given & 0x40000)
4762 func (stream, "s");
4763 if (given & 0x20000)
4764 func (stream, "x");
4765 if (given & 0x10000)
4766 func (stream, "c");
4767 }
4768 break;
4769
4770 case 'U':
4771 if ((given & 0xf0) == 0x60)
4772 {
4773 switch (given & 0xf)
4774 {
4775 case 0xf: func (stream, "sy"); break;
4776 default:
4777 func (stream, "#%d", (int) given & 0xf);
4778 break;
4779 }
4780 }
4781 else
4782 {
4783 const char * opt = data_barrier_option (given & 0xf);
4784 if (opt != NULL)
4785 func (stream, "%s", opt);
4786 else
4787 func (stream, "#%d", (int) given & 0xf);
4788 }
4789 break;
4790
4791 case '0': case '1': case '2': case '3': case '4':
4792 case '5': case '6': case '7': case '8': case '9':
4793 {
4794 int width;
4795 unsigned long value;
4796
4797 c = arm_decode_bitfield (c, given, &value, &width);
4798
4799 switch (*c)
4800 {
4801 case 'R':
4802 if (value == 15)
4803 is_unpredictable = TRUE;
4804 /* Fall through. */
4805 case 'r':
4806 case 'T':
4807 /* We want register + 1 when decoding T. */
4808 if (*c == 'T')
4809 ++value;
4810
4811 if (c[1] == 'u')
4812 {
4813 /* Eat the 'u' character. */
4814 ++ c;
4815
4816 if (u_reg == value)
4817 is_unpredictable = TRUE;
4818 u_reg = value;
4819 }
4820 if (c[1] == 'U')
4821 {
4822 /* Eat the 'U' character. */
4823 ++ c;
4824
4825 if (U_reg == value)
4826 is_unpredictable = TRUE;
4827 U_reg = value;
4828 }
4829 func (stream, "%s", arm_regnames[value]);
4830 break;
4831 case 'd':
4832 func (stream, "%ld", value);
4833 value_in_comment = value;
4834 break;
4835 case 'b':
4836 func (stream, "%ld", value * 8);
4837 value_in_comment = value * 8;
4838 break;
4839 case 'W':
4840 func (stream, "%ld", value + 1);
4841 value_in_comment = value + 1;
4842 break;
4843 case 'x':
4844 func (stream, "0x%08lx", value);
4845
4846 /* Some SWI instructions have special
4847 meanings. */
4848 if ((given & 0x0fffffff) == 0x0FF00000)
4849 func (stream, "\t; IMB");
4850 else if ((given & 0x0fffffff) == 0x0FF00001)
4851 func (stream, "\t; IMBRange");
4852 break;
4853 case 'X':
4854 func (stream, "%01lx", value & 0xf);
4855 value_in_comment = value;
4856 break;
4857 case '`':
4858 c++;
4859 if (value == 0)
4860 func (stream, "%c", *c);
4861 break;
4862 case '\'':
4863 c++;
4864 if (value == ((1ul << width) - 1))
4865 func (stream, "%c", *c);
4866 break;
4867 case '?':
4868 func (stream, "%c", c[(1 << width) - (int) value]);
4869 c += 1 << width;
4870 break;
4871 default:
4872 abort ();
4873 }
4874 break;
4875
4876 case 'e':
4877 {
4878 int imm;
4879
4880 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
4881 func (stream, "%d", imm);
4882 value_in_comment = imm;
4883 }
4884 break;
4885
4886 case 'E':
4887 /* LSB and WIDTH fields of BFI or BFC. The machine-
4888 language instruction encodes LSB and MSB. */
4889 {
4890 long msb = (given & 0x001f0000) >> 16;
4891 long lsb = (given & 0x00000f80) >> 7;
4892 long w = msb - lsb + 1;
4893
4894 if (w > 0)
4895 func (stream, "#%lu, #%lu", lsb, w);
4896 else
4897 func (stream, "(invalid: %lu:%lu)", lsb, msb);
4898 }
4899 break;
4900
4901 case 'R':
4902 /* Get the PSR/banked register name. */
4903 {
4904 const char * name;
4905 unsigned sysm = (given & 0x004f0000) >> 16;
4906
4907 sysm |= (given & 0x300) >> 4;
4908 name = banked_regname (sysm);
4909
4910 if (name != NULL)
4911 func (stream, "%s", name);
4912 else
4913 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
4914 }
4915 break;
4916
4917 case 'V':
4918 /* 16-bit unsigned immediate from a MOVT or MOVW
4919 instruction, encoded in bits 0:11 and 15:19. */
4920 {
4921 long hi = (given & 0x000f0000) >> 4;
4922 long lo = (given & 0x00000fff);
4923 long imm16 = hi | lo;
4924
4925 func (stream, "#%lu", imm16);
4926 value_in_comment = imm16;
4927 }
4928 break;
4929
4930 default:
4931 abort ();
4932 }
4933 }
4934 }
4935 else
4936 func (stream, "%c", *c);
4937 }
4938
4939 if (value_in_comment > 32 || value_in_comment < -16)
4940 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
4941
4942 if (is_unpredictable)
4943 func (stream, UNPREDICTABLE_INSTRUCTION);
4944
4945 return;
4946 }
4947 }
4948 abort ();
4949 }
4950
4951 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
4952
4953 static void
4954 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
4955 {
4956 const struct opcode16 *insn;
4957 void *stream = info->stream;
4958 fprintf_ftype func = info->fprintf_func;
4959
4960 for (insn = thumb_opcodes; insn->assembler; insn++)
4961 if ((given & insn->mask) == insn->value)
4962 {
4963 signed long value_in_comment = 0;
4964 const char *c = insn->assembler;
4965
4966 for (; *c; c++)
4967 {
4968 int domaskpc = 0;
4969 int domasklr = 0;
4970
4971 if (*c != '%')
4972 {
4973 func (stream, "%c", *c);
4974 continue;
4975 }
4976
4977 switch (*++c)
4978 {
4979 case '%':
4980 func (stream, "%%");
4981 break;
4982
4983 case 'c':
4984 if (ifthen_state)
4985 func (stream, "%s", arm_conditional[IFTHEN_COND]);
4986 break;
4987
4988 case 'C':
4989 if (ifthen_state)
4990 func (stream, "%s", arm_conditional[IFTHEN_COND]);
4991 else
4992 func (stream, "s");
4993 break;
4994
4995 case 'I':
4996 {
4997 unsigned int tmp;
4998
4999 ifthen_next_state = given & 0xff;
5000 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
5001 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
5002 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
5003 }
5004 break;
5005
5006 case 'x':
5007 if (ifthen_next_state)
5008 func (stream, "\t; unpredictable branch in IT block\n");
5009 break;
5010
5011 case 'X':
5012 if (ifthen_state)
5013 func (stream, "\t; unpredictable <IT:%s>",
5014 arm_conditional[IFTHEN_COND]);
5015 break;
5016
5017 case 'S':
5018 {
5019 long reg;
5020
5021 reg = (given >> 3) & 0x7;
5022 if (given & (1 << 6))
5023 reg += 8;
5024
5025 func (stream, "%s", arm_regnames[reg]);
5026 }
5027 break;
5028
5029 case 'D':
5030 {
5031 long reg;
5032
5033 reg = given & 0x7;
5034 if (given & (1 << 7))
5035 reg += 8;
5036
5037 func (stream, "%s", arm_regnames[reg]);
5038 }
5039 break;
5040
5041 case 'N':
5042 if (given & (1 << 8))
5043 domasklr = 1;
5044 /* Fall through. */
5045 case 'O':
5046 if (*c == 'O' && (given & (1 << 8)))
5047 domaskpc = 1;
5048 /* Fall through. */
5049 case 'M':
5050 {
5051 int started = 0;
5052 int reg;
5053
5054 func (stream, "{");
5055
5056 /* It would be nice if we could spot
5057 ranges, and generate the rS-rE format: */
5058 for (reg = 0; (reg < 8); reg++)
5059 if ((given & (1 << reg)) != 0)
5060 {
5061 if (started)
5062 func (stream, ", ");
5063 started = 1;
5064 func (stream, "%s", arm_regnames[reg]);
5065 }
5066
5067 if (domasklr)
5068 {
5069 if (started)
5070 func (stream, ", ");
5071 started = 1;
5072 func (stream, "%s", arm_regnames[14] /* "lr" */);
5073 }
5074
5075 if (domaskpc)
5076 {
5077 if (started)
5078 func (stream, ", ");
5079 func (stream, "%s", arm_regnames[15] /* "pc" */);
5080 }
5081
5082 func (stream, "}");
5083 }
5084 break;
5085
5086 case 'W':
5087 /* Print writeback indicator for a LDMIA. We are doing a
5088 writeback if the base register is not in the register
5089 mask. */
5090 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
5091 func (stream, "!");
5092 break;
5093
5094 case 'b':
5095 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
5096 {
5097 bfd_vma address = (pc + 4
5098 + ((given & 0x00f8) >> 2)
5099 + ((given & 0x0200) >> 3));
5100 info->print_address_func (address, info);
5101 }
5102 break;
5103
5104 case 's':
5105 /* Right shift immediate -- bits 6..10; 1-31 print
5106 as themselves, 0 prints as 32. */
5107 {
5108 long imm = (given & 0x07c0) >> 6;
5109 if (imm == 0)
5110 imm = 32;
5111 func (stream, "#%ld", imm);
5112 }
5113 break;
5114
5115 case '0': case '1': case '2': case '3': case '4':
5116 case '5': case '6': case '7': case '8': case '9':
5117 {
5118 int bitstart = *c++ - '0';
5119 int bitend = 0;
5120
5121 while (*c >= '0' && *c <= '9')
5122 bitstart = (bitstart * 10) + *c++ - '0';
5123
5124 switch (*c)
5125 {
5126 case '-':
5127 {
5128 bfd_vma reg;
5129
5130 c++;
5131 while (*c >= '0' && *c <= '9')
5132 bitend = (bitend * 10) + *c++ - '0';
5133 if (!bitend)
5134 abort ();
5135 reg = given >> bitstart;
5136 reg &= (2 << (bitend - bitstart)) - 1;
5137
5138 switch (*c)
5139 {
5140 case 'r':
5141 func (stream, "%s", arm_regnames[reg]);
5142 break;
5143
5144 case 'd':
5145 func (stream, "%ld", (long) reg);
5146 value_in_comment = reg;
5147 break;
5148
5149 case 'H':
5150 func (stream, "%ld", (long) (reg << 1));
5151 value_in_comment = reg << 1;
5152 break;
5153
5154 case 'W':
5155 func (stream, "%ld", (long) (reg << 2));
5156 value_in_comment = reg << 2;
5157 break;
5158
5159 case 'a':
5160 /* PC-relative address -- the bottom two
5161 bits of the address are dropped
5162 before the calculation. */
5163 info->print_address_func
5164 (((pc + 4) & ~3) + (reg << 2), info);
5165 value_in_comment = 0;
5166 break;
5167
5168 case 'x':
5169 func (stream, "0x%04lx", (long) reg);
5170 break;
5171
5172 case 'B':
5173 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
5174 info->print_address_func (reg * 2 + pc + 4, info);
5175 value_in_comment = 0;
5176 break;
5177
5178 case 'c':
5179 func (stream, "%s", arm_conditional [reg]);
5180 break;
5181
5182 default:
5183 abort ();
5184 }
5185 }
5186 break;
5187
5188 case '\'':
5189 c++;
5190 if ((given & (1 << bitstart)) != 0)
5191 func (stream, "%c", *c);
5192 break;
5193
5194 case '?':
5195 ++c;
5196 if ((given & (1 << bitstart)) != 0)
5197 func (stream, "%c", *c++);
5198 else
5199 func (stream, "%c", *++c);
5200 break;
5201
5202 default:
5203 abort ();
5204 }
5205 }
5206 break;
5207
5208 default:
5209 abort ();
5210 }
5211 }
5212
5213 if (value_in_comment > 32 || value_in_comment < -16)
5214 func (stream, "\t; 0x%lx", value_in_comment);
5215 return;
5216 }
5217
5218 /* No match. */
5219 abort ();
5220 }
5221
5222 /* Return the name of an V7M special register. */
5223
5224 static const char *
5225 psr_name (int regno)
5226 {
5227 switch (regno)
5228 {
5229 case 0: return "APSR";
5230 case 1: return "IAPSR";
5231 case 2: return "EAPSR";
5232 case 3: return "PSR";
5233 case 5: return "IPSR";
5234 case 6: return "EPSR";
5235 case 7: return "IEPSR";
5236 case 8: return "MSP";
5237 case 9: return "PSP";
5238 case 16: return "PRIMASK";
5239 case 17: return "BASEPRI";
5240 case 18: return "BASEPRI_MAX";
5241 case 19: return "FAULTMASK";
5242 case 20: return "CONTROL";
5243 default: return "<unknown>";
5244 }
5245 }
5246
5247 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
5248
5249 static void
5250 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
5251 {
5252 const struct opcode32 *insn;
5253 void *stream = info->stream;
5254 fprintf_ftype func = info->fprintf_func;
5255
5256 if (print_insn_coprocessor (pc, info, given, TRUE))
5257 return;
5258
5259 if (print_insn_neon (info, given, TRUE))
5260 return;
5261
5262 for (insn = thumb32_opcodes; insn->assembler; insn++)
5263 if ((given & insn->mask) == insn->value)
5264 {
5265 bfd_boolean is_unpredictable = FALSE;
5266 signed long value_in_comment = 0;
5267 const char *c = insn->assembler;
5268
5269 for (; *c; c++)
5270 {
5271 if (*c != '%')
5272 {
5273 func (stream, "%c", *c);
5274 continue;
5275 }
5276
5277 switch (*++c)
5278 {
5279 case '%':
5280 func (stream, "%%");
5281 break;
5282
5283 case 'c':
5284 if (ifthen_state)
5285 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5286 break;
5287
5288 case 'x':
5289 if (ifthen_next_state)
5290 func (stream, "\t; unpredictable branch in IT block\n");
5291 break;
5292
5293 case 'X':
5294 if (ifthen_state)
5295 func (stream, "\t; unpredictable <IT:%s>",
5296 arm_conditional[IFTHEN_COND]);
5297 break;
5298
5299 case 'I':
5300 {
5301 unsigned int imm12 = 0;
5302
5303 imm12 |= (given & 0x000000ffu);
5304 imm12 |= (given & 0x00007000u) >> 4;
5305 imm12 |= (given & 0x04000000u) >> 15;
5306 func (stream, "#%u", imm12);
5307 value_in_comment = imm12;
5308 }
5309 break;
5310
5311 case 'M':
5312 {
5313 unsigned int bits = 0, imm, imm8, mod;
5314
5315 bits |= (given & 0x000000ffu);
5316 bits |= (given & 0x00007000u) >> 4;
5317 bits |= (given & 0x04000000u) >> 15;
5318 imm8 = (bits & 0x0ff);
5319 mod = (bits & 0xf00) >> 8;
5320 switch (mod)
5321 {
5322 case 0: imm = imm8; break;
5323 case 1: imm = ((imm8 << 16) | imm8); break;
5324 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
5325 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
5326 default:
5327 mod = (bits & 0xf80) >> 7;
5328 imm8 = (bits & 0x07f) | 0x80;
5329 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
5330 }
5331 func (stream, "#%u", imm);
5332 value_in_comment = imm;
5333 }
5334 break;
5335
5336 case 'J':
5337 {
5338 unsigned int imm = 0;
5339
5340 imm |= (given & 0x000000ffu);
5341 imm |= (given & 0x00007000u) >> 4;
5342 imm |= (given & 0x04000000u) >> 15;
5343 imm |= (given & 0x000f0000u) >> 4;
5344 func (stream, "#%u", imm);
5345 value_in_comment = imm;
5346 }
5347 break;
5348
5349 case 'K':
5350 {
5351 unsigned int imm = 0;
5352
5353 imm |= (given & 0x000f0000u) >> 16;
5354 imm |= (given & 0x00000ff0u) >> 0;
5355 imm |= (given & 0x0000000fu) << 12;
5356 func (stream, "#%u", imm);
5357 value_in_comment = imm;
5358 }
5359 break;
5360
5361 case 'H':
5362 {
5363 unsigned int imm = 0;
5364
5365 imm |= (given & 0x000f0000u) >> 4;
5366 imm |= (given & 0x00000fffu) >> 0;
5367 func (stream, "#%u", imm);
5368 value_in_comment = imm;
5369 }
5370 break;
5371
5372 case 'V':
5373 {
5374 unsigned int imm = 0;
5375
5376 imm |= (given & 0x00000fffu);
5377 imm |= (given & 0x000f0000u) >> 4;
5378 func (stream, "#%u", imm);
5379 value_in_comment = imm;
5380 }
5381 break;
5382
5383 case 'S':
5384 {
5385 unsigned int reg = (given & 0x0000000fu);
5386 unsigned int stp = (given & 0x00000030u) >> 4;
5387 unsigned int imm = 0;
5388 imm |= (given & 0x000000c0u) >> 6;
5389 imm |= (given & 0x00007000u) >> 10;
5390
5391 func (stream, "%s", arm_regnames[reg]);
5392 switch (stp)
5393 {
5394 case 0:
5395 if (imm > 0)
5396 func (stream, ", lsl #%u", imm);
5397 break;
5398
5399 case 1:
5400 if (imm == 0)
5401 imm = 32;
5402 func (stream, ", lsr #%u", imm);
5403 break;
5404
5405 case 2:
5406 if (imm == 0)
5407 imm = 32;
5408 func (stream, ", asr #%u", imm);
5409 break;
5410
5411 case 3:
5412 if (imm == 0)
5413 func (stream, ", rrx");
5414 else
5415 func (stream, ", ror #%u", imm);
5416 }
5417 }
5418 break;
5419
5420 case 'a':
5421 {
5422 unsigned int Rn = (given & 0x000f0000) >> 16;
5423 unsigned int U = ! NEGATIVE_BIT_SET;
5424 unsigned int op = (given & 0x00000f00) >> 8;
5425 unsigned int i12 = (given & 0x00000fff);
5426 unsigned int i8 = (given & 0x000000ff);
5427 bfd_boolean writeback = FALSE, postind = FALSE;
5428 bfd_vma offset = 0;
5429
5430 func (stream, "[%s", arm_regnames[Rn]);
5431 if (U) /* 12-bit positive immediate offset. */
5432 {
5433 offset = i12;
5434 if (Rn != 15)
5435 value_in_comment = offset;
5436 }
5437 else if (Rn == 15) /* 12-bit negative immediate offset. */
5438 offset = - (int) i12;
5439 else if (op == 0x0) /* Shifted register offset. */
5440 {
5441 unsigned int Rm = (i8 & 0x0f);
5442 unsigned int sh = (i8 & 0x30) >> 4;
5443
5444 func (stream, ", %s", arm_regnames[Rm]);
5445 if (sh)
5446 func (stream, ", lsl #%u", sh);
5447 func (stream, "]");
5448 break;
5449 }
5450 else switch (op)
5451 {
5452 case 0xE: /* 8-bit positive immediate offset. */
5453 offset = i8;
5454 break;
5455
5456 case 0xC: /* 8-bit negative immediate offset. */
5457 offset = -i8;
5458 break;
5459
5460 case 0xF: /* 8-bit + preindex with wb. */
5461 offset = i8;
5462 writeback = TRUE;
5463 break;
5464
5465 case 0xD: /* 8-bit - preindex with wb. */
5466 offset = -i8;
5467 writeback = TRUE;
5468 break;
5469
5470 case 0xB: /* 8-bit + postindex. */
5471 offset = i8;
5472 postind = TRUE;
5473 break;
5474
5475 case 0x9: /* 8-bit - postindex. */
5476 offset = -i8;
5477 postind = TRUE;
5478 break;
5479
5480 default:
5481 func (stream, ", <undefined>]");
5482 goto skip;
5483 }
5484
5485 if (postind)
5486 func (stream, "], #%d", (int) offset);
5487 else
5488 {
5489 if (offset)
5490 func (stream, ", #%d", (int) offset);
5491 func (stream, writeback ? "]!" : "]");
5492 }
5493
5494 if (Rn == 15)
5495 {
5496 func (stream, "\t; ");
5497 info->print_address_func (((pc + 4) & ~3) + offset, info);
5498 }
5499 }
5500 skip:
5501 break;
5502
5503 case 'A':
5504 {
5505 unsigned int U = ! NEGATIVE_BIT_SET;
5506 unsigned int W = WRITEBACK_BIT_SET;
5507 unsigned int Rn = (given & 0x000f0000) >> 16;
5508 unsigned int off = (given & 0x000000ff);
5509
5510 func (stream, "[%s", arm_regnames[Rn]);
5511
5512 if (PRE_BIT_SET)
5513 {
5514 if (off || !U)
5515 {
5516 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
5517 value_in_comment = off * 4 * U ? 1 : -1;
5518 }
5519 func (stream, "]");
5520 if (W)
5521 func (stream, "!");
5522 }
5523 else
5524 {
5525 func (stream, "], ");
5526 if (W)
5527 {
5528 func (stream, "#%c%u", U ? '+' : '-', off * 4);
5529 value_in_comment = off * 4 * U ? 1 : -1;
5530 }
5531 else
5532 {
5533 func (stream, "{%u}", off);
5534 value_in_comment = off;
5535 }
5536 }
5537 }
5538 break;
5539
5540 case 'w':
5541 {
5542 unsigned int Sbit = (given & 0x01000000) >> 24;
5543 unsigned int type = (given & 0x00600000) >> 21;
5544
5545 switch (type)
5546 {
5547 case 0: func (stream, Sbit ? "sb" : "b"); break;
5548 case 1: func (stream, Sbit ? "sh" : "h"); break;
5549 case 2:
5550 if (Sbit)
5551 func (stream, "??");
5552 break;
5553 case 3:
5554 func (stream, "??");
5555 break;
5556 }
5557 }
5558 break;
5559
5560 case 'm':
5561 {
5562 int started = 0;
5563 int reg;
5564
5565 func (stream, "{");
5566 for (reg = 0; reg < 16; reg++)
5567 if ((given & (1 << reg)) != 0)
5568 {
5569 if (started)
5570 func (stream, ", ");
5571 started = 1;
5572 func (stream, "%s", arm_regnames[reg]);
5573 }
5574 func (stream, "}");
5575 }
5576 break;
5577
5578 case 'E':
5579 {
5580 unsigned int msb = (given & 0x0000001f);
5581 unsigned int lsb = 0;
5582
5583 lsb |= (given & 0x000000c0u) >> 6;
5584 lsb |= (given & 0x00007000u) >> 10;
5585 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
5586 }
5587 break;
5588
5589 case 'F':
5590 {
5591 unsigned int width = (given & 0x0000001f) + 1;
5592 unsigned int lsb = 0;
5593
5594 lsb |= (given & 0x000000c0u) >> 6;
5595 lsb |= (given & 0x00007000u) >> 10;
5596 func (stream, "#%u, #%u", lsb, width);
5597 }
5598 break;
5599
5600 case 'b':
5601 {
5602 unsigned int S = (given & 0x04000000u) >> 26;
5603 unsigned int J1 = (given & 0x00002000u) >> 13;
5604 unsigned int J2 = (given & 0x00000800u) >> 11;
5605 bfd_vma offset = 0;
5606
5607 offset |= !S << 20;
5608 offset |= J2 << 19;
5609 offset |= J1 << 18;
5610 offset |= (given & 0x003f0000) >> 4;
5611 offset |= (given & 0x000007ff) << 1;
5612 offset -= (1 << 20);
5613
5614 info->print_address_func (pc + 4 + offset, info);
5615 }
5616 break;
5617
5618 case 'B':
5619 {
5620 unsigned int S = (given & 0x04000000u) >> 26;
5621 unsigned int I1 = (given & 0x00002000u) >> 13;
5622 unsigned int I2 = (given & 0x00000800u) >> 11;
5623 bfd_vma offset = 0;
5624
5625 offset |= !S << 24;
5626 offset |= !(I1 ^ S) << 23;
5627 offset |= !(I2 ^ S) << 22;
5628 offset |= (given & 0x03ff0000u) >> 4;
5629 offset |= (given & 0x000007ffu) << 1;
5630 offset -= (1 << 24);
5631 offset += pc + 4;
5632
5633 /* BLX target addresses are always word aligned. */
5634 if ((given & 0x00001000u) == 0)
5635 offset &= ~2u;
5636
5637 info->print_address_func (offset, info);
5638 }
5639 break;
5640
5641 case 's':
5642 {
5643 unsigned int shift = 0;
5644
5645 shift |= (given & 0x000000c0u) >> 6;
5646 shift |= (given & 0x00007000u) >> 10;
5647 if (WRITEBACK_BIT_SET)
5648 func (stream, ", asr #%u", shift);
5649 else if (shift)
5650 func (stream, ", lsl #%u", shift);
5651 /* else print nothing - lsl #0 */
5652 }
5653 break;
5654
5655 case 'R':
5656 {
5657 unsigned int rot = (given & 0x00000030) >> 4;
5658
5659 if (rot)
5660 func (stream, ", ror #%u", rot * 8);
5661 }
5662 break;
5663
5664 case 'U':
5665 if ((given & 0xf0) == 0x60)
5666 {
5667 switch (given & 0xf)
5668 {
5669 case 0xf: func (stream, "sy"); break;
5670 default:
5671 func (stream, "#%d", (int) given & 0xf);
5672 break;
5673 }
5674 }
5675 else
5676 {
5677 const char * opt = data_barrier_option (given & 0xf);
5678 if (opt != NULL)
5679 func (stream, "%s", opt);
5680 else
5681 func (stream, "#%d", (int) given & 0xf);
5682 }
5683 break;
5684
5685 case 'C':
5686 if ((given & 0xff) == 0)
5687 {
5688 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
5689 if (given & 0x800)
5690 func (stream, "f");
5691 if (given & 0x400)
5692 func (stream, "s");
5693 if (given & 0x200)
5694 func (stream, "x");
5695 if (given & 0x100)
5696 func (stream, "c");
5697 }
5698 else if ((given & 0x20) == 0x20)
5699 {
5700 char const* name;
5701 unsigned sysm = (given & 0xf00) >> 8;
5702
5703 sysm |= (given & 0x30);
5704 sysm |= (given & 0x00100000) >> 14;
5705 name = banked_regname (sysm);
5706
5707 if (name != NULL)
5708 func (stream, "%s", name);
5709 else
5710 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
5711 }
5712 else
5713 {
5714 func (stream, "%s", psr_name (given & 0xff));
5715 }
5716 break;
5717
5718 case 'D':
5719 if (((given & 0xff) == 0)
5720 || ((given & 0x20) == 0x20))
5721 {
5722 char const* name;
5723 unsigned sm = (given & 0xf0000) >> 16;
5724
5725 sm |= (given & 0x30);
5726 sm |= (given & 0x00100000) >> 14;
5727 name = banked_regname (sm);
5728
5729 if (name != NULL)
5730 func (stream, "%s", name);
5731 else
5732 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
5733 }
5734 else
5735 func (stream, "%s", psr_name (given & 0xff));
5736 break;
5737
5738 case '0': case '1': case '2': case '3': case '4':
5739 case '5': case '6': case '7': case '8': case '9':
5740 {
5741 int width;
5742 unsigned long val;
5743
5744 c = arm_decode_bitfield (c, given, &val, &width);
5745
5746 switch (*c)
5747 {
5748 case 'd':
5749 func (stream, "%lu", val);
5750 value_in_comment = val;
5751 break;
5752
5753 case 'D':
5754 func (stream, "%lu", val + 1);
5755 value_in_comment = val + 1;
5756 break;
5757
5758 case 'W':
5759 func (stream, "%lu", val * 4);
5760 value_in_comment = val * 4;
5761 break;
5762
5763 case 'S':
5764 if (val == 13)
5765 is_unpredictable = TRUE;
5766 /* Fall through. */
5767 case 'R':
5768 if (val == 15)
5769 is_unpredictable = TRUE;
5770 /* Fall through. */
5771 case 'r':
5772 func (stream, "%s", arm_regnames[val]);
5773 break;
5774
5775 case 'c':
5776 func (stream, "%s", arm_conditional[val]);
5777 break;
5778
5779 case '\'':
5780 c++;
5781 if (val == ((1ul << width) - 1))
5782 func (stream, "%c", *c);
5783 break;
5784
5785 case '`':
5786 c++;
5787 if (val == 0)
5788 func (stream, "%c", *c);
5789 break;
5790
5791 case '?':
5792 func (stream, "%c", c[(1 << width) - (int) val]);
5793 c += 1 << width;
5794 break;
5795
5796 case 'x':
5797 func (stream, "0x%lx", val & 0xffffffffUL);
5798 break;
5799
5800 default:
5801 abort ();
5802 }
5803 }
5804 break;
5805
5806 case 'L':
5807 /* PR binutils/12534
5808 If we have a PC relative offset in an LDRD or STRD
5809 instructions then display the decoded address. */
5810 if (((given >> 16) & 0xf) == 0xf)
5811 {
5812 bfd_vma offset = (given & 0xff) * 4;
5813
5814 if ((given & (1 << 23)) == 0)
5815 offset = - offset;
5816 func (stream, "\t; ");
5817 info->print_address_func ((pc & ~3) + 4 + offset, info);
5818 }
5819 break;
5820
5821 default:
5822 abort ();
5823 }
5824 }
5825
5826 if (value_in_comment > 32 || value_in_comment < -16)
5827 func (stream, "\t; 0x%lx", value_in_comment);
5828
5829 if (is_unpredictable)
5830 func (stream, UNPREDICTABLE_INSTRUCTION);
5831
5832 return;
5833 }
5834
5835 /* No match. */
5836 abort ();
5837 }
5838
5839 /* Print data bytes on INFO->STREAM. */
5840
5841 static void
5842 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
5843 struct disassemble_info *info,
5844 long given)
5845 {
5846 switch (info->bytes_per_chunk)
5847 {
5848 case 1:
5849 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
5850 break;
5851 case 2:
5852 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
5853 break;
5854 case 4:
5855 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
5856 break;
5857 default:
5858 abort ();
5859 }
5860 }
5861
5862 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
5863 being displayed in symbol relative addresses.
5864
5865 Also disallow private symbol, with __tagsym$$ prefix,
5866 from ARM RVCT toolchain being displayed. */
5867
5868 bfd_boolean
5869 arm_symbol_is_valid (asymbol * sym,
5870 struct disassemble_info * info ATTRIBUTE_UNUSED)
5871 {
5872 const char * name;
5873
5874 if (sym == NULL)
5875 return FALSE;
5876
5877 name = bfd_asymbol_name (sym);
5878
5879 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
5880 }
5881
5882 /* Parse an individual disassembler option. */
5883
5884 void
5885 parse_arm_disassembler_option (char *option)
5886 {
5887 if (option == NULL)
5888 return;
5889
5890 if (CONST_STRNEQ (option, "reg-names-"))
5891 {
5892 int i;
5893
5894 option += 10;
5895
5896 for (i = NUM_ARM_REGNAMES; i--;)
5897 if (strneq (option, regnames[i].name, strlen (regnames[i].name)))
5898 {
5899 regname_selected = i;
5900 break;
5901 }
5902
5903 if (i < 0)
5904 /* XXX - should break 'option' at following delimiter. */
5905 fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
5906 }
5907 else if (CONST_STRNEQ (option, "force-thumb"))
5908 force_thumb = 1;
5909 else if (CONST_STRNEQ (option, "no-force-thumb"))
5910 force_thumb = 0;
5911 else
5912 /* XXX - should break 'option' at following delimiter. */
5913 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
5914
5915 return;
5916 }
5917
5918 /* Parse the string of disassembler options, spliting it at whitespaces
5919 or commas. (Whitespace separators supported for backwards compatibility). */
5920
5921 static void
5922 parse_disassembler_options (char *options)
5923 {
5924 if (options == NULL)
5925 return;
5926
5927 while (*options)
5928 {
5929 parse_arm_disassembler_option (options);
5930
5931 /* Skip forward to next seperator. */
5932 while ((*options) && (! ISSPACE (*options)) && (*options != ','))
5933 ++ options;
5934 /* Skip forward past seperators. */
5935 while (ISSPACE (*options) || (*options == ','))
5936 ++ options;
5937 }
5938 }
5939
5940 /* Search back through the insn stream to determine if this instruction is
5941 conditionally executed. */
5942
5943 static void
5944 find_ifthen_state (bfd_vma pc,
5945 struct disassemble_info *info,
5946 bfd_boolean little)
5947 {
5948 unsigned char b[2];
5949 unsigned int insn;
5950 int status;
5951 /* COUNT is twice the number of instructions seen. It will be odd if we
5952 just crossed an instruction boundary. */
5953 int count;
5954 int it_count;
5955 unsigned int seen_it;
5956 bfd_vma addr;
5957
5958 ifthen_address = pc;
5959 ifthen_state = 0;
5960
5961 addr = pc;
5962 count = 1;
5963 it_count = 0;
5964 seen_it = 0;
5965 /* Scan backwards looking for IT instructions, keeping track of where
5966 instruction boundaries are. We don't know if something is actually an
5967 IT instruction until we find a definite instruction boundary. */
5968 for (;;)
5969 {
5970 if (addr == 0 || info->symbol_at_address_func (addr, info))
5971 {
5972 /* A symbol must be on an instruction boundary, and will not
5973 be within an IT block. */
5974 if (seen_it && (count & 1))
5975 break;
5976
5977 return;
5978 }
5979 addr -= 2;
5980 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
5981 if (status)
5982 return;
5983
5984 if (little)
5985 insn = (b[0]) | (b[1] << 8);
5986 else
5987 insn = (b[1]) | (b[0] << 8);
5988 if (seen_it)
5989 {
5990 if ((insn & 0xf800) < 0xe800)
5991 {
5992 /* Addr + 2 is an instruction boundary. See if this matches
5993 the expected boundary based on the position of the last
5994 IT candidate. */
5995 if (count & 1)
5996 break;
5997 seen_it = 0;
5998 }
5999 }
6000 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
6001 {
6002 /* This could be an IT instruction. */
6003 seen_it = insn;
6004 it_count = count >> 1;
6005 }
6006 if ((insn & 0xf800) >= 0xe800)
6007 count++;
6008 else
6009 count = (count + 2) | 1;
6010 /* IT blocks contain at most 4 instructions. */
6011 if (count >= 8 && !seen_it)
6012 return;
6013 }
6014 /* We found an IT instruction. */
6015 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
6016 if ((ifthen_state & 0xf) == 0)
6017 ifthen_state = 0;
6018 }
6019
6020 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
6021 mapping symbol. */
6022
6023 static int
6024 is_mapping_symbol (struct disassemble_info *info, int n,
6025 enum map_type *map_type)
6026 {
6027 const char *name;
6028
6029 name = bfd_asymbol_name (info->symtab[n]);
6030 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
6031 && (name[2] == 0 || name[2] == '.'))
6032 {
6033 *map_type = ((name[1] == 'a') ? MAP_ARM
6034 : (name[1] == 't') ? MAP_THUMB
6035 : MAP_DATA);
6036 return TRUE;
6037 }
6038
6039 return FALSE;
6040 }
6041
6042 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
6043 Returns nonzero if *MAP_TYPE was set. */
6044
6045 static int
6046 get_map_sym_type (struct disassemble_info *info,
6047 int n,
6048 enum map_type *map_type)
6049 {
6050 /* If the symbol is in a different section, ignore it. */
6051 if (info->section != NULL && info->section != info->symtab[n]->section)
6052 return FALSE;
6053
6054 return is_mapping_symbol (info, n, map_type);
6055 }
6056
6057 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
6058 Returns nonzero if *MAP_TYPE was set. */
6059
6060 static int
6061 get_sym_code_type (struct disassemble_info *info,
6062 int n,
6063 enum map_type *map_type)
6064 {
6065 elf_symbol_type *es;
6066 unsigned int type;
6067
6068 /* If the symbol is in a different section, ignore it. */
6069 if (info->section != NULL && info->section != info->symtab[n]->section)
6070 return FALSE;
6071
6072 es = *(elf_symbol_type **)(info->symtab + n);
6073 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6074
6075 /* If the symbol has function type then use that. */
6076 if (type == STT_FUNC || type == STT_GNU_IFUNC)
6077 {
6078 if (ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym) == ST_BRANCH_TO_THUMB)
6079 *map_type = MAP_THUMB;
6080 else
6081 *map_type = MAP_ARM;
6082 return TRUE;
6083 }
6084
6085 return FALSE;
6086 }
6087
6088 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
6089 of the supplied arm_feature_set structure with bitmasks indicating
6090 the support base architectures and coprocessor extensions.
6091
6092 FIXME: This could more efficiently implemented as a constant array,
6093 although it would also be less robust. */
6094
6095 static void
6096 select_arm_features (unsigned long mach,
6097 arm_feature_set * features)
6098 {
6099 #undef ARM_SET_FEATURES
6100 #define ARM_SET_FEATURES(FSET) \
6101 { \
6102 const arm_feature_set fset = FSET; \
6103 arm_feature_set tmp = ARM_FEATURE (0, 0, FPU_FPA) ; \
6104 ARM_MERGE_FEATURE_SETS (*features, tmp, fset); \
6105 }
6106
6107 switch (mach)
6108 {
6109 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
6110 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
6111 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
6112 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
6113 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
6114 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
6115 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
6116 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
6117 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
6118 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
6119 case bfd_mach_arm_ep9312:
6120 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
6121 ARM_CEXT_MAVERICK | FPU_MAVERICK));
6122 break;
6123 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
6124 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
6125 /* If the machine type is unknown allow all
6126 architecture types and all extensions. */
6127 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
6128 default:
6129 abort ();
6130 }
6131
6132 #undef ARM_SET_FEATURES
6133 }
6134
6135
6136 /* NOTE: There are no checks in these routines that
6137 the relevant number of data bytes exist. */
6138
6139 static int
6140 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
6141 {
6142 unsigned char b[4];
6143 long given;
6144 int status;
6145 int is_thumb = FALSE;
6146 int is_data = FALSE;
6147 int little_code;
6148 unsigned int size = 4;
6149 void (*printer) (bfd_vma, struct disassemble_info *, long);
6150 bfd_boolean found = FALSE;
6151 struct arm_private_data *private_data;
6152
6153 if (info->disassembler_options)
6154 {
6155 parse_disassembler_options (info->disassembler_options);
6156
6157 /* To avoid repeated parsing of these options, we remove them here. */
6158 info->disassembler_options = NULL;
6159 }
6160
6161 /* PR 10288: Control which instructions will be disassembled. */
6162 if (info->private_data == NULL)
6163 {
6164 static struct arm_private_data private;
6165
6166 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
6167 /* If the user did not use the -m command line switch then default to
6168 disassembling all types of ARM instruction.
6169
6170 The info->mach value has to be ignored as this will be based on
6171 the default archictecture for the target and/or hints in the notes
6172 section, but it will never be greater than the current largest arm
6173 machine value (iWMMXt2), which is only equivalent to the V5TE
6174 architecture. ARM architectures have advanced beyond the machine
6175 value encoding, and these newer architectures would be ignored if
6176 the machine value was used.
6177
6178 Ie the -m switch is used to restrict which instructions will be
6179 disassembled. If it is necessary to use the -m switch to tell
6180 objdump that an ARM binary is being disassembled, eg because the
6181 input is a raw binary file, but it is also desired to disassemble
6182 all ARM instructions then use "-marm". This will select the
6183 "unknown" arm architecture which is compatible with any ARM
6184 instruction. */
6185 info->mach = bfd_mach_arm_unknown;
6186
6187 /* Compute the architecture bitmask from the machine number.
6188 Note: This assumes that the machine number will not change
6189 during disassembly.... */
6190 select_arm_features (info->mach, & private.features);
6191
6192 private.has_mapping_symbols = -1;
6193 private.last_mapping_sym = -1;
6194 private.last_mapping_addr = 0;
6195
6196 info->private_data = & private;
6197 }
6198
6199 private_data = info->private_data;
6200
6201 /* Decide if our code is going to be little-endian, despite what the
6202 function argument might say. */
6203 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
6204
6205 /* For ELF, consult the symbol table to determine what kind of code
6206 or data we have. */
6207 if (info->symtab_size != 0
6208 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
6209 {
6210 bfd_vma addr;
6211 int n, start;
6212 int last_sym = -1;
6213 enum map_type type = MAP_ARM;
6214
6215 /* Start scanning at the start of the function, or wherever
6216 we finished last time. */
6217 /* PR 14006. When the address is 0 we are either at the start of the
6218 very first function, or else the first function in a new, unlinked
6219 executable section (eg because uf -ffunction-sections). Either way
6220 start scanning from the beginning of the symbol table, not where we
6221 left off last time. */
6222 if (pc == 0)
6223 start = 0;
6224 else
6225 {
6226 start = info->symtab_pos + 1;
6227 if (start < private_data->last_mapping_sym)
6228 start = private_data->last_mapping_sym;
6229 }
6230 found = FALSE;
6231
6232 /* First, look for mapping symbols. */
6233 if (private_data->has_mapping_symbols != 0)
6234 {
6235 /* Scan up to the location being disassembled. */
6236 for (n = start; n < info->symtab_size; n++)
6237 {
6238 addr = bfd_asymbol_value (info->symtab[n]);
6239 if (addr > pc)
6240 break;
6241 if (get_map_sym_type (info, n, &type))
6242 {
6243 last_sym = n;
6244 found = TRUE;
6245 }
6246 }
6247
6248 if (!found)
6249 {
6250 /* No mapping symbol found at this address. Look backwards
6251 for a preceding one. */
6252 for (n = start - 1; n >= 0; n--)
6253 {
6254 if (get_map_sym_type (info, n, &type))
6255 {
6256 last_sym = n;
6257 found = TRUE;
6258 break;
6259 }
6260 }
6261 }
6262
6263 if (found)
6264 private_data->has_mapping_symbols = 1;
6265
6266 /* No mapping symbols were found. A leading $d may be
6267 omitted for sections which start with data; but for
6268 compatibility with legacy and stripped binaries, only
6269 assume the leading $d if there is at least one mapping
6270 symbol in the file. */
6271 if (!found && private_data->has_mapping_symbols == -1)
6272 {
6273 /* Look for mapping symbols, in any section. */
6274 for (n = 0; n < info->symtab_size; n++)
6275 if (is_mapping_symbol (info, n, &type))
6276 {
6277 private_data->has_mapping_symbols = 1;
6278 break;
6279 }
6280 if (private_data->has_mapping_symbols == -1)
6281 private_data->has_mapping_symbols = 0;
6282 }
6283
6284 if (!found && private_data->has_mapping_symbols == 1)
6285 {
6286 type = MAP_DATA;
6287 found = TRUE;
6288 }
6289 }
6290
6291 /* Next search for function symbols to separate ARM from Thumb
6292 in binaries without mapping symbols. */
6293 if (!found)
6294 {
6295 /* Scan up to the location being disassembled. */
6296 for (n = start; n < info->symtab_size; n++)
6297 {
6298 addr = bfd_asymbol_value (info->symtab[n]);
6299 if (addr > pc)
6300 break;
6301 if (get_sym_code_type (info, n, &type))
6302 {
6303 last_sym = n;
6304 found = TRUE;
6305 }
6306 }
6307
6308 if (!found)
6309 {
6310 /* No mapping symbol found at this address. Look backwards
6311 for a preceding one. */
6312 for (n = start - 1; n >= 0; n--)
6313 {
6314 if (get_sym_code_type (info, n, &type))
6315 {
6316 last_sym = n;
6317 found = TRUE;
6318 break;
6319 }
6320 }
6321 }
6322 }
6323
6324 private_data->last_mapping_sym = last_sym;
6325 private_data->last_type = type;
6326 is_thumb = (private_data->last_type == MAP_THUMB);
6327 is_data = (private_data->last_type == MAP_DATA);
6328
6329 /* Look a little bit ahead to see if we should print out
6330 two or four bytes of data. If there's a symbol,
6331 mapping or otherwise, after two bytes then don't
6332 print more. */
6333 if (is_data)
6334 {
6335 size = 4 - (pc & 3);
6336 for (n = last_sym + 1; n < info->symtab_size; n++)
6337 {
6338 addr = bfd_asymbol_value (info->symtab[n]);
6339 if (addr > pc
6340 && (info->section == NULL
6341 || info->section == info->symtab[n]->section))
6342 {
6343 if (addr - pc < size)
6344 size = addr - pc;
6345 break;
6346 }
6347 }
6348 /* If the next symbol is after three bytes, we need to
6349 print only part of the data, so that we can use either
6350 .byte or .short. */
6351 if (size == 3)
6352 size = (pc & 1) ? 1 : 2;
6353 }
6354 }
6355
6356 if (info->symbols != NULL)
6357 {
6358 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
6359 {
6360 coff_symbol_type * cs;
6361
6362 cs = coffsymbol (*info->symbols);
6363 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
6364 || cs->native->u.syment.n_sclass == C_THUMBSTAT
6365 || cs->native->u.syment.n_sclass == C_THUMBLABEL
6366 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
6367 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
6368 }
6369 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
6370 && !found)
6371 {
6372 /* If no mapping symbol has been found then fall back to the type
6373 of the function symbol. */
6374 elf_symbol_type * es;
6375 unsigned int type;
6376
6377 es = *(elf_symbol_type **)(info->symbols);
6378 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6379
6380 is_thumb = ((ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym)
6381 == ST_BRANCH_TO_THUMB)
6382 || type == STT_ARM_16BIT);
6383 }
6384 else if (bfd_asymbol_flavour (*info->symbols)
6385 == bfd_target_mach_o_flavour)
6386 {
6387 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
6388
6389 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
6390 }
6391 }
6392
6393 if (force_thumb)
6394 is_thumb = TRUE;
6395
6396 if (is_data)
6397 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6398 else
6399 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6400
6401 info->bytes_per_line = 4;
6402
6403 /* PR 10263: Disassemble data if requested to do so by the user. */
6404 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
6405 {
6406 int i;
6407
6408 /* Size was already set above. */
6409 info->bytes_per_chunk = size;
6410 printer = print_insn_data;
6411
6412 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
6413 given = 0;
6414 if (little)
6415 for (i = size - 1; i >= 0; i--)
6416 given = b[i] | (given << 8);
6417 else
6418 for (i = 0; i < (int) size; i++)
6419 given = b[i] | (given << 8);
6420 }
6421 else if (!is_thumb)
6422 {
6423 /* In ARM mode endianness is a straightforward issue: the instruction
6424 is four bytes long and is either ordered 0123 or 3210. */
6425 printer = print_insn_arm;
6426 info->bytes_per_chunk = 4;
6427 size = 4;
6428
6429 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
6430 if (little_code)
6431 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
6432 else
6433 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
6434 }
6435 else
6436 {
6437 /* In Thumb mode we have the additional wrinkle of two
6438 instruction lengths. Fortunately, the bits that determine
6439 the length of the current instruction are always to be found
6440 in the first two bytes. */
6441 printer = print_insn_thumb16;
6442 info->bytes_per_chunk = 2;
6443 size = 2;
6444
6445 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
6446 if (little_code)
6447 given = (b[0]) | (b[1] << 8);
6448 else
6449 given = (b[1]) | (b[0] << 8);
6450
6451 if (!status)
6452 {
6453 /* These bit patterns signal a four-byte Thumb
6454 instruction. */
6455 if ((given & 0xF800) == 0xF800
6456 || (given & 0xF800) == 0xF000
6457 || (given & 0xF800) == 0xE800)
6458 {
6459 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
6460 if (little_code)
6461 given = (b[0]) | (b[1] << 8) | (given << 16);
6462 else
6463 given = (b[1]) | (b[0] << 8) | (given << 16);
6464
6465 printer = print_insn_thumb32;
6466 size = 4;
6467 }
6468 }
6469
6470 if (ifthen_address != pc)
6471 find_ifthen_state (pc, info, little_code);
6472
6473 if (ifthen_state)
6474 {
6475 if ((ifthen_state & 0xf) == 0x8)
6476 ifthen_next_state = 0;
6477 else
6478 ifthen_next_state = (ifthen_state & 0xe0)
6479 | ((ifthen_state & 0xf) << 1);
6480 }
6481 }
6482
6483 if (status)
6484 {
6485 info->memory_error_func (status, pc, info);
6486 return -1;
6487 }
6488 if (info->flags & INSN_HAS_RELOC)
6489 /* If the instruction has a reloc associated with it, then
6490 the offset field in the instruction will actually be the
6491 addend for the reloc. (We are using REL type relocs).
6492 In such cases, we can ignore the pc when computing
6493 addresses, since the addend is not currently pc-relative. */
6494 pc = 0;
6495
6496 printer (pc, info, given);
6497
6498 if (is_thumb)
6499 {
6500 ifthen_state = ifthen_next_state;
6501 ifthen_address += size;
6502 }
6503 return size;
6504 }
6505
6506 int
6507 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
6508 {
6509 /* Detect BE8-ness and record it in the disassembler info. */
6510 if (info->flavour == bfd_target_elf_flavour
6511 && info->section != NULL
6512 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
6513 info->endian_code = BFD_ENDIAN_LITTLE;
6514
6515 return print_insn (pc, info, FALSE);
6516 }
6517
6518 int
6519 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
6520 {
6521 return print_insn (pc, info, TRUE);
6522 }
6523
6524 void
6525 print_arm_disassembler_options (FILE *stream)
6526 {
6527 int i;
6528
6529 fprintf (stream, _("\n\
6530 The following ARM specific disassembler options are supported for use with\n\
6531 the -M switch:\n"));
6532
6533 for (i = NUM_ARM_REGNAMES; i--;)
6534 fprintf (stream, " reg-names-%s %*c%s\n",
6535 regnames[i].name,
6536 (int)(14 - strlen (regnames[i].name)), ' ',
6537 regnames[i].description);
6538
6539 fprintf (stream, " force-thumb Assume all insns are Thumb insns\n");
6540 fprintf (stream, " no-force-thumb Examine preceding label to determine an insn's type\n\n");
6541 }
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