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[PATCH 54/57][Arm][OBJDUMP] Add support for MVE instructions: vmax(a), vmax(a)v,...
[thirdparty/binutils-gdb.git] / opcodes / arm-dis.c
1 /* Instruction printing code for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
6 This file is part of libopcodes.
7
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
22
23 #include "sysdep.h"
24 #include <assert.h>
25
26 #include "disassemble.h"
27 #include "opcode/arm.h"
28 #include "opintl.h"
29 #include "safe-ctype.h"
30 #include "libiberty.h"
31 #include "floatformat.h"
32
33 /* FIXME: This shouldn't be done here. */
34 #include "coff/internal.h"
35 #include "libcoff.h"
36 #include "bfd.h"
37 #include "elf-bfd.h"
38 #include "elf/internal.h"
39 #include "elf/arm.h"
40 #include "mach-o.h"
41
42 /* FIXME: Belongs in global header. */
43 #ifndef strneq
44 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
45 #endif
46
47 /* Cached mapping symbol state. */
48 enum map_type
49 {
50 MAP_ARM,
51 MAP_THUMB,
52 MAP_DATA
53 };
54
55 struct arm_private_data
56 {
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features;
59
60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type;
62
63 /* Tracking symbol table information */
64 int last_mapping_sym;
65
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset;
68 bfd_vma last_mapping_addr;
69 };
70
71 enum mve_instructions
72 {
73 MVE_VPST,
74 MVE_VPT_FP_T1,
75 MVE_VPT_FP_T2,
76 MVE_VPT_VEC_T1,
77 MVE_VPT_VEC_T2,
78 MVE_VPT_VEC_T3,
79 MVE_VPT_VEC_T4,
80 MVE_VPT_VEC_T5,
81 MVE_VPT_VEC_T6,
82 MVE_VCMP_FP_T1,
83 MVE_VCMP_FP_T2,
84 MVE_VCMP_VEC_T1,
85 MVE_VCMP_VEC_T2,
86 MVE_VCMP_VEC_T3,
87 MVE_VCMP_VEC_T4,
88 MVE_VCMP_VEC_T5,
89 MVE_VCMP_VEC_T6,
90 MVE_VDUP,
91 MVE_VEOR,
92 MVE_VFMAS_FP_SCALAR,
93 MVE_VFMA_FP_SCALAR,
94 MVE_VFMA_FP,
95 MVE_VFMS_FP,
96 MVE_VHADD_T1,
97 MVE_VHADD_T2,
98 MVE_VHSUB_T1,
99 MVE_VHSUB_T2,
100 MVE_VRHADD,
101 MVE_VLD2,
102 MVE_VLD4,
103 MVE_VST2,
104 MVE_VST4,
105 MVE_VLDRB_T1,
106 MVE_VLDRH_T2,
107 MVE_VLDRB_T5,
108 MVE_VLDRH_T6,
109 MVE_VLDRW_T7,
110 MVE_VSTRB_T1,
111 MVE_VSTRH_T2,
112 MVE_VSTRB_T5,
113 MVE_VSTRH_T6,
114 MVE_VSTRW_T7,
115 MVE_VLDRB_GATHER_T1,
116 MVE_VLDRH_GATHER_T2,
117 MVE_VLDRW_GATHER_T3,
118 MVE_VLDRD_GATHER_T4,
119 MVE_VLDRW_GATHER_T5,
120 MVE_VLDRD_GATHER_T6,
121 MVE_VSTRB_SCATTER_T1,
122 MVE_VSTRH_SCATTER_T2,
123 MVE_VSTRW_SCATTER_T3,
124 MVE_VSTRD_SCATTER_T4,
125 MVE_VSTRW_SCATTER_T5,
126 MVE_VSTRD_SCATTER_T6,
127 MVE_VCVT_FP_FIX_VEC,
128 MVE_VCVT_BETWEEN_FP_INT,
129 MVE_VCVT_FP_HALF_FP,
130 MVE_VCVT_FROM_FP_TO_INT,
131 MVE_VRINT_FP,
132 MVE_VMOV_HFP_TO_GP,
133 MVE_VMOV_GP_TO_VEC_LANE,
134 MVE_VMOV_IMM_TO_VEC,
135 MVE_VMOV_VEC_TO_VEC,
136 MVE_VMOV2_VEC_LANE_TO_GP,
137 MVE_VMOV2_GP_TO_VEC_LANE,
138 MVE_VMOV_VEC_LANE_TO_GP,
139 MVE_VMVN_IMM,
140 MVE_VMVN_REG,
141 MVE_VORR_IMM,
142 MVE_VORR_REG,
143 MVE_VORN,
144 MVE_VBIC_IMM,
145 MVE_VBIC_REG,
146 MVE_VMOVX,
147 MVE_VMOVL,
148 MVE_VMOVN,
149 MVE_VMULL_INT,
150 MVE_VMULL_POLY,
151 MVE_VQDMULL_T1,
152 MVE_VQDMULL_T2,
153 MVE_VQMOVN,
154 MVE_VQMOVUN,
155 MVE_VADDV,
156 MVE_VMLADAV_T1,
157 MVE_VMLADAV_T2,
158 MVE_VMLALDAV,
159 MVE_VMLAS,
160 MVE_VADDLV,
161 MVE_VMLSDAV_T1,
162 MVE_VMLSDAV_T2,
163 MVE_VMLSLDAV,
164 MVE_VRMLALDAVH,
165 MVE_VRMLSLDAVH,
166 MVE_VQDMLADH,
167 MVE_VQRDMLADH,
168 MVE_VQDMLAH,
169 MVE_VQRDMLAH,
170 MVE_VQDMLASH,
171 MVE_VQRDMLASH,
172 MVE_VQDMLSDH,
173 MVE_VQRDMLSDH,
174 MVE_VQDMULH_T1,
175 MVE_VQRDMULH_T2,
176 MVE_VQDMULH_T3,
177 MVE_VQRDMULH_T4,
178 MVE_VDDUP,
179 MVE_VDWDUP,
180 MVE_VIWDUP,
181 MVE_VIDUP,
182 MVE_VCADD_FP,
183 MVE_VCADD_VEC,
184 MVE_VHCADD,
185 MVE_VCMLA_FP,
186 MVE_VCMUL_FP,
187 MVE_VQRSHL_T1,
188 MVE_VQRSHL_T2,
189 MVE_VQRSHRN,
190 MVE_VQRSHRUN,
191 MVE_VQSHL_T1,
192 MVE_VQSHL_T2,
193 MVE_VQSHLU_T3,
194 MVE_VQSHL_T4,
195 MVE_VQSHRN,
196 MVE_VQSHRUN,
197 MVE_VRSHL_T1,
198 MVE_VRSHL_T2,
199 MVE_VRSHR,
200 MVE_VRSHRN,
201 MVE_VSHL_T1,
202 MVE_VSHL_T2,
203 MVE_VSHL_T3,
204 MVE_VSHLC,
205 MVE_VSHLL_T1,
206 MVE_VSHLL_T2,
207 MVE_VSHR,
208 MVE_VSHRN,
209 MVE_VSLI,
210 MVE_VSRI,
211 MVE_VADC,
212 MVE_VABAV,
213 MVE_VABD_FP,
214 MVE_VABD_VEC,
215 MVE_VABS_FP,
216 MVE_VABS_VEC,
217 MVE_VADD_FP_T1,
218 MVE_VADD_FP_T2,
219 MVE_VADD_VEC_T1,
220 MVE_VADD_VEC_T2,
221 MVE_VSBC,
222 MVE_VSUB_FP_T1,
223 MVE_VSUB_FP_T2,
224 MVE_VSUB_VEC_T1,
225 MVE_VSUB_VEC_T2,
226 MVE_VAND,
227 MVE_VBRSR,
228 MVE_VCLS,
229 MVE_VCLZ,
230 MVE_VCTP,
231 MVE_VMAX,
232 MVE_VMAXA,
233 MVE_VMAXNM_FP,
234 MVE_VMAXNMA_FP,
235 MVE_VMAXNMV_FP,
236 MVE_VMAXNMAV_FP,
237 MVE_VMAXV,
238 MVE_VMAXAV,
239 MVE_VMIN,
240 MVE_VMINA,
241 MVE_VMINNM_FP,
242 MVE_VMINNMA_FP,
243 MVE_VMINNMV_FP,
244 MVE_VMINNMAV_FP,
245 MVE_VMINV,
246 MVE_VMINAV,
247 MVE_VMLA,
248 MVE_NONE
249 };
250
251 enum mve_unpredictable
252 {
253 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block.
254 */
255 UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and
256 fcB = 1 (vpt). */
257 UNPRED_R13, /* Unpredictable because r13 (sp) or
258 r15 (sp) used. */
259 UNPRED_R15, /* Unpredictable because r15 (pc) is used. */
260 UNPRED_Q_GT_4, /* Unpredictable because
261 vec reg start > 4 (vld4/st4). */
262 UNPRED_Q_GT_6, /* Unpredictable because
263 vec reg start > 6 (vld2/st2). */
264 UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13
265 and WB bit = 1. */
266 UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are
267 equal. */
268 UNPRED_OS, /* Unpredictable because offset scaled == 1. */
269 UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the
270 same. */
271 UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and
272 size = 1. */
273 UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and
274 size = 2. */
275 UNPRED_NONE /* No unpredictable behavior. */
276 };
277
278 enum mve_undefined
279 {
280 UNDEF_SIZE, /* undefined size. */
281 UNDEF_SIZE_0, /* undefined because size == 0. */
282 UNDEF_SIZE_2, /* undefined because size == 2. */
283 UNDEF_SIZE_3, /* undefined because size == 3. */
284 UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
285 UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
286 UNDEF_SIZE_NOT_3, /* undefined because size != 3. */
287 UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and
288 size == 0. */
289 UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and
290 size == 1. */
291 UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */
292 UNDEF_VCVT_IMM6, /* imm6 < 32. */
293 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
294 UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and
295 op1 == (0 or 1). */
296 UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and
297 op2 == 0 and op1 == (0 or 1). */
298 UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode
299 in {0xx1, x0x1}. */
300 UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */
301 UNDEF_NONE /* no undefined behavior. */
302 };
303
304 struct opcode32
305 {
306 arm_feature_set arch; /* Architecture defining this insn. */
307 unsigned long value; /* If arch is 0 then value is a sentinel. */
308 unsigned long mask; /* Recognise insn if (op & mask) == value. */
309 const char * assembler; /* How to disassemble this insn. */
310 };
311
312 /* MVE opcodes. */
313
314 struct mopcode32
315 {
316 arm_feature_set arch; /* Architecture defining this insn. */
317 enum mve_instructions mve_op; /* Specific mve instruction for faster
318 decoding. */
319 unsigned long value; /* If arch is 0 then value is a sentinel. */
320 unsigned long mask; /* Recognise insn if (op & mask) == value. */
321 const char * assembler; /* How to disassemble this insn. */
322 };
323
324 enum isa {
325 ANY,
326 T32,
327 ARM
328 };
329
330
331 /* Shared (between Arm and Thumb mode) opcode. */
332 struct sopcode32
333 {
334 enum isa isa; /* Execution mode instruction availability. */
335 arm_feature_set arch; /* Architecture defining this insn. */
336 unsigned long value; /* If arch is 0 then value is a sentinel. */
337 unsigned long mask; /* Recognise insn if (op & mask) == value. */
338 const char * assembler; /* How to disassemble this insn. */
339 };
340
341 struct opcode16
342 {
343 arm_feature_set arch; /* Architecture defining this insn. */
344 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
345 const char *assembler; /* How to disassemble this insn. */
346 };
347
348 /* print_insn_coprocessor recognizes the following format control codes:
349
350 %% %
351
352 %c print condition code (always bits 28-31 in ARM mode)
353 %q print shifter argument
354 %u print condition code (unconditional in ARM mode,
355 UNPREDICTABLE if not AL in Thumb)
356 %A print address for ldc/stc/ldf/stf instruction
357 %B print vstm/vldm register list
358 %C print vscclrm register list
359 %I print cirrus signed shift immediate: bits 0..3|4..6
360 %J print register for VLDR instruction
361 %K print address for VLDR instruction
362 %F print the COUNT field of a LFM/SFM instruction.
363 %P print floating point precision in arithmetic insn
364 %Q print floating point precision in ldf/stf insn
365 %R print floating point rounding mode
366
367 %<bitfield>c print as a condition code (for vsel)
368 %<bitfield>r print as an ARM register
369 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
370 %<bitfield>ru as %<>r but each u register must be unique.
371 %<bitfield>d print the bitfield in decimal
372 %<bitfield>k print immediate for VFPv3 conversion instruction
373 %<bitfield>x print the bitfield in hex
374 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
375 %<bitfield>f print a floating point constant if >7 else a
376 floating point register
377 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
378 %<bitfield>g print as an iWMMXt 64-bit register
379 %<bitfield>G print as an iWMMXt general purpose or control register
380 %<bitfield>D print as a NEON D register
381 %<bitfield>Q print as a NEON Q register
382 %<bitfield>V print as a NEON D or Q register
383 %<bitfield>E print a quarter-float immediate value
384
385 %y<code> print a single precision VFP reg.
386 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
387 %z<code> print a double precision VFP reg
388 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
389
390 %<bitfield>'c print specified char iff bitfield is all ones
391 %<bitfield>`c print specified char iff bitfield is all zeroes
392 %<bitfield>?ab... select from array of values in big endian order
393
394 %L print as an iWMMXt N/M width field.
395 %Z print the Immediate of a WSHUFH instruction.
396 %l like 'A' except use byte offsets for 'B' & 'H'
397 versions.
398 %i print 5-bit immediate in bits 8,3..0
399 (print "32" when 0)
400 %r print register offset address for wldt/wstr instruction. */
401
402 enum opcode_sentinel_enum
403 {
404 SENTINEL_IWMMXT_START = 1,
405 SENTINEL_IWMMXT_END,
406 SENTINEL_GENERIC_START
407 } opcode_sentinels;
408
409 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
410 #define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
411 #define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
412 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
413
414 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
415
416 static const struct sopcode32 coprocessor_opcodes[] =
417 {
418 /* XScale instructions. */
419 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
420 0x0e200010, 0x0fff0ff0,
421 "mia%c\tacc0, %0-3r, %12-15r"},
422 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
423 0x0e280010, 0x0fff0ff0,
424 "miaph%c\tacc0, %0-3r, %12-15r"},
425 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
426 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
427 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
428 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
429 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
430 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
431
432 /* Intel Wireless MMX technology instructions. */
433 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
434 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
435 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
436 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
437 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
438 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
439 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
440 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
441 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
442 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
443 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
444 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
445 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
446 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
447 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
448 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
449 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
450 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
451 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
452 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
453 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
454 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
455 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
456 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
457 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
458 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
459 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
460 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
461 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
462 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
463 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
464 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
465 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
466 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
467 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
468 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
469 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
470 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
471 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
472 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
473 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
474 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
475 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
476 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
477 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
478 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
479 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
480 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
481 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
482 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
483 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
484 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
485 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
486 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
487 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
488 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
489 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
490 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
491 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
492 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
493 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
494 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
495 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
496 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
497 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
498 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
499 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
500 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
501 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
502 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
503 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
504 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
505 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
506 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
507 0x0e800120, 0x0f800ff0,
508 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
509 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
510 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
511 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
512 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
513 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
514 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
515 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
516 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
517 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
518 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
519 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
520 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
521 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
522 0x0e8000a0, 0x0f800ff0,
523 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
524 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
525 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
526 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
527 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
528 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
529 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
530 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
531 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
532 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
533 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
534 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
535 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
536 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
537 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
538 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
539 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
540 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
541 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
542 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
543 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
544 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
545 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
546 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
547 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
548 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
549 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
550 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
551 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
552 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
553 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
554 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
555 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
556 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
557 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
558 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
559 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
560 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
561 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
562 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
563 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
564 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
565 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
566 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
567 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
568 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
569 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
570 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
571 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
572 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
573 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
574 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
575 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
576 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
577 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
578 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
579 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
580 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
581 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
582 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
583 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
584 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
585 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
586 {ANY, ARM_FEATURE_CORE_LOW (0),
587 SENTINEL_IWMMXT_END, 0, "" },
588
589 /* Floating point coprocessor (FPA) instructions. */
590 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
591 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
592 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
593 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
594 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
595 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
596 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
597 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
598 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
599 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
600 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
601 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
602 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
603 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
604 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
605 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
606 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
607 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
608 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
609 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
610 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
611 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
612 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
613 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
614 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
615 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
616 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
617 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
618 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
619 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
620 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
621 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
622 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
623 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
624 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
625 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
626 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
627 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
628 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
629 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
630 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
631 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
632 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
633 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
634 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
635 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
636 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
637 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
638 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
639 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
640 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
641 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
642 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
643 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
644 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
645 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
646 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
647 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
648 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
649 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
650 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
651 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
652 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
653 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
654 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
655 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
656 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
657 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
658 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
659 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
660 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
661 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
662 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
663 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
664 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
665 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
666 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
667 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
668 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
669 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
670 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
671 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
672 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
673 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
674 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
675 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
676
677 /* Armv8.1-M Mainline instructions. */
678 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
679 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
680 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
681 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
682
683 /* ARMv8-M Mainline Security Extensions instructions. */
684 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
685 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
686 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
687 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
688
689 /* Register load/store. */
690 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
691 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
692 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
693 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
694 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
695 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
696 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
697 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
698 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
699 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
700 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
701 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
702 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
703 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
704 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
705 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
706 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
707 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
708 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
709 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
710 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
711 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
712 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
713 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
714 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
715 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
716 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
717 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
718 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
719 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
720 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
721 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
722 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
723 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
724 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
725 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
726
727 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
728 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
729 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
730 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
731 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
732 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
733 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
734 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
735
736 /* Data transfer between ARM and NEON registers. */
737 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
738 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
739 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
740 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
741 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
742 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
743 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
744 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
745 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
746 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
747 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
748 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
749 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
750 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
751 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
752 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
753 /* Half-precision conversion instructions. */
754 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
755 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
756 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
757 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
758 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
759 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
760 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
761 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
762
763 /* Floating point coprocessor (VFP) instructions. */
764 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
765 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
766 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
767 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
768 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
769 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
770 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
771 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
772 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
773 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
774 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
775 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
776 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
777 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
778 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
779 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
780 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
781 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
782 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
783 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
784 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
785 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
786 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
787 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
788 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
789 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
790 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
791 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
792 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
793 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
794 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
795 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
796 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
797 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
798 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
799 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
800 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
801 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
802 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
803 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
804 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
805 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
806 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
807 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
808 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
809 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
810 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
811 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
812 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
813 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
814 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
815 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
816 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
817 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
818 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
819 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
820 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
821 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
822 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
824 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
825 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
826 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
827 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
828 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
829 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
830 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
831 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
832 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
833 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
834 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
835 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
836 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
837 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
838 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
839 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
840 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
841 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
842 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
843 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
844 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
845 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
846 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
847 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
848 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
849 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
850 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
851 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
852 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
853 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
854 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
855 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
856 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
857 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
858 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
859 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
860 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
861 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
862 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
863 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
864 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
865 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
866 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
867 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
868 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
869 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
870 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
871 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
872 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
873 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
874 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
875 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
876 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
877 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
878 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
879 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
880 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
881 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
882 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
883 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
884 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
885 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
886 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
887 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
888 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
889 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
890 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
891 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
892 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
893 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
894 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
895 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
896 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
897 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
898 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
899 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
900 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
901 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
902
903 /* Cirrus coprocessor instructions. */
904 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
905 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
906 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
907 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
908 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
909 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
910 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
911 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
912 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
913 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
914 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
915 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
916 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
917 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
918 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
919 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
920 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
921 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
922 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
923 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
924 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
925 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
926 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
927 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
928 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
929 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
930 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
931 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
932 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
933 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
934 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
935 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
936 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
937 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
938 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
939 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
940 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
941 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
942 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
943 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
944 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
945 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
946 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
947 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
948 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
949 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
950 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
951 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
952 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
953 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
954 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
955 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
956 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
957 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
958 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
959 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
960 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
961 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
962 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
963 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
964 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
965 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
966 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
967 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
968 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
969 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
970 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
971 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
972 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
973 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
974 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
975 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
976 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
977 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
978 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
979 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
980 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
981 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
982 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
983 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
984 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
985 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
986 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
987 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
988 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
989 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
990 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
991 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
992 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
993 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
994 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
995 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
996 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
997 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
998 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
999 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
1000 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1001 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
1002 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1003 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
1004 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1005 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
1006 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1007 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
1008 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1009 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
1010 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1011 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
1012 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1013 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
1014 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1015 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
1016 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1017 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
1018 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1019 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
1020 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1021 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
1022 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1023 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
1024 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1025 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
1026 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1027 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
1028 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1029 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1030 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1031 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1032 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1033 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1034 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1035 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1036 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1037 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1038 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1039 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1040 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1041 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
1042 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1043 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
1044 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1045 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
1046 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1047 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
1048 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1049 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1050 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1051 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1052 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1053 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1054 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1055 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1056 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1057 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1058 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1059 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1060 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1061 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1062 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1063 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1064 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1065 0x0e000600, 0x0ff00f10,
1066 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1067 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1068 0x0e100600, 0x0ff00f10,
1069 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1070 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1071 0x0e200600, 0x0ff00f10,
1072 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1073 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1074 0x0e300600, 0x0ff00f10,
1075 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1076
1077 /* VFP Fused multiply add instructions. */
1078 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1079 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
1080 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1081 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
1082 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1083 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
1084 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1085 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
1086 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1087 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
1088 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1089 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
1090 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1091 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
1092 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1093 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
1094
1095 /* FP v5. */
1096 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1097 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
1098 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1099 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
1100 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1101 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
1102 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1103 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
1104 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1105 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
1106 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1107 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
1108 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1109 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
1110 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1111 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
1112 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1113 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
1114 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1115 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
1116 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1117 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
1118 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1119 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
1120
1121 /* Generic coprocessor instructions. */
1122 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
1123 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1124 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
1125 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1126 0x0c500000, 0x0ff00000,
1127 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1128 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1129 0x0e000000, 0x0f000010,
1130 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1131 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1132 0x0e10f010, 0x0f10f010,
1133 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
1134 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1135 0x0e100010, 0x0f100010,
1136 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1137 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1138 0x0e000010, 0x0f100010,
1139 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1140 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1141 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
1142 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1143 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
1144
1145 /* V6 coprocessor instructions. */
1146 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1147 0xfc500000, 0xfff00000,
1148 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1149 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1150 0xfc400000, 0xfff00000,
1151 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
1152
1153 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
1154 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1155 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1156 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1157 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1158 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1159 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1160 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1161 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1162 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1163 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1164 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1165 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1166 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1167 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
1168 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1169 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
1170 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1171 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
1172 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1173 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
1174
1175 /* Dot Product instructions in the space of coprocessor 13. */
1176 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
1177 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
1178 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
1179 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1180
1181 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
1182 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1183 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1184 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1185 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1186 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1187 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1188 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1189 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1190 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1191 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1192 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1193 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1194 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1195 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1196 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1197 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1198
1199 /* V5 coprocessor instructions. */
1200 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1201 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1202 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1203 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1204 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1205 0xfe000000, 0xff000010,
1206 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1207 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1208 0xfe000010, 0xff100010,
1209 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1210 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1211 0xfe100010, 0xff100010,
1212 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1213
1214 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1215 cp_num: bit <11:8> == 0b1001.
1216 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
1217 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1218 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
1219 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1220 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
1221 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1222 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
1223 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1224 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
1225 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1226 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
1227 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1228 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
1229 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1230 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
1231 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1232 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
1233 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1234 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1235 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1236 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1237 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1238 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1239 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1240 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1241 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1242 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1243 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1244 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1245 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1246 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1247 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1248 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1249 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1250 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1251 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1252 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1253 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1254 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1255 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1256 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1257 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1258 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1259 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1260 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1261 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1262 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1263 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1264 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1265 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1266 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1267 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1268 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1269 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1270 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1271 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1272 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1273 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1274 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1275 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1276 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1277 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1278 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1279 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1280 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1281 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1282 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1283 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1284 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1285 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1286 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1287
1288 /* ARMv8.3 javascript conversion instruction. */
1289 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1290 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1291
1292 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1293 };
1294
1295 /* Neon opcode table: This does not encode the top byte -- that is
1296 checked by the print_insn_neon routine, as it depends on whether we are
1297 doing thumb32 or arm32 disassembly. */
1298
1299 /* print_insn_neon recognizes the following format control codes:
1300
1301 %% %
1302
1303 %c print condition code
1304 %u print condition code (unconditional in ARM mode,
1305 UNPREDICTABLE if not AL in Thumb)
1306 %A print v{st,ld}[1234] operands
1307 %B print v{st,ld}[1234] any one operands
1308 %C print v{st,ld}[1234] single->all operands
1309 %D print scalar
1310 %E print vmov, vmvn, vorr, vbic encoded constant
1311 %F print vtbl,vtbx register list
1312
1313 %<bitfield>r print as an ARM register
1314 %<bitfield>d print the bitfield in decimal
1315 %<bitfield>e print the 2^N - bitfield in decimal
1316 %<bitfield>D print as a NEON D register
1317 %<bitfield>Q print as a NEON Q register
1318 %<bitfield>R print as a NEON D or Q register
1319 %<bitfield>Sn print byte scaled width limited by n
1320 %<bitfield>Tn print short scaled width limited by n
1321 %<bitfield>Un print long scaled width limited by n
1322
1323 %<bitfield>'c print specified char iff bitfield is all ones
1324 %<bitfield>`c print specified char iff bitfield is all zeroes
1325 %<bitfield>?ab... select from array of values in big endian order. */
1326
1327 static const struct opcode32 neon_opcodes[] =
1328 {
1329 /* Extract. */
1330 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1331 0xf2b00840, 0xffb00850,
1332 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1333 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1334 0xf2b00000, 0xffb00810,
1335 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1336
1337 /* Data transfer between ARM and NEON registers. */
1338 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1339 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1340 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1341 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1342 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1343 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1344 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1345 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1346 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1347 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1348 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1349 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1350
1351 /* Move data element to all lanes. */
1352 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1353 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1354 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1355 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1356 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1357 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1358
1359 /* Table lookup. */
1360 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1361 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1362 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1363 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1364
1365 /* Half-precision conversions. */
1366 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1367 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1368 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1369 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1370
1371 /* NEON fused multiply add instructions. */
1372 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1373 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1374 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1375 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1376 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1377 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1378 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1379 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1380
1381 /* Two registers, miscellaneous. */
1382 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1383 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1384 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1385 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1386 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1387 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1388 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1389 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1390 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1391 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1392 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1393 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1394 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1395 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1396 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1397 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1398 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1399 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1400 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1401 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1402 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1403 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1404 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1405 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1406 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1407 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1408 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1409 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1410 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1411 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1412 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1413 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1414 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1415 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1416 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1417 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1418 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1419 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1420 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1421 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1422 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1423 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1424 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1425 0xf3b20300, 0xffb30fd0,
1426 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1427 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1428 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1429 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1430 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1431 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1432 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1433 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1434 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1435 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1436 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1437 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1438 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1439 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1440 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1441 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1442 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1443 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1444 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1445 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1446 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1447 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1448 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1449 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1450 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1451 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1452 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1453 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1454 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1456 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1457 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1458 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1459 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1460 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1462 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1464 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1466 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1468 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1470 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1472 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1474 0xf3bb0600, 0xffbf0e10,
1475 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1476 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1477 0xf3b70600, 0xffbf0e10,
1478 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1479
1480 /* Three registers of the same length. */
1481 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1482 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1483 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1484 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1485 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1486 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1487 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1488 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1489 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1490 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1491 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1492 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1493 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1494 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1495 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1496 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1497 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1498 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1499 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1500 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1501 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1502 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1503 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1504 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1507 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1511 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1512 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1514 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1515 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1517 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1518 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1519 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1520 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1521 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1522 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1523 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1524 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1525 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1526 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1527 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1528 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1529 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1530 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1531 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1532 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1533 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1534 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1535 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1536 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1537 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1538 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1539 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1540 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1541 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1542 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1543 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1544 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1545 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1546 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1547 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1548 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1549 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1550 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1551 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1552 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1553 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1554 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1555 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1556 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1557 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1558 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1559 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1560 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1561 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1562 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1564 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1565 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1566 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1567 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1568 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1569 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1570 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1571 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1572 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1573 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1574 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1576 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1577 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1578 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1579 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1580 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1581 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1582 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1583 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1584 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1585 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1586 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1587 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1588 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1589 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1590 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1591 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1592 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1594 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1595 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1596 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1597 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1598 0xf2000b00, 0xff800f10,
1599 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1600 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1601 0xf2000b10, 0xff800f10,
1602 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1603 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1604 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1605 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1606 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1607 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1608 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1609 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1610 0xf3000b00, 0xff800f10,
1611 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1612 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1613 0xf2000000, 0xfe800f10,
1614 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1615 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1616 0xf2000010, 0xfe800f10,
1617 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1618 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1619 0xf2000100, 0xfe800f10,
1620 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1621 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1622 0xf2000200, 0xfe800f10,
1623 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1624 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1625 0xf2000210, 0xfe800f10,
1626 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1627 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1628 0xf2000300, 0xfe800f10,
1629 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1630 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1631 0xf2000310, 0xfe800f10,
1632 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1633 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1634 0xf2000400, 0xfe800f10,
1635 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1636 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1637 0xf2000410, 0xfe800f10,
1638 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1639 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1640 0xf2000500, 0xfe800f10,
1641 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1642 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1643 0xf2000510, 0xfe800f10,
1644 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1645 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1646 0xf2000600, 0xfe800f10,
1647 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1648 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1649 0xf2000610, 0xfe800f10,
1650 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1651 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1652 0xf2000700, 0xfe800f10,
1653 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1654 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1655 0xf2000710, 0xfe800f10,
1656 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1658 0xf2000910, 0xfe800f10,
1659 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1660 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1661 0xf2000a00, 0xfe800f10,
1662 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1663 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1664 0xf2000a10, 0xfe800f10,
1665 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1666 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1667 0xf3000b10, 0xff800f10,
1668 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1669 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1670 0xf3000c10, 0xff800f10,
1671 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1672
1673 /* One register and an immediate value. */
1674 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1675 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1676 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1677 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1678 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1679 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1680 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1681 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1682 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1683 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1684 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1685 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1687 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1688 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1689 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1691 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1692 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1693 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1694 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1695 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1696 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1697 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1698 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1699 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1700
1701 /* Two registers and a shift amount. */
1702 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1703 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1704 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1705 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1706 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1707 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1708 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1709 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1710 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1711 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1712 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1713 0xf2880950, 0xfeb80fd0,
1714 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1715 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1716 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1717 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1718 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1719 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1720 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1721 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1722 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1723 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1724 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1725 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1726 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1727 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1728 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1729 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1730 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1731 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1732 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1733 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1734 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1735 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1736 0xf2900950, 0xfeb00fd0,
1737 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1738 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1739 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1740 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1741 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1742 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1743 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1744 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1745 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1746 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1747 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1748 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1749 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1750 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1751 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1753 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1754 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1755 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1756 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1757 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1758 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1759 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1760 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1761 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1762 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1763 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1764 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1765 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1766 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1767 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1768 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1769 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1770 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1771 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1772 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1773 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1774 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1775 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1776 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1777 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1778 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1779 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1780 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1781 0xf2a00950, 0xfea00fd0,
1782 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1783 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1784 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1785 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1786 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1787 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1788 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1789 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1790 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1791 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1792 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1793 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1794 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1795 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1796 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1797 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1798 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1799 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1800 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1801 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1802 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1803 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1804 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1805 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1806 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1807 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1808 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1809 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1810 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1811 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1812 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1813 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1814 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1815 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1816 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1817 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1818 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1819 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1820 0xf2a00e10, 0xfea00e90,
1821 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1822 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1823 0xf2a00c10, 0xfea00e90,
1824 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
1825
1826 /* Three registers of different lengths. */
1827 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1828 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1829 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1830 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1831 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1832 0xf2800400, 0xff800f50,
1833 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1834 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1835 0xf2800600, 0xff800f50,
1836 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1837 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1838 0xf2800900, 0xff800f50,
1839 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1840 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1841 0xf2800b00, 0xff800f50,
1842 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1843 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1844 0xf2800d00, 0xff800f50,
1845 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1846 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1847 0xf3800400, 0xff800f50,
1848 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1849 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1850 0xf3800600, 0xff800f50,
1851 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1852 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1853 0xf2800000, 0xfe800f50,
1854 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1855 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1856 0xf2800100, 0xfe800f50,
1857 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1858 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1859 0xf2800200, 0xfe800f50,
1860 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1861 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1862 0xf2800300, 0xfe800f50,
1863 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1864 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1865 0xf2800500, 0xfe800f50,
1866 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1867 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1868 0xf2800700, 0xfe800f50,
1869 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1870 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1871 0xf2800800, 0xfe800f50,
1872 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1873 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1874 0xf2800a00, 0xfe800f50,
1875 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1876 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1877 0xf2800c00, 0xfe800f50,
1878 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1879
1880 /* Two registers and a scalar. */
1881 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1882 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1883 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1884 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1885 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1886 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1887 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1888 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1889 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1890 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1891 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1892 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1893 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1894 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1895 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1896 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1897 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1898 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1899 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1900 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1901 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1902 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1903 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1904 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1905 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1906 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1907 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1908 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1909 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1910 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1911 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1912 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1913 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1914 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1915 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1916 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1917 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1918 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1919 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1920 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1921 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1922 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1923 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1924 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1925 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1926 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1927 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1928 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1929 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1930 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1931 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1932 0xf2800240, 0xfe800f50,
1933 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1934 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1935 0xf2800640, 0xfe800f50,
1936 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1937 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1938 0xf2800a40, 0xfe800f50,
1939 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1940 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1941 0xf2800e40, 0xff800f50,
1942 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1943 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1944 0xf2800f40, 0xff800f50,
1945 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1946 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1947 0xf3800e40, 0xff800f50,
1948 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1949 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1950 0xf3800f40, 0xff800f50,
1951 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1952 },
1953
1954 /* Element and structure load/store. */
1955 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1956 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1957 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1958 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1959 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1960 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1961 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1962 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1963 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1964 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1965 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1966 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1967 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1968 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1969 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1970 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1971 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1972 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1973 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1974 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1975 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1976 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1977 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1978 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1979 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1980 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1981 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1982 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1983 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1984 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1985 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1986 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1987 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1988 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1989 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1990 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1991 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1992 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1993
1994 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
1995 };
1996
1997 /* mve opcode table. */
1998
1999 /* print_insn_mve recognizes the following format control codes:
2000
2001 %% %
2002
2003 %a print '+' or '-' or imm offset in vldr[bhwd] and
2004 vstr[bhwd]
2005 %c print condition code
2006 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
2007 %u print 'U' (unsigned) or 'S' for various mve instructions
2008 %i print MVE predicate(s) for vpt and vpst
2009 %m print rounding mode for vcvt and vrint
2010 %n print vector comparison code for predicated instruction
2011 %s print size for various vcvt instructions
2012 %v print vector predicate for instruction in predicated
2013 block
2014 %o print offset scaled for vldr[hwd] and vstr[hwd]
2015 %w print writeback mode for MVE v{st,ld}[24]
2016 %B print v{st,ld}[24] any one operands
2017 %E print vmov, vmvn, vorr, vbic encoded constant
2018 %N print generic index for vmov
2019 %T print bottom ('b') or top ('t') of source register
2020 %X print exchange field in vmla* instructions
2021
2022 %<bitfield>r print as an ARM register
2023 %<bitfield>d print the bitfield in decimal
2024 %<bitfield>A print accumulate or not
2025 %<bitfield>Q print as a MVE Q register
2026 %<bitfield>F print as a MVE S register
2027 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
2028 UNPREDICTABLE
2029 %<bitfield>s print size for vector predicate & non VMOV instructions
2030 %<bitfield>I print carry flag or not
2031 %<bitfield>i print immediate for vstr/vldr reg +/- imm
2032 %<bitfield>h print high half of 64-bit destination reg
2033 %<bitfield>k print immediate for vector conversion instruction
2034 %<bitfield>l print low half of 64-bit destination reg
2035 %<bitfield>o print rotate value for vcmul
2036 %<bitfield>u print immediate value for vddup/vdwdup
2037 %<bitfield>x print the bitfield in hex.
2038 */
2039
2040 static const struct mopcode32 mve_opcodes[] =
2041 {
2042 /* MVE. */
2043
2044 {ARM_FEATURE_COPROC (FPU_MVE),
2045 MVE_VPST,
2046 0xfe310f4d, 0xffbf1fff,
2047 "vpst%i"
2048 },
2049
2050 /* Floating point VPT T1. */
2051 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2052 MVE_VPT_FP_T1,
2053 0xee310f00, 0xefb10f50,
2054 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2055 /* Floating point VPT T2. */
2056 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2057 MVE_VPT_FP_T2,
2058 0xee310f40, 0xefb10f50,
2059 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2060
2061 /* Vector VPT T1. */
2062 {ARM_FEATURE_COPROC (FPU_MVE),
2063 MVE_VPT_VEC_T1,
2064 0xfe010f00, 0xff811f51,
2065 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2066 /* Vector VPT T2. */
2067 {ARM_FEATURE_COPROC (FPU_MVE),
2068 MVE_VPT_VEC_T2,
2069 0xfe010f01, 0xff811f51,
2070 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2071 /* Vector VPT T3. */
2072 {ARM_FEATURE_COPROC (FPU_MVE),
2073 MVE_VPT_VEC_T3,
2074 0xfe011f00, 0xff811f50,
2075 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2076 /* Vector VPT T4. */
2077 {ARM_FEATURE_COPROC (FPU_MVE),
2078 MVE_VPT_VEC_T4,
2079 0xfe010f40, 0xff811f70,
2080 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2081 /* Vector VPT T5. */
2082 {ARM_FEATURE_COPROC (FPU_MVE),
2083 MVE_VPT_VEC_T5,
2084 0xfe010f60, 0xff811f70,
2085 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2086 /* Vector VPT T6. */
2087 {ARM_FEATURE_COPROC (FPU_MVE),
2088 MVE_VPT_VEC_T6,
2089 0xfe011f40, 0xff811f50,
2090 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2091
2092 /* Vector VBIC immediate. */
2093 {ARM_FEATURE_COPROC (FPU_MVE),
2094 MVE_VBIC_IMM,
2095 0xef800070, 0xefb81070,
2096 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2097
2098 /* Vector VBIC register. */
2099 {ARM_FEATURE_COPROC (FPU_MVE),
2100 MVE_VBIC_REG,
2101 0xef100150, 0xffb11f51,
2102 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2103
2104 /* Vector VABAV. */
2105 {ARM_FEATURE_COPROC (FPU_MVE),
2106 MVE_VABAV,
2107 0xee800f01, 0xefc10f51,
2108 "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2109
2110 /* Vector VABD floating point. */
2111 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2112 MVE_VABD_FP,
2113 0xff200d40, 0xffa11f51,
2114 "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2115
2116 /* Vector VABD. */
2117 {ARM_FEATURE_COPROC (FPU_MVE),
2118 MVE_VABD_VEC,
2119 0xef000740, 0xef811f51,
2120 "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2121
2122 /* Vector VABS floating point. */
2123 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2124 MVE_VABS_FP,
2125 0xFFB10740, 0xFFB31FD1,
2126 "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2127 /* Vector VABS. */
2128 {ARM_FEATURE_COPROC (FPU_MVE),
2129 MVE_VABS_VEC,
2130 0xffb10340, 0xffb31fd1,
2131 "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2132
2133 /* Vector VADD floating point T1. */
2134 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2135 MVE_VADD_FP_T1,
2136 0xef000d40, 0xffa11f51,
2137 "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2138 /* Vector VADD floating point T2. */
2139 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2140 MVE_VADD_FP_T2,
2141 0xee300f40, 0xefb11f70,
2142 "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2143 /* Vector VADD T1. */
2144 {ARM_FEATURE_COPROC (FPU_MVE),
2145 MVE_VADD_VEC_T1,
2146 0xef000840, 0xff811f51,
2147 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2148 /* Vector VADD T2. */
2149 {ARM_FEATURE_COPROC (FPU_MVE),
2150 MVE_VADD_VEC_T2,
2151 0xee010f40, 0xff811f70,
2152 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2153
2154 /* Vector VADDLV. */
2155 {ARM_FEATURE_COPROC (FPU_MVE),
2156 MVE_VADDLV,
2157 0xee890f00, 0xef8f1fd1,
2158 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2159
2160 /* Vector VADDV. */
2161 {ARM_FEATURE_COPROC (FPU_MVE),
2162 MVE_VADDV,
2163 0xeef10f00, 0xeff31fd1,
2164 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2165
2166 /* Vector VADC. */
2167 {ARM_FEATURE_COPROC (FPU_MVE),
2168 MVE_VADC,
2169 0xee300f00, 0xffb10f51,
2170 "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2171
2172 /* Vector VAND. */
2173 {ARM_FEATURE_COPROC (FPU_MVE),
2174 MVE_VAND,
2175 0xef000150, 0xffb11f51,
2176 "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2177
2178 /* Vector VBRSR register. */
2179 {ARM_FEATURE_COPROC (FPU_MVE),
2180 MVE_VBRSR,
2181 0xfe011e60, 0xff811f70,
2182 "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2183
2184 /* Vector VCADD floating point. */
2185 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2186 MVE_VCADD_FP,
2187 0xfc800840, 0xfea11f51,
2188 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
2189
2190 /* Vector VCADD. */
2191 {ARM_FEATURE_COPROC (FPU_MVE),
2192 MVE_VCADD_VEC,
2193 0xfe000f00, 0xff810f51,
2194 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2195
2196 /* Vector VCLS. */
2197 {ARM_FEATURE_COPROC (FPU_MVE),
2198 MVE_VCLS,
2199 0xffb00440, 0xffb31fd1,
2200 "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2201
2202 /* Vector VCLZ. */
2203 {ARM_FEATURE_COPROC (FPU_MVE),
2204 MVE_VCLZ,
2205 0xffb004c0, 0xffb31fd1,
2206 "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2207
2208 /* Vector VCMLA. */
2209 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2210 MVE_VCMLA_FP,
2211 0xfc200840, 0xfe211f51,
2212 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
2213
2214 /* Vector VCMP floating point T1. */
2215 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2216 MVE_VCMP_FP_T1,
2217 0xee310f00, 0xeff1ef50,
2218 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2219
2220 /* Vector VCMP floating point T2. */
2221 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2222 MVE_VCMP_FP_T2,
2223 0xee310f40, 0xeff1ef50,
2224 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2225
2226 /* Vector VCMP T1. */
2227 {ARM_FEATURE_COPROC (FPU_MVE),
2228 MVE_VCMP_VEC_T1,
2229 0xfe010f00, 0xffc1ff51,
2230 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2231 /* Vector VCMP T2. */
2232 {ARM_FEATURE_COPROC (FPU_MVE),
2233 MVE_VCMP_VEC_T2,
2234 0xfe010f01, 0xffc1ff51,
2235 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2236 /* Vector VCMP T3. */
2237 {ARM_FEATURE_COPROC (FPU_MVE),
2238 MVE_VCMP_VEC_T3,
2239 0xfe011f00, 0xffc1ff50,
2240 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2241 /* Vector VCMP T4. */
2242 {ARM_FEATURE_COPROC (FPU_MVE),
2243 MVE_VCMP_VEC_T4,
2244 0xfe010f40, 0xffc1ff70,
2245 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2246 /* Vector VCMP T5. */
2247 {ARM_FEATURE_COPROC (FPU_MVE),
2248 MVE_VCMP_VEC_T5,
2249 0xfe010f60, 0xffc1ff70,
2250 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2251 /* Vector VCMP T6. */
2252 {ARM_FEATURE_COPROC (FPU_MVE),
2253 MVE_VCMP_VEC_T6,
2254 0xfe011f40, 0xffc1ff50,
2255 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2256
2257 /* Vector VDUP. */
2258 {ARM_FEATURE_COPROC (FPU_MVE),
2259 MVE_VDUP,
2260 0xeea00b10, 0xffb10f5f,
2261 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2262
2263 /* Vector VEOR. */
2264 {ARM_FEATURE_COPROC (FPU_MVE),
2265 MVE_VEOR,
2266 0xff000150, 0xffd11f51,
2267 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2268
2269 /* Vector VFMA, vector * scalar. */
2270 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2271 MVE_VFMA_FP_SCALAR,
2272 0xee310e40, 0xefb11f70,
2273 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2274
2275 /* Vector VFMA floating point. */
2276 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2277 MVE_VFMA_FP,
2278 0xef000c50, 0xffa11f51,
2279 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2280
2281 /* Vector VFMS floating point. */
2282 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2283 MVE_VFMS_FP,
2284 0xef200c50, 0xffa11f51,
2285 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2286
2287 /* Vector VFMAS, vector * scalar. */
2288 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2289 MVE_VFMAS_FP_SCALAR,
2290 0xee311e40, 0xefb11f70,
2291 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2292
2293 /* Vector VHADD T1. */
2294 {ARM_FEATURE_COPROC (FPU_MVE),
2295 MVE_VHADD_T1,
2296 0xef000040, 0xef811f51,
2297 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2298
2299 /* Vector VHADD T2. */
2300 {ARM_FEATURE_COPROC (FPU_MVE),
2301 MVE_VHADD_T2,
2302 0xee000f40, 0xef811f70,
2303 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2304
2305 /* Vector VHSUB T1. */
2306 {ARM_FEATURE_COPROC (FPU_MVE),
2307 MVE_VHSUB_T1,
2308 0xef000240, 0xef811f51,
2309 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2310
2311 /* Vector VHSUB T2. */
2312 {ARM_FEATURE_COPROC (FPU_MVE),
2313 MVE_VHSUB_T2,
2314 0xee001f40, 0xef811f70,
2315 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2316
2317 /* Vector VCMUL. */
2318 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2319 MVE_VCMUL_FP,
2320 0xee300e00, 0xefb10f50,
2321 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
2322
2323 /* Vector VCTP. */
2324 {ARM_FEATURE_COPROC (FPU_MVE),
2325 MVE_VCTP,
2326 0xf000e801, 0xffc0ffff,
2327 "vctp%v.%20-21s\t%16-19r"},
2328
2329 /* Vector VDUP. */
2330 {ARM_FEATURE_COPROC (FPU_MVE),
2331 MVE_VDUP,
2332 0xeea00b10, 0xffb10f5f,
2333 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2334
2335 /* Vector VRHADD. */
2336 {ARM_FEATURE_COPROC (FPU_MVE),
2337 MVE_VRHADD,
2338 0xef000140, 0xef811f51,
2339 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2340
2341 /* Vector VCVT. */
2342 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2343 MVE_VCVT_FP_FIX_VEC,
2344 0xef800c50, 0xef801cd1,
2345 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2346
2347 /* Vector VCVT. */
2348 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2349 MVE_VCVT_BETWEEN_FP_INT,
2350 0xffb30640, 0xffb31e51,
2351 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2352
2353 /* Vector VCVT between single and half-precision float, bottom half. */
2354 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2355 MVE_VCVT_FP_HALF_FP,
2356 0xee3f0e01, 0xefbf1fd1,
2357 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2358
2359 /* Vector VCVT between single and half-precision float, top half. */
2360 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2361 MVE_VCVT_FP_HALF_FP,
2362 0xee3f1e01, 0xefbf1fd1,
2363 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2364
2365 /* Vector VCVT. */
2366 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2367 MVE_VCVT_FROM_FP_TO_INT,
2368 0xffb30040, 0xffb31c51,
2369 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2370
2371 /* Vector VDDUP. */
2372 {ARM_FEATURE_COPROC (FPU_MVE),
2373 MVE_VDDUP,
2374 0xee011f6e, 0xff811f7e,
2375 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2376
2377 /* Vector VDWDUP. */
2378 {ARM_FEATURE_COPROC (FPU_MVE),
2379 MVE_VDWDUP,
2380 0xee011f60, 0xff811f70,
2381 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2382
2383 /* Vector VHCADD. */
2384 {ARM_FEATURE_COPROC (FPU_MVE),
2385 MVE_VHCADD,
2386 0xee000f00, 0xff810f51,
2387 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2388
2389 /* Vector VIWDUP. */
2390 {ARM_FEATURE_COPROC (FPU_MVE),
2391 MVE_VIWDUP,
2392 0xee010f60, 0xff811f70,
2393 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2394
2395 /* Vector VIDUP. */
2396 {ARM_FEATURE_COPROC (FPU_MVE),
2397 MVE_VIDUP,
2398 0xee010f6e, 0xff811f7e,
2399 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2400
2401 /* Vector VLD2. */
2402 {ARM_FEATURE_COPROC (FPU_MVE),
2403 MVE_VLD2,
2404 0xfc901e00, 0xff901e5f,
2405 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2406
2407 /* Vector VLD4. */
2408 {ARM_FEATURE_COPROC (FPU_MVE),
2409 MVE_VLD4,
2410 0xfc901e01, 0xff901e1f,
2411 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2412
2413 /* Vector VLDRB gather load. */
2414 {ARM_FEATURE_COPROC (FPU_MVE),
2415 MVE_VLDRB_GATHER_T1,
2416 0xec900e00, 0xefb01e50,
2417 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2418
2419 /* Vector VLDRH gather load. */
2420 {ARM_FEATURE_COPROC (FPU_MVE),
2421 MVE_VLDRH_GATHER_T2,
2422 0xec900e10, 0xefb01e50,
2423 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2424
2425 /* Vector VLDRW gather load. */
2426 {ARM_FEATURE_COPROC (FPU_MVE),
2427 MVE_VLDRW_GATHER_T3,
2428 0xfc900f40, 0xffb01fd0,
2429 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2430
2431 /* Vector VLDRD gather load. */
2432 {ARM_FEATURE_COPROC (FPU_MVE),
2433 MVE_VLDRD_GATHER_T4,
2434 0xec900fd0, 0xefb01fd0,
2435 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2436
2437 /* Vector VLDRW gather load. */
2438 {ARM_FEATURE_COPROC (FPU_MVE),
2439 MVE_VLDRW_GATHER_T5,
2440 0xfd101e00, 0xff111f00,
2441 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2442
2443 /* Vector VLDRD gather load, variant T6. */
2444 {ARM_FEATURE_COPROC (FPU_MVE),
2445 MVE_VLDRD_GATHER_T6,
2446 0xfd101f00, 0xff111f00,
2447 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2448
2449 /* Vector VLDRB. */
2450 {ARM_FEATURE_COPROC (FPU_MVE),
2451 MVE_VLDRB_T1,
2452 0xec100e00, 0xee581e00,
2453 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2454
2455 /* Vector VLDRH. */
2456 {ARM_FEATURE_COPROC (FPU_MVE),
2457 MVE_VLDRH_T2,
2458 0xec180e00, 0xee581e00,
2459 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2460
2461 /* Vector VLDRB unsigned, variant T5. */
2462 {ARM_FEATURE_COPROC (FPU_MVE),
2463 MVE_VLDRB_T5,
2464 0xec101e00, 0xfe101f80,
2465 "vldrb%v.u8\t%13-15,22Q, %d"},
2466
2467 /* Vector VLDRH unsigned, variant T6. */
2468 {ARM_FEATURE_COPROC (FPU_MVE),
2469 MVE_VLDRH_T6,
2470 0xec101e80, 0xfe101f80,
2471 "vldrh%v.u16\t%13-15,22Q, %d"},
2472
2473 /* Vector VLDRW unsigned, variant T7. */
2474 {ARM_FEATURE_COPROC (FPU_MVE),
2475 MVE_VLDRW_T7,
2476 0xec101f00, 0xfe101f80,
2477 "vldrw%v.u32\t%13-15,22Q, %d"},
2478
2479 /* Vector VMAX. */
2480 {ARM_FEATURE_COPROC (FPU_MVE),
2481 MVE_VMAX,
2482 0xef000640, 0xef811f51,
2483 "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2484
2485 /* Vector VMAXA. */
2486 {ARM_FEATURE_COPROC (FPU_MVE),
2487 MVE_VMAXA,
2488 0xee330e81, 0xffb31fd1,
2489 "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2490
2491 /* Vector VMAXNM floating point. */
2492 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2493 MVE_VMAXNM_FP,
2494 0xff000f50, 0xffa11f51,
2495 "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2496
2497 /* Vector VMAXNMA floating point. */
2498 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2499 MVE_VMAXNMA_FP,
2500 0xee3f0e81, 0xefbf1fd1,
2501 "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2502
2503 /* Vector VMAXNMV floating point. */
2504 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2505 MVE_VMAXNMV_FP,
2506 0xeeee0f00, 0xefff0fd1,
2507 "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2508
2509 /* Vector VMAXNMAV floating point. */
2510 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2511 MVE_VMAXNMAV_FP,
2512 0xeeec0f00, 0xefff0fd1,
2513 "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2514
2515 /* Vector VMAXV. */
2516 {ARM_FEATURE_COPROC (FPU_MVE),
2517 MVE_VMAXV,
2518 0xeee20f00, 0xeff30fd1,
2519 "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2520
2521 /* Vector VMAXAV. */
2522 {ARM_FEATURE_COPROC (FPU_MVE),
2523 MVE_VMAXAV,
2524 0xeee00f00, 0xfff30fd1,
2525 "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2526
2527 /* Vector VMIN. */
2528 {ARM_FEATURE_COPROC (FPU_MVE),
2529 MVE_VMIN,
2530 0xef000650, 0xef811f51,
2531 "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2532
2533 /* Vector VMINA. */
2534 {ARM_FEATURE_COPROC (FPU_MVE),
2535 MVE_VMINA,
2536 0xee331e81, 0xffb31fd1,
2537 "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2538
2539 /* Vector VMINNM floating point. */
2540 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2541 MVE_VMINNM_FP,
2542 0xff200f50, 0xffa11f51,
2543 "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2544
2545 /* Vector VMINNMA floating point. */
2546 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2547 MVE_VMINNMA_FP,
2548 0xee3f1e81, 0xefbf1fd1,
2549 "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2550
2551 /* Vector VMINNMV floating point. */
2552 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2553 MVE_VMINNMV_FP,
2554 0xeeee0f80, 0xefff0fd1,
2555 "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2556
2557 /* Vector VMINNMAV floating point. */
2558 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2559 MVE_VMINNMAV_FP,
2560 0xeeec0f80, 0xefff0fd1,
2561 "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2562
2563 /* Vector VMINV. */
2564 {ARM_FEATURE_COPROC (FPU_MVE),
2565 MVE_VMINV,
2566 0xeee20f80, 0xeff30fd1,
2567 "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2568
2569 /* Vector VMINAV. */
2570 {ARM_FEATURE_COPROC (FPU_MVE),
2571 MVE_VMINAV,
2572 0xeee00f80, 0xfff30fd1,
2573 "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2574
2575 /* Vector VMLA. */
2576 {ARM_FEATURE_COPROC (FPU_MVE),
2577 MVE_VMLA,
2578 0xee010e40, 0xef811f70,
2579 "vmla%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2580
2581 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2582 opcode aliasing. */
2583 {ARM_FEATURE_COPROC (FPU_MVE),
2584 MVE_VMLALDAV,
2585 0xee801e00, 0xef801f51,
2586 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2587
2588 {ARM_FEATURE_COPROC (FPU_MVE),
2589 MVE_VMLALDAV,
2590 0xee800e00, 0xef801f51,
2591 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2592
2593 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2594 {ARM_FEATURE_COPROC (FPU_MVE),
2595 MVE_VMLADAV_T1,
2596 0xeef00e00, 0xeff01f51,
2597 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2598
2599 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2600 {ARM_FEATURE_COPROC (FPU_MVE),
2601 MVE_VMLADAV_T2,
2602 0xeef00f00, 0xeff11f51,
2603 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2604
2605 /* Vector VMLADAV T1 variant. */
2606 {ARM_FEATURE_COPROC (FPU_MVE),
2607 MVE_VMLADAV_T1,
2608 0xeef01e00, 0xeff01f51,
2609 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2610
2611 /* Vector VMLADAV T2 variant. */
2612 {ARM_FEATURE_COPROC (FPU_MVE),
2613 MVE_VMLADAV_T2,
2614 0xeef01f00, 0xeff11f51,
2615 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2616
2617 /* Vector VMLAS. */
2618 {ARM_FEATURE_COPROC (FPU_MVE),
2619 MVE_VMLAS,
2620 0xee011e40, 0xef811f70,
2621 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2622
2623 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2624 opcode aliasing. */
2625 {ARM_FEATURE_COPROC (FPU_MVE),
2626 MVE_VRMLSLDAVH,
2627 0xfe800e01, 0xff810f51,
2628 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2629
2630 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2631 opcdoe aliasing. */
2632 {ARM_FEATURE_COPROC (FPU_MVE),
2633 MVE_VMLSLDAV,
2634 0xee800e01, 0xff800f51,
2635 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2636
2637 /* Vector VMLSDAV T1 Variant. */
2638 {ARM_FEATURE_COPROC (FPU_MVE),
2639 MVE_VMLSDAV_T1,
2640 0xeef00e01, 0xfff00f51,
2641 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2642
2643 /* Vector VMLSDAV T2 Variant. */
2644 {ARM_FEATURE_COPROC (FPU_MVE),
2645 MVE_VMLSDAV_T2,
2646 0xfef00e01, 0xfff10f51,
2647 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2648
2649 /* Vector VMOV between gpr and half precision register, op == 0. */
2650 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2651 MVE_VMOV_HFP_TO_GP,
2652 0xee000910, 0xfff00f7f,
2653 "vmov.f16\t%7,16-19F, %12-15r"},
2654
2655 /* Vector VMOV between gpr and half precision register, op == 1. */
2656 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2657 MVE_VMOV_HFP_TO_GP,
2658 0xee100910, 0xfff00f7f,
2659 "vmov.f16\t%12-15r, %7,16-19F"},
2660
2661 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2662 MVE_VMOV_GP_TO_VEC_LANE,
2663 0xee000b10, 0xff900f1f,
2664 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2665
2666 /* Vector VORR immediate to vector.
2667 NOTE: MVE_VORR_IMM must appear in the table
2668 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2669 {ARM_FEATURE_COPROC (FPU_MVE),
2670 MVE_VORR_IMM,
2671 0xef800050, 0xefb810f0,
2672 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2673
2674 /* Vector VQSHL T2 Variant.
2675 NOTE: MVE_VQSHL_T2 must appear in the table before
2676 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2677 {ARM_FEATURE_COPROC (FPU_MVE),
2678 MVE_VQSHL_T2,
2679 0xef800750, 0xef801fd1,
2680 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2681
2682 /* Vector VQSHLU T3 Variant
2683 NOTE: MVE_VQSHL_T2 must appear in the table before
2684 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2685
2686 {ARM_FEATURE_COPROC (FPU_MVE),
2687 MVE_VQSHLU_T3,
2688 0xff800650, 0xff801fd1,
2689 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2690
2691 /* Vector VRSHR
2692 NOTE: MVE_VRSHR must appear in the table before
2693 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2694 {ARM_FEATURE_COPROC (FPU_MVE),
2695 MVE_VRSHR,
2696 0xef800250, 0xef801fd1,
2697 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2698
2699 /* Vector VSHL.
2700 NOTE: MVE_VSHL must appear in the table before
2701 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2702 {ARM_FEATURE_COPROC (FPU_MVE),
2703 MVE_VSHL_T1,
2704 0xef800550, 0xff801fd1,
2705 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2706
2707 /* Vector VSHR
2708 NOTE: MVE_VSHR must appear in the table before
2709 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2710 {ARM_FEATURE_COPROC (FPU_MVE),
2711 MVE_VSHR,
2712 0xef800050, 0xef801fd1,
2713 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2714
2715 /* Vector VSLI
2716 NOTE: MVE_VSLI must appear in the table before
2717 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2718 {ARM_FEATURE_COPROC (FPU_MVE),
2719 MVE_VSLI,
2720 0xff800550, 0xff801fd1,
2721 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2722
2723 /* Vector VSRI
2724 NOTE: MVE_VSRI must appear in the table before
2725 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2726 {ARM_FEATURE_COPROC (FPU_MVE),
2727 MVE_VSRI,
2728 0xff800450, 0xff801fd1,
2729 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2730
2731 /* Vector VMOV immediate to vector,
2732 cmode == 11x1 -> VMVN which is UNDEFINED
2733 for such a cmode. */
2734 {ARM_FEATURE_COPROC (FPU_MVE),
2735 MVE_VMVN_IMM, 0xef800d50, 0xefb81dd0, UNDEFINED_INSTRUCTION},
2736
2737 /* Vector VMOV immediate to vector. */
2738 {ARM_FEATURE_COPROC (FPU_MVE),
2739 MVE_VMOV_IMM_TO_VEC,
2740 0xef800050, 0xefb810d0,
2741 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2742
2743 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2744 {ARM_FEATURE_COPROC (FPU_MVE),
2745 MVE_VMOV2_VEC_LANE_TO_GP,
2746 0xec000f00, 0xffb01ff0,
2747 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2748
2749 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2750 {ARM_FEATURE_COPROC (FPU_MVE),
2751 MVE_VMOV2_VEC_LANE_TO_GP,
2752 0xec000f10, 0xffb01ff0,
2753 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2754
2755 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2756 {ARM_FEATURE_COPROC (FPU_MVE),
2757 MVE_VMOV2_GP_TO_VEC_LANE,
2758 0xec100f00, 0xffb01ff0,
2759 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2760
2761 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2762 {ARM_FEATURE_COPROC (FPU_MVE),
2763 MVE_VMOV2_GP_TO_VEC_LANE,
2764 0xec100f10, 0xffb01ff0,
2765 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2766
2767 /* Vector VMOV Vector lane to gpr. */
2768 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2769 MVE_VMOV_VEC_LANE_TO_GP,
2770 0xee100b10, 0xff100f1f,
2771 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2772
2773 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
2774 to instruction opcode aliasing. */
2775 {ARM_FEATURE_COPROC (FPU_MVE),
2776 MVE_VSHLL_T1,
2777 0xeea00f40, 0xefa00fd1,
2778 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2779
2780 /* Vector VMOVL long. */
2781 {ARM_FEATURE_COPROC (FPU_MVE),
2782 MVE_VMOVL,
2783 0xeea00f40, 0xefa70fd1,
2784 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2785
2786 /* Vector VMOV and narrow. */
2787 {ARM_FEATURE_COPROC (FPU_MVE),
2788 MVE_VMOVN,
2789 0xfe310e81, 0xffb30fd1,
2790 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2791
2792 /* Floating point move extract. */
2793 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2794 MVE_VMOVX,
2795 0xfeb00a40, 0xffbf0fd0,
2796 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2797
2798 /* Vector VMULL integer. */
2799 {ARM_FEATURE_COPROC (FPU_MVE),
2800 MVE_VMULL_INT,
2801 0xee010e00, 0xef810f51,
2802 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2803
2804 /* Vector VMULL polynomial. */
2805 {ARM_FEATURE_COPROC (FPU_MVE),
2806 MVE_VMULL_POLY,
2807 0xee310e00, 0xefb10f51,
2808 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2809
2810 /* Vector VMVN immediate to vector. */
2811 {ARM_FEATURE_COPROC (FPU_MVE),
2812 MVE_VMVN_IMM,
2813 0xef800070, 0xefb810f0,
2814 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
2815
2816 /* Vector VMVN register. */
2817 {ARM_FEATURE_COPROC (FPU_MVE),
2818 MVE_VMVN_REG,
2819 0xffb005c0, 0xffbf1fd1,
2820 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
2821
2822 /* Vector VORN, vector bitwise or not. */
2823 {ARM_FEATURE_COPROC (FPU_MVE),
2824 MVE_VORN,
2825 0xef300150, 0xffb11f51,
2826 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2827
2828 /* Vector VORR register. */
2829 {ARM_FEATURE_COPROC (FPU_MVE),
2830 MVE_VORR_REG,
2831 0xef200150, 0xffb11f51,
2832 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2833
2834 /* Vector VQDMULL T1 variant. */
2835 {ARM_FEATURE_COPROC (FPU_MVE),
2836 MVE_VQDMULL_T1,
2837 0xee300f01, 0xefb10f51,
2838 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2839
2840 /* Vector VQDMULL T2 variant. */
2841 {ARM_FEATURE_COPROC (FPU_MVE),
2842 MVE_VQDMULL_T2,
2843 0xee300f60, 0xefb10f70,
2844 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2845
2846 /* Vector VQMOVN. */
2847 {ARM_FEATURE_COPROC (FPU_MVE),
2848 MVE_VQMOVN,
2849 0xee330e01, 0xefb30fd1,
2850 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
2851
2852 /* Vector VQMOVUN. */
2853 {ARM_FEATURE_COPROC (FPU_MVE),
2854 MVE_VQMOVUN,
2855 0xee310e81, 0xffb30fd1,
2856 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2857
2858 /* Vector VQDMLADH. */
2859 {ARM_FEATURE_COPROC (FPU_MVE),
2860 MVE_VQDMLADH,
2861 0xee000e00, 0xff810f51,
2862 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2863
2864 /* Vector VQRDMLADH. */
2865 {ARM_FEATURE_COPROC (FPU_MVE),
2866 MVE_VQRDMLADH,
2867 0xee000e01, 0xff810f51,
2868 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2869
2870 /* Vector VQDMLAH. */
2871 {ARM_FEATURE_COPROC (FPU_MVE),
2872 MVE_VQDMLAH,
2873 0xee000e60, 0xef811f70,
2874 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2875
2876 /* Vector VQRDMLAH. */
2877 {ARM_FEATURE_COPROC (FPU_MVE),
2878 MVE_VQRDMLAH,
2879 0xee000e40, 0xef811f70,
2880 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2881
2882 /* Vector VQDMLASH. */
2883 {ARM_FEATURE_COPROC (FPU_MVE),
2884 MVE_VQDMLASH,
2885 0xee001e60, 0xef811f70,
2886 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2887
2888 /* Vector VQRDMLASH. */
2889 {ARM_FEATURE_COPROC (FPU_MVE),
2890 MVE_VQRDMLASH,
2891 0xee001e40, 0xef811f70,
2892 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2893
2894 /* Vector VQDMLSDH. */
2895 {ARM_FEATURE_COPROC (FPU_MVE),
2896 MVE_VQDMLSDH,
2897 0xfe000e00, 0xff810f51,
2898 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2899
2900 /* Vector VQRDMLSDH. */
2901 {ARM_FEATURE_COPROC (FPU_MVE),
2902 MVE_VQRDMLSDH,
2903 0xfe000e01, 0xff810f51,
2904 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2905
2906 /* Vector VQDMULH T1 variant. */
2907 {ARM_FEATURE_COPROC (FPU_MVE),
2908 MVE_VQDMULH_T1,
2909 0xef000b40, 0xff811f51,
2910 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2911
2912 /* Vector VQRDMULH T2 variant. */
2913 {ARM_FEATURE_COPROC (FPU_MVE),
2914 MVE_VQRDMULH_T2,
2915 0xff000b40, 0xff811f51,
2916 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2917
2918 /* Vector VQDMULH T3 variant. */
2919 {ARM_FEATURE_COPROC (FPU_MVE),
2920 MVE_VQDMULH_T3,
2921 0xee010e60, 0xff811f70,
2922 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2923
2924 /* Vector VQRDMULH T4 variant. */
2925 {ARM_FEATURE_COPROC (FPU_MVE),
2926 MVE_VQRDMULH_T4,
2927 0xfe010e60, 0xff811f70,
2928 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2929
2930 /* Vector VQRSHL T1 variant. */
2931 {ARM_FEATURE_COPROC (FPU_MVE),
2932 MVE_VQRSHL_T1,
2933 0xef000550, 0xef811f51,
2934 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
2935
2936 /* Vector VQRSHL T2 variant. */
2937 {ARM_FEATURE_COPROC (FPU_MVE),
2938 MVE_VQRSHL_T2,
2939 0xee331ee0, 0xefb31ff0,
2940 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
2941
2942 /* Vector VQRSHRN. */
2943 {ARM_FEATURE_COPROC (FPU_MVE),
2944 MVE_VQRSHRN,
2945 0xee800f41, 0xefa00fd1,
2946 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2947
2948 /* Vector VQRSHRUN. */
2949 {ARM_FEATURE_COPROC (FPU_MVE),
2950 MVE_VQRSHRUN,
2951 0xfe800fc0, 0xffa00fd1,
2952 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2953
2954 /* Vector VQSHL T1 Variant. */
2955 {ARM_FEATURE_COPROC (FPU_MVE),
2956 MVE_VQSHL_T1,
2957 0xee311ee0, 0xefb31ff0,
2958 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
2959
2960 /* Vector VQSHL T4 Variant. */
2961 {ARM_FEATURE_COPROC (FPU_MVE),
2962 MVE_VQSHL_T4,
2963 0xef000450, 0xef811f51,
2964 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
2965
2966 /* Vector VQSHRN. */
2967 {ARM_FEATURE_COPROC (FPU_MVE),
2968 MVE_VQSHRN,
2969 0xee800f40, 0xefa00fd1,
2970 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2971
2972 /* Vector VQSHRUN. */
2973 {ARM_FEATURE_COPROC (FPU_MVE),
2974 MVE_VQSHRUN,
2975 0xee800fc0, 0xffa00fd1,
2976 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2977
2978 /* Vector VRINT floating point. */
2979 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2980 MVE_VRINT_FP,
2981 0xffb20440, 0xffb31c51,
2982 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2983
2984 /* Vector VRMLALDAVH. */
2985 {ARM_FEATURE_COPROC (FPU_MVE),
2986 MVE_VRMLALDAVH,
2987 0xee800f00, 0xef811f51,
2988 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2989
2990 /* Vector VRMLALDAVH. */
2991 {ARM_FEATURE_COPROC (FPU_MVE),
2992 MVE_VRMLALDAVH,
2993 0xee801f00, 0xef811f51,
2994 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2995
2996 /* Vector VRSHL T1 Variant. */
2997 {ARM_FEATURE_COPROC (FPU_MVE),
2998 MVE_VRSHL_T1,
2999 0xef000540, 0xef811f51,
3000 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3001
3002 /* Vector VRSHL T2 Variant. */
3003 {ARM_FEATURE_COPROC (FPU_MVE),
3004 MVE_VRSHL_T2,
3005 0xee331e60, 0xefb31ff0,
3006 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3007
3008 /* Vector VRSHRN. */
3009 {ARM_FEATURE_COPROC (FPU_MVE),
3010 MVE_VRSHRN,
3011 0xfe800fc1, 0xffa00fd1,
3012 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3013
3014 /* Vector VSBC. */
3015 {ARM_FEATURE_COPROC (FPU_MVE),
3016 MVE_VSBC,
3017 0xfe300f00, 0xffb10f51,
3018 "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3019
3020 /* Vector VSHL T2 Variant. */
3021 {ARM_FEATURE_COPROC (FPU_MVE),
3022 MVE_VSHL_T2,
3023 0xee311e60, 0xefb31ff0,
3024 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3025
3026 /* Vector VSHL T3 Variant. */
3027 {ARM_FEATURE_COPROC (FPU_MVE),
3028 MVE_VSHL_T3,
3029 0xef000440, 0xef811f51,
3030 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3031
3032 /* Vector VSHLC. */
3033 {ARM_FEATURE_COPROC (FPU_MVE),
3034 MVE_VSHLC,
3035 0xeea00fc0, 0xffa01ff0,
3036 "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
3037
3038 /* Vector VSHLL T2 Variant. */
3039 {ARM_FEATURE_COPROC (FPU_MVE),
3040 MVE_VSHLL_T2,
3041 0xee310e01, 0xefb30fd1,
3042 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
3043
3044 /* Vector VSHRN. */
3045 {ARM_FEATURE_COPROC (FPU_MVE),
3046 MVE_VSHRN,
3047 0xee800fc1, 0xffa00fd1,
3048 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3049
3050 /* Vector VST2 no writeback. */
3051 {ARM_FEATURE_COPROC (FPU_MVE),
3052 MVE_VST2,
3053 0xfc801e00, 0xffb01e5f,
3054 "vst2%5d.%7-8s\t%B, [%16-19r]"},
3055
3056 /* Vector VST2 writeback. */
3057 {ARM_FEATURE_COPROC (FPU_MVE),
3058 MVE_VST2,
3059 0xfca01e00, 0xffb01e5f,
3060 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3061
3062 /* Vector VST4 no writeback. */
3063 {ARM_FEATURE_COPROC (FPU_MVE),
3064 MVE_VST4,
3065 0xfc801e01, 0xffb01e1f,
3066 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3067
3068 /* Vector VST4 writeback. */
3069 {ARM_FEATURE_COPROC (FPU_MVE),
3070 MVE_VST4,
3071 0xfca01e01, 0xffb01e1f,
3072 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3073
3074 /* Vector VSTRB scatter store, T1 variant. */
3075 {ARM_FEATURE_COPROC (FPU_MVE),
3076 MVE_VSTRB_SCATTER_T1,
3077 0xec800e00, 0xffb01e50,
3078 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3079
3080 /* Vector VSTRH scatter store, T2 variant. */
3081 {ARM_FEATURE_COPROC (FPU_MVE),
3082 MVE_VSTRH_SCATTER_T2,
3083 0xec800e10, 0xffb01e50,
3084 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3085
3086 /* Vector VSTRW scatter store, T3 variant. */
3087 {ARM_FEATURE_COPROC (FPU_MVE),
3088 MVE_VSTRW_SCATTER_T3,
3089 0xec800e40, 0xffb01e50,
3090 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3091
3092 /* Vector VSTRD scatter store, T4 variant. */
3093 {ARM_FEATURE_COPROC (FPU_MVE),
3094 MVE_VSTRD_SCATTER_T4,
3095 0xec800fd0, 0xffb01fd0,
3096 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3097
3098 /* Vector VSTRW scatter store, T5 variant. */
3099 {ARM_FEATURE_COPROC (FPU_MVE),
3100 MVE_VSTRW_SCATTER_T5,
3101 0xfd001e00, 0xff111f00,
3102 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3103
3104 /* Vector VSTRD scatter store, T6 variant. */
3105 {ARM_FEATURE_COPROC (FPU_MVE),
3106 MVE_VSTRD_SCATTER_T6,
3107 0xfd001f00, 0xff111f00,
3108 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3109
3110 /* Vector VSTRB. */
3111 {ARM_FEATURE_COPROC (FPU_MVE),
3112 MVE_VSTRB_T1,
3113 0xec000e00, 0xfe581e00,
3114 "vstrb%v.%7-8s\t%13-15Q, %d"},
3115
3116 /* Vector VSTRH. */
3117 {ARM_FEATURE_COPROC (FPU_MVE),
3118 MVE_VSTRH_T2,
3119 0xec080e00, 0xfe581e00,
3120 "vstrh%v.%7-8s\t%13-15Q, %d"},
3121
3122 /* Vector VSTRB variant T5. */
3123 {ARM_FEATURE_COPROC (FPU_MVE),
3124 MVE_VSTRB_T5,
3125 0xec001e00, 0xfe101f80,
3126 "vstrb%v.8\t%13-15,22Q, %d"},
3127
3128 /* Vector VSTRH variant T6. */
3129 {ARM_FEATURE_COPROC (FPU_MVE),
3130 MVE_VSTRH_T6,
3131 0xec001e80, 0xfe101f80,
3132 "vstrh%v.16\t%13-15,22Q, %d"},
3133
3134 /* Vector VSTRW variant T7. */
3135 {ARM_FEATURE_COPROC (FPU_MVE),
3136 MVE_VSTRW_T7,
3137 0xec001f00, 0xfe101f80,
3138 "vstrw%v.32\t%13-15,22Q, %d"},
3139
3140 /* Vector VSUB floating point T1 variant. */
3141 {ARM_FEATURE_COPROC (FPU_MVE_FP),
3142 MVE_VSUB_FP_T1,
3143 0xef200d40, 0xffa11f51,
3144 "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3145
3146 /* Vector VSUB floating point T2 variant. */
3147 {ARM_FEATURE_COPROC (FPU_MVE_FP),
3148 MVE_VSUB_FP_T2,
3149 0xee301f40, 0xefb11f70,
3150 "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3151
3152 /* Vector VSUB T1 variant. */
3153 {ARM_FEATURE_COPROC (FPU_MVE),
3154 MVE_VSUB_VEC_T1,
3155 0xff000840, 0xff811f51,
3156 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3157
3158 /* Vector VSUB T2 variant. */
3159 {ARM_FEATURE_COPROC (FPU_MVE),
3160 MVE_VSUB_VEC_T2,
3161 0xee011f40, 0xff811f70,
3162 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3163
3164 {ARM_FEATURE_CORE_LOW (0),
3165 MVE_NONE,
3166 0x00000000, 0x00000000, 0}
3167 };
3168
3169 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
3170 ordered: they must be searched linearly from the top to obtain a correct
3171 match. */
3172
3173 /* print_insn_arm recognizes the following format control codes:
3174
3175 %% %
3176
3177 %a print address for ldr/str instruction
3178 %s print address for ldr/str halfword/signextend instruction
3179 %S like %s but allow UNPREDICTABLE addressing
3180 %b print branch destination
3181 %c print condition code (always bits 28-31)
3182 %m print register mask for ldm/stm instruction
3183 %o print operand2 (immediate or register + shift)
3184 %p print 'p' iff bits 12-15 are 15
3185 %t print 't' iff bit 21 set and bit 24 clear
3186 %B print arm BLX(1) destination
3187 %C print the PSR sub type.
3188 %U print barrier type.
3189 %P print address for pli instruction.
3190
3191 %<bitfield>r print as an ARM register
3192 %<bitfield>T print as an ARM register + 1
3193 %<bitfield>R as %r but r15 is UNPREDICTABLE
3194 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3195 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
3196 %<bitfield>d print the bitfield in decimal
3197 %<bitfield>W print the bitfield plus one in decimal
3198 %<bitfield>x print the bitfield in hex
3199 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
3200
3201 %<bitfield>'c print specified char iff bitfield is all ones
3202 %<bitfield>`c print specified char iff bitfield is all zeroes
3203 %<bitfield>?ab... select from array of values in big endian order
3204
3205 %e print arm SMI operand (bits 0..7,8..19).
3206 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
3207 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
3208 %R print the SPSR/CPSR or banked register of an MRS. */
3209
3210 static const struct opcode32 arm_opcodes[] =
3211 {
3212 /* ARM instructions. */
3213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3214 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
3215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3216 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
3217
3218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
3219 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3221 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3223 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
3225 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3227 0x00800090, 0x0fa000f0,
3228 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3230 0x00a00090, 0x0fa000f0,
3231 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3232
3233 /* V8.2 RAS extension instructions. */
3234 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
3235 0xe320f010, 0xffffffff, "esb"},
3236
3237 /* V8 instructions. */
3238 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3239 0x0320f005, 0x0fffffff, "sevl"},
3240 /* Defined in V8 but is in NOP space so available to all arch. */
3241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3242 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
3243 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
3244 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
3245 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3246 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3248 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3250 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
3251 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3252 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
3253 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3254 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3255 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3256 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
3257 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3258 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3259 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3260 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
3261 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3262 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
3263 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3264 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
3265 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3266 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3267 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3268 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
3269 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3270 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3271 /* CRC32 instructions. */
3272 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3273 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
3274 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3275 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
3276 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3277 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
3278 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3279 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
3280 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3281 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
3282 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3283 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
3284
3285 /* Privileged Access Never extension instructions. */
3286 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
3287 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
3288
3289 /* Virtualization Extension instructions. */
3290 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
3291 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
3292
3293 /* Integer Divide Extension instructions. */
3294 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3295 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3296 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3297 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
3298
3299 /* MP Extension instructions. */
3300 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
3301
3302 /* Speculation Barriers. */
3303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
3304 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
3305 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
3306
3307 /* V7 instructions. */
3308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
3309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
3310 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3312 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
3315 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3316 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
3317
3318 /* ARM V6T2 instructions. */
3319 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3320 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3321 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3322 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3323 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3324 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3325 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3326 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3327
3328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3329 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
3330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3331 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3332
3333 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3334 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
3335 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3336 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3338 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3339 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3340 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
3341
3342 /* ARM Security extension instructions. */
3343 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
3344 0x01600070, 0x0ff000f0, "smc%c\t%e"},
3345
3346 /* ARM V6K instructions. */
3347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3348 0xf57ff01f, 0xffffffff, "clrex"},
3349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3350 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3352 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3354 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3356 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3358 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3360 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
3361
3362 /* ARMv8.5-A instructions. */
3363 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
3364
3365 /* ARM V6K NOP hints. */
3366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3367 0x0320f001, 0x0fffffff, "yield%c"},
3368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3369 0x0320f002, 0x0fffffff, "wfe%c"},
3370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3371 0x0320f003, 0x0fffffff, "wfi%c"},
3372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3373 0x0320f004, 0x0fffffff, "sev%c"},
3374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3375 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
3376
3377 /* ARM V6 instructions. */
3378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3379 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
3380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3381 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
3382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3383 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
3384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3385 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
3386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3387 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
3388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3389 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3391 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
3392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3393 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
3394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3395 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
3396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3397 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
3398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3399 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3401 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3403 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3405 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3407 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3409 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3411 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3413 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3415 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3417 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3418 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3419 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3421 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3422 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3423 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3425 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3427 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3429 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3431 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3433 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3434 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3435 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3437 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3439 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3440 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3441 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3443 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3445 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3447 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3448 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3449 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3451 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3453 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3455 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3457 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3459 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3461 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3462 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3463 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3465 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3467 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3469 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3471 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3473 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3475 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3476 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3477 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3478 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3479 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3480 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3481 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3482 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3483 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3485 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3487 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3489 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3490 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3491 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3493 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3495 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3497 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3499 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3501 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3502 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3503 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3504 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3505 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3507 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3509 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3510 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3511 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3513 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3515 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3517 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3518 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3519 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3520 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3521 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3522 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3523 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3524 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3525 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3526 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3527 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3528 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3529 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3531 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3533 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3534 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3535 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3537 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3539 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3541 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3543 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3545 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3547 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3549 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3551 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3553 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3555 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3557 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3559 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3561 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3563 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3565 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
3566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3567 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3569 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3571 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3573 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3575 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
3576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3577 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
3578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3579 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
3580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3581 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
3582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3583 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3585 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3587 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3589 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3591 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
3592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3593 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3595 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3597 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
3598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3599 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
3600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3601 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
3602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3603 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
3604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3605 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
3606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3607 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
3608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3609 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
3610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3611 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
3612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3613 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3615 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
3616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3617 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
3618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3619 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
3620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3621 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
3622
3623 /* V5J instruction. */
3624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
3625 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
3626
3627 /* V5 Instructions. */
3628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3629 0xe1200070, 0xfff000f0,
3630 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
3631 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3632 0xfa000000, 0xfe000000, "blx\t%B"},
3633 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3634 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
3635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3636 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
3637
3638 /* V5E "El Segundo" Instructions. */
3639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3640 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
3641 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3642 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
3643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3644 0xf450f000, 0xfc70f000, "pld\t%a"},
3645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3646 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3648 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3650 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3652 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
3653
3654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3655 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3657 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
3658
3659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3660 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3662 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3664 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3665 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3666 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3667
3668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3669 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
3670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3671 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
3672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3673 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
3674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3675 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
3676
3677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3678 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
3679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3680 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
3681
3682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3683 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
3684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3685 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
3686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3687 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
3688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3689 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
3690
3691 /* ARM Instructions. */
3692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3693 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
3694
3695 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3696 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
3697 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3698 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
3699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3700 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
3701 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3702 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
3703 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3704 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
3705 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3706 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
3707
3708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3709 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
3710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3711 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
3712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3713 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
3714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3715 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
3716
3717 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3718 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
3719 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3720 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
3721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3722 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
3723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3724 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
3725
3726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3727 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
3728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3729 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
3730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3731 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
3732
3733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3734 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
3735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3736 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
3737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3738 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
3739
3740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3741 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
3742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3743 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
3744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3745 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
3746
3747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3748 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3750 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3752 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
3753
3754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3755 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
3756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3757 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
3758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3759 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
3760
3761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3762 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
3763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3764 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
3765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3766 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
3767
3768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3769 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3771 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3773 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
3774
3775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3776 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3778 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3780 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
3781
3782 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
3783 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
3784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
3785 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
3786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
3787 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
3788
3789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3790 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
3791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3792 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
3793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3794 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
3795
3796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3797 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
3798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3799 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
3800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3801 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
3802
3803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3804 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
3805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3806 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
3807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3808 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
3809
3810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3811 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
3812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3813 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
3814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3815 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
3816
3817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3818 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
3819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3820 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
3821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3822 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
3823
3824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3825 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
3826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3827 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
3828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3829 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
3830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3831 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
3832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3833 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
3834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3835 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
3836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3837 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
3838
3839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3840 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
3841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3842 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
3843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3844 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
3845
3846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3847 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
3848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3849 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
3850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3851 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
3852
3853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3854 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
3855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3856 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
3857
3858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3859 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
3860
3861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3862 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
3863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3864 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
3865
3866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3867 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3869 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3871 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3873 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3875 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3877 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3879 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3881 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3883 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3885 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3887 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3889 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3891 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3893 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3895 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3897 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3899 0x092d0000, 0x0fff0000, "push%c\t%m"},
3900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3901 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
3902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3903 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3904
3905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3906 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3908 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3910 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3912 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3914 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3916 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3918 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3920 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3922 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3924 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3926 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3928 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3930 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3932 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3934 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3936 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3938 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
3939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3940 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
3941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3942 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3943
3944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3945 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
3946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3947 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
3948
3949 /* The rest. */
3950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3951 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
3952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3953 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3954 {ARM_FEATURE_CORE_LOW (0),
3955 0x00000000, 0x00000000, 0}
3956 };
3957
3958 /* print_insn_thumb16 recognizes the following format control codes:
3959
3960 %S print Thumb register (bits 3..5 as high number if bit 6 set)
3961 %D print Thumb register (bits 0..2 as high number if bit 7 set)
3962 %<bitfield>I print bitfield as a signed decimal
3963 (top bit of range being the sign bit)
3964 %N print Thumb register mask (with LR)
3965 %O print Thumb register mask (with PC)
3966 %M print Thumb register mask
3967 %b print CZB's 6-bit unsigned branch destination
3968 %s print Thumb right-shift immediate (6..10; 0 == 32).
3969 %c print the condition code
3970 %C print the condition code, or "s" if not conditional
3971 %x print warning if conditional an not at end of IT block"
3972 %X print "\t; unpredictable <IT:code>" if conditional
3973 %I print IT instruction suffix and operands
3974 %W print Thumb Writeback indicator for LDMIA
3975 %<bitfield>r print bitfield as an ARM register
3976 %<bitfield>d print bitfield as a decimal
3977 %<bitfield>H print (bitfield * 2) as a decimal
3978 %<bitfield>W print (bitfield * 4) as a decimal
3979 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
3980 %<bitfield>B print Thumb branch destination (signed displacement)
3981 %<bitfield>c print bitfield as a condition code
3982 %<bitnum>'c print specified char iff bit is one
3983 %<bitnum>?ab print a if bit is one else print b. */
3984
3985 static const struct opcode16 thumb_opcodes[] =
3986 {
3987 /* Thumb instructions. */
3988
3989 /* ARMv8-M Security Extensions instructions. */
3990 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
3991 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
3992
3993 /* ARM V8 instructions. */
3994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
3995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
3996 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
3997
3998 /* ARM V6K no-argument instructions. */
3999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
4000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
4001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
4002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
4003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
4004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
4005
4006 /* ARM V6T2 instructions. */
4007 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4008 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4009 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4010 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
4011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
4012
4013 /* ARM V6. */
4014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
4015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
4016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
4020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
4021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
4025
4026 /* ARM V5 ISA extends Thumb. */
4027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4028 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
4029 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
4030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4031 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
4032 /* ARM V4T ISA (Thumb v1). */
4033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4034 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
4035 /* Format 4. */
4036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
4052 /* format 13 */
4053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
4054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
4055 /* format 5 */
4056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
4057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
4058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
4060 /* format 14 */
4061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
4062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
4063 /* format 2 */
4064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4065 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4067 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4069 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
4070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4071 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
4072 /* format 8 */
4073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4074 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4076 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4078 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
4079 /* format 7 */
4080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4081 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4083 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4084 /* format 1 */
4085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4087 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
4088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
4090 /* format 3 */
4091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
4092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
4093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
4094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
4095 /* format 6 */
4096 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4098 0x4800, 0xF800,
4099 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
4100 /* format 9 */
4101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4102 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
4103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4104 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
4105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4106 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
4107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4108 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
4109 /* format 10 */
4110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4111 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
4112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4113 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
4114 /* format 11 */
4115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4116 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
4117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4118 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
4119 /* format 12 */
4120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4121 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
4122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4123 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
4124 /* format 15 */
4125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
4127 /* format 17 */
4128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
4129 /* format 16 */
4130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
4131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
4132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
4133 /* format 18 */
4134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
4135
4136 /* The E800 .. FFFF range is unconditionally redirected to the
4137 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4138 are processed via that table. Thus, we can never encounter a
4139 bare "second half of BL/BLX(1)" instruction here. */
4140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
4141 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
4142 };
4143
4144 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
4145 We adopt the convention that hw1 is the high 16 bits of .value and
4146 .mask, hw2 the low 16 bits.
4147
4148 print_insn_thumb32 recognizes the following format control codes:
4149
4150 %% %
4151
4152 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4153 %M print a modified 12-bit immediate (same location)
4154 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4155 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
4156 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
4157 %S print a possibly-shifted Rm
4158
4159 %L print address for a ldrd/strd instruction
4160 %a print the address of a plain load/store
4161 %w print the width and signedness of a core load/store
4162 %m print register mask for ldm/stm
4163 %n print register mask for clrm
4164
4165 %E print the lsb and width fields of a bfc/bfi instruction
4166 %F print the lsb and width fields of a sbfx/ubfx instruction
4167 %G print a fallback offset for Branch Future instructions
4168 %W print an offset for BF instruction
4169 %Y print an offset for BFL instruction
4170 %Z print an offset for BFCSEL instruction
4171 %Q print an offset for Low Overhead Loop instructions
4172 %P print an offset for Low Overhead Loop end instructions
4173 %b print a conditional branch offset
4174 %B print an unconditional branch offset
4175 %s print the shift field of an SSAT instruction
4176 %R print the rotation field of an SXT instruction
4177 %U print barrier type.
4178 %P print address for pli instruction.
4179 %c print the condition code
4180 %x print warning if conditional an not at end of IT block"
4181 %X print "\t; unpredictable <IT:code>" if conditional
4182
4183 %<bitfield>d print bitfield in decimal
4184 %<bitfield>D print bitfield plus one in decimal
4185 %<bitfield>W print bitfield*4 in decimal
4186 %<bitfield>r print bitfield as an ARM register
4187 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
4188 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
4189 %<bitfield>c print bitfield as a condition code
4190
4191 %<bitfield>'c print specified char iff bitfield is all ones
4192 %<bitfield>`c print specified char iff bitfield is all zeroes
4193 %<bitfield>?ab... select from array of values in big endian order
4194
4195 With one exception at the bottom (done because BL and BLX(1) need
4196 to come dead last), this table was machine-sorted first in
4197 decreasing order of number of bits set in the mask, then in
4198 increasing numeric order of mask, then in increasing numeric order
4199 of opcode. This order is not the clearest for a human reader, but
4200 is guaranteed never to catch a special-case bit pattern with a more
4201 general mask, which is important, because this instruction encoding
4202 makes heavy use of special-case bit patterns. */
4203 static const struct opcode32 thumb32_opcodes[] =
4204 {
4205 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4206 instructions. */
4207 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4208 0xf00fe001, 0xffffffff, "lctp%c"},
4209 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4210 0xf02fc001, 0xfffff001, "le\t%P"},
4211 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4212 0xf00fc001, 0xfffff001, "le\tlr, %P"},
4213 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4214 0xf01fc001, 0xfffff001, "letp\tlr, %P"},
4215 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4216 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
4217 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4218 0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
4219 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4220 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
4221 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4222 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
4223
4224 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4225 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
4226 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4227 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
4228 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4229 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
4230 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4231 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
4232 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4233 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4234
4235 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4236 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4237
4238 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
4239 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4240 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4241 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4242 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4243 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
4244 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4245 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4246 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4247 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4248
4249 /* ARM V8.2 RAS extension instructions. */
4250 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
4251 0xf3af8010, 0xffffffff, "esb"},
4252
4253 /* V8 instructions. */
4254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4255 0xf3af8005, 0xffffffff, "sevl%c.w"},
4256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4257 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4259 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4261 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4263 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4265 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4266 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4267 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4269 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4271 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4273 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4275 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4277 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4279 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4281 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4282 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4283 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4285 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
4286
4287 /* CRC32 instructions. */
4288 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4289 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
4290 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4291 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
4292 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4293 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
4294 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4295 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
4296 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4297 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
4298 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4299 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
4300
4301 /* Speculation Barriers. */
4302 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
4303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
4304 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
4305
4306 /* V7 instructions. */
4307 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
4309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4310 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4312 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4314 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4315 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4316 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4317 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
4318
4319 /* Virtualization Extension instructions. */
4320 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
4321 /* We skip ERET as that is SUBS pc, lr, #0. */
4322
4323 /* MP Extension instructions. */
4324 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
4325
4326 /* Security extension instructions. */
4327 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
4328
4329 /* ARMv8.5-A instructions. */
4330 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
4331
4332 /* Instructions defined in the basic V6T2 set. */
4333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
4334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
4335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
4338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4339 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
4340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4341
4342 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4343 0xf3bf8f2f, 0xffffffff, "clrex%c"},
4344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4345 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
4346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4347 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
4348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4349 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4351 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4353 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4355 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4357 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
4358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4359 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4360 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4361 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
4362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4363 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
4364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4365 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
4366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4367 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
4368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4369 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
4370 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4371 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
4372 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4373 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4375 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
4376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4377 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
4378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4379 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4381 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4383 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4385 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4387 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4389 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
4390 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4391 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4393 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4395 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4397 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4399 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4401 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4403 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4405 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4407 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4409 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4411 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4413 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4415 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4417 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4418 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4419 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4421 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4422 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4423 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4425 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4427 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4429 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4431 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4433 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4434 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4435 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4437 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4439 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4440 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4441 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4443 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4445 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4447 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4448 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4449 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4451 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4453 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4455 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4457 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4459 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4461 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4462 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4463 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4465 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4467 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4469 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4471 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4473 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4475 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4476 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4477 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4478 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4479 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4480 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4481 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4482 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4483 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4485 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4487 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4489 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4490 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4491 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4493 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4495 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4497 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
4498 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4499 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4501 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
4502 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4503 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4504 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4505 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4507 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4509 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4510 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4511 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4513 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4515 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4517 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4518 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4519 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4520 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4521 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4522 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4523 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4524 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4525 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4526 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4527 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4528 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4529 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4531 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4533 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4534 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4535 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4537 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4539 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4541 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4543 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4545 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4547 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4549 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
4550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4551 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4553 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4555 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4557 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4559 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4561 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4563 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4565 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4566 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4567 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
4568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4569 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
4570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4571 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
4572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4573 0xf810f000, 0xff70f000, "pld%c\t%a"},
4574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4575 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4577 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4579 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4581 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4583 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4585 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4587 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4589 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
4590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4591 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
4592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4593 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
4594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4595 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
4596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4597 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
4598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4599 0xfb100000, 0xfff000c0,
4600 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4601 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4602 0xfbc00080, 0xfff000c0,
4603 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
4604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4605 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
4606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4607 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
4608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4609 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
4610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4611 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
4612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4613 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
4614 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4615 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
4616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4617 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
4618 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4619 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
4620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4621 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
4622 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4623 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
4624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4625 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
4626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4627 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
4628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4629 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
4630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4631 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
4632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4633 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
4634 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4635 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
4636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4637 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
4638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4639 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
4640 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4641 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
4642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4643 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
4644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4645 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
4646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4647 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
4648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4649 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
4650 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4651 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
4652 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4653 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
4654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4655 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
4656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4657 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
4658 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4659 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
4660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4661 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
4662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4663 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
4664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4665 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
4666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4667 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
4668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4669 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
4670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4671 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
4672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4673 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
4674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4675 0xe9400000, 0xff500000,
4676 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4678 0xe9500000, 0xff500000,
4679 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4681 0xe8600000, 0xff700000,
4682 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4683 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4684 0xe8700000, 0xff700000,
4685 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4687 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
4688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4689 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
4690
4691 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
4692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4693 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
4694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4695 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
4696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4697 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
4698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4699 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
4700
4701 /* These have been 32-bit since the invention of Thumb. */
4702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4703 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
4704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4705 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
4706
4707 /* Fallback. */
4708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4709 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4710 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
4711 };
4712
4713 static const char *const arm_conditional[] =
4714 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
4715 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
4716
4717 static const char *const arm_fp_const[] =
4718 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
4719
4720 static const char *const arm_shift[] =
4721 {"lsl", "lsr", "asr", "ror"};
4722
4723 typedef struct
4724 {
4725 const char *name;
4726 const char *description;
4727 const char *reg_names[16];
4728 }
4729 arm_regname;
4730
4731 static const arm_regname regnames[] =
4732 {
4733 { "reg-names-raw", N_("Select raw register names"),
4734 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
4735 { "reg-names-gcc", N_("Select register names used by GCC"),
4736 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
4737 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
4738 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
4739 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
4740 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
4741 { "reg-names-apcs", N_("Select register names used in the APCS"),
4742 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
4743 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
4744 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
4745 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
4746 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
4747 };
4748
4749 static const char *const iwmmxt_wwnames[] =
4750 {"b", "h", "w", "d"};
4751
4752 static const char *const iwmmxt_wwssnames[] =
4753 {"b", "bus", "bc", "bss",
4754 "h", "hus", "hc", "hss",
4755 "w", "wus", "wc", "wss",
4756 "d", "dus", "dc", "dss"
4757 };
4758
4759 static const char *const iwmmxt_regnames[] =
4760 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
4761 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
4762 };
4763
4764 static const char *const iwmmxt_cregnames[] =
4765 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
4766 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
4767 };
4768
4769 static const char *const vec_condnames[] =
4770 { "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
4771 };
4772
4773 static const char *const mve_predicatenames[] =
4774 { "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
4775 "eee", "ee", "eet", "e", "ett", "et", "ete"
4776 };
4777
4778 /* Names for 2-bit size field for mve vector isntructions. */
4779 static const char *const mve_vec_sizename[] =
4780 { "8", "16", "32", "64"};
4781
4782 /* Indicates whether we are processing a then predicate,
4783 else predicate or none at all. */
4784 enum vpt_pred_state
4785 {
4786 PRED_NONE,
4787 PRED_THEN,
4788 PRED_ELSE
4789 };
4790
4791 /* Information used to process a vpt block and subsequent instructions. */
4792 struct vpt_block
4793 {
4794 /* Are we in a vpt block. */
4795 bfd_boolean in_vpt_block;
4796
4797 /* Next predicate state if in vpt block. */
4798 enum vpt_pred_state next_pred_state;
4799
4800 /* Mask from vpt/vpst instruction. */
4801 long predicate_mask;
4802
4803 /* Instruction number in vpt block. */
4804 long current_insn_num;
4805
4806 /* Number of instructions in vpt block.. */
4807 long num_pred_insn;
4808 };
4809
4810 static struct vpt_block vpt_block_state =
4811 {
4812 FALSE,
4813 PRED_NONE,
4814 0,
4815 0,
4816 0
4817 };
4818
4819 /* Default to GCC register name set. */
4820 static unsigned int regname_selected = 1;
4821
4822 #define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
4823 #define arm_regnames regnames[regname_selected].reg_names
4824
4825 static bfd_boolean force_thumb = FALSE;
4826
4827 /* Current IT instruction state. This contains the same state as the IT
4828 bits in the CPSR. */
4829 static unsigned int ifthen_state;
4830 /* IT state for the next instruction. */
4831 static unsigned int ifthen_next_state;
4832 /* The address of the insn for which the IT state is valid. */
4833 static bfd_vma ifthen_address;
4834 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
4835 /* Indicates that the current Conditional state is unconditional or outside
4836 an IT block. */
4837 #define COND_UNCOND 16
4838
4839 \f
4840 /* Functions. */
4841 /* Extract the predicate mask for a VPT or VPST instruction.
4842 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
4843
4844 static long
4845 mve_extract_pred_mask (long given)
4846 {
4847 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
4848 }
4849
4850 /* Return the number of instructions in a MVE predicate block. */
4851 static long
4852 num_instructions_vpt_block (long given)
4853 {
4854 long mask = mve_extract_pred_mask (given);
4855 if (mask == 0)
4856 return 0;
4857
4858 if (mask == 8)
4859 return 1;
4860
4861 if ((mask & 7) == 4)
4862 return 2;
4863
4864 if ((mask & 3) == 2)
4865 return 3;
4866
4867 if ((mask & 1) == 1)
4868 return 4;
4869
4870 return 0;
4871 }
4872
4873 static void
4874 mark_outside_vpt_block (void)
4875 {
4876 vpt_block_state.in_vpt_block = FALSE;
4877 vpt_block_state.next_pred_state = PRED_NONE;
4878 vpt_block_state.predicate_mask = 0;
4879 vpt_block_state.current_insn_num = 0;
4880 vpt_block_state.num_pred_insn = 0;
4881 }
4882
4883 static void
4884 mark_inside_vpt_block (long given)
4885 {
4886 vpt_block_state.in_vpt_block = TRUE;
4887 vpt_block_state.next_pred_state = PRED_THEN;
4888 vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
4889 vpt_block_state.current_insn_num = 0;
4890 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
4891 assert (vpt_block_state.num_pred_insn >= 1);
4892 }
4893
4894 static enum vpt_pred_state
4895 invert_next_predicate_state (enum vpt_pred_state astate)
4896 {
4897 if (astate == PRED_THEN)
4898 return PRED_ELSE;
4899 else if (astate == PRED_ELSE)
4900 return PRED_THEN;
4901 else
4902 return PRED_NONE;
4903 }
4904
4905 static enum vpt_pred_state
4906 update_next_predicate_state (void)
4907 {
4908 long pred_mask = vpt_block_state.predicate_mask;
4909 long mask_for_insn = 0;
4910
4911 switch (vpt_block_state.current_insn_num)
4912 {
4913 case 1:
4914 mask_for_insn = 8;
4915 break;
4916
4917 case 2:
4918 mask_for_insn = 4;
4919 break;
4920
4921 case 3:
4922 mask_for_insn = 2;
4923 break;
4924
4925 case 4:
4926 return PRED_NONE;
4927 }
4928
4929 if (pred_mask & mask_for_insn)
4930 return invert_next_predicate_state (vpt_block_state.next_pred_state);
4931 else
4932 return vpt_block_state.next_pred_state;
4933 }
4934
4935 static void
4936 update_vpt_block_state (void)
4937 {
4938 vpt_block_state.current_insn_num++;
4939 if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
4940 {
4941 /* No more instructions to process in vpt block. */
4942 mark_outside_vpt_block ();
4943 return;
4944 }
4945
4946 vpt_block_state.next_pred_state = update_next_predicate_state ();
4947 }
4948
4949 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
4950 Returns pointer to following character of the format string and
4951 fills in *VALUEP and *WIDTHP with the extracted value and number of
4952 bits extracted. WIDTHP can be NULL. */
4953
4954 static const char *
4955 arm_decode_bitfield (const char *ptr,
4956 unsigned long insn,
4957 unsigned long *valuep,
4958 int *widthp)
4959 {
4960 unsigned long value = 0;
4961 int width = 0;
4962
4963 do
4964 {
4965 int start, end;
4966 int bits;
4967
4968 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
4969 start = start * 10 + *ptr - '0';
4970 if (*ptr == '-')
4971 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
4972 end = end * 10 + *ptr - '0';
4973 else
4974 end = start;
4975 bits = end - start;
4976 if (bits < 0)
4977 abort ();
4978 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
4979 width += bits + 1;
4980 }
4981 while (*ptr++ == ',');
4982 *valuep = value;
4983 if (widthp)
4984 *widthp = width;
4985 return ptr - 1;
4986 }
4987
4988 static void
4989 arm_decode_shift (long given, fprintf_ftype func, void *stream,
4990 bfd_boolean print_shift)
4991 {
4992 func (stream, "%s", arm_regnames[given & 0xf]);
4993
4994 if ((given & 0xff0) != 0)
4995 {
4996 if ((given & 0x10) == 0)
4997 {
4998 int amount = (given & 0xf80) >> 7;
4999 int shift = (given & 0x60) >> 5;
5000
5001 if (amount == 0)
5002 {
5003 if (shift == 3)
5004 {
5005 func (stream, ", rrx");
5006 return;
5007 }
5008
5009 amount = 32;
5010 }
5011
5012 if (print_shift)
5013 func (stream, ", %s #%d", arm_shift[shift], amount);
5014 else
5015 func (stream, ", #%d", amount);
5016 }
5017 else if ((given & 0x80) == 0x80)
5018 func (stream, "\t; <illegal shifter operand>");
5019 else if (print_shift)
5020 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
5021 arm_regnames[(given & 0xf00) >> 8]);
5022 else
5023 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
5024 }
5025 }
5026
5027 /* Return TRUE if the MATCHED_INSN can be inside an IT block. */
5028
5029 static bfd_boolean
5030 is_mve_okay_in_it (enum mve_instructions matched_insn)
5031 {
5032 switch (matched_insn)
5033 {
5034 case MVE_VMOV_GP_TO_VEC_LANE:
5035 case MVE_VMOV2_VEC_LANE_TO_GP:
5036 case MVE_VMOV2_GP_TO_VEC_LANE:
5037 case MVE_VMOV_VEC_LANE_TO_GP:
5038 return TRUE;
5039 default:
5040 return FALSE;
5041 }
5042 }
5043
5044 static bfd_boolean
5045 is_mve_architecture (struct disassemble_info *info)
5046 {
5047 struct arm_private_data *private_data = info->private_data;
5048 arm_feature_set allowed_arches = private_data->features;
5049
5050 arm_feature_set arm_ext_v8_1m_main
5051 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
5052
5053 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
5054 && !ARM_CPU_IS_ANY (allowed_arches))
5055 return TRUE;
5056 else
5057 return FALSE;
5058 }
5059
5060 static bfd_boolean
5061 is_vpt_instruction (long given)
5062 {
5063
5064 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
5065 if ((given & 0x0040e000) == 0)
5066 return FALSE;
5067
5068 /* VPT floating point T1 variant. */
5069 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
5070 /* VPT floating point T2 variant. */
5071 || ((given & 0xefb10f50) == 0xee310f40)
5072 /* VPT vector T1 variant. */
5073 || ((given & 0xff811f51) == 0xfe010f00)
5074 /* VPT vector T2 variant. */
5075 || ((given & 0xff811f51) == 0xfe010f01
5076 && ((given & 0x300000) != 0x300000))
5077 /* VPT vector T3 variant. */
5078 || ((given & 0xff811f50) == 0xfe011f00)
5079 /* VPT vector T4 variant. */
5080 || ((given & 0xff811f70) == 0xfe010f40)
5081 /* VPT vector T5 variant. */
5082 || ((given & 0xff811f70) == 0xfe010f60)
5083 /* VPT vector T6 variant. */
5084 || ((given & 0xff811f50) == 0xfe011f40)
5085 /* VPST vector T variant. */
5086 || ((given & 0xffbf1fff) == 0xfe310f4d))
5087 return TRUE;
5088 else
5089 return FALSE;
5090 }
5091
5092 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5093 and ending bitfield = END. END must be greater than START. */
5094
5095 static unsigned long
5096 arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
5097 {
5098 int bits = end - start;
5099
5100 if (bits < 0)
5101 abort ();
5102
5103 return ((given >> start) & ((2ul << bits) - 1));
5104 }
5105
5106 /* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5107 START:END and START2:END2. END/END2 must be greater than
5108 START/START2. */
5109
5110 static unsigned long
5111 arm_decode_field_multiple (unsigned long given, unsigned int start,
5112 unsigned int end, unsigned int start2,
5113 unsigned int end2)
5114 {
5115 int bits = end - start;
5116 int bits2 = end2 - start2;
5117 unsigned long value = 0;
5118 int width = 0;
5119
5120 if (bits2 < 0)
5121 abort ();
5122
5123 value = arm_decode_field (given, start, end);
5124 width += bits + 1;
5125
5126 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
5127 return value;
5128 }
5129
5130 /* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5131 This helps us decode instructions that change mnemonic depending on specific
5132 operand values/encodings. */
5133
5134 static bfd_boolean
5135 is_mve_encoding_conflict (unsigned long given,
5136 enum mve_instructions matched_insn)
5137 {
5138 switch (matched_insn)
5139 {
5140 case MVE_VPST:
5141 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5142 return TRUE;
5143 else
5144 return FALSE;
5145
5146 case MVE_VPT_FP_T1:
5147 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5148 return TRUE;
5149 if ((arm_decode_field (given, 12, 12) == 0)
5150 && (arm_decode_field (given, 0, 0) == 1))
5151 return TRUE;
5152 return FALSE;
5153
5154 case MVE_VPT_FP_T2:
5155 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5156 return TRUE;
5157 if (arm_decode_field (given, 0, 3) == 0xd)
5158 return TRUE;
5159 return FALSE;
5160
5161 case MVE_VPT_VEC_T1:
5162 case MVE_VPT_VEC_T2:
5163 case MVE_VPT_VEC_T3:
5164 case MVE_VPT_VEC_T4:
5165 case MVE_VPT_VEC_T5:
5166 case MVE_VPT_VEC_T6:
5167 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5168 return TRUE;
5169 if (arm_decode_field (given, 20, 21) == 3)
5170 return TRUE;
5171 return FALSE;
5172
5173 case MVE_VCMP_FP_T1:
5174 if ((arm_decode_field (given, 12, 12) == 0)
5175 && (arm_decode_field (given, 0, 0) == 1))
5176 return TRUE;
5177 else
5178 return FALSE;
5179
5180 case MVE_VCMP_FP_T2:
5181 if (arm_decode_field (given, 0, 3) == 0xd)
5182 return TRUE;
5183 else
5184 return FALSE;
5185
5186 case MVE_VMLA:
5187 case MVE_VMAX:
5188 case MVE_VMIN:
5189 case MVE_VBRSR:
5190 case MVE_VADD_VEC_T2:
5191 case MVE_VSUB_VEC_T2:
5192 case MVE_VABAV:
5193 case MVE_VQRSHL_T1:
5194 case MVE_VQSHL_T4:
5195 case MVE_VRSHL_T1:
5196 case MVE_VSHL_T3:
5197 case MVE_VCADD_VEC:
5198 case MVE_VHCADD:
5199 case MVE_VDDUP:
5200 case MVE_VIDUP:
5201 case MVE_VQRDMLADH:
5202 case MVE_VQDMLAH:
5203 case MVE_VQRDMLAH:
5204 case MVE_VQDMLASH:
5205 case MVE_VQRDMLASH:
5206 case MVE_VQDMLSDH:
5207 case MVE_VQRDMLSDH:
5208 case MVE_VQDMULH_T3:
5209 case MVE_VQRDMULH_T4:
5210 case MVE_VQDMLADH:
5211 case MVE_VMLAS:
5212 case MVE_VMULL_INT:
5213 case MVE_VHADD_T2:
5214 case MVE_VHSUB_T2:
5215 case MVE_VCMP_VEC_T1:
5216 case MVE_VCMP_VEC_T2:
5217 case MVE_VCMP_VEC_T3:
5218 case MVE_VCMP_VEC_T4:
5219 case MVE_VCMP_VEC_T5:
5220 case MVE_VCMP_VEC_T6:
5221 if (arm_decode_field (given, 20, 21) == 3)
5222 return TRUE;
5223 else
5224 return FALSE;
5225
5226 case MVE_VLD2:
5227 case MVE_VLD4:
5228 case MVE_VST2:
5229 case MVE_VST4:
5230 if (arm_decode_field (given, 7, 8) == 3)
5231 return TRUE;
5232 else
5233 return FALSE;
5234
5235 case MVE_VSTRB_T1:
5236 case MVE_VSTRH_T2:
5237 if ((arm_decode_field (given, 24, 24) == 0)
5238 && (arm_decode_field (given, 21, 21) == 0))
5239 {
5240 return TRUE;
5241 }
5242 else if ((arm_decode_field (given, 7, 8) == 3))
5243 return TRUE;
5244 else
5245 return FALSE;
5246
5247 case MVE_VSTRB_T5:
5248 case MVE_VSTRH_T6:
5249 case MVE_VSTRW_T7:
5250 if ((arm_decode_field (given, 24, 24) == 0)
5251 && (arm_decode_field (given, 21, 21) == 0))
5252 {
5253 return TRUE;
5254 }
5255 else
5256 return FALSE;
5257
5258 case MVE_VCVT_FP_FIX_VEC:
5259 return (arm_decode_field (given, 16, 21) & 0x38) == 0;
5260
5261 case MVE_VBIC_IMM:
5262 case MVE_VORR_IMM:
5263 {
5264 unsigned long cmode = arm_decode_field (given, 8, 11);
5265
5266 if ((cmode & 1) == 0)
5267 return TRUE;
5268 else if ((cmode & 0xc) == 0xc)
5269 return TRUE;
5270 else
5271 return FALSE;
5272 }
5273
5274 case MVE_VMVN_IMM:
5275 {
5276 unsigned long cmode = arm_decode_field (given, 8, 11);
5277
5278 if ((cmode & 9) == 1)
5279 return TRUE;
5280 else if ((cmode & 5) == 1)
5281 return TRUE;
5282 else if ((cmode & 0xe) == 0xe)
5283 return TRUE;
5284 else
5285 return FALSE;
5286 }
5287
5288 case MVE_VMOV_IMM_TO_VEC:
5289 if ((arm_decode_field (given, 5, 5) == 1)
5290 && (arm_decode_field (given, 8, 11) != 0xe))
5291 return TRUE;
5292 else
5293 return FALSE;
5294
5295 case MVE_VMOVL:
5296 {
5297 unsigned long size = arm_decode_field (given, 19, 20);
5298 if ((size == 0) || (size == 3))
5299 return TRUE;
5300 else
5301 return FALSE;
5302 }
5303
5304 case MVE_VMAXA:
5305 case MVE_VMINA:
5306 case MVE_VMAXV:
5307 case MVE_VMAXAV:
5308 case MVE_VMINV:
5309 case MVE_VMINAV:
5310 case MVE_VQRSHL_T2:
5311 case MVE_VQSHL_T1:
5312 case MVE_VRSHL_T2:
5313 case MVE_VSHL_T2:
5314 case MVE_VSHLL_T2:
5315 case MVE_VADDV:
5316 case MVE_VMOVN:
5317 case MVE_VQMOVUN:
5318 case MVE_VQMOVN:
5319 if (arm_decode_field (given, 18, 19) == 3)
5320 return TRUE;
5321 else
5322 return FALSE;
5323
5324 case MVE_VMLSLDAV:
5325 case MVE_VRMLSLDAVH:
5326 case MVE_VMLALDAV:
5327 case MVE_VADDLV:
5328 if (arm_decode_field (given, 20, 22) == 7)
5329 return TRUE;
5330 else
5331 return FALSE;
5332
5333 case MVE_VRMLALDAVH:
5334 if ((arm_decode_field (given, 20, 22) & 6) == 6)
5335 return TRUE;
5336 else
5337 return FALSE;
5338
5339 case MVE_VDWDUP:
5340 case MVE_VIWDUP:
5341 if ((arm_decode_field (given, 20, 21) == 3)
5342 || (arm_decode_field (given, 1, 3) == 7))
5343 return TRUE;
5344 else
5345 return FALSE;
5346
5347
5348 case MVE_VSHLL_T1:
5349 if (arm_decode_field (given, 16, 18) == 0)
5350 {
5351 unsigned long sz = arm_decode_field (given, 19, 20);
5352
5353 if ((sz == 1) || (sz == 2))
5354 return TRUE;
5355 else
5356 return FALSE;
5357 }
5358 else
5359 return FALSE;
5360
5361 case MVE_VQSHL_T2:
5362 case MVE_VQSHLU_T3:
5363 case MVE_VRSHR:
5364 case MVE_VSHL_T1:
5365 case MVE_VSHR:
5366 case MVE_VSLI:
5367 case MVE_VSRI:
5368 if (arm_decode_field (given, 19, 21) == 0)
5369 return TRUE;
5370 else
5371 return FALSE;
5372
5373 case MVE_VCTP:
5374 if (arm_decode_field (given, 16, 19) == 0xf)
5375 return TRUE;
5376 else
5377 return FALSE;
5378
5379 default:
5380 case MVE_VADD_FP_T1:
5381 case MVE_VADD_FP_T2:
5382 case MVE_VADD_VEC_T1:
5383 return FALSE;
5384
5385 }
5386 }
5387
5388 static void
5389 print_mve_vld_str_addr (struct disassemble_info *info,
5390 unsigned long given,
5391 enum mve_instructions matched_insn)
5392 {
5393 void *stream = info->stream;
5394 fprintf_ftype func = info->fprintf_func;
5395
5396 unsigned long p, w, gpr, imm, add, mod_imm;
5397
5398 imm = arm_decode_field (given, 0, 6);
5399 mod_imm = imm;
5400
5401 switch (matched_insn)
5402 {
5403 case MVE_VLDRB_T1:
5404 case MVE_VSTRB_T1:
5405 gpr = arm_decode_field (given, 16, 18);
5406 break;
5407
5408 case MVE_VLDRH_T2:
5409 case MVE_VSTRH_T2:
5410 gpr = arm_decode_field (given, 16, 18);
5411 mod_imm = imm << 1;
5412 break;
5413
5414 case MVE_VLDRH_T6:
5415 case MVE_VSTRH_T6:
5416 gpr = arm_decode_field (given, 16, 19);
5417 mod_imm = imm << 1;
5418 break;
5419
5420 case MVE_VLDRW_T7:
5421 case MVE_VSTRW_T7:
5422 gpr = arm_decode_field (given, 16, 19);
5423 mod_imm = imm << 2;
5424 break;
5425
5426 case MVE_VLDRB_T5:
5427 case MVE_VSTRB_T5:
5428 gpr = arm_decode_field (given, 16, 19);
5429 break;
5430
5431 default:
5432 return;
5433 }
5434
5435 p = arm_decode_field (given, 24, 24);
5436 w = arm_decode_field (given, 21, 21);
5437
5438 add = arm_decode_field (given, 23, 23);
5439
5440 char * add_sub;
5441
5442 /* Don't print anything for '+' as it is implied. */
5443 if (add == 1)
5444 add_sub = "";
5445 else
5446 add_sub = "-";
5447
5448 if (p == 1)
5449 {
5450 /* Offset mode. */
5451 if (w == 0)
5452 func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm);
5453 /* Pre-indexed mode. */
5454 else
5455 func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm);
5456 }
5457 else if ((p == 0) && (w == 1))
5458 /* Post-index mode. */
5459 func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm);
5460 }
5461
5462 /* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5463 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5464 this encoding is undefined. */
5465
5466 static bfd_boolean
5467 is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
5468 enum mve_undefined *undefined_code)
5469 {
5470 *undefined_code = UNDEF_NONE;
5471
5472 switch (matched_insn)
5473 {
5474 case MVE_VDUP:
5475 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
5476 {
5477 *undefined_code = UNDEF_SIZE_3;
5478 return TRUE;
5479 }
5480 else
5481 return FALSE;
5482
5483 case MVE_VABD_VEC:
5484 case MVE_VADD_VEC_T1:
5485 case MVE_VSUB_VEC_T1:
5486 case MVE_VQDMULH_T1:
5487 case MVE_VQRDMULH_T2:
5488 case MVE_VRHADD:
5489 case MVE_VHADD_T1:
5490 case MVE_VHSUB_T1:
5491 if (arm_decode_field (given, 20, 21) == 3)
5492 {
5493 *undefined_code = UNDEF_SIZE_3;
5494 return TRUE;
5495 }
5496 else
5497 return FALSE;
5498
5499 case MVE_VLDRB_T1:
5500 if (arm_decode_field (given, 7, 8) == 3)
5501 {
5502 *undefined_code = UNDEF_SIZE_3;
5503 return TRUE;
5504 }
5505 else
5506 return FALSE;
5507
5508 case MVE_VLDRH_T2:
5509 if (arm_decode_field (given, 7, 8) <= 1)
5510 {
5511 *undefined_code = UNDEF_SIZE_LE_1;
5512 return TRUE;
5513 }
5514 else
5515 return FALSE;
5516
5517 case MVE_VSTRB_T1:
5518 if ((arm_decode_field (given, 7, 8) == 0))
5519 {
5520 *undefined_code = UNDEF_SIZE_0;
5521 return TRUE;
5522 }
5523 else
5524 return FALSE;
5525
5526 case MVE_VSTRH_T2:
5527 if ((arm_decode_field (given, 7, 8) <= 1))
5528 {
5529 *undefined_code = UNDEF_SIZE_LE_1;
5530 return TRUE;
5531 }
5532 else
5533 return FALSE;
5534
5535 case MVE_VLDRB_GATHER_T1:
5536 if (arm_decode_field (given, 7, 8) == 3)
5537 {
5538 *undefined_code = UNDEF_SIZE_3;
5539 return TRUE;
5540 }
5541 else if ((arm_decode_field (given, 28, 28) == 0)
5542 && (arm_decode_field (given, 7, 8) == 0))
5543 {
5544 *undefined_code = UNDEF_NOT_UNS_SIZE_0;
5545 return TRUE;
5546 }
5547 else
5548 return FALSE;
5549
5550 case MVE_VLDRH_GATHER_T2:
5551 if (arm_decode_field (given, 7, 8) == 3)
5552 {
5553 *undefined_code = UNDEF_SIZE_3;
5554 return TRUE;
5555 }
5556 else if ((arm_decode_field (given, 28, 28) == 0)
5557 && (arm_decode_field (given, 7, 8) == 1))
5558 {
5559 *undefined_code = UNDEF_NOT_UNS_SIZE_1;
5560 return TRUE;
5561 }
5562 else if (arm_decode_field (given, 7, 8) == 0)
5563 {
5564 *undefined_code = UNDEF_SIZE_0;
5565 return TRUE;
5566 }
5567 else
5568 return FALSE;
5569
5570 case MVE_VLDRW_GATHER_T3:
5571 if (arm_decode_field (given, 7, 8) != 2)
5572 {
5573 *undefined_code = UNDEF_SIZE_NOT_2;
5574 return TRUE;
5575 }
5576 else if (arm_decode_field (given, 28, 28) == 0)
5577 {
5578 *undefined_code = UNDEF_NOT_UNSIGNED;
5579 return TRUE;
5580 }
5581 else
5582 return FALSE;
5583
5584 case MVE_VLDRD_GATHER_T4:
5585 if (arm_decode_field (given, 7, 8) != 3)
5586 {
5587 *undefined_code = UNDEF_SIZE_NOT_3;
5588 return TRUE;
5589 }
5590 else if (arm_decode_field (given, 28, 28) == 0)
5591 {
5592 *undefined_code = UNDEF_NOT_UNSIGNED;
5593 return TRUE;
5594 }
5595 else
5596 return FALSE;
5597
5598 case MVE_VSTRB_SCATTER_T1:
5599 if (arm_decode_field (given, 7, 8) == 3)
5600 {
5601 *undefined_code = UNDEF_SIZE_3;
5602 return TRUE;
5603 }
5604 else
5605 return FALSE;
5606
5607 case MVE_VSTRH_SCATTER_T2:
5608 {
5609 unsigned long size = arm_decode_field (given, 7, 8);
5610 if (size == 3)
5611 {
5612 *undefined_code = UNDEF_SIZE_3;
5613 return TRUE;
5614 }
5615 else if (size == 0)
5616 {
5617 *undefined_code = UNDEF_SIZE_0;
5618 return TRUE;
5619 }
5620 else
5621 return FALSE;
5622 }
5623
5624 case MVE_VSTRW_SCATTER_T3:
5625 if (arm_decode_field (given, 7, 8) != 2)
5626 {
5627 *undefined_code = UNDEF_SIZE_NOT_2;
5628 return TRUE;
5629 }
5630 else
5631 return FALSE;
5632
5633 case MVE_VSTRD_SCATTER_T4:
5634 if (arm_decode_field (given, 7, 8) != 3)
5635 {
5636 *undefined_code = UNDEF_SIZE_NOT_3;
5637 return TRUE;
5638 }
5639 else
5640 return FALSE;
5641
5642 case MVE_VCVT_FP_FIX_VEC:
5643 {
5644 unsigned long imm6 = arm_decode_field (given, 16, 21);
5645 if ((imm6 & 0x20) == 0)
5646 {
5647 *undefined_code = UNDEF_VCVT_IMM6;
5648 return TRUE;
5649 }
5650
5651 if ((arm_decode_field (given, 9, 9) == 0)
5652 && ((imm6 & 0x30) == 0x20))
5653 {
5654 *undefined_code = UNDEF_VCVT_FSI_IMM6;
5655 return TRUE;
5656 }
5657
5658 return FALSE;
5659 }
5660
5661 case MVE_VABS_FP:
5662 case MVE_VCVT_BETWEEN_FP_INT:
5663 case MVE_VCVT_FROM_FP_TO_INT:
5664 {
5665 unsigned long size = arm_decode_field (given, 18, 19);
5666 if (size == 0)
5667 {
5668 *undefined_code = UNDEF_SIZE_0;
5669 return TRUE;
5670 }
5671 else if (size == 3)
5672 {
5673 *undefined_code = UNDEF_SIZE_3;
5674 return TRUE;
5675 }
5676 else
5677 return FALSE;
5678 }
5679
5680 case MVE_VMOV_VEC_LANE_TO_GP:
5681 {
5682 unsigned long op1 = arm_decode_field (given, 21, 22);
5683 unsigned long op2 = arm_decode_field (given, 5, 6);
5684 unsigned long u = arm_decode_field (given, 23, 23);
5685
5686 if ((op2 == 0) && (u == 1))
5687 {
5688 if ((op1 == 0) || (op1 == 1))
5689 {
5690 *undefined_code = UNDEF_BAD_U_OP1_OP2;
5691 return TRUE;
5692 }
5693 else
5694 return FALSE;
5695 }
5696 else if (op2 == 2)
5697 {
5698 if ((op1 == 0) || (op1 == 1))
5699 {
5700 *undefined_code = UNDEF_BAD_OP1_OP2;
5701 return TRUE;
5702 }
5703 else
5704 return FALSE;
5705 }
5706
5707 return FALSE;
5708 }
5709
5710 case MVE_VMOV_GP_TO_VEC_LANE:
5711 if (arm_decode_field (given, 5, 6) == 2)
5712 {
5713 unsigned long op1 = arm_decode_field (given, 21, 22);
5714 if ((op1 == 0) || (op1 == 1))
5715 {
5716 *undefined_code = UNDEF_BAD_OP1_OP2;
5717 return TRUE;
5718 }
5719 else
5720 return FALSE;
5721 }
5722 else
5723 return FALSE;
5724
5725 case MVE_VMOV_IMM_TO_VEC:
5726 if (arm_decode_field (given, 5, 5) == 0)
5727 {
5728 unsigned long cmode = arm_decode_field (given, 8, 11);
5729
5730 if (((cmode & 9) == 1) || ((cmode & 5) == 1))
5731 {
5732 *undefined_code = UNDEF_OP_0_BAD_CMODE;
5733 return TRUE;
5734 }
5735 else
5736 return FALSE;
5737 }
5738 else
5739 return FALSE;
5740
5741 case MVE_VSHLL_T2:
5742 case MVE_VMOVN:
5743 if (arm_decode_field (given, 18, 19) == 2)
5744 {
5745 *undefined_code = UNDEF_SIZE_2;
5746 return TRUE;
5747 }
5748 else
5749 return FALSE;
5750
5751 case MVE_VRMLALDAVH:
5752 case MVE_VMLADAV_T1:
5753 case MVE_VMLADAV_T2:
5754 case MVE_VMLALDAV:
5755 if ((arm_decode_field (given, 28, 28) == 1)
5756 && (arm_decode_field (given, 12, 12) == 1))
5757 {
5758 *undefined_code = UNDEF_XCHG_UNS;
5759 return TRUE;
5760 }
5761 else
5762 return FALSE;
5763
5764 case MVE_VQSHRN:
5765 case MVE_VQSHRUN:
5766 case MVE_VSHLL_T1:
5767 case MVE_VSHRN:
5768 {
5769 unsigned long sz = arm_decode_field (given, 19, 20);
5770 if (sz == 1)
5771 return FALSE;
5772 else if ((sz & 2) == 2)
5773 return FALSE;
5774 else
5775 {
5776 *undefined_code = UNDEF_SIZE;
5777 return TRUE;
5778 }
5779 }
5780 break;
5781
5782 case MVE_VQSHL_T2:
5783 case MVE_VQSHLU_T3:
5784 case MVE_VRSHR:
5785 case MVE_VSHL_T1:
5786 case MVE_VSHR:
5787 case MVE_VSLI:
5788 case MVE_VSRI:
5789 {
5790 unsigned long sz = arm_decode_field (given, 19, 21);
5791 if ((sz & 7) == 1)
5792 return FALSE;
5793 else if ((sz & 6) == 2)
5794 return FALSE;
5795 else if ((sz & 4) == 4)
5796 return FALSE;
5797 else
5798 {
5799 *undefined_code = UNDEF_SIZE;
5800 return TRUE;
5801 }
5802 }
5803
5804 case MVE_VQRSHRN:
5805 case MVE_VQRSHRUN:
5806 if (arm_decode_field (given, 19, 20) == 0)
5807 {
5808 *undefined_code = UNDEF_SIZE_0;
5809 return TRUE;
5810 }
5811 else
5812 return FALSE;
5813
5814 case MVE_VABS_VEC:
5815 if (arm_decode_field (given, 18, 19) == 3)
5816 {
5817 *undefined_code = UNDEF_SIZE_3;
5818 return TRUE;
5819 }
5820 else
5821 return FALSE;
5822
5823 case MVE_VCLS:
5824 case MVE_VCLZ:
5825 if (arm_decode_field (given, 18, 19) == 3)
5826 {
5827 *undefined_code = UNDEF_SIZE_3;
5828 return TRUE;
5829 }
5830 else
5831 return FALSE;
5832
5833 default:
5834 return FALSE;
5835 }
5836 }
5837
5838 /* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
5839 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
5840 why this encoding is unpredictable. */
5841
5842 static bfd_boolean
5843 is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
5844 enum mve_unpredictable *unpredictable_code)
5845 {
5846 *unpredictable_code = UNPRED_NONE;
5847
5848 switch (matched_insn)
5849 {
5850 case MVE_VCMP_FP_T2:
5851 case MVE_VPT_FP_T2:
5852 if ((arm_decode_field (given, 12, 12) == 0)
5853 && (arm_decode_field (given, 5, 5) == 1))
5854 {
5855 *unpredictable_code = UNPRED_FCA_0_FCB_1;
5856 return TRUE;
5857 }
5858 else
5859 return FALSE;
5860
5861 case MVE_VPT_VEC_T4:
5862 case MVE_VPT_VEC_T5:
5863 case MVE_VPT_VEC_T6:
5864 case MVE_VCMP_VEC_T4:
5865 case MVE_VCMP_VEC_T5:
5866 case MVE_VCMP_VEC_T6:
5867 if (arm_decode_field (given, 0, 3) == 0xd)
5868 {
5869 *unpredictable_code = UNPRED_R13;
5870 return TRUE;
5871 }
5872 else
5873 return FALSE;
5874
5875 case MVE_VDUP:
5876 {
5877 unsigned long gpr = arm_decode_field (given, 12, 15);
5878 if (gpr == 0xd)
5879 {
5880 *unpredictable_code = UNPRED_R13;
5881 return TRUE;
5882 }
5883 else if (gpr == 0xf)
5884 {
5885 *unpredictable_code = UNPRED_R15;
5886 return TRUE;
5887 }
5888
5889 return FALSE;
5890 }
5891
5892 case MVE_VMLA:
5893 case MVE_VBRSR:
5894 case MVE_VADD_FP_T2:
5895 case MVE_VSUB_FP_T2:
5896 case MVE_VADD_VEC_T2:
5897 case MVE_VSUB_VEC_T2:
5898 case MVE_VQRSHL_T2:
5899 case MVE_VQSHL_T1:
5900 case MVE_VRSHL_T2:
5901 case MVE_VSHL_T2:
5902 case MVE_VSHLC:
5903 case MVE_VQDMLAH:
5904 case MVE_VQRDMLAH:
5905 case MVE_VQDMLASH:
5906 case MVE_VQRDMLASH:
5907 case MVE_VQDMULH_T3:
5908 case MVE_VQRDMULH_T4:
5909 case MVE_VMLAS:
5910 case MVE_VFMA_FP_SCALAR:
5911 case MVE_VFMAS_FP_SCALAR:
5912 case MVE_VHADD_T2:
5913 case MVE_VHSUB_T2:
5914 {
5915 unsigned long gpr = arm_decode_field (given, 0, 3);
5916 if (gpr == 0xd)
5917 {
5918 *unpredictable_code = UNPRED_R13;
5919 return TRUE;
5920 }
5921 else if (gpr == 0xf)
5922 {
5923 *unpredictable_code = UNPRED_R15;
5924 return TRUE;
5925 }
5926
5927 return FALSE;
5928 }
5929
5930 case MVE_VLD2:
5931 case MVE_VST2:
5932 {
5933 unsigned long rn = arm_decode_field (given, 16, 19);
5934
5935 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
5936 {
5937 *unpredictable_code = UNPRED_R13_AND_WB;
5938 return TRUE;
5939 }
5940
5941 if (rn == 0xf)
5942 {
5943 *unpredictable_code = UNPRED_R15;
5944 return TRUE;
5945 }
5946
5947 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
5948 {
5949 *unpredictable_code = UNPRED_Q_GT_6;
5950 return TRUE;
5951 }
5952 else
5953 return FALSE;
5954 }
5955
5956 case MVE_VLD4:
5957 case MVE_VST4:
5958 {
5959 unsigned long rn = arm_decode_field (given, 16, 19);
5960
5961 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
5962 {
5963 *unpredictable_code = UNPRED_R13_AND_WB;
5964 return TRUE;
5965 }
5966
5967 if (rn == 0xf)
5968 {
5969 *unpredictable_code = UNPRED_R15;
5970 return TRUE;
5971 }
5972
5973 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
5974 {
5975 *unpredictable_code = UNPRED_Q_GT_4;
5976 return TRUE;
5977 }
5978 else
5979 return FALSE;
5980 }
5981
5982 case MVE_VLDRB_T5:
5983 case MVE_VLDRH_T6:
5984 case MVE_VLDRW_T7:
5985 case MVE_VSTRB_T5:
5986 case MVE_VSTRH_T6:
5987 case MVE_VSTRW_T7:
5988 {
5989 unsigned long rn = arm_decode_field (given, 16, 19);
5990
5991 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
5992 {
5993 *unpredictable_code = UNPRED_R13_AND_WB;
5994 return TRUE;
5995 }
5996 else if (rn == 0xf)
5997 {
5998 *unpredictable_code = UNPRED_R15;
5999 return TRUE;
6000 }
6001 else
6002 return FALSE;
6003 }
6004
6005 case MVE_VLDRB_GATHER_T1:
6006 if (arm_decode_field (given, 0, 0) == 1)
6007 {
6008 *unpredictable_code = UNPRED_OS;
6009 return TRUE;
6010 }
6011
6012 /* fall through. */
6013 /* To handle common code with T2-T4 variants. */
6014 case MVE_VLDRH_GATHER_T2:
6015 case MVE_VLDRW_GATHER_T3:
6016 case MVE_VLDRD_GATHER_T4:
6017 {
6018 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6019 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6020
6021 if (qd == qm)
6022 {
6023 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6024 return TRUE;
6025 }
6026
6027 if (arm_decode_field (given, 16, 19) == 0xf)
6028 {
6029 *unpredictable_code = UNPRED_R15;
6030 return TRUE;
6031 }
6032
6033 return FALSE;
6034 }
6035
6036 case MVE_VLDRW_GATHER_T5:
6037 case MVE_VLDRD_GATHER_T6:
6038 {
6039 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6040 unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
6041
6042 if (qd == qm)
6043 {
6044 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6045 return TRUE;
6046 }
6047 else
6048 return FALSE;
6049 }
6050
6051 case MVE_VSTRB_SCATTER_T1:
6052 if (arm_decode_field (given, 16, 19) == 0xf)
6053 {
6054 *unpredictable_code = UNPRED_R15;
6055 return TRUE;
6056 }
6057 else if (arm_decode_field (given, 0, 0) == 1)
6058 {
6059 *unpredictable_code = UNPRED_OS;
6060 return TRUE;
6061 }
6062 else
6063 return FALSE;
6064
6065 case MVE_VSTRH_SCATTER_T2:
6066 case MVE_VSTRW_SCATTER_T3:
6067 case MVE_VSTRD_SCATTER_T4:
6068 if (arm_decode_field (given, 16, 19) == 0xf)
6069 {
6070 *unpredictable_code = UNPRED_R15;
6071 return TRUE;
6072 }
6073 else
6074 return FALSE;
6075
6076 case MVE_VMOV2_VEC_LANE_TO_GP:
6077 case MVE_VMOV2_GP_TO_VEC_LANE:
6078 case MVE_VCVT_BETWEEN_FP_INT:
6079 case MVE_VCVT_FROM_FP_TO_INT:
6080 {
6081 unsigned long rt = arm_decode_field (given, 0, 3);
6082 unsigned long rt2 = arm_decode_field (given, 16, 19);
6083
6084 if ((rt == 0xd) || (rt2 == 0xd))
6085 {
6086 *unpredictable_code = UNPRED_R13;
6087 return TRUE;
6088 }
6089 else if ((rt == 0xf) || (rt2 == 0xf))
6090 {
6091 *unpredictable_code = UNPRED_R15;
6092 return TRUE;
6093 }
6094 else if (rt == rt2)
6095 {
6096 *unpredictable_code = UNPRED_GP_REGS_EQUAL;
6097 return TRUE;
6098 }
6099
6100 return FALSE;
6101 }
6102
6103 case MVE_VMAXV:
6104 case MVE_VMAXAV:
6105 case MVE_VMAXNMV_FP:
6106 case MVE_VMAXNMAV_FP:
6107 case MVE_VMINNMV_FP:
6108 case MVE_VMINNMAV_FP:
6109 case MVE_VMINV:
6110 case MVE_VMINAV:
6111 case MVE_VABAV:
6112 case MVE_VMOV_HFP_TO_GP:
6113 case MVE_VMOV_GP_TO_VEC_LANE:
6114 case MVE_VMOV_VEC_LANE_TO_GP:
6115 {
6116 unsigned long rda = arm_decode_field (given, 12, 15);
6117 if (rda == 0xd)
6118 {
6119 *unpredictable_code = UNPRED_R13;
6120 return TRUE;
6121 }
6122 else if (rda == 0xf)
6123 {
6124 *unpredictable_code = UNPRED_R15;
6125 return TRUE;
6126 }
6127
6128 return FALSE;
6129 }
6130
6131 case MVE_VQRDMLADH:
6132 case MVE_VQDMLSDH:
6133 case MVE_VQRDMLSDH:
6134 case MVE_VQDMLADH:
6135 case MVE_VMULL_INT:
6136 {
6137 unsigned long Qd;
6138 unsigned long Qm;
6139 unsigned long Qn;
6140
6141 if (arm_decode_field (given, 20, 21) == 2)
6142 {
6143 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6144 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6145 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6146
6147 if ((Qd == Qn) || (Qd == Qm))
6148 {
6149 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6150 return TRUE;
6151 }
6152 else
6153 return FALSE;
6154 }
6155 else
6156 return FALSE;
6157 }
6158
6159 case MVE_VCMUL_FP:
6160 case MVE_VQDMULL_T1:
6161 {
6162 unsigned long Qd;
6163 unsigned long Qm;
6164 unsigned long Qn;
6165
6166 if (arm_decode_field (given, 28, 28) == 1)
6167 {
6168 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6169 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6170 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6171
6172 if ((Qd == Qn) || (Qd == Qm))
6173 {
6174 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6175 return TRUE;
6176 }
6177 else
6178 return FALSE;
6179 }
6180 else
6181 return FALSE;
6182 }
6183
6184 case MVE_VQDMULL_T2:
6185 {
6186 unsigned long gpr = arm_decode_field (given, 0, 3);
6187 if (gpr == 0xd)
6188 {
6189 *unpredictable_code = UNPRED_R13;
6190 return TRUE;
6191 }
6192 else if (gpr == 0xf)
6193 {
6194 *unpredictable_code = UNPRED_R15;
6195 return TRUE;
6196 }
6197
6198 if (arm_decode_field (given, 28, 28) == 1)
6199 {
6200 unsigned long Qd
6201 = arm_decode_field_multiple (given, 13, 15, 22, 22);
6202 unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6203
6204 if ((Qd == Qn))
6205 {
6206 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6207 return TRUE;
6208 }
6209 else
6210 return FALSE;
6211 }
6212
6213 return FALSE;
6214 }
6215
6216 case MVE_VMLSLDAV:
6217 case MVE_VRMLSLDAVH:
6218 case MVE_VMLALDAV:
6219 case MVE_VADDLV:
6220 if (arm_decode_field (given, 20, 22) == 6)
6221 {
6222 *unpredictable_code = UNPRED_R13;
6223 return TRUE;
6224 }
6225 else
6226 return FALSE;
6227
6228 case MVE_VDWDUP:
6229 case MVE_VIWDUP:
6230 if (arm_decode_field (given, 1, 3) == 6)
6231 {
6232 *unpredictable_code = UNPRED_R13;
6233 return TRUE;
6234 }
6235 else
6236 return FALSE;
6237
6238 case MVE_VCADD_VEC:
6239 case MVE_VHCADD:
6240 {
6241 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6242 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6243 if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
6244 {
6245 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6246 return TRUE;
6247 }
6248 else
6249 return FALSE;
6250 }
6251
6252 case MVE_VCADD_FP:
6253 {
6254 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6255 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6256 if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
6257 {
6258 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6259 return TRUE;
6260 }
6261 else
6262 return FALSE;
6263 }
6264
6265 case MVE_VCMLA_FP:
6266 {
6267 unsigned long Qda;
6268 unsigned long Qm;
6269 unsigned long Qn;
6270
6271 if (arm_decode_field (given, 20, 20) == 1)
6272 {
6273 Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
6274 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6275 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6276
6277 if ((Qda == Qn) || (Qda == Qm))
6278 {
6279 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6280 return TRUE;
6281 }
6282 else
6283 return FALSE;
6284 }
6285 else
6286 return FALSE;
6287
6288 }
6289
6290 case MVE_VCTP:
6291 if (arm_decode_field (given, 16, 19) == 0xd)
6292 {
6293 *unpredictable_code = UNPRED_R13;
6294 return TRUE;
6295 }
6296 else
6297 return FALSE;
6298
6299 default:
6300 return FALSE;
6301 }
6302 }
6303
6304 static void
6305 print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
6306 {
6307 unsigned long op1 = arm_decode_field (given, 21, 22);
6308 unsigned long op2 = arm_decode_field (given, 5, 6);
6309 unsigned long h = arm_decode_field (given, 16, 16);
6310 unsigned long index, esize, targetBeat, idx;
6311 void *stream = info->stream;
6312 fprintf_ftype func = info->fprintf_func;
6313
6314 if ((op1 & 0x2) == 0x2)
6315 {
6316 index = op2;
6317 esize = 8;
6318 }
6319 else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
6320 {
6321 index = op2 >> 1;
6322 esize = 16;
6323 }
6324 else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
6325 {
6326 index = 0;
6327 esize = 32;
6328 }
6329 else
6330 {
6331 func (stream, "<undefined index>");
6332 return;
6333 }
6334
6335 targetBeat = (op1 & 0x1) | (h << 1);
6336 idx = index + targetBeat * (32/esize);
6337
6338 func (stream, "%lu", idx);
6339 }
6340
6341 /* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6342 in length and integer of floating-point type. */
6343 static void
6344 print_simd_imm8 (struct disassemble_info *info, unsigned long given,
6345 unsigned int ibit_loc, const struct mopcode32 *insn)
6346 {
6347 int bits = 0;
6348 int cmode = (given >> 8) & 0xf;
6349 int op = (given >> 5) & 0x1;
6350 unsigned long value = 0, hival = 0;
6351 unsigned shift;
6352 int size = 0;
6353 int isfloat = 0;
6354 void *stream = info->stream;
6355 fprintf_ftype func = info->fprintf_func;
6356
6357 /* On Neon the 'i' bit is at bit 24, on mve it is
6358 at bit 28. */
6359 bits |= ((given >> ibit_loc) & 1) << 7;
6360 bits |= ((given >> 16) & 7) << 4;
6361 bits |= ((given >> 0) & 15) << 0;
6362
6363 if (cmode < 8)
6364 {
6365 shift = (cmode >> 1) & 3;
6366 value = (unsigned long) bits << (8 * shift);
6367 size = 32;
6368 }
6369 else if (cmode < 12)
6370 {
6371 shift = (cmode >> 1) & 1;
6372 value = (unsigned long) bits << (8 * shift);
6373 size = 16;
6374 }
6375 else if (cmode < 14)
6376 {
6377 shift = (cmode & 1) + 1;
6378 value = (unsigned long) bits << (8 * shift);
6379 value |= (1ul << (8 * shift)) - 1;
6380 size = 32;
6381 }
6382 else if (cmode == 14)
6383 {
6384 if (op)
6385 {
6386 /* Bit replication into bytes. */
6387 int ix;
6388 unsigned long mask;
6389
6390 value = 0;
6391 hival = 0;
6392 for (ix = 7; ix >= 0; ix--)
6393 {
6394 mask = ((bits >> ix) & 1) ? 0xff : 0;
6395 if (ix <= 3)
6396 value = (value << 8) | mask;
6397 else
6398 hival = (hival << 8) | mask;
6399 }
6400 size = 64;
6401 }
6402 else
6403 {
6404 /* Byte replication. */
6405 value = (unsigned long) bits;
6406 size = 8;
6407 }
6408 }
6409 else if (!op)
6410 {
6411 /* Floating point encoding. */
6412 int tmp;
6413
6414 value = (unsigned long) (bits & 0x7f) << 19;
6415 value |= (unsigned long) (bits & 0x80) << 24;
6416 tmp = bits & 0x40 ? 0x3c : 0x40;
6417 value |= (unsigned long) tmp << 24;
6418 size = 32;
6419 isfloat = 1;
6420 }
6421 else
6422 {
6423 func (stream, "<illegal constant %.8x:%x:%x>",
6424 bits, cmode, op);
6425 size = 32;
6426 return;
6427 }
6428
6429 // printU determines whether the immediate value should be printed as
6430 // unsigned.
6431 unsigned printU = 0;
6432 switch (insn->mve_op)
6433 {
6434 default:
6435 break;
6436 // We want this for instructions that don't have a 'signed' type
6437 case MVE_VBIC_IMM:
6438 case MVE_VORR_IMM:
6439 case MVE_VMVN_IMM:
6440 case MVE_VMOV_IMM_TO_VEC:
6441 printU = 1;
6442 break;
6443 }
6444 switch (size)
6445 {
6446 case 8:
6447 func (stream, "#%ld\t; 0x%.2lx", value, value);
6448 break;
6449
6450 case 16:
6451 func (stream,
6452 printU
6453 ? "#%lu\t; 0x%.4lx"
6454 : "#%ld\t; 0x%.4lx", value, value);
6455 break;
6456
6457 case 32:
6458 if (isfloat)
6459 {
6460 unsigned char valbytes[4];
6461 double fvalue;
6462
6463 /* Do this a byte at a time so we don't have to
6464 worry about the host's endianness. */
6465 valbytes[0] = value & 0xff;
6466 valbytes[1] = (value >> 8) & 0xff;
6467 valbytes[2] = (value >> 16) & 0xff;
6468 valbytes[3] = (value >> 24) & 0xff;
6469
6470 floatformat_to_double
6471 (& floatformat_ieee_single_little, valbytes,
6472 & fvalue);
6473
6474 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
6475 value);
6476 }
6477 else
6478 func (stream,
6479 printU
6480 ? "#%lu\t; 0x%.8lx"
6481 : "#%ld\t; 0x%.8lx",
6482 (long) (((value & 0x80000000L) != 0)
6483 && !printU
6484 ? value | ~0xffffffffL : value),
6485 value);
6486 break;
6487
6488 case 64:
6489 func (stream, "#0x%.8lx%.8lx", hival, value);
6490 break;
6491
6492 default:
6493 abort ();
6494 }
6495
6496 }
6497
6498 static void
6499 print_mve_undefined (struct disassemble_info *info,
6500 enum mve_undefined undefined_code)
6501 {
6502 void *stream = info->stream;
6503 fprintf_ftype func = info->fprintf_func;
6504
6505 func (stream, "\t\tundefined instruction: ");
6506
6507 switch (undefined_code)
6508 {
6509 case UNDEF_SIZE:
6510 func (stream, "illegal size");
6511 break;
6512
6513 case UNDEF_SIZE_0:
6514 func (stream, "size equals zero");
6515 break;
6516
6517 case UNDEF_SIZE_2:
6518 func (stream, "size equals two");
6519 break;
6520
6521 case UNDEF_SIZE_3:
6522 func (stream, "size equals three");
6523 break;
6524
6525 case UNDEF_SIZE_LE_1:
6526 func (stream, "size <= 1");
6527 break;
6528
6529 case UNDEF_SIZE_NOT_2:
6530 func (stream, "size not equal to 2");
6531 break;
6532
6533 case UNDEF_SIZE_NOT_3:
6534 func (stream, "size not equal to 3");
6535 break;
6536
6537 case UNDEF_NOT_UNS_SIZE_0:
6538 func (stream, "not unsigned and size = zero");
6539 break;
6540
6541 case UNDEF_NOT_UNS_SIZE_1:
6542 func (stream, "not unsigned and size = one");
6543 break;
6544
6545 case UNDEF_NOT_UNSIGNED:
6546 func (stream, "not unsigned");
6547 break;
6548
6549 case UNDEF_VCVT_IMM6:
6550 func (stream, "invalid imm6");
6551 break;
6552
6553 case UNDEF_VCVT_FSI_IMM6:
6554 func (stream, "fsi = 0 and invalid imm6");
6555 break;
6556
6557 case UNDEF_BAD_OP1_OP2:
6558 func (stream, "bad size with op2 = 2 and op1 = 0 or 1");
6559 break;
6560
6561 case UNDEF_BAD_U_OP1_OP2:
6562 func (stream, "unsigned with op2 = 0 and op1 = 0 or 1");
6563 break;
6564
6565 case UNDEF_OP_0_BAD_CMODE:
6566 func (stream, "op field equal 0 and bad cmode");
6567 break;
6568
6569 case UNDEF_XCHG_UNS:
6570 func (stream, "exchange and unsigned together");
6571 break;
6572
6573 case UNDEF_NONE:
6574 break;
6575 }
6576
6577 }
6578
6579 static void
6580 print_mve_unpredictable (struct disassemble_info *info,
6581 enum mve_unpredictable unpredict_code)
6582 {
6583 void *stream = info->stream;
6584 fprintf_ftype func = info->fprintf_func;
6585
6586 func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
6587
6588 switch (unpredict_code)
6589 {
6590 case UNPRED_IT_BLOCK:
6591 func (stream, "mve instruction in it block");
6592 break;
6593
6594 case UNPRED_FCA_0_FCB_1:
6595 func (stream, "condition bits, fca = 0 and fcb = 1");
6596 break;
6597
6598 case UNPRED_R13:
6599 func (stream, "use of r13 (sp)");
6600 break;
6601
6602 case UNPRED_R15:
6603 func (stream, "use of r15 (pc)");
6604 break;
6605
6606 case UNPRED_Q_GT_4:
6607 func (stream, "start register block > r4");
6608 break;
6609
6610 case UNPRED_Q_GT_6:
6611 func (stream, "start register block > r6");
6612 break;
6613
6614 case UNPRED_R13_AND_WB:
6615 func (stream, "use of r13 and write back");
6616 break;
6617
6618 case UNPRED_Q_REGS_EQUAL:
6619 func (stream,
6620 "same vector register used for destination and other operand");
6621 break;
6622
6623 case UNPRED_OS:
6624 func (stream, "use of offset scaled");
6625 break;
6626
6627 case UNPRED_GP_REGS_EQUAL:
6628 func (stream, "same general-purpose register used for both operands");
6629 break;
6630
6631 case UNPRED_Q_REGS_EQ_AND_SIZE_1:
6632 func (stream, "use of identical q registers and size = 1");
6633 break;
6634
6635 case UNPRED_Q_REGS_EQ_AND_SIZE_2:
6636 func (stream, "use of identical q registers and size = 1");
6637 break;
6638
6639 case UNPRED_NONE:
6640 break;
6641 }
6642 }
6643
6644 /* Print register block operand for mve vld2/vld4/vst2/vld4. */
6645
6646 static void
6647 print_mve_register_blocks (struct disassemble_info *info,
6648 unsigned long given,
6649 enum mve_instructions matched_insn)
6650 {
6651 void *stream = info->stream;
6652 fprintf_ftype func = info->fprintf_func;
6653
6654 unsigned long q_reg_start = arm_decode_field_multiple (given,
6655 13, 15,
6656 22, 22);
6657 switch (matched_insn)
6658 {
6659 case MVE_VLD2:
6660 case MVE_VST2:
6661 if (q_reg_start <= 6)
6662 func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1);
6663 else
6664 func (stream, "<illegal reg q%ld>", q_reg_start);
6665 break;
6666
6667 case MVE_VLD4:
6668 case MVE_VST4:
6669 if (q_reg_start <= 4)
6670 func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start,
6671 q_reg_start + 1, q_reg_start + 2,
6672 q_reg_start + 3);
6673 else
6674 func (stream, "<illegal reg q%ld>", q_reg_start);
6675 break;
6676
6677 default:
6678 break;
6679 }
6680 }
6681
6682 static void
6683 print_mve_rounding_mode (struct disassemble_info *info,
6684 unsigned long given,
6685 enum mve_instructions matched_insn)
6686 {
6687 void *stream = info->stream;
6688 fprintf_ftype func = info->fprintf_func;
6689
6690 switch (matched_insn)
6691 {
6692 case MVE_VCVT_FROM_FP_TO_INT:
6693 {
6694 switch (arm_decode_field (given, 8, 9))
6695 {
6696 case 0:
6697 func (stream, "a");
6698 break;
6699
6700 case 1:
6701 func (stream, "n");
6702 break;
6703
6704 case 2:
6705 func (stream, "p");
6706 break;
6707
6708 case 3:
6709 func (stream, "m");
6710 break;
6711
6712 default:
6713 break;
6714 }
6715 }
6716 break;
6717
6718 case MVE_VRINT_FP:
6719 {
6720 switch (arm_decode_field (given, 7, 9))
6721 {
6722 case 0:
6723 func (stream, "n");
6724 break;
6725
6726 case 1:
6727 func (stream, "x");
6728 break;
6729
6730 case 2:
6731 func (stream, "a");
6732 break;
6733
6734 case 3:
6735 func (stream, "z");
6736 break;
6737
6738 case 5:
6739 func (stream, "m");
6740 break;
6741
6742 case 7:
6743 func (stream, "p");
6744
6745 case 4:
6746 case 6:
6747 default:
6748 break;
6749 }
6750 }
6751 break;
6752
6753 default:
6754 break;
6755 }
6756 }
6757
6758 static void
6759 print_mve_vcvt_size (struct disassemble_info *info,
6760 unsigned long given,
6761 enum mve_instructions matched_insn)
6762 {
6763 unsigned long mode = 0;
6764 void *stream = info->stream;
6765 fprintf_ftype func = info->fprintf_func;
6766
6767 switch (matched_insn)
6768 {
6769 case MVE_VCVT_FP_FIX_VEC:
6770 {
6771 mode = (((given & 0x200) >> 7)
6772 | ((given & 0x10000000) >> 27)
6773 | ((given & 0x100) >> 8));
6774
6775 switch (mode)
6776 {
6777 case 0:
6778 func (stream, "f16.s16");
6779 break;
6780
6781 case 1:
6782 func (stream, "s16.f16");
6783 break;
6784
6785 case 2:
6786 func (stream, "f16.u16");
6787 break;
6788
6789 case 3:
6790 func (stream, "u16.f16");
6791 break;
6792
6793 case 4:
6794 func (stream, "f32.s32");
6795 break;
6796
6797 case 5:
6798 func (stream, "s32.f32");
6799 break;
6800
6801 case 6:
6802 func (stream, "f32.u32");
6803 break;
6804
6805 case 7:
6806 func (stream, "u32.f32");
6807 break;
6808
6809 default:
6810 break;
6811 }
6812 break;
6813 }
6814 case MVE_VCVT_BETWEEN_FP_INT:
6815 {
6816 unsigned long size = arm_decode_field (given, 18, 19);
6817 unsigned long op = arm_decode_field (given, 7, 8);
6818
6819 if (size == 1)
6820 {
6821 switch (op)
6822 {
6823 case 0:
6824 func (stream, "f16.s16");
6825 break;
6826
6827 case 1:
6828 func (stream, "f16.u16");
6829 break;
6830
6831 case 2:
6832 func (stream, "s16.f16");
6833 break;
6834
6835 case 3:
6836 func (stream, "u16.f16");
6837 break;
6838
6839 default:
6840 break;
6841 }
6842 }
6843 else if (size == 2)
6844 {
6845 switch (op)
6846 {
6847 case 0:
6848 func (stream, "f32.s32");
6849 break;
6850
6851 case 1:
6852 func (stream, "f32.u32");
6853 break;
6854
6855 case 2:
6856 func (stream, "s32.f32");
6857 break;
6858
6859 case 3:
6860 func (stream, "u32.f32");
6861 break;
6862 }
6863 }
6864 }
6865 break;
6866
6867 case MVE_VCVT_FP_HALF_FP:
6868 {
6869 unsigned long op = arm_decode_field (given, 28, 28);
6870 if (op == 0)
6871 func (stream, "f16.f32");
6872 else if (op == 1)
6873 func (stream, "f32.f16");
6874 }
6875 break;
6876
6877 case MVE_VCVT_FROM_FP_TO_INT:
6878 {
6879 unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
6880
6881 switch (size)
6882 {
6883 case 2:
6884 func (stream, "s16.f16");
6885 break;
6886
6887 case 3:
6888 func (stream, "u16.f16");
6889 break;
6890
6891 case 4:
6892 func (stream, "s32.f32");
6893 break;
6894
6895 case 5:
6896 func (stream, "u32.f32");
6897 break;
6898
6899 default:
6900 break;
6901 }
6902 }
6903 break;
6904
6905 default:
6906 break;
6907 }
6908 }
6909
6910 static void
6911 print_mve_rotate (struct disassemble_info *info, unsigned long rot,
6912 unsigned long rot_width)
6913 {
6914 void *stream = info->stream;
6915 fprintf_ftype func = info->fprintf_func;
6916
6917 if (rot_width == 1)
6918 {
6919 switch (rot)
6920 {
6921 case 0:
6922 func (stream, "90");
6923 break;
6924 case 1:
6925 func (stream, "270");
6926 break;
6927 default:
6928 break;
6929 }
6930 }
6931 else if (rot_width == 2)
6932 {
6933 switch (rot)
6934 {
6935 case 0:
6936 func (stream, "0");
6937 break;
6938 case 1:
6939 func (stream, "90");
6940 break;
6941 case 2:
6942 func (stream, "180");
6943 break;
6944 case 3:
6945 func (stream, "270");
6946 break;
6947 default:
6948 break;
6949 }
6950 }
6951 }
6952
6953 static void
6954 print_instruction_predicate (struct disassemble_info *info)
6955 {
6956 void *stream = info->stream;
6957 fprintf_ftype func = info->fprintf_func;
6958
6959 if (vpt_block_state.next_pred_state == PRED_THEN)
6960 func (stream, "t");
6961 else if (vpt_block_state.next_pred_state == PRED_ELSE)
6962 func (stream, "e");
6963 }
6964
6965 static void
6966 print_mve_size (struct disassemble_info *info,
6967 unsigned long size,
6968 enum mve_instructions matched_insn)
6969 {
6970 void *stream = info->stream;
6971 fprintf_ftype func = info->fprintf_func;
6972
6973 switch (matched_insn)
6974 {
6975 case MVE_VABAV:
6976 case MVE_VABD_VEC:
6977 case MVE_VABS_FP:
6978 case MVE_VABS_VEC:
6979 case MVE_VADD_VEC_T1:
6980 case MVE_VADD_VEC_T2:
6981 case MVE_VADDV:
6982 case MVE_VBRSR:
6983 case MVE_VCADD_VEC:
6984 case MVE_VCLS:
6985 case MVE_VCLZ:
6986 case MVE_VCMP_VEC_T1:
6987 case MVE_VCMP_VEC_T2:
6988 case MVE_VCMP_VEC_T3:
6989 case MVE_VCMP_VEC_T4:
6990 case MVE_VCMP_VEC_T5:
6991 case MVE_VCMP_VEC_T6:
6992 case MVE_VCTP:
6993 case MVE_VDDUP:
6994 case MVE_VDWDUP:
6995 case MVE_VHADD_T1:
6996 case MVE_VHADD_T2:
6997 case MVE_VHCADD:
6998 case MVE_VHSUB_T1:
6999 case MVE_VHSUB_T2:
7000 case MVE_VIDUP:
7001 case MVE_VIWDUP:
7002 case MVE_VLD2:
7003 case MVE_VLD4:
7004 case MVE_VLDRB_GATHER_T1:
7005 case MVE_VLDRH_GATHER_T2:
7006 case MVE_VLDRW_GATHER_T3:
7007 case MVE_VLDRD_GATHER_T4:
7008 case MVE_VLDRB_T1:
7009 case MVE_VLDRH_T2:
7010 case MVE_VMAX:
7011 case MVE_VMAXA:
7012 case MVE_VMAXV:
7013 case MVE_VMAXAV:
7014 case MVE_VMIN:
7015 case MVE_VMINA:
7016 case MVE_VMINV:
7017 case MVE_VMINAV:
7018 case MVE_VMLA:
7019 case MVE_VMLAS:
7020 case MVE_VPT_VEC_T1:
7021 case MVE_VPT_VEC_T2:
7022 case MVE_VPT_VEC_T3:
7023 case MVE_VPT_VEC_T4:
7024 case MVE_VPT_VEC_T5:
7025 case MVE_VPT_VEC_T6:
7026 case MVE_VQDMLADH:
7027 case MVE_VQRDMLADH:
7028 case MVE_VQDMLAH:
7029 case MVE_VQRDMLAH:
7030 case MVE_VQDMLASH:
7031 case MVE_VQRDMLASH:
7032 case MVE_VQDMLSDH:
7033 case MVE_VQRDMLSDH:
7034 case MVE_VQDMULH_T1:
7035 case MVE_VQRDMULH_T2:
7036 case MVE_VQDMULH_T3:
7037 case MVE_VQRDMULH_T4:
7038 case MVE_VQRSHL_T1:
7039 case MVE_VQRSHL_T2:
7040 case MVE_VQSHL_T1:
7041 case MVE_VQSHL_T4:
7042 case MVE_VRHADD:
7043 case MVE_VRINT_FP:
7044 case MVE_VRSHL_T1:
7045 case MVE_VRSHL_T2:
7046 case MVE_VSHL_T2:
7047 case MVE_VSHL_T3:
7048 case MVE_VSHLL_T2:
7049 case MVE_VST2:
7050 case MVE_VST4:
7051 case MVE_VSTRB_SCATTER_T1:
7052 case MVE_VSTRH_SCATTER_T2:
7053 case MVE_VSTRW_SCATTER_T3:
7054 case MVE_VSTRB_T1:
7055 case MVE_VSTRH_T2:
7056 case MVE_VSUB_VEC_T1:
7057 case MVE_VSUB_VEC_T2:
7058 if (size <= 3)
7059 func (stream, "%s", mve_vec_sizename[size]);
7060 else
7061 func (stream, "<undef size>");
7062 break;
7063
7064 case MVE_VABD_FP:
7065 case MVE_VADD_FP_T1:
7066 case MVE_VADD_FP_T2:
7067 case MVE_VSUB_FP_T1:
7068 case MVE_VSUB_FP_T2:
7069 case MVE_VCMP_FP_T1:
7070 case MVE_VCMP_FP_T2:
7071 case MVE_VFMA_FP_SCALAR:
7072 case MVE_VFMA_FP:
7073 case MVE_VFMS_FP:
7074 case MVE_VFMAS_FP_SCALAR:
7075 case MVE_VMAXNM_FP:
7076 case MVE_VMAXNMA_FP:
7077 case MVE_VMAXNMV_FP:
7078 case MVE_VMAXNMAV_FP:
7079 case MVE_VMINNM_FP:
7080 case MVE_VMINNMA_FP:
7081 case MVE_VMINNMV_FP:
7082 case MVE_VMINNMAV_FP:
7083 case MVE_VPT_FP_T1:
7084 case MVE_VPT_FP_T2:
7085 if (size == 0)
7086 func (stream, "32");
7087 else if (size == 1)
7088 func (stream, "16");
7089 break;
7090
7091 case MVE_VCADD_FP:
7092 case MVE_VCMLA_FP:
7093 case MVE_VCMUL_FP:
7094 case MVE_VMLADAV_T1:
7095 case MVE_VMLALDAV:
7096 case MVE_VMLSDAV_T1:
7097 case MVE_VMLSLDAV:
7098 case MVE_VMOVN:
7099 case MVE_VQDMULL_T1:
7100 case MVE_VQDMULL_T2:
7101 case MVE_VQMOVN:
7102 case MVE_VQMOVUN:
7103 if (size == 0)
7104 func (stream, "16");
7105 else if (size == 1)
7106 func (stream, "32");
7107 break;
7108
7109 case MVE_VMOVL:
7110 if (size == 1)
7111 func (stream, "8");
7112 else if (size == 2)
7113 func (stream, "16");
7114 break;
7115
7116 case MVE_VDUP:
7117 switch (size)
7118 {
7119 case 0:
7120 func (stream, "32");
7121 break;
7122 case 1:
7123 func (stream, "16");
7124 break;
7125 case 2:
7126 func (stream, "8");
7127 break;
7128 default:
7129 break;
7130 }
7131 break;
7132
7133 case MVE_VMOV_GP_TO_VEC_LANE:
7134 case MVE_VMOV_VEC_LANE_TO_GP:
7135 switch (size)
7136 {
7137 case 0: case 4:
7138 func (stream, "32");
7139 break;
7140
7141 case 1: case 3:
7142 case 5: case 7:
7143 func (stream, "16");
7144 break;
7145
7146 case 8: case 9: case 10: case 11:
7147 case 12: case 13: case 14: case 15:
7148 func (stream, "8");
7149 break;
7150
7151 default:
7152 break;
7153 }
7154 break;
7155
7156 case MVE_VMOV_IMM_TO_VEC:
7157 switch (size)
7158 {
7159 case 0: case 4: case 8:
7160 case 12: case 24: case 26:
7161 func (stream, "i32");
7162 break;
7163 case 16: case 20:
7164 func (stream, "i16");
7165 break;
7166 case 28:
7167 func (stream, "i8");
7168 break;
7169 case 29:
7170 func (stream, "i64");
7171 break;
7172 case 30:
7173 func (stream, "f32");
7174 break;
7175 default:
7176 break;
7177 }
7178 break;
7179
7180 case MVE_VMULL_POLY:
7181 if (size == 0)
7182 func (stream, "p8");
7183 else if (size == 1)
7184 func (stream, "p16");
7185 break;
7186
7187 case MVE_VMVN_IMM:
7188 switch (size)
7189 {
7190 case 0: case 2: case 4:
7191 case 6: case 12: case 13:
7192 func (stream, "32");
7193 break;
7194
7195 case 8: case 10:
7196 func (stream, "16");
7197 break;
7198
7199 default:
7200 break;
7201 }
7202 break;
7203
7204 case MVE_VBIC_IMM:
7205 case MVE_VORR_IMM:
7206 switch (size)
7207 {
7208 case 1: case 3:
7209 case 5: case 7:
7210 func (stream, "32");
7211 break;
7212
7213 case 9: case 11:
7214 func (stream, "16");
7215 break;
7216
7217 default:
7218 break;
7219 }
7220 break;
7221
7222 case MVE_VQSHRN:
7223 case MVE_VQSHRUN:
7224 case MVE_VQRSHRN:
7225 case MVE_VQRSHRUN:
7226 case MVE_VRSHRN:
7227 case MVE_VSHRN:
7228 {
7229 switch (size)
7230 {
7231 case 1:
7232 func (stream, "16");
7233 break;
7234
7235 case 2: case 3:
7236 func (stream, "32");
7237 break;
7238
7239 default:
7240 break;
7241 }
7242 }
7243 break;
7244
7245 case MVE_VQSHL_T2:
7246 case MVE_VQSHLU_T3:
7247 case MVE_VRSHR:
7248 case MVE_VSHL_T1:
7249 case MVE_VSHLL_T1:
7250 case MVE_VSHR:
7251 case MVE_VSLI:
7252 case MVE_VSRI:
7253 {
7254 switch (size)
7255 {
7256 case 1:
7257 func (stream, "8");
7258 break;
7259
7260 case 2: case 3:
7261 func (stream, "16");
7262 break;
7263
7264 case 4: case 5: case 6: case 7:
7265 func (stream, "32");
7266 break;
7267
7268 default:
7269 break;
7270 }
7271 }
7272 break;
7273
7274 default:
7275 break;
7276 }
7277 }
7278
7279 static void
7280 print_mve_shift_n (struct disassemble_info *info, long given,
7281 enum mve_instructions matched_insn)
7282 {
7283 void *stream = info->stream;
7284 fprintf_ftype func = info->fprintf_func;
7285
7286 int startAt0
7287 = matched_insn == MVE_VQSHL_T2
7288 || matched_insn == MVE_VQSHLU_T3
7289 || matched_insn == MVE_VSHL_T1
7290 || matched_insn == MVE_VSHLL_T1
7291 || matched_insn == MVE_VSLI;
7292
7293 unsigned imm6 = (given & 0x3f0000) >> 16;
7294
7295 if (matched_insn == MVE_VSHLL_T1)
7296 imm6 &= 0x1f;
7297
7298 unsigned shiftAmount = 0;
7299 if ((imm6 & 0x20) != 0)
7300 shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6;
7301 else if ((imm6 & 0x10) != 0)
7302 shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6;
7303 else if ((imm6 & 0x08) != 0)
7304 shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6;
7305 else
7306 print_mve_undefined (info, UNDEF_SIZE_0);
7307
7308 func (stream, "%u", shiftAmount);
7309 }
7310
7311 static void
7312 print_vec_condition (struct disassemble_info *info, long given,
7313 enum mve_instructions matched_insn)
7314 {
7315 void *stream = info->stream;
7316 fprintf_ftype func = info->fprintf_func;
7317 long vec_cond = 0;
7318
7319 switch (matched_insn)
7320 {
7321 case MVE_VPT_FP_T1:
7322 case MVE_VCMP_FP_T1:
7323 vec_cond = (((given & 0x1000) >> 10)
7324 | ((given & 1) << 1)
7325 | ((given & 0x0080) >> 7));
7326 func (stream, "%s",vec_condnames[vec_cond]);
7327 break;
7328
7329 case MVE_VPT_FP_T2:
7330 case MVE_VCMP_FP_T2:
7331 vec_cond = (((given & 0x1000) >> 10)
7332 | ((given & 0x0020) >> 4)
7333 | ((given & 0x0080) >> 7));
7334 func (stream, "%s",vec_condnames[vec_cond]);
7335 break;
7336
7337 case MVE_VPT_VEC_T1:
7338 case MVE_VCMP_VEC_T1:
7339 vec_cond = (given & 0x0080) >> 7;
7340 func (stream, "%s",vec_condnames[vec_cond]);
7341 break;
7342
7343 case MVE_VPT_VEC_T2:
7344 case MVE_VCMP_VEC_T2:
7345 vec_cond = 2 | ((given & 0x0080) >> 7);
7346 func (stream, "%s",vec_condnames[vec_cond]);
7347 break;
7348
7349 case MVE_VPT_VEC_T3:
7350 case MVE_VCMP_VEC_T3:
7351 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
7352 func (stream, "%s",vec_condnames[vec_cond]);
7353 break;
7354
7355 case MVE_VPT_VEC_T4:
7356 case MVE_VCMP_VEC_T4:
7357 vec_cond = (given & 0x0080) >> 7;
7358 func (stream, "%s",vec_condnames[vec_cond]);
7359 break;
7360
7361 case MVE_VPT_VEC_T5:
7362 case MVE_VCMP_VEC_T5:
7363 vec_cond = 2 | ((given & 0x0080) >> 7);
7364 func (stream, "%s",vec_condnames[vec_cond]);
7365 break;
7366
7367 case MVE_VPT_VEC_T6:
7368 case MVE_VCMP_VEC_T6:
7369 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
7370 func (stream, "%s",vec_condnames[vec_cond]);
7371 break;
7372
7373 case MVE_NONE:
7374 case MVE_VPST:
7375 default:
7376 break;
7377 }
7378 }
7379
7380 #define W_BIT 21
7381 #define I_BIT 22
7382 #define U_BIT 23
7383 #define P_BIT 24
7384
7385 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
7386 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
7387 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
7388 #define PRE_BIT_SET (given & (1 << P_BIT))
7389
7390
7391 /* Print one coprocessor instruction on INFO->STREAM.
7392 Return TRUE if the instuction matched, FALSE if this is not a
7393 recognised coprocessor instruction. */
7394
7395 static bfd_boolean
7396 print_insn_coprocessor (bfd_vma pc,
7397 struct disassemble_info *info,
7398 long given,
7399 bfd_boolean thumb)
7400 {
7401 const struct sopcode32 *insn;
7402 void *stream = info->stream;
7403 fprintf_ftype func = info->fprintf_func;
7404 unsigned long mask;
7405 unsigned long value = 0;
7406 int cond;
7407 int cp_num;
7408 struct arm_private_data *private_data = info->private_data;
7409 arm_feature_set allowed_arches = ARM_ARCH_NONE;
7410 arm_feature_set arm_ext_v8_1m_main =
7411 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
7412
7413 allowed_arches = private_data->features;
7414
7415 for (insn = coprocessor_opcodes; insn->assembler; insn++)
7416 {
7417 unsigned long u_reg = 16;
7418 bfd_boolean is_unpredictable = FALSE;
7419 signed long value_in_comment = 0;
7420 const char *c;
7421
7422 if (ARM_FEATURE_ZERO (insn->arch))
7423 switch (insn->value)
7424 {
7425 case SENTINEL_IWMMXT_START:
7426 if (info->mach != bfd_mach_arm_XScale
7427 && info->mach != bfd_mach_arm_iWMMXt
7428 && info->mach != bfd_mach_arm_iWMMXt2)
7429 do
7430 insn++;
7431 while ((! ARM_FEATURE_ZERO (insn->arch))
7432 && insn->value != SENTINEL_IWMMXT_END);
7433 continue;
7434
7435 case SENTINEL_IWMMXT_END:
7436 continue;
7437
7438 case SENTINEL_GENERIC_START:
7439 allowed_arches = private_data->features;
7440 continue;
7441
7442 default:
7443 abort ();
7444 }
7445
7446 mask = insn->mask;
7447 value = insn->value;
7448 cp_num = (given >> 8) & 0xf;
7449
7450 if (thumb)
7451 {
7452 /* The high 4 bits are 0xe for Arm conditional instructions, and
7453 0xe for arm unconditional instructions. The rest of the
7454 encoding is the same. */
7455 mask |= 0xf0000000;
7456 value |= 0xe0000000;
7457 if (ifthen_state)
7458 cond = IFTHEN_COND;
7459 else
7460 cond = COND_UNCOND;
7461 }
7462 else
7463 {
7464 /* Only match unconditional instuctions against unconditional
7465 patterns. */
7466 if ((given & 0xf0000000) == 0xf0000000)
7467 {
7468 mask |= 0xf0000000;
7469 cond = COND_UNCOND;
7470 }
7471 else
7472 {
7473 cond = (given >> 28) & 0xf;
7474 if (cond == 0xe)
7475 cond = COND_UNCOND;
7476 }
7477 }
7478
7479 if ((insn->isa == T32 && !thumb)
7480 || (insn->isa == ARM && thumb))
7481 continue;
7482
7483 if ((given & mask) != value)
7484 continue;
7485
7486 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
7487 continue;
7488
7489 if (insn->value == 0xfe000010 /* mcr2 */
7490 || insn->value == 0xfe100010 /* mrc2 */
7491 || insn->value == 0xfc100000 /* ldc2 */
7492 || insn->value == 0xfc000000) /* stc2 */
7493 {
7494 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
7495 is_unpredictable = TRUE;
7496
7497 /* Armv8.1-M Mainline FP & MVE instructions. */
7498 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
7499 && !ARM_CPU_IS_ANY (allowed_arches)
7500 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
7501 continue;
7502
7503 }
7504 else if (insn->value == 0x0e000000 /* cdp */
7505 || insn->value == 0xfe000000 /* cdp2 */
7506 || insn->value == 0x0e000010 /* mcr */
7507 || insn->value == 0x0e100010 /* mrc */
7508 || insn->value == 0x0c100000 /* ldc */
7509 || insn->value == 0x0c000000) /* stc */
7510 {
7511 /* Floating-point instructions. */
7512 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
7513 continue;
7514
7515 /* Armv8.1-M Mainline FP & MVE instructions. */
7516 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
7517 && !ARM_CPU_IS_ANY (allowed_arches)
7518 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
7519 continue;
7520 }
7521 else if ((insn->value == 0xec100f80 /* vldr (system register) */
7522 || insn->value == 0xec000f80) /* vstr (system register) */
7523 && arm_decode_field (given, 24, 24) == 0
7524 && arm_decode_field (given, 21, 21) == 0)
7525 /* If the P and W bits are both 0 then these encodings match the MVE
7526 VLDR and VSTR instructions, these are in a different table, so we
7527 don't let it match here. */
7528 continue;
7529
7530 for (c = insn->assembler; *c; c++)
7531 {
7532 if (*c == '%')
7533 {
7534 const char mod = *++c;
7535 switch (mod)
7536 {
7537 case '%':
7538 func (stream, "%%");
7539 break;
7540
7541 case 'A':
7542 case 'K':
7543 {
7544 int rn = (given >> 16) & 0xf;
7545 bfd_vma offset = given & 0xff;
7546
7547 if (mod == 'K')
7548 offset = given & 0x7f;
7549
7550 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
7551
7552 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
7553 {
7554 /* Not unindexed. The offset is scaled. */
7555 if (cp_num == 9)
7556 /* vldr.16/vstr.16 will shift the address
7557 left by 1 bit only. */
7558 offset = offset * 2;
7559 else
7560 offset = offset * 4;
7561
7562 if (NEGATIVE_BIT_SET)
7563 offset = - offset;
7564 if (rn != 15)
7565 value_in_comment = offset;
7566 }
7567
7568 if (PRE_BIT_SET)
7569 {
7570 if (offset)
7571 func (stream, ", #%d]%s",
7572 (int) offset,
7573 WRITEBACK_BIT_SET ? "!" : "");
7574 else if (NEGATIVE_BIT_SET)
7575 func (stream, ", #-0]");
7576 else
7577 func (stream, "]");
7578 }
7579 else
7580 {
7581 func (stream, "]");
7582
7583 if (WRITEBACK_BIT_SET)
7584 {
7585 if (offset)
7586 func (stream, ", #%d", (int) offset);
7587 else if (NEGATIVE_BIT_SET)
7588 func (stream, ", #-0");
7589 }
7590 else
7591 {
7592 func (stream, ", {%s%d}",
7593 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
7594 (int) offset);
7595 value_in_comment = offset;
7596 }
7597 }
7598 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
7599 {
7600 func (stream, "\t; ");
7601 /* For unaligned PCs, apply off-by-alignment
7602 correction. */
7603 info->print_address_func (offset + pc
7604 + info->bytes_per_chunk * 2
7605 - (pc & 3),
7606 info);
7607 }
7608 }
7609 break;
7610
7611 case 'B':
7612 {
7613 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
7614 int offset = (given >> 1) & 0x3f;
7615
7616 if (offset == 1)
7617 func (stream, "{d%d}", regno);
7618 else if (regno + offset > 32)
7619 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
7620 else
7621 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
7622 }
7623 break;
7624
7625 case 'C':
7626 {
7627 bfd_boolean single = ((given >> 8) & 1) == 0;
7628 char reg_prefix = single ? 's' : 'd';
7629 int Dreg = (given >> 22) & 0x1;
7630 int Vdreg = (given >> 12) & 0xf;
7631 int reg = single ? ((Vdreg << 1) | Dreg)
7632 : ((Dreg << 4) | Vdreg);
7633 int num = (given >> (single ? 0 : 1)) & 0x7f;
7634 int maxreg = single ? 31 : 15;
7635 int topreg = reg + num - 1;
7636
7637 if (!num)
7638 func (stream, "{VPR}");
7639 else if (num == 1)
7640 func (stream, "{%c%d, VPR}", reg_prefix, reg);
7641 else if (topreg > maxreg)
7642 func (stream, "{%c%d-<overflow reg d%d, VPR}",
7643 reg_prefix, reg, single ? topreg >> 1 : topreg);
7644 else
7645 func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
7646 reg_prefix, topreg);
7647 }
7648 break;
7649
7650 case 'u':
7651 if (cond != COND_UNCOND)
7652 is_unpredictable = TRUE;
7653
7654 /* Fall through. */
7655 case 'c':
7656 if (cond != COND_UNCOND && cp_num == 9)
7657 is_unpredictable = TRUE;
7658
7659 func (stream, "%s", arm_conditional[cond]);
7660 break;
7661
7662 case 'I':
7663 /* Print a Cirrus/DSP shift immediate. */
7664 /* Immediates are 7bit signed ints with bits 0..3 in
7665 bits 0..3 of opcode and bits 4..6 in bits 5..7
7666 of opcode. */
7667 {
7668 int imm;
7669
7670 imm = (given & 0xf) | ((given & 0xe0) >> 1);
7671
7672 /* Is ``imm'' a negative number? */
7673 if (imm & 0x40)
7674 imm -= 0x80;
7675
7676 func (stream, "%d", imm);
7677 }
7678
7679 break;
7680
7681 case 'J':
7682 {
7683 unsigned long regno
7684 = arm_decode_field_multiple (given, 13, 15, 22, 22);
7685
7686 switch (regno)
7687 {
7688 case 0x1:
7689 func (stream, "FPSCR");
7690 break;
7691 case 0x2:
7692 func (stream, "FPSCR_nzcvqc");
7693 break;
7694 case 0xc:
7695 func (stream, "VPR");
7696 break;
7697 case 0xd:
7698 func (stream, "P0");
7699 break;
7700 case 0xe:
7701 func (stream, "FPCXTNS");
7702 break;
7703 case 0xf:
7704 func (stream, "FPCXTS");
7705 break;
7706 default:
7707 func (stream, "<invalid reg %lu>", regno);
7708 break;
7709 }
7710 }
7711 break;
7712
7713 case 'F':
7714 switch (given & 0x00408000)
7715 {
7716 case 0:
7717 func (stream, "4");
7718 break;
7719 case 0x8000:
7720 func (stream, "1");
7721 break;
7722 case 0x00400000:
7723 func (stream, "2");
7724 break;
7725 default:
7726 func (stream, "3");
7727 }
7728 break;
7729
7730 case 'P':
7731 switch (given & 0x00080080)
7732 {
7733 case 0:
7734 func (stream, "s");
7735 break;
7736 case 0x80:
7737 func (stream, "d");
7738 break;
7739 case 0x00080000:
7740 func (stream, "e");
7741 break;
7742 default:
7743 func (stream, _("<illegal precision>"));
7744 break;
7745 }
7746 break;
7747
7748 case 'Q':
7749 switch (given & 0x00408000)
7750 {
7751 case 0:
7752 func (stream, "s");
7753 break;
7754 case 0x8000:
7755 func (stream, "d");
7756 break;
7757 case 0x00400000:
7758 func (stream, "e");
7759 break;
7760 default:
7761 func (stream, "p");
7762 break;
7763 }
7764 break;
7765
7766 case 'R':
7767 switch (given & 0x60)
7768 {
7769 case 0:
7770 break;
7771 case 0x20:
7772 func (stream, "p");
7773 break;
7774 case 0x40:
7775 func (stream, "m");
7776 break;
7777 default:
7778 func (stream, "z");
7779 break;
7780 }
7781 break;
7782
7783 case '0': case '1': case '2': case '3': case '4':
7784 case '5': case '6': case '7': case '8': case '9':
7785 {
7786 int width;
7787
7788 c = arm_decode_bitfield (c, given, &value, &width);
7789
7790 switch (*c)
7791 {
7792 case 'R':
7793 if (value == 15)
7794 is_unpredictable = TRUE;
7795 /* Fall through. */
7796 case 'r':
7797 if (c[1] == 'u')
7798 {
7799 /* Eat the 'u' character. */
7800 ++ c;
7801
7802 if (u_reg == value)
7803 is_unpredictable = TRUE;
7804 u_reg = value;
7805 }
7806 func (stream, "%s", arm_regnames[value]);
7807 break;
7808 case 'V':
7809 if (given & (1 << 6))
7810 goto Q;
7811 /* FALLTHROUGH */
7812 case 'D':
7813 func (stream, "d%ld", value);
7814 break;
7815 case 'Q':
7816 Q:
7817 if (value & 1)
7818 func (stream, "<illegal reg q%ld.5>", value >> 1);
7819 else
7820 func (stream, "q%ld", value >> 1);
7821 break;
7822 case 'd':
7823 func (stream, "%ld", value);
7824 value_in_comment = value;
7825 break;
7826 case 'E':
7827 {
7828 /* Converts immediate 8 bit back to float value. */
7829 unsigned floatVal = (value & 0x80) << 24
7830 | (value & 0x3F) << 19
7831 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
7832
7833 /* Quarter float have a maximum value of 31.0.
7834 Get floating point value multiplied by 1e7.
7835 The maximum value stays in limit of a 32-bit int. */
7836 unsigned decVal =
7837 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
7838 (16 + (value & 0xF));
7839
7840 if (!(decVal % 1000000))
7841 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
7842 floatVal, value & 0x80 ? '-' : ' ',
7843 decVal / 10000000,
7844 decVal % 10000000 / 1000000);
7845 else if (!(decVal % 10000))
7846 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
7847 floatVal, value & 0x80 ? '-' : ' ',
7848 decVal / 10000000,
7849 decVal % 10000000 / 10000);
7850 else
7851 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
7852 floatVal, value & 0x80 ? '-' : ' ',
7853 decVal / 10000000, decVal % 10000000);
7854 break;
7855 }
7856 case 'k':
7857 {
7858 int from = (given & (1 << 7)) ? 32 : 16;
7859 func (stream, "%ld", from - value);
7860 }
7861 break;
7862
7863 case 'f':
7864 if (value > 7)
7865 func (stream, "#%s", arm_fp_const[value & 7]);
7866 else
7867 func (stream, "f%ld", value);
7868 break;
7869
7870 case 'w':
7871 if (width == 2)
7872 func (stream, "%s", iwmmxt_wwnames[value]);
7873 else
7874 func (stream, "%s", iwmmxt_wwssnames[value]);
7875 break;
7876
7877 case 'g':
7878 func (stream, "%s", iwmmxt_regnames[value]);
7879 break;
7880 case 'G':
7881 func (stream, "%s", iwmmxt_cregnames[value]);
7882 break;
7883
7884 case 'x':
7885 func (stream, "0x%lx", (value & 0xffffffffUL));
7886 break;
7887
7888 case 'c':
7889 switch (value)
7890 {
7891 case 0:
7892 func (stream, "eq");
7893 break;
7894
7895 case 1:
7896 func (stream, "vs");
7897 break;
7898
7899 case 2:
7900 func (stream, "ge");
7901 break;
7902
7903 case 3:
7904 func (stream, "gt");
7905 break;
7906
7907 default:
7908 func (stream, "??");
7909 break;
7910 }
7911 break;
7912
7913 case '`':
7914 c++;
7915 if (value == 0)
7916 func (stream, "%c", *c);
7917 break;
7918 case '\'':
7919 c++;
7920 if (value == ((1ul << width) - 1))
7921 func (stream, "%c", *c);
7922 break;
7923 case '?':
7924 func (stream, "%c", c[(1 << width) - (int) value]);
7925 c += 1 << width;
7926 break;
7927 default:
7928 abort ();
7929 }
7930 }
7931 break;
7932
7933 case 'y':
7934 case 'z':
7935 {
7936 int single = *c++ == 'y';
7937 int regno;
7938
7939 switch (*c)
7940 {
7941 case '4': /* Sm pair */
7942 case '0': /* Sm, Dm */
7943 regno = given & 0x0000000f;
7944 if (single)
7945 {
7946 regno <<= 1;
7947 regno += (given >> 5) & 1;
7948 }
7949 else
7950 regno += ((given >> 5) & 1) << 4;
7951 break;
7952
7953 case '1': /* Sd, Dd */
7954 regno = (given >> 12) & 0x0000000f;
7955 if (single)
7956 {
7957 regno <<= 1;
7958 regno += (given >> 22) & 1;
7959 }
7960 else
7961 regno += ((given >> 22) & 1) << 4;
7962 break;
7963
7964 case '2': /* Sn, Dn */
7965 regno = (given >> 16) & 0x0000000f;
7966 if (single)
7967 {
7968 regno <<= 1;
7969 regno += (given >> 7) & 1;
7970 }
7971 else
7972 regno += ((given >> 7) & 1) << 4;
7973 break;
7974
7975 case '3': /* List */
7976 func (stream, "{");
7977 regno = (given >> 12) & 0x0000000f;
7978 if (single)
7979 {
7980 regno <<= 1;
7981 regno += (given >> 22) & 1;
7982 }
7983 else
7984 regno += ((given >> 22) & 1) << 4;
7985 break;
7986
7987 default:
7988 abort ();
7989 }
7990
7991 func (stream, "%c%d", single ? 's' : 'd', regno);
7992
7993 if (*c == '3')
7994 {
7995 int count = given & 0xff;
7996
7997 if (single == 0)
7998 count >>= 1;
7999
8000 if (--count)
8001 {
8002 func (stream, "-%c%d",
8003 single ? 's' : 'd',
8004 regno + count);
8005 }
8006
8007 func (stream, "}");
8008 }
8009 else if (*c == '4')
8010 func (stream, ", %c%d", single ? 's' : 'd',
8011 regno + 1);
8012 }
8013 break;
8014
8015 case 'L':
8016 switch (given & 0x00400100)
8017 {
8018 case 0x00000000: func (stream, "b"); break;
8019 case 0x00400000: func (stream, "h"); break;
8020 case 0x00000100: func (stream, "w"); break;
8021 case 0x00400100: func (stream, "d"); break;
8022 default:
8023 break;
8024 }
8025 break;
8026
8027 case 'Z':
8028 {
8029 /* given (20, 23) | given (0, 3) */
8030 value = ((given >> 16) & 0xf0) | (given & 0xf);
8031 func (stream, "%d", (int) value);
8032 }
8033 break;
8034
8035 case 'l':
8036 /* This is like the 'A' operator, except that if
8037 the width field "M" is zero, then the offset is
8038 *not* multiplied by four. */
8039 {
8040 int offset = given & 0xff;
8041 int multiplier = (given & 0x00000100) ? 4 : 1;
8042
8043 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8044
8045 if (multiplier > 1)
8046 {
8047 value_in_comment = offset * multiplier;
8048 if (NEGATIVE_BIT_SET)
8049 value_in_comment = - value_in_comment;
8050 }
8051
8052 if (offset)
8053 {
8054 if (PRE_BIT_SET)
8055 func (stream, ", #%s%d]%s",
8056 NEGATIVE_BIT_SET ? "-" : "",
8057 offset * multiplier,
8058 WRITEBACK_BIT_SET ? "!" : "");
8059 else
8060 func (stream, "], #%s%d",
8061 NEGATIVE_BIT_SET ? "-" : "",
8062 offset * multiplier);
8063 }
8064 else
8065 func (stream, "]");
8066 }
8067 break;
8068
8069 case 'r':
8070 {
8071 int imm4 = (given >> 4) & 0xf;
8072 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
8073 int ubit = ! NEGATIVE_BIT_SET;
8074 const char *rm = arm_regnames [given & 0xf];
8075 const char *rn = arm_regnames [(given >> 16) & 0xf];
8076
8077 switch (puw_bits)
8078 {
8079 case 1:
8080 case 3:
8081 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
8082 if (imm4)
8083 func (stream, ", lsl #%d", imm4);
8084 break;
8085
8086 case 4:
8087 case 5:
8088 case 6:
8089 case 7:
8090 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
8091 if (imm4 > 0)
8092 func (stream, ", lsl #%d", imm4);
8093 func (stream, "]");
8094 if (puw_bits == 5 || puw_bits == 7)
8095 func (stream, "!");
8096 break;
8097
8098 default:
8099 func (stream, "INVALID");
8100 }
8101 }
8102 break;
8103
8104 case 'i':
8105 {
8106 long imm5;
8107 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
8108 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
8109 }
8110 break;
8111
8112 default:
8113 abort ();
8114 }
8115 }
8116 else
8117 func (stream, "%c", *c);
8118 }
8119
8120 if (value_in_comment > 32 || value_in_comment < -16)
8121 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
8122
8123 if (is_unpredictable)
8124 func (stream, UNPREDICTABLE_INSTRUCTION);
8125
8126 return TRUE;
8127 }
8128 return FALSE;
8129 }
8130
8131 /* Decodes and prints ARM addressing modes. Returns the offset
8132 used in the address, if any, if it is worthwhile printing the
8133 offset as a hexadecimal value in a comment at the end of the
8134 line of disassembly. */
8135
8136 static signed long
8137 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
8138 {
8139 void *stream = info->stream;
8140 fprintf_ftype func = info->fprintf_func;
8141 bfd_vma offset = 0;
8142
8143 if (((given & 0x000f0000) == 0x000f0000)
8144 && ((given & 0x02000000) == 0))
8145 {
8146 offset = given & 0xfff;
8147
8148 func (stream, "[pc");
8149
8150 if (PRE_BIT_SET)
8151 {
8152 /* Pre-indexed. Elide offset of positive zero when
8153 non-writeback. */
8154 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
8155 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8156
8157 if (NEGATIVE_BIT_SET)
8158 offset = -offset;
8159
8160 offset += pc + 8;
8161
8162 /* Cope with the possibility of write-back
8163 being used. Probably a very dangerous thing
8164 for the programmer to do, but who are we to
8165 argue ? */
8166 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
8167 }
8168 else /* Post indexed. */
8169 {
8170 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8171
8172 /* Ie ignore the offset. */
8173 offset = pc + 8;
8174 }
8175
8176 func (stream, "\t; ");
8177 info->print_address_func (offset, info);
8178 offset = 0;
8179 }
8180 else
8181 {
8182 func (stream, "[%s",
8183 arm_regnames[(given >> 16) & 0xf]);
8184
8185 if (PRE_BIT_SET)
8186 {
8187 if ((given & 0x02000000) == 0)
8188 {
8189 /* Elide offset of positive zero when non-writeback. */
8190 offset = given & 0xfff;
8191 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
8192 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8193 }
8194 else
8195 {
8196 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
8197 arm_decode_shift (given, func, stream, TRUE);
8198 }
8199
8200 func (stream, "]%s",
8201 WRITEBACK_BIT_SET ? "!" : "");
8202 }
8203 else
8204 {
8205 if ((given & 0x02000000) == 0)
8206 {
8207 /* Always show offset. */
8208 offset = given & 0xfff;
8209 func (stream, "], #%s%d",
8210 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8211 }
8212 else
8213 {
8214 func (stream, "], %s",
8215 NEGATIVE_BIT_SET ? "-" : "");
8216 arm_decode_shift (given, func, stream, TRUE);
8217 }
8218 }
8219 if (NEGATIVE_BIT_SET)
8220 offset = -offset;
8221 }
8222
8223 return (signed long) offset;
8224 }
8225
8226 /* Print one neon instruction on INFO->STREAM.
8227 Return TRUE if the instuction matched, FALSE if this is not a
8228 recognised neon instruction. */
8229
8230 static bfd_boolean
8231 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
8232 {
8233 const struct opcode32 *insn;
8234 void *stream = info->stream;
8235 fprintf_ftype func = info->fprintf_func;
8236
8237 if (thumb)
8238 {
8239 if ((given & 0xef000000) == 0xef000000)
8240 {
8241 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
8242 unsigned long bit28 = given & (1 << 28);
8243
8244 given &= 0x00ffffff;
8245 if (bit28)
8246 given |= 0xf3000000;
8247 else
8248 given |= 0xf2000000;
8249 }
8250 else if ((given & 0xff000000) == 0xf9000000)
8251 given ^= 0xf9000000 ^ 0xf4000000;
8252 /* vdup is also a valid neon instruction. */
8253 else if ((given & 0xff910f5f) != 0xee800b10)
8254 return FALSE;
8255 }
8256
8257 for (insn = neon_opcodes; insn->assembler; insn++)
8258 {
8259 if ((given & insn->mask) == insn->value)
8260 {
8261 signed long value_in_comment = 0;
8262 bfd_boolean is_unpredictable = FALSE;
8263 const char *c;
8264
8265 for (c = insn->assembler; *c; c++)
8266 {
8267 if (*c == '%')
8268 {
8269 switch (*++c)
8270 {
8271 case '%':
8272 func (stream, "%%");
8273 break;
8274
8275 case 'u':
8276 if (thumb && ifthen_state)
8277 is_unpredictable = TRUE;
8278
8279 /* Fall through. */
8280 case 'c':
8281 if (thumb && ifthen_state)
8282 func (stream, "%s", arm_conditional[IFTHEN_COND]);
8283 break;
8284
8285 case 'A':
8286 {
8287 static const unsigned char enc[16] =
8288 {
8289 0x4, 0x14, /* st4 0,1 */
8290 0x4, /* st1 2 */
8291 0x4, /* st2 3 */
8292 0x3, /* st3 4 */
8293 0x13, /* st3 5 */
8294 0x3, /* st1 6 */
8295 0x1, /* st1 7 */
8296 0x2, /* st2 8 */
8297 0x12, /* st2 9 */
8298 0x2, /* st1 10 */
8299 0, 0, 0, 0, 0
8300 };
8301 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8302 int rn = ((given >> 16) & 0xf);
8303 int rm = ((given >> 0) & 0xf);
8304 int align = ((given >> 4) & 0x3);
8305 int type = ((given >> 8) & 0xf);
8306 int n = enc[type] & 0xf;
8307 int stride = (enc[type] >> 4) + 1;
8308 int ix;
8309
8310 func (stream, "{");
8311 if (stride > 1)
8312 for (ix = 0; ix != n; ix++)
8313 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
8314 else if (n == 1)
8315 func (stream, "d%d", rd);
8316 else
8317 func (stream, "d%d-d%d", rd, rd + n - 1);
8318 func (stream, "}, [%s", arm_regnames[rn]);
8319 if (align)
8320 func (stream, " :%d", 32 << align);
8321 func (stream, "]");
8322 if (rm == 0xd)
8323 func (stream, "!");
8324 else if (rm != 0xf)
8325 func (stream, ", %s", arm_regnames[rm]);
8326 }
8327 break;
8328
8329 case 'B':
8330 {
8331 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8332 int rn = ((given >> 16) & 0xf);
8333 int rm = ((given >> 0) & 0xf);
8334 int idx_align = ((given >> 4) & 0xf);
8335 int align = 0;
8336 int size = ((given >> 10) & 0x3);
8337 int idx = idx_align >> (size + 1);
8338 int length = ((given >> 8) & 3) + 1;
8339 int stride = 1;
8340 int i;
8341
8342 if (length > 1 && size > 0)
8343 stride = (idx_align & (1 << size)) ? 2 : 1;
8344
8345 switch (length)
8346 {
8347 case 1:
8348 {
8349 int amask = (1 << size) - 1;
8350 if ((idx_align & (1 << size)) != 0)
8351 return FALSE;
8352 if (size > 0)
8353 {
8354 if ((idx_align & amask) == amask)
8355 align = 8 << size;
8356 else if ((idx_align & amask) != 0)
8357 return FALSE;
8358 }
8359 }
8360 break;
8361
8362 case 2:
8363 if (size == 2 && (idx_align & 2) != 0)
8364 return FALSE;
8365 align = (idx_align & 1) ? 16 << size : 0;
8366 break;
8367
8368 case 3:
8369 if ((size == 2 && (idx_align & 3) != 0)
8370 || (idx_align & 1) != 0)
8371 return FALSE;
8372 break;
8373
8374 case 4:
8375 if (size == 2)
8376 {
8377 if ((idx_align & 3) == 3)
8378 return FALSE;
8379 align = (idx_align & 3) * 64;
8380 }
8381 else
8382 align = (idx_align & 1) ? 32 << size : 0;
8383 break;
8384
8385 default:
8386 abort ();
8387 }
8388
8389 func (stream, "{");
8390 for (i = 0; i < length; i++)
8391 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
8392 rd + i * stride, idx);
8393 func (stream, "}, [%s", arm_regnames[rn]);
8394 if (align)
8395 func (stream, " :%d", align);
8396 func (stream, "]");
8397 if (rm == 0xd)
8398 func (stream, "!");
8399 else if (rm != 0xf)
8400 func (stream, ", %s", arm_regnames[rm]);
8401 }
8402 break;
8403
8404 case 'C':
8405 {
8406 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8407 int rn = ((given >> 16) & 0xf);
8408 int rm = ((given >> 0) & 0xf);
8409 int align = ((given >> 4) & 0x1);
8410 int size = ((given >> 6) & 0x3);
8411 int type = ((given >> 8) & 0x3);
8412 int n = type + 1;
8413 int stride = ((given >> 5) & 0x1);
8414 int ix;
8415
8416 if (stride && (n == 1))
8417 n++;
8418 else
8419 stride++;
8420
8421 func (stream, "{");
8422 if (stride > 1)
8423 for (ix = 0; ix != n; ix++)
8424 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
8425 else if (n == 1)
8426 func (stream, "d%d[]", rd);
8427 else
8428 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
8429 func (stream, "}, [%s", arm_regnames[rn]);
8430 if (align)
8431 {
8432 align = (8 * (type + 1)) << size;
8433 if (type == 3)
8434 align = (size > 1) ? align >> 1 : align;
8435 if (type == 2 || (type == 0 && !size))
8436 func (stream, " :<bad align %d>", align);
8437 else
8438 func (stream, " :%d", align);
8439 }
8440 func (stream, "]");
8441 if (rm == 0xd)
8442 func (stream, "!");
8443 else if (rm != 0xf)
8444 func (stream, ", %s", arm_regnames[rm]);
8445 }
8446 break;
8447
8448 case 'D':
8449 {
8450 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
8451 int size = (given >> 20) & 3;
8452 int reg = raw_reg & ((4 << size) - 1);
8453 int ix = raw_reg >> size >> 2;
8454
8455 func (stream, "d%d[%d]", reg, ix);
8456 }
8457 break;
8458
8459 case 'E':
8460 /* Neon encoded constant for mov, mvn, vorr, vbic. */
8461 {
8462 int bits = 0;
8463 int cmode = (given >> 8) & 0xf;
8464 int op = (given >> 5) & 0x1;
8465 unsigned long value = 0, hival = 0;
8466 unsigned shift;
8467 int size = 0;
8468 int isfloat = 0;
8469
8470 bits |= ((given >> 24) & 1) << 7;
8471 bits |= ((given >> 16) & 7) << 4;
8472 bits |= ((given >> 0) & 15) << 0;
8473
8474 if (cmode < 8)
8475 {
8476 shift = (cmode >> 1) & 3;
8477 value = (unsigned long) bits << (8 * shift);
8478 size = 32;
8479 }
8480 else if (cmode < 12)
8481 {
8482 shift = (cmode >> 1) & 1;
8483 value = (unsigned long) bits << (8 * shift);
8484 size = 16;
8485 }
8486 else if (cmode < 14)
8487 {
8488 shift = (cmode & 1) + 1;
8489 value = (unsigned long) bits << (8 * shift);
8490 value |= (1ul << (8 * shift)) - 1;
8491 size = 32;
8492 }
8493 else if (cmode == 14)
8494 {
8495 if (op)
8496 {
8497 /* Bit replication into bytes. */
8498 int ix;
8499 unsigned long mask;
8500
8501 value = 0;
8502 hival = 0;
8503 for (ix = 7; ix >= 0; ix--)
8504 {
8505 mask = ((bits >> ix) & 1) ? 0xff : 0;
8506 if (ix <= 3)
8507 value = (value << 8) | mask;
8508 else
8509 hival = (hival << 8) | mask;
8510 }
8511 size = 64;
8512 }
8513 else
8514 {
8515 /* Byte replication. */
8516 value = (unsigned long) bits;
8517 size = 8;
8518 }
8519 }
8520 else if (!op)
8521 {
8522 /* Floating point encoding. */
8523 int tmp;
8524
8525 value = (unsigned long) (bits & 0x7f) << 19;
8526 value |= (unsigned long) (bits & 0x80) << 24;
8527 tmp = bits & 0x40 ? 0x3c : 0x40;
8528 value |= (unsigned long) tmp << 24;
8529 size = 32;
8530 isfloat = 1;
8531 }
8532 else
8533 {
8534 func (stream, "<illegal constant %.8x:%x:%x>",
8535 bits, cmode, op);
8536 size = 32;
8537 break;
8538 }
8539 switch (size)
8540 {
8541 case 8:
8542 func (stream, "#%ld\t; 0x%.2lx", value, value);
8543 break;
8544
8545 case 16:
8546 func (stream, "#%ld\t; 0x%.4lx", value, value);
8547 break;
8548
8549 case 32:
8550 if (isfloat)
8551 {
8552 unsigned char valbytes[4];
8553 double fvalue;
8554
8555 /* Do this a byte at a time so we don't have to
8556 worry about the host's endianness. */
8557 valbytes[0] = value & 0xff;
8558 valbytes[1] = (value >> 8) & 0xff;
8559 valbytes[2] = (value >> 16) & 0xff;
8560 valbytes[3] = (value >> 24) & 0xff;
8561
8562 floatformat_to_double
8563 (& floatformat_ieee_single_little, valbytes,
8564 & fvalue);
8565
8566 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
8567 value);
8568 }
8569 else
8570 func (stream, "#%ld\t; 0x%.8lx",
8571 (long) (((value & 0x80000000L) != 0)
8572 ? value | ~0xffffffffL : value),
8573 value);
8574 break;
8575
8576 case 64:
8577 func (stream, "#0x%.8lx%.8lx", hival, value);
8578 break;
8579
8580 default:
8581 abort ();
8582 }
8583 }
8584 break;
8585
8586 case 'F':
8587 {
8588 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
8589 int num = (given >> 8) & 0x3;
8590
8591 if (!num)
8592 func (stream, "{d%d}", regno);
8593 else if (num + regno >= 32)
8594 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
8595 else
8596 func (stream, "{d%d-d%d}", regno, regno + num);
8597 }
8598 break;
8599
8600
8601 case '0': case '1': case '2': case '3': case '4':
8602 case '5': case '6': case '7': case '8': case '9':
8603 {
8604 int width;
8605 unsigned long value;
8606
8607 c = arm_decode_bitfield (c, given, &value, &width);
8608
8609 switch (*c)
8610 {
8611 case 'r':
8612 func (stream, "%s", arm_regnames[value]);
8613 break;
8614 case 'd':
8615 func (stream, "%ld", value);
8616 value_in_comment = value;
8617 break;
8618 case 'e':
8619 func (stream, "%ld", (1ul << width) - value);
8620 break;
8621
8622 case 'S':
8623 case 'T':
8624 case 'U':
8625 /* Various width encodings. */
8626 {
8627 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
8628 int limit;
8629 unsigned low, high;
8630
8631 c++;
8632 if (*c >= '0' && *c <= '9')
8633 limit = *c - '0';
8634 else if (*c >= 'a' && *c <= 'f')
8635 limit = *c - 'a' + 10;
8636 else
8637 abort ();
8638 low = limit >> 2;
8639 high = limit & 3;
8640
8641 if (value < low || value > high)
8642 func (stream, "<illegal width %d>", base << value);
8643 else
8644 func (stream, "%d", base << value);
8645 }
8646 break;
8647 case 'R':
8648 if (given & (1 << 6))
8649 goto Q;
8650 /* FALLTHROUGH */
8651 case 'D':
8652 func (stream, "d%ld", value);
8653 break;
8654 case 'Q':
8655 Q:
8656 if (value & 1)
8657 func (stream, "<illegal reg q%ld.5>", value >> 1);
8658 else
8659 func (stream, "q%ld", value >> 1);
8660 break;
8661
8662 case '`':
8663 c++;
8664 if (value == 0)
8665 func (stream, "%c", *c);
8666 break;
8667 case '\'':
8668 c++;
8669 if (value == ((1ul << width) - 1))
8670 func (stream, "%c", *c);
8671 break;
8672 case '?':
8673 func (stream, "%c", c[(1 << width) - (int) value]);
8674 c += 1 << width;
8675 break;
8676 default:
8677 abort ();
8678 }
8679 }
8680 break;
8681
8682 default:
8683 abort ();
8684 }
8685 }
8686 else
8687 func (stream, "%c", *c);
8688 }
8689
8690 if (value_in_comment > 32 || value_in_comment < -16)
8691 func (stream, "\t; 0x%lx", value_in_comment);
8692
8693 if (is_unpredictable)
8694 func (stream, UNPREDICTABLE_INSTRUCTION);
8695
8696 return TRUE;
8697 }
8698 }
8699 return FALSE;
8700 }
8701
8702 /* Print one mve instruction on INFO->STREAM.
8703 Return TRUE if the instuction matched, FALSE if this is not a
8704 recognised mve instruction. */
8705
8706 static bfd_boolean
8707 print_insn_mve (struct disassemble_info *info, long given)
8708 {
8709 const struct mopcode32 *insn;
8710 void *stream = info->stream;
8711 fprintf_ftype func = info->fprintf_func;
8712
8713 for (insn = mve_opcodes; insn->assembler; insn++)
8714 {
8715 if (((given & insn->mask) == insn->value)
8716 && !is_mve_encoding_conflict (given, insn->mve_op))
8717 {
8718 signed long value_in_comment = 0;
8719 bfd_boolean is_unpredictable = FALSE;
8720 bfd_boolean is_undefined = FALSE;
8721 const char *c;
8722 enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
8723 enum mve_undefined undefined_cond = UNDEF_NONE;
8724
8725 /* Most vector mve instruction are illegal in a it block.
8726 There are a few exceptions; check for them. */
8727 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
8728 {
8729 is_unpredictable = TRUE;
8730 unpredictable_cond = UNPRED_IT_BLOCK;
8731 }
8732 else if (is_mve_unpredictable (given, insn->mve_op,
8733 &unpredictable_cond))
8734 is_unpredictable = TRUE;
8735
8736 if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
8737 is_undefined = TRUE;
8738
8739 for (c = insn->assembler; *c; c++)
8740 {
8741 if (*c == '%')
8742 {
8743 switch (*++c)
8744 {
8745 case '%':
8746 func (stream, "%%");
8747 break;
8748
8749 case 'a':
8750 /* Don't print anything for '+' as it is implied. */
8751 if (arm_decode_field (given, 23, 23) == 0)
8752 func (stream, "-");
8753 break;
8754
8755 case 'c':
8756 if (ifthen_state)
8757 func (stream, "%s", arm_conditional[IFTHEN_COND]);
8758 break;
8759
8760 case 'd':
8761 print_mve_vld_str_addr (info, given, insn->mve_op);
8762 break;
8763
8764 case 'i':
8765 {
8766 long mve_mask = mve_extract_pred_mask (given);
8767 func (stream, "%s", mve_predicatenames[mve_mask]);
8768 }
8769 break;
8770
8771 case 'n':
8772 print_vec_condition (info, given, insn->mve_op);
8773 break;
8774
8775 case 'o':
8776 if (arm_decode_field (given, 0, 0) == 1)
8777 {
8778 unsigned long size
8779 = arm_decode_field (given, 4, 4)
8780 | (arm_decode_field (given, 6, 6) << 1);
8781
8782 func (stream, ", uxtw #%lu", size);
8783 }
8784 break;
8785
8786 case 'm':
8787 print_mve_rounding_mode (info, given, insn->mve_op);
8788 break;
8789
8790 case 's':
8791 print_mve_vcvt_size (info, given, insn->mve_op);
8792 break;
8793
8794 case 'u':
8795 {
8796 unsigned long op1 = arm_decode_field (given, 21, 22);
8797
8798 if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
8799 {
8800 /* Check for signed. */
8801 if (arm_decode_field (given, 23, 23) == 0)
8802 {
8803 /* We don't print 's' for S32. */
8804 if ((arm_decode_field (given, 5, 6) == 0)
8805 && ((op1 == 0) || (op1 == 1)))
8806 ;
8807 else
8808 func (stream, "s");
8809 }
8810 else
8811 func (stream, "u");
8812 }
8813 else
8814 {
8815 if (arm_decode_field (given, 28, 28) == 0)
8816 func (stream, "s");
8817 else
8818 func (stream, "u");
8819 }
8820 }
8821 break;
8822
8823 case 'v':
8824 print_instruction_predicate (info);
8825 break;
8826
8827 case 'w':
8828 if (arm_decode_field (given, 21, 21) == 1)
8829 func (stream, "!");
8830 break;
8831
8832 case 'B':
8833 print_mve_register_blocks (info, given, insn->mve_op);
8834 break;
8835
8836 case 'E':
8837 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
8838
8839 print_simd_imm8 (info, given, 28, insn);
8840 break;
8841
8842 case 'N':
8843 print_mve_vmov_index (info, given);
8844 break;
8845
8846 case 'T':
8847 if (arm_decode_field (given, 12, 12) == 0)
8848 func (stream, "b");
8849 else
8850 func (stream, "t");
8851 break;
8852
8853 case 'X':
8854 if (arm_decode_field (given, 12, 12) == 1)
8855 func (stream, "x");
8856 break;
8857
8858 case '0': case '1': case '2': case '3': case '4':
8859 case '5': case '6': case '7': case '8': case '9':
8860 {
8861 int width;
8862 unsigned long value;
8863
8864 c = arm_decode_bitfield (c, given, &value, &width);
8865
8866 switch (*c)
8867 {
8868 case 'Z':
8869 if (value == 13)
8870 is_unpredictable = TRUE;
8871 else if (value == 15)
8872 func (stream, "zr");
8873 else
8874 func (stream, "%s", arm_regnames[value]);
8875 break;
8876 case 's':
8877 print_mve_size (info,
8878 value,
8879 insn->mve_op);
8880 break;
8881 case 'I':
8882 if (value == 1)
8883 func (stream, "i");
8884 break;
8885 case 'A':
8886 if (value == 1)
8887 func (stream, "a");
8888 break;
8889 case 'h':
8890 {
8891 unsigned int odd_reg = (value << 1) | 1;
8892 func (stream, "%s", arm_regnames[odd_reg]);
8893 }
8894 break;
8895 case 'i':
8896 {
8897 unsigned long imm
8898 = arm_decode_field (given, 0, 6);
8899 unsigned long mod_imm = imm;
8900
8901 switch (insn->mve_op)
8902 {
8903 case MVE_VLDRW_GATHER_T5:
8904 case MVE_VSTRW_SCATTER_T5:
8905 mod_imm = mod_imm << 2;
8906 break;
8907 case MVE_VSTRD_SCATTER_T6:
8908 case MVE_VLDRD_GATHER_T6:
8909 mod_imm = mod_imm << 3;
8910 break;
8911
8912 default:
8913 break;
8914 }
8915
8916 func (stream, "%lu", mod_imm);
8917 }
8918 break;
8919 case 'k':
8920 func (stream, "%lu", 64 - value);
8921 break;
8922 case 'l':
8923 {
8924 unsigned int even_reg = value << 1;
8925 func (stream, "%s", arm_regnames[even_reg]);
8926 }
8927 break;
8928 case 'u':
8929 switch (value)
8930 {
8931 case 0:
8932 func (stream, "1");
8933 break;
8934 case 1:
8935 func (stream, "2");
8936 break;
8937 case 2:
8938 func (stream, "4");
8939 break;
8940 case 3:
8941 func (stream, "8");
8942 break;
8943 default:
8944 break;
8945 }
8946 break;
8947 case 'o':
8948 print_mve_rotate (info, value, width);
8949 break;
8950 case 'r':
8951 func (stream, "%s", arm_regnames[value]);
8952 break;
8953 case 'd':
8954 if (insn->mve_op == MVE_VQSHL_T2
8955 || insn->mve_op == MVE_VQSHLU_T3
8956 || insn->mve_op == MVE_VRSHR
8957 || insn->mve_op == MVE_VRSHRN
8958 || insn->mve_op == MVE_VSHL_T1
8959 || insn->mve_op == MVE_VSHLL_T1
8960 || insn->mve_op == MVE_VSHR
8961 || insn->mve_op == MVE_VSHRN
8962 || insn->mve_op == MVE_VSLI
8963 || insn->mve_op == MVE_VSRI)
8964 print_mve_shift_n (info, given, insn->mve_op);
8965 else if (insn->mve_op == MVE_VSHLL_T2)
8966 {
8967 switch (value)
8968 {
8969 case 0x00:
8970 func (stream, "8");
8971 break;
8972 case 0x01:
8973 func (stream, "16");
8974 break;
8975 case 0x10:
8976 print_mve_undefined (info, UNDEF_SIZE_0);
8977 break;
8978 default:
8979 assert (0);
8980 break;
8981 }
8982 }
8983 else
8984 {
8985 if (insn->mve_op == MVE_VSHLC && value == 0)
8986 value = 32;
8987 func (stream, "%ld", value);
8988 value_in_comment = value;
8989 }
8990 break;
8991 case 'F':
8992 func (stream, "s%ld", value);
8993 break;
8994 case 'Q':
8995 if (value & 0x8)
8996 func (stream, "<illegal reg q%ld.5>", value);
8997 else
8998 func (stream, "q%ld", value);
8999 break;
9000 case 'x':
9001 func (stream, "0x%08lx", value);
9002 break;
9003 default:
9004 abort ();
9005 }
9006 break;
9007 default:
9008 abort ();
9009 }
9010 }
9011 }
9012 else
9013 func (stream, "%c", *c);
9014 }
9015
9016 if (value_in_comment > 32 || value_in_comment < -16)
9017 func (stream, "\t; 0x%lx", value_in_comment);
9018
9019 if (is_unpredictable)
9020 print_mve_unpredictable (info, unpredictable_cond);
9021
9022 if (is_undefined)
9023 print_mve_undefined (info, undefined_cond);
9024
9025 if ((vpt_block_state.in_vpt_block == FALSE)
9026 && !ifthen_state
9027 && (is_vpt_instruction (given) == TRUE))
9028 mark_inside_vpt_block (given);
9029 else if (vpt_block_state.in_vpt_block == TRUE)
9030 update_vpt_block_state ();
9031
9032 return TRUE;
9033 }
9034 }
9035 return FALSE;
9036 }
9037
9038
9039 /* Return the name of a v7A special register. */
9040
9041 static const char *
9042 banked_regname (unsigned reg)
9043 {
9044 switch (reg)
9045 {
9046 case 15: return "CPSR";
9047 case 32: return "R8_usr";
9048 case 33: return "R9_usr";
9049 case 34: return "R10_usr";
9050 case 35: return "R11_usr";
9051 case 36: return "R12_usr";
9052 case 37: return "SP_usr";
9053 case 38: return "LR_usr";
9054 case 40: return "R8_fiq";
9055 case 41: return "R9_fiq";
9056 case 42: return "R10_fiq";
9057 case 43: return "R11_fiq";
9058 case 44: return "R12_fiq";
9059 case 45: return "SP_fiq";
9060 case 46: return "LR_fiq";
9061 case 48: return "LR_irq";
9062 case 49: return "SP_irq";
9063 case 50: return "LR_svc";
9064 case 51: return "SP_svc";
9065 case 52: return "LR_abt";
9066 case 53: return "SP_abt";
9067 case 54: return "LR_und";
9068 case 55: return "SP_und";
9069 case 60: return "LR_mon";
9070 case 61: return "SP_mon";
9071 case 62: return "ELR_hyp";
9072 case 63: return "SP_hyp";
9073 case 79: return "SPSR";
9074 case 110: return "SPSR_fiq";
9075 case 112: return "SPSR_irq";
9076 case 114: return "SPSR_svc";
9077 case 116: return "SPSR_abt";
9078 case 118: return "SPSR_und";
9079 case 124: return "SPSR_mon";
9080 case 126: return "SPSR_hyp";
9081 default: return NULL;
9082 }
9083 }
9084
9085 /* Return the name of the DMB/DSB option. */
9086 static const char *
9087 data_barrier_option (unsigned option)
9088 {
9089 switch (option & 0xf)
9090 {
9091 case 0xf: return "sy";
9092 case 0xe: return "st";
9093 case 0xd: return "ld";
9094 case 0xb: return "ish";
9095 case 0xa: return "ishst";
9096 case 0x9: return "ishld";
9097 case 0x7: return "un";
9098 case 0x6: return "unst";
9099 case 0x5: return "nshld";
9100 case 0x3: return "osh";
9101 case 0x2: return "oshst";
9102 case 0x1: return "oshld";
9103 default: return NULL;
9104 }
9105 }
9106
9107 /* Print one ARM instruction from PC on INFO->STREAM. */
9108
9109 static void
9110 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
9111 {
9112 const struct opcode32 *insn;
9113 void *stream = info->stream;
9114 fprintf_ftype func = info->fprintf_func;
9115 struct arm_private_data *private_data = info->private_data;
9116
9117 if (print_insn_coprocessor (pc, info, given, FALSE))
9118 return;
9119
9120 if (print_insn_neon (info, given, FALSE))
9121 return;
9122
9123 for (insn = arm_opcodes; insn->assembler; insn++)
9124 {
9125 if ((given & insn->mask) != insn->value)
9126 continue;
9127
9128 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
9129 continue;
9130
9131 /* Special case: an instruction with all bits set in the condition field
9132 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
9133 or by the catchall at the end of the table. */
9134 if ((given & 0xF0000000) != 0xF0000000
9135 || (insn->mask & 0xF0000000) == 0xF0000000
9136 || (insn->mask == 0 && insn->value == 0))
9137 {
9138 unsigned long u_reg = 16;
9139 unsigned long U_reg = 16;
9140 bfd_boolean is_unpredictable = FALSE;
9141 signed long value_in_comment = 0;
9142 const char *c;
9143
9144 for (c = insn->assembler; *c; c++)
9145 {
9146 if (*c == '%')
9147 {
9148 bfd_boolean allow_unpredictable = FALSE;
9149
9150 switch (*++c)
9151 {
9152 case '%':
9153 func (stream, "%%");
9154 break;
9155
9156 case 'a':
9157 value_in_comment = print_arm_address (pc, info, given);
9158 break;
9159
9160 case 'P':
9161 /* Set P address bit and use normal address
9162 printing routine. */
9163 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
9164 break;
9165
9166 case 'S':
9167 allow_unpredictable = TRUE;
9168 /* Fall through. */
9169 case 's':
9170 if ((given & 0x004f0000) == 0x004f0000)
9171 {
9172 /* PC relative with immediate offset. */
9173 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
9174
9175 if (PRE_BIT_SET)
9176 {
9177 /* Elide positive zero offset. */
9178 if (offset || NEGATIVE_BIT_SET)
9179 func (stream, "[pc, #%s%d]\t; ",
9180 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
9181 else
9182 func (stream, "[pc]\t; ");
9183 if (NEGATIVE_BIT_SET)
9184 offset = -offset;
9185 info->print_address_func (offset + pc + 8, info);
9186 }
9187 else
9188 {
9189 /* Always show the offset. */
9190 func (stream, "[pc], #%s%d",
9191 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
9192 if (! allow_unpredictable)
9193 is_unpredictable = TRUE;
9194 }
9195 }
9196 else
9197 {
9198 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
9199
9200 func (stream, "[%s",
9201 arm_regnames[(given >> 16) & 0xf]);
9202
9203 if (PRE_BIT_SET)
9204 {
9205 if (IMMEDIATE_BIT_SET)
9206 {
9207 /* Elide offset for non-writeback
9208 positive zero. */
9209 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
9210 || offset)
9211 func (stream, ", #%s%d",
9212 NEGATIVE_BIT_SET ? "-" : "", offset);
9213
9214 if (NEGATIVE_BIT_SET)
9215 offset = -offset;
9216
9217 value_in_comment = offset;
9218 }
9219 else
9220 {
9221 /* Register Offset or Register Pre-Indexed. */
9222 func (stream, ", %s%s",
9223 NEGATIVE_BIT_SET ? "-" : "",
9224 arm_regnames[given & 0xf]);
9225
9226 /* Writing back to the register that is the source/
9227 destination of the load/store is unpredictable. */
9228 if (! allow_unpredictable
9229 && WRITEBACK_BIT_SET
9230 && ((given & 0xf) == ((given >> 12) & 0xf)))
9231 is_unpredictable = TRUE;
9232 }
9233
9234 func (stream, "]%s",
9235 WRITEBACK_BIT_SET ? "!" : "");
9236 }
9237 else
9238 {
9239 if (IMMEDIATE_BIT_SET)
9240 {
9241 /* Immediate Post-indexed. */
9242 /* PR 10924: Offset must be printed, even if it is zero. */
9243 func (stream, "], #%s%d",
9244 NEGATIVE_BIT_SET ? "-" : "", offset);
9245 if (NEGATIVE_BIT_SET)
9246 offset = -offset;
9247 value_in_comment = offset;
9248 }
9249 else
9250 {
9251 /* Register Post-indexed. */
9252 func (stream, "], %s%s",
9253 NEGATIVE_BIT_SET ? "-" : "",
9254 arm_regnames[given & 0xf]);
9255
9256 /* Writing back to the register that is the source/
9257 destination of the load/store is unpredictable. */
9258 if (! allow_unpredictable
9259 && (given & 0xf) == ((given >> 12) & 0xf))
9260 is_unpredictable = TRUE;
9261 }
9262
9263 if (! allow_unpredictable)
9264 {
9265 /* Writeback is automatically implied by post- addressing.
9266 Setting the W bit is unnecessary and ARM specify it as
9267 being unpredictable. */
9268 if (WRITEBACK_BIT_SET
9269 /* Specifying the PC register as the post-indexed
9270 registers is also unpredictable. */
9271 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
9272 is_unpredictable = TRUE;
9273 }
9274 }
9275 }
9276 break;
9277
9278 case 'b':
9279 {
9280 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
9281 info->print_address_func (disp * 4 + pc + 8, info);
9282 }
9283 break;
9284
9285 case 'c':
9286 if (((given >> 28) & 0xf) != 0xe)
9287 func (stream, "%s",
9288 arm_conditional [(given >> 28) & 0xf]);
9289 break;
9290
9291 case 'm':
9292 {
9293 int started = 0;
9294 int reg;
9295
9296 func (stream, "{");
9297 for (reg = 0; reg < 16; reg++)
9298 if ((given & (1 << reg)) != 0)
9299 {
9300 if (started)
9301 func (stream, ", ");
9302 started = 1;
9303 func (stream, "%s", arm_regnames[reg]);
9304 }
9305 func (stream, "}");
9306 if (! started)
9307 is_unpredictable = TRUE;
9308 }
9309 break;
9310
9311 case 'q':
9312 arm_decode_shift (given, func, stream, FALSE);
9313 break;
9314
9315 case 'o':
9316 if ((given & 0x02000000) != 0)
9317 {
9318 unsigned int rotate = (given & 0xf00) >> 7;
9319 unsigned int immed = (given & 0xff);
9320 unsigned int a, i;
9321
9322 a = (((immed << (32 - rotate))
9323 | (immed >> rotate)) & 0xffffffff);
9324 /* If there is another encoding with smaller rotate,
9325 the rotate should be specified directly. */
9326 for (i = 0; i < 32; i += 2)
9327 if ((a << i | a >> (32 - i)) <= 0xff)
9328 break;
9329
9330 if (i != rotate)
9331 func (stream, "#%d, %d", immed, rotate);
9332 else
9333 func (stream, "#%d", a);
9334 value_in_comment = a;
9335 }
9336 else
9337 arm_decode_shift (given, func, stream, TRUE);
9338 break;
9339
9340 case 'p':
9341 if ((given & 0x0000f000) == 0x0000f000)
9342 {
9343 arm_feature_set arm_ext_v6 =
9344 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
9345
9346 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
9347 mechanism for setting PSR flag bits. They are
9348 obsolete in V6 onwards. */
9349 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
9350 arm_ext_v6))
9351 func (stream, "p");
9352 else
9353 is_unpredictable = TRUE;
9354 }
9355 break;
9356
9357 case 't':
9358 if ((given & 0x01200000) == 0x00200000)
9359 func (stream, "t");
9360 break;
9361
9362 case 'A':
9363 {
9364 int offset = given & 0xff;
9365
9366 value_in_comment = offset * 4;
9367 if (NEGATIVE_BIT_SET)
9368 value_in_comment = - value_in_comment;
9369
9370 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
9371
9372 if (PRE_BIT_SET)
9373 {
9374 if (offset)
9375 func (stream, ", #%d]%s",
9376 (int) value_in_comment,
9377 WRITEBACK_BIT_SET ? "!" : "");
9378 else
9379 func (stream, "]");
9380 }
9381 else
9382 {
9383 func (stream, "]");
9384
9385 if (WRITEBACK_BIT_SET)
9386 {
9387 if (offset)
9388 func (stream, ", #%d", (int) value_in_comment);
9389 }
9390 else
9391 {
9392 func (stream, ", {%d}", (int) offset);
9393 value_in_comment = offset;
9394 }
9395 }
9396 }
9397 break;
9398
9399 case 'B':
9400 /* Print ARM V5 BLX(1) address: pc+25 bits. */
9401 {
9402 bfd_vma address;
9403 bfd_vma offset = 0;
9404
9405 if (! NEGATIVE_BIT_SET)
9406 /* Is signed, hi bits should be ones. */
9407 offset = (-1) ^ 0x00ffffff;
9408
9409 /* Offset is (SignExtend(offset field)<<2). */
9410 offset += given & 0x00ffffff;
9411 offset <<= 2;
9412 address = offset + pc + 8;
9413
9414 if (given & 0x01000000)
9415 /* H bit allows addressing to 2-byte boundaries. */
9416 address += 2;
9417
9418 info->print_address_func (address, info);
9419 }
9420 break;
9421
9422 case 'C':
9423 if ((given & 0x02000200) == 0x200)
9424 {
9425 const char * name;
9426 unsigned sysm = (given & 0x004f0000) >> 16;
9427
9428 sysm |= (given & 0x300) >> 4;
9429 name = banked_regname (sysm);
9430
9431 if (name != NULL)
9432 func (stream, "%s", name);
9433 else
9434 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
9435 }
9436 else
9437 {
9438 func (stream, "%cPSR_",
9439 (given & 0x00400000) ? 'S' : 'C');
9440 if (given & 0x80000)
9441 func (stream, "f");
9442 if (given & 0x40000)
9443 func (stream, "s");
9444 if (given & 0x20000)
9445 func (stream, "x");
9446 if (given & 0x10000)
9447 func (stream, "c");
9448 }
9449 break;
9450
9451 case 'U':
9452 if ((given & 0xf0) == 0x60)
9453 {
9454 switch (given & 0xf)
9455 {
9456 case 0xf: func (stream, "sy"); break;
9457 default:
9458 func (stream, "#%d", (int) given & 0xf);
9459 break;
9460 }
9461 }
9462 else
9463 {
9464 const char * opt = data_barrier_option (given & 0xf);
9465 if (opt != NULL)
9466 func (stream, "%s", opt);
9467 else
9468 func (stream, "#%d", (int) given & 0xf);
9469 }
9470 break;
9471
9472 case '0': case '1': case '2': case '3': case '4':
9473 case '5': case '6': case '7': case '8': case '9':
9474 {
9475 int width;
9476 unsigned long value;
9477
9478 c = arm_decode_bitfield (c, given, &value, &width);
9479
9480 switch (*c)
9481 {
9482 case 'R':
9483 if (value == 15)
9484 is_unpredictable = TRUE;
9485 /* Fall through. */
9486 case 'r':
9487 case 'T':
9488 /* We want register + 1 when decoding T. */
9489 if (*c == 'T')
9490 ++value;
9491
9492 if (c[1] == 'u')
9493 {
9494 /* Eat the 'u' character. */
9495 ++ c;
9496
9497 if (u_reg == value)
9498 is_unpredictable = TRUE;
9499 u_reg = value;
9500 }
9501 if (c[1] == 'U')
9502 {
9503 /* Eat the 'U' character. */
9504 ++ c;
9505
9506 if (U_reg == value)
9507 is_unpredictable = TRUE;
9508 U_reg = value;
9509 }
9510 func (stream, "%s", arm_regnames[value]);
9511 break;
9512 case 'd':
9513 func (stream, "%ld", value);
9514 value_in_comment = value;
9515 break;
9516 case 'b':
9517 func (stream, "%ld", value * 8);
9518 value_in_comment = value * 8;
9519 break;
9520 case 'W':
9521 func (stream, "%ld", value + 1);
9522 value_in_comment = value + 1;
9523 break;
9524 case 'x':
9525 func (stream, "0x%08lx", value);
9526
9527 /* Some SWI instructions have special
9528 meanings. */
9529 if ((given & 0x0fffffff) == 0x0FF00000)
9530 func (stream, "\t; IMB");
9531 else if ((given & 0x0fffffff) == 0x0FF00001)
9532 func (stream, "\t; IMBRange");
9533 break;
9534 case 'X':
9535 func (stream, "%01lx", value & 0xf);
9536 value_in_comment = value;
9537 break;
9538 case '`':
9539 c++;
9540 if (value == 0)
9541 func (stream, "%c", *c);
9542 break;
9543 case '\'':
9544 c++;
9545 if (value == ((1ul << width) - 1))
9546 func (stream, "%c", *c);
9547 break;
9548 case '?':
9549 func (stream, "%c", c[(1 << width) - (int) value]);
9550 c += 1 << width;
9551 break;
9552 default:
9553 abort ();
9554 }
9555 }
9556 break;
9557
9558 case 'e':
9559 {
9560 int imm;
9561
9562 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
9563 func (stream, "%d", imm);
9564 value_in_comment = imm;
9565 }
9566 break;
9567
9568 case 'E':
9569 /* LSB and WIDTH fields of BFI or BFC. The machine-
9570 language instruction encodes LSB and MSB. */
9571 {
9572 long msb = (given & 0x001f0000) >> 16;
9573 long lsb = (given & 0x00000f80) >> 7;
9574 long w = msb - lsb + 1;
9575
9576 if (w > 0)
9577 func (stream, "#%lu, #%lu", lsb, w);
9578 else
9579 func (stream, "(invalid: %lu:%lu)", lsb, msb);
9580 }
9581 break;
9582
9583 case 'R':
9584 /* Get the PSR/banked register name. */
9585 {
9586 const char * name;
9587 unsigned sysm = (given & 0x004f0000) >> 16;
9588
9589 sysm |= (given & 0x300) >> 4;
9590 name = banked_regname (sysm);
9591
9592 if (name != NULL)
9593 func (stream, "%s", name);
9594 else
9595 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
9596 }
9597 break;
9598
9599 case 'V':
9600 /* 16-bit unsigned immediate from a MOVT or MOVW
9601 instruction, encoded in bits 0:11 and 15:19. */
9602 {
9603 long hi = (given & 0x000f0000) >> 4;
9604 long lo = (given & 0x00000fff);
9605 long imm16 = hi | lo;
9606
9607 func (stream, "#%lu", imm16);
9608 value_in_comment = imm16;
9609 }
9610 break;
9611
9612 default:
9613 abort ();
9614 }
9615 }
9616 else
9617 func (stream, "%c", *c);
9618 }
9619
9620 if (value_in_comment > 32 || value_in_comment < -16)
9621 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
9622
9623 if (is_unpredictable)
9624 func (stream, UNPREDICTABLE_INSTRUCTION);
9625
9626 return;
9627 }
9628 }
9629 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
9630 return;
9631 }
9632
9633 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
9634
9635 static void
9636 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
9637 {
9638 const struct opcode16 *insn;
9639 void *stream = info->stream;
9640 fprintf_ftype func = info->fprintf_func;
9641
9642 for (insn = thumb_opcodes; insn->assembler; insn++)
9643 if ((given & insn->mask) == insn->value)
9644 {
9645 signed long value_in_comment = 0;
9646 const char *c = insn->assembler;
9647
9648 for (; *c; c++)
9649 {
9650 int domaskpc = 0;
9651 int domasklr = 0;
9652
9653 if (*c != '%')
9654 {
9655 func (stream, "%c", *c);
9656 continue;
9657 }
9658
9659 switch (*++c)
9660 {
9661 case '%':
9662 func (stream, "%%");
9663 break;
9664
9665 case 'c':
9666 if (ifthen_state)
9667 func (stream, "%s", arm_conditional[IFTHEN_COND]);
9668 break;
9669
9670 case 'C':
9671 if (ifthen_state)
9672 func (stream, "%s", arm_conditional[IFTHEN_COND]);
9673 else
9674 func (stream, "s");
9675 break;
9676
9677 case 'I':
9678 {
9679 unsigned int tmp;
9680
9681 ifthen_next_state = given & 0xff;
9682 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
9683 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
9684 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
9685 }
9686 break;
9687
9688 case 'x':
9689 if (ifthen_next_state)
9690 func (stream, "\t; unpredictable branch in IT block\n");
9691 break;
9692
9693 case 'X':
9694 if (ifthen_state)
9695 func (stream, "\t; unpredictable <IT:%s>",
9696 arm_conditional[IFTHEN_COND]);
9697 break;
9698
9699 case 'S':
9700 {
9701 long reg;
9702
9703 reg = (given >> 3) & 0x7;
9704 if (given & (1 << 6))
9705 reg += 8;
9706
9707 func (stream, "%s", arm_regnames[reg]);
9708 }
9709 break;
9710
9711 case 'D':
9712 {
9713 long reg;
9714
9715 reg = given & 0x7;
9716 if (given & (1 << 7))
9717 reg += 8;
9718
9719 func (stream, "%s", arm_regnames[reg]);
9720 }
9721 break;
9722
9723 case 'N':
9724 if (given & (1 << 8))
9725 domasklr = 1;
9726 /* Fall through. */
9727 case 'O':
9728 if (*c == 'O' && (given & (1 << 8)))
9729 domaskpc = 1;
9730 /* Fall through. */
9731 case 'M':
9732 {
9733 int started = 0;
9734 int reg;
9735
9736 func (stream, "{");
9737
9738 /* It would be nice if we could spot
9739 ranges, and generate the rS-rE format: */
9740 for (reg = 0; (reg < 8); reg++)
9741 if ((given & (1 << reg)) != 0)
9742 {
9743 if (started)
9744 func (stream, ", ");
9745 started = 1;
9746 func (stream, "%s", arm_regnames[reg]);
9747 }
9748
9749 if (domasklr)
9750 {
9751 if (started)
9752 func (stream, ", ");
9753 started = 1;
9754 func (stream, "%s", arm_regnames[14] /* "lr" */);
9755 }
9756
9757 if (domaskpc)
9758 {
9759 if (started)
9760 func (stream, ", ");
9761 func (stream, "%s", arm_regnames[15] /* "pc" */);
9762 }
9763
9764 func (stream, "}");
9765 }
9766 break;
9767
9768 case 'W':
9769 /* Print writeback indicator for a LDMIA. We are doing a
9770 writeback if the base register is not in the register
9771 mask. */
9772 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
9773 func (stream, "!");
9774 break;
9775
9776 case 'b':
9777 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
9778 {
9779 bfd_vma address = (pc + 4
9780 + ((given & 0x00f8) >> 2)
9781 + ((given & 0x0200) >> 3));
9782 info->print_address_func (address, info);
9783 }
9784 break;
9785
9786 case 's':
9787 /* Right shift immediate -- bits 6..10; 1-31 print
9788 as themselves, 0 prints as 32. */
9789 {
9790 long imm = (given & 0x07c0) >> 6;
9791 if (imm == 0)
9792 imm = 32;
9793 func (stream, "#%ld", imm);
9794 }
9795 break;
9796
9797 case '0': case '1': case '2': case '3': case '4':
9798 case '5': case '6': case '7': case '8': case '9':
9799 {
9800 int bitstart = *c++ - '0';
9801 int bitend = 0;
9802
9803 while (*c >= '0' && *c <= '9')
9804 bitstart = (bitstart * 10) + *c++ - '0';
9805
9806 switch (*c)
9807 {
9808 case '-':
9809 {
9810 bfd_vma reg;
9811
9812 c++;
9813 while (*c >= '0' && *c <= '9')
9814 bitend = (bitend * 10) + *c++ - '0';
9815 if (!bitend)
9816 abort ();
9817 reg = given >> bitstart;
9818 reg &= (2 << (bitend - bitstart)) - 1;
9819
9820 switch (*c)
9821 {
9822 case 'r':
9823 func (stream, "%s", arm_regnames[reg]);
9824 break;
9825
9826 case 'd':
9827 func (stream, "%ld", (long) reg);
9828 value_in_comment = reg;
9829 break;
9830
9831 case 'H':
9832 func (stream, "%ld", (long) (reg << 1));
9833 value_in_comment = reg << 1;
9834 break;
9835
9836 case 'W':
9837 func (stream, "%ld", (long) (reg << 2));
9838 value_in_comment = reg << 2;
9839 break;
9840
9841 case 'a':
9842 /* PC-relative address -- the bottom two
9843 bits of the address are dropped
9844 before the calculation. */
9845 info->print_address_func
9846 (((pc + 4) & ~3) + (reg << 2), info);
9847 value_in_comment = 0;
9848 break;
9849
9850 case 'x':
9851 func (stream, "0x%04lx", (long) reg);
9852 break;
9853
9854 case 'B':
9855 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
9856 info->print_address_func (reg * 2 + pc + 4, info);
9857 value_in_comment = 0;
9858 break;
9859
9860 case 'c':
9861 func (stream, "%s", arm_conditional [reg]);
9862 break;
9863
9864 default:
9865 abort ();
9866 }
9867 }
9868 break;
9869
9870 case '\'':
9871 c++;
9872 if ((given & (1 << bitstart)) != 0)
9873 func (stream, "%c", *c);
9874 break;
9875
9876 case '?':
9877 ++c;
9878 if ((given & (1 << bitstart)) != 0)
9879 func (stream, "%c", *c++);
9880 else
9881 func (stream, "%c", *++c);
9882 break;
9883
9884 default:
9885 abort ();
9886 }
9887 }
9888 break;
9889
9890 default:
9891 abort ();
9892 }
9893 }
9894
9895 if (value_in_comment > 32 || value_in_comment < -16)
9896 func (stream, "\t; 0x%lx", value_in_comment);
9897 return;
9898 }
9899
9900 /* No match. */
9901 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
9902 return;
9903 }
9904
9905 /* Return the name of an V7M special register. */
9906
9907 static const char *
9908 psr_name (int regno)
9909 {
9910 switch (regno)
9911 {
9912 case 0x0: return "APSR";
9913 case 0x1: return "IAPSR";
9914 case 0x2: return "EAPSR";
9915 case 0x3: return "PSR";
9916 case 0x5: return "IPSR";
9917 case 0x6: return "EPSR";
9918 case 0x7: return "IEPSR";
9919 case 0x8: return "MSP";
9920 case 0x9: return "PSP";
9921 case 0xa: return "MSPLIM";
9922 case 0xb: return "PSPLIM";
9923 case 0x10: return "PRIMASK";
9924 case 0x11: return "BASEPRI";
9925 case 0x12: return "BASEPRI_MAX";
9926 case 0x13: return "FAULTMASK";
9927 case 0x14: return "CONTROL";
9928 case 0x88: return "MSP_NS";
9929 case 0x89: return "PSP_NS";
9930 case 0x8a: return "MSPLIM_NS";
9931 case 0x8b: return "PSPLIM_NS";
9932 case 0x90: return "PRIMASK_NS";
9933 case 0x91: return "BASEPRI_NS";
9934 case 0x93: return "FAULTMASK_NS";
9935 case 0x94: return "CONTROL_NS";
9936 case 0x98: return "SP_NS";
9937 default: return "<unknown>";
9938 }
9939 }
9940
9941 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
9942
9943 static void
9944 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
9945 {
9946 const struct opcode32 *insn;
9947 void *stream = info->stream;
9948 fprintf_ftype func = info->fprintf_func;
9949 bfd_boolean is_mve = is_mve_architecture (info);
9950
9951 if (print_insn_coprocessor (pc, info, given, TRUE))
9952 return;
9953
9954 if ((is_mve == FALSE) && print_insn_neon (info, given, TRUE))
9955 return;
9956
9957 if (is_mve && print_insn_mve (info, given))
9958 return;
9959
9960 for (insn = thumb32_opcodes; insn->assembler; insn++)
9961 if ((given & insn->mask) == insn->value)
9962 {
9963 bfd_boolean is_clrm = FALSE;
9964 bfd_boolean is_unpredictable = FALSE;
9965 signed long value_in_comment = 0;
9966 const char *c = insn->assembler;
9967
9968 for (; *c; c++)
9969 {
9970 if (*c != '%')
9971 {
9972 func (stream, "%c", *c);
9973 continue;
9974 }
9975
9976 switch (*++c)
9977 {
9978 case '%':
9979 func (stream, "%%");
9980 break;
9981
9982 case 'c':
9983 if (ifthen_state)
9984 func (stream, "%s", arm_conditional[IFTHEN_COND]);
9985 break;
9986
9987 case 'x':
9988 if (ifthen_next_state)
9989 func (stream, "\t; unpredictable branch in IT block\n");
9990 break;
9991
9992 case 'X':
9993 if (ifthen_state)
9994 func (stream, "\t; unpredictable <IT:%s>",
9995 arm_conditional[IFTHEN_COND]);
9996 break;
9997
9998 case 'I':
9999 {
10000 unsigned int imm12 = 0;
10001
10002 imm12 |= (given & 0x000000ffu);
10003 imm12 |= (given & 0x00007000u) >> 4;
10004 imm12 |= (given & 0x04000000u) >> 15;
10005 func (stream, "#%u", imm12);
10006 value_in_comment = imm12;
10007 }
10008 break;
10009
10010 case 'M':
10011 {
10012 unsigned int bits = 0, imm, imm8, mod;
10013
10014 bits |= (given & 0x000000ffu);
10015 bits |= (given & 0x00007000u) >> 4;
10016 bits |= (given & 0x04000000u) >> 15;
10017 imm8 = (bits & 0x0ff);
10018 mod = (bits & 0xf00) >> 8;
10019 switch (mod)
10020 {
10021 case 0: imm = imm8; break;
10022 case 1: imm = ((imm8 << 16) | imm8); break;
10023 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
10024 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
10025 default:
10026 mod = (bits & 0xf80) >> 7;
10027 imm8 = (bits & 0x07f) | 0x80;
10028 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
10029 }
10030 func (stream, "#%u", imm);
10031 value_in_comment = imm;
10032 }
10033 break;
10034
10035 case 'J':
10036 {
10037 unsigned int imm = 0;
10038
10039 imm |= (given & 0x000000ffu);
10040 imm |= (given & 0x00007000u) >> 4;
10041 imm |= (given & 0x04000000u) >> 15;
10042 imm |= (given & 0x000f0000u) >> 4;
10043 func (stream, "#%u", imm);
10044 value_in_comment = imm;
10045 }
10046 break;
10047
10048 case 'K':
10049 {
10050 unsigned int imm = 0;
10051
10052 imm |= (given & 0x000f0000u) >> 16;
10053 imm |= (given & 0x00000ff0u) >> 0;
10054 imm |= (given & 0x0000000fu) << 12;
10055 func (stream, "#%u", imm);
10056 value_in_comment = imm;
10057 }
10058 break;
10059
10060 case 'H':
10061 {
10062 unsigned int imm = 0;
10063
10064 imm |= (given & 0x000f0000u) >> 4;
10065 imm |= (given & 0x00000fffu) >> 0;
10066 func (stream, "#%u", imm);
10067 value_in_comment = imm;
10068 }
10069 break;
10070
10071 case 'V':
10072 {
10073 unsigned int imm = 0;
10074
10075 imm |= (given & 0x00000fffu);
10076 imm |= (given & 0x000f0000u) >> 4;
10077 func (stream, "#%u", imm);
10078 value_in_comment = imm;
10079 }
10080 break;
10081
10082 case 'S':
10083 {
10084 unsigned int reg = (given & 0x0000000fu);
10085 unsigned int stp = (given & 0x00000030u) >> 4;
10086 unsigned int imm = 0;
10087 imm |= (given & 0x000000c0u) >> 6;
10088 imm |= (given & 0x00007000u) >> 10;
10089
10090 func (stream, "%s", arm_regnames[reg]);
10091 switch (stp)
10092 {
10093 case 0:
10094 if (imm > 0)
10095 func (stream, ", lsl #%u", imm);
10096 break;
10097
10098 case 1:
10099 if (imm == 0)
10100 imm = 32;
10101 func (stream, ", lsr #%u", imm);
10102 break;
10103
10104 case 2:
10105 if (imm == 0)
10106 imm = 32;
10107 func (stream, ", asr #%u", imm);
10108 break;
10109
10110 case 3:
10111 if (imm == 0)
10112 func (stream, ", rrx");
10113 else
10114 func (stream, ", ror #%u", imm);
10115 }
10116 }
10117 break;
10118
10119 case 'a':
10120 {
10121 unsigned int Rn = (given & 0x000f0000) >> 16;
10122 unsigned int U = ! NEGATIVE_BIT_SET;
10123 unsigned int op = (given & 0x00000f00) >> 8;
10124 unsigned int i12 = (given & 0x00000fff);
10125 unsigned int i8 = (given & 0x000000ff);
10126 bfd_boolean writeback = FALSE, postind = FALSE;
10127 bfd_vma offset = 0;
10128
10129 func (stream, "[%s", arm_regnames[Rn]);
10130 if (U) /* 12-bit positive immediate offset. */
10131 {
10132 offset = i12;
10133 if (Rn != 15)
10134 value_in_comment = offset;
10135 }
10136 else if (Rn == 15) /* 12-bit negative immediate offset. */
10137 offset = - (int) i12;
10138 else if (op == 0x0) /* Shifted register offset. */
10139 {
10140 unsigned int Rm = (i8 & 0x0f);
10141 unsigned int sh = (i8 & 0x30) >> 4;
10142
10143 func (stream, ", %s", arm_regnames[Rm]);
10144 if (sh)
10145 func (stream, ", lsl #%u", sh);
10146 func (stream, "]");
10147 break;
10148 }
10149 else switch (op)
10150 {
10151 case 0xE: /* 8-bit positive immediate offset. */
10152 offset = i8;
10153 break;
10154
10155 case 0xC: /* 8-bit negative immediate offset. */
10156 offset = -i8;
10157 break;
10158
10159 case 0xF: /* 8-bit + preindex with wb. */
10160 offset = i8;
10161 writeback = TRUE;
10162 break;
10163
10164 case 0xD: /* 8-bit - preindex with wb. */
10165 offset = -i8;
10166 writeback = TRUE;
10167 break;
10168
10169 case 0xB: /* 8-bit + postindex. */
10170 offset = i8;
10171 postind = TRUE;
10172 break;
10173
10174 case 0x9: /* 8-bit - postindex. */
10175 offset = -i8;
10176 postind = TRUE;
10177 break;
10178
10179 default:
10180 func (stream, ", <undefined>]");
10181 goto skip;
10182 }
10183
10184 if (postind)
10185 func (stream, "], #%d", (int) offset);
10186 else
10187 {
10188 if (offset)
10189 func (stream, ", #%d", (int) offset);
10190 func (stream, writeback ? "]!" : "]");
10191 }
10192
10193 if (Rn == 15)
10194 {
10195 func (stream, "\t; ");
10196 info->print_address_func (((pc + 4) & ~3) + offset, info);
10197 }
10198 }
10199 skip:
10200 break;
10201
10202 case 'A':
10203 {
10204 unsigned int U = ! NEGATIVE_BIT_SET;
10205 unsigned int W = WRITEBACK_BIT_SET;
10206 unsigned int Rn = (given & 0x000f0000) >> 16;
10207 unsigned int off = (given & 0x000000ff);
10208
10209 func (stream, "[%s", arm_regnames[Rn]);
10210
10211 if (PRE_BIT_SET)
10212 {
10213 if (off || !U)
10214 {
10215 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
10216 value_in_comment = off * 4 * (U ? 1 : -1);
10217 }
10218 func (stream, "]");
10219 if (W)
10220 func (stream, "!");
10221 }
10222 else
10223 {
10224 func (stream, "], ");
10225 if (W)
10226 {
10227 func (stream, "#%c%u", U ? '+' : '-', off * 4);
10228 value_in_comment = off * 4 * (U ? 1 : -1);
10229 }
10230 else
10231 {
10232 func (stream, "{%u}", off);
10233 value_in_comment = off;
10234 }
10235 }
10236 }
10237 break;
10238
10239 case 'w':
10240 {
10241 unsigned int Sbit = (given & 0x01000000) >> 24;
10242 unsigned int type = (given & 0x00600000) >> 21;
10243
10244 switch (type)
10245 {
10246 case 0: func (stream, Sbit ? "sb" : "b"); break;
10247 case 1: func (stream, Sbit ? "sh" : "h"); break;
10248 case 2:
10249 if (Sbit)
10250 func (stream, "??");
10251 break;
10252 case 3:
10253 func (stream, "??");
10254 break;
10255 }
10256 }
10257 break;
10258
10259 case 'n':
10260 is_clrm = TRUE;
10261 /* Fall through. */
10262 case 'm':
10263 {
10264 int started = 0;
10265 int reg;
10266
10267 func (stream, "{");
10268 for (reg = 0; reg < 16; reg++)
10269 if ((given & (1 << reg)) != 0)
10270 {
10271 if (started)
10272 func (stream, ", ");
10273 started = 1;
10274 if (is_clrm && reg == 13)
10275 func (stream, "(invalid: %s)", arm_regnames[reg]);
10276 else if (is_clrm && reg == 15)
10277 func (stream, "%s", "APSR");
10278 else
10279 func (stream, "%s", arm_regnames[reg]);
10280 }
10281 func (stream, "}");
10282 }
10283 break;
10284
10285 case 'E':
10286 {
10287 unsigned int msb = (given & 0x0000001f);
10288 unsigned int lsb = 0;
10289
10290 lsb |= (given & 0x000000c0u) >> 6;
10291 lsb |= (given & 0x00007000u) >> 10;
10292 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
10293 }
10294 break;
10295
10296 case 'F':
10297 {
10298 unsigned int width = (given & 0x0000001f) + 1;
10299 unsigned int lsb = 0;
10300
10301 lsb |= (given & 0x000000c0u) >> 6;
10302 lsb |= (given & 0x00007000u) >> 10;
10303 func (stream, "#%u, #%u", lsb, width);
10304 }
10305 break;
10306
10307 case 'G':
10308 {
10309 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
10310 func (stream, "%x", boff);
10311 }
10312 break;
10313
10314 case 'W':
10315 {
10316 unsigned int immA = (given & 0x001f0000u) >> 16;
10317 unsigned int immB = (given & 0x000007feu) >> 1;
10318 unsigned int immC = (given & 0x00000800u) >> 11;
10319 bfd_vma offset = 0;
10320
10321 offset |= immA << 12;
10322 offset |= immB << 2;
10323 offset |= immC << 1;
10324 /* Sign extend. */
10325 offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
10326
10327 info->print_address_func (pc + 4 + offset, info);
10328 }
10329 break;
10330
10331 case 'Y':
10332 {
10333 unsigned int immA = (given & 0x007f0000u) >> 16;
10334 unsigned int immB = (given & 0x000007feu) >> 1;
10335 unsigned int immC = (given & 0x00000800u) >> 11;
10336 bfd_vma offset = 0;
10337
10338 offset |= immA << 12;
10339 offset |= immB << 2;
10340 offset |= immC << 1;
10341 /* Sign extend. */
10342 offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
10343
10344 info->print_address_func (pc + 4 + offset, info);
10345 }
10346 break;
10347
10348 case 'Z':
10349 {
10350 unsigned int immA = (given & 0x00010000u) >> 16;
10351 unsigned int immB = (given & 0x000007feu) >> 1;
10352 unsigned int immC = (given & 0x00000800u) >> 11;
10353 bfd_vma offset = 0;
10354
10355 offset |= immA << 12;
10356 offset |= immB << 2;
10357 offset |= immC << 1;
10358 /* Sign extend. */
10359 offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
10360
10361 info->print_address_func (pc + 4 + offset, info);
10362
10363 unsigned int T = (given & 0x00020000u) >> 17;
10364 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
10365 unsigned int boffset = (T == 1) ? 4 : 2;
10366 func (stream, ", ");
10367 func (stream, "%x", endoffset + boffset);
10368 }
10369 break;
10370
10371 case 'Q':
10372 {
10373 unsigned int immh = (given & 0x000007feu) >> 1;
10374 unsigned int imml = (given & 0x00000800u) >> 11;
10375 bfd_vma imm32 = 0;
10376
10377 imm32 |= immh << 2;
10378 imm32 |= imml << 1;
10379
10380 info->print_address_func (pc + 4 + imm32, info);
10381 }
10382 break;
10383
10384 case 'P':
10385 {
10386 unsigned int immh = (given & 0x000007feu) >> 1;
10387 unsigned int imml = (given & 0x00000800u) >> 11;
10388 bfd_vma imm32 = 0;
10389
10390 imm32 |= immh << 2;
10391 imm32 |= imml << 1;
10392
10393 info->print_address_func (pc + 4 - imm32, info);
10394 }
10395 break;
10396
10397 case 'b':
10398 {
10399 unsigned int S = (given & 0x04000000u) >> 26;
10400 unsigned int J1 = (given & 0x00002000u) >> 13;
10401 unsigned int J2 = (given & 0x00000800u) >> 11;
10402 bfd_vma offset = 0;
10403
10404 offset |= !S << 20;
10405 offset |= J2 << 19;
10406 offset |= J1 << 18;
10407 offset |= (given & 0x003f0000) >> 4;
10408 offset |= (given & 0x000007ff) << 1;
10409 offset -= (1 << 20);
10410
10411 info->print_address_func (pc + 4 + offset, info);
10412 }
10413 break;
10414
10415 case 'B':
10416 {
10417 unsigned int S = (given & 0x04000000u) >> 26;
10418 unsigned int I1 = (given & 0x00002000u) >> 13;
10419 unsigned int I2 = (given & 0x00000800u) >> 11;
10420 bfd_vma offset = 0;
10421
10422 offset |= !S << 24;
10423 offset |= !(I1 ^ S) << 23;
10424 offset |= !(I2 ^ S) << 22;
10425 offset |= (given & 0x03ff0000u) >> 4;
10426 offset |= (given & 0x000007ffu) << 1;
10427 offset -= (1 << 24);
10428 offset += pc + 4;
10429
10430 /* BLX target addresses are always word aligned. */
10431 if ((given & 0x00001000u) == 0)
10432 offset &= ~2u;
10433
10434 info->print_address_func (offset, info);
10435 }
10436 break;
10437
10438 case 's':
10439 {
10440 unsigned int shift = 0;
10441
10442 shift |= (given & 0x000000c0u) >> 6;
10443 shift |= (given & 0x00007000u) >> 10;
10444 if (WRITEBACK_BIT_SET)
10445 func (stream, ", asr #%u", shift);
10446 else if (shift)
10447 func (stream, ", lsl #%u", shift);
10448 /* else print nothing - lsl #0 */
10449 }
10450 break;
10451
10452 case 'R':
10453 {
10454 unsigned int rot = (given & 0x00000030) >> 4;
10455
10456 if (rot)
10457 func (stream, ", ror #%u", rot * 8);
10458 }
10459 break;
10460
10461 case 'U':
10462 if ((given & 0xf0) == 0x60)
10463 {
10464 switch (given & 0xf)
10465 {
10466 case 0xf: func (stream, "sy"); break;
10467 default:
10468 func (stream, "#%d", (int) given & 0xf);
10469 break;
10470 }
10471 }
10472 else
10473 {
10474 const char * opt = data_barrier_option (given & 0xf);
10475 if (opt != NULL)
10476 func (stream, "%s", opt);
10477 else
10478 func (stream, "#%d", (int) given & 0xf);
10479 }
10480 break;
10481
10482 case 'C':
10483 if ((given & 0xff) == 0)
10484 {
10485 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
10486 if (given & 0x800)
10487 func (stream, "f");
10488 if (given & 0x400)
10489 func (stream, "s");
10490 if (given & 0x200)
10491 func (stream, "x");
10492 if (given & 0x100)
10493 func (stream, "c");
10494 }
10495 else if ((given & 0x20) == 0x20)
10496 {
10497 char const* name;
10498 unsigned sysm = (given & 0xf00) >> 8;
10499
10500 sysm |= (given & 0x30);
10501 sysm |= (given & 0x00100000) >> 14;
10502 name = banked_regname (sysm);
10503
10504 if (name != NULL)
10505 func (stream, "%s", name);
10506 else
10507 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
10508 }
10509 else
10510 {
10511 func (stream, "%s", psr_name (given & 0xff));
10512 }
10513 break;
10514
10515 case 'D':
10516 if (((given & 0xff) == 0)
10517 || ((given & 0x20) == 0x20))
10518 {
10519 char const* name;
10520 unsigned sm = (given & 0xf0000) >> 16;
10521
10522 sm |= (given & 0x30);
10523 sm |= (given & 0x00100000) >> 14;
10524 name = banked_regname (sm);
10525
10526 if (name != NULL)
10527 func (stream, "%s", name);
10528 else
10529 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
10530 }
10531 else
10532 func (stream, "%s", psr_name (given & 0xff));
10533 break;
10534
10535 case '0': case '1': case '2': case '3': case '4':
10536 case '5': case '6': case '7': case '8': case '9':
10537 {
10538 int width;
10539 unsigned long val;
10540
10541 c = arm_decode_bitfield (c, given, &val, &width);
10542
10543 switch (*c)
10544 {
10545 case 's':
10546 if (val <= 3)
10547 func (stream, "%s", mve_vec_sizename[val]);
10548 else
10549 func (stream, "<undef size>");
10550 break;
10551
10552 case 'd':
10553 func (stream, "%lu", val);
10554 value_in_comment = val;
10555 break;
10556
10557 case 'D':
10558 func (stream, "%lu", val + 1);
10559 value_in_comment = val + 1;
10560 break;
10561
10562 case 'W':
10563 func (stream, "%lu", val * 4);
10564 value_in_comment = val * 4;
10565 break;
10566
10567 case 'S':
10568 if (val == 13)
10569 is_unpredictable = TRUE;
10570 /* Fall through. */
10571 case 'R':
10572 if (val == 15)
10573 is_unpredictable = TRUE;
10574 /* Fall through. */
10575 case 'r':
10576 func (stream, "%s", arm_regnames[val]);
10577 break;
10578
10579 case 'c':
10580 func (stream, "%s", arm_conditional[val]);
10581 break;
10582
10583 case '\'':
10584 c++;
10585 if (val == ((1ul << width) - 1))
10586 func (stream, "%c", *c);
10587 break;
10588
10589 case '`':
10590 c++;
10591 if (val == 0)
10592 func (stream, "%c", *c);
10593 break;
10594
10595 case '?':
10596 func (stream, "%c", c[(1 << width) - (int) val]);
10597 c += 1 << width;
10598 break;
10599
10600 case 'x':
10601 func (stream, "0x%lx", val & 0xffffffffUL);
10602 break;
10603
10604 default:
10605 abort ();
10606 }
10607 }
10608 break;
10609
10610 case 'L':
10611 /* PR binutils/12534
10612 If we have a PC relative offset in an LDRD or STRD
10613 instructions then display the decoded address. */
10614 if (((given >> 16) & 0xf) == 0xf)
10615 {
10616 bfd_vma offset = (given & 0xff) * 4;
10617
10618 if ((given & (1 << 23)) == 0)
10619 offset = - offset;
10620 func (stream, "\t; ");
10621 info->print_address_func ((pc & ~3) + 4 + offset, info);
10622 }
10623 break;
10624
10625 default:
10626 abort ();
10627 }
10628 }
10629
10630 if (value_in_comment > 32 || value_in_comment < -16)
10631 func (stream, "\t; 0x%lx", value_in_comment);
10632
10633 if (is_unpredictable)
10634 func (stream, UNPREDICTABLE_INSTRUCTION);
10635
10636 return;
10637 }
10638
10639 /* No match. */
10640 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
10641 return;
10642 }
10643
10644 /* Print data bytes on INFO->STREAM. */
10645
10646 static void
10647 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
10648 struct disassemble_info *info,
10649 long given)
10650 {
10651 switch (info->bytes_per_chunk)
10652 {
10653 case 1:
10654 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
10655 break;
10656 case 2:
10657 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
10658 break;
10659 case 4:
10660 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
10661 break;
10662 default:
10663 abort ();
10664 }
10665 }
10666
10667 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
10668 being displayed in symbol relative addresses.
10669
10670 Also disallow private symbol, with __tagsym$$ prefix,
10671 from ARM RVCT toolchain being displayed. */
10672
10673 bfd_boolean
10674 arm_symbol_is_valid (asymbol * sym,
10675 struct disassemble_info * info ATTRIBUTE_UNUSED)
10676 {
10677 const char * name;
10678
10679 if (sym == NULL)
10680 return FALSE;
10681
10682 name = bfd_asymbol_name (sym);
10683
10684 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
10685 }
10686
10687 /* Parse the string of disassembler options. */
10688
10689 static void
10690 parse_arm_disassembler_options (const char *options)
10691 {
10692 const char *opt;
10693
10694 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
10695 {
10696 if (CONST_STRNEQ (opt, "reg-names-"))
10697 {
10698 unsigned int i;
10699 for (i = 0; i < NUM_ARM_OPTIONS; i++)
10700 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
10701 {
10702 regname_selected = i;
10703 break;
10704 }
10705
10706 if (i >= NUM_ARM_OPTIONS)
10707 /* xgettext: c-format */
10708 opcodes_error_handler (_("unrecognised register name set: %s"),
10709 opt);
10710 }
10711 else if (CONST_STRNEQ (opt, "force-thumb"))
10712 force_thumb = 1;
10713 else if (CONST_STRNEQ (opt, "no-force-thumb"))
10714 force_thumb = 0;
10715 else
10716 /* xgettext: c-format */
10717 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
10718 }
10719
10720 return;
10721 }
10722
10723 static bfd_boolean
10724 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
10725 enum map_type *map_symbol);
10726
10727 /* Search back through the insn stream to determine if this instruction is
10728 conditionally executed. */
10729
10730 static void
10731 find_ifthen_state (bfd_vma pc,
10732 struct disassemble_info *info,
10733 bfd_boolean little)
10734 {
10735 unsigned char b[2];
10736 unsigned int insn;
10737 int status;
10738 /* COUNT is twice the number of instructions seen. It will be odd if we
10739 just crossed an instruction boundary. */
10740 int count;
10741 int it_count;
10742 unsigned int seen_it;
10743 bfd_vma addr;
10744
10745 ifthen_address = pc;
10746 ifthen_state = 0;
10747
10748 addr = pc;
10749 count = 1;
10750 it_count = 0;
10751 seen_it = 0;
10752 /* Scan backwards looking for IT instructions, keeping track of where
10753 instruction boundaries are. We don't know if something is actually an
10754 IT instruction until we find a definite instruction boundary. */
10755 for (;;)
10756 {
10757 if (addr == 0 || info->symbol_at_address_func (addr, info))
10758 {
10759 /* A symbol must be on an instruction boundary, and will not
10760 be within an IT block. */
10761 if (seen_it && (count & 1))
10762 break;
10763
10764 return;
10765 }
10766 addr -= 2;
10767 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
10768 if (status)
10769 return;
10770
10771 if (little)
10772 insn = (b[0]) | (b[1] << 8);
10773 else
10774 insn = (b[1]) | (b[0] << 8);
10775 if (seen_it)
10776 {
10777 if ((insn & 0xf800) < 0xe800)
10778 {
10779 /* Addr + 2 is an instruction boundary. See if this matches
10780 the expected boundary based on the position of the last
10781 IT candidate. */
10782 if (count & 1)
10783 break;
10784 seen_it = 0;
10785 }
10786 }
10787 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
10788 {
10789 enum map_type type = MAP_ARM;
10790 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
10791
10792 if (!found || (found && type == MAP_THUMB))
10793 {
10794 /* This could be an IT instruction. */
10795 seen_it = insn;
10796 it_count = count >> 1;
10797 }
10798 }
10799 if ((insn & 0xf800) >= 0xe800)
10800 count++;
10801 else
10802 count = (count + 2) | 1;
10803 /* IT blocks contain at most 4 instructions. */
10804 if (count >= 8 && !seen_it)
10805 return;
10806 }
10807 /* We found an IT instruction. */
10808 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
10809 if ((ifthen_state & 0xf) == 0)
10810 ifthen_state = 0;
10811 }
10812
10813 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
10814 mapping symbol. */
10815
10816 static int
10817 is_mapping_symbol (struct disassemble_info *info, int n,
10818 enum map_type *map_type)
10819 {
10820 const char *name;
10821
10822 name = bfd_asymbol_name (info->symtab[n]);
10823 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
10824 && (name[2] == 0 || name[2] == '.'))
10825 {
10826 *map_type = ((name[1] == 'a') ? MAP_ARM
10827 : (name[1] == 't') ? MAP_THUMB
10828 : MAP_DATA);
10829 return TRUE;
10830 }
10831
10832 return FALSE;
10833 }
10834
10835 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
10836 Returns nonzero if *MAP_TYPE was set. */
10837
10838 static int
10839 get_map_sym_type (struct disassemble_info *info,
10840 int n,
10841 enum map_type *map_type)
10842 {
10843 /* If the symbol is in a different section, ignore it. */
10844 if (info->section != NULL && info->section != info->symtab[n]->section)
10845 return FALSE;
10846
10847 return is_mapping_symbol (info, n, map_type);
10848 }
10849
10850 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
10851 Returns nonzero if *MAP_TYPE was set. */
10852
10853 static int
10854 get_sym_code_type (struct disassemble_info *info,
10855 int n,
10856 enum map_type *map_type)
10857 {
10858 elf_symbol_type *es;
10859 unsigned int type;
10860
10861 /* If the symbol is in a different section, ignore it. */
10862 if (info->section != NULL && info->section != info->symtab[n]->section)
10863 return FALSE;
10864
10865 es = *(elf_symbol_type **)(info->symtab + n);
10866 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
10867
10868 /* If the symbol has function type then use that. */
10869 if (type == STT_FUNC || type == STT_GNU_IFUNC)
10870 {
10871 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
10872 == ST_BRANCH_TO_THUMB)
10873 *map_type = MAP_THUMB;
10874 else
10875 *map_type = MAP_ARM;
10876 return TRUE;
10877 }
10878
10879 return FALSE;
10880 }
10881
10882 /* Search the mapping symbol state for instruction at pc. This is only
10883 applicable for elf target.
10884
10885 There is an assumption Here, info->private_data contains the correct AND
10886 up-to-date information about current scan process. The information will be
10887 used to speed this search process.
10888
10889 Return TRUE if the mapping state can be determined, and map_symbol
10890 will be updated accordingly. Otherwise, return FALSE. */
10891
10892 static bfd_boolean
10893 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
10894 enum map_type *map_symbol)
10895 {
10896 bfd_vma addr, section_vma = 0;
10897 int n, last_sym = -1;
10898 bfd_boolean found = FALSE;
10899 bfd_boolean can_use_search_opt_p = FALSE;
10900
10901 /* Default to DATA. A text section is required by the ABI to contain an
10902 INSN mapping symbol at the start. A data section has no such
10903 requirement, hence if no mapping symbol is found the section must
10904 contain only data. This however isn't very useful if the user has
10905 fully stripped the binaries. If this is the case use the section
10906 attributes to determine the default. If we have no section default to
10907 INSN as well, as we may be disassembling some raw bytes on a baremetal
10908 HEX file or similar. */
10909 enum map_type type = MAP_DATA;
10910 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
10911 type = MAP_ARM;
10912 struct arm_private_data *private_data;
10913
10914 if (info->private_data == NULL
10915 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
10916 return FALSE;
10917
10918 private_data = info->private_data;
10919
10920 /* First, look for mapping symbols. */
10921 if (info->symtab_size != 0)
10922 {
10923 if (pc <= private_data->last_mapping_addr)
10924 private_data->last_mapping_sym = -1;
10925
10926 /* Start scanning at the start of the function, or wherever
10927 we finished last time. */
10928 n = info->symtab_pos + 1;
10929
10930 /* If the last stop offset is different from the current one it means we
10931 are disassembling a different glob of bytes. As such the optimization
10932 would not be safe and we should start over. */
10933 can_use_search_opt_p
10934 = private_data->last_mapping_sym >= 0
10935 && info->stop_offset == private_data->last_stop_offset;
10936
10937 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
10938 n = private_data->last_mapping_sym;
10939
10940 /* Look down while we haven't passed the location being disassembled.
10941 The reason for this is that there's no defined order between a symbol
10942 and an mapping symbol that may be at the same address. We may have to
10943 look at least one position ahead. */
10944 for (; n < info->symtab_size; n++)
10945 {
10946 addr = bfd_asymbol_value (info->symtab[n]);
10947 if (addr > pc)
10948 break;
10949 if (get_map_sym_type (info, n, &type))
10950 {
10951 last_sym = n;
10952 found = TRUE;
10953 }
10954 }
10955
10956 if (!found)
10957 {
10958 n = info->symtab_pos;
10959 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
10960 n = private_data->last_mapping_sym;
10961
10962 /* No mapping symbol found at this address. Look backwards
10963 for a preceeding one, but don't go pass the section start
10964 otherwise a data section with no mapping symbol can pick up
10965 a text mapping symbol of a preceeding section. The documentation
10966 says section can be NULL, in which case we will seek up all the
10967 way to the top. */
10968 if (info->section)
10969 section_vma = info->section->vma;
10970
10971 for (; n >= 0; n--)
10972 {
10973 addr = bfd_asymbol_value (info->symtab[n]);
10974 if (addr < section_vma)
10975 break;
10976
10977 if (get_map_sym_type (info, n, &type))
10978 {
10979 last_sym = n;
10980 found = TRUE;
10981 break;
10982 }
10983 }
10984 }
10985 }
10986
10987 /* If no mapping symbol was found, try looking up without a mapping
10988 symbol. This is done by walking up from the current PC to the nearest
10989 symbol. We don't actually have to loop here since symtab_pos will
10990 contain the nearest symbol already. */
10991 if (!found)
10992 {
10993 n = info->symtab_pos;
10994 if (n >= 0 && get_sym_code_type (info, n, &type))
10995 {
10996 last_sym = n;
10997 found = TRUE;
10998 }
10999 }
11000
11001 private_data->last_mapping_sym = last_sym;
11002 private_data->last_type = type;
11003 private_data->last_stop_offset = info->stop_offset;
11004
11005 *map_symbol = type;
11006 return found;
11007 }
11008
11009 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
11010 of the supplied arm_feature_set structure with bitmasks indicating
11011 the supported base architectures and coprocessor extensions.
11012
11013 FIXME: This could more efficiently implemented as a constant array,
11014 although it would also be less robust. */
11015
11016 static void
11017 select_arm_features (unsigned long mach,
11018 arm_feature_set * features)
11019 {
11020 arm_feature_set arch_fset;
11021 const arm_feature_set fpu_any = FPU_ANY;
11022
11023 #undef ARM_SET_FEATURES
11024 #define ARM_SET_FEATURES(FSET) \
11025 { \
11026 const arm_feature_set fset = FSET; \
11027 arch_fset = fset; \
11028 }
11029
11030 /* When several architecture versions share the same bfd_mach_arm_XXX value
11031 the most featureful is chosen. */
11032 switch (mach)
11033 {
11034 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
11035 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
11036 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
11037 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
11038 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
11039 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
11040 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
11041 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
11042 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
11043 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
11044 case bfd_mach_arm_ep9312:
11045 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
11046 ARM_CEXT_MAVERICK | FPU_MAVERICK));
11047 break;
11048 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
11049 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
11050 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
11051 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
11052 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
11053 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
11054 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
11055 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
11056 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
11057 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
11058 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
11059 case bfd_mach_arm_8:
11060 {
11061 /* Add bits for extensions that Armv8.5-A recognizes. */
11062 arm_feature_set armv8_5_ext_fset
11063 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
11064 ARM_SET_FEATURES (ARM_ARCH_V8_5A);
11065 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset);
11066 break;
11067 }
11068 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
11069 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
11070 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
11071 case bfd_mach_arm_8_1M_MAIN:
11072 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
11073 force_thumb = 1;
11074 break;
11075 /* If the machine type is unknown allow all architecture types and all
11076 extensions. */
11077 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
11078 default:
11079 abort ();
11080 }
11081 #undef ARM_SET_FEATURES
11082
11083 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
11084 and thus on bfd_mach_arm_XXX value. Therefore for a given
11085 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
11086 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
11087 }
11088
11089
11090 /* NOTE: There are no checks in these routines that
11091 the relevant number of data bytes exist. */
11092
11093 static int
11094 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
11095 {
11096 unsigned char b[4];
11097 long given;
11098 int status;
11099 int is_thumb = FALSE;
11100 int is_data = FALSE;
11101 int little_code;
11102 unsigned int size = 4;
11103 void (*printer) (bfd_vma, struct disassemble_info *, long);
11104 bfd_boolean found = FALSE;
11105 struct arm_private_data *private_data;
11106
11107 if (info->disassembler_options)
11108 {
11109 parse_arm_disassembler_options (info->disassembler_options);
11110
11111 /* To avoid repeated parsing of these options, we remove them here. */
11112 info->disassembler_options = NULL;
11113 }
11114
11115 /* PR 10288: Control which instructions will be disassembled. */
11116 if (info->private_data == NULL)
11117 {
11118 static struct arm_private_data private;
11119
11120 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
11121 /* If the user did not use the -m command line switch then default to
11122 disassembling all types of ARM instruction.
11123
11124 The info->mach value has to be ignored as this will be based on
11125 the default archictecture for the target and/or hints in the notes
11126 section, but it will never be greater than the current largest arm
11127 machine value (iWMMXt2), which is only equivalent to the V5TE
11128 architecture. ARM architectures have advanced beyond the machine
11129 value encoding, and these newer architectures would be ignored if
11130 the machine value was used.
11131
11132 Ie the -m switch is used to restrict which instructions will be
11133 disassembled. If it is necessary to use the -m switch to tell
11134 objdump that an ARM binary is being disassembled, eg because the
11135 input is a raw binary file, but it is also desired to disassemble
11136 all ARM instructions then use "-marm". This will select the
11137 "unknown" arm architecture which is compatible with any ARM
11138 instruction. */
11139 info->mach = bfd_mach_arm_unknown;
11140
11141 /* Compute the architecture bitmask from the machine number.
11142 Note: This assumes that the machine number will not change
11143 during disassembly.... */
11144 select_arm_features (info->mach, & private.features);
11145
11146 private.last_mapping_sym = -1;
11147 private.last_mapping_addr = 0;
11148 private.last_stop_offset = 0;
11149
11150 info->private_data = & private;
11151 }
11152
11153 private_data = info->private_data;
11154
11155 /* Decide if our code is going to be little-endian, despite what the
11156 function argument might say. */
11157 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
11158
11159 /* For ELF, consult the symbol table to determine what kind of code
11160 or data we have. */
11161 if (info->symtab_size != 0
11162 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
11163 {
11164 bfd_vma addr;
11165 int n;
11166 int last_sym = -1;
11167 enum map_type type = MAP_ARM;
11168
11169 found = mapping_symbol_for_insn (pc, info, &type);
11170 last_sym = private_data->last_mapping_sym;
11171
11172 is_thumb = (private_data->last_type == MAP_THUMB);
11173 is_data = (private_data->last_type == MAP_DATA);
11174
11175 /* Look a little bit ahead to see if we should print out
11176 two or four bytes of data. If there's a symbol,
11177 mapping or otherwise, after two bytes then don't
11178 print more. */
11179 if (is_data)
11180 {
11181 size = 4 - (pc & 3);
11182 for (n = last_sym + 1; n < info->symtab_size; n++)
11183 {
11184 addr = bfd_asymbol_value (info->symtab[n]);
11185 if (addr > pc
11186 && (info->section == NULL
11187 || info->section == info->symtab[n]->section))
11188 {
11189 if (addr - pc < size)
11190 size = addr - pc;
11191 break;
11192 }
11193 }
11194 /* If the next symbol is after three bytes, we need to
11195 print only part of the data, so that we can use either
11196 .byte or .short. */
11197 if (size == 3)
11198 size = (pc & 1) ? 1 : 2;
11199 }
11200 }
11201
11202 if (info->symbols != NULL)
11203 {
11204 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
11205 {
11206 coff_symbol_type * cs;
11207
11208 cs = coffsymbol (*info->symbols);
11209 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
11210 || cs->native->u.syment.n_sclass == C_THUMBSTAT
11211 || cs->native->u.syment.n_sclass == C_THUMBLABEL
11212 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
11213 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
11214 }
11215 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
11216 && !found)
11217 {
11218 /* If no mapping symbol has been found then fall back to the type
11219 of the function symbol. */
11220 elf_symbol_type * es;
11221 unsigned int type;
11222
11223 es = *(elf_symbol_type **)(info->symbols);
11224 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
11225
11226 is_thumb =
11227 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
11228 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
11229 }
11230 else if (bfd_asymbol_flavour (*info->symbols)
11231 == bfd_target_mach_o_flavour)
11232 {
11233 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
11234
11235 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
11236 }
11237 }
11238
11239 if (force_thumb)
11240 is_thumb = TRUE;
11241
11242 if (is_data)
11243 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
11244 else
11245 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
11246
11247 info->bytes_per_line = 4;
11248
11249 /* PR 10263: Disassemble data if requested to do so by the user. */
11250 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
11251 {
11252 int i;
11253
11254 /* Size was already set above. */
11255 info->bytes_per_chunk = size;
11256 printer = print_insn_data;
11257
11258 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
11259 given = 0;
11260 if (little)
11261 for (i = size - 1; i >= 0; i--)
11262 given = b[i] | (given << 8);
11263 else
11264 for (i = 0; i < (int) size; i++)
11265 given = b[i] | (given << 8);
11266 }
11267 else if (!is_thumb)
11268 {
11269 /* In ARM mode endianness is a straightforward issue: the instruction
11270 is four bytes long and is either ordered 0123 or 3210. */
11271 printer = print_insn_arm;
11272 info->bytes_per_chunk = 4;
11273 size = 4;
11274
11275 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
11276 if (little_code)
11277 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
11278 else
11279 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
11280 }
11281 else
11282 {
11283 /* In Thumb mode we have the additional wrinkle of two
11284 instruction lengths. Fortunately, the bits that determine
11285 the length of the current instruction are always to be found
11286 in the first two bytes. */
11287 printer = print_insn_thumb16;
11288 info->bytes_per_chunk = 2;
11289 size = 2;
11290
11291 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
11292 if (little_code)
11293 given = (b[0]) | (b[1] << 8);
11294 else
11295 given = (b[1]) | (b[0] << 8);
11296
11297 if (!status)
11298 {
11299 /* These bit patterns signal a four-byte Thumb
11300 instruction. */
11301 if ((given & 0xF800) == 0xF800
11302 || (given & 0xF800) == 0xF000
11303 || (given & 0xF800) == 0xE800)
11304 {
11305 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
11306 if (little_code)
11307 given = (b[0]) | (b[1] << 8) | (given << 16);
11308 else
11309 given = (b[1]) | (b[0] << 8) | (given << 16);
11310
11311 printer = print_insn_thumb32;
11312 size = 4;
11313 }
11314 }
11315
11316 if (ifthen_address != pc)
11317 find_ifthen_state (pc, info, little_code);
11318
11319 if (ifthen_state)
11320 {
11321 if ((ifthen_state & 0xf) == 0x8)
11322 ifthen_next_state = 0;
11323 else
11324 ifthen_next_state = (ifthen_state & 0xe0)
11325 | ((ifthen_state & 0xf) << 1);
11326 }
11327 }
11328
11329 if (status)
11330 {
11331 info->memory_error_func (status, pc, info);
11332 return -1;
11333 }
11334 if (info->flags & INSN_HAS_RELOC)
11335 /* If the instruction has a reloc associated with it, then
11336 the offset field in the instruction will actually be the
11337 addend for the reloc. (We are using REL type relocs).
11338 In such cases, we can ignore the pc when computing
11339 addresses, since the addend is not currently pc-relative. */
11340 pc = 0;
11341
11342 printer (pc, info, given);
11343
11344 if (is_thumb)
11345 {
11346 ifthen_state = ifthen_next_state;
11347 ifthen_address += size;
11348 }
11349 return size;
11350 }
11351
11352 int
11353 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
11354 {
11355 /* Detect BE8-ness and record it in the disassembler info. */
11356 if (info->flavour == bfd_target_elf_flavour
11357 && info->section != NULL
11358 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
11359 info->endian_code = BFD_ENDIAN_LITTLE;
11360
11361 return print_insn (pc, info, FALSE);
11362 }
11363
11364 int
11365 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
11366 {
11367 return print_insn (pc, info, TRUE);
11368 }
11369
11370 const disasm_options_and_args_t *
11371 disassembler_options_arm (void)
11372 {
11373 static disasm_options_and_args_t *opts_and_args;
11374
11375 if (opts_and_args == NULL)
11376 {
11377 disasm_options_t *opts;
11378 unsigned int i;
11379
11380 opts_and_args = XNEW (disasm_options_and_args_t);
11381 opts_and_args->args = NULL;
11382
11383 opts = &opts_and_args->options;
11384 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
11385 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
11386 opts->arg = NULL;
11387 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11388 {
11389 opts->name[i] = regnames[i].name;
11390 if (regnames[i].description != NULL)
11391 opts->description[i] = _(regnames[i].description);
11392 else
11393 opts->description[i] = NULL;
11394 }
11395 /* The array we return must be NULL terminated. */
11396 opts->name[i] = NULL;
11397 opts->description[i] = NULL;
11398 }
11399
11400 return opts_and_args;
11401 }
11402
11403 void
11404 print_arm_disassembler_options (FILE *stream)
11405 {
11406 unsigned int i, max_len = 0;
11407 fprintf (stream, _("\n\
11408 The following ARM specific disassembler options are supported for use with\n\
11409 the -M switch:\n"));
11410
11411 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11412 {
11413 unsigned int len = strlen (regnames[i].name);
11414 if (max_len < len)
11415 max_len = len;
11416 }
11417
11418 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
11419 fprintf (stream, " %s%*c %s\n",
11420 regnames[i].name,
11421 (int)(max_len - strlen (regnames[i].name)), ' ',
11422 _(regnames[i].description));
11423 }
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