1 /* Instruction printing code for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
6 This file is part of libopcodes.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
25 #include "disassemble.h"
26 #include "opcode/arm.h"
28 #include "safe-ctype.h"
29 #include "libiberty.h"
30 #include "floatformat.h"
32 /* FIXME: This shouldn't be done here. */
33 #include "coff/internal.h"
37 #include "elf/internal.h"
41 /* FIXME: Belongs in global header. */
43 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
46 /* Cached mapping symbol state. */
54 struct arm_private_data
56 /* The features to use when disassembling optional instructions. */
57 arm_feature_set features
;
59 /* Track the last type (although this doesn't seem to be useful) */
60 enum map_type last_type
;
62 /* Tracking symbol table information */
65 /* The end range of the current range being disassembled. */
66 bfd_vma last_stop_offset
;
67 bfd_vma last_mapping_addr
;
75 enum mve_unpredictable
77 UNPRED_IT_BLOCK
, /* Unpredictable because mve insn in it block.
79 UNPRED_NONE
/* No unpredictable behavior. */
84 UNDEF_NONE
/* no undefined behavior. */
89 arm_feature_set arch
; /* Architecture defining this insn. */
90 unsigned long value
; /* If arch is 0 then value is a sentinel. */
91 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
92 const char * assembler
; /* How to disassemble this insn. */
99 arm_feature_set arch
; /* Architecture defining this insn. */
100 enum mve_instructions mve_op
; /* Specific mve instruction for faster
102 unsigned long value
; /* If arch is 0 then value is a sentinel. */
103 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
104 const char * assembler
; /* How to disassemble this insn. */
114 /* Shared (between Arm and Thumb mode) opcode. */
117 enum isa isa
; /* Execution mode instruction availability. */
118 arm_feature_set arch
; /* Architecture defining this insn. */
119 unsigned long value
; /* If arch is 0 then value is a sentinel. */
120 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
121 const char * assembler
; /* How to disassemble this insn. */
126 arm_feature_set arch
; /* Architecture defining this insn. */
127 unsigned short value
, mask
; /* Recognise insn if (op & mask) == value. */
128 const char *assembler
; /* How to disassemble this insn. */
131 /* print_insn_coprocessor recognizes the following format control codes:
135 %c print condition code (always bits 28-31 in ARM mode)
136 %q print shifter argument
137 %u print condition code (unconditional in ARM mode,
138 UNPREDICTABLE if not AL in Thumb)
139 %A print address for ldc/stc/ldf/stf instruction
140 %B print vstm/vldm register list
141 %C print vscclrm register list
142 %I print cirrus signed shift immediate: bits 0..3|4..6
143 %J print register for VLDR instruction
144 %K print address for VLDR instruction
145 %F print the COUNT field of a LFM/SFM instruction.
146 %P print floating point precision in arithmetic insn
147 %Q print floating point precision in ldf/stf insn
148 %R print floating point rounding mode
150 %<bitfield>c print as a condition code (for vsel)
151 %<bitfield>r print as an ARM register
152 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
153 %<bitfield>ru as %<>r but each u register must be unique.
154 %<bitfield>d print the bitfield in decimal
155 %<bitfield>k print immediate for VFPv3 conversion instruction
156 %<bitfield>x print the bitfield in hex
157 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
158 %<bitfield>f print a floating point constant if >7 else a
159 floating point register
160 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
161 %<bitfield>g print as an iWMMXt 64-bit register
162 %<bitfield>G print as an iWMMXt general purpose or control register
163 %<bitfield>D print as a NEON D register
164 %<bitfield>Q print as a NEON Q register
165 %<bitfield>V print as a NEON D or Q register
166 %<bitfield>E print a quarter-float immediate value
168 %y<code> print a single precision VFP reg.
169 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
170 %z<code> print a double precision VFP reg
171 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
173 %<bitfield>'c print specified char iff bitfield is all ones
174 %<bitfield>`c print specified char iff bitfield is all zeroes
175 %<bitfield>?ab... select from array of values in big endian order
177 %L print as an iWMMXt N/M width field.
178 %Z print the Immediate of a WSHUFH instruction.
179 %l like 'A' except use byte offsets for 'B' & 'H'
181 %i print 5-bit immediate in bits 8,3..0
183 %r print register offset address for wldt/wstr instruction. */
185 enum opcode_sentinel_enum
187 SENTINEL_IWMMXT_START
= 1,
189 SENTINEL_GENERIC_START
192 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
193 #define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
194 #define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
195 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
197 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
199 static const struct sopcode32 coprocessor_opcodes
[] =
201 /* XScale instructions. */
202 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
203 0x0e200010, 0x0fff0ff0,
204 "mia%c\tacc0, %0-3r, %12-15r"},
205 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
206 0x0e280010, 0x0fff0ff0,
207 "miaph%c\tacc0, %0-3r, %12-15r"},
208 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
209 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
210 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
211 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
212 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
213 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
215 /* Intel Wireless MMX technology instructions. */
216 {ANY
, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START
, 0, "" },
217 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
218 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
219 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
220 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
221 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
222 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
223 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
224 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
225 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
226 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
227 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
228 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
229 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
230 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
231 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
232 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
233 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
234 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
235 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
236 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
237 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
238 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
239 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
240 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
241 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
242 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
243 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
244 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
245 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
246 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
247 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
248 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
249 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
250 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
251 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
252 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
253 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
254 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
255 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
256 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
257 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
258 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
259 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
260 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
261 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
262 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
263 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
264 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
265 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
266 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
267 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
268 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
269 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
270 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
271 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
272 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
273 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
274 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
275 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
276 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
277 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
278 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
279 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
280 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
281 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
282 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
283 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
284 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
285 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
286 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
287 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
288 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
289 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
290 0x0e800120, 0x0f800ff0,
291 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
292 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
293 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
294 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
295 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
296 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
297 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
298 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
299 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
300 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
301 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
302 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
303 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
304 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
305 0x0e8000a0, 0x0f800ff0,
306 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
307 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
308 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
309 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
310 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
311 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
312 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
313 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
314 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
315 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
316 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
317 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
318 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
319 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
320 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
321 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
322 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
323 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
324 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
325 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
326 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
327 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
328 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
329 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
330 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
331 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
332 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
333 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
334 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
335 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
336 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
337 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
338 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
339 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
340 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
341 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
342 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
343 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
344 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
345 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
346 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
347 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
348 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
349 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
350 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
351 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
352 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
353 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
354 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
355 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
356 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
357 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
358 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
359 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
360 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
361 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
362 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
363 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
364 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
365 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
366 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
367 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
368 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
369 {ANY
, ARM_FEATURE_CORE_LOW (0),
370 SENTINEL_IWMMXT_END
, 0, "" },
372 /* Floating point coprocessor (FPA) instructions. */
373 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
374 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
375 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
376 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
377 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
378 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
379 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
380 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
381 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
382 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
383 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
384 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
385 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
386 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
387 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
388 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
389 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
390 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
391 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
392 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
393 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
394 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
395 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
396 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
397 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
398 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
399 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
400 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
401 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
402 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
403 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
404 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
405 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
406 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
407 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
408 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
409 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
410 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
411 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
412 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
413 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
414 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
415 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
416 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
417 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
418 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
419 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
420 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
421 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
422 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
423 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
424 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
425 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
426 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
427 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
428 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
429 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
430 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
431 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
432 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
433 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
434 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
435 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
436 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
437 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
438 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
439 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
440 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
441 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
442 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
443 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
444 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
445 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
446 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
447 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
448 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
449 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
450 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
451 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
452 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
453 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
454 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
455 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
),
456 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
457 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
),
458 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
460 /* Armv8.1-M Mainline instructions. */
461 {T32
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
462 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
463 {T32
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
464 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
466 /* ARMv8-M Mainline Security Extensions instructions. */
467 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
),
468 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
469 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
),
470 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
472 /* Register load/store. */
473 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
474 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
475 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
476 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
477 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
478 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
479 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
480 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
481 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
482 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
483 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
484 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
485 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
486 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
487 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
488 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
489 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
490 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
491 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
492 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
493 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
494 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
495 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
496 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
497 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
498 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
499 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
500 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
501 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
502 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
503 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
504 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
505 {ANY
, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN
),
506 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
507 {ANY
, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN
),
508 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
510 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
511 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
512 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
513 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
514 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
515 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
516 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
517 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
519 /* Data transfer between ARM and NEON registers. */
520 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
521 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
522 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
523 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
524 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
525 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
526 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
527 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
528 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
529 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
530 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
531 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
532 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
533 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
534 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
535 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
536 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
537 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
538 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
539 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
540 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
541 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
542 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
543 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
544 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
545 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
546 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
547 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
548 /* Half-precision conversion instructions. */
549 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
550 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
551 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
552 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
553 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
554 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
555 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
556 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
558 /* Floating point coprocessor (VFP) instructions. */
559 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
560 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
561 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
562 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
563 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
564 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
565 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
566 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
567 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
568 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
569 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
570 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
571 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
572 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
573 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
574 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
575 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
576 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
577 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
578 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
579 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
580 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
581 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
582 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
583 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
584 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
585 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
586 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
587 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
588 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
589 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
590 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
591 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
592 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
593 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
594 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
595 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
596 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
597 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
598 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
599 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
600 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
601 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
602 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
603 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
604 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
605 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
606 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
607 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
608 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
609 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
610 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
611 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
612 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
613 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
614 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
615 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
616 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
617 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
618 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
619 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
620 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
621 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
622 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
623 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
624 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
625 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
626 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
627 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
628 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
629 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
630 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
631 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
632 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
633 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
634 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
635 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
636 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
637 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
638 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
639 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
640 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
641 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
642 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
643 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
644 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
645 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
646 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
647 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
648 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
649 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
650 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
651 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
652 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
653 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
654 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
655 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
656 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
657 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
658 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
659 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
660 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
661 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
662 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
663 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
664 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
665 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
666 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
667 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
668 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
669 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
670 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
671 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
672 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
673 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
674 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
675 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
676 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
677 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
678 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
679 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
680 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
681 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
682 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
683 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
684 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
685 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
686 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
687 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
688 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
689 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
690 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
691 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
692 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
693 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
694 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
695 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
696 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
698 /* Cirrus coprocessor instructions. */
699 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
700 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
701 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
702 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
703 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
704 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
705 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
706 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
707 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
708 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
709 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
710 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
711 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
712 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
713 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
714 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
715 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
716 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
717 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
718 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
719 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
720 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
721 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
722 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
723 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
724 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
725 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
726 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
727 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
728 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
729 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
730 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
731 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
732 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
733 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
734 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
735 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
736 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
737 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
738 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
739 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
740 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
741 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
742 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
743 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
744 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
745 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
746 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
747 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
748 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
749 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
750 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
751 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
752 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
753 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
754 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
755 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
756 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
757 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
758 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
759 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
760 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
761 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
762 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
763 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
764 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
765 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
766 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
767 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
768 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
769 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
770 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
771 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
772 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
773 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
774 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
775 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
776 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
777 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
778 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
779 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
780 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
781 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
782 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
783 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
784 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
785 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
786 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
787 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
788 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
789 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
790 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
791 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
792 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
793 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
794 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
795 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
796 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
797 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
798 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
799 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
800 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
801 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
802 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
803 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
804 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
805 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
806 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
807 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
808 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
809 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
810 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
811 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
812 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
813 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
814 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
815 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
816 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
817 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
818 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
819 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
820 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
821 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
822 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
823 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
824 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
825 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
826 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
827 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
828 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
829 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
830 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
831 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
832 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
833 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
834 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
835 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
836 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
837 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
838 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
839 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
840 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
841 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
842 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
843 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
844 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
845 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
846 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
847 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
848 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
849 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
850 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
851 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
852 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
853 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
854 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
855 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
856 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
857 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
858 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
859 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
860 0x0e000600, 0x0ff00f10,
861 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
862 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
863 0x0e100600, 0x0ff00f10,
864 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
865 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
866 0x0e200600, 0x0ff00f10,
867 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
868 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
869 0x0e300600, 0x0ff00f10,
870 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
872 /* VFP Fused multiply add instructions. */
873 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
874 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
875 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
876 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
877 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
878 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
879 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
880 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
881 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
882 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
883 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
884 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
885 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
886 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
887 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
888 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
891 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
892 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
893 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
894 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
895 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
896 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
897 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
898 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
899 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
900 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
901 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
902 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
903 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
904 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
905 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
906 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
907 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
908 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
909 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
910 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
911 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
912 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
913 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
914 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
916 /* Generic coprocessor instructions. */
917 {ANY
, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START
, 0, "" },
918 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
919 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
920 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
921 0x0c500000, 0x0ff00000,
922 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
923 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
924 0x0e000000, 0x0f000010,
925 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
926 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
927 0x0e10f010, 0x0f10f010,
928 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
929 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
930 0x0e100010, 0x0f100010,
931 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
932 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
933 0x0e000010, 0x0f100010,
934 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
935 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
936 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
937 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
938 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
940 /* V6 coprocessor instructions. */
941 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
942 0xfc500000, 0xfff00000,
943 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
944 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
945 0xfc400000, 0xfff00000,
946 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
948 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
949 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
950 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
951 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
952 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
953 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
954 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
955 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
956 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
957 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
958 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
959 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
960 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
961 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
962 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
963 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
964 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
965 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
966 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
967 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
968 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
970 /* Dot Product instructions in the space of coprocessor 13. */
971 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
972 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
973 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
974 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
976 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
977 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
978 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
979 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
980 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
981 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
982 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
983 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
984 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
985 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
986 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
987 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
988 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
989 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
990 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
991 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
992 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
994 /* V5 coprocessor instructions. */
995 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
996 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
997 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
998 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
999 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1000 0xfe000000, 0xff000010,
1001 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1002 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1003 0xfe000010, 0xff100010,
1004 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1005 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1006 0xfe100010, 0xff100010,
1007 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1009 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1010 cp_num: bit <11:8> == 0b1001.
1011 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
1012 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1013 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
1014 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1015 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
1016 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1017 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
1018 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1019 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
1020 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1021 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
1022 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1023 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
1024 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1025 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
1026 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1027 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
1028 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1029 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1030 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1031 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1032 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1033 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1034 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1035 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1036 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1037 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1038 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1039 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1040 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1041 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1042 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1043 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1044 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1045 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1046 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1047 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1048 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1049 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1050 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1051 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1052 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1053 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1054 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1055 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1056 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1057 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1058 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1059 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1060 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1061 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1062 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1063 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1064 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1065 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1066 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1067 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1068 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1069 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1070 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1071 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1072 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1073 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1074 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1075 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1076 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1077 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1078 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1079 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1080 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1081 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1083 /* ARMv8.3 javascript conversion instruction. */
1084 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1085 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1087 {ANY
, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1090 /* Neon opcode table: This does not encode the top byte -- that is
1091 checked by the print_insn_neon routine, as it depends on whether we are
1092 doing thumb32 or arm32 disassembly. */
1094 /* print_insn_neon recognizes the following format control codes:
1098 %c print condition code
1099 %u print condition code (unconditional in ARM mode,
1100 UNPREDICTABLE if not AL in Thumb)
1101 %A print v{st,ld}[1234] operands
1102 %B print v{st,ld}[1234] any one operands
1103 %C print v{st,ld}[1234] single->all operands
1105 %E print vmov, vmvn, vorr, vbic encoded constant
1106 %F print vtbl,vtbx register list
1108 %<bitfield>r print as an ARM register
1109 %<bitfield>d print the bitfield in decimal
1110 %<bitfield>e print the 2^N - bitfield in decimal
1111 %<bitfield>D print as a NEON D register
1112 %<bitfield>Q print as a NEON Q register
1113 %<bitfield>R print as a NEON D or Q register
1114 %<bitfield>Sn print byte scaled width limited by n
1115 %<bitfield>Tn print short scaled width limited by n
1116 %<bitfield>Un print long scaled width limited by n
1118 %<bitfield>'c print specified char iff bitfield is all ones
1119 %<bitfield>`c print specified char iff bitfield is all zeroes
1120 %<bitfield>?ab... select from array of values in big endian order. */
1122 static const struct opcode32 neon_opcodes
[] =
1125 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1126 0xf2b00840, 0xffb00850,
1127 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1128 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1129 0xf2b00000, 0xffb00810,
1130 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1132 /* Move data element to all lanes. */
1133 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1134 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1135 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1136 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1137 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1138 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1141 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1142 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1143 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1144 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1146 /* Half-precision conversions. */
1147 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
1148 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1149 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
1150 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1152 /* NEON fused multiply add instructions. */
1153 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
),
1154 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1155 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1156 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1157 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
),
1158 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1159 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1160 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1162 /* Two registers, miscellaneous. */
1163 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1164 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1165 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1166 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1167 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1168 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1169 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1170 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1171 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1172 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1173 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1174 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1175 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1176 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1177 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1178 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1179 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1180 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1181 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1182 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1183 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1184 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1185 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1186 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1187 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1188 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1189 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1190 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1191 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1192 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1193 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1194 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1195 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1196 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1197 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1198 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1199 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1200 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1201 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1202 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1203 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1204 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1205 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1206 0xf3b20300, 0xffb30fd0,
1207 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1208 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1209 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1210 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1211 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1212 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1213 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1214 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1215 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1216 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1217 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1218 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1219 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1220 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1221 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1222 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1223 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1224 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1225 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1226 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1227 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1228 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1229 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1230 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1231 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1232 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1233 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1234 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1235 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1236 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1237 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1238 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1239 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1240 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1241 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1242 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1243 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1244 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1245 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1246 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1247 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1248 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1249 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1250 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1251 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1252 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1253 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1254 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1255 0xf3bb0600, 0xffbf0e10,
1256 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1257 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1258 0xf3b70600, 0xffbf0e10,
1259 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1261 /* Three registers of the same length. */
1262 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1263 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1264 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1265 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1266 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1267 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1268 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1269 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1270 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1271 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1272 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1273 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1274 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1275 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1276 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1277 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1278 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1279 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1280 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1281 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1282 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1283 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1284 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1285 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1286 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1287 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1288 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1289 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1290 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1291 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1292 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1293 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1294 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1295 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1296 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1297 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1298 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1299 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1300 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1301 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1302 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1303 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1304 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1305 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1306 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1307 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1308 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1309 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1310 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1311 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1312 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1313 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1314 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1315 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1316 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1317 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1318 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1319 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1320 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1321 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1322 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1323 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1324 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1325 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1326 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1327 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1328 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1329 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1330 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1331 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1332 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1333 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1334 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1335 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1336 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1337 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1338 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1339 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1340 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1341 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1342 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1343 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1344 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1345 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1346 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1347 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1348 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1349 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1350 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1351 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1352 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1353 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1354 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1355 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1356 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1357 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1358 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1359 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1360 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1361 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1362 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1363 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1364 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1365 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1366 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1367 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1368 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1369 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1370 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1371 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1372 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1373 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1374 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1375 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1376 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1377 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1378 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1379 0xf2000b00, 0xff800f10,
1380 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1381 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1382 0xf2000b10, 0xff800f10,
1383 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1384 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1385 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1386 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1387 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1388 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1389 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1390 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1391 0xf3000b00, 0xff800f10,
1392 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1393 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1394 0xf2000000, 0xfe800f10,
1395 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1396 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1397 0xf2000010, 0xfe800f10,
1398 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1399 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1400 0xf2000100, 0xfe800f10,
1401 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1402 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1403 0xf2000200, 0xfe800f10,
1404 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1405 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1406 0xf2000210, 0xfe800f10,
1407 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1408 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1409 0xf2000300, 0xfe800f10,
1410 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1411 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1412 0xf2000310, 0xfe800f10,
1413 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1414 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1415 0xf2000400, 0xfe800f10,
1416 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1417 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1418 0xf2000410, 0xfe800f10,
1419 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1420 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1421 0xf2000500, 0xfe800f10,
1422 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1423 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1424 0xf2000510, 0xfe800f10,
1425 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1426 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1427 0xf2000600, 0xfe800f10,
1428 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1429 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1430 0xf2000610, 0xfe800f10,
1431 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1432 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1433 0xf2000700, 0xfe800f10,
1434 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1435 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1436 0xf2000710, 0xfe800f10,
1437 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1438 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1439 0xf2000910, 0xfe800f10,
1440 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1441 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1442 0xf2000a00, 0xfe800f10,
1443 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1444 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1445 0xf2000a10, 0xfe800f10,
1446 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1447 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1448 0xf3000b10, 0xff800f10,
1449 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1450 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1451 0xf3000c10, 0xff800f10,
1452 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1454 /* One register and an immediate value. */
1455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1456 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1457 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1458 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1459 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1460 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1462 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1464 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1466 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1468 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1470 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1472 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1474 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1476 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1478 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1480 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1482 /* Two registers and a shift amount. */
1483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1484 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1486 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1487 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1488 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1489 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1490 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1492 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1494 0xf2880950, 0xfeb80fd0,
1495 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1496 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1497 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1498 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1499 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1500 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1501 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1502 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1503 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1504 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1505 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1506 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1507 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1508 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1509 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1510 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1511 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1512 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1513 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1514 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1515 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1516 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1517 0xf2900950, 0xfeb00fd0,
1518 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1519 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1520 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1521 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1522 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1523 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1524 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1525 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1526 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1527 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1528 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1530 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1531 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1532 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1533 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1534 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1535 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1536 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1537 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1538 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1539 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1540 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1541 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1542 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1543 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1544 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1545 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1546 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1547 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1548 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1549 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1550 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1551 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1552 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1553 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1554 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1555 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1556 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1557 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1558 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1559 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1560 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1561 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1562 0xf2a00950, 0xfea00fd0,
1563 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1564 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1565 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1566 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1567 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1568 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1569 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1570 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1571 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1572 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1573 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1574 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1575 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1576 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1577 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1578 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1579 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1580 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1581 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1582 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1583 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1584 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1585 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1586 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1587 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1588 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1589 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1590 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1591 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1592 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1593 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1594 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1595 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1596 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1597 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1598 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1599 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1600 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1601 0xf2a00e10, 0xfea00e90,
1602 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1603 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1604 0xf2a00c10, 0xfea00e90,
1605 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
1607 /* Three registers of different lengths. */
1608 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1609 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1610 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1611 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1612 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1613 0xf2800400, 0xff800f50,
1614 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1615 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1616 0xf2800600, 0xff800f50,
1617 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1618 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1619 0xf2800900, 0xff800f50,
1620 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1621 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1622 0xf2800b00, 0xff800f50,
1623 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1624 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1625 0xf2800d00, 0xff800f50,
1626 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1627 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1628 0xf3800400, 0xff800f50,
1629 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1630 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1631 0xf3800600, 0xff800f50,
1632 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1633 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1634 0xf2800000, 0xfe800f50,
1635 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1636 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1637 0xf2800100, 0xfe800f50,
1638 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1639 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1640 0xf2800200, 0xfe800f50,
1641 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1642 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1643 0xf2800300, 0xfe800f50,
1644 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1645 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1646 0xf2800500, 0xfe800f50,
1647 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1648 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1649 0xf2800700, 0xfe800f50,
1650 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1651 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1652 0xf2800800, 0xfe800f50,
1653 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1654 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1655 0xf2800a00, 0xfe800f50,
1656 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1658 0xf2800c00, 0xfe800f50,
1659 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1661 /* Two registers and a scalar. */
1662 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1663 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1664 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1665 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1666 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1667 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1668 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1669 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1670 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1671 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1672 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1673 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1674 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1675 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1676 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1677 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1678 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1679 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1680 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1681 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1682 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1683 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1684 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1685 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1687 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1688 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1689 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1691 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1692 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1693 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1694 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1695 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1696 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1697 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1698 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1699 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1700 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1701 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1702 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1703 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1704 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1705 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1706 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1707 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1708 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1709 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1710 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1711 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1712 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1713 0xf2800240, 0xfe800f50,
1714 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1715 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1716 0xf2800640, 0xfe800f50,
1717 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1718 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1719 0xf2800a40, 0xfe800f50,
1720 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1721 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1722 0xf2800e40, 0xff800f50,
1723 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1724 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1725 0xf2800f40, 0xff800f50,
1726 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1727 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1728 0xf3800e40, 0xff800f50,
1729 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1730 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1731 0xf3800f40, 0xff800f50,
1732 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1735 /* Element and structure load/store. */
1736 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1737 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1738 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1739 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1740 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1741 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1742 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1743 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1744 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1745 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1746 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1747 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1748 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1749 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1750 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1751 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1753 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1754 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1755 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1756 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1757 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1758 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1759 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1760 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1761 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1762 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1763 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1764 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1765 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1766 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1767 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1768 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1769 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1770 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1771 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1772 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1773 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1775 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
1778 /* mve opcode table. */
1780 /* print_insn_mve recognizes the following format control codes:
1786 static const struct mopcode32 mve_opcodes
[] =
1790 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
1791 ordered: they must be searched linearly from the top to obtain a correct
1794 /* print_insn_arm recognizes the following format control codes:
1798 %a print address for ldr/str instruction
1799 %s print address for ldr/str halfword/signextend instruction
1800 %S like %s but allow UNPREDICTABLE addressing
1801 %b print branch destination
1802 %c print condition code (always bits 28-31)
1803 %m print register mask for ldm/stm instruction
1804 %o print operand2 (immediate or register + shift)
1805 %p print 'p' iff bits 12-15 are 15
1806 %t print 't' iff bit 21 set and bit 24 clear
1807 %B print arm BLX(1) destination
1808 %C print the PSR sub type.
1809 %U print barrier type.
1810 %P print address for pli instruction.
1812 %<bitfield>r print as an ARM register
1813 %<bitfield>T print as an ARM register + 1
1814 %<bitfield>R as %r but r15 is UNPREDICTABLE
1815 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1816 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
1817 %<bitfield>d print the bitfield in decimal
1818 %<bitfield>W print the bitfield plus one in decimal
1819 %<bitfield>x print the bitfield in hex
1820 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
1822 %<bitfield>'c print specified char iff bitfield is all ones
1823 %<bitfield>`c print specified char iff bitfield is all zeroes
1824 %<bitfield>?ab... select from array of values in big endian order
1826 %e print arm SMI operand (bits 0..7,8..19).
1827 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
1828 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
1829 %R print the SPSR/CPSR or banked register of an MRS. */
1831 static const struct opcode32 arm_opcodes
[] =
1833 /* ARM instructions. */
1834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
1835 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
1837 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
1839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
),
1840 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1842 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1844 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
),
1846 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
),
1848 0x00800090, 0x0fa000f0,
1849 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
),
1851 0x00a00090, 0x0fa000f0,
1852 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1854 /* V8.2 RAS extension instructions. */
1855 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
1856 0xe320f010, 0xffffffff, "esb"},
1858 /* V8 instructions. */
1859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
1860 0x0320f005, 0x0fffffff, "sevl"},
1861 /* Defined in V8 but is in NOP space so available to all arch. */
1862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
1863 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
1864 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
),
1865 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
1866 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
1867 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
1869 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
1870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
1871 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
1872 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
1873 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
1874 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
1875 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
1876 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
1877 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
1878 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
1879 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
1880 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
1881 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
1882 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
1883 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
1884 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
1885 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
1886 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
1887 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
1888 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
1889 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
1890 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
1891 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
1892 /* CRC32 instructions. */
1893 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
1894 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
1895 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
1896 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
1897 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
1898 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
1899 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
1900 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
1901 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
1902 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
1903 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
1904 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
1906 /* Privileged Access Never extension instructions. */
1907 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
1908 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
1910 /* Virtualization Extension instructions. */
1911 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0x0160006e, 0x0fffffff, "eret%c"},
1912 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
1914 /* Integer Divide Extension instructions. */
1915 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
1916 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
1917 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
1918 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
1920 /* MP Extension instructions. */
1921 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP
), 0xf410f000, 0xfc70f000, "pldw\t%a"},
1923 /* Speculation Barriers. */
1924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xe320f014, 0xffffffff, "csdb"},
1925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xf57ff040, 0xffffffff, "ssbb"},
1926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xf57ff044, 0xffffffff, "pssbb"},
1928 /* V7 instructions. */
1929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf450f000, 0xfd70f000, "pli\t%P"},
1930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
1931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
1932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
1933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
1934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
1935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff060, 0xfffffff0, "isb\t%U"},
1936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
),
1937 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
1939 /* ARM V6T2 instructions. */
1940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
1941 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
1942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
1943 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
1944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
1945 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
1947 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
1949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
1950 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION
},
1951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
1952 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
1954 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
1955 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
1956 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
1957 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
1958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
1959 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
1960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
1961 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
1963 /* ARM Security extension instructions. */
1964 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
1965 0x01600070, 0x0ff000f0, "smc%c\t%e"},
1967 /* ARM V6K instructions. */
1968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
1969 0xf57ff01f, 0xffffffff, "clrex"},
1970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
1971 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
1972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
1973 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
1974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
1975 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
1976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
1977 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
1978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
1979 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
1980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
1981 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
1983 /* ARMv8.5-A instructions. */
1984 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
), 0xf57ff070, 0xffffffff, "sb"},
1986 /* ARM V6K NOP hints. */
1987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
1988 0x0320f001, 0x0fffffff, "yield%c"},
1989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
1990 0x0320f002, 0x0fffffff, "wfe%c"},
1991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
1992 0x0320f003, 0x0fffffff, "wfi%c"},
1993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
1994 0x0320f004, 0x0fffffff, "sev%c"},
1995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
1996 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
1998 /* ARM V6 instructions. */
1999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2000 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
2001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2002 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
2003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2004 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
2005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2006 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
2007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2008 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
2009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2010 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
2011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2012 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
2013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2014 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
2015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2016 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
2017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2018 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
2019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2020 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
2021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2022 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
2023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2024 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
2025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2026 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
2027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2028 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
2029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2030 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
2031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2032 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
2033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2034 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
2035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2036 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
2037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2038 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
2039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2040 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
2041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2042 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
2043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2044 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
2045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2046 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
2047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2048 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
2049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2050 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
2051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2052 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
2053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2054 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
2055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2056 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
2057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2058 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
2059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2060 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
2061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2062 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
2063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2064 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
2065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2066 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
2067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2068 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
2069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2070 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
2071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2072 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
2073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2074 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
2075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2076 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
2077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2078 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
2079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2080 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
2081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2082 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
2083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2084 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
2085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2086 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
2087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2088 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
2089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2090 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
2091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2092 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
2093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2094 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
2095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2096 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
2097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2098 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
2099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2100 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
2101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2102 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
2103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2104 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
2105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2106 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
2107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2108 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
2109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2110 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
2111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2112 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
2113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2114 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
2115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2116 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
2117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2118 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
2119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2120 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
2121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2122 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
2123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2124 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
2125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2126 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
2127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2128 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
2129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2130 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
2131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2132 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
2133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2134 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
2135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2136 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
2137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2138 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
2139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2140 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
2141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2142 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
2143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2144 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
2145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2146 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
2147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2148 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
2149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2150 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2152 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2154 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2156 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
2157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2158 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2160 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2162 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2164 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
2165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2166 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2168 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2170 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2172 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
2173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2174 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2176 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2178 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2180 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
2181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2182 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2184 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2186 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
2187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2188 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
2189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2190 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2192 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2194 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2196 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
2197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2198 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
2199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2200 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
2201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2202 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
2203 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2204 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2206 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2208 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2210 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2212 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
2213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2214 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2216 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2217 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2218 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
2219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2220 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
2221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2222 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
2223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2224 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
2225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2226 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
2227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2228 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
2229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2230 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
2231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2232 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
2233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2234 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2236 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
2237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2238 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
2239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2240 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
2241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2242 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
2244 /* V5J instruction. */
2245 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
),
2246 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
2248 /* V5 Instructions. */
2249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
2250 0xe1200070, 0xfff000f0,
2251 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
2252 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
2253 0xfa000000, 0xfe000000, "blx\t%B"},
2254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
2255 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
2256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
2257 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
2259 /* V5E "El Segundo" Instructions. */
2260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
2261 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
2262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
2263 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
2264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
2265 0xf450f000, 0xfc70f000, "pld\t%a"},
2266 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2267 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2269 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2271 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2273 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
2275 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2276 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2277 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2278 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
2280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2281 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2282 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2283 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2285 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2287 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2289 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2290 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2291 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2292 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2294 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2295 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2296 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2299 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2301 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2304 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
2305 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2306 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2307 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2308 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
2309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2310 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
2312 /* ARM Instructions. */
2313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2314 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2317 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2319 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2321 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2323 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2325 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2327 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2329 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2330 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2331 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2332 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2334 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2336 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2339 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION
},
2340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2341 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2343 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION
},
2344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2345 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2348 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2350 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2352 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2355 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2357 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2359 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2362 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2364 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2366 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2369 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2371 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2373 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2376 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2378 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2380 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2383 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2385 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2387 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2390 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2392 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2393 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2394 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2397 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2399 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2401 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2403 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
2404 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
),
2406 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
),
2408 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2411 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2413 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2415 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2418 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
2419 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2420 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
2421 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2422 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
2424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2425 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2427 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2429 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2431 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2432 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2433 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2434 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2435 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2436 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2439 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2440 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2441 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2443 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2446 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2447 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2448 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2450 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2451 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2452 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2453 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2454 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2455 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2456 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2457 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2458 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2461 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2462 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2463 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2465 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2467 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2468 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2469 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2470 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2471 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2472 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2475 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION
},
2476 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2477 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2479 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2480 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2482 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2483 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2485 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2487 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2488 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2489 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2490 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2492 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2494 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2495 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2496 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2497 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2498 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2499 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2500 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2501 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2502 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2503 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2504 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2505 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2506 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2507 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2508 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2509 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2510 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2511 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2512 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2513 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2514 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2515 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2516 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2517 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2518 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2519 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2520 0x092d0000, 0x0fff0000, "push%c\t%m"},
2521 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2522 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2523 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2524 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2526 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2527 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2528 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2529 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2531 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2533 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2534 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2535 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2537 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2539 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2541 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2543 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2545 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2547 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2549 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2551 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2553 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2555 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2557 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2559 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2561 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2563 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2566 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2568 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
2571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
),
2572 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION
},
2573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2574 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
2575 {ARM_FEATURE_CORE_LOW (0),
2576 0x00000000, 0x00000000, 0}
2579 /* print_insn_thumb16 recognizes the following format control codes:
2581 %S print Thumb register (bits 3..5 as high number if bit 6 set)
2582 %D print Thumb register (bits 0..2 as high number if bit 7 set)
2583 %<bitfield>I print bitfield as a signed decimal
2584 (top bit of range being the sign bit)
2585 %N print Thumb register mask (with LR)
2586 %O print Thumb register mask (with PC)
2587 %M print Thumb register mask
2588 %b print CZB's 6-bit unsigned branch destination
2589 %s print Thumb right-shift immediate (6..10; 0 == 32).
2590 %c print the condition code
2591 %C print the condition code, or "s" if not conditional
2592 %x print warning if conditional an not at end of IT block"
2593 %X print "\t; unpredictable <IT:code>" if conditional
2594 %I print IT instruction suffix and operands
2595 %W print Thumb Writeback indicator for LDMIA
2596 %<bitfield>r print bitfield as an ARM register
2597 %<bitfield>d print bitfield as a decimal
2598 %<bitfield>H print (bitfield * 2) as a decimal
2599 %<bitfield>W print (bitfield * 4) as a decimal
2600 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
2601 %<bitfield>B print Thumb branch destination (signed displacement)
2602 %<bitfield>c print bitfield as a condition code
2603 %<bitnum>'c print specified char iff bit is one
2604 %<bitnum>?ab print a if bit is one else print b. */
2606 static const struct opcode16 thumb_opcodes
[] =
2608 /* Thumb instructions. */
2610 /* ARMv8-M Security Extensions instructions. */
2611 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0x4784, 0xff87, "blxns\t%3-6r"},
2612 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0x4704, 0xff87, "bxns\t%3-6r"},
2614 /* ARM V8 instructions. */
2615 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xbf50, 0xffff, "sevl%c"},
2616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xba80, 0xffc0, "hlt\t%0-5x"},
2617 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
), 0xb610, 0xfff7, "setpan\t#%3-3d"},
2619 /* ARM V6K no-argument instructions. */
2620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf00, 0xffff, "nop%c"},
2621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf10, 0xffff, "yield%c"},
2622 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf20, 0xffff, "wfe%c"},
2623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf30, 0xffff, "wfi%c"},
2624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf40, 0xffff, "sev%c"},
2625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
2627 /* ARM V6T2 instructions. */
2628 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
2629 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2630 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
2631 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
2632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xbf00, 0xff00, "it%I%X"},
2635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2641 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
2647 /* ARM V5 ISA extends Thumb. */
2648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
),
2649 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
2650 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
2651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
),
2652 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
2653 /* ARM V4T ISA (Thumb v1). */
2654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2655 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
2657 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2658 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2665 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2667 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2669 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
2674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
2677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4700, 0xFF80, "bx%c\t%S%x"},
2678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4400, 0xFF00, "add%c\t%D, %S"},
2679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4600, 0xFF00, "mov%c\t%D, %S"},
2682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB400, 0xFE00, "push%c\t%N"},
2683 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xBC00, 0xFE00, "pop%c\t%O"},
2685 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2686 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2687 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2688 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2689 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2690 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2692 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
2694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2695 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2697 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2699 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
2701 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2702 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2703 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2704 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2708 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2709 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
2712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2713 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2715 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
2717 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2720 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
2722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2723 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2725 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2727 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2729 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
2731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2732 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2734 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
2736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2737 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2739 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
2741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2742 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2744 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
2746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
2749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
2751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION
},
2753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
2755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
2757 /* The E800 .. FFFF range is unconditionally redirected to the
2758 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2759 are processed via that table. Thus, we can never encounter a
2760 bare "second half of BL/BLX(1)" instruction here. */
2761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
), 0x0000, 0x0000, UNDEFINED_INSTRUCTION
},
2762 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2765 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
2766 We adopt the convention that hw1 is the high 16 bits of .value and
2767 .mask, hw2 the low 16 bits.
2769 print_insn_thumb32 recognizes the following format control codes:
2773 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2774 %M print a modified 12-bit immediate (same location)
2775 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2776 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
2777 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
2778 %S print a possibly-shifted Rm
2780 %L print address for a ldrd/strd instruction
2781 %a print the address of a plain load/store
2782 %w print the width and signedness of a core load/store
2783 %m print register mask for ldm/stm
2784 %n print register mask for clrm
2786 %E print the lsb and width fields of a bfc/bfi instruction
2787 %F print the lsb and width fields of a sbfx/ubfx instruction
2788 %G print a fallback offset for Branch Future instructions
2789 %W print an offset for BF instruction
2790 %Y print an offset for BFL instruction
2791 %Z print an offset for BFCSEL instruction
2792 %Q print an offset for Low Overhead Loop instructions
2793 %P print an offset for Low Overhead Loop end instructions
2794 %b print a conditional branch offset
2795 %B print an unconditional branch offset
2796 %s print the shift field of an SSAT instruction
2797 %R print the rotation field of an SXT instruction
2798 %U print barrier type.
2799 %P print address for pli instruction.
2800 %c print the condition code
2801 %x print warning if conditional an not at end of IT block"
2802 %X print "\t; unpredictable <IT:code>" if conditional
2804 %<bitfield>d print bitfield in decimal
2805 %<bitfield>D print bitfield plus one in decimal
2806 %<bitfield>W print bitfield*4 in decimal
2807 %<bitfield>r print bitfield as an ARM register
2808 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
2809 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
2810 %<bitfield>c print bitfield as a condition code
2812 %<bitfield>'c print specified char iff bitfield is all ones
2813 %<bitfield>`c print specified char iff bitfield is all zeroes
2814 %<bitfield>?ab... select from array of values in big endian order
2816 With one exception at the bottom (done because BL and BLX(1) need
2817 to come dead last), this table was machine-sorted first in
2818 decreasing order of number of bits set in the mask, then in
2819 increasing numeric order of mask, then in increasing numeric order
2820 of opcode. This order is not the clearest for a human reader, but
2821 is guaranteed never to catch a special-case bit pattern with a more
2822 general mask, which is important, because this instruction encoding
2823 makes heavy use of special-case bit patterns. */
2824 static const struct opcode32 thumb32_opcodes
[] =
2826 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
2828 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
2829 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
2830 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
2831 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
2832 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
2833 0xf02fc001, 0xfffff001, "le\t%P"},
2834 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
2835 0xf00fc001, 0xfffff001, "le\tlr, %P"},
2837 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
2838 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
2839 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
2840 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
2841 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
2842 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
2843 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
2844 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
2845 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
2846 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
2848 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
2849 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
2851 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
2852 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0xe97fe97f, 0xffffffff, "sg"},
2853 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
2854 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
2855 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
2856 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
2857 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
2858 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
2859 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
2860 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
2862 /* ARM V8.2 RAS extension instructions. */
2863 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
2864 0xf3af8010, 0xffffffff, "esb"},
2866 /* V8 instructions. */
2867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2868 0xf3af8005, 0xffffffff, "sevl%c.w"},
2869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2870 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2872 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
2873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2874 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
2875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2876 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
2877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2878 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
2879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2880 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
2881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2882 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
2883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2884 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
2885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2886 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2888 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2890 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
2891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2892 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2894 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2896 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2898 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
2900 /* CRC32 instructions. */
2901 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2902 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
2903 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2904 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
2905 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2906 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
2907 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2908 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
2909 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2910 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
2911 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2912 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
2914 /* Speculation Barriers. */
2915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8014, 0xffffffff, "csdb"},
2916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3bf8f40, 0xffffffff, "ssbb"},
2917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3bf8f44, 0xffffffff, "pssbb"},
2919 /* V7 instructions. */
2920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf910f000, 0xff70f000, "pli%c\t%a"},
2921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
2922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
2923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
2924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
2925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
2926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
2927 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
2928 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
2929 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
2930 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
2932 /* Virtualization Extension instructions. */
2933 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
2934 /* We skip ERET as that is SUBS pc, lr, #0. */
2936 /* MP Extension instructions. */
2937 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP
), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
2939 /* Security extension instructions. */
2940 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
2942 /* ARMv8.5-A instructions. */
2943 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
), 0xf3bf8f70, 0xffffffff, "sb"},
2945 /* Instructions defined in the basic V6T2 set. */
2946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8000, 0xffffffff, "nop%c.w"},
2947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8001, 0xffffffff, "yield%c.w"},
2948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8002, 0xffffffff, "wfe%c.w"},
2949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8003, 0xffffffff, "wfi%c.w"},
2950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8004, 0xffffffff, "sev%c.w"},
2951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2952 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
2953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
2955 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
2956 0xf3bf8f2f, 0xffffffff, "clrex%c"},
2957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2958 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
2959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2960 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
2961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2962 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
2963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2964 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
2965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2966 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
2967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2968 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
2969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2970 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
2971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2972 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
2973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2974 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
2975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2976 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
2977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2978 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
2979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2980 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
2981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2982 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
2983 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
2984 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
2985 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
2986 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
2987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2988 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
2989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2990 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
2991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2992 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
2993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2994 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
2995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2996 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
2997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2998 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
2999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3000 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
3001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3002 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
3003 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3004 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
3005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3006 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
3007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3008 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
3009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3010 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
3011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3012 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
3013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3014 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
3015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3016 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
3017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3018 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
3019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3020 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
3021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3022 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
3023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3024 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
3025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3026 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
3027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3028 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
3029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3030 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
3031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3032 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
3033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3034 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
3035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3036 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
3037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3038 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
3039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3040 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
3041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3042 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
3043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3044 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
3045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3046 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
3047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3048 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
3049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3050 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
3051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3052 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
3053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3054 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
3055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3056 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
3057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3058 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
3059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3060 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
3061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3062 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
3063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3064 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
3065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3066 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
3067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3068 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
3069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3070 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
3071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3072 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
3073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3074 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
3075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3076 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
3077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3078 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
3079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3080 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
3081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3082 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
3083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3084 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
3085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3086 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
3087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3088 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
3089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3090 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
3091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3092 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
3093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3094 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
3095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3096 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
3097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3098 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
3099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3100 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
3101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3102 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
3103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3104 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3106 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3108 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3110 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
3111 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3112 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
3113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3114 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
3115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3116 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
3117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3118 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
3119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3120 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3122 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
3123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3124 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
3125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3126 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3128 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3130 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3132 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3134 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3136 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3138 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3140 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
3141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3142 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
3143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3144 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
3145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3146 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
3147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3148 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
3149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3150 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
3151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3152 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
3153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3154 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
3155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3156 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
3157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3158 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
3159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3160 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
3161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3162 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
3163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3164 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3166 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3168 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3170 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3172 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3174 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3176 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3178 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3179 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3180 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
3181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3182 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
3183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3184 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
3185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3186 0xf810f000, 0xff70f000, "pld%c\t%a"},
3187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3188 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3190 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3192 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3194 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3196 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3198 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3200 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3202 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
3203 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3204 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
3205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3206 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
3207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3208 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
3209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3210 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
3211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3212 0xfb100000, 0xfff000c0,
3213 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3215 0xfbc00080, 0xfff000c0,
3216 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
3217 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3218 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
3219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3220 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
3221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3222 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
3223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3224 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
3225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3226 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
3227 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3228 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
3229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3230 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
3231 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3232 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
3233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3234 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
3235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3236 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
3237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3238 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
3239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3240 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
3241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3242 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
3243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3244 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
3245 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3246 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
3247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3248 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
3249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3250 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
3251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3252 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
3253 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3254 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
3255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3256 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
3257 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3258 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
3259 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3260 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
3261 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3262 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
3263 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3264 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
3265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3266 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
3267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3268 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
3269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3270 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
3271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3272 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
3273 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3274 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
3275 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3276 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
3277 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3278 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
3279 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3280 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
3281 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3282 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
3283 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3284 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
3285 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3286 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
3287 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3288 0xe9400000, 0xff500000,
3289 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3291 0xe9500000, 0xff500000,
3292 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3294 0xe8600000, 0xff700000,
3295 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3297 0xe8700000, 0xff700000,
3298 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3299 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3300 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
3301 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3302 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
3304 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
3305 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3306 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
3307 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3308 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
3309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3310 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
3311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3312 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
3314 /* These have been 32-bit since the invention of Thumb. */
3315 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3316 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
3317 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3318 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
3321 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3322 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
3323 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
3326 static const char *const arm_conditional
[] =
3327 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
3328 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
3330 static const char *const arm_fp_const
[] =
3331 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
3333 static const char *const arm_shift
[] =
3334 {"lsl", "lsr", "asr", "ror"};
3339 const char *description
;
3340 const char *reg_names
[16];
3344 static const arm_regname regnames
[] =
3346 { "reg-names-raw", N_("Select raw register names"),
3347 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
3348 { "reg-names-gcc", N_("Select register names used by GCC"),
3349 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
3350 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
3351 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
3352 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL
} },
3353 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL
} },
3354 { "reg-names-apcs", N_("Select register names used in the APCS"),
3355 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
3356 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
3357 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
3358 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
3359 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
3362 static const char *const iwmmxt_wwnames
[] =
3363 {"b", "h", "w", "d"};
3365 static const char *const iwmmxt_wwssnames
[] =
3366 {"b", "bus", "bc", "bss",
3367 "h", "hus", "hc", "hss",
3368 "w", "wus", "wc", "wss",
3369 "d", "dus", "dc", "dss"
3372 static const char *const iwmmxt_regnames
[] =
3373 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3374 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3377 static const char *const iwmmxt_cregnames
[] =
3378 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3379 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3382 /* Default to GCC register name set. */
3383 static unsigned int regname_selected
= 1;
3385 #define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
3386 #define arm_regnames regnames[regname_selected].reg_names
3388 static bfd_boolean force_thumb
= FALSE
;
3390 /* Current IT instruction state. This contains the same state as the IT
3391 bits in the CPSR. */
3392 static unsigned int ifthen_state
;
3393 /* IT state for the next instruction. */
3394 static unsigned int ifthen_next_state
;
3395 /* The address of the insn for which the IT state is valid. */
3396 static bfd_vma ifthen_address
;
3397 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
3398 /* Indicates that the current Conditional state is unconditional or outside
3400 #define COND_UNCOND 16
3405 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3406 Returns pointer to following character of the format string and
3407 fills in *VALUEP and *WIDTHP with the extracted value and number of
3408 bits extracted. WIDTHP can be NULL. */
3411 arm_decode_bitfield (const char *ptr
,
3413 unsigned long *valuep
,
3416 unsigned long value
= 0;
3424 for (start
= 0; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
3425 start
= start
* 10 + *ptr
- '0';
3427 for (end
= 0, ptr
++; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
3428 end
= end
* 10 + *ptr
- '0';
3434 value
|= ((insn
>> start
) & ((2ul << bits
) - 1)) << width
;
3437 while (*ptr
++ == ',');
3445 arm_decode_shift (long given
, fprintf_ftype func
, void *stream
,
3446 bfd_boolean print_shift
)
3448 func (stream
, "%s", arm_regnames
[given
& 0xf]);
3450 if ((given
& 0xff0) != 0)
3452 if ((given
& 0x10) == 0)
3454 int amount
= (given
& 0xf80) >> 7;
3455 int shift
= (given
& 0x60) >> 5;
3461 func (stream
, ", rrx");
3469 func (stream
, ", %s #%d", arm_shift
[shift
], amount
);
3471 func (stream
, ", #%d", amount
);
3473 else if ((given
& 0x80) == 0x80)
3474 func (stream
, "\t; <illegal shifter operand>");
3475 else if (print_shift
)
3476 func (stream
, ", %s %s", arm_shift
[(given
& 0x60) >> 5],
3477 arm_regnames
[(given
& 0xf00) >> 8]);
3479 func (stream
, ", %s", arm_regnames
[(given
& 0xf00) >> 8]);
3483 /* Return TRUE if the MATCHED_INSN can be inside an IT block. */
3486 is_mve_okay_in_it (enum mve_instructions matched_insn
)
3492 is_mve_architecture (struct disassemble_info
*info
)
3494 struct arm_private_data
*private_data
= info
->private_data
;
3495 arm_feature_set allowed_arches
= private_data
->features
;
3497 arm_feature_set arm_ext_v8_1m_main
3498 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
3500 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
3501 && !ARM_CPU_IS_ANY (allowed_arches
))
3507 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START
3508 and ending bitfield = END. END must be greater than START. */
3510 static unsigned long
3511 arm_decode_field (unsigned long given
, unsigned int start
, unsigned int end
)
3513 int bits
= end
- start
;
3518 return ((given
>> start
) & ((2ul << bits
) - 1));
3521 /* Decode a bitfield from opcode GIVEN, with multiple bitfields:
3522 START:END and START2:END2. END/END2 must be greater than
3525 static unsigned long
3526 arm_decode_field_multiple (unsigned long given
, unsigned int start
,
3527 unsigned int end
, unsigned int start2
,
3530 int bits
= end
- start
;
3531 int bits2
= end2
- start2
;
3532 unsigned long value
= 0;
3538 value
= arm_decode_field (given
, start
, end
);
3541 value
|= ((given
>> start2
) & ((2ul << bits2
) - 1)) << width
;
3545 /* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
3546 This helps us decode instructions that change mnemonic depending on specific
3547 operand values/encodings. */
3550 is_mve_encoding_conflict (unsigned long given
,
3551 enum mve_instructions matched_insn
)
3556 /* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
3557 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
3558 this encoding is undefined. */
3561 is_mve_undefined (unsigned long given
, enum mve_instructions matched_insn
,
3562 enum mve_undefined
*undefined_code
)
3564 *undefined_code
= UNDEF_NONE
;
3569 /* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
3570 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
3571 why this encoding is unpredictable. */
3574 is_mve_unpredictable (unsigned long given
, enum mve_instructions matched_insn
,
3575 enum mve_unpredictable
*unpredictable_code
)
3577 *unpredictable_code
= UNPRED_NONE
;
3587 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
3588 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
3589 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
3590 #define PRE_BIT_SET (given & (1 << P_BIT))
3593 print_mve_undefined (struct disassemble_info
*info
,
3594 enum mve_undefined undefined_code
)
3596 void *stream
= info
->stream
;
3597 fprintf_ftype func
= info
->fprintf_func
;
3599 func (stream
, "\t\tundefined instruction: ");
3601 switch (undefined_code
)
3610 print_mve_unpredictable (struct disassemble_info
*info
,
3611 enum mve_unpredictable unpredict_code
)
3613 void *stream
= info
->stream
;
3614 fprintf_ftype func
= info
->fprintf_func
;
3616 func (stream
, "%s: ", UNPREDICTABLE_INSTRUCTION
);
3618 switch (unpredict_code
)
3620 case UNPRED_IT_BLOCK
:
3621 func (stream
, "mve instruction in it block");
3629 /* Print one coprocessor instruction on INFO->STREAM.
3630 Return TRUE if the instuction matched, FALSE if this is not a
3631 recognised coprocessor instruction. */
3634 print_insn_coprocessor (bfd_vma pc
,
3635 struct disassemble_info
*info
,
3639 const struct sopcode32
*insn
;
3640 void *stream
= info
->stream
;
3641 fprintf_ftype func
= info
->fprintf_func
;
3643 unsigned long value
= 0;
3646 struct arm_private_data
*private_data
= info
->private_data
;
3647 arm_feature_set allowed_arches
= ARM_ARCH_NONE
;
3648 arm_feature_set arm_ext_v8_1m_main
=
3649 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
3651 allowed_arches
= private_data
->features
;
3653 for (insn
= coprocessor_opcodes
; insn
->assembler
; insn
++)
3655 unsigned long u_reg
= 16;
3656 bfd_boolean is_unpredictable
= FALSE
;
3657 signed long value_in_comment
= 0;
3660 if (ARM_FEATURE_ZERO (insn
->arch
))
3661 switch (insn
->value
)
3663 case SENTINEL_IWMMXT_START
:
3664 if (info
->mach
!= bfd_mach_arm_XScale
3665 && info
->mach
!= bfd_mach_arm_iWMMXt
3666 && info
->mach
!= bfd_mach_arm_iWMMXt2
)
3669 while ((! ARM_FEATURE_ZERO (insn
->arch
))
3670 && insn
->value
!= SENTINEL_IWMMXT_END
);
3673 case SENTINEL_IWMMXT_END
:
3676 case SENTINEL_GENERIC_START
:
3677 allowed_arches
= private_data
->features
;
3685 value
= insn
->value
;
3686 cp_num
= (given
>> 8) & 0xf;
3690 /* The high 4 bits are 0xe for Arm conditional instructions, and
3691 0xe for arm unconditional instructions. The rest of the
3692 encoding is the same. */
3694 value
|= 0xe0000000;
3702 /* Only match unconditional instuctions against unconditional
3704 if ((given
& 0xf0000000) == 0xf0000000)
3711 cond
= (given
>> 28) & 0xf;
3717 if ((insn
->isa
== T32
&& !thumb
)
3718 || (insn
->isa
== ARM
&& thumb
))
3721 if ((given
& mask
) != value
)
3724 if (! ARM_CPU_HAS_FEATURE (insn
->arch
, allowed_arches
))
3727 if (insn
->value
== 0xfe000010 /* mcr2 */
3728 || insn
->value
== 0xfe100010 /* mrc2 */
3729 || insn
->value
== 0xfc100000 /* ldc2 */
3730 || insn
->value
== 0xfc000000) /* stc2 */
3732 if (cp_num
== 9 || cp_num
== 10 || cp_num
== 11)
3733 is_unpredictable
= TRUE
;
3735 else if (insn
->value
== 0x0e000000 /* cdp */
3736 || insn
->value
== 0xfe000000 /* cdp2 */
3737 || insn
->value
== 0x0e000010 /* mcr */
3738 || insn
->value
== 0x0e100010 /* mrc */
3739 || insn
->value
== 0x0c100000 /* ldc */
3740 || insn
->value
== 0x0c000000) /* stc */
3742 /* Floating-point instructions. */
3743 if (cp_num
== 9 || cp_num
== 10 || cp_num
== 11)
3746 /* Armv8.1-M Mainline FP & MVE instructions. */
3747 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
3748 && !ARM_CPU_IS_ANY (allowed_arches
)
3749 && (cp_num
== 8 || cp_num
== 14 || cp_num
== 15))
3753 for (c
= insn
->assembler
; *c
; c
++)
3757 const char mod
= *++c
;
3761 func (stream
, "%%");
3767 int rn
= (given
>> 16) & 0xf;
3768 bfd_vma offset
= given
& 0xff;
3771 offset
= given
& 0x7f;
3773 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
3775 if (PRE_BIT_SET
|| WRITEBACK_BIT_SET
)
3777 /* Not unindexed. The offset is scaled. */
3779 /* vldr.16/vstr.16 will shift the address
3780 left by 1 bit only. */
3781 offset
= offset
* 2;
3783 offset
= offset
* 4;
3785 if (NEGATIVE_BIT_SET
)
3788 value_in_comment
= offset
;
3794 func (stream
, ", #%d]%s",
3796 WRITEBACK_BIT_SET
? "!" : "");
3797 else if (NEGATIVE_BIT_SET
)
3798 func (stream
, ", #-0]");
3806 if (WRITEBACK_BIT_SET
)
3809 func (stream
, ", #%d", (int) offset
);
3810 else if (NEGATIVE_BIT_SET
)
3811 func (stream
, ", #-0");
3815 func (stream
, ", {%s%d}",
3816 (NEGATIVE_BIT_SET
&& !offset
) ? "-" : "",
3818 value_in_comment
= offset
;
3821 if (rn
== 15 && (PRE_BIT_SET
|| WRITEBACK_BIT_SET
))
3823 func (stream
, "\t; ");
3824 /* For unaligned PCs, apply off-by-alignment
3826 info
->print_address_func (offset
+ pc
3827 + info
->bytes_per_chunk
* 2
3836 int regno
= ((given
>> 12) & 0xf) | ((given
>> (22 - 4)) & 0x10);
3837 int offset
= (given
>> 1) & 0x3f;
3840 func (stream
, "{d%d}", regno
);
3841 else if (regno
+ offset
> 32)
3842 func (stream
, "{d%d-<overflow reg d%d>}", regno
, regno
+ offset
- 1);
3844 func (stream
, "{d%d-d%d}", regno
, regno
+ offset
- 1);
3850 bfd_boolean single
= ((given
>> 8) & 1) == 0;
3851 char reg_prefix
= single
? 's' : 'd';
3852 int Dreg
= (given
>> 22) & 0x1;
3853 int Vdreg
= (given
>> 12) & 0xf;
3854 int reg
= single
? ((Vdreg
<< 1) | Dreg
)
3855 : ((Dreg
<< 4) | Vdreg
);
3856 int num
= (given
>> (single
? 0 : 1)) & 0x7f;
3857 int maxreg
= single
? 31 : 15;
3858 int topreg
= reg
+ num
- 1;
3861 func (stream
, "{VPR}");
3863 func (stream
, "{%c%d, VPR}", reg_prefix
, reg
);
3864 else if (topreg
> maxreg
)
3865 func (stream
, "{%c%d-<overflow reg d%d, VPR}",
3866 reg_prefix
, reg
, single
? topreg
>> 1 : topreg
);
3868 func (stream
, "{%c%d-%c%d, VPR}", reg_prefix
, reg
,
3869 reg_prefix
, topreg
);
3874 if (cond
!= COND_UNCOND
)
3875 is_unpredictable
= TRUE
;
3879 if (cond
!= COND_UNCOND
&& cp_num
== 9)
3880 is_unpredictable
= TRUE
;
3882 func (stream
, "%s", arm_conditional
[cond
]);
3886 /* Print a Cirrus/DSP shift immediate. */
3887 /* Immediates are 7bit signed ints with bits 0..3 in
3888 bits 0..3 of opcode and bits 4..6 in bits 5..7
3893 imm
= (given
& 0xf) | ((given
& 0xe0) >> 1);
3895 /* Is ``imm'' a negative number? */
3899 func (stream
, "%d", imm
);
3907 = arm_decode_field_multiple (given
, 13, 15, 22, 22);
3912 func (stream
, "FPSCR");
3915 func (stream
, "FPSCR_nzcvqc");
3918 func (stream
, "VPR");
3921 func (stream
, "P0");
3924 func (stream
, "FPCXTNS");
3927 func (stream
, "FPCXTS");
3930 func (stream
, "<invalid reg %lu>", regno
);
3937 switch (given
& 0x00408000)
3954 switch (given
& 0x00080080)
3966 func (stream
, _("<illegal precision>"));
3972 switch (given
& 0x00408000)
3990 switch (given
& 0x60)
4006 case '0': case '1': case '2': case '3': case '4':
4007 case '5': case '6': case '7': case '8': case '9':
4011 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
4017 is_unpredictable
= TRUE
;
4022 /* Eat the 'u' character. */
4026 is_unpredictable
= TRUE
;
4029 func (stream
, "%s", arm_regnames
[value
]);
4032 if (given
& (1 << 6))
4036 func (stream
, "d%ld", value
);
4041 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
4043 func (stream
, "q%ld", value
>> 1);
4046 func (stream
, "%ld", value
);
4047 value_in_comment
= value
;
4051 /* Converts immediate 8 bit back to float value. */
4052 unsigned floatVal
= (value
& 0x80) << 24
4053 | (value
& 0x3F) << 19
4054 | ((value
& 0x40) ? (0xF8 << 22) : (1 << 30));
4056 /* Quarter float have a maximum value of 31.0.
4057 Get floating point value multiplied by 1e7.
4058 The maximum value stays in limit of a 32-bit int. */
4060 (78125 << (((floatVal
>> 23) & 0xFF) - 124)) *
4061 (16 + (value
& 0xF));
4063 if (!(decVal
% 1000000))
4064 func (stream
, "%ld\t; 0x%08x %c%u.%01u", value
,
4065 floatVal
, value
& 0x80 ? '-' : ' ',
4067 decVal
% 10000000 / 1000000);
4068 else if (!(decVal
% 10000))
4069 func (stream
, "%ld\t; 0x%08x %c%u.%03u", value
,
4070 floatVal
, value
& 0x80 ? '-' : ' ',
4072 decVal
% 10000000 / 10000);
4074 func (stream
, "%ld\t; 0x%08x %c%u.%07u", value
,
4075 floatVal
, value
& 0x80 ? '-' : ' ',
4076 decVal
/ 10000000, decVal
% 10000000);
4081 int from
= (given
& (1 << 7)) ? 32 : 16;
4082 func (stream
, "%ld", from
- value
);
4088 func (stream
, "#%s", arm_fp_const
[value
& 7]);
4090 func (stream
, "f%ld", value
);
4095 func (stream
, "%s", iwmmxt_wwnames
[value
]);
4097 func (stream
, "%s", iwmmxt_wwssnames
[value
]);
4101 func (stream
, "%s", iwmmxt_regnames
[value
]);
4104 func (stream
, "%s", iwmmxt_cregnames
[value
]);
4108 func (stream
, "0x%lx", (value
& 0xffffffffUL
));
4115 func (stream
, "eq");
4119 func (stream
, "vs");
4123 func (stream
, "ge");
4127 func (stream
, "gt");
4131 func (stream
, "??");
4139 func (stream
, "%c", *c
);
4143 if (value
== ((1ul << width
) - 1))
4144 func (stream
, "%c", *c
);
4147 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
4159 int single
= *c
++ == 'y';
4164 case '4': /* Sm pair */
4165 case '0': /* Sm, Dm */
4166 regno
= given
& 0x0000000f;
4170 regno
+= (given
>> 5) & 1;
4173 regno
+= ((given
>> 5) & 1) << 4;
4176 case '1': /* Sd, Dd */
4177 regno
= (given
>> 12) & 0x0000000f;
4181 regno
+= (given
>> 22) & 1;
4184 regno
+= ((given
>> 22) & 1) << 4;
4187 case '2': /* Sn, Dn */
4188 regno
= (given
>> 16) & 0x0000000f;
4192 regno
+= (given
>> 7) & 1;
4195 regno
+= ((given
>> 7) & 1) << 4;
4198 case '3': /* List */
4200 regno
= (given
>> 12) & 0x0000000f;
4204 regno
+= (given
>> 22) & 1;
4207 regno
+= ((given
>> 22) & 1) << 4;
4214 func (stream
, "%c%d", single
? 's' : 'd', regno
);
4218 int count
= given
& 0xff;
4225 func (stream
, "-%c%d",
4233 func (stream
, ", %c%d", single
? 's' : 'd',
4239 switch (given
& 0x00400100)
4241 case 0x00000000: func (stream
, "b"); break;
4242 case 0x00400000: func (stream
, "h"); break;
4243 case 0x00000100: func (stream
, "w"); break;
4244 case 0x00400100: func (stream
, "d"); break;
4252 /* given (20, 23) | given (0, 3) */
4253 value
= ((given
>> 16) & 0xf0) | (given
& 0xf);
4254 func (stream
, "%d", (int) value
);
4259 /* This is like the 'A' operator, except that if
4260 the width field "M" is zero, then the offset is
4261 *not* multiplied by four. */
4263 int offset
= given
& 0xff;
4264 int multiplier
= (given
& 0x00000100) ? 4 : 1;
4266 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
4270 value_in_comment
= offset
* multiplier
;
4271 if (NEGATIVE_BIT_SET
)
4272 value_in_comment
= - value_in_comment
;
4278 func (stream
, ", #%s%d]%s",
4279 NEGATIVE_BIT_SET
? "-" : "",
4280 offset
* multiplier
,
4281 WRITEBACK_BIT_SET
? "!" : "");
4283 func (stream
, "], #%s%d",
4284 NEGATIVE_BIT_SET
? "-" : "",
4285 offset
* multiplier
);
4294 int imm4
= (given
>> 4) & 0xf;
4295 int puw_bits
= ((given
>> 22) & 6) | ((given
>> W_BIT
) & 1);
4296 int ubit
= ! NEGATIVE_BIT_SET
;
4297 const char *rm
= arm_regnames
[given
& 0xf];
4298 const char *rn
= arm_regnames
[(given
>> 16) & 0xf];
4304 func (stream
, "[%s], %c%s", rn
, ubit
? '+' : '-', rm
);
4306 func (stream
, ", lsl #%d", imm4
);
4313 func (stream
, "[%s, %c%s", rn
, ubit
? '+' : '-', rm
);
4315 func (stream
, ", lsl #%d", imm4
);
4317 if (puw_bits
== 5 || puw_bits
== 7)
4322 func (stream
, "INVALID");
4330 imm5
= ((given
& 0x100) >> 4) | (given
& 0xf);
4331 func (stream
, "%ld", (imm5
== 0) ? 32 : imm5
);
4340 func (stream
, "%c", *c
);
4343 if (value_in_comment
> 32 || value_in_comment
< -16)
4344 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
4346 if (is_unpredictable
)
4347 func (stream
, UNPREDICTABLE_INSTRUCTION
);
4354 /* Decodes and prints ARM addressing modes. Returns the offset
4355 used in the address, if any, if it is worthwhile printing the
4356 offset as a hexadecimal value in a comment at the end of the
4357 line of disassembly. */
4360 print_arm_address (bfd_vma pc
, struct disassemble_info
*info
, long given
)
4362 void *stream
= info
->stream
;
4363 fprintf_ftype func
= info
->fprintf_func
;
4366 if (((given
& 0x000f0000) == 0x000f0000)
4367 && ((given
& 0x02000000) == 0))
4369 offset
= given
& 0xfff;
4371 func (stream
, "[pc");
4375 /* Pre-indexed. Elide offset of positive zero when
4377 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
4378 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
4380 if (NEGATIVE_BIT_SET
)
4385 /* Cope with the possibility of write-back
4386 being used. Probably a very dangerous thing
4387 for the programmer to do, but who are we to
4389 func (stream
, "]%s", WRITEBACK_BIT_SET
? "!" : "");
4391 else /* Post indexed. */
4393 func (stream
, "], #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
4395 /* Ie ignore the offset. */
4399 func (stream
, "\t; ");
4400 info
->print_address_func (offset
, info
);
4405 func (stream
, "[%s",
4406 arm_regnames
[(given
>> 16) & 0xf]);
4410 if ((given
& 0x02000000) == 0)
4412 /* Elide offset of positive zero when non-writeback. */
4413 offset
= given
& 0xfff;
4414 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
4415 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
4419 func (stream
, ", %s", NEGATIVE_BIT_SET
? "-" : "");
4420 arm_decode_shift (given
, func
, stream
, TRUE
);
4423 func (stream
, "]%s",
4424 WRITEBACK_BIT_SET
? "!" : "");
4428 if ((given
& 0x02000000) == 0)
4430 /* Always show offset. */
4431 offset
= given
& 0xfff;
4432 func (stream
, "], #%s%d",
4433 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
4437 func (stream
, "], %s",
4438 NEGATIVE_BIT_SET
? "-" : "");
4439 arm_decode_shift (given
, func
, stream
, TRUE
);
4442 if (NEGATIVE_BIT_SET
)
4446 return (signed long) offset
;
4449 /* Print one neon instruction on INFO->STREAM.
4450 Return TRUE if the instuction matched, FALSE if this is not a
4451 recognised neon instruction. */
4454 print_insn_neon (struct disassemble_info
*info
, long given
, bfd_boolean thumb
)
4456 const struct opcode32
*insn
;
4457 void *stream
= info
->stream
;
4458 fprintf_ftype func
= info
->fprintf_func
;
4462 if ((given
& 0xef000000) == 0xef000000)
4464 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
4465 unsigned long bit28
= given
& (1 << 28);
4467 given
&= 0x00ffffff;
4469 given
|= 0xf3000000;
4471 given
|= 0xf2000000;
4473 else if ((given
& 0xff000000) == 0xf9000000)
4474 given
^= 0xf9000000 ^ 0xf4000000;
4479 for (insn
= neon_opcodes
; insn
->assembler
; insn
++)
4481 if ((given
& insn
->mask
) == insn
->value
)
4483 signed long value_in_comment
= 0;
4484 bfd_boolean is_unpredictable
= FALSE
;
4487 for (c
= insn
->assembler
; *c
; c
++)
4494 func (stream
, "%%");
4498 if (thumb
&& ifthen_state
)
4499 is_unpredictable
= TRUE
;
4503 if (thumb
&& ifthen_state
)
4504 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
4509 static const unsigned char enc
[16] =
4511 0x4, 0x14, /* st4 0,1 */
4523 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
4524 int rn
= ((given
>> 16) & 0xf);
4525 int rm
= ((given
>> 0) & 0xf);
4526 int align
= ((given
>> 4) & 0x3);
4527 int type
= ((given
>> 8) & 0xf);
4528 int n
= enc
[type
] & 0xf;
4529 int stride
= (enc
[type
] >> 4) + 1;
4534 for (ix
= 0; ix
!= n
; ix
++)
4535 func (stream
, "%sd%d", ix
? "," : "", rd
+ ix
* stride
);
4537 func (stream
, "d%d", rd
);
4539 func (stream
, "d%d-d%d", rd
, rd
+ n
- 1);
4540 func (stream
, "}, [%s", arm_regnames
[rn
]);
4542 func (stream
, " :%d", 32 << align
);
4547 func (stream
, ", %s", arm_regnames
[rm
]);
4553 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
4554 int rn
= ((given
>> 16) & 0xf);
4555 int rm
= ((given
>> 0) & 0xf);
4556 int idx_align
= ((given
>> 4) & 0xf);
4558 int size
= ((given
>> 10) & 0x3);
4559 int idx
= idx_align
>> (size
+ 1);
4560 int length
= ((given
>> 8) & 3) + 1;
4564 if (length
> 1 && size
> 0)
4565 stride
= (idx_align
& (1 << size
)) ? 2 : 1;
4571 int amask
= (1 << size
) - 1;
4572 if ((idx_align
& (1 << size
)) != 0)
4576 if ((idx_align
& amask
) == amask
)
4578 else if ((idx_align
& amask
) != 0)
4585 if (size
== 2 && (idx_align
& 2) != 0)
4587 align
= (idx_align
& 1) ? 16 << size
: 0;
4591 if ((size
== 2 && (idx_align
& 3) != 0)
4592 || (idx_align
& 1) != 0)
4599 if ((idx_align
& 3) == 3)
4601 align
= (idx_align
& 3) * 64;
4604 align
= (idx_align
& 1) ? 32 << size
: 0;
4612 for (i
= 0; i
< length
; i
++)
4613 func (stream
, "%sd%d[%d]", (i
== 0) ? "" : ",",
4614 rd
+ i
* stride
, idx
);
4615 func (stream
, "}, [%s", arm_regnames
[rn
]);
4617 func (stream
, " :%d", align
);
4622 func (stream
, ", %s", arm_regnames
[rm
]);
4628 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
4629 int rn
= ((given
>> 16) & 0xf);
4630 int rm
= ((given
>> 0) & 0xf);
4631 int align
= ((given
>> 4) & 0x1);
4632 int size
= ((given
>> 6) & 0x3);
4633 int type
= ((given
>> 8) & 0x3);
4635 int stride
= ((given
>> 5) & 0x1);
4638 if (stride
&& (n
== 1))
4645 for (ix
= 0; ix
!= n
; ix
++)
4646 func (stream
, "%sd%d[]", ix
? "," : "", rd
+ ix
* stride
);
4648 func (stream
, "d%d[]", rd
);
4650 func (stream
, "d%d[]-d%d[]", rd
, rd
+ n
- 1);
4651 func (stream
, "}, [%s", arm_regnames
[rn
]);
4654 align
= (8 * (type
+ 1)) << size
;
4656 align
= (size
> 1) ? align
>> 1 : align
;
4657 if (type
== 2 || (type
== 0 && !size
))
4658 func (stream
, " :<bad align %d>", align
);
4660 func (stream
, " :%d", align
);
4666 func (stream
, ", %s", arm_regnames
[rm
]);
4672 int raw_reg
= (given
& 0xf) | ((given
>> 1) & 0x10);
4673 int size
= (given
>> 20) & 3;
4674 int reg
= raw_reg
& ((4 << size
) - 1);
4675 int ix
= raw_reg
>> size
>> 2;
4677 func (stream
, "d%d[%d]", reg
, ix
);
4682 /* Neon encoded constant for mov, mvn, vorr, vbic. */
4685 int cmode
= (given
>> 8) & 0xf;
4686 int op
= (given
>> 5) & 0x1;
4687 unsigned long value
= 0, hival
= 0;
4692 bits
|= ((given
>> 24) & 1) << 7;
4693 bits
|= ((given
>> 16) & 7) << 4;
4694 bits
|= ((given
>> 0) & 15) << 0;
4698 shift
= (cmode
>> 1) & 3;
4699 value
= (unsigned long) bits
<< (8 * shift
);
4702 else if (cmode
< 12)
4704 shift
= (cmode
>> 1) & 1;
4705 value
= (unsigned long) bits
<< (8 * shift
);
4708 else if (cmode
< 14)
4710 shift
= (cmode
& 1) + 1;
4711 value
= (unsigned long) bits
<< (8 * shift
);
4712 value
|= (1ul << (8 * shift
)) - 1;
4715 else if (cmode
== 14)
4719 /* Bit replication into bytes. */
4725 for (ix
= 7; ix
>= 0; ix
--)
4727 mask
= ((bits
>> ix
) & 1) ? 0xff : 0;
4729 value
= (value
<< 8) | mask
;
4731 hival
= (hival
<< 8) | mask
;
4737 /* Byte replication. */
4738 value
= (unsigned long) bits
;
4744 /* Floating point encoding. */
4747 value
= (unsigned long) (bits
& 0x7f) << 19;
4748 value
|= (unsigned long) (bits
& 0x80) << 24;
4749 tmp
= bits
& 0x40 ? 0x3c : 0x40;
4750 value
|= (unsigned long) tmp
<< 24;
4756 func (stream
, "<illegal constant %.8x:%x:%x>",
4764 func (stream
, "#%ld\t; 0x%.2lx", value
, value
);
4768 func (stream
, "#%ld\t; 0x%.4lx", value
, value
);
4774 unsigned char valbytes
[4];
4777 /* Do this a byte at a time so we don't have to
4778 worry about the host's endianness. */
4779 valbytes
[0] = value
& 0xff;
4780 valbytes
[1] = (value
>> 8) & 0xff;
4781 valbytes
[2] = (value
>> 16) & 0xff;
4782 valbytes
[3] = (value
>> 24) & 0xff;
4784 floatformat_to_double
4785 (& floatformat_ieee_single_little
, valbytes
,
4788 func (stream
, "#%.7g\t; 0x%.8lx", fvalue
,
4792 func (stream
, "#%ld\t; 0x%.8lx",
4793 (long) (((value
& 0x80000000L
) != 0)
4794 ? value
| ~0xffffffffL
: value
),
4799 func (stream
, "#0x%.8lx%.8lx", hival
, value
);
4810 int regno
= ((given
>> 16) & 0xf) | ((given
>> (7 - 4)) & 0x10);
4811 int num
= (given
>> 8) & 0x3;
4814 func (stream
, "{d%d}", regno
);
4815 else if (num
+ regno
>= 32)
4816 func (stream
, "{d%d-<overflow reg d%d}", regno
, regno
+ num
);
4818 func (stream
, "{d%d-d%d}", regno
, regno
+ num
);
4823 case '0': case '1': case '2': case '3': case '4':
4824 case '5': case '6': case '7': case '8': case '9':
4827 unsigned long value
;
4829 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
4834 func (stream
, "%s", arm_regnames
[value
]);
4837 func (stream
, "%ld", value
);
4838 value_in_comment
= value
;
4841 func (stream
, "%ld", (1ul << width
) - value
);
4847 /* Various width encodings. */
4849 int base
= 8 << (*c
- 'S'); /* 8,16 or 32 */
4854 if (*c
>= '0' && *c
<= '9')
4856 else if (*c
>= 'a' && *c
<= 'f')
4857 limit
= *c
- 'a' + 10;
4863 if (value
< low
|| value
> high
)
4864 func (stream
, "<illegal width %d>", base
<< value
);
4866 func (stream
, "%d", base
<< value
);
4870 if (given
& (1 << 6))
4874 func (stream
, "d%ld", value
);
4879 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
4881 func (stream
, "q%ld", value
>> 1);
4887 func (stream
, "%c", *c
);
4891 if (value
== ((1ul << width
) - 1))
4892 func (stream
, "%c", *c
);
4895 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
4909 func (stream
, "%c", *c
);
4912 if (value_in_comment
> 32 || value_in_comment
< -16)
4913 func (stream
, "\t; 0x%lx", value_in_comment
);
4915 if (is_unpredictable
)
4916 func (stream
, UNPREDICTABLE_INSTRUCTION
);
4924 /* Print one mve instruction on INFO->STREAM.
4925 Return TRUE if the instuction matched, FALSE if this is not a
4926 recognised mve instruction. */
4929 print_insn_mve (struct disassemble_info
*info
, long given
)
4931 const struct mopcode32
*insn
;
4932 void *stream
= info
->stream
;
4933 fprintf_ftype func
= info
->fprintf_func
;
4935 for (insn
= mve_opcodes
; insn
->assembler
; insn
++)
4937 if (((given
& insn
->mask
) == insn
->value
)
4938 && !is_mve_encoding_conflict (given
, insn
->mve_op
))
4940 signed long value_in_comment
= 0;
4941 bfd_boolean is_unpredictable
= FALSE
;
4942 bfd_boolean is_undefined
= FALSE
;
4944 enum mve_unpredictable unpredictable_cond
= UNPRED_NONE
;
4945 enum mve_undefined undefined_cond
= UNDEF_NONE
;
4947 /* Most vector mve instruction are illegal in a it block.
4948 There are a few exceptions; check for them. */
4949 if (ifthen_state
&& !is_mve_okay_in_it (insn
->mve_op
))
4951 is_unpredictable
= TRUE
;
4952 unpredictable_cond
= UNPRED_IT_BLOCK
;
4954 else if (is_mve_unpredictable (given
, insn
->mve_op
,
4955 &unpredictable_cond
))
4956 is_unpredictable
= TRUE
;
4958 if (is_mve_undefined (given
, insn
->mve_op
, &undefined_cond
))
4959 is_undefined
= TRUE
;
4961 for (c
= insn
->assembler
; *c
; c
++)
4968 func (stream
, "%%");
4974 func (stream
, "%c", *c
);
4977 if (value_in_comment
> 32 || value_in_comment
< -16)
4978 func (stream
, "\t; 0x%lx", value_in_comment
);
4980 if (is_unpredictable
)
4981 print_mve_unpredictable (info
, unpredictable_cond
);
4984 print_mve_undefined (info
, undefined_cond
);
4993 /* Return the name of a v7A special register. */
4996 banked_regname (unsigned reg
)
5000 case 15: return "CPSR";
5001 case 32: return "R8_usr";
5002 case 33: return "R9_usr";
5003 case 34: return "R10_usr";
5004 case 35: return "R11_usr";
5005 case 36: return "R12_usr";
5006 case 37: return "SP_usr";
5007 case 38: return "LR_usr";
5008 case 40: return "R8_fiq";
5009 case 41: return "R9_fiq";
5010 case 42: return "R10_fiq";
5011 case 43: return "R11_fiq";
5012 case 44: return "R12_fiq";
5013 case 45: return "SP_fiq";
5014 case 46: return "LR_fiq";
5015 case 48: return "LR_irq";
5016 case 49: return "SP_irq";
5017 case 50: return "LR_svc";
5018 case 51: return "SP_svc";
5019 case 52: return "LR_abt";
5020 case 53: return "SP_abt";
5021 case 54: return "LR_und";
5022 case 55: return "SP_und";
5023 case 60: return "LR_mon";
5024 case 61: return "SP_mon";
5025 case 62: return "ELR_hyp";
5026 case 63: return "SP_hyp";
5027 case 79: return "SPSR";
5028 case 110: return "SPSR_fiq";
5029 case 112: return "SPSR_irq";
5030 case 114: return "SPSR_svc";
5031 case 116: return "SPSR_abt";
5032 case 118: return "SPSR_und";
5033 case 124: return "SPSR_mon";
5034 case 126: return "SPSR_hyp";
5035 default: return NULL
;
5039 /* Return the name of the DMB/DSB option. */
5041 data_barrier_option (unsigned option
)
5043 switch (option
& 0xf)
5045 case 0xf: return "sy";
5046 case 0xe: return "st";
5047 case 0xd: return "ld";
5048 case 0xb: return "ish";
5049 case 0xa: return "ishst";
5050 case 0x9: return "ishld";
5051 case 0x7: return "un";
5052 case 0x6: return "unst";
5053 case 0x5: return "nshld";
5054 case 0x3: return "osh";
5055 case 0x2: return "oshst";
5056 case 0x1: return "oshld";
5057 default: return NULL
;
5061 /* Print one ARM instruction from PC on INFO->STREAM. */
5064 print_insn_arm (bfd_vma pc
, struct disassemble_info
*info
, long given
)
5066 const struct opcode32
*insn
;
5067 void *stream
= info
->stream
;
5068 fprintf_ftype func
= info
->fprintf_func
;
5069 struct arm_private_data
*private_data
= info
->private_data
;
5071 if (print_insn_coprocessor (pc
, info
, given
, FALSE
))
5074 if (print_insn_neon (info
, given
, FALSE
))
5077 for (insn
= arm_opcodes
; insn
->assembler
; insn
++)
5079 if ((given
& insn
->mask
) != insn
->value
)
5082 if (! ARM_CPU_HAS_FEATURE (insn
->arch
, private_data
->features
))
5085 /* Special case: an instruction with all bits set in the condition field
5086 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
5087 or by the catchall at the end of the table. */
5088 if ((given
& 0xF0000000) != 0xF0000000
5089 || (insn
->mask
& 0xF0000000) == 0xF0000000
5090 || (insn
->mask
== 0 && insn
->value
== 0))
5092 unsigned long u_reg
= 16;
5093 unsigned long U_reg
= 16;
5094 bfd_boolean is_unpredictable
= FALSE
;
5095 signed long value_in_comment
= 0;
5098 for (c
= insn
->assembler
; *c
; c
++)
5102 bfd_boolean allow_unpredictable
= FALSE
;
5107 func (stream
, "%%");
5111 value_in_comment
= print_arm_address (pc
, info
, given
);
5115 /* Set P address bit and use normal address
5116 printing routine. */
5117 value_in_comment
= print_arm_address (pc
, info
, given
| (1 << P_BIT
));
5121 allow_unpredictable
= TRUE
;
5124 if ((given
& 0x004f0000) == 0x004f0000)
5126 /* PC relative with immediate offset. */
5127 bfd_vma offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
5131 /* Elide positive zero offset. */
5132 if (offset
|| NEGATIVE_BIT_SET
)
5133 func (stream
, "[pc, #%s%d]\t; ",
5134 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
5136 func (stream
, "[pc]\t; ");
5137 if (NEGATIVE_BIT_SET
)
5139 info
->print_address_func (offset
+ pc
+ 8, info
);
5143 /* Always show the offset. */
5144 func (stream
, "[pc], #%s%d",
5145 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
5146 if (! allow_unpredictable
)
5147 is_unpredictable
= TRUE
;
5152 int offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
5154 func (stream
, "[%s",
5155 arm_regnames
[(given
>> 16) & 0xf]);
5159 if (IMMEDIATE_BIT_SET
)
5161 /* Elide offset for non-writeback
5163 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
5165 func (stream
, ", #%s%d",
5166 NEGATIVE_BIT_SET
? "-" : "", offset
);
5168 if (NEGATIVE_BIT_SET
)
5171 value_in_comment
= offset
;
5175 /* Register Offset or Register Pre-Indexed. */
5176 func (stream
, ", %s%s",
5177 NEGATIVE_BIT_SET
? "-" : "",
5178 arm_regnames
[given
& 0xf]);
5180 /* Writing back to the register that is the source/
5181 destination of the load/store is unpredictable. */
5182 if (! allow_unpredictable
5183 && WRITEBACK_BIT_SET
5184 && ((given
& 0xf) == ((given
>> 12) & 0xf)))
5185 is_unpredictable
= TRUE
;
5188 func (stream
, "]%s",
5189 WRITEBACK_BIT_SET
? "!" : "");
5193 if (IMMEDIATE_BIT_SET
)
5195 /* Immediate Post-indexed. */
5196 /* PR 10924: Offset must be printed, even if it is zero. */
5197 func (stream
, "], #%s%d",
5198 NEGATIVE_BIT_SET
? "-" : "", offset
);
5199 if (NEGATIVE_BIT_SET
)
5201 value_in_comment
= offset
;
5205 /* Register Post-indexed. */
5206 func (stream
, "], %s%s",
5207 NEGATIVE_BIT_SET
? "-" : "",
5208 arm_regnames
[given
& 0xf]);
5210 /* Writing back to the register that is the source/
5211 destination of the load/store is unpredictable. */
5212 if (! allow_unpredictable
5213 && (given
& 0xf) == ((given
>> 12) & 0xf))
5214 is_unpredictable
= TRUE
;
5217 if (! allow_unpredictable
)
5219 /* Writeback is automatically implied by post- addressing.
5220 Setting the W bit is unnecessary and ARM specify it as
5221 being unpredictable. */
5222 if (WRITEBACK_BIT_SET
5223 /* Specifying the PC register as the post-indexed
5224 registers is also unpredictable. */
5225 || (! IMMEDIATE_BIT_SET
&& ((given
& 0xf) == 0xf)))
5226 is_unpredictable
= TRUE
;
5234 bfd_vma disp
= (((given
& 0xffffff) ^ 0x800000) - 0x800000);
5235 info
->print_address_func (disp
* 4 + pc
+ 8, info
);
5240 if (((given
>> 28) & 0xf) != 0xe)
5242 arm_conditional
[(given
>> 28) & 0xf]);
5251 for (reg
= 0; reg
< 16; reg
++)
5252 if ((given
& (1 << reg
)) != 0)
5255 func (stream
, ", ");
5257 func (stream
, "%s", arm_regnames
[reg
]);
5261 is_unpredictable
= TRUE
;
5266 arm_decode_shift (given
, func
, stream
, FALSE
);
5270 if ((given
& 0x02000000) != 0)
5272 unsigned int rotate
= (given
& 0xf00) >> 7;
5273 unsigned int immed
= (given
& 0xff);
5276 a
= (((immed
<< (32 - rotate
))
5277 | (immed
>> rotate
)) & 0xffffffff);
5278 /* If there is another encoding with smaller rotate,
5279 the rotate should be specified directly. */
5280 for (i
= 0; i
< 32; i
+= 2)
5281 if ((a
<< i
| a
>> (32 - i
)) <= 0xff)
5285 func (stream
, "#%d, %d", immed
, rotate
);
5287 func (stream
, "#%d", a
);
5288 value_in_comment
= a
;
5291 arm_decode_shift (given
, func
, stream
, TRUE
);
5295 if ((given
& 0x0000f000) == 0x0000f000)
5297 arm_feature_set arm_ext_v6
=
5298 ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
5300 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
5301 mechanism for setting PSR flag bits. They are
5302 obsolete in V6 onwards. */
5303 if (! ARM_CPU_HAS_FEATURE (private_data
->features
, \
5307 is_unpredictable
= TRUE
;
5312 if ((given
& 0x01200000) == 0x00200000)
5318 int offset
= given
& 0xff;
5320 value_in_comment
= offset
* 4;
5321 if (NEGATIVE_BIT_SET
)
5322 value_in_comment
= - value_in_comment
;
5324 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
5329 func (stream
, ", #%d]%s",
5330 (int) value_in_comment
,
5331 WRITEBACK_BIT_SET
? "!" : "");
5339 if (WRITEBACK_BIT_SET
)
5342 func (stream
, ", #%d", (int) value_in_comment
);
5346 func (stream
, ", {%d}", (int) offset
);
5347 value_in_comment
= offset
;
5354 /* Print ARM V5 BLX(1) address: pc+25 bits. */
5359 if (! NEGATIVE_BIT_SET
)
5360 /* Is signed, hi bits should be ones. */
5361 offset
= (-1) ^ 0x00ffffff;
5363 /* Offset is (SignExtend(offset field)<<2). */
5364 offset
+= given
& 0x00ffffff;
5366 address
= offset
+ pc
+ 8;
5368 if (given
& 0x01000000)
5369 /* H bit allows addressing to 2-byte boundaries. */
5372 info
->print_address_func (address
, info
);
5377 if ((given
& 0x02000200) == 0x200)
5380 unsigned sysm
= (given
& 0x004f0000) >> 16;
5382 sysm
|= (given
& 0x300) >> 4;
5383 name
= banked_regname (sysm
);
5386 func (stream
, "%s", name
);
5388 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
5392 func (stream
, "%cPSR_",
5393 (given
& 0x00400000) ? 'S' : 'C');
5394 if (given
& 0x80000)
5396 if (given
& 0x40000)
5398 if (given
& 0x20000)
5400 if (given
& 0x10000)
5406 if ((given
& 0xf0) == 0x60)
5408 switch (given
& 0xf)
5410 case 0xf: func (stream
, "sy"); break;
5412 func (stream
, "#%d", (int) given
& 0xf);
5418 const char * opt
= data_barrier_option (given
& 0xf);
5420 func (stream
, "%s", opt
);
5422 func (stream
, "#%d", (int) given
& 0xf);
5426 case '0': case '1': case '2': case '3': case '4':
5427 case '5': case '6': case '7': case '8': case '9':
5430 unsigned long value
;
5432 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
5438 is_unpredictable
= TRUE
;
5442 /* We want register + 1 when decoding T. */
5448 /* Eat the 'u' character. */
5452 is_unpredictable
= TRUE
;
5457 /* Eat the 'U' character. */
5461 is_unpredictable
= TRUE
;
5464 func (stream
, "%s", arm_regnames
[value
]);
5467 func (stream
, "%ld", value
);
5468 value_in_comment
= value
;
5471 func (stream
, "%ld", value
* 8);
5472 value_in_comment
= value
* 8;
5475 func (stream
, "%ld", value
+ 1);
5476 value_in_comment
= value
+ 1;
5479 func (stream
, "0x%08lx", value
);
5481 /* Some SWI instructions have special
5483 if ((given
& 0x0fffffff) == 0x0FF00000)
5484 func (stream
, "\t; IMB");
5485 else if ((given
& 0x0fffffff) == 0x0FF00001)
5486 func (stream
, "\t; IMBRange");
5489 func (stream
, "%01lx", value
& 0xf);
5490 value_in_comment
= value
;
5495 func (stream
, "%c", *c
);
5499 if (value
== ((1ul << width
) - 1))
5500 func (stream
, "%c", *c
);
5503 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
5516 imm
= (given
& 0xf) | ((given
& 0xfff00) >> 4);
5517 func (stream
, "%d", imm
);
5518 value_in_comment
= imm
;
5523 /* LSB and WIDTH fields of BFI or BFC. The machine-
5524 language instruction encodes LSB and MSB. */
5526 long msb
= (given
& 0x001f0000) >> 16;
5527 long lsb
= (given
& 0x00000f80) >> 7;
5528 long w
= msb
- lsb
+ 1;
5531 func (stream
, "#%lu, #%lu", lsb
, w
);
5533 func (stream
, "(invalid: %lu:%lu)", lsb
, msb
);
5538 /* Get the PSR/banked register name. */
5541 unsigned sysm
= (given
& 0x004f0000) >> 16;
5543 sysm
|= (given
& 0x300) >> 4;
5544 name
= banked_regname (sysm
);
5547 func (stream
, "%s", name
);
5549 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
5554 /* 16-bit unsigned immediate from a MOVT or MOVW
5555 instruction, encoded in bits 0:11 and 15:19. */
5557 long hi
= (given
& 0x000f0000) >> 4;
5558 long lo
= (given
& 0x00000fff);
5559 long imm16
= hi
| lo
;
5561 func (stream
, "#%lu", imm16
);
5562 value_in_comment
= imm16
;
5571 func (stream
, "%c", *c
);
5574 if (value_in_comment
> 32 || value_in_comment
< -16)
5575 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
5577 if (is_unpredictable
)
5578 func (stream
, UNPREDICTABLE_INSTRUCTION
);
5583 func (stream
, UNKNOWN_INSTRUCTION_32BIT
, (unsigned)given
);
5587 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
5590 print_insn_thumb16 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
5592 const struct opcode16
*insn
;
5593 void *stream
= info
->stream
;
5594 fprintf_ftype func
= info
->fprintf_func
;
5596 for (insn
= thumb_opcodes
; insn
->assembler
; insn
++)
5597 if ((given
& insn
->mask
) == insn
->value
)
5599 signed long value_in_comment
= 0;
5600 const char *c
= insn
->assembler
;
5609 func (stream
, "%c", *c
);
5616 func (stream
, "%%");
5621 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
5626 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
5635 ifthen_next_state
= given
& 0xff;
5636 for (tmp
= given
<< 1; tmp
& 0xf; tmp
<<= 1)
5637 func (stream
, ((given
^ tmp
) & 0x10) ? "e" : "t");
5638 func (stream
, "\t%s", arm_conditional
[(given
>> 4) & 0xf]);
5643 if (ifthen_next_state
)
5644 func (stream
, "\t; unpredictable branch in IT block\n");
5649 func (stream
, "\t; unpredictable <IT:%s>",
5650 arm_conditional
[IFTHEN_COND
]);
5657 reg
= (given
>> 3) & 0x7;
5658 if (given
& (1 << 6))
5661 func (stream
, "%s", arm_regnames
[reg
]);
5670 if (given
& (1 << 7))
5673 func (stream
, "%s", arm_regnames
[reg
]);
5678 if (given
& (1 << 8))
5682 if (*c
== 'O' && (given
& (1 << 8)))
5692 /* It would be nice if we could spot
5693 ranges, and generate the rS-rE format: */
5694 for (reg
= 0; (reg
< 8); reg
++)
5695 if ((given
& (1 << reg
)) != 0)
5698 func (stream
, ", ");
5700 func (stream
, "%s", arm_regnames
[reg
]);
5706 func (stream
, ", ");
5708 func (stream
, "%s", arm_regnames
[14] /* "lr" */);
5714 func (stream
, ", ");
5715 func (stream
, "%s", arm_regnames
[15] /* "pc" */);
5723 /* Print writeback indicator for a LDMIA. We are doing a
5724 writeback if the base register is not in the register
5726 if ((given
& (1 << ((given
& 0x0700) >> 8))) == 0)
5731 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
5733 bfd_vma address
= (pc
+ 4
5734 + ((given
& 0x00f8) >> 2)
5735 + ((given
& 0x0200) >> 3));
5736 info
->print_address_func (address
, info
);
5741 /* Right shift immediate -- bits 6..10; 1-31 print
5742 as themselves, 0 prints as 32. */
5744 long imm
= (given
& 0x07c0) >> 6;
5747 func (stream
, "#%ld", imm
);
5751 case '0': case '1': case '2': case '3': case '4':
5752 case '5': case '6': case '7': case '8': case '9':
5754 int bitstart
= *c
++ - '0';
5757 while (*c
>= '0' && *c
<= '9')
5758 bitstart
= (bitstart
* 10) + *c
++ - '0';
5767 while (*c
>= '0' && *c
<= '9')
5768 bitend
= (bitend
* 10) + *c
++ - '0';
5771 reg
= given
>> bitstart
;
5772 reg
&= (2 << (bitend
- bitstart
)) - 1;
5777 func (stream
, "%s", arm_regnames
[reg
]);
5781 func (stream
, "%ld", (long) reg
);
5782 value_in_comment
= reg
;
5786 func (stream
, "%ld", (long) (reg
<< 1));
5787 value_in_comment
= reg
<< 1;
5791 func (stream
, "%ld", (long) (reg
<< 2));
5792 value_in_comment
= reg
<< 2;
5796 /* PC-relative address -- the bottom two
5797 bits of the address are dropped
5798 before the calculation. */
5799 info
->print_address_func
5800 (((pc
+ 4) & ~3) + (reg
<< 2), info
);
5801 value_in_comment
= 0;
5805 func (stream
, "0x%04lx", (long) reg
);
5809 reg
= ((reg
^ (1 << bitend
)) - (1 << bitend
));
5810 info
->print_address_func (reg
* 2 + pc
+ 4, info
);
5811 value_in_comment
= 0;
5815 func (stream
, "%s", arm_conditional
[reg
]);
5826 if ((given
& (1 << bitstart
)) != 0)
5827 func (stream
, "%c", *c
);
5832 if ((given
& (1 << bitstart
)) != 0)
5833 func (stream
, "%c", *c
++);
5835 func (stream
, "%c", *++c
);
5849 if (value_in_comment
> 32 || value_in_comment
< -16)
5850 func (stream
, "\t; 0x%lx", value_in_comment
);
5855 func (stream
, UNKNOWN_INSTRUCTION_16BIT
, (unsigned)given
);
5859 /* Return the name of an V7M special register. */
5862 psr_name (int regno
)
5866 case 0x0: return "APSR";
5867 case 0x1: return "IAPSR";
5868 case 0x2: return "EAPSR";
5869 case 0x3: return "PSR";
5870 case 0x5: return "IPSR";
5871 case 0x6: return "EPSR";
5872 case 0x7: return "IEPSR";
5873 case 0x8: return "MSP";
5874 case 0x9: return "PSP";
5875 case 0xa: return "MSPLIM";
5876 case 0xb: return "PSPLIM";
5877 case 0x10: return "PRIMASK";
5878 case 0x11: return "BASEPRI";
5879 case 0x12: return "BASEPRI_MAX";
5880 case 0x13: return "FAULTMASK";
5881 case 0x14: return "CONTROL";
5882 case 0x88: return "MSP_NS";
5883 case 0x89: return "PSP_NS";
5884 case 0x8a: return "MSPLIM_NS";
5885 case 0x8b: return "PSPLIM_NS";
5886 case 0x90: return "PRIMASK_NS";
5887 case 0x91: return "BASEPRI_NS";
5888 case 0x93: return "FAULTMASK_NS";
5889 case 0x94: return "CONTROL_NS";
5890 case 0x98: return "SP_NS";
5891 default: return "<unknown>";
5895 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
5898 print_insn_thumb32 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
5900 const struct opcode32
*insn
;
5901 void *stream
= info
->stream
;
5902 fprintf_ftype func
= info
->fprintf_func
;
5903 bfd_boolean is_mve
= is_mve_architecture (info
);
5905 if (print_insn_coprocessor (pc
, info
, given
, TRUE
))
5908 if ((is_mve
== FALSE
) && print_insn_neon (info
, given
, TRUE
))
5911 if (is_mve
&& print_insn_mve (info
, given
))
5914 for (insn
= thumb32_opcodes
; insn
->assembler
; insn
++)
5915 if ((given
& insn
->mask
) == insn
->value
)
5917 bfd_boolean is_clrm
= FALSE
;
5918 bfd_boolean is_unpredictable
= FALSE
;
5919 signed long value_in_comment
= 0;
5920 const char *c
= insn
->assembler
;
5926 func (stream
, "%c", *c
);
5933 func (stream
, "%%");
5938 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
5942 if (ifthen_next_state
)
5943 func (stream
, "\t; unpredictable branch in IT block\n");
5948 func (stream
, "\t; unpredictable <IT:%s>",
5949 arm_conditional
[IFTHEN_COND
]);
5954 unsigned int imm12
= 0;
5956 imm12
|= (given
& 0x000000ffu
);
5957 imm12
|= (given
& 0x00007000u
) >> 4;
5958 imm12
|= (given
& 0x04000000u
) >> 15;
5959 func (stream
, "#%u", imm12
);
5960 value_in_comment
= imm12
;
5966 unsigned int bits
= 0, imm
, imm8
, mod
;
5968 bits
|= (given
& 0x000000ffu
);
5969 bits
|= (given
& 0x00007000u
) >> 4;
5970 bits
|= (given
& 0x04000000u
) >> 15;
5971 imm8
= (bits
& 0x0ff);
5972 mod
= (bits
& 0xf00) >> 8;
5975 case 0: imm
= imm8
; break;
5976 case 1: imm
= ((imm8
<< 16) | imm8
); break;
5977 case 2: imm
= ((imm8
<< 24) | (imm8
<< 8)); break;
5978 case 3: imm
= ((imm8
<< 24) | (imm8
<< 16) | (imm8
<< 8) | imm8
); break;
5980 mod
= (bits
& 0xf80) >> 7;
5981 imm8
= (bits
& 0x07f) | 0x80;
5982 imm
= (((imm8
<< (32 - mod
)) | (imm8
>> mod
)) & 0xffffffff);
5984 func (stream
, "#%u", imm
);
5985 value_in_comment
= imm
;
5991 unsigned int imm
= 0;
5993 imm
|= (given
& 0x000000ffu
);
5994 imm
|= (given
& 0x00007000u
) >> 4;
5995 imm
|= (given
& 0x04000000u
) >> 15;
5996 imm
|= (given
& 0x000f0000u
) >> 4;
5997 func (stream
, "#%u", imm
);
5998 value_in_comment
= imm
;
6004 unsigned int imm
= 0;
6006 imm
|= (given
& 0x000f0000u
) >> 16;
6007 imm
|= (given
& 0x00000ff0u
) >> 0;
6008 imm
|= (given
& 0x0000000fu
) << 12;
6009 func (stream
, "#%u", imm
);
6010 value_in_comment
= imm
;
6016 unsigned int imm
= 0;
6018 imm
|= (given
& 0x000f0000u
) >> 4;
6019 imm
|= (given
& 0x00000fffu
) >> 0;
6020 func (stream
, "#%u", imm
);
6021 value_in_comment
= imm
;
6027 unsigned int imm
= 0;
6029 imm
|= (given
& 0x00000fffu
);
6030 imm
|= (given
& 0x000f0000u
) >> 4;
6031 func (stream
, "#%u", imm
);
6032 value_in_comment
= imm
;
6038 unsigned int reg
= (given
& 0x0000000fu
);
6039 unsigned int stp
= (given
& 0x00000030u
) >> 4;
6040 unsigned int imm
= 0;
6041 imm
|= (given
& 0x000000c0u
) >> 6;
6042 imm
|= (given
& 0x00007000u
) >> 10;
6044 func (stream
, "%s", arm_regnames
[reg
]);
6049 func (stream
, ", lsl #%u", imm
);
6055 func (stream
, ", lsr #%u", imm
);
6061 func (stream
, ", asr #%u", imm
);
6066 func (stream
, ", rrx");
6068 func (stream
, ", ror #%u", imm
);
6075 unsigned int Rn
= (given
& 0x000f0000) >> 16;
6076 unsigned int U
= ! NEGATIVE_BIT_SET
;
6077 unsigned int op
= (given
& 0x00000f00) >> 8;
6078 unsigned int i12
= (given
& 0x00000fff);
6079 unsigned int i8
= (given
& 0x000000ff);
6080 bfd_boolean writeback
= FALSE
, postind
= FALSE
;
6083 func (stream
, "[%s", arm_regnames
[Rn
]);
6084 if (U
) /* 12-bit positive immediate offset. */
6088 value_in_comment
= offset
;
6090 else if (Rn
== 15) /* 12-bit negative immediate offset. */
6091 offset
= - (int) i12
;
6092 else if (op
== 0x0) /* Shifted register offset. */
6094 unsigned int Rm
= (i8
& 0x0f);
6095 unsigned int sh
= (i8
& 0x30) >> 4;
6097 func (stream
, ", %s", arm_regnames
[Rm
]);
6099 func (stream
, ", lsl #%u", sh
);
6105 case 0xE: /* 8-bit positive immediate offset. */
6109 case 0xC: /* 8-bit negative immediate offset. */
6113 case 0xF: /* 8-bit + preindex with wb. */
6118 case 0xD: /* 8-bit - preindex with wb. */
6123 case 0xB: /* 8-bit + postindex. */
6128 case 0x9: /* 8-bit - postindex. */
6134 func (stream
, ", <undefined>]");
6139 func (stream
, "], #%d", (int) offset
);
6143 func (stream
, ", #%d", (int) offset
);
6144 func (stream
, writeback
? "]!" : "]");
6149 func (stream
, "\t; ");
6150 info
->print_address_func (((pc
+ 4) & ~3) + offset
, info
);
6158 unsigned int U
= ! NEGATIVE_BIT_SET
;
6159 unsigned int W
= WRITEBACK_BIT_SET
;
6160 unsigned int Rn
= (given
& 0x000f0000) >> 16;
6161 unsigned int off
= (given
& 0x000000ff);
6163 func (stream
, "[%s", arm_regnames
[Rn
]);
6169 func (stream
, ", #%c%u", U
? '+' : '-', off
* 4);
6170 value_in_comment
= off
* 4 * (U
? 1 : -1);
6178 func (stream
, "], ");
6181 func (stream
, "#%c%u", U
? '+' : '-', off
* 4);
6182 value_in_comment
= off
* 4 * (U
? 1 : -1);
6186 func (stream
, "{%u}", off
);
6187 value_in_comment
= off
;
6195 unsigned int Sbit
= (given
& 0x01000000) >> 24;
6196 unsigned int type
= (given
& 0x00600000) >> 21;
6200 case 0: func (stream
, Sbit
? "sb" : "b"); break;
6201 case 1: func (stream
, Sbit
? "sh" : "h"); break;
6204 func (stream
, "??");
6207 func (stream
, "??");
6222 for (reg
= 0; reg
< 16; reg
++)
6223 if ((given
& (1 << reg
)) != 0)
6226 func (stream
, ", ");
6228 if (is_clrm
&& reg
== 13)
6229 func (stream
, "(invalid: %s)", arm_regnames
[reg
]);
6230 else if (is_clrm
&& reg
== 15)
6231 func (stream
, "%s", "APSR");
6233 func (stream
, "%s", arm_regnames
[reg
]);
6241 unsigned int msb
= (given
& 0x0000001f);
6242 unsigned int lsb
= 0;
6244 lsb
|= (given
& 0x000000c0u
) >> 6;
6245 lsb
|= (given
& 0x00007000u
) >> 10;
6246 func (stream
, "#%u, #%u", lsb
, msb
- lsb
+ 1);
6252 unsigned int width
= (given
& 0x0000001f) + 1;
6253 unsigned int lsb
= 0;
6255 lsb
|= (given
& 0x000000c0u
) >> 6;
6256 lsb
|= (given
& 0x00007000u
) >> 10;
6257 func (stream
, "#%u, #%u", lsb
, width
);
6263 unsigned int boff
= (((given
& 0x07800000) >> 23) << 1);
6264 func (stream
, "%x", boff
);
6270 unsigned int immA
= (given
& 0x001f0000u
) >> 16;
6271 unsigned int immB
= (given
& 0x000007feu
) >> 1;
6272 unsigned int immC
= (given
& 0x00000800u
) >> 11;
6275 offset
|= immA
<< 12;
6276 offset
|= immB
<< 2;
6277 offset
|= immC
<< 1;
6279 offset
= (offset
& 0x10000) ? offset
- (1 << 17) : offset
;
6281 info
->print_address_func (pc
+ 4 + offset
, info
);
6287 unsigned int immA
= (given
& 0x007f0000u
) >> 16;
6288 unsigned int immB
= (given
& 0x000007feu
) >> 1;
6289 unsigned int immC
= (given
& 0x00000800u
) >> 11;
6292 offset
|= immA
<< 12;
6293 offset
|= immB
<< 2;
6294 offset
|= immC
<< 1;
6296 offset
= (offset
& 0x40000) ? offset
- (1 << 19) : offset
;
6298 info
->print_address_func (pc
+ 4 + offset
, info
);
6304 unsigned int immA
= (given
& 0x00010000u
) >> 16;
6305 unsigned int immB
= (given
& 0x000007feu
) >> 1;
6306 unsigned int immC
= (given
& 0x00000800u
) >> 11;
6309 offset
|= immA
<< 12;
6310 offset
|= immB
<< 2;
6311 offset
|= immC
<< 1;
6313 offset
= (offset
& 0x1000) ? offset
- (1 << 13) : offset
;
6315 info
->print_address_func (pc
+ 4 + offset
, info
);
6317 unsigned int T
= (given
& 0x00020000u
) >> 17;
6318 unsigned int endoffset
= (((given
& 0x07800000) >> 23) << 1);
6319 unsigned int boffset
= (T
== 1) ? 4 : 2;
6320 func (stream
, ", ");
6321 func (stream
, "%x", endoffset
+ boffset
);
6327 unsigned int immh
= (given
& 0x000007feu
) >> 1;
6328 unsigned int imml
= (given
& 0x00000800u
) >> 11;
6334 info
->print_address_func (pc
+ 4 + imm32
, info
);
6340 unsigned int immh
= (given
& 0x000007feu
) >> 1;
6341 unsigned int imml
= (given
& 0x00000800u
) >> 11;
6347 info
->print_address_func (pc
+ 4 - imm32
, info
);
6353 unsigned int S
= (given
& 0x04000000u
) >> 26;
6354 unsigned int J1
= (given
& 0x00002000u
) >> 13;
6355 unsigned int J2
= (given
& 0x00000800u
) >> 11;
6361 offset
|= (given
& 0x003f0000) >> 4;
6362 offset
|= (given
& 0x000007ff) << 1;
6363 offset
-= (1 << 20);
6365 info
->print_address_func (pc
+ 4 + offset
, info
);
6371 unsigned int S
= (given
& 0x04000000u
) >> 26;
6372 unsigned int I1
= (given
& 0x00002000u
) >> 13;
6373 unsigned int I2
= (given
& 0x00000800u
) >> 11;
6377 offset
|= !(I1
^ S
) << 23;
6378 offset
|= !(I2
^ S
) << 22;
6379 offset
|= (given
& 0x03ff0000u
) >> 4;
6380 offset
|= (given
& 0x000007ffu
) << 1;
6381 offset
-= (1 << 24);
6384 /* BLX target addresses are always word aligned. */
6385 if ((given
& 0x00001000u
) == 0)
6388 info
->print_address_func (offset
, info
);
6394 unsigned int shift
= 0;
6396 shift
|= (given
& 0x000000c0u
) >> 6;
6397 shift
|= (given
& 0x00007000u
) >> 10;
6398 if (WRITEBACK_BIT_SET
)
6399 func (stream
, ", asr #%u", shift
);
6401 func (stream
, ", lsl #%u", shift
);
6402 /* else print nothing - lsl #0 */
6408 unsigned int rot
= (given
& 0x00000030) >> 4;
6411 func (stream
, ", ror #%u", rot
* 8);
6416 if ((given
& 0xf0) == 0x60)
6418 switch (given
& 0xf)
6420 case 0xf: func (stream
, "sy"); break;
6422 func (stream
, "#%d", (int) given
& 0xf);
6428 const char * opt
= data_barrier_option (given
& 0xf);
6430 func (stream
, "%s", opt
);
6432 func (stream
, "#%d", (int) given
& 0xf);
6437 if ((given
& 0xff) == 0)
6439 func (stream
, "%cPSR_", (given
& 0x100000) ? 'S' : 'C');
6449 else if ((given
& 0x20) == 0x20)
6452 unsigned sysm
= (given
& 0xf00) >> 8;
6454 sysm
|= (given
& 0x30);
6455 sysm
|= (given
& 0x00100000) >> 14;
6456 name
= banked_regname (sysm
);
6459 func (stream
, "%s", name
);
6461 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
6465 func (stream
, "%s", psr_name (given
& 0xff));
6470 if (((given
& 0xff) == 0)
6471 || ((given
& 0x20) == 0x20))
6474 unsigned sm
= (given
& 0xf0000) >> 16;
6476 sm
|= (given
& 0x30);
6477 sm
|= (given
& 0x00100000) >> 14;
6478 name
= banked_regname (sm
);
6481 func (stream
, "%s", name
);
6483 func (stream
, "(UNDEF: %lu)", (unsigned long) sm
);
6486 func (stream
, "%s", psr_name (given
& 0xff));
6489 case '0': case '1': case '2': case '3': case '4':
6490 case '5': case '6': case '7': case '8': case '9':
6495 c
= arm_decode_bitfield (c
, given
, &val
, &width
);
6500 func (stream
, "%lu", val
);
6501 value_in_comment
= val
;
6505 func (stream
, "%lu", val
+ 1);
6506 value_in_comment
= val
+ 1;
6510 func (stream
, "%lu", val
* 4);
6511 value_in_comment
= val
* 4;
6516 is_unpredictable
= TRUE
;
6520 is_unpredictable
= TRUE
;
6523 func (stream
, "%s", arm_regnames
[val
]);
6527 func (stream
, "%s", arm_conditional
[val
]);
6532 if (val
== ((1ul << width
) - 1))
6533 func (stream
, "%c", *c
);
6539 func (stream
, "%c", *c
);
6543 func (stream
, "%c", c
[(1 << width
) - (int) val
]);
6548 func (stream
, "0x%lx", val
& 0xffffffffUL
);
6558 /* PR binutils/12534
6559 If we have a PC relative offset in an LDRD or STRD
6560 instructions then display the decoded address. */
6561 if (((given
>> 16) & 0xf) == 0xf)
6563 bfd_vma offset
= (given
& 0xff) * 4;
6565 if ((given
& (1 << 23)) == 0)
6567 func (stream
, "\t; ");
6568 info
->print_address_func ((pc
& ~3) + 4 + offset
, info
);
6577 if (value_in_comment
> 32 || value_in_comment
< -16)
6578 func (stream
, "\t; 0x%lx", value_in_comment
);
6580 if (is_unpredictable
)
6581 func (stream
, UNPREDICTABLE_INSTRUCTION
);
6587 func (stream
, UNKNOWN_INSTRUCTION_32BIT
, (unsigned)given
);
6591 /* Print data bytes on INFO->STREAM. */
6594 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED
,
6595 struct disassemble_info
*info
,
6598 switch (info
->bytes_per_chunk
)
6601 info
->fprintf_func (info
->stream
, ".byte\t0x%02lx", given
);
6604 info
->fprintf_func (info
->stream
, ".short\t0x%04lx", given
);
6607 info
->fprintf_func (info
->stream
, ".word\t0x%08lx", given
);
6614 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
6615 being displayed in symbol relative addresses.
6617 Also disallow private symbol, with __tagsym$$ prefix,
6618 from ARM RVCT toolchain being displayed. */
6621 arm_symbol_is_valid (asymbol
* sym
,
6622 struct disassemble_info
* info ATTRIBUTE_UNUSED
)
6629 name
= bfd_asymbol_name (sym
);
6631 return (name
&& *name
!= '$' && strncmp (name
, "__tagsym$$", 10));
6634 /* Parse the string of disassembler options. */
6637 parse_arm_disassembler_options (const char *options
)
6641 FOR_EACH_DISASSEMBLER_OPTION (opt
, options
)
6643 if (CONST_STRNEQ (opt
, "reg-names-"))
6646 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
6647 if (disassembler_options_cmp (opt
, regnames
[i
].name
) == 0)
6649 regname_selected
= i
;
6653 if (i
>= NUM_ARM_OPTIONS
)
6654 /* xgettext: c-format */
6655 opcodes_error_handler (_("unrecognised register name set: %s"),
6658 else if (CONST_STRNEQ (opt
, "force-thumb"))
6660 else if (CONST_STRNEQ (opt
, "no-force-thumb"))
6663 /* xgettext: c-format */
6664 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt
);
6671 mapping_symbol_for_insn (bfd_vma pc
, struct disassemble_info
*info
,
6672 enum map_type
*map_symbol
);
6674 /* Search back through the insn stream to determine if this instruction is
6675 conditionally executed. */
6678 find_ifthen_state (bfd_vma pc
,
6679 struct disassemble_info
*info
,
6685 /* COUNT is twice the number of instructions seen. It will be odd if we
6686 just crossed an instruction boundary. */
6689 unsigned int seen_it
;
6692 ifthen_address
= pc
;
6699 /* Scan backwards looking for IT instructions, keeping track of where
6700 instruction boundaries are. We don't know if something is actually an
6701 IT instruction until we find a definite instruction boundary. */
6704 if (addr
== 0 || info
->symbol_at_address_func (addr
, info
))
6706 /* A symbol must be on an instruction boundary, and will not
6707 be within an IT block. */
6708 if (seen_it
&& (count
& 1))
6714 status
= info
->read_memory_func (addr
, (bfd_byte
*) b
, 2, info
);
6719 insn
= (b
[0]) | (b
[1] << 8);
6721 insn
= (b
[1]) | (b
[0] << 8);
6724 if ((insn
& 0xf800) < 0xe800)
6726 /* Addr + 2 is an instruction boundary. See if this matches
6727 the expected boundary based on the position of the last
6734 if ((insn
& 0xff00) == 0xbf00 && (insn
& 0xf) != 0)
6736 enum map_type type
= MAP_ARM
;
6737 bfd_boolean found
= mapping_symbol_for_insn (addr
, info
, &type
);
6739 if (!found
|| (found
&& type
== MAP_THUMB
))
6741 /* This could be an IT instruction. */
6743 it_count
= count
>> 1;
6746 if ((insn
& 0xf800) >= 0xe800)
6749 count
= (count
+ 2) | 1;
6750 /* IT blocks contain at most 4 instructions. */
6751 if (count
>= 8 && !seen_it
)
6754 /* We found an IT instruction. */
6755 ifthen_state
= (seen_it
& 0xe0) | ((seen_it
<< it_count
) & 0x1f);
6756 if ((ifthen_state
& 0xf) == 0)
6760 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
6764 is_mapping_symbol (struct disassemble_info
*info
, int n
,
6765 enum map_type
*map_type
)
6769 name
= bfd_asymbol_name (info
->symtab
[n
]);
6770 if (name
[0] == '$' && (name
[1] == 'a' || name
[1] == 't' || name
[1] == 'd')
6771 && (name
[2] == 0 || name
[2] == '.'))
6773 *map_type
= ((name
[1] == 'a') ? MAP_ARM
6774 : (name
[1] == 't') ? MAP_THUMB
6782 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
6783 Returns nonzero if *MAP_TYPE was set. */
6786 get_map_sym_type (struct disassemble_info
*info
,
6788 enum map_type
*map_type
)
6790 /* If the symbol is in a different section, ignore it. */
6791 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
6794 return is_mapping_symbol (info
, n
, map_type
);
6797 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
6798 Returns nonzero if *MAP_TYPE was set. */
6801 get_sym_code_type (struct disassemble_info
*info
,
6803 enum map_type
*map_type
)
6805 elf_symbol_type
*es
;
6808 /* If the symbol is in a different section, ignore it. */
6809 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
6812 es
= *(elf_symbol_type
**)(info
->symtab
+ n
);
6813 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
6815 /* If the symbol has function type then use that. */
6816 if (type
== STT_FUNC
|| type
== STT_GNU_IFUNC
)
6818 if (ARM_GET_SYM_BRANCH_TYPE (es
->internal_elf_sym
.st_target_internal
)
6819 == ST_BRANCH_TO_THUMB
)
6820 *map_type
= MAP_THUMB
;
6822 *map_type
= MAP_ARM
;
6829 /* Search the mapping symbol state for instruction at pc. This is only
6830 applicable for elf target.
6832 There is an assumption Here, info->private_data contains the correct AND
6833 up-to-date information about current scan process. The information will be
6834 used to speed this search process.
6836 Return TRUE if the mapping state can be determined, and map_symbol
6837 will be updated accordingly. Otherwise, return FALSE. */
6840 mapping_symbol_for_insn (bfd_vma pc
, struct disassemble_info
*info
,
6841 enum map_type
*map_symbol
)
6843 bfd_vma addr
, section_vma
= 0;
6844 int n
, last_sym
= -1;
6845 bfd_boolean found
= FALSE
;
6846 bfd_boolean can_use_search_opt_p
= FALSE
;
6848 /* Default to DATA. A text section is required by the ABI to contain an
6849 INSN mapping symbol at the start. A data section has no such
6850 requirement, hence if no mapping symbol is found the section must
6851 contain only data. This however isn't very useful if the user has
6852 fully stripped the binaries. If this is the case use the section
6853 attributes to determine the default. If we have no section default to
6854 INSN as well, as we may be disassembling some raw bytes on a baremetal
6855 HEX file or similar. */
6856 enum map_type type
= MAP_DATA
;
6857 if ((info
->section
&& info
->section
->flags
& SEC_CODE
) || !info
->section
)
6859 struct arm_private_data
*private_data
;
6861 if (info
->private_data
== NULL
6862 || bfd_asymbol_flavour (*info
->symtab
) != bfd_target_elf_flavour
)
6865 private_data
= info
->private_data
;
6867 /* First, look for mapping symbols. */
6868 if (info
->symtab_size
!= 0)
6870 if (pc
<= private_data
->last_mapping_addr
)
6871 private_data
->last_mapping_sym
= -1;
6873 /* Start scanning at the start of the function, or wherever
6874 we finished last time. */
6875 n
= info
->symtab_pos
+ 1;
6877 /* If the last stop offset is different from the current one it means we
6878 are disassembling a different glob of bytes. As such the optimization
6879 would not be safe and we should start over. */
6880 can_use_search_opt_p
6881 = private_data
->last_mapping_sym
>= 0
6882 && info
->stop_offset
== private_data
->last_stop_offset
;
6884 if (n
>= private_data
->last_mapping_sym
&& can_use_search_opt_p
)
6885 n
= private_data
->last_mapping_sym
;
6887 /* Look down while we haven't passed the location being disassembled.
6888 The reason for this is that there's no defined order between a symbol
6889 and an mapping symbol that may be at the same address. We may have to
6890 look at least one position ahead. */
6891 for (; n
< info
->symtab_size
; n
++)
6893 addr
= bfd_asymbol_value (info
->symtab
[n
]);
6896 if (get_map_sym_type (info
, n
, &type
))
6905 n
= info
->symtab_pos
;
6906 if (n
>= private_data
->last_mapping_sym
&& can_use_search_opt_p
)
6907 n
= private_data
->last_mapping_sym
;
6909 /* No mapping symbol found at this address. Look backwards
6910 for a preceeding one, but don't go pass the section start
6911 otherwise a data section with no mapping symbol can pick up
6912 a text mapping symbol of a preceeding section. The documentation
6913 says section can be NULL, in which case we will seek up all the
6916 section_vma
= info
->section
->vma
;
6920 addr
= bfd_asymbol_value (info
->symtab
[n
]);
6921 if (addr
< section_vma
)
6924 if (get_map_sym_type (info
, n
, &type
))
6934 /* If no mapping symbol was found, try looking up without a mapping
6935 symbol. This is done by walking up from the current PC to the nearest
6936 symbol. We don't actually have to loop here since symtab_pos will
6937 contain the nearest symbol already. */
6940 n
= info
->symtab_pos
;
6941 if (n
>= 0 && get_sym_code_type (info
, n
, &type
))
6948 private_data
->last_mapping_sym
= last_sym
;
6949 private_data
->last_type
= type
;
6950 private_data
->last_stop_offset
= info
->stop_offset
;
6956 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
6957 of the supplied arm_feature_set structure with bitmasks indicating
6958 the supported base architectures and coprocessor extensions.
6960 FIXME: This could more efficiently implemented as a constant array,
6961 although it would also be less robust. */
6964 select_arm_features (unsigned long mach
,
6965 arm_feature_set
* features
)
6967 arm_feature_set arch_fset
;
6968 const arm_feature_set fpu_any
= FPU_ANY
;
6970 #undef ARM_SET_FEATURES
6971 #define ARM_SET_FEATURES(FSET) \
6973 const arm_feature_set fset = FSET; \
6977 /* When several architecture versions share the same bfd_mach_arm_XXX value
6978 the most featureful is chosen. */
6981 case bfd_mach_arm_2
: ARM_SET_FEATURES (ARM_ARCH_V2
); break;
6982 case bfd_mach_arm_2a
: ARM_SET_FEATURES (ARM_ARCH_V2S
); break;
6983 case bfd_mach_arm_3
: ARM_SET_FEATURES (ARM_ARCH_V3
); break;
6984 case bfd_mach_arm_3M
: ARM_SET_FEATURES (ARM_ARCH_V3M
); break;
6985 case bfd_mach_arm_4
: ARM_SET_FEATURES (ARM_ARCH_V4
); break;
6986 case bfd_mach_arm_4T
: ARM_SET_FEATURES (ARM_ARCH_V4T
); break;
6987 case bfd_mach_arm_5
: ARM_SET_FEATURES (ARM_ARCH_V5
); break;
6988 case bfd_mach_arm_5T
: ARM_SET_FEATURES (ARM_ARCH_V5T
); break;
6989 case bfd_mach_arm_5TE
: ARM_SET_FEATURES (ARM_ARCH_V5TE
); break;
6990 case bfd_mach_arm_XScale
: ARM_SET_FEATURES (ARM_ARCH_XSCALE
); break;
6991 case bfd_mach_arm_ep9312
:
6992 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T
,
6993 ARM_CEXT_MAVERICK
| FPU_MAVERICK
));
6995 case bfd_mach_arm_iWMMXt
: ARM_SET_FEATURES (ARM_ARCH_IWMMXT
); break;
6996 case bfd_mach_arm_iWMMXt2
: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2
); break;
6997 case bfd_mach_arm_5TEJ
: ARM_SET_FEATURES (ARM_ARCH_V5TEJ
); break;
6998 case bfd_mach_arm_6
: ARM_SET_FEATURES (ARM_ARCH_V6
); break;
6999 case bfd_mach_arm_6KZ
: ARM_SET_FEATURES (ARM_ARCH_V6KZ
); break;
7000 case bfd_mach_arm_6T2
: ARM_SET_FEATURES (ARM_ARCH_V6KZT2
); break;
7001 case bfd_mach_arm_6K
: ARM_SET_FEATURES (ARM_ARCH_V6K
); break;
7002 case bfd_mach_arm_7
: ARM_SET_FEATURES (ARM_ARCH_V7VE
); break;
7003 case bfd_mach_arm_6M
: ARM_SET_FEATURES (ARM_ARCH_V6M
); break;
7004 case bfd_mach_arm_6SM
: ARM_SET_FEATURES (ARM_ARCH_V6SM
); break;
7005 case bfd_mach_arm_7EM
: ARM_SET_FEATURES (ARM_ARCH_V7EM
); break;
7006 case bfd_mach_arm_8
:
7008 /* Add bits for extensions that Armv8.5-A recognizes. */
7009 arm_feature_set armv8_5_ext_fset
7010 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
7011 ARM_SET_FEATURES (ARM_ARCH_V8_5A
);
7012 ARM_MERGE_FEATURE_SETS (arch_fset
, arch_fset
, armv8_5_ext_fset
);
7015 case bfd_mach_arm_8R
: ARM_SET_FEATURES (ARM_ARCH_V8R
); break;
7016 case bfd_mach_arm_8M_BASE
: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE
); break;
7017 case bfd_mach_arm_8M_MAIN
: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN
); break;
7018 case bfd_mach_arm_8_1M_MAIN
:
7019 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN
);
7022 /* If the machine type is unknown allow all architecture types and all
7024 case bfd_mach_arm_unknown
: ARM_SET_FEATURES (ARM_FEATURE_ALL
); break;
7028 #undef ARM_SET_FEATURES
7030 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
7031 and thus on bfd_mach_arm_XXX value. Therefore for a given
7032 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
7033 ARM_MERGE_FEATURE_SETS (*features
, arch_fset
, fpu_any
);
7037 /* NOTE: There are no checks in these routines that
7038 the relevant number of data bytes exist. */
7041 print_insn (bfd_vma pc
, struct disassemble_info
*info
, bfd_boolean little
)
7046 int is_thumb
= FALSE
;
7047 int is_data
= FALSE
;
7049 unsigned int size
= 4;
7050 void (*printer
) (bfd_vma
, struct disassemble_info
*, long);
7051 bfd_boolean found
= FALSE
;
7052 struct arm_private_data
*private_data
;
7054 if (info
->disassembler_options
)
7056 parse_arm_disassembler_options (info
->disassembler_options
);
7058 /* To avoid repeated parsing of these options, we remove them here. */
7059 info
->disassembler_options
= NULL
;
7062 /* PR 10288: Control which instructions will be disassembled. */
7063 if (info
->private_data
== NULL
)
7065 static struct arm_private_data
private;
7067 if ((info
->flags
& USER_SPECIFIED_MACHINE_TYPE
) == 0)
7068 /* If the user did not use the -m command line switch then default to
7069 disassembling all types of ARM instruction.
7071 The info->mach value has to be ignored as this will be based on
7072 the default archictecture for the target and/or hints in the notes
7073 section, but it will never be greater than the current largest arm
7074 machine value (iWMMXt2), which is only equivalent to the V5TE
7075 architecture. ARM architectures have advanced beyond the machine
7076 value encoding, and these newer architectures would be ignored if
7077 the machine value was used.
7079 Ie the -m switch is used to restrict which instructions will be
7080 disassembled. If it is necessary to use the -m switch to tell
7081 objdump that an ARM binary is being disassembled, eg because the
7082 input is a raw binary file, but it is also desired to disassemble
7083 all ARM instructions then use "-marm". This will select the
7084 "unknown" arm architecture which is compatible with any ARM
7086 info
->mach
= bfd_mach_arm_unknown
;
7088 /* Compute the architecture bitmask from the machine number.
7089 Note: This assumes that the machine number will not change
7090 during disassembly.... */
7091 select_arm_features (info
->mach
, & private.features
);
7093 private.last_mapping_sym
= -1;
7094 private.last_mapping_addr
= 0;
7095 private.last_stop_offset
= 0;
7097 info
->private_data
= & private;
7100 private_data
= info
->private_data
;
7102 /* Decide if our code is going to be little-endian, despite what the
7103 function argument might say. */
7104 little_code
= ((info
->endian_code
== BFD_ENDIAN_LITTLE
) || little
);
7106 /* For ELF, consult the symbol table to determine what kind of code
7108 if (info
->symtab_size
!= 0
7109 && bfd_asymbol_flavour (*info
->symtab
) == bfd_target_elf_flavour
)
7114 enum map_type type
= MAP_ARM
;
7116 found
= mapping_symbol_for_insn (pc
, info
, &type
);
7117 last_sym
= private_data
->last_mapping_sym
;
7119 is_thumb
= (private_data
->last_type
== MAP_THUMB
);
7120 is_data
= (private_data
->last_type
== MAP_DATA
);
7122 /* Look a little bit ahead to see if we should print out
7123 two or four bytes of data. If there's a symbol,
7124 mapping or otherwise, after two bytes then don't
7128 size
= 4 - (pc
& 3);
7129 for (n
= last_sym
+ 1; n
< info
->symtab_size
; n
++)
7131 addr
= bfd_asymbol_value (info
->symtab
[n
]);
7133 && (info
->section
== NULL
7134 || info
->section
== info
->symtab
[n
]->section
))
7136 if (addr
- pc
< size
)
7141 /* If the next symbol is after three bytes, we need to
7142 print only part of the data, so that we can use either
7145 size
= (pc
& 1) ? 1 : 2;
7149 if (info
->symbols
!= NULL
)
7151 if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_coff_flavour
)
7153 coff_symbol_type
* cs
;
7155 cs
= coffsymbol (*info
->symbols
);
7156 is_thumb
= ( cs
->native
->u
.syment
.n_sclass
== C_THUMBEXT
7157 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTAT
7158 || cs
->native
->u
.syment
.n_sclass
== C_THUMBLABEL
7159 || cs
->native
->u
.syment
.n_sclass
== C_THUMBEXTFUNC
7160 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTATFUNC
);
7162 else if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_elf_flavour
7165 /* If no mapping symbol has been found then fall back to the type
7166 of the function symbol. */
7167 elf_symbol_type
* es
;
7170 es
= *(elf_symbol_type
**)(info
->symbols
);
7171 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
7174 ((ARM_GET_SYM_BRANCH_TYPE (es
->internal_elf_sym
.st_target_internal
)
7175 == ST_BRANCH_TO_THUMB
) || type
== STT_ARM_16BIT
);
7177 else if (bfd_asymbol_flavour (*info
->symbols
)
7178 == bfd_target_mach_o_flavour
)
7180 bfd_mach_o_asymbol
*asym
= (bfd_mach_o_asymbol
*)*info
->symbols
;
7182 is_thumb
= (asym
->n_desc
& BFD_MACH_O_N_ARM_THUMB_DEF
);
7190 info
->display_endian
= little
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
7192 info
->display_endian
= little_code
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
7194 info
->bytes_per_line
= 4;
7196 /* PR 10263: Disassemble data if requested to do so by the user. */
7197 if (is_data
&& ((info
->flags
& DISASSEMBLE_DATA
) == 0))
7201 /* Size was already set above. */
7202 info
->bytes_per_chunk
= size
;
7203 printer
= print_insn_data
;
7205 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, size
, info
);
7208 for (i
= size
- 1; i
>= 0; i
--)
7209 given
= b
[i
] | (given
<< 8);
7211 for (i
= 0; i
< (int) size
; i
++)
7212 given
= b
[i
] | (given
<< 8);
7216 /* In ARM mode endianness is a straightforward issue: the instruction
7217 is four bytes long and is either ordered 0123 or 3210. */
7218 printer
= print_insn_arm
;
7219 info
->bytes_per_chunk
= 4;
7222 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 4, info
);
7224 given
= (b
[0]) | (b
[1] << 8) | (b
[2] << 16) | (b
[3] << 24);
7226 given
= (b
[3]) | (b
[2] << 8) | (b
[1] << 16) | (b
[0] << 24);
7230 /* In Thumb mode we have the additional wrinkle of two
7231 instruction lengths. Fortunately, the bits that determine
7232 the length of the current instruction are always to be found
7233 in the first two bytes. */
7234 printer
= print_insn_thumb16
;
7235 info
->bytes_per_chunk
= 2;
7238 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 2, info
);
7240 given
= (b
[0]) | (b
[1] << 8);
7242 given
= (b
[1]) | (b
[0] << 8);
7246 /* These bit patterns signal a four-byte Thumb
7248 if ((given
& 0xF800) == 0xF800
7249 || (given
& 0xF800) == 0xF000
7250 || (given
& 0xF800) == 0xE800)
7252 status
= info
->read_memory_func (pc
+ 2, (bfd_byte
*) b
, 2, info
);
7254 given
= (b
[0]) | (b
[1] << 8) | (given
<< 16);
7256 given
= (b
[1]) | (b
[0] << 8) | (given
<< 16);
7258 printer
= print_insn_thumb32
;
7263 if (ifthen_address
!= pc
)
7264 find_ifthen_state (pc
, info
, little_code
);
7268 if ((ifthen_state
& 0xf) == 0x8)
7269 ifthen_next_state
= 0;
7271 ifthen_next_state
= (ifthen_state
& 0xe0)
7272 | ((ifthen_state
& 0xf) << 1);
7278 info
->memory_error_func (status
, pc
, info
);
7281 if (info
->flags
& INSN_HAS_RELOC
)
7282 /* If the instruction has a reloc associated with it, then
7283 the offset field in the instruction will actually be the
7284 addend for the reloc. (We are using REL type relocs).
7285 In such cases, we can ignore the pc when computing
7286 addresses, since the addend is not currently pc-relative. */
7289 printer (pc
, info
, given
);
7293 ifthen_state
= ifthen_next_state
;
7294 ifthen_address
+= size
;
7300 print_insn_big_arm (bfd_vma pc
, struct disassemble_info
*info
)
7302 /* Detect BE8-ness and record it in the disassembler info. */
7303 if (info
->flavour
== bfd_target_elf_flavour
7304 && info
->section
!= NULL
7305 && (elf_elfheader (info
->section
->owner
)->e_flags
& EF_ARM_BE8
))
7306 info
->endian_code
= BFD_ENDIAN_LITTLE
;
7308 return print_insn (pc
, info
, FALSE
);
7312 print_insn_little_arm (bfd_vma pc
, struct disassemble_info
*info
)
7314 return print_insn (pc
, info
, TRUE
);
7317 const disasm_options_and_args_t
*
7318 disassembler_options_arm (void)
7320 static disasm_options_and_args_t
*opts_and_args
;
7322 if (opts_and_args
== NULL
)
7324 disasm_options_t
*opts
;
7327 opts_and_args
= XNEW (disasm_options_and_args_t
);
7328 opts_and_args
->args
= NULL
;
7330 opts
= &opts_and_args
->options
;
7331 opts
->name
= XNEWVEC (const char *, NUM_ARM_OPTIONS
+ 1);
7332 opts
->description
= XNEWVEC (const char *, NUM_ARM_OPTIONS
+ 1);
7334 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
7336 opts
->name
[i
] = regnames
[i
].name
;
7337 if (regnames
[i
].description
!= NULL
)
7338 opts
->description
[i
] = _(regnames
[i
].description
);
7340 opts
->description
[i
] = NULL
;
7342 /* The array we return must be NULL terminated. */
7343 opts
->name
[i
] = NULL
;
7344 opts
->description
[i
] = NULL
;
7347 return opts_and_args
;
7351 print_arm_disassembler_options (FILE *stream
)
7353 unsigned int i
, max_len
= 0;
7354 fprintf (stream
, _("\n\
7355 The following ARM specific disassembler options are supported for use with\n\
7356 the -M switch:\n"));
7358 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
7360 unsigned int len
= strlen (regnames
[i
].name
);
7365 for (i
= 0, max_len
++; i
< NUM_ARM_OPTIONS
; i
++)
7366 fprintf (stream
, " %s%*c %s\n",
7368 (int)(max_len
- strlen (regnames
[i
].name
)), ' ',
7369 _(regnames
[i
].description
));