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opcodes: blackfin: do not force align the PC
[thirdparty/binutils-gdb.git] / opcodes / bfin-dis.c
1 /* Disassemble ADI Blackfin Instructions.
2 Copyright (C) 2005-2014 Free Software Foundation, Inc.
3
4 This file is part of libopcodes.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21 #include "sysdep.h"
22 #include <stdio.h>
23
24 #include "opcode/bfin.h"
25
26 #ifndef PRINTF
27 #define PRINTF printf
28 #endif
29
30 #ifndef EXIT
31 #define EXIT exit
32 #endif
33
34 typedef long TIword;
35
36 #define HOST_LONG_WORD_SIZE (sizeof (long) * 8)
37 #define XFIELD(w,p,s) (((w) & ((1 << (s)) - 1) << (p)) >> (p))
38 #define SIGNEXTEND(v, n) ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
39 #define MASKBITS(val, bits) (val & ((1 << bits) - 1))
40
41 #include "dis-asm.h"
42
43 typedef unsigned int bu32;
44
45 static char comment = 0;
46 static char parallel = 0;
47
48 typedef enum
49 {
50 c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
51 c_imm4, c_uimm4s4, c_uimm4s4d, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_imm5d, c_uimm5, c_imm6,
52 c_imm7, c_imm7d, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10,
53 c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_imm16d, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4,
54 c_uimm16s4d, c_uimm16, c_pcrel24, c_uimm32, c_imm32, c_huimm32, c_huimm32e,
55 } const_forms_t;
56
57 static const struct
58 {
59 const char *name;
60 const int nbits;
61 const char reloc;
62 const char issigned;
63 const char pcrel;
64 const char scale;
65 const char offset;
66 const char negative;
67 const char positive;
68 const char decimal;
69 const char leading;
70 const char exact;
71 } constant_formats[] =
72 {
73 { "0", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
74 { "1", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
75 { "4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
76 { "2", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
77 { "uimm2", 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
78 { "uimm3", 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
79 { "imm3", 3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
80 { "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
81 { "imm4", 4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
82 { "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0},
83 { "uimm4s4d", 4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0},
84 { "uimm4", 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
85 { "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0},
86 { "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0},
87 { "imm5", 5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
88 { "imm5d", 5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0},
89 { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
90 { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
91 { "imm7", 7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
92 { "imm7d", 7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
93 { "imm8", 8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
94 { "uimm8", 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
95 { "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
96 { "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
97 { "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0},
98 { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
99 { "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
100 { "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
101 { "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0},
102 { "luimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
103 { "imm16", 16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
104 { "imm16d", 16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
105 { "huimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
106 { "rimm16", 16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
107 { "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0},
108 { "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
109 { "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0},
110 { "uimm16", 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
111 { "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
112 { "uimm32", 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
113 { "imm32", 32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
114 { "huimm32", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
115 { "huimm32e", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1},
116 };
117
118 static const char *
119 fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info *outf)
120 {
121 static char buf[60];
122
123 if (constant_formats[cf].reloc)
124 {
125 bfd_vma ea = (((constant_formats[cf].pcrel ? SIGNEXTEND (x, constant_formats[cf].nbits)
126 : x) + constant_formats[cf].offset) << constant_formats[cf].scale);
127 if (constant_formats[cf].pcrel)
128 ea += pc;
129
130 /* truncate to 32-bits for proper symbol lookup/matching */
131 ea = (bu32)ea;
132
133 if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact)
134 {
135 outf->print_address_func (ea, outf);
136 return "";
137 }
138 else
139 {
140 sprintf (buf, "%lx", (unsigned long) x);
141 return buf;
142 }
143 }
144
145 /* Negative constants have an implied sign bit. */
146 if (constant_formats[cf].negative)
147 {
148 int nb = constant_formats[cf].nbits + 1;
149
150 x = x | (1 << constant_formats[cf].nbits);
151 x = SIGNEXTEND (x, nb);
152 }
153 else
154 x = constant_formats[cf].issigned ? SIGNEXTEND (x, constant_formats[cf].nbits) : x;
155
156 if (constant_formats[cf].offset)
157 x += constant_formats[cf].offset;
158
159 if (constant_formats[cf].scale)
160 x <<= constant_formats[cf].scale;
161
162 if (constant_formats[cf].decimal)
163 sprintf (buf, "%*li", constant_formats[cf].leading, x);
164 else
165 {
166 if (constant_formats[cf].issigned && x < 0)
167 sprintf (buf, "-0x%x", abs (x));
168 else
169 sprintf (buf, "0x%lx", (unsigned long) x);
170 }
171
172 return buf;
173 }
174
175 static bu32
176 fmtconst_val (const_forms_t cf, unsigned int x, unsigned int pc)
177 {
178 if (0 && constant_formats[cf].reloc)
179 {
180 bu32 ea = (((constant_formats[cf].pcrel
181 ? SIGNEXTEND (x, constant_formats[cf].nbits)
182 : x) + constant_formats[cf].offset)
183 << constant_formats[cf].scale);
184 if (constant_formats[cf].pcrel)
185 ea += pc;
186
187 return ea;
188 }
189
190 /* Negative constants have an implied sign bit. */
191 if (constant_formats[cf].negative)
192 {
193 int nb = constant_formats[cf].nbits + 1;
194 x = x | (1 << constant_formats[cf].nbits);
195 x = SIGNEXTEND (x, nb);
196 }
197 else if (constant_formats[cf].issigned)
198 x = SIGNEXTEND (x, constant_formats[cf].nbits);
199
200 x += constant_formats[cf].offset;
201 x <<= constant_formats[cf].scale;
202
203 return x;
204 }
205
206 enum machine_registers
207 {
208 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
209 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
210 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
211 REG_R1_0, REG_R3_2, REG_R5_4, REG_R7_6, REG_P0, REG_P1, REG_P2, REG_P3,
212 REG_P4, REG_P5, REG_SP, REG_FP, REG_A0x, REG_A1x, REG_A0w, REG_A1w,
213 REG_A0, REG_A1, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1,
214 REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1,
215 REG_L2, REG_L3,
216 REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S,
217 REG_AQ, REG_V, REG_VS,
218 REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0,
219 REG_LC1, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1,
220 REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN,
221 REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6,
222 REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
223 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
224 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
225 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
226 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
227 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
228 REG_AC0_COPY, REG_V_COPY, REG_RND_MOD,
229 REG_LASTREG,
230 };
231
232 enum reg_class
233 {
234 rc_dregs_lo, rc_dregs_hi, rc_dregs, rc_dregs_pair, rc_pregs, rc_spfp, rc_dregs_hilo, rc_accum_ext,
235 rc_accum_word, rc_accum, rc_iregs, rc_mregs, rc_bregs, rc_lregs, rc_dpregs, rc_gregs,
236 rc_regs, rc_statbits, rc_ignore_bits, rc_ccstat, rc_counters, rc_dregs2_sysregs1, rc_open, rc_sysregs2,
237 rc_sysregs3, rc_allregs,
238 LIM_REG_CLASSES
239 };
240
241 static const char * const reg_names[] =
242 {
243 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
244 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
245 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
246 "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3",
247 "P4", "P5", "SP", "FP", "A0.X", "A1.X", "A0.W", "A1.W",
248 "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1",
249 "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1",
250 "L2", "L3",
251 "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
252 "AQ", "V", "VS",
253 "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0",
254 "LC1", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1",
255 "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN",
256 "RETE", "EMUDAT",
257 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",
258 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L",
259 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H",
260 "I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L",
261 "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L",
262 "I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H",
263 "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H",
264 "AC0_COPY", "V_COPY", "RND_MOD",
265 "LASTREG",
266 0
267 };
268
269 #define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......")
270
271 /* RL(0..7). */
272 static const enum machine_registers decode_dregs_lo[] =
273 {
274 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
275 };
276
277 #define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
278
279 /* RH(0..7). */
280 static const enum machine_registers decode_dregs_hi[] =
281 {
282 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
283 };
284
285 #define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
286
287 /* R(0..7). */
288 static const enum machine_registers decode_dregs[] =
289 {
290 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
291 };
292
293 #define dregs(x) REGNAME (decode_dregs[(x) & 7])
294
295 /* R BYTE(0..7). */
296 static const enum machine_registers decode_dregs_byte[] =
297 {
298 REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
299 };
300
301 #define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
302
303 /* P(0..5) SP FP. */
304 static const enum machine_registers decode_pregs[] =
305 {
306 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
307 };
308
309 #define pregs(x) REGNAME (decode_pregs[(x) & 7])
310 #define spfp(x) REGNAME (decode_spfp[(x) & 1])
311 #define dregs_hilo(x, i) REGNAME (decode_dregs_hilo[((i) << 3) | (x)])
312 #define accum_ext(x) REGNAME (decode_accum_ext[(x) & 1])
313 #define accum_word(x) REGNAME (decode_accum_word[(x) & 1])
314 #define accum(x) REGNAME (decode_accum[(x) & 1])
315
316 /* I(0..3). */
317 static const enum machine_registers decode_iregs[] =
318 {
319 REG_I0, REG_I1, REG_I2, REG_I3,
320 };
321
322 #define iregs(x) REGNAME (decode_iregs[(x) & 3])
323
324 /* M(0..3). */
325 static const enum machine_registers decode_mregs[] =
326 {
327 REG_M0, REG_M1, REG_M2, REG_M3,
328 };
329
330 #define mregs(x) REGNAME (decode_mregs[(x) & 3])
331 #define bregs(x) REGNAME (decode_bregs[(x) & 3])
332 #define lregs(x) REGNAME (decode_lregs[(x) & 3])
333
334 /* dregs pregs. */
335 static const enum machine_registers decode_dpregs[] =
336 {
337 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
338 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
339 };
340
341 #define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
342
343 /* [dregs pregs]. */
344 static const enum machine_registers decode_gregs[] =
345 {
346 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
347 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
348 };
349
350 #define gregs(x, i) REGNAME (decode_gregs[((i) << 3) | (x)])
351
352 /* [dregs pregs (iregs mregs) (bregs lregs)]. */
353 static const enum machine_registers decode_regs[] =
354 {
355 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
356 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
357 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
358 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
359 };
360
361 #define regs(x, i) REGNAME (decode_regs[((i) << 3) | (x)])
362
363 /* [dregs pregs (iregs mregs) (bregs lregs) Low Half]. */
364 static const enum machine_registers decode_regs_lo[] =
365 {
366 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
367 REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
368 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
369 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
370 };
371
372 #define regs_lo(x, i) REGNAME (decode_regs_lo[((i) << 3) | (x)])
373
374 /* [dregs pregs (iregs mregs) (bregs lregs) High Half]. */
375 static const enum machine_registers decode_regs_hi[] =
376 {
377 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
378 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
379 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
380 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
381 };
382
383 #define regs_hi(x, i) REGNAME (decode_regs_hi[((i) << 3) | (x)])
384
385 static const enum machine_registers decode_statbits[] =
386 {
387 REG_AZ, REG_AN, REG_AC0_COPY, REG_V_COPY,
388 REG_LASTREG, REG_LASTREG, REG_AQ, REG_LASTREG,
389 REG_RND_MOD, REG_LASTREG, REG_LASTREG, REG_LASTREG,
390 REG_AC0, REG_AC1, REG_LASTREG, REG_LASTREG,
391 REG_AV0, REG_AV0S, REG_AV1, REG_AV1S,
392 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
393 REG_V, REG_VS, REG_LASTREG, REG_LASTREG,
394 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
395 };
396
397 #define statbits(x) REGNAME (decode_statbits[(x) & 31])
398
399 /* LC0 LC1. */
400 static const enum machine_registers decode_counters[] =
401 {
402 REG_LC0, REG_LC1,
403 };
404
405 #define counters(x) REGNAME (decode_counters[(x) & 1])
406 #define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7])
407
408 /* [dregs pregs (iregs mregs) (bregs lregs)
409 dregs2_sysregs1 open sysregs2 sysregs3]. */
410 static const enum machine_registers decode_allregs[] =
411 {
412 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
413 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
414 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
415 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
416 REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_LASTREG, REG_LASTREG, REG_ASTAT, REG_RETS,
417 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
418 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
419 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT,
420 REG_LASTREG,
421 };
422
423 #define IS_DREG(g,r) ((g) == 0 && (r) < 8)
424 #define IS_PREG(g,r) ((g) == 1 && (r) < 8)
425 #define IS_AREG(g,r) ((g) == 4 && (r) >= 0 && (r) < 4)
426 #define IS_GENREG(g,r) ((((g) == 0 || (g) == 1) && (r) < 8) || IS_AREG (g, r))
427 #define IS_DAGREG(g,r) (((g) == 2 || (g) == 3) && (r) < 8)
428 #define IS_SYSREG(g,r) \
429 (((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7)
430 #define IS_RESERVEDREG(g,r) \
431 (((r) > 7) || ((g) == 4 && ((r) == 4 || (r) == 5)) || (g) == 5)
432
433 #define allreg(r,g) (!IS_RESERVEDREG (g, r))
434 #define mostreg(r,g) (!(IS_DREG (g, r) || IS_PREG (g, r) || IS_RESERVEDREG (g, r)))
435
436 #define allregs(x, i) REGNAME (decode_allregs[((i) << 3) | (x)])
437 #define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf)
438 #define uimm16s4d(x) fmtconst (c_uimm16s4d, x, 0, outf)
439 #define pcrel4(x) fmtconst (c_pcrel4, x, pc, outf)
440 #define pcrel8(x) fmtconst (c_pcrel8, x, pc, outf)
441 #define pcrel8s4(x) fmtconst (c_pcrel8s4, x, pc, outf)
442 #define pcrel10(x) fmtconst (c_pcrel10, x, pc, outf)
443 #define pcrel12(x) fmtconst (c_pcrel12, x, pc, outf)
444 #define negimm5s4(x) fmtconst (c_negimm5s4, x, 0, outf)
445 #define rimm16(x) fmtconst (c_rimm16, x, 0, outf)
446 #define huimm16(x) fmtconst (c_huimm16, x, 0, outf)
447 #define imm16(x) fmtconst (c_imm16, x, 0, outf)
448 #define imm16d(x) fmtconst (c_imm16d, x, 0, outf)
449 #define uimm2(x) fmtconst (c_uimm2, x, 0, outf)
450 #define uimm3(x) fmtconst (c_uimm3, x, 0, outf)
451 #define luimm16(x) fmtconst (c_luimm16, x, 0, outf)
452 #define uimm4(x) fmtconst (c_uimm4, x, 0, outf)
453 #define uimm5(x) fmtconst (c_uimm5, x, 0, outf)
454 #define imm16s2(x) fmtconst (c_imm16s2, x, 0, outf)
455 #define uimm8(x) fmtconst (c_uimm8, x, 0, outf)
456 #define imm16s4(x) fmtconst (c_imm16s4, x, 0, outf)
457 #define uimm4s2(x) fmtconst (c_uimm4s2, x, 0, outf)
458 #define uimm4s4(x) fmtconst (c_uimm4s4, x, 0, outf)
459 #define uimm4s4d(x) fmtconst (c_uimm4s4d, x, 0, outf)
460 #define lppcrel10(x) fmtconst (c_lppcrel10, x, pc, outf)
461 #define imm3(x) fmtconst (c_imm3, x, 0, outf)
462 #define imm4(x) fmtconst (c_imm4, x, 0, outf)
463 #define uimm8s4(x) fmtconst (c_uimm8s4, x, 0, outf)
464 #define imm5(x) fmtconst (c_imm5, x, 0, outf)
465 #define imm5d(x) fmtconst (c_imm5d, x, 0, outf)
466 #define imm6(x) fmtconst (c_imm6, x, 0, outf)
467 #define imm7(x) fmtconst (c_imm7, x, 0, outf)
468 #define imm7d(x) fmtconst (c_imm7d, x, 0, outf)
469 #define imm8(x) fmtconst (c_imm8, x, 0, outf)
470 #define pcrel24(x) fmtconst (c_pcrel24, x, pc, outf)
471 #define uimm16(x) fmtconst (c_uimm16, x, 0, outf)
472 #define uimm32(x) fmtconst (c_uimm32, x, 0, outf)
473 #define imm32(x) fmtconst (c_imm32, x, 0, outf)
474 #define huimm32(x) fmtconst (c_huimm32, x, 0, outf)
475 #define huimm32e(x) fmtconst (c_huimm32e, x, 0, outf)
476 #define imm7_val(x) fmtconst_val (c_imm7, x, 0)
477 #define imm16_val(x) fmtconst_val (c_uimm16, x, 0)
478 #define luimm16_val(x) fmtconst_val (c_luimm16, x, 0)
479
480 /* (arch.pm)arch_disassembler_functions. */
481 #ifndef OUTS
482 #define OUTS(p, txt) (p)->fprintf_func ((p)->stream, "%s", txt)
483 #endif
484
485 static void
486 amod0 (int s0, int x0, disassemble_info *outf)
487 {
488 if (s0 == 1 && x0 == 0)
489 OUTS (outf, " (S)");
490 else if (s0 == 0 && x0 == 1)
491 OUTS (outf, " (CO)");
492 else if (s0 == 1 && x0 == 1)
493 OUTS (outf, " (SCO)");
494 }
495
496 static void
497 amod1 (int s0, int x0, disassemble_info *outf)
498 {
499 if (s0 == 0 && x0 == 0)
500 OUTS (outf, " (NS)");
501 else if (s0 == 1 && x0 == 0)
502 OUTS (outf, " (S)");
503 }
504
505 static void
506 amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf)
507 {
508 if (s0 == 1 && x0 == 0 && aop0 == 0)
509 OUTS (outf, " (S)");
510 else if (s0 == 0 && x0 == 1 && aop0 == 0)
511 OUTS (outf, " (CO)");
512 else if (s0 == 1 && x0 == 1 && aop0 == 0)
513 OUTS (outf, " (SCO)");
514 else if (s0 == 0 && x0 == 0 && aop0 == 2)
515 OUTS (outf, " (ASR)");
516 else if (s0 == 1 && x0 == 0 && aop0 == 2)
517 OUTS (outf, " (S, ASR)");
518 else if (s0 == 0 && x0 == 1 && aop0 == 2)
519 OUTS (outf, " (CO, ASR)");
520 else if (s0 == 1 && x0 == 1 && aop0 == 2)
521 OUTS (outf, " (SCO, ASR)");
522 else if (s0 == 0 && x0 == 0 && aop0 == 3)
523 OUTS (outf, " (ASL)");
524 else if (s0 == 1 && x0 == 0 && aop0 == 3)
525 OUTS (outf, " (S, ASL)");
526 else if (s0 == 0 && x0 == 1 && aop0 == 3)
527 OUTS (outf, " (CO, ASL)");
528 else if (s0 == 1 && x0 == 1 && aop0 == 3)
529 OUTS (outf, " (SCO, ASL)");
530 }
531
532 static void
533 searchmod (int r0, disassemble_info *outf)
534 {
535 if (r0 == 0)
536 OUTS (outf, "GT");
537 else if (r0 == 1)
538 OUTS (outf, "GE");
539 else if (r0 == 2)
540 OUTS (outf, "LT");
541 else if (r0 == 3)
542 OUTS (outf, "LE");
543 }
544
545 static void
546 aligndir (int r0, disassemble_info *outf)
547 {
548 if (r0 == 1)
549 OUTS (outf, " (R)");
550 }
551
552 static int
553 decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info *outf)
554 {
555 const char *s0, *s1;
556
557 if (h0)
558 s0 = dregs_hi (src0);
559 else
560 s0 = dregs_lo (src0);
561
562 if (h1)
563 s1 = dregs_hi (src1);
564 else
565 s1 = dregs_lo (src1);
566
567 OUTS (outf, s0);
568 OUTS (outf, " * ");
569 OUTS (outf, s1);
570 return 0;
571 }
572
573 static int
574 decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info *outf)
575 {
576 const char *a;
577 const char *sop = "<unknown op>";
578
579 if (which)
580 a = "A1";
581 else
582 a = "A0";
583
584 if (op == 3)
585 {
586 OUTS (outf, a);
587 return 0;
588 }
589
590 switch (op)
591 {
592 case 0: sop = " = "; break;
593 case 1: sop = " += "; break;
594 case 2: sop = " -= "; break;
595 default: break;
596 }
597
598 OUTS (outf, a);
599 OUTS (outf, sop);
600 decode_multfunc (h0, h1, src0, src1, outf);
601
602 return 0;
603 }
604
605 static void
606 decode_optmode (int mod, int MM, disassemble_info *outf)
607 {
608 if (mod == 0 && MM == 0)
609 return;
610
611 OUTS (outf, " (");
612
613 if (MM && !mod)
614 {
615 OUTS (outf, "M)");
616 return;
617 }
618
619 if (MM)
620 OUTS (outf, "M, ");
621
622 if (mod == M_S2RND)
623 OUTS (outf, "S2RND");
624 else if (mod == M_T)
625 OUTS (outf, "T");
626 else if (mod == M_W32)
627 OUTS (outf, "W32");
628 else if (mod == M_FU)
629 OUTS (outf, "FU");
630 else if (mod == M_TFU)
631 OUTS (outf, "TFU");
632 else if (mod == M_IS)
633 OUTS (outf, "IS");
634 else if (mod == M_ISS2)
635 OUTS (outf, "ISS2");
636 else if (mod == M_IH)
637 OUTS (outf, "IH");
638 else if (mod == M_IU)
639 OUTS (outf, "IU");
640 else
641 abort ();
642
643 OUTS (outf, ")");
644 }
645
646 static struct saved_state
647 {
648 bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4];
649 bu32 ax[2], aw[2];
650 bu32 lt[2], lc[2], lb[2];
651 bu32 rets;
652 } saved_state;
653
654 #define DREG(x) (saved_state.dpregs[x])
655 #define GREG(x, i) DPREG ((x) | ((i) << 3))
656 #define DPREG(x) (saved_state.dpregs[x])
657 #define DREG(x) (saved_state.dpregs[x])
658 #define PREG(x) (saved_state.dpregs[(x) + 8])
659 #define SPREG PREG (6)
660 #define FPREG PREG (7)
661 #define IREG(x) (saved_state.iregs[x])
662 #define MREG(x) (saved_state.mregs[x])
663 #define BREG(x) (saved_state.bregs[x])
664 #define LREG(x) (saved_state.lregs[x])
665 #define AXREG(x) (saved_state.ax[x])
666 #define AWREG(x) (saved_state.aw[x])
667 #define LCREG(x) (saved_state.lc[x])
668 #define LTREG(x) (saved_state.lt[x])
669 #define LBREG(x) (saved_state.lb[x])
670 #define RETSREG (saved_state.rets)
671
672 static bu32 *
673 get_allreg (int grp, int reg)
674 {
675 int fullreg = (grp << 3) | reg;
676 /* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
677 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
678 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
679 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
680 REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS,
681 , , , , , , , ,
682 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
683 REG_CYCLES2,
684 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE,
685 REG_LASTREG */
686 switch (fullreg >> 2)
687 {
688 case 0: case 1: return &DREG (reg);
689 case 2: case 3: return &PREG (reg);
690 case 4: return &IREG (reg & 3);
691 case 5: return &MREG (reg & 3);
692 case 6: return &BREG (reg & 3);
693 case 7: return &LREG (reg & 3);
694 default:
695 switch (fullreg)
696 {
697 case 32: return &AXREG (0);
698 case 33: return &AWREG (0);
699 case 34: return &AXREG (1);
700 case 35: return &AWREG (1);
701 case 39: return &RETSREG;
702 case 48: return &LCREG (0);
703 case 49: return &LTREG (0);
704 case 50: return &LBREG (0);
705 case 51: return &LCREG (1);
706 case 52: return &LTREG (1);
707 case 53: return &LBREG (1);
708 }
709 }
710 abort ();
711 }
712
713 static int
714 decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
715 {
716 /* ProgCtrl
717 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
718 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
719 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
720 int poprnd = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
721 int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
722
723 if (prgfunc == 0 && poprnd == 0)
724 OUTS (outf, "NOP");
725 else if (parallel)
726 return 0;
727 else if (prgfunc == 1 && poprnd == 0)
728 OUTS (outf, "RTS");
729 else if (prgfunc == 1 && poprnd == 1)
730 OUTS (outf, "RTI");
731 else if (prgfunc == 1 && poprnd == 2)
732 OUTS (outf, "RTX");
733 else if (prgfunc == 1 && poprnd == 3)
734 OUTS (outf, "RTN");
735 else if (prgfunc == 1 && poprnd == 4)
736 OUTS (outf, "RTE");
737 else if (prgfunc == 2 && poprnd == 0)
738 OUTS (outf, "IDLE");
739 else if (prgfunc == 2 && poprnd == 3)
740 OUTS (outf, "CSYNC");
741 else if (prgfunc == 2 && poprnd == 4)
742 OUTS (outf, "SSYNC");
743 else if (prgfunc == 2 && poprnd == 5)
744 OUTS (outf, "EMUEXCPT");
745 else if (prgfunc == 3 && IS_DREG (0, poprnd))
746 {
747 OUTS (outf, "CLI ");
748 OUTS (outf, dregs (poprnd));
749 }
750 else if (prgfunc == 4 && IS_DREG (0, poprnd))
751 {
752 OUTS (outf, "STI ");
753 OUTS (outf, dregs (poprnd));
754 }
755 else if (prgfunc == 5 && IS_PREG (1, poprnd))
756 {
757 OUTS (outf, "JUMP (");
758 OUTS (outf, pregs (poprnd));
759 OUTS (outf, ")");
760 }
761 else if (prgfunc == 6 && IS_PREG (1, poprnd))
762 {
763 OUTS (outf, "CALL (");
764 OUTS (outf, pregs (poprnd));
765 OUTS (outf, ")");
766 }
767 else if (prgfunc == 7 && IS_PREG (1, poprnd))
768 {
769 OUTS (outf, "CALL (PC + ");
770 OUTS (outf, pregs (poprnd));
771 OUTS (outf, ")");
772 }
773 else if (prgfunc == 8 && IS_PREG (1, poprnd))
774 {
775 OUTS (outf, "JUMP (PC + ");
776 OUTS (outf, pregs (poprnd));
777 OUTS (outf, ")");
778 }
779 else if (prgfunc == 9)
780 {
781 OUTS (outf, "RAISE ");
782 OUTS (outf, uimm4 (poprnd));
783 }
784 else if (prgfunc == 10)
785 {
786 OUTS (outf, "EXCPT ");
787 OUTS (outf, uimm4 (poprnd));
788 }
789 else if (prgfunc == 11 && IS_PREG (1, poprnd) && poprnd <= 5)
790 {
791 OUTS (outf, "TESTSET (");
792 OUTS (outf, pregs (poprnd));
793 OUTS (outf, ")");
794 }
795 else
796 return 0;
797 return 2;
798 }
799
800 static int
801 decode_CaCTRL_0 (TIword iw0, disassemble_info *outf)
802 {
803 /* CaCTRL
804 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
805 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
806 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
807 int a = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask);
808 int op = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask);
809 int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask);
810
811 if (parallel)
812 return 0;
813
814 if (a == 0 && op == 0)
815 {
816 OUTS (outf, "PREFETCH[");
817 OUTS (outf, pregs (reg));
818 OUTS (outf, "]");
819 }
820 else if (a == 0 && op == 1)
821 {
822 OUTS (outf, "FLUSHINV[");
823 OUTS (outf, pregs (reg));
824 OUTS (outf, "]");
825 }
826 else if (a == 0 && op == 2)
827 {
828 OUTS (outf, "FLUSH[");
829 OUTS (outf, pregs (reg));
830 OUTS (outf, "]");
831 }
832 else if (a == 0 && op == 3)
833 {
834 OUTS (outf, "IFLUSH[");
835 OUTS (outf, pregs (reg));
836 OUTS (outf, "]");
837 }
838 else if (a == 1 && op == 0)
839 {
840 OUTS (outf, "PREFETCH[");
841 OUTS (outf, pregs (reg));
842 OUTS (outf, "++]");
843 }
844 else if (a == 1 && op == 1)
845 {
846 OUTS (outf, "FLUSHINV[");
847 OUTS (outf, pregs (reg));
848 OUTS (outf, "++]");
849 }
850 else if (a == 1 && op == 2)
851 {
852 OUTS (outf, "FLUSH[");
853 OUTS (outf, pregs (reg));
854 OUTS (outf, "++]");
855 }
856 else if (a == 1 && op == 3)
857 {
858 OUTS (outf, "IFLUSH[");
859 OUTS (outf, pregs (reg));
860 OUTS (outf, "++]");
861 }
862 else
863 return 0;
864 return 2;
865 }
866
867 static int
868 decode_PushPopReg_0 (TIword iw0, disassemble_info *outf)
869 {
870 /* PushPopReg
871 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
872 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
873 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
874 int W = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask);
875 int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask);
876 int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask);
877
878 if (parallel)
879 return 0;
880
881 if (W == 0 && mostreg (reg, grp))
882 {
883 OUTS (outf, allregs (reg, grp));
884 OUTS (outf, " = [SP++]");
885 }
886 else if (W == 1 && allreg (reg, grp) && !(grp == 1 && reg == 6))
887 {
888 OUTS (outf, "[--SP] = ");
889 OUTS (outf, allregs (reg, grp));
890 }
891 else
892 return 0;
893 return 2;
894 }
895
896 static int
897 decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf)
898 {
899 /* PushPopMultiple
900 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
901 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
902 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
903 int p = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask);
904 int d = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask);
905 int W = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask);
906 int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
907 int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
908
909 if (parallel)
910 return 0;
911
912 if (pr > 5)
913 return 0;
914
915 if (W == 1 && d == 1 && p == 1)
916 {
917 OUTS (outf, "[--SP] = (R7:");
918 OUTS (outf, imm5d (dr));
919 OUTS (outf, ", P5:");
920 OUTS (outf, imm5d (pr));
921 OUTS (outf, ")");
922 }
923 else if (W == 1 && d == 1 && p == 0 && pr == 0)
924 {
925 OUTS (outf, "[--SP] = (R7:");
926 OUTS (outf, imm5d (dr));
927 OUTS (outf, ")");
928 }
929 else if (W == 1 && d == 0 && p == 1 && dr == 0)
930 {
931 OUTS (outf, "[--SP] = (P5:");
932 OUTS (outf, imm5d (pr));
933 OUTS (outf, ")");
934 }
935 else if (W == 0 && d == 1 && p == 1)
936 {
937 OUTS (outf, "(R7:");
938 OUTS (outf, imm5d (dr));
939 OUTS (outf, ", P5:");
940 OUTS (outf, imm5d (pr));
941 OUTS (outf, ") = [SP++]");
942 }
943 else if (W == 0 && d == 1 && p == 0 && pr == 0)
944 {
945 OUTS (outf, "(R7:");
946 OUTS (outf, imm5d (dr));
947 OUTS (outf, ") = [SP++]");
948 }
949 else if (W == 0 && d == 0 && p == 1 && dr == 0)
950 {
951 OUTS (outf, "(P5:");
952 OUTS (outf, imm5d (pr));
953 OUTS (outf, ") = [SP++]");
954 }
955 else
956 return 0;
957 return 2;
958 }
959
960 static int
961 decode_ccMV_0 (TIword iw0, disassemble_info *outf)
962 {
963 /* ccMV
964 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
965 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
966 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
967 int s = ((iw0 >> CCmv_s_bits) & CCmv_s_mask);
968 int d = ((iw0 >> CCmv_d_bits) & CCmv_d_mask);
969 int T = ((iw0 >> CCmv_T_bits) & CCmv_T_mask);
970 int src = ((iw0 >> CCmv_src_bits) & CCmv_src_mask);
971 int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask);
972
973 if (parallel)
974 return 0;
975
976 if (T == 1)
977 {
978 OUTS (outf, "IF CC ");
979 OUTS (outf, gregs (dst, d));
980 OUTS (outf, " = ");
981 OUTS (outf, gregs (src, s));
982 }
983 else if (T == 0)
984 {
985 OUTS (outf, "IF !CC ");
986 OUTS (outf, gregs (dst, d));
987 OUTS (outf, " = ");
988 OUTS (outf, gregs (src, s));
989 }
990 else
991 return 0;
992 return 2;
993 }
994
995 static int
996 decode_CCflag_0 (TIword iw0, disassemble_info *outf)
997 {
998 /* CCflag
999 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1000 | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
1001 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1002 int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask);
1003 int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask);
1004 int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask);
1005 int G = ((iw0 >> CCflag_G_bits) & CCflag_G_mask);
1006 int opc = ((iw0 >> CCflag_opc_bits) & CCflag_opc_mask);
1007
1008 if (parallel)
1009 return 0;
1010
1011 if (opc == 0 && I == 0 && G == 0)
1012 {
1013 OUTS (outf, "CC = ");
1014 OUTS (outf, dregs (x));
1015 OUTS (outf, " == ");
1016 OUTS (outf, dregs (y));
1017 }
1018 else if (opc == 1 && I == 0 && G == 0)
1019 {
1020 OUTS (outf, "CC = ");
1021 OUTS (outf, dregs (x));
1022 OUTS (outf, " < ");
1023 OUTS (outf, dregs (y));
1024 }
1025 else if (opc == 2 && I == 0 && G == 0)
1026 {
1027 OUTS (outf, "CC = ");
1028 OUTS (outf, dregs (x));
1029 OUTS (outf, " <= ");
1030 OUTS (outf, dregs (y));
1031 }
1032 else if (opc == 3 && I == 0 && G == 0)
1033 {
1034 OUTS (outf, "CC = ");
1035 OUTS (outf, dregs (x));
1036 OUTS (outf, " < ");
1037 OUTS (outf, dregs (y));
1038 OUTS (outf, " (IU)");
1039 }
1040 else if (opc == 4 && I == 0 && G == 0)
1041 {
1042 OUTS (outf, "CC = ");
1043 OUTS (outf, dregs (x));
1044 OUTS (outf, " <= ");
1045 OUTS (outf, dregs (y));
1046 OUTS (outf, " (IU)");
1047 }
1048 else if (opc == 0 && I == 1 && G == 0)
1049 {
1050 OUTS (outf, "CC = ");
1051 OUTS (outf, dregs (x));
1052 OUTS (outf, " == ");
1053 OUTS (outf, imm3 (y));
1054 }
1055 else if (opc == 1 && I == 1 && G == 0)
1056 {
1057 OUTS (outf, "CC = ");
1058 OUTS (outf, dregs (x));
1059 OUTS (outf, " < ");
1060 OUTS (outf, imm3 (y));
1061 }
1062 else if (opc == 2 && I == 1 && G == 0)
1063 {
1064 OUTS (outf, "CC = ");
1065 OUTS (outf, dregs (x));
1066 OUTS (outf, " <= ");
1067 OUTS (outf, imm3 (y));
1068 }
1069 else if (opc == 3 && I == 1 && G == 0)
1070 {
1071 OUTS (outf, "CC = ");
1072 OUTS (outf, dregs (x));
1073 OUTS (outf, " < ");
1074 OUTS (outf, uimm3 (y));
1075 OUTS (outf, " (IU)");
1076 }
1077 else if (opc == 4 && I == 1 && G == 0)
1078 {
1079 OUTS (outf, "CC = ");
1080 OUTS (outf, dregs (x));
1081 OUTS (outf, " <= ");
1082 OUTS (outf, uimm3 (y));
1083 OUTS (outf, " (IU)");
1084 }
1085 else if (opc == 0 && I == 0 && G == 1)
1086 {
1087 OUTS (outf, "CC = ");
1088 OUTS (outf, pregs (x));
1089 OUTS (outf, " == ");
1090 OUTS (outf, pregs (y));
1091 }
1092 else if (opc == 1 && I == 0 && G == 1)
1093 {
1094 OUTS (outf, "CC = ");
1095 OUTS (outf, pregs (x));
1096 OUTS (outf, " < ");
1097 OUTS (outf, pregs (y));
1098 }
1099 else if (opc == 2 && I == 0 && G == 1)
1100 {
1101 OUTS (outf, "CC = ");
1102 OUTS (outf, pregs (x));
1103 OUTS (outf, " <= ");
1104 OUTS (outf, pregs (y));
1105 }
1106 else if (opc == 3 && I == 0 && G == 1)
1107 {
1108 OUTS (outf, "CC = ");
1109 OUTS (outf, pregs (x));
1110 OUTS (outf, " < ");
1111 OUTS (outf, pregs (y));
1112 OUTS (outf, " (IU)");
1113 }
1114 else if (opc == 4 && I == 0 && G == 1)
1115 {
1116 OUTS (outf, "CC = ");
1117 OUTS (outf, pregs (x));
1118 OUTS (outf, " <= ");
1119 OUTS (outf, pregs (y));
1120 OUTS (outf, " (IU)");
1121 }
1122 else if (opc == 0 && I == 1 && G == 1)
1123 {
1124 OUTS (outf, "CC = ");
1125 OUTS (outf, pregs (x));
1126 OUTS (outf, " == ");
1127 OUTS (outf, imm3 (y));
1128 }
1129 else if (opc == 1 && I == 1 && G == 1)
1130 {
1131 OUTS (outf, "CC = ");
1132 OUTS (outf, pregs (x));
1133 OUTS (outf, " < ");
1134 OUTS (outf, imm3 (y));
1135 }
1136 else if (opc == 2 && I == 1 && G == 1)
1137 {
1138 OUTS (outf, "CC = ");
1139 OUTS (outf, pregs (x));
1140 OUTS (outf, " <= ");
1141 OUTS (outf, imm3 (y));
1142 }
1143 else if (opc == 3 && I == 1 && G == 1)
1144 {
1145 OUTS (outf, "CC = ");
1146 OUTS (outf, pregs (x));
1147 OUTS (outf, " < ");
1148 OUTS (outf, uimm3 (y));
1149 OUTS (outf, " (IU)");
1150 }
1151 else if (opc == 4 && I == 1 && G == 1)
1152 {
1153 OUTS (outf, "CC = ");
1154 OUTS (outf, pregs (x));
1155 OUTS (outf, " <= ");
1156 OUTS (outf, uimm3 (y));
1157 OUTS (outf, " (IU)");
1158 }
1159 else if (opc == 5 && I == 0 && G == 0 && x == 0 && y == 0)
1160 OUTS (outf, "CC = A0 == A1");
1161
1162 else if (opc == 6 && I == 0 && G == 0 && x == 0 && y == 0)
1163 OUTS (outf, "CC = A0 < A1");
1164
1165 else if (opc == 7 && I == 0 && G == 0 && x == 0 && y == 0)
1166 OUTS (outf, "CC = A0 <= A1");
1167
1168 else
1169 return 0;
1170 return 2;
1171 }
1172
1173 static int
1174 decode_CC2dreg_0 (TIword iw0, disassemble_info *outf)
1175 {
1176 /* CC2dreg
1177 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1178 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
1179 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1180 int op = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask);
1181 int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask);
1182
1183 if (parallel)
1184 return 0;
1185
1186 if (op == 0)
1187 {
1188 OUTS (outf, dregs (reg));
1189 OUTS (outf, " = CC");
1190 }
1191 else if (op == 1)
1192 {
1193 OUTS (outf, "CC = ");
1194 OUTS (outf, dregs (reg));
1195 }
1196 else if (op == 3 && reg == 0)
1197 OUTS (outf, "CC = !CC");
1198 else
1199 return 0;
1200
1201 return 2;
1202 }
1203
1204 static int
1205 decode_CC2stat_0 (TIword iw0, disassemble_info *outf)
1206 {
1207 /* CC2stat
1208 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1209 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
1210 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1211 int D = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask);
1212 int op = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask);
1213 int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask);
1214
1215 const char *bitname = statbits (cbit);
1216
1217 if (parallel)
1218 return 0;
1219
1220 if (decode_statbits[cbit] == REG_LASTREG)
1221 {
1222 /* All ASTAT bits except CC may be operated on in hardware, but may
1223 not have a dedicated insn, so still decode "valid" insns. */
1224 static char bitnames[64];
1225 if (cbit != 5)
1226 sprintf (bitnames, "ASTAT[%i /* unused bit */]", cbit);
1227 else
1228 return 0;
1229
1230 bitname = bitnames;
1231 }
1232
1233 if (op == 0 && D == 0)
1234 {
1235 OUTS (outf, "CC = ");
1236 OUTS (outf, bitname);
1237 }
1238 else if (op == 1 && D == 0)
1239 {
1240 OUTS (outf, "CC |= ");
1241 OUTS (outf, bitname);
1242 }
1243 else if (op == 2 && D == 0)
1244 {
1245 OUTS (outf, "CC &= ");
1246 OUTS (outf, bitname);
1247 }
1248 else if (op == 3 && D == 0)
1249 {
1250 OUTS (outf, "CC ^= ");
1251 OUTS (outf, bitname);
1252 }
1253 else if (op == 0 && D == 1)
1254 {
1255 OUTS (outf, bitname);
1256 OUTS (outf, " = CC");
1257 }
1258 else if (op == 1 && D == 1)
1259 {
1260 OUTS (outf, bitname);
1261 OUTS (outf, " |= CC");
1262 }
1263 else if (op == 2 && D == 1)
1264 {
1265 OUTS (outf, bitname);
1266 OUTS (outf, " &= CC");
1267 }
1268 else if (op == 3 && D == 1)
1269 {
1270 OUTS (outf, bitname);
1271 OUTS (outf, " ^= CC");
1272 }
1273 else
1274 return 0;
1275
1276 return 2;
1277 }
1278
1279 static int
1280 decode_BRCC_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1281 {
1282 /* BRCC
1283 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1284 | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
1285 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1286 int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask);
1287 int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask);
1288 int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask);
1289
1290 if (parallel)
1291 return 0;
1292
1293 if (T == 1 && B == 1)
1294 {
1295 OUTS (outf, "IF CC JUMP 0x");
1296 OUTS (outf, pcrel10 (offset));
1297 OUTS (outf, " (BP)");
1298 }
1299 else if (T == 0 && B == 1)
1300 {
1301 OUTS (outf, "IF !CC JUMP 0x");
1302 OUTS (outf, pcrel10 (offset));
1303 OUTS (outf, " (BP)");
1304 }
1305 else if (T == 1)
1306 {
1307 OUTS (outf, "IF CC JUMP 0x");
1308 OUTS (outf, pcrel10 (offset));
1309 }
1310 else if (T == 0)
1311 {
1312 OUTS (outf, "IF !CC JUMP 0x");
1313 OUTS (outf, pcrel10 (offset));
1314 }
1315 else
1316 return 0;
1317
1318 return 2;
1319 }
1320
1321 static int
1322 decode_UJUMP_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1323 {
1324 /* UJUMP
1325 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1326 | 0 | 0 | 1 | 0 |.offset........................................|
1327 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1328 int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask);
1329
1330 if (parallel)
1331 return 0;
1332
1333 OUTS (outf, "JUMP.S 0x");
1334 OUTS (outf, pcrel12 (offset));
1335 return 2;
1336 }
1337
1338 static int
1339 decode_REGMV_0 (TIword iw0, disassemble_info *outf)
1340 {
1341 /* REGMV
1342 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1343 | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
1344 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1345 int gs = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask);
1346 int gd = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask);
1347 int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
1348 int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
1349
1350 /* Reserved slots cannot be a src/dst. */
1351 if (IS_RESERVEDREG (gs, src) || IS_RESERVEDREG (gd, dst))
1352 goto invalid_move;
1353
1354 /* Standard register moves */
1355 if ((gs < 2) || /* Dregs/Pregs as source */
1356 (gd < 2) || /* Dregs/Pregs as dest */
1357 (gs == 4 && src < 4) || /* Accumulators as source */
1358 (gd == 4 && dst < 4 && (gs < 4)) || /* Accumulators as dest */
1359 (gs == 7 && src == 7 && !(gd == 4 && dst < 4)) || /* EMUDAT as src */
1360 (gd == 7 && dst == 7)) /* EMUDAT as dest */
1361 goto valid_move;
1362
1363 /* dareg = dareg (IMBL) */
1364 if (gs < 4 && gd < 4)
1365 goto valid_move;
1366
1367 /* USP can be src to sysregs, but not dagregs. */
1368 if ((gs == 7 && src == 0) && (gd >= 4))
1369 goto valid_move;
1370
1371 /* USP can move between genregs (only check Accumulators). */
1372 if (((gs == 7 && src == 0) && (gd == 4 && dst < 4)) ||
1373 ((gd == 7 && dst == 0) && (gs == 4 && src < 4)))
1374 goto valid_move;
1375
1376 /* Still here ? Invalid reg pair. */
1377 invalid_move:
1378 return 0;
1379
1380 valid_move:
1381 OUTS (outf, allregs (dst, gd));
1382 OUTS (outf, " = ");
1383 OUTS (outf, allregs (src, gs));
1384 return 2;
1385 }
1386
1387 static int
1388 decode_ALU2op_0 (TIword iw0, disassemble_info *outf)
1389 {
1390 /* ALU2op
1391 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1392 | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
1393 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1394 int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask);
1395 int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask);
1396 int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask);
1397
1398 if (opc == 0)
1399 {
1400 OUTS (outf, dregs (dst));
1401 OUTS (outf, " >>>= ");
1402 OUTS (outf, dregs (src));
1403 }
1404 else if (opc == 1)
1405 {
1406 OUTS (outf, dregs (dst));
1407 OUTS (outf, " >>= ");
1408 OUTS (outf, dregs (src));
1409 }
1410 else if (opc == 2)
1411 {
1412 OUTS (outf, dregs (dst));
1413 OUTS (outf, " <<= ");
1414 OUTS (outf, dregs (src));
1415 }
1416 else if (opc == 3)
1417 {
1418 OUTS (outf, dregs (dst));
1419 OUTS (outf, " *= ");
1420 OUTS (outf, dregs (src));
1421 }
1422 else if (opc == 4)
1423 {
1424 OUTS (outf, dregs (dst));
1425 OUTS (outf, " = (");
1426 OUTS (outf, dregs (dst));
1427 OUTS (outf, " + ");
1428 OUTS (outf, dregs (src));
1429 OUTS (outf, ") << 0x1");
1430 }
1431 else if (opc == 5)
1432 {
1433 OUTS (outf, dregs (dst));
1434 OUTS (outf, " = (");
1435 OUTS (outf, dregs (dst));
1436 OUTS (outf, " + ");
1437 OUTS (outf, dregs (src));
1438 OUTS (outf, ") << 0x2");
1439 }
1440 else if (opc == 8)
1441 {
1442 OUTS (outf, "DIVQ (");
1443 OUTS (outf, dregs (dst));
1444 OUTS (outf, ", ");
1445 OUTS (outf, dregs (src));
1446 OUTS (outf, ")");
1447 }
1448 else if (opc == 9)
1449 {
1450 OUTS (outf, "DIVS (");
1451 OUTS (outf, dregs (dst));
1452 OUTS (outf, ", ");
1453 OUTS (outf, dregs (src));
1454 OUTS (outf, ")");
1455 }
1456 else if (opc == 10)
1457 {
1458 OUTS (outf, dregs (dst));
1459 OUTS (outf, " = ");
1460 OUTS (outf, dregs_lo (src));
1461 OUTS (outf, " (X)");
1462 }
1463 else if (opc == 11)
1464 {
1465 OUTS (outf, dregs (dst));
1466 OUTS (outf, " = ");
1467 OUTS (outf, dregs_lo (src));
1468 OUTS (outf, " (Z)");
1469 }
1470 else if (opc == 12)
1471 {
1472 OUTS (outf, dregs (dst));
1473 OUTS (outf, " = ");
1474 OUTS (outf, dregs_byte (src));
1475 OUTS (outf, " (X)");
1476 }
1477 else if (opc == 13)
1478 {
1479 OUTS (outf, dregs (dst));
1480 OUTS (outf, " = ");
1481 OUTS (outf, dregs_byte (src));
1482 OUTS (outf, " (Z)");
1483 }
1484 else if (opc == 14)
1485 {
1486 OUTS (outf, dregs (dst));
1487 OUTS (outf, " = -");
1488 OUTS (outf, dregs (src));
1489 }
1490 else if (opc == 15)
1491 {
1492 OUTS (outf, dregs (dst));
1493 OUTS (outf, " =~ ");
1494 OUTS (outf, dregs (src));
1495 }
1496 else
1497 return 0;
1498
1499 return 2;
1500 }
1501
1502 static int
1503 decode_PTR2op_0 (TIword iw0, disassemble_info *outf)
1504 {
1505 /* PTR2op
1506 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1507 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
1508 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1509 int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask);
1510 int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask);
1511 int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask);
1512
1513 if (opc == 0)
1514 {
1515 OUTS (outf, pregs (dst));
1516 OUTS (outf, " -= ");
1517 OUTS (outf, pregs (src));
1518 }
1519 else if (opc == 1)
1520 {
1521 OUTS (outf, pregs (dst));
1522 OUTS (outf, " = ");
1523 OUTS (outf, pregs (src));
1524 OUTS (outf, " << 0x2");
1525 }
1526 else if (opc == 3)
1527 {
1528 OUTS (outf, pregs (dst));
1529 OUTS (outf, " = ");
1530 OUTS (outf, pregs (src));
1531 OUTS (outf, " >> 0x2");
1532 }
1533 else if (opc == 4)
1534 {
1535 OUTS (outf, pregs (dst));
1536 OUTS (outf, " = ");
1537 OUTS (outf, pregs (src));
1538 OUTS (outf, " >> 0x1");
1539 }
1540 else if (opc == 5)
1541 {
1542 OUTS (outf, pregs (dst));
1543 OUTS (outf, " += ");
1544 OUTS (outf, pregs (src));
1545 OUTS (outf, " (BREV)");
1546 }
1547 else if (opc == 6)
1548 {
1549 OUTS (outf, pregs (dst));
1550 OUTS (outf, " = (");
1551 OUTS (outf, pregs (dst));
1552 OUTS (outf, " + ");
1553 OUTS (outf, pregs (src));
1554 OUTS (outf, ") << 0x1");
1555 }
1556 else if (opc == 7)
1557 {
1558 OUTS (outf, pregs (dst));
1559 OUTS (outf, " = (");
1560 OUTS (outf, pregs (dst));
1561 OUTS (outf, " + ");
1562 OUTS (outf, pregs (src));
1563 OUTS (outf, ") << 0x2");
1564 }
1565 else
1566 return 0;
1567
1568 return 2;
1569 }
1570
1571 static int
1572 decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
1573 {
1574 /* LOGI2op
1575 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1576 | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
1577 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1578 int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask);
1579 int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask);
1580 int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask);
1581
1582 if (parallel)
1583 return 0;
1584
1585 if (opc == 0)
1586 {
1587 OUTS (outf, "CC = !BITTST (");
1588 OUTS (outf, dregs (dst));
1589 OUTS (outf, ", ");
1590 OUTS (outf, uimm5 (src));
1591 OUTS (outf, ");\t\t/* bit");
1592 OUTS (outf, imm7d (src));
1593 OUTS (outf, " */");
1594 comment = 1;
1595 }
1596 else if (opc == 1)
1597 {
1598 OUTS (outf, "CC = BITTST (");
1599 OUTS (outf, dregs (dst));
1600 OUTS (outf, ", ");
1601 OUTS (outf, uimm5 (src));
1602 OUTS (outf, ");\t\t/* bit");
1603 OUTS (outf, imm7d (src));
1604 OUTS (outf, " */");
1605 comment = 1;
1606 }
1607 else if (opc == 2)
1608 {
1609 OUTS (outf, "BITSET (");
1610 OUTS (outf, dregs (dst));
1611 OUTS (outf, ", ");
1612 OUTS (outf, uimm5 (src));
1613 OUTS (outf, ");\t\t/* bit");
1614 OUTS (outf, imm7d (src));
1615 OUTS (outf, " */");
1616 comment = 1;
1617 }
1618 else if (opc == 3)
1619 {
1620 OUTS (outf, "BITTGL (");
1621 OUTS (outf, dregs (dst));
1622 OUTS (outf, ", ");
1623 OUTS (outf, uimm5 (src));
1624 OUTS (outf, ");\t\t/* bit");
1625 OUTS (outf, imm7d (src));
1626 OUTS (outf, " */");
1627 comment = 1;
1628 }
1629 else if (opc == 4)
1630 {
1631 OUTS (outf, "BITCLR (");
1632 OUTS (outf, dregs (dst));
1633 OUTS (outf, ", ");
1634 OUTS (outf, uimm5 (src));
1635 OUTS (outf, ");\t\t/* bit");
1636 OUTS (outf, imm7d (src));
1637 OUTS (outf, " */");
1638 comment = 1;
1639 }
1640 else if (opc == 5)
1641 {
1642 OUTS (outf, dregs (dst));
1643 OUTS (outf, " >>>= ");
1644 OUTS (outf, uimm5 (src));
1645 }
1646 else if (opc == 6)
1647 {
1648 OUTS (outf, dregs (dst));
1649 OUTS (outf, " >>= ");
1650 OUTS (outf, uimm5 (src));
1651 }
1652 else if (opc == 7)
1653 {
1654 OUTS (outf, dregs (dst));
1655 OUTS (outf, " <<= ");
1656 OUTS (outf, uimm5 (src));
1657 }
1658 else
1659 return 0;
1660
1661 return 2;
1662 }
1663
1664 static int
1665 decode_COMP3op_0 (TIword iw0, disassemble_info *outf)
1666 {
1667 /* COMP3op
1668 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1669 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1670 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1671 int opc = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask);
1672 int dst = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask);
1673 int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask);
1674 int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask);
1675
1676 if (opc == 5 && src1 == src0)
1677 {
1678 OUTS (outf, pregs (dst));
1679 OUTS (outf, " = ");
1680 OUTS (outf, pregs (src0));
1681 OUTS (outf, " << 0x1");
1682 }
1683 else if (opc == 1)
1684 {
1685 OUTS (outf, dregs (dst));
1686 OUTS (outf, " = ");
1687 OUTS (outf, dregs (src0));
1688 OUTS (outf, " - ");
1689 OUTS (outf, dregs (src1));
1690 }
1691 else if (opc == 2)
1692 {
1693 OUTS (outf, dregs (dst));
1694 OUTS (outf, " = ");
1695 OUTS (outf, dregs (src0));
1696 OUTS (outf, " & ");
1697 OUTS (outf, dregs (src1));
1698 }
1699 else if (opc == 3)
1700 {
1701 OUTS (outf, dregs (dst));
1702 OUTS (outf, " = ");
1703 OUTS (outf, dregs (src0));
1704 OUTS (outf, " | ");
1705 OUTS (outf, dregs (src1));
1706 }
1707 else if (opc == 4)
1708 {
1709 OUTS (outf, dregs (dst));
1710 OUTS (outf, " = ");
1711 OUTS (outf, dregs (src0));
1712 OUTS (outf, " ^ ");
1713 OUTS (outf, dregs (src1));
1714 }
1715 else if (opc == 5)
1716 {
1717 OUTS (outf, pregs (dst));
1718 OUTS (outf, " = ");
1719 OUTS (outf, pregs (src0));
1720 OUTS (outf, " + ");
1721 OUTS (outf, pregs (src1));
1722 }
1723 else if (opc == 6)
1724 {
1725 OUTS (outf, pregs (dst));
1726 OUTS (outf, " = ");
1727 OUTS (outf, pregs (src0));
1728 OUTS (outf, " + (");
1729 OUTS (outf, pregs (src1));
1730 OUTS (outf, " << 0x1)");
1731 }
1732 else if (opc == 7)
1733 {
1734 OUTS (outf, pregs (dst));
1735 OUTS (outf, " = ");
1736 OUTS (outf, pregs (src0));
1737 OUTS (outf, " + (");
1738 OUTS (outf, pregs (src1));
1739 OUTS (outf, " << 0x2)");
1740 }
1741 else if (opc == 0)
1742 {
1743 OUTS (outf, dregs (dst));
1744 OUTS (outf, " = ");
1745 OUTS (outf, dregs (src0));
1746 OUTS (outf, " + ");
1747 OUTS (outf, dregs (src1));
1748 }
1749 else
1750 return 0;
1751
1752 return 2;
1753 }
1754
1755 static int
1756 decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf)
1757 {
1758 /* COMPI2opD
1759 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1760 | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......|
1761 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1762 int op = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask);
1763 int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask);
1764 int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask);
1765
1766 bu32 *pval = get_allreg (0, dst);
1767
1768 if (parallel)
1769 return 0;
1770
1771 /* Since we don't have 32-bit immediate loads, we allow the disassembler
1772 to combine them, so it prints out the right values.
1773 Here we keep track of the registers. */
1774 if (op == 0)
1775 {
1776 *pval = imm7_val (src);
1777 if (src & 0x40)
1778 *pval |= 0xFFFFFF80;
1779 else
1780 *pval &= 0x7F;
1781 }
1782
1783 if (op == 0)
1784 {
1785 OUTS (outf, dregs (dst));
1786 OUTS (outf, " = ");
1787 OUTS (outf, imm7 (src));
1788 OUTS (outf, " (X);\t\t/*\t\t");
1789 OUTS (outf, dregs (dst));
1790 OUTS (outf, "=");
1791 OUTS (outf, uimm32 (*pval));
1792 OUTS (outf, "(");
1793 OUTS (outf, imm32 (*pval));
1794 OUTS (outf, ") */");
1795 comment = 1;
1796 }
1797 else if (op == 1)
1798 {
1799 OUTS (outf, dregs (dst));
1800 OUTS (outf, " += ");
1801 OUTS (outf, imm7 (src));
1802 OUTS (outf, ";\t\t/* (");
1803 OUTS (outf, imm7d (src));
1804 OUTS (outf, ") */");
1805 comment = 1;
1806 }
1807 else
1808 return 0;
1809
1810 return 2;
1811 }
1812
1813 static int
1814 decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf)
1815 {
1816 /* COMPI2opP
1817 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1818 | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
1819 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1820 int op = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask);
1821 int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask);
1822 int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask);
1823
1824 bu32 *pval = get_allreg (1, dst);
1825
1826 if (parallel)
1827 return 0;
1828
1829 if (op == 0)
1830 {
1831 *pval = imm7_val (src);
1832 if (src & 0x40)
1833 *pval |= 0xFFFFFF80;
1834 else
1835 *pval &= 0x7F;
1836 }
1837
1838 if (op == 0)
1839 {
1840 OUTS (outf, pregs (dst));
1841 OUTS (outf, " = ");
1842 OUTS (outf, imm7 (src));
1843 OUTS (outf, " (X);\t\t/*\t\t");
1844 OUTS (outf, pregs (dst));
1845 OUTS (outf, "=");
1846 OUTS (outf, uimm32 (*pval));
1847 OUTS (outf, "(");
1848 OUTS (outf, imm32 (*pval));
1849 OUTS (outf, ") */");
1850 comment = 1;
1851 }
1852 else if (op == 1)
1853 {
1854 OUTS (outf, pregs (dst));
1855 OUTS (outf, " += ");
1856 OUTS (outf, imm7 (src));
1857 OUTS (outf, ";\t\t/* (");
1858 OUTS (outf, imm7d (src));
1859 OUTS (outf, ") */");
1860 comment = 1;
1861 }
1862 else
1863 return 0;
1864
1865 return 2;
1866 }
1867
1868 static int
1869 decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf)
1870 {
1871 /* LDSTpmod
1872 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1873 | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
1874 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1875 int W = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask);
1876 int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask);
1877 int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask);
1878 int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask);
1879 int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask);
1880
1881 if (aop == 1 && W == 0 && idx == ptr)
1882 {
1883 OUTS (outf, dregs_lo (reg));
1884 OUTS (outf, " = W[");
1885 OUTS (outf, pregs (ptr));
1886 OUTS (outf, "]");
1887 }
1888 else if (aop == 2 && W == 0 && idx == ptr)
1889 {
1890 OUTS (outf, dregs_hi (reg));
1891 OUTS (outf, " = W[");
1892 OUTS (outf, pregs (ptr));
1893 OUTS (outf, "]");
1894 }
1895 else if (aop == 1 && W == 1 && idx == ptr)
1896 {
1897 OUTS (outf, "W[");
1898 OUTS (outf, pregs (ptr));
1899 OUTS (outf, "] = ");
1900 OUTS (outf, dregs_lo (reg));
1901 }
1902 else if (aop == 2 && W == 1 && idx == ptr)
1903 {
1904 OUTS (outf, "W[");
1905 OUTS (outf, pregs (ptr));
1906 OUTS (outf, "] = ");
1907 OUTS (outf, dregs_hi (reg));
1908 }
1909 else if (aop == 0 && W == 0)
1910 {
1911 OUTS (outf, dregs (reg));
1912 OUTS (outf, " = [");
1913 OUTS (outf, pregs (ptr));
1914 OUTS (outf, " ++ ");
1915 OUTS (outf, pregs (idx));
1916 OUTS (outf, "]");
1917 }
1918 else if (aop == 1 && W == 0)
1919 {
1920 OUTS (outf, dregs_lo (reg));
1921 OUTS (outf, " = W[");
1922 OUTS (outf, pregs (ptr));
1923 OUTS (outf, " ++ ");
1924 OUTS (outf, pregs (idx));
1925 OUTS (outf, "]");
1926 }
1927 else if (aop == 2 && W == 0)
1928 {
1929 OUTS (outf, dregs_hi (reg));
1930 OUTS (outf, " = W[");
1931 OUTS (outf, pregs (ptr));
1932 OUTS (outf, " ++ ");
1933 OUTS (outf, pregs (idx));
1934 OUTS (outf, "]");
1935 }
1936 else if (aop == 3 && W == 0)
1937 {
1938 OUTS (outf, dregs (reg));
1939 OUTS (outf, " = W[");
1940 OUTS (outf, pregs (ptr));
1941 OUTS (outf, " ++ ");
1942 OUTS (outf, pregs (idx));
1943 OUTS (outf, "] (Z)");
1944 }
1945 else if (aop == 3 && W == 1)
1946 {
1947 OUTS (outf, dregs (reg));
1948 OUTS (outf, " = W[");
1949 OUTS (outf, pregs (ptr));
1950 OUTS (outf, " ++ ");
1951 OUTS (outf, pregs (idx));
1952 OUTS (outf, "] (X)");
1953 }
1954 else if (aop == 0 && W == 1)
1955 {
1956 OUTS (outf, "[");
1957 OUTS (outf, pregs (ptr));
1958 OUTS (outf, " ++ ");
1959 OUTS (outf, pregs (idx));
1960 OUTS (outf, "] = ");
1961 OUTS (outf, dregs (reg));
1962 }
1963 else if (aop == 1 && W == 1)
1964 {
1965 OUTS (outf, "W[");
1966 OUTS (outf, pregs (ptr));
1967 OUTS (outf, " ++ ");
1968 OUTS (outf, pregs (idx));
1969 OUTS (outf, "] = ");
1970 OUTS (outf, dregs_lo (reg));
1971 }
1972 else if (aop == 2 && W == 1)
1973 {
1974 OUTS (outf, "W[");
1975 OUTS (outf, pregs (ptr));
1976 OUTS (outf, " ++ ");
1977 OUTS (outf, pregs (idx));
1978 OUTS (outf, "] = ");
1979 OUTS (outf, dregs_hi (reg));
1980 }
1981 else
1982 return 0;
1983
1984 return 2;
1985 }
1986
1987 static int
1988 decode_dagMODim_0 (TIword iw0, disassemble_info *outf)
1989 {
1990 /* dagMODim
1991 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1992 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
1993 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1994 int i = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
1995 int m = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask);
1996 int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask);
1997 int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
1998
1999 if (op == 0 && br == 1)
2000 {
2001 OUTS (outf, iregs (i));
2002 OUTS (outf, " += ");
2003 OUTS (outf, mregs (m));
2004 OUTS (outf, " (BREV)");
2005 }
2006 else if (op == 0)
2007 {
2008 OUTS (outf, iregs (i));
2009 OUTS (outf, " += ");
2010 OUTS (outf, mregs (m));
2011 }
2012 else if (op == 1 && br == 0)
2013 {
2014 OUTS (outf, iregs (i));
2015 OUTS (outf, " -= ");
2016 OUTS (outf, mregs (m));
2017 }
2018 else
2019 return 0;
2020
2021 return 2;
2022 }
2023
2024 static int
2025 decode_dagMODik_0 (TIword iw0, disassemble_info *outf)
2026 {
2027 /* dagMODik
2028 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2029 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
2030 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2031 int i = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask);
2032 int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask);
2033
2034 if (op == 0)
2035 {
2036 OUTS (outf, iregs (i));
2037 OUTS (outf, " += 0x2");
2038 }
2039 else if (op == 1)
2040 {
2041 OUTS (outf, iregs (i));
2042 OUTS (outf, " -= 0x2");
2043 }
2044 else if (op == 2)
2045 {
2046 OUTS (outf, iregs (i));
2047 OUTS (outf, " += 0x4");
2048 }
2049 else if (op == 3)
2050 {
2051 OUTS (outf, iregs (i));
2052 OUTS (outf, " -= 0x4");
2053 }
2054 else
2055 return 0;
2056
2057 if (! parallel)
2058 {
2059 OUTS (outf, ";\t\t/* ( ");
2060 if (op == 0 || op == 1)
2061 OUTS (outf, "2");
2062 else if (op == 2 || op == 3)
2063 OUTS (outf, "4");
2064 OUTS (outf, ") */");
2065 comment = 1;
2066 }
2067
2068 return 2;
2069 }
2070
2071 static int
2072 decode_dspLDST_0 (TIword iw0, disassemble_info *outf)
2073 {
2074 /* dspLDST
2075 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2076 | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
2077 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2078 int i = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask);
2079 int m = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask);
2080 int W = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask);
2081 int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask);
2082 int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask);
2083
2084 if (aop == 0 && W == 0 && m == 0)
2085 {
2086 OUTS (outf, dregs (reg));
2087 OUTS (outf, " = [");
2088 OUTS (outf, iregs (i));
2089 OUTS (outf, "++]");
2090 }
2091 else if (aop == 0 && W == 0 && m == 1)
2092 {
2093 OUTS (outf, dregs_lo (reg));
2094 OUTS (outf, " = W[");
2095 OUTS (outf, iregs (i));
2096 OUTS (outf, "++]");
2097 }
2098 else if (aop == 0 && W == 0 && m == 2)
2099 {
2100 OUTS (outf, dregs_hi (reg));
2101 OUTS (outf, " = W[");
2102 OUTS (outf, iregs (i));
2103 OUTS (outf, "++]");
2104 }
2105 else if (aop == 1 && W == 0 && m == 0)
2106 {
2107 OUTS (outf, dregs (reg));
2108 OUTS (outf, " = [");
2109 OUTS (outf, iregs (i));
2110 OUTS (outf, "--]");
2111 }
2112 else if (aop == 1 && W == 0 && m == 1)
2113 {
2114 OUTS (outf, dregs_lo (reg));
2115 OUTS (outf, " = W[");
2116 OUTS (outf, iregs (i));
2117 OUTS (outf, "--]");
2118 }
2119 else if (aop == 1 && W == 0 && m == 2)
2120 {
2121 OUTS (outf, dregs_hi (reg));
2122 OUTS (outf, " = W[");
2123 OUTS (outf, iregs (i));
2124 OUTS (outf, "--]");
2125 }
2126 else if (aop == 2 && W == 0 && m == 0)
2127 {
2128 OUTS (outf, dregs (reg));
2129 OUTS (outf, " = [");
2130 OUTS (outf, iregs (i));
2131 OUTS (outf, "]");
2132 }
2133 else if (aop == 2 && W == 0 && m == 1)
2134 {
2135 OUTS (outf, dregs_lo (reg));
2136 OUTS (outf, " = W[");
2137 OUTS (outf, iregs (i));
2138 OUTS (outf, "]");
2139 }
2140 else if (aop == 2 && W == 0 && m == 2)
2141 {
2142 OUTS (outf, dregs_hi (reg));
2143 OUTS (outf, " = W[");
2144 OUTS (outf, iregs (i));
2145 OUTS (outf, "]");
2146 }
2147 else if (aop == 0 && W == 1 && m == 0)
2148 {
2149 OUTS (outf, "[");
2150 OUTS (outf, iregs (i));
2151 OUTS (outf, "++] = ");
2152 OUTS (outf, dregs (reg));
2153 }
2154 else if (aop == 0 && W == 1 && m == 1)
2155 {
2156 OUTS (outf, "W[");
2157 OUTS (outf, iregs (i));
2158 OUTS (outf, "++] = ");
2159 OUTS (outf, dregs_lo (reg));
2160 }
2161 else if (aop == 0 && W == 1 && m == 2)
2162 {
2163 OUTS (outf, "W[");
2164 OUTS (outf, iregs (i));
2165 OUTS (outf, "++] = ");
2166 OUTS (outf, dregs_hi (reg));
2167 }
2168 else if (aop == 1 && W == 1 && m == 0)
2169 {
2170 OUTS (outf, "[");
2171 OUTS (outf, iregs (i));
2172 OUTS (outf, "--] = ");
2173 OUTS (outf, dregs (reg));
2174 }
2175 else if (aop == 1 && W == 1 && m == 1)
2176 {
2177 OUTS (outf, "W[");
2178 OUTS (outf, iregs (i));
2179 OUTS (outf, "--] = ");
2180 OUTS (outf, dregs_lo (reg));
2181 }
2182 else if (aop == 1 && W == 1 && m == 2)
2183 {
2184 OUTS (outf, "W[");
2185 OUTS (outf, iregs (i));
2186 OUTS (outf, "--] = ");
2187 OUTS (outf, dregs_hi (reg));
2188 }
2189 else if (aop == 2 && W == 1 && m == 0)
2190 {
2191 OUTS (outf, "[");
2192 OUTS (outf, iregs (i));
2193 OUTS (outf, "] = ");
2194 OUTS (outf, dregs (reg));
2195 }
2196 else if (aop == 2 && W == 1 && m == 1)
2197 {
2198 OUTS (outf, "W[");
2199 OUTS (outf, iregs (i));
2200 OUTS (outf, "] = ");
2201 OUTS (outf, dregs_lo (reg));
2202 }
2203 else if (aop == 2 && W == 1 && m == 2)
2204 {
2205 OUTS (outf, "W[");
2206 OUTS (outf, iregs (i));
2207 OUTS (outf, "] = ");
2208 OUTS (outf, dregs_hi (reg));
2209 }
2210 else if (aop == 3 && W == 0)
2211 {
2212 OUTS (outf, dregs (reg));
2213 OUTS (outf, " = [");
2214 OUTS (outf, iregs (i));
2215 OUTS (outf, " ++ ");
2216 OUTS (outf, mregs (m));
2217 OUTS (outf, "]");
2218 }
2219 else if (aop == 3 && W == 1)
2220 {
2221 OUTS (outf, "[");
2222 OUTS (outf, iregs (i));
2223 OUTS (outf, " ++ ");
2224 OUTS (outf, mregs (m));
2225 OUTS (outf, "] = ");
2226 OUTS (outf, dregs (reg));
2227 }
2228 else
2229 return 0;
2230
2231 return 2;
2232 }
2233
2234 static int
2235 decode_LDST_0 (TIword iw0, disassemble_info *outf)
2236 {
2237 /* LDST
2238 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2239 | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
2240 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2241 int Z = ((iw0 >> LDST_Z_bits) & LDST_Z_mask);
2242 int W = ((iw0 >> LDST_W_bits) & LDST_W_mask);
2243 int sz = ((iw0 >> LDST_sz_bits) & LDST_sz_mask);
2244 int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask);
2245 int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask);
2246 int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask);
2247
2248 if (aop == 0 && sz == 0 && Z == 0 && W == 0)
2249 {
2250 OUTS (outf, dregs (reg));
2251 OUTS (outf, " = [");
2252 OUTS (outf, pregs (ptr));
2253 OUTS (outf, "++]");
2254 }
2255 else if (aop == 0 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
2256 {
2257 OUTS (outf, pregs (reg));
2258 OUTS (outf, " = [");
2259 OUTS (outf, pregs (ptr));
2260 OUTS (outf, "++]");
2261 }
2262 else if (aop == 0 && sz == 1 && Z == 0 && W == 0)
2263 {
2264 OUTS (outf, dregs (reg));
2265 OUTS (outf, " = W[");
2266 OUTS (outf, pregs (ptr));
2267 OUTS (outf, "++] (Z)");
2268 }
2269 else if (aop == 0 && sz == 1 && Z == 1 && W == 0)
2270 {
2271 OUTS (outf, dregs (reg));
2272 OUTS (outf, " = W[");
2273 OUTS (outf, pregs (ptr));
2274 OUTS (outf, "++] (X)");
2275 }
2276 else if (aop == 0 && sz == 2 && Z == 0 && W == 0)
2277 {
2278 OUTS (outf, dregs (reg));
2279 OUTS (outf, " = B[");
2280 OUTS (outf, pregs (ptr));
2281 OUTS (outf, "++] (Z)");
2282 }
2283 else if (aop == 0 && sz == 2 && Z == 1 && W == 0)
2284 {
2285 OUTS (outf, dregs (reg));
2286 OUTS (outf, " = B[");
2287 OUTS (outf, pregs (ptr));
2288 OUTS (outf, "++] (X)");
2289 }
2290 else if (aop == 1 && sz == 0 && Z == 0 && W == 0)
2291 {
2292 OUTS (outf, dregs (reg));
2293 OUTS (outf, " = [");
2294 OUTS (outf, pregs (ptr));
2295 OUTS (outf, "--]");
2296 }
2297 else if (aop == 1 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
2298 {
2299 OUTS (outf, pregs (reg));
2300 OUTS (outf, " = [");
2301 OUTS (outf, pregs (ptr));
2302 OUTS (outf, "--]");
2303 }
2304 else if (aop == 1 && sz == 1 && Z == 0 && W == 0)
2305 {
2306 OUTS (outf, dregs (reg));
2307 OUTS (outf, " = W[");
2308 OUTS (outf, pregs (ptr));
2309 OUTS (outf, "--] (Z)");
2310 }
2311 else if (aop == 1 && sz == 1 && Z == 1 && W == 0)
2312 {
2313 OUTS (outf, dregs (reg));
2314 OUTS (outf, " = W[");
2315 OUTS (outf, pregs (ptr));
2316 OUTS (outf, "--] (X)");
2317 }
2318 else if (aop == 1 && sz == 2 && Z == 0 && W == 0)
2319 {
2320 OUTS (outf, dregs (reg));
2321 OUTS (outf, " = B[");
2322 OUTS (outf, pregs (ptr));
2323 OUTS (outf, "--] (Z)");
2324 }
2325 else if (aop == 1 && sz == 2 && Z == 1 && W == 0)
2326 {
2327 OUTS (outf, dregs (reg));
2328 OUTS (outf, " = B[");
2329 OUTS (outf, pregs (ptr));
2330 OUTS (outf, "--] (X)");
2331 }
2332 else if (aop == 2 && sz == 0 && Z == 0 && W == 0)
2333 {
2334 OUTS (outf, dregs (reg));
2335 OUTS (outf, " = [");
2336 OUTS (outf, pregs (ptr));
2337 OUTS (outf, "]");
2338 }
2339 else if (aop == 2 && sz == 0 && Z == 1 && W == 0)
2340 {
2341 OUTS (outf, pregs (reg));
2342 OUTS (outf, " = [");
2343 OUTS (outf, pregs (ptr));
2344 OUTS (outf, "]");
2345 }
2346 else if (aop == 2 && sz == 1 && Z == 0 && W == 0)
2347 {
2348 OUTS (outf, dregs (reg));
2349 OUTS (outf, " = W[");
2350 OUTS (outf, pregs (ptr));
2351 OUTS (outf, "] (Z)");
2352 }
2353 else if (aop == 2 && sz == 1 && Z == 1 && W == 0)
2354 {
2355 OUTS (outf, dregs (reg));
2356 OUTS (outf, " = W[");
2357 OUTS (outf, pregs (ptr));
2358 OUTS (outf, "] (X)");
2359 }
2360 else if (aop == 2 && sz == 2 && Z == 0 && W == 0)
2361 {
2362 OUTS (outf, dregs (reg));
2363 OUTS (outf, " = B[");
2364 OUTS (outf, pregs (ptr));
2365 OUTS (outf, "] (Z)");
2366 }
2367 else if (aop == 2 && sz == 2 && Z == 1 && W == 0)
2368 {
2369 OUTS (outf, dregs (reg));
2370 OUTS (outf, " = B[");
2371 OUTS (outf, pregs (ptr));
2372 OUTS (outf, "] (X)");
2373 }
2374 else if (aop == 0 && sz == 0 && Z == 0 && W == 1)
2375 {
2376 OUTS (outf, "[");
2377 OUTS (outf, pregs (ptr));
2378 OUTS (outf, "++] = ");
2379 OUTS (outf, dregs (reg));
2380 }
2381 else if (aop == 0 && sz == 0 && Z == 1 && W == 1)
2382 {
2383 OUTS (outf, "[");
2384 OUTS (outf, pregs (ptr));
2385 OUTS (outf, "++] = ");
2386 OUTS (outf, pregs (reg));
2387 }
2388 else if (aop == 0 && sz == 1 && Z == 0 && W == 1)
2389 {
2390 OUTS (outf, "W[");
2391 OUTS (outf, pregs (ptr));
2392 OUTS (outf, "++] = ");
2393 OUTS (outf, dregs (reg));
2394 }
2395 else if (aop == 0 && sz == 2 && Z == 0 && W == 1)
2396 {
2397 OUTS (outf, "B[");
2398 OUTS (outf, pregs (ptr));
2399 OUTS (outf, "++] = ");
2400 OUTS (outf, dregs (reg));
2401 }
2402 else if (aop == 1 && sz == 0 && Z == 0 && W == 1)
2403 {
2404 OUTS (outf, "[");
2405 OUTS (outf, pregs (ptr));
2406 OUTS (outf, "--] = ");
2407 OUTS (outf, dregs (reg));
2408 }
2409 else if (aop == 1 && sz == 0 && Z == 1 && W == 1)
2410 {
2411 OUTS (outf, "[");
2412 OUTS (outf, pregs (ptr));
2413 OUTS (outf, "--] = ");
2414 OUTS (outf, pregs (reg));
2415 }
2416 else if (aop == 1 && sz == 1 && Z == 0 && W == 1)
2417 {
2418 OUTS (outf, "W[");
2419 OUTS (outf, pregs (ptr));
2420 OUTS (outf, "--] = ");
2421 OUTS (outf, dregs (reg));
2422 }
2423 else if (aop == 1 && sz == 2 && Z == 0 && W == 1)
2424 {
2425 OUTS (outf, "B[");
2426 OUTS (outf, pregs (ptr));
2427 OUTS (outf, "--] = ");
2428 OUTS (outf, dregs (reg));
2429 }
2430 else if (aop == 2 && sz == 0 && Z == 0 && W == 1)
2431 {
2432 OUTS (outf, "[");
2433 OUTS (outf, pregs (ptr));
2434 OUTS (outf, "] = ");
2435 OUTS (outf, dregs (reg));
2436 }
2437 else if (aop == 2 && sz == 0 && Z == 1 && W == 1)
2438 {
2439 OUTS (outf, "[");
2440 OUTS (outf, pregs (ptr));
2441 OUTS (outf, "] = ");
2442 OUTS (outf, pregs (reg));
2443 }
2444 else if (aop == 2 && sz == 1 && Z == 0 && W == 1)
2445 {
2446 OUTS (outf, "W[");
2447 OUTS (outf, pregs (ptr));
2448 OUTS (outf, "] = ");
2449 OUTS (outf, dregs (reg));
2450 }
2451 else if (aop == 2 && sz == 2 && Z == 0 && W == 1)
2452 {
2453 OUTS (outf, "B[");
2454 OUTS (outf, pregs (ptr));
2455 OUTS (outf, "] = ");
2456 OUTS (outf, dregs (reg));
2457 }
2458 else
2459 return 0;
2460
2461 return 2;
2462 }
2463
2464 static int
2465 decode_LDSTiiFP_0 (TIword iw0, disassemble_info *outf)
2466 {
2467 /* LDSTiiFP
2468 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2469 | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
2470 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2471 int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask);
2472 int offset = ((iw0 >> LDSTiiFP_offset_bits) & LDSTiiFP_offset_mask);
2473 int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask);
2474
2475 if (W == 0)
2476 {
2477 OUTS (outf, dpregs (reg));
2478 OUTS (outf, " = [FP ");
2479 OUTS (outf, negimm5s4 (offset));
2480 OUTS (outf, "]");
2481 }
2482 else if (W == 1)
2483 {
2484 OUTS (outf, "[FP ");
2485 OUTS (outf, negimm5s4 (offset));
2486 OUTS (outf, "] = ");
2487 OUTS (outf, dpregs (reg));
2488 }
2489 else
2490 return 0;
2491
2492 return 2;
2493 }
2494
2495 static int
2496 decode_LDSTii_0 (TIword iw0, disassemble_info *outf)
2497 {
2498 /* LDSTii
2499 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2500 | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
2501 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2502 int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask);
2503 int ptr = ((iw0 >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
2504 int offset = ((iw0 >> LDSTii_offset_bit) & LDSTii_offset_mask);
2505 int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask);
2506 int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask);
2507
2508 if (W == 0 && op == 0)
2509 {
2510 OUTS (outf, dregs (reg));
2511 OUTS (outf, " = [");
2512 OUTS (outf, pregs (ptr));
2513 OUTS (outf, " + ");
2514 OUTS (outf, uimm4s4 (offset));
2515 OUTS (outf, "]");
2516 }
2517 else if (W == 0 && op == 1)
2518 {
2519 OUTS (outf, dregs (reg));
2520 OUTS (outf, " = W[");
2521 OUTS (outf, pregs (ptr));
2522 OUTS (outf, " + ");
2523 OUTS (outf, uimm4s2 (offset));
2524 OUTS (outf, "] (Z)");
2525 }
2526 else if (W == 0 && op == 2)
2527 {
2528 OUTS (outf, dregs (reg));
2529 OUTS (outf, " = W[");
2530 OUTS (outf, pregs (ptr));
2531 OUTS (outf, " + ");
2532 OUTS (outf, uimm4s2 (offset));
2533 OUTS (outf, "] (X)");
2534 }
2535 else if (W == 0 && op == 3)
2536 {
2537 OUTS (outf, pregs (reg));
2538 OUTS (outf, " = [");
2539 OUTS (outf, pregs (ptr));
2540 OUTS (outf, " + ");
2541 OUTS (outf, uimm4s4 (offset));
2542 OUTS (outf, "]");
2543 }
2544 else if (W == 1 && op == 0)
2545 {
2546 OUTS (outf, "[");
2547 OUTS (outf, pregs (ptr));
2548 OUTS (outf, " + ");
2549 OUTS (outf, uimm4s4 (offset));
2550 OUTS (outf, "] = ");
2551 OUTS (outf, dregs (reg));
2552 }
2553 else if (W == 1 && op == 1)
2554 {
2555 OUTS (outf, "W[");
2556 OUTS (outf, pregs (ptr));
2557 OUTS (outf, " + ");
2558 OUTS (outf, uimm4s2 (offset));
2559 OUTS (outf, "] = ");
2560 OUTS (outf, dregs (reg));
2561 }
2562 else if (W == 1 && op == 3)
2563 {
2564 OUTS (outf, "[");
2565 OUTS (outf, pregs (ptr));
2566 OUTS (outf, " + ");
2567 OUTS (outf, uimm4s4 (offset));
2568 OUTS (outf, "] = ");
2569 OUTS (outf, pregs (reg));
2570 }
2571 else
2572 return 0;
2573
2574 return 2;
2575 }
2576
2577 static int
2578 decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2579 {
2580 /* LoopSetup
2581 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2582 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
2583 |.reg...........| - | - |.eoffset...............................|
2584 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2585 int c = ((iw0 >> (LoopSetup_c_bits - 16)) & LoopSetup_c_mask);
2586 int reg = ((iw1 >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
2587 int rop = ((iw0 >> (LoopSetup_rop_bits - 16)) & LoopSetup_rop_mask);
2588 int soffset = ((iw0 >> (LoopSetup_soffset_bits - 16)) & LoopSetup_soffset_mask);
2589 int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask);
2590
2591 if (parallel)
2592 return 0;
2593
2594 if (reg > 7)
2595 return 0;
2596
2597 if (rop == 0)
2598 {
2599 OUTS (outf, "LSETUP");
2600 OUTS (outf, "(0x");
2601 OUTS (outf, pcrel4 (soffset));
2602 OUTS (outf, ", 0x");
2603 OUTS (outf, lppcrel10 (eoffset));
2604 OUTS (outf, ") ");
2605 OUTS (outf, counters (c));
2606 }
2607 else if (rop == 1)
2608 {
2609 OUTS (outf, "LSETUP");
2610 OUTS (outf, "(0x");
2611 OUTS (outf, pcrel4 (soffset));
2612 OUTS (outf, ", 0x");
2613 OUTS (outf, lppcrel10 (eoffset));
2614 OUTS (outf, ") ");
2615 OUTS (outf, counters (c));
2616 OUTS (outf, " = ");
2617 OUTS (outf, pregs (reg));
2618 }
2619 else if (rop == 3)
2620 {
2621 OUTS (outf, "LSETUP");
2622 OUTS (outf, "(0x");
2623 OUTS (outf, pcrel4 (soffset));
2624 OUTS (outf, ", 0x");
2625 OUTS (outf, lppcrel10 (eoffset));
2626 OUTS (outf, ") ");
2627 OUTS (outf, counters (c));
2628 OUTS (outf, " = ");
2629 OUTS (outf, pregs (reg));
2630 OUTS (outf, " >> 0x1");
2631 }
2632 else
2633 return 0;
2634
2635 return 4;
2636 }
2637
2638 static int
2639 decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2640 {
2641 /* LDIMMhalf
2642 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2643 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
2644 |.hword.........................................................|
2645 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2646 int H = ((iw0 >> (LDIMMhalf_H_bits - 16)) & LDIMMhalf_H_mask);
2647 int Z = ((iw0 >> (LDIMMhalf_Z_bits - 16)) & LDIMMhalf_Z_mask);
2648 int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask);
2649 int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask);
2650 int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask);
2651 int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask);
2652
2653 bu32 *pval = get_allreg (grp, reg);
2654
2655 if (parallel)
2656 return 0;
2657
2658 /* Since we don't have 32-bit immediate loads, we allow the disassembler
2659 to combine them, so it prints out the right values.
2660 Here we keep track of the registers. */
2661 if (H == 0 && S == 1 && Z == 0)
2662 {
2663 /* regs = imm16 (x) */
2664 *pval = imm16_val (hword);
2665 if (hword & 0x8000)
2666 *pval |= 0xFFFF0000;
2667 else
2668 *pval &= 0xFFFF;
2669 }
2670 else if (H == 0 && S == 0 && Z == 1)
2671 {
2672 /* regs = luimm16 (Z) */
2673 *pval = luimm16_val (hword);
2674 *pval &= 0xFFFF;
2675 }
2676 else if (H == 0 && S == 0 && Z == 0)
2677 {
2678 /* regs_lo = luimm16 */
2679 *pval &= 0xFFFF0000;
2680 *pval |= luimm16_val (hword);
2681 }
2682 else if (H == 1 && S == 0 && Z == 0)
2683 {
2684 /* regs_hi = huimm16 */
2685 *pval &= 0xFFFF;
2686 *pval |= luimm16_val (hword) << 16;
2687 }
2688
2689 /* Here we do the disassembly */
2690 if (grp == 0 && H == 0 && S == 0 && Z == 0)
2691 {
2692 OUTS (outf, dregs_lo (reg));
2693 OUTS (outf, " = ");
2694 OUTS (outf, uimm16 (hword));
2695 }
2696 else if (grp == 0 && H == 1 && S == 0 && Z == 0)
2697 {
2698 OUTS (outf, dregs_hi (reg));
2699 OUTS (outf, " = ");
2700 OUTS (outf, uimm16 (hword));
2701 }
2702 else if (grp == 0 && H == 0 && S == 1 && Z == 0)
2703 {
2704 OUTS (outf, dregs (reg));
2705 OUTS (outf, " = ");
2706 OUTS (outf, imm16 (hword));
2707 OUTS (outf, " (X)");
2708 }
2709 else if (H == 0 && S == 1 && Z == 0)
2710 {
2711 OUTS (outf, regs (reg, grp));
2712 OUTS (outf, " = ");
2713 OUTS (outf, imm16 (hword));
2714 OUTS (outf, " (X)");
2715 }
2716 else if (H == 0 && S == 0 && Z == 1)
2717 {
2718 OUTS (outf, regs (reg, grp));
2719 OUTS (outf, " = ");
2720 OUTS (outf, uimm16 (hword));
2721 OUTS (outf, " (Z)");
2722 }
2723 else if (H == 0 && S == 0 && Z == 0)
2724 {
2725 OUTS (outf, regs_lo (reg, grp));
2726 OUTS (outf, " = ");
2727 OUTS (outf, uimm16 (hword));
2728 }
2729 else if (H == 1 && S == 0 && Z == 0)
2730 {
2731 OUTS (outf, regs_hi (reg, grp));
2732 OUTS (outf, " = ");
2733 OUTS (outf, uimm16 (hword));
2734 }
2735 else
2736 return 0;
2737
2738 /* And we print out the 32-bit value if it is a pointer. */
2739 if (S == 0 && Z == 0)
2740 {
2741 OUTS (outf, ";\t\t/* (");
2742 OUTS (outf, imm16d (hword));
2743 OUTS (outf, ")\t");
2744
2745 /* If it is an MMR, don't print the symbol. */
2746 if (*pval < 0xFFC00000 && grp == 1)
2747 {
2748 OUTS (outf, regs (reg, grp));
2749 OUTS (outf, "=0x");
2750 OUTS (outf, huimm32e (*pval));
2751 }
2752 else
2753 {
2754 OUTS (outf, regs (reg, grp));
2755 OUTS (outf, "=0x");
2756 OUTS (outf, huimm32e (*pval));
2757 OUTS (outf, "(");
2758 OUTS (outf, imm32 (*pval));
2759 OUTS (outf, ")");
2760 }
2761
2762 OUTS (outf, " */");
2763 comment = 1;
2764 }
2765 if (S == 1 || Z == 1)
2766 {
2767 OUTS (outf, ";\t\t/*\t\t");
2768 OUTS (outf, regs (reg, grp));
2769 OUTS (outf, "=0x");
2770 OUTS (outf, huimm32e (*pval));
2771 OUTS (outf, "(");
2772 OUTS (outf, imm32 (*pval));
2773 OUTS (outf, ") */");
2774 comment = 1;
2775 }
2776 return 4;
2777 }
2778
2779 static int
2780 decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2781 {
2782 /* CALLa
2783 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2784 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
2785 |.lsw...........................................................|
2786 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2787 int S = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask);
2788 int lsw = ((iw1 >> 0) & 0xffff);
2789 int msw = ((iw0 >> 0) & 0xff);
2790
2791 if (parallel)
2792 return 0;
2793
2794 if (S == 1)
2795 OUTS (outf, "CALL 0x");
2796 else if (S == 0)
2797 OUTS (outf, "JUMP.L 0x");
2798 else
2799 return 0;
2800
2801 OUTS (outf, pcrel24 (((msw) << 16) | (lsw)));
2802 return 4;
2803 }
2804
2805 static int
2806 decode_LDSTidxI_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2807 {
2808 /* LDSTidxI
2809 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2810 | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
2811 |.offset........................................................|
2812 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2813 int Z = ((iw0 >> (LDSTidxI_Z_bits - 16)) & LDSTidxI_Z_mask);
2814 int W = ((iw0 >> (LDSTidxI_W_bits - 16)) & LDSTidxI_W_mask);
2815 int sz = ((iw0 >> (LDSTidxI_sz_bits - 16)) & LDSTidxI_sz_mask);
2816 int reg = ((iw0 >> (LDSTidxI_reg_bits - 16)) & LDSTidxI_reg_mask);
2817 int ptr = ((iw0 >> (LDSTidxI_ptr_bits - 16)) & LDSTidxI_ptr_mask);
2818 int offset = ((iw1 >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
2819
2820 if (W == 0 && sz == 0 && Z == 0)
2821 {
2822 OUTS (outf, dregs (reg));
2823 OUTS (outf, " = [");
2824 OUTS (outf, pregs (ptr));
2825 OUTS (outf, " + ");
2826 OUTS (outf, imm16s4 (offset));
2827 OUTS (outf, "]");
2828 }
2829 else if (W == 0 && sz == 0 && Z == 1)
2830 {
2831 OUTS (outf, pregs (reg));
2832 OUTS (outf, " = [");
2833 OUTS (outf, pregs (ptr));
2834 OUTS (outf, " + ");
2835 OUTS (outf, imm16s4 (offset));
2836 OUTS (outf, "]");
2837 }
2838 else if (W == 0 && sz == 1 && Z == 0)
2839 {
2840 OUTS (outf, dregs (reg));
2841 OUTS (outf, " = W[");
2842 OUTS (outf, pregs (ptr));
2843 OUTS (outf, " + ");
2844 OUTS (outf, imm16s2 (offset));
2845 OUTS (outf, "] (Z)");
2846 }
2847 else if (W == 0 && sz == 1 && Z == 1)
2848 {
2849 OUTS (outf, dregs (reg));
2850 OUTS (outf, " = W[");
2851 OUTS (outf, pregs (ptr));
2852 OUTS (outf, " + ");
2853 OUTS (outf, imm16s2 (offset));
2854 OUTS (outf, "] (X)");
2855 }
2856 else if (W == 0 && sz == 2 && Z == 0)
2857 {
2858 OUTS (outf, dregs (reg));
2859 OUTS (outf, " = B[");
2860 OUTS (outf, pregs (ptr));
2861 OUTS (outf, " + ");
2862 OUTS (outf, imm16 (offset));
2863 OUTS (outf, "] (Z)");
2864 }
2865 else if (W == 0 && sz == 2 && Z == 1)
2866 {
2867 OUTS (outf, dregs (reg));
2868 OUTS (outf, " = B[");
2869 OUTS (outf, pregs (ptr));
2870 OUTS (outf, " + ");
2871 OUTS (outf, imm16 (offset));
2872 OUTS (outf, "] (X)");
2873 }
2874 else if (W == 1 && sz == 0 && Z == 0)
2875 {
2876 OUTS (outf, "[");
2877 OUTS (outf, pregs (ptr));
2878 OUTS (outf, " + ");
2879 OUTS (outf, imm16s4 (offset));
2880 OUTS (outf, "] = ");
2881 OUTS (outf, dregs (reg));
2882 }
2883 else if (W == 1 && sz == 0 && Z == 1)
2884 {
2885 OUTS (outf, "[");
2886 OUTS (outf, pregs (ptr));
2887 OUTS (outf, " + ");
2888 OUTS (outf, imm16s4 (offset));
2889 OUTS (outf, "] = ");
2890 OUTS (outf, pregs (reg));
2891 }
2892 else if (W == 1 && sz == 1 && Z == 0)
2893 {
2894 OUTS (outf, "W[");
2895 OUTS (outf, pregs (ptr));
2896 OUTS (outf, " + ");
2897 OUTS (outf, imm16s2 (offset));
2898 OUTS (outf, "] = ");
2899 OUTS (outf, dregs (reg));
2900 }
2901 else if (W == 1 && sz == 2 && Z == 0)
2902 {
2903 OUTS (outf, "B[");
2904 OUTS (outf, pregs (ptr));
2905 OUTS (outf, " + ");
2906 OUTS (outf, imm16 (offset));
2907 OUTS (outf, "] = ");
2908 OUTS (outf, dregs (reg));
2909 }
2910 else
2911 return 0;
2912
2913 return 4;
2914 }
2915
2916 static int
2917 decode_linkage_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2918 {
2919 /* linkage
2920 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2921 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
2922 |.framesize.....................................................|
2923 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2924 int R = ((iw0 >> (Linkage_R_bits - 16)) & Linkage_R_mask);
2925 int framesize = ((iw1 >> Linkage_framesize_bits) & Linkage_framesize_mask);
2926
2927 if (parallel)
2928 return 0;
2929
2930 if (R == 0)
2931 {
2932 OUTS (outf, "LINK ");
2933 OUTS (outf, uimm16s4 (framesize));
2934 OUTS (outf, ";\t\t/* (");
2935 OUTS (outf, uimm16s4d (framesize));
2936 OUTS (outf, ") */");
2937 comment = 1;
2938 }
2939 else if (R == 1)
2940 OUTS (outf, "UNLINK");
2941 else
2942 return 0;
2943
2944 return 4;
2945 }
2946
2947 static int
2948 decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2949 {
2950 /* dsp32mac
2951 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2952 | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
2953 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2954 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2955 int op1 = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask);
2956 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2957 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2958 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
2959 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
2960 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
2961 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
2962 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
2963 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2964 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
2965 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
2966 int op0 = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask);
2967 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
2968 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
2969
2970 if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3)
2971 return 0;
2972
2973 if (op1 == 3 && MM)
2974 return 0;
2975
2976 if ((w1 || w0) && mmod == M_W32)
2977 return 0;
2978
2979 if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0)
2980 return 0;
2981
2982 if (w1 == 1 || op1 != 3)
2983 {
2984 if (w1)
2985 OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
2986
2987 if (op1 == 3)
2988 OUTS (outf, " = A1");
2989 else
2990 {
2991 if (w1)
2992 OUTS (outf, " = (");
2993 decode_macfunc (1, op1, h01, h11, src0, src1, outf);
2994 if (w1)
2995 OUTS (outf, ")");
2996 }
2997
2998 if (w0 == 1 || op0 != 3)
2999 {
3000 if (MM)
3001 OUTS (outf, " (M)");
3002 OUTS (outf, ", ");
3003 }
3004 }
3005
3006 if (w0 == 1 || op0 != 3)
3007 {
3008 /* Clear MM option since it only matters for MAC1, and if we made
3009 it this far, we've already shown it or we want to ignore it. */
3010 MM = 0;
3011
3012 if (w0)
3013 OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
3014
3015 if (op0 == 3)
3016 OUTS (outf, " = A0");
3017 else
3018 {
3019 if (w0)
3020 OUTS (outf, " = (");
3021 decode_macfunc (0, op0, h00, h10, src0, src1, outf);
3022 if (w0)
3023 OUTS (outf, ")");
3024 }
3025 }
3026
3027 decode_optmode (mmod, MM, outf);
3028
3029 return 4;
3030 }
3031
3032 static int
3033 decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3034 {
3035 /* dsp32mult
3036 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3037 | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
3038 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
3039 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3040 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
3041 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
3042 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
3043 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
3044 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
3045 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
3046 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
3047 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
3048 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
3049 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
3050 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
3051 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
3052
3053 if (w1 == 0 && w0 == 0)
3054 return 0;
3055
3056 if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0)
3057 return 0;
3058
3059 if (w1)
3060 {
3061 OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
3062 OUTS (outf, " = ");
3063 decode_multfunc (h01, h11, src0, src1, outf);
3064
3065 if (w0)
3066 {
3067 if (MM)
3068 OUTS (outf, " (M)");
3069 MM = 0;
3070 OUTS (outf, ", ");
3071 }
3072 }
3073
3074 if (w0)
3075 {
3076 OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
3077 OUTS (outf, " = ");
3078 decode_multfunc (h00, h10, src0, src1, outf);
3079 }
3080
3081 decode_optmode (mmod, MM, outf);
3082 return 4;
3083 }
3084
3085 static int
3086 decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3087 {
3088 /* dsp32alu
3089 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3090 | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
3091 |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
3092 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3093 int s = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask);
3094 int x = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask);
3095 int aop = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask);
3096 int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask);
3097 int src1 = ((iw1 >> DSP32Alu_src1_bits) & DSP32Alu_src1_mask);
3098 int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask);
3099 int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask);
3100 int HL = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask);
3101 int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask);
3102
3103 if (aop == 0 && aopcde == 9 && HL == 0 && s == 0)
3104 {
3105 OUTS (outf, "A0.L = ");
3106 OUTS (outf, dregs_lo (src0));
3107 }
3108 else if (aop == 2 && aopcde == 9 && HL == 1 && s == 0)
3109 {
3110 OUTS (outf, "A1.H = ");
3111 OUTS (outf, dregs_hi (src0));
3112 }
3113 else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0)
3114 {
3115 OUTS (outf, "A1.L = ");
3116 OUTS (outf, dregs_lo (src0));
3117 }
3118 else if (aop == 0 && aopcde == 9 && HL == 1 && s == 0)
3119 {
3120 OUTS (outf, "A0.H = ");
3121 OUTS (outf, dregs_hi (src0));
3122 }
3123 else if (x == 1 && HL == 1 && aop == 3 && aopcde == 5)
3124 {
3125 OUTS (outf, dregs_hi (dst0));
3126 OUTS (outf, " = ");
3127 OUTS (outf, dregs (src0));
3128 OUTS (outf, " - ");
3129 OUTS (outf, dregs (src1));
3130 OUTS (outf, " (RND20)");
3131 }
3132 else if (x == 1 && HL == 1 && aop == 2 && aopcde == 5)
3133 {
3134 OUTS (outf, dregs_hi (dst0));
3135 OUTS (outf, " = ");
3136 OUTS (outf, dregs (src0));
3137 OUTS (outf, " + ");
3138 OUTS (outf, dregs (src1));
3139 OUTS (outf, " (RND20)");
3140 }
3141 else if (x == 0 && HL == 0 && aop == 1 && aopcde == 5)
3142 {
3143 OUTS (outf, dregs_lo (dst0));
3144 OUTS (outf, " = ");
3145 OUTS (outf, dregs (src0));
3146 OUTS (outf, " - ");
3147 OUTS (outf, dregs (src1));
3148 OUTS (outf, " (RND12)");
3149 }
3150 else if (x == 0 && HL == 0 && aop == 0 && aopcde == 5)
3151 {
3152 OUTS (outf, dregs_lo (dst0));
3153 OUTS (outf, " = ");
3154 OUTS (outf, dregs (src0));
3155 OUTS (outf, " + ");
3156 OUTS (outf, dregs (src1));
3157 OUTS (outf, " (RND12)");
3158 }
3159 else if (x == 1 && HL == 0 && aop == 3 && aopcde == 5)
3160 {
3161 OUTS (outf, dregs_lo (dst0));
3162 OUTS (outf, " = ");
3163 OUTS (outf, dregs (src0));
3164 OUTS (outf, " - ");
3165 OUTS (outf, dregs (src1));
3166 OUTS (outf, " (RND20)");
3167 }
3168 else if (x == 0 && HL == 1 && aop == 0 && aopcde == 5)
3169 {
3170 OUTS (outf, dregs_hi (dst0));
3171 OUTS (outf, " = ");
3172 OUTS (outf, dregs (src0));
3173 OUTS (outf, " + ");
3174 OUTS (outf, dregs (src1));
3175 OUTS (outf, " (RND12)");
3176 }
3177 else if (x == 1 && HL == 0 && aop == 2 && aopcde == 5)
3178 {
3179 OUTS (outf, dregs_lo (dst0));
3180 OUTS (outf, " = ");
3181 OUTS (outf, dregs (src0));
3182 OUTS (outf, " + ");
3183 OUTS (outf, dregs (src1));
3184 OUTS (outf, " (RND20)");
3185 }
3186 else if (x == 0 && HL == 1 && aop == 1 && aopcde == 5)
3187 {
3188 OUTS (outf, dregs_hi (dst0));
3189 OUTS (outf, " = ");
3190 OUTS (outf, dregs (src0));
3191 OUTS (outf, " - ");
3192 OUTS (outf, dregs (src1));
3193 OUTS (outf, " (RND12)");
3194 }
3195 else if (HL == 1 && aop == 0 && aopcde == 2)
3196 {
3197 OUTS (outf, dregs_hi (dst0));
3198 OUTS (outf, " = ");
3199 OUTS (outf, dregs_lo (src0));
3200 OUTS (outf, " + ");
3201 OUTS (outf, dregs_lo (src1));
3202 amod1 (s, x, outf);
3203 }
3204 else if (HL == 1 && aop == 1 && aopcde == 2)
3205 {
3206 OUTS (outf, dregs_hi (dst0));
3207 OUTS (outf, " = ");
3208 OUTS (outf, dregs_lo (src0));
3209 OUTS (outf, " + ");
3210 OUTS (outf, dregs_hi (src1));
3211 amod1 (s, x, outf);
3212 }
3213 else if (HL == 1 && aop == 2 && aopcde == 2)
3214 {
3215 OUTS (outf, dregs_hi (dst0));
3216 OUTS (outf, " = ");
3217 OUTS (outf, dregs_hi (src0));
3218 OUTS (outf, " + ");
3219 OUTS (outf, dregs_lo (src1));
3220 amod1 (s, x, outf);
3221 }
3222 else if (HL == 1 && aop == 3 && aopcde == 2)
3223 {
3224 OUTS (outf, dregs_hi (dst0));
3225 OUTS (outf, " = ");
3226 OUTS (outf, dregs_hi (src0));
3227 OUTS (outf, " + ");
3228 OUTS (outf, dregs_hi (src1));
3229 amod1 (s, x, outf);
3230 }
3231 else if (HL == 0 && aop == 0 && aopcde == 3)
3232 {
3233 OUTS (outf, dregs_lo (dst0));
3234 OUTS (outf, " = ");
3235 OUTS (outf, dregs_lo (src0));
3236 OUTS (outf, " - ");
3237 OUTS (outf, dregs_lo (src1));
3238 amod1 (s, x, outf);
3239 }
3240 else if (HL == 0 && aop == 1 && aopcde == 3)
3241 {
3242 OUTS (outf, dregs_lo (dst0));
3243 OUTS (outf, " = ");
3244 OUTS (outf, dregs_lo (src0));
3245 OUTS (outf, " - ");
3246 OUTS (outf, dregs_hi (src1));
3247 amod1 (s, x, outf);
3248 }
3249 else if (HL == 0 && aop == 3 && aopcde == 2)
3250 {
3251 OUTS (outf, dregs_lo (dst0));
3252 OUTS (outf, " = ");
3253 OUTS (outf, dregs_hi (src0));
3254 OUTS (outf, " + ");
3255 OUTS (outf, dregs_hi (src1));
3256 amod1 (s, x, outf);
3257 }
3258 else if (HL == 1 && aop == 0 && aopcde == 3)
3259 {
3260 OUTS (outf, dregs_hi (dst0));
3261 OUTS (outf, " = ");
3262 OUTS (outf, dregs_lo (src0));
3263 OUTS (outf, " - ");
3264 OUTS (outf, dregs_lo (src1));
3265 amod1 (s, x, outf);
3266 }
3267 else if (HL == 1 && aop == 1 && aopcde == 3)
3268 {
3269 OUTS (outf, dregs_hi (dst0));
3270 OUTS (outf, " = ");
3271 OUTS (outf, dregs_lo (src0));
3272 OUTS (outf, " - ");
3273 OUTS (outf, dregs_hi (src1));
3274 amod1 (s, x, outf);
3275 }
3276 else if (HL == 1 && aop == 2 && aopcde == 3)
3277 {
3278 OUTS (outf, dregs_hi (dst0));
3279 OUTS (outf, " = ");
3280 OUTS (outf, dregs_hi (src0));
3281 OUTS (outf, " - ");
3282 OUTS (outf, dregs_lo (src1));
3283 amod1 (s, x, outf);
3284 }
3285 else if (HL == 1 && aop == 3 && aopcde == 3)
3286 {
3287 OUTS (outf, dregs_hi (dst0));
3288 OUTS (outf, " = ");
3289 OUTS (outf, dregs_hi (src0));
3290 OUTS (outf, " - ");
3291 OUTS (outf, dregs_hi (src1));
3292 amod1 (s, x, outf);
3293 }
3294 else if (HL == 0 && aop == 2 && aopcde == 2)
3295 {
3296 OUTS (outf, dregs_lo (dst0));
3297 OUTS (outf, " = ");
3298 OUTS (outf, dregs_hi (src0));
3299 OUTS (outf, " + ");
3300 OUTS (outf, dregs_lo (src1));
3301 amod1 (s, x, outf);
3302 }
3303 else if (HL == 0 && aop == 1 && aopcde == 2)
3304 {
3305 OUTS (outf, dregs_lo (dst0));
3306 OUTS (outf, " = ");
3307 OUTS (outf, dregs_lo (src0));
3308 OUTS (outf, " + ");
3309 OUTS (outf, dregs_hi (src1));
3310 amod1 (s, x, outf);
3311 }
3312 else if (HL == 0 && aop == 2 && aopcde == 3)
3313 {
3314 OUTS (outf, dregs_lo (dst0));
3315 OUTS (outf, " = ");
3316 OUTS (outf, dregs_hi (src0));
3317 OUTS (outf, " - ");
3318 OUTS (outf, dregs_lo (src1));
3319 amod1 (s, x, outf);
3320 }
3321 else if (HL == 0 && aop == 3 && aopcde == 3)
3322 {
3323 OUTS (outf, dregs_lo (dst0));
3324 OUTS (outf, " = ");
3325 OUTS (outf, dregs_hi (src0));
3326 OUTS (outf, " - ");
3327 OUTS (outf, dregs_hi (src1));
3328 amod1 (s, x, outf);
3329 }
3330 else if (HL == 0 && aop == 0 && aopcde == 2)
3331 {
3332 OUTS (outf, dregs_lo (dst0));
3333 OUTS (outf, " = ");
3334 OUTS (outf, dregs_lo (src0));
3335 OUTS (outf, " + ");
3336 OUTS (outf, dregs_lo (src1));
3337 amod1 (s, x, outf);
3338 }
3339 else if (aop == 0 && aopcde == 9 && s == 1)
3340 {
3341 OUTS (outf, "A0 = ");
3342 OUTS (outf, dregs (src0));
3343 }
3344 else if (aop == 3 && aopcde == 11 && s == 0)
3345 OUTS (outf, "A0 -= A1");
3346
3347 else if (aop == 3 && aopcde == 11 && s == 1)
3348 OUTS (outf, "A0 -= A1 (W32)");
3349
3350 else if (aop == 1 && aopcde == 22 && HL == 1)
3351 {
3352 OUTS (outf, dregs (dst0));
3353 OUTS (outf, " = BYTEOP2P (");
3354 OUTS (outf, dregs (src0 + 1));
3355 OUTS (outf, ":");
3356 OUTS (outf, imm5d (src0));
3357 OUTS (outf, ", ");
3358 OUTS (outf, dregs (src1 + 1));
3359 OUTS (outf, ":");
3360 OUTS (outf, imm5d (src1));
3361 OUTS (outf, ") (TH");
3362 if (s == 1)
3363 OUTS (outf, ", R)");
3364 else
3365 OUTS (outf, ")");
3366 }
3367 else if (aop == 1 && aopcde == 22 && HL == 0)
3368 {
3369 OUTS (outf, dregs (dst0));
3370 OUTS (outf, " = BYTEOP2P (");
3371 OUTS (outf, dregs (src0 + 1));
3372 OUTS (outf, ":");
3373 OUTS (outf, imm5d (src0));
3374 OUTS (outf, ", ");
3375 OUTS (outf, dregs (src1 + 1));
3376 OUTS (outf, ":");
3377 OUTS (outf, imm5d (src1));
3378 OUTS (outf, ") (TL");
3379 if (s == 1)
3380 OUTS (outf, ", R)");
3381 else
3382 OUTS (outf, ")");
3383 }
3384 else if (aop == 0 && aopcde == 22 && HL == 1)
3385 {
3386 OUTS (outf, dregs (dst0));
3387 OUTS (outf, " = BYTEOP2P (");
3388 OUTS (outf, dregs (src0 + 1));
3389 OUTS (outf, ":");
3390 OUTS (outf, imm5d (src0));
3391 OUTS (outf, ", ");
3392 OUTS (outf, dregs (src1 + 1));
3393 OUTS (outf, ":");
3394 OUTS (outf, imm5d (src1));
3395 OUTS (outf, ") (RNDH");
3396 if (s == 1)
3397 OUTS (outf, ", R)");
3398 else
3399 OUTS (outf, ")");
3400 }
3401 else if (aop == 0 && aopcde == 22 && HL == 0)
3402 {
3403 OUTS (outf, dregs (dst0));
3404 OUTS (outf, " = BYTEOP2P (");
3405 OUTS (outf, dregs (src0 + 1));
3406 OUTS (outf, ":");
3407 OUTS (outf, imm5d (src0));
3408 OUTS (outf, ", ");
3409 OUTS (outf, dregs (src1 + 1));
3410 OUTS (outf, ":");
3411 OUTS (outf, imm5d (src1));
3412 OUTS (outf, ") (RNDL");
3413 if (s == 1)
3414 OUTS (outf, ", R)");
3415 else
3416 OUTS (outf, ")");
3417 }
3418 else if (aop == 0 && s == 0 && aopcde == 8)
3419 OUTS (outf, "A0 = 0");
3420
3421 else if (aop == 0 && s == 1 && aopcde == 8)
3422 OUTS (outf, "A0 = A0 (S)");
3423
3424 else if (aop == 1 && s == 0 && aopcde == 8)
3425 OUTS (outf, "A1 = 0");
3426
3427 else if (aop == 1 && s == 1 && aopcde == 8)
3428 OUTS (outf, "A1 = A1 (S)");
3429
3430 else if (aop == 2 && s == 0 && aopcde == 8)
3431 OUTS (outf, "A1 = A0 = 0");
3432
3433 else if (aop == 2 && s == 1 && aopcde == 8)
3434 OUTS (outf, "A1 = A1 (S), A0 = A0 (S)");
3435
3436 else if (aop == 3 && s == 0 && aopcde == 8)
3437 OUTS (outf, "A0 = A1");
3438
3439 else if (aop == 3 && s == 1 && aopcde == 8)
3440 OUTS (outf, "A1 = A0");
3441
3442 else if (aop == 1 && aopcde == 9 && s == 0)
3443 {
3444 OUTS (outf, "A0.X = ");
3445 OUTS (outf, dregs_lo (src0));
3446 }
3447 else if (aop == 1 && HL == 0 && aopcde == 11)
3448 {
3449 OUTS (outf, dregs_lo (dst0));
3450 OUTS (outf, " = (A0 += A1)");
3451 }
3452 else if (aop == 3 && HL == 0 && aopcde == 16)
3453 OUTS (outf, "A1 = ABS A1, A0 = ABS A0");
3454
3455 else if (aop == 0 && aopcde == 23 && HL == 1)
3456 {
3457 OUTS (outf, dregs (dst0));
3458 OUTS (outf, " = BYTEOP3P (");
3459 OUTS (outf, dregs (src0 + 1));
3460 OUTS (outf, ":");
3461 OUTS (outf, imm5d (src0));
3462 OUTS (outf, ", ");
3463 OUTS (outf, dregs (src1 + 1));
3464 OUTS (outf, ":");
3465 OUTS (outf, imm5d (src1));
3466 OUTS (outf, ") (HI");
3467 if (s == 1)
3468 OUTS (outf, ", R)");
3469 else
3470 OUTS (outf, ")");
3471 }
3472 else if (aop == 3 && aopcde == 9 && s == 0)
3473 {
3474 OUTS (outf, "A1.X = ");
3475 OUTS (outf, dregs_lo (src0));
3476 }
3477 else if (aop == 1 && HL == 1 && aopcde == 16)
3478 OUTS (outf, "A1 = ABS A1");
3479
3480 else if (aop == 0 && HL == 1 && aopcde == 16)
3481 OUTS (outf, "A1 = ABS A0");
3482
3483 else if (aop == 2 && aopcde == 9 && s == 1)
3484 {
3485 OUTS (outf, "A1 = ");
3486 OUTS (outf, dregs (src0));
3487 }
3488 else if (HL == 0 && aop == 3 && aopcde == 12)
3489 {
3490 OUTS (outf, dregs_lo (dst0));
3491 OUTS (outf, " = ");
3492 OUTS (outf, dregs (src0));
3493 OUTS (outf, " (RND)");
3494 }
3495 else if (aop == 1 && HL == 0 && aopcde == 16)
3496 OUTS (outf, "A0 = ABS A1");
3497
3498 else if (aop == 0 && HL == 0 && aopcde == 16)
3499 OUTS (outf, "A0 = ABS A0");
3500
3501 else if (aop == 3 && HL == 0 && aopcde == 15)
3502 {
3503 OUTS (outf, dregs (dst0));
3504 OUTS (outf, " = -");
3505 OUTS (outf, dregs (src0));
3506 OUTS (outf, " (V)");
3507 }
3508 else if (aop == 3 && s == 1 && HL == 0 && aopcde == 7)
3509 {
3510 OUTS (outf, dregs (dst0));
3511 OUTS (outf, " = -");
3512 OUTS (outf, dregs (src0));
3513 OUTS (outf, " (S)");
3514 }
3515 else if (aop == 3 && s == 0 && HL == 0 && aopcde == 7)
3516 {
3517 OUTS (outf, dregs (dst0));
3518 OUTS (outf, " = -");
3519 OUTS (outf, dregs (src0));
3520 OUTS (outf, " (NS)");
3521 }
3522 else if (aop == 1 && HL == 1 && aopcde == 11)
3523 {
3524 OUTS (outf, dregs_hi (dst0));
3525 OUTS (outf, " = (A0 += A1)");
3526 }
3527 else if (aop == 2 && aopcde == 11 && s == 0)
3528 OUTS (outf, "A0 += A1");
3529
3530 else if (aop == 2 && aopcde == 11 && s == 1)
3531 OUTS (outf, "A0 += A1 (W32)");
3532
3533 else if (aop == 3 && HL == 0 && aopcde == 14)
3534 OUTS (outf, "A1 = -A1, A0 = -A0");
3535
3536 else if (HL == 1 && aop == 3 && aopcde == 12)
3537 {
3538 OUTS (outf, dregs_hi (dst0));
3539 OUTS (outf, " = ");
3540 OUTS (outf, dregs (src0));
3541 OUTS (outf, " (RND)");
3542 }
3543 else if (aop == 0 && aopcde == 23 && HL == 0)
3544 {
3545 OUTS (outf, dregs (dst0));
3546 OUTS (outf, " = BYTEOP3P (");
3547 OUTS (outf, dregs (src0 + 1));
3548 OUTS (outf, ":");
3549 OUTS (outf, imm5d (src0));
3550 OUTS (outf, ", ");
3551 OUTS (outf, dregs (src1 + 1));
3552 OUTS (outf, ":");
3553 OUTS (outf, imm5d (src1));
3554 OUTS (outf, ") (LO");
3555 if (s == 1)
3556 OUTS (outf, ", R)");
3557 else
3558 OUTS (outf, ")");
3559 }
3560 else if (aop == 0 && HL == 0 && aopcde == 14)
3561 OUTS (outf, "A0 = -A0");
3562
3563 else if (aop == 1 && HL == 0 && aopcde == 14)
3564 OUTS (outf, "A0 = -A1");
3565
3566 else if (aop == 0 && HL == 1 && aopcde == 14)
3567 OUTS (outf, "A1 = -A0");
3568
3569 else if (aop == 1 && HL == 1 && aopcde == 14)
3570 OUTS (outf, "A1 = -A1");
3571
3572 else if (aop == 0 && aopcde == 12)
3573 {
3574 OUTS (outf, dregs_hi (dst0));
3575 OUTS (outf, " = ");
3576 OUTS (outf, dregs_lo (dst0));
3577 OUTS (outf, " = SIGN (");
3578 OUTS (outf, dregs_hi (src0));
3579 OUTS (outf, ") * ");
3580 OUTS (outf, dregs_hi (src1));
3581 OUTS (outf, " + SIGN (");
3582 OUTS (outf, dregs_lo (src0));
3583 OUTS (outf, ") * ");
3584 OUTS (outf, dregs_lo (src1));
3585 }
3586 else if (aop == 2 && aopcde == 0)
3587 {
3588 OUTS (outf, dregs (dst0));
3589 OUTS (outf, " = ");
3590 OUTS (outf, dregs (src0));
3591 OUTS (outf, " -|+ ");
3592 OUTS (outf, dregs (src1));
3593 amod0 (s, x, outf);
3594 }
3595 else if (aop == 1 && aopcde == 12)
3596 {
3597 OUTS (outf, dregs (dst1));
3598 OUTS (outf, " = A1.L + A1.H, ");
3599 OUTS (outf, dregs (dst0));
3600 OUTS (outf, " = A0.L + A0.H");
3601 }
3602 else if (aop == 2 && aopcde == 4)
3603 {
3604 OUTS (outf, dregs (dst1));
3605 OUTS (outf, " = ");
3606 OUTS (outf, dregs (src0));
3607 OUTS (outf, " + ");
3608 OUTS (outf, dregs (src1));
3609 OUTS (outf, ", ");
3610 OUTS (outf, dregs (dst0));
3611 OUTS (outf, " = ");
3612 OUTS (outf, dregs (src0));
3613 OUTS (outf, " - ");
3614 OUTS (outf, dregs (src1));
3615 amod1 (s, x, outf);
3616 }
3617 else if (HL == 0 && aopcde == 1)
3618 {
3619 OUTS (outf, dregs (dst1));
3620 OUTS (outf, " = ");
3621 OUTS (outf, dregs (src0));
3622 OUTS (outf, " +|+ ");
3623 OUTS (outf, dregs (src1));
3624 OUTS (outf, ", ");
3625 OUTS (outf, dregs (dst0));
3626 OUTS (outf, " = ");
3627 OUTS (outf, dregs (src0));
3628 OUTS (outf, " -|- ");
3629 OUTS (outf, dregs (src1));
3630 amod0amod2 (s, x, aop, outf);
3631 }
3632 else if (aop == 0 && aopcde == 11)
3633 {
3634 OUTS (outf, dregs (dst0));
3635 OUTS (outf, " = (A0 += A1)");
3636 }
3637 else if (aop == 0 && aopcde == 10)
3638 {
3639 OUTS (outf, dregs_lo (dst0));
3640 OUTS (outf, " = A0.X");
3641 }
3642 else if (aop == 1 && aopcde == 10)
3643 {
3644 OUTS (outf, dregs_lo (dst0));
3645 OUTS (outf, " = A1.X");
3646 }
3647 else if (aop == 1 && aopcde == 0)
3648 {
3649 OUTS (outf, dregs (dst0));
3650 OUTS (outf, " = ");
3651 OUTS (outf, dregs (src0));
3652 OUTS (outf, " +|- ");
3653 OUTS (outf, dregs (src1));
3654 amod0 (s, x, outf);
3655 }
3656 else if (aop == 3 && aopcde == 0)
3657 {
3658 OUTS (outf, dregs (dst0));
3659 OUTS (outf, " = ");
3660 OUTS (outf, dregs (src0));
3661 OUTS (outf, " -|- ");
3662 OUTS (outf, dregs (src1));
3663 amod0 (s, x, outf);
3664 }
3665 else if (aop == 1 && aopcde == 4)
3666 {
3667 OUTS (outf, dregs (dst0));
3668 OUTS (outf, " = ");
3669 OUTS (outf, dregs (src0));
3670 OUTS (outf, " - ");
3671 OUTS (outf, dregs (src1));
3672 amod1 (s, x, outf);
3673 }
3674 else if (aop == 0 && aopcde == 17)
3675 {
3676 OUTS (outf, dregs (dst1));
3677 OUTS (outf, " = A1 + A0, ");
3678 OUTS (outf, dregs (dst0));
3679 OUTS (outf, " = A1 - A0");
3680 amod1 (s, x, outf);
3681 }
3682 else if (aop == 1 && aopcde == 17)
3683 {
3684 OUTS (outf, dregs (dst1));
3685 OUTS (outf, " = A0 + A1, ");
3686 OUTS (outf, dregs (dst0));
3687 OUTS (outf, " = A0 - A1");
3688 amod1 (s, x, outf);
3689 }
3690 else if (aop == 0 && aopcde == 18)
3691 {
3692 OUTS (outf, "SAA (");
3693 OUTS (outf, dregs (src0 + 1));
3694 OUTS (outf, ":");
3695 OUTS (outf, imm5d (src0));
3696 OUTS (outf, ", ");
3697 OUTS (outf, dregs (src1 + 1));
3698 OUTS (outf, ":");
3699 OUTS (outf, imm5d (src1));
3700 OUTS (outf, ")");
3701 aligndir (s, outf);
3702 }
3703 else if (aop == 3 && aopcde == 18)
3704 OUTS (outf, "DISALGNEXCPT");
3705
3706 else if (aop == 0 && aopcde == 20)
3707 {
3708 OUTS (outf, dregs (dst0));
3709 OUTS (outf, " = BYTEOP1P (");
3710 OUTS (outf, dregs (src0 + 1));
3711 OUTS (outf, ":");
3712 OUTS (outf, imm5d (src0));
3713 OUTS (outf, ", ");
3714 OUTS (outf, dregs (src1 + 1));
3715 OUTS (outf, ":");
3716 OUTS (outf, imm5d (src1));
3717 OUTS (outf, ")");
3718 aligndir (s, outf);
3719 }
3720 else if (aop == 1 && aopcde == 20)
3721 {
3722 OUTS (outf, dregs (dst0));
3723 OUTS (outf, " = BYTEOP1P (");
3724 OUTS (outf, dregs (src0 + 1));
3725 OUTS (outf, ":");
3726 OUTS (outf, imm5d (src0));
3727 OUTS (outf, ", ");
3728 OUTS (outf, dregs (src1 + 1));
3729 OUTS (outf, ":");
3730 OUTS (outf, imm5d (src1));
3731 OUTS (outf, ") (T");
3732 if (s == 1)
3733 OUTS (outf, ", R)");
3734 else
3735 OUTS (outf, ")");
3736 }
3737 else if (aop == 0 && aopcde == 21)
3738 {
3739 OUTS (outf, "(");
3740 OUTS (outf, dregs (dst1));
3741 OUTS (outf, ", ");
3742 OUTS (outf, dregs (dst0));
3743 OUTS (outf, ") = BYTEOP16P (");
3744 OUTS (outf, dregs (src0 + 1));
3745 OUTS (outf, ":");
3746 OUTS (outf, imm5d (src0));
3747 OUTS (outf, ", ");
3748 OUTS (outf, dregs (src1 + 1));
3749 OUTS (outf, ":");
3750 OUTS (outf, imm5d (src1));
3751 OUTS (outf, ")");
3752 aligndir (s, outf);
3753 }
3754 else if (aop == 1 && aopcde == 21)
3755 {
3756 OUTS (outf, "(");
3757 OUTS (outf, dregs (dst1));
3758 OUTS (outf, ", ");
3759 OUTS (outf, dregs (dst0));
3760 OUTS (outf, ") = BYTEOP16M (");
3761 OUTS (outf, dregs (src0 + 1));
3762 OUTS (outf, ":");
3763 OUTS (outf, imm5d (src0));
3764 OUTS (outf, ", ");
3765 OUTS (outf, dregs (src1 + 1));
3766 OUTS (outf, ":");
3767 OUTS (outf, imm5d (src1));
3768 OUTS (outf, ")");
3769 aligndir (s, outf);
3770 }
3771 else if (aop == 2 && aopcde == 7)
3772 {
3773 OUTS (outf, dregs (dst0));
3774 OUTS (outf, " = ABS ");
3775 OUTS (outf, dregs (src0));
3776 }
3777 else if (aop == 1 && aopcde == 7)
3778 {
3779 OUTS (outf, dregs (dst0));
3780 OUTS (outf, " = MIN (");
3781 OUTS (outf, dregs (src0));
3782 OUTS (outf, ", ");
3783 OUTS (outf, dregs (src1));
3784 OUTS (outf, ")");
3785 }
3786 else if (aop == 0 && aopcde == 7)
3787 {
3788 OUTS (outf, dregs (dst0));
3789 OUTS (outf, " = MAX (");
3790 OUTS (outf, dregs (src0));
3791 OUTS (outf, ", ");
3792 OUTS (outf, dregs (src1));
3793 OUTS (outf, ")");
3794 }
3795 else if (aop == 2 && aopcde == 6)
3796 {
3797 OUTS (outf, dregs (dst0));
3798 OUTS (outf, " = ABS ");
3799 OUTS (outf, dregs (src0));
3800 OUTS (outf, " (V)");
3801 }
3802 else if (aop == 1 && aopcde == 6)
3803 {
3804 OUTS (outf, dregs (dst0));
3805 OUTS (outf, " = MIN (");
3806 OUTS (outf, dregs (src0));
3807 OUTS (outf, ", ");
3808 OUTS (outf, dregs (src1));
3809 OUTS (outf, ") (V)");
3810 }
3811 else if (aop == 0 && aopcde == 6)
3812 {
3813 OUTS (outf, dregs (dst0));
3814 OUTS (outf, " = MAX (");
3815 OUTS (outf, dregs (src0));
3816 OUTS (outf, ", ");
3817 OUTS (outf, dregs (src1));
3818 OUTS (outf, ") (V)");
3819 }
3820 else if (HL == 1 && aopcde == 1)
3821 {
3822 OUTS (outf, dregs (dst1));
3823 OUTS (outf, " = ");
3824 OUTS (outf, dregs (src0));
3825 OUTS (outf, " +|- ");
3826 OUTS (outf, dregs (src1));
3827 OUTS (outf, ", ");
3828 OUTS (outf, dregs (dst0));
3829 OUTS (outf, " = ");
3830 OUTS (outf, dregs (src0));
3831 OUTS (outf, " -|+ ");
3832 OUTS (outf, dregs (src1));
3833 amod0amod2 (s, x, aop, outf);
3834 }
3835 else if (aop == 0 && aopcde == 4)
3836 {
3837 OUTS (outf, dregs (dst0));
3838 OUTS (outf, " = ");
3839 OUTS (outf, dregs (src0));
3840 OUTS (outf, " + ");
3841 OUTS (outf, dregs (src1));
3842 amod1 (s, x, outf);
3843 }
3844 else if (aop == 0 && aopcde == 0)
3845 {
3846 OUTS (outf, dregs (dst0));
3847 OUTS (outf, " = ");
3848 OUTS (outf, dregs (src0));
3849 OUTS (outf, " +|+ ");
3850 OUTS (outf, dregs (src1));
3851 amod0 (s, x, outf);
3852 }
3853 else if (aop == 0 && aopcde == 24)
3854 {
3855 OUTS (outf, dregs (dst0));
3856 OUTS (outf, " = BYTEPACK (");
3857 OUTS (outf, dregs (src0));
3858 OUTS (outf, ", ");
3859 OUTS (outf, dregs (src1));
3860 OUTS (outf, ")");
3861 }
3862 else if (aop == 1 && aopcde == 24)
3863 {
3864 OUTS (outf, "(");
3865 OUTS (outf, dregs (dst1));
3866 OUTS (outf, ", ");
3867 OUTS (outf, dregs (dst0));
3868 OUTS (outf, ") = BYTEUNPACK ");
3869 OUTS (outf, dregs (src0 + 1));
3870 OUTS (outf, ":");
3871 OUTS (outf, imm5d (src0));
3872 aligndir (s, outf);
3873 }
3874 else if (aopcde == 13)
3875 {
3876 OUTS (outf, "(");
3877 OUTS (outf, dregs (dst1));
3878 OUTS (outf, ", ");
3879 OUTS (outf, dregs (dst0));
3880 OUTS (outf, ") = SEARCH ");
3881 OUTS (outf, dregs (src0));
3882 OUTS (outf, " (");
3883 searchmod (aop, outf);
3884 OUTS (outf, ")");
3885 }
3886 else
3887 return 0;
3888
3889 return 4;
3890 }
3891
3892 static int
3893 decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3894 {
3895 /* dsp32shift
3896 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3897 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
3898 |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
3899 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3900 int HLs = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask);
3901 int sop = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask);
3902 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask);
3903 int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask);
3904 int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask);
3905 int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask);
3906 const char *acc01 = (HLs & 1) == 0 ? "A0" : "A1";
3907
3908 if (HLs == 0 && sop == 0 && sopcde == 0)
3909 {
3910 OUTS (outf, dregs_lo (dst0));
3911 OUTS (outf, " = ASHIFT ");
3912 OUTS (outf, dregs_lo (src1));
3913 OUTS (outf, " BY ");
3914 OUTS (outf, dregs_lo (src0));
3915 }
3916 else if (HLs == 1 && sop == 0 && sopcde == 0)
3917 {
3918 OUTS (outf, dregs_lo (dst0));
3919 OUTS (outf, " = ASHIFT ");
3920 OUTS (outf, dregs_hi (src1));
3921 OUTS (outf, " BY ");
3922 OUTS (outf, dregs_lo (src0));
3923 }
3924 else if (HLs == 2 && sop == 0 && sopcde == 0)
3925 {
3926 OUTS (outf, dregs_hi (dst0));
3927 OUTS (outf, " = ASHIFT ");
3928 OUTS (outf, dregs_lo (src1));
3929 OUTS (outf, " BY ");
3930 OUTS (outf, dregs_lo (src0));
3931 }
3932 else if (HLs == 3 && sop == 0 && sopcde == 0)
3933 {
3934 OUTS (outf, dregs_hi (dst0));
3935 OUTS (outf, " = ASHIFT ");
3936 OUTS (outf, dregs_hi (src1));
3937 OUTS (outf, " BY ");
3938 OUTS (outf, dregs_lo (src0));
3939 }
3940 else if (HLs == 0 && sop == 1 && sopcde == 0)
3941 {
3942 OUTS (outf, dregs_lo (dst0));
3943 OUTS (outf, " = ASHIFT ");
3944 OUTS (outf, dregs_lo (src1));
3945 OUTS (outf, " BY ");
3946 OUTS (outf, dregs_lo (src0));
3947 OUTS (outf, " (S)");
3948 }
3949 else if (HLs == 1 && sop == 1 && sopcde == 0)
3950 {
3951 OUTS (outf, dregs_lo (dst0));
3952 OUTS (outf, " = ASHIFT ");
3953 OUTS (outf, dregs_hi (src1));
3954 OUTS (outf, " BY ");
3955 OUTS (outf, dregs_lo (src0));
3956 OUTS (outf, " (S)");
3957 }
3958 else if (HLs == 2 && sop == 1 && sopcde == 0)
3959 {
3960 OUTS (outf, dregs_hi (dst0));
3961 OUTS (outf, " = ASHIFT ");
3962 OUTS (outf, dregs_lo (src1));
3963 OUTS (outf, " BY ");
3964 OUTS (outf, dregs_lo (src0));
3965 OUTS (outf, " (S)");
3966 }
3967 else if (HLs == 3 && sop == 1 && sopcde == 0)
3968 {
3969 OUTS (outf, dregs_hi (dst0));
3970 OUTS (outf, " = ASHIFT ");
3971 OUTS (outf, dregs_hi (src1));
3972 OUTS (outf, " BY ");
3973 OUTS (outf, dregs_lo (src0));
3974 OUTS (outf, " (S)");
3975 }
3976 else if (sop == 2 && sopcde == 0)
3977 {
3978 OUTS (outf, (HLs & 2) == 0 ? dregs_lo (dst0) : dregs_hi (dst0));
3979 OUTS (outf, " = LSHIFT ");
3980 OUTS (outf, (HLs & 1) == 0 ? dregs_lo (src1) : dregs_hi (src1));
3981 OUTS (outf, " BY ");
3982 OUTS (outf, dregs_lo (src0));
3983 }
3984 else if (sop == 0 && sopcde == 3)
3985 {
3986 OUTS (outf, acc01);
3987 OUTS (outf, " = ASHIFT ");
3988 OUTS (outf, acc01);
3989 OUTS (outf, " BY ");
3990 OUTS (outf, dregs_lo (src0));
3991 }
3992 else if (sop == 1 && sopcde == 3)
3993 {
3994 OUTS (outf, acc01);
3995 OUTS (outf, " = LSHIFT ");
3996 OUTS (outf, acc01);
3997 OUTS (outf, " BY ");
3998 OUTS (outf, dregs_lo (src0));
3999 }
4000 else if (sop == 2 && sopcde == 3)
4001 {
4002 OUTS (outf, acc01);
4003 OUTS (outf, " = ROT ");
4004 OUTS (outf, acc01);
4005 OUTS (outf, " BY ");
4006 OUTS (outf, dregs_lo (src0));
4007 }
4008 else if (sop == 3 && sopcde == 3)
4009 {
4010 OUTS (outf, dregs (dst0));
4011 OUTS (outf, " = ROT ");
4012 OUTS (outf, dregs (src1));
4013 OUTS (outf, " BY ");
4014 OUTS (outf, dregs_lo (src0));
4015 }
4016 else if (sop == 1 && sopcde == 1)
4017 {
4018 OUTS (outf, dregs (dst0));
4019 OUTS (outf, " = ASHIFT ");
4020 OUTS (outf, dregs (src1));
4021 OUTS (outf, " BY ");
4022 OUTS (outf, dregs_lo (src0));
4023 OUTS (outf, " (V, S)");
4024 }
4025 else if (sop == 0 && sopcde == 1)
4026 {
4027 OUTS (outf, dregs (dst0));
4028 OUTS (outf, " = ASHIFT ");
4029 OUTS (outf, dregs (src1));
4030 OUTS (outf, " BY ");
4031 OUTS (outf, dregs_lo (src0));
4032 OUTS (outf, " (V)");
4033 }
4034 else if (sop == 0 && sopcde == 2)
4035 {
4036 OUTS (outf, dregs (dst0));
4037 OUTS (outf, " = ASHIFT ");
4038 OUTS (outf, dregs (src1));
4039 OUTS (outf, " BY ");
4040 OUTS (outf, dregs_lo (src0));
4041 }
4042 else if (sop == 1 && sopcde == 2)
4043 {
4044 OUTS (outf, dregs (dst0));
4045 OUTS (outf, " = ASHIFT ");
4046 OUTS (outf, dregs (src1));
4047 OUTS (outf, " BY ");
4048 OUTS (outf, dregs_lo (src0));
4049 OUTS (outf, " (S)");
4050 }
4051 else if (sop == 2 && sopcde == 2)
4052 {
4053 OUTS (outf, dregs (dst0));
4054 OUTS (outf, " = LSHIFT ");
4055 OUTS (outf, dregs (src1));
4056 OUTS (outf, " BY ");
4057 OUTS (outf, dregs_lo (src0));
4058 }
4059 else if (sop == 3 && sopcde == 2)
4060 {
4061 OUTS (outf, dregs (dst0));
4062 OUTS (outf, " = ROT ");
4063 OUTS (outf, dregs (src1));
4064 OUTS (outf, " BY ");
4065 OUTS (outf, dregs_lo (src0));
4066 }
4067 else if (sop == 2 && sopcde == 1)
4068 {
4069 OUTS (outf, dregs (dst0));
4070 OUTS (outf, " = LSHIFT ");
4071 OUTS (outf, dregs (src1));
4072 OUTS (outf, " BY ");
4073 OUTS (outf, dregs_lo (src0));
4074 OUTS (outf, " (V)");
4075 }
4076 else if (sop == 0 && sopcde == 4)
4077 {
4078 OUTS (outf, dregs (dst0));
4079 OUTS (outf, " = PACK (");
4080 OUTS (outf, dregs_lo (src1));
4081 OUTS (outf, ", ");
4082 OUTS (outf, dregs_lo (src0));
4083 OUTS (outf, ")");
4084 }
4085 else if (sop == 1 && sopcde == 4)
4086 {
4087 OUTS (outf, dregs (dst0));
4088 OUTS (outf, " = PACK (");
4089 OUTS (outf, dregs_lo (src1));
4090 OUTS (outf, ", ");
4091 OUTS (outf, dregs_hi (src0));
4092 OUTS (outf, ")");
4093 }
4094 else if (sop == 2 && sopcde == 4)
4095 {
4096 OUTS (outf, dregs (dst0));
4097 OUTS (outf, " = PACK (");
4098 OUTS (outf, dregs_hi (src1));
4099 OUTS (outf, ", ");
4100 OUTS (outf, dregs_lo (src0));
4101 OUTS (outf, ")");
4102 }
4103 else if (sop == 3 && sopcde == 4)
4104 {
4105 OUTS (outf, dregs (dst0));
4106 OUTS (outf, " = PACK (");
4107 OUTS (outf, dregs_hi (src1));
4108 OUTS (outf, ", ");
4109 OUTS (outf, dregs_hi (src0));
4110 OUTS (outf, ")");
4111 }
4112 else if (sop == 0 && sopcde == 5)
4113 {
4114 OUTS (outf, dregs_lo (dst0));
4115 OUTS (outf, " = SIGNBITS ");
4116 OUTS (outf, dregs (src1));
4117 }
4118 else if (sop == 1 && sopcde == 5)
4119 {
4120 OUTS (outf, dregs_lo (dst0));
4121 OUTS (outf, " = SIGNBITS ");
4122 OUTS (outf, dregs_lo (src1));
4123 }
4124 else if (sop == 2 && sopcde == 5)
4125 {
4126 OUTS (outf, dregs_lo (dst0));
4127 OUTS (outf, " = SIGNBITS ");
4128 OUTS (outf, dregs_hi (src1));
4129 }
4130 else if (sop == 0 && sopcde == 6)
4131 {
4132 OUTS (outf, dregs_lo (dst0));
4133 OUTS (outf, " = SIGNBITS A0");
4134 }
4135 else if (sop == 1 && sopcde == 6)
4136 {
4137 OUTS (outf, dregs_lo (dst0));
4138 OUTS (outf, " = SIGNBITS A1");
4139 }
4140 else if (sop == 3 && sopcde == 6)
4141 {
4142 OUTS (outf, dregs_lo (dst0));
4143 OUTS (outf, " = ONES ");
4144 OUTS (outf, dregs (src1));
4145 }
4146 else if (sop == 0 && sopcde == 7)
4147 {
4148 OUTS (outf, dregs_lo (dst0));
4149 OUTS (outf, " = EXPADJ (");
4150 OUTS (outf, dregs (src1));
4151 OUTS (outf, ", ");
4152 OUTS (outf, dregs_lo (src0));
4153 OUTS (outf, ")");
4154 }
4155 else if (sop == 1 && sopcde == 7)
4156 {
4157 OUTS (outf, dregs_lo (dst0));
4158 OUTS (outf, " = EXPADJ (");
4159 OUTS (outf, dregs (src1));
4160 OUTS (outf, ", ");
4161 OUTS (outf, dregs_lo (src0));
4162 OUTS (outf, ") (V)");
4163 }
4164 else if (sop == 2 && sopcde == 7)
4165 {
4166 OUTS (outf, dregs_lo (dst0));
4167 OUTS (outf, " = EXPADJ (");
4168 OUTS (outf, dregs_lo (src1));
4169 OUTS (outf, ", ");
4170 OUTS (outf, dregs_lo (src0));
4171 OUTS (outf, ")");
4172 }
4173 else if (sop == 3 && sopcde == 7)
4174 {
4175 OUTS (outf, dregs_lo (dst0));
4176 OUTS (outf, " = EXPADJ (");
4177 OUTS (outf, dregs_hi (src1));
4178 OUTS (outf, ", ");
4179 OUTS (outf, dregs_lo (src0));
4180 OUTS (outf, ")");
4181 }
4182 else if (sop == 0 && sopcde == 8)
4183 {
4184 OUTS (outf, "BITMUX (");
4185 OUTS (outf, dregs (src0));
4186 OUTS (outf, ", ");
4187 OUTS (outf, dregs (src1));
4188 OUTS (outf, ", A0) (ASR)");
4189 }
4190 else if (sop == 1 && sopcde == 8)
4191 {
4192 OUTS (outf, "BITMUX (");
4193 OUTS (outf, dregs (src0));
4194 OUTS (outf, ", ");
4195 OUTS (outf, dregs (src1));
4196 OUTS (outf, ", A0) (ASL)");
4197 }
4198 else if (sop == 0 && sopcde == 9)
4199 {
4200 OUTS (outf, dregs_lo (dst0));
4201 OUTS (outf, " = VIT_MAX (");
4202 OUTS (outf, dregs (src1));
4203 OUTS (outf, ") (ASL)");
4204 }
4205 else if (sop == 1 && sopcde == 9)
4206 {
4207 OUTS (outf, dregs_lo (dst0));
4208 OUTS (outf, " = VIT_MAX (");
4209 OUTS (outf, dregs (src1));
4210 OUTS (outf, ") (ASR)");
4211 }
4212 else if (sop == 2 && sopcde == 9)
4213 {
4214 OUTS (outf, dregs (dst0));
4215 OUTS (outf, " = VIT_MAX (");
4216 OUTS (outf, dregs (src1));
4217 OUTS (outf, ", ");
4218 OUTS (outf, dregs (src0));
4219 OUTS (outf, ") (ASL)");
4220 }
4221 else if (sop == 3 && sopcde == 9)
4222 {
4223 OUTS (outf, dregs (dst0));
4224 OUTS (outf, " = VIT_MAX (");
4225 OUTS (outf, dregs (src1));
4226 OUTS (outf, ", ");
4227 OUTS (outf, dregs (src0));
4228 OUTS (outf, ") (ASR)");
4229 }
4230 else if (sop == 0 && sopcde == 10)
4231 {
4232 OUTS (outf, dregs (dst0));
4233 OUTS (outf, " = EXTRACT (");
4234 OUTS (outf, dregs (src1));
4235 OUTS (outf, ", ");
4236 OUTS (outf, dregs_lo (src0));
4237 OUTS (outf, ") (Z)");
4238 }
4239 else if (sop == 1 && sopcde == 10)
4240 {
4241 OUTS (outf, dregs (dst0));
4242 OUTS (outf, " = EXTRACT (");
4243 OUTS (outf, dregs (src1));
4244 OUTS (outf, ", ");
4245 OUTS (outf, dregs_lo (src0));
4246 OUTS (outf, ") (X)");
4247 }
4248 else if (sop == 2 && sopcde == 10)
4249 {
4250 OUTS (outf, dregs (dst0));
4251 OUTS (outf, " = DEPOSIT (");
4252 OUTS (outf, dregs (src1));
4253 OUTS (outf, ", ");
4254 OUTS (outf, dregs (src0));
4255 OUTS (outf, ")");
4256 }
4257 else if (sop == 3 && sopcde == 10)
4258 {
4259 OUTS (outf, dregs (dst0));
4260 OUTS (outf, " = DEPOSIT (");
4261 OUTS (outf, dregs (src1));
4262 OUTS (outf, ", ");
4263 OUTS (outf, dregs (src0));
4264 OUTS (outf, ") (X)");
4265 }
4266 else if (sop == 0 && sopcde == 11)
4267 {
4268 OUTS (outf, dregs_lo (dst0));
4269 OUTS (outf, " = CC = BXORSHIFT (A0, ");
4270 OUTS (outf, dregs (src0));
4271 OUTS (outf, ")");
4272 }
4273 else if (sop == 1 && sopcde == 11)
4274 {
4275 OUTS (outf, dregs_lo (dst0));
4276 OUTS (outf, " = CC = BXOR (A0, ");
4277 OUTS (outf, dregs (src0));
4278 OUTS (outf, ")");
4279 }
4280 else if (sop == 0 && sopcde == 12)
4281 OUTS (outf, "A0 = BXORSHIFT (A0, A1, CC)");
4282
4283 else if (sop == 1 && sopcde == 12)
4284 {
4285 OUTS (outf, dregs_lo (dst0));
4286 OUTS (outf, " = CC = BXOR (A0, A1, CC)");
4287 }
4288 else if (sop == 0 && sopcde == 13)
4289 {
4290 OUTS (outf, dregs (dst0));
4291 OUTS (outf, " = ALIGN8 (");
4292 OUTS (outf, dregs (src1));
4293 OUTS (outf, ", ");
4294 OUTS (outf, dregs (src0));
4295 OUTS (outf, ")");
4296 }
4297 else if (sop == 1 && sopcde == 13)
4298 {
4299 OUTS (outf, dregs (dst0));
4300 OUTS (outf, " = ALIGN16 (");
4301 OUTS (outf, dregs (src1));
4302 OUTS (outf, ", ");
4303 OUTS (outf, dregs (src0));
4304 OUTS (outf, ")");
4305 }
4306 else if (sop == 2 && sopcde == 13)
4307 {
4308 OUTS (outf, dregs (dst0));
4309 OUTS (outf, " = ALIGN24 (");
4310 OUTS (outf, dregs (src1));
4311 OUTS (outf, ", ");
4312 OUTS (outf, dregs (src0));
4313 OUTS (outf, ")");
4314 }
4315 else
4316 return 0;
4317
4318 return 4;
4319 }
4320
4321 static int
4322 decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4323 {
4324 /* dsp32shiftimm
4325 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4326 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
4327 |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
4328 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4329 int src1 = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask);
4330 int sop = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask);
4331 int bit8 = ((iw1 >> 8) & 0x1);
4332 int immag = ((iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4333 int newimmag = (-(iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4334 int dst0 = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask);
4335 int sopcde = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
4336 int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
4337
4338 if (sop == 0 && sopcde == 0)
4339 {
4340 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4341 OUTS (outf, " = ");
4342 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4343 OUTS (outf, " >>> ");
4344 OUTS (outf, uimm4 (newimmag));
4345 }
4346 else if (sop == 1 && sopcde == 0 && bit8 == 0)
4347 {
4348 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4349 OUTS (outf, " = ");
4350 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4351 OUTS (outf, " << ");
4352 OUTS (outf, uimm4 (immag));
4353 OUTS (outf, " (S)");
4354 }
4355 else if (sop == 1 && sopcde == 0 && bit8 == 1)
4356 {
4357 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4358 OUTS (outf, " = ");
4359 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4360 OUTS (outf, " >>> ");
4361 OUTS (outf, uimm4 (newimmag));
4362 OUTS (outf, " (S)");
4363 }
4364 else if (sop == 2 && sopcde == 0 && bit8 == 0)
4365 {
4366 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4367 OUTS (outf, " = ");
4368 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4369 OUTS (outf, " << ");
4370 OUTS (outf, uimm4 (immag));
4371 }
4372 else if (sop == 2 && sopcde == 0 && bit8 == 1)
4373 {
4374 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4375 OUTS (outf, " = ");
4376 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4377 OUTS (outf, " >> ");
4378 OUTS (outf, uimm4 (newimmag));
4379 }
4380 else if (sop == 2 && sopcde == 3 && HLs == 1)
4381 {
4382 OUTS (outf, "A1 = ROT A1 BY ");
4383 OUTS (outf, imm6 (immag));
4384 }
4385 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0)
4386 {
4387 OUTS (outf, "A0 = A0 << ");
4388 OUTS (outf, uimm5 (immag));
4389 }
4390 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1)
4391 {
4392 OUTS (outf, "A0 = A0 >>> ");
4393 OUTS (outf, uimm5 (newimmag));
4394 }
4395 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0)
4396 {
4397 OUTS (outf, "A1 = A1 << ");
4398 OUTS (outf, uimm5 (immag));
4399 }
4400 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1)
4401 {
4402 OUTS (outf, "A1 = A1 >>> ");
4403 OUTS (outf, uimm5 (newimmag));
4404 }
4405 else if (sop == 1 && sopcde == 3 && HLs == 0)
4406 {
4407 OUTS (outf, "A0 = A0 >> ");
4408 OUTS (outf, uimm5 (newimmag));
4409 }
4410 else if (sop == 1 && sopcde == 3 && HLs == 1)
4411 {
4412 OUTS (outf, "A1 = A1 >> ");
4413 OUTS (outf, uimm5 (newimmag));
4414 }
4415 else if (sop == 2 && sopcde == 3 && HLs == 0)
4416 {
4417 OUTS (outf, "A0 = ROT A0 BY ");
4418 OUTS (outf, imm6 (immag));
4419 }
4420 else if (sop == 1 && sopcde == 1 && bit8 == 0)
4421 {
4422 OUTS (outf, dregs (dst0));
4423 OUTS (outf, " = ");
4424 OUTS (outf, dregs (src1));
4425 OUTS (outf, " << ");
4426 OUTS (outf, uimm5 (immag));
4427 OUTS (outf, " (V, S)");
4428 }
4429 else if (sop == 1 && sopcde == 1 && bit8 == 1)
4430 {
4431 OUTS (outf, dregs (dst0));
4432 OUTS (outf, " = ");
4433 OUTS (outf, dregs (src1));
4434 OUTS (outf, " >>> ");
4435 OUTS (outf, imm5 (-immag));
4436 OUTS (outf, " (V, S)");
4437 }
4438 else if (sop == 2 && sopcde == 1 && bit8 == 1)
4439 {
4440 OUTS (outf, dregs (dst0));
4441 OUTS (outf, " = ");
4442 OUTS (outf, dregs (src1));
4443 OUTS (outf, " >> ");
4444 OUTS (outf, uimm5 (newimmag));
4445 OUTS (outf, " (V)");
4446 }
4447 else if (sop == 2 && sopcde == 1 && bit8 == 0)
4448 {
4449 OUTS (outf, dregs (dst0));
4450 OUTS (outf, " = ");
4451 OUTS (outf, dregs (src1));
4452 OUTS (outf, " << ");
4453 OUTS (outf, imm5 (immag));
4454 OUTS (outf, " (V)");
4455 }
4456 else if (sop == 0 && sopcde == 1)
4457 {
4458 OUTS (outf, dregs (dst0));
4459 OUTS (outf, " = ");
4460 OUTS (outf, dregs (src1));
4461 OUTS (outf, " >>> ");
4462 OUTS (outf, uimm5 (newimmag));
4463 OUTS (outf, " (V)");
4464 }
4465 else if (sop == 1 && sopcde == 2)
4466 {
4467 OUTS (outf, dregs (dst0));
4468 OUTS (outf, " = ");
4469 OUTS (outf, dregs (src1));
4470 OUTS (outf, " << ");
4471 OUTS (outf, uimm5 (immag));
4472 OUTS (outf, " (S)");
4473 }
4474 else if (sop == 2 && sopcde == 2 && bit8 == 1)
4475 {
4476 OUTS (outf, dregs (dst0));
4477 OUTS (outf, " = ");
4478 OUTS (outf, dregs (src1));
4479 OUTS (outf, " >> ");
4480 OUTS (outf, uimm5 (newimmag));
4481 }
4482 else if (sop == 2 && sopcde == 2 && bit8 == 0)
4483 {
4484 OUTS (outf, dregs (dst0));
4485 OUTS (outf, " = ");
4486 OUTS (outf, dregs (src1));
4487 OUTS (outf, " << ");
4488 OUTS (outf, uimm5 (immag));
4489 }
4490 else if (sop == 3 && sopcde == 2)
4491 {
4492 OUTS (outf, dregs (dst0));
4493 OUTS (outf, " = ROT ");
4494 OUTS (outf, dregs (src1));
4495 OUTS (outf, " BY ");
4496 OUTS (outf, imm6 (immag));
4497 }
4498 else if (sop == 0 && sopcde == 2)
4499 {
4500 OUTS (outf, dregs (dst0));
4501 OUTS (outf, " = ");
4502 OUTS (outf, dregs (src1));
4503 OUTS (outf, " >>> ");
4504 OUTS (outf, uimm5 (newimmag));
4505 }
4506 else
4507 return 0;
4508
4509 return 4;
4510 }
4511
4512 static int
4513 decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf)
4514 {
4515 /* pseudoDEBUG
4516 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4517 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
4518 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4519 int fn = ((iw0 >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
4520 int grp = ((iw0 >> PseudoDbg_grp_bits) & PseudoDbg_grp_mask);
4521 int reg = ((iw0 >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
4522
4523 if (parallel)
4524 return 0;
4525
4526 if (reg == 0 && fn == 3)
4527 OUTS (outf, "DBG A0");
4528
4529 else if (reg == 1 && fn == 3)
4530 OUTS (outf, "DBG A1");
4531
4532 else if (reg == 3 && fn == 3)
4533 OUTS (outf, "ABORT");
4534
4535 else if (reg == 4 && fn == 3)
4536 OUTS (outf, "HLT");
4537
4538 else if (reg == 5 && fn == 3)
4539 OUTS (outf, "DBGHALT");
4540
4541 else if (reg == 6 && fn == 3)
4542 {
4543 OUTS (outf, "DBGCMPLX (");
4544 OUTS (outf, dregs (grp));
4545 OUTS (outf, ")");
4546 }
4547 else if (reg == 7 && fn == 3)
4548 OUTS (outf, "DBG");
4549
4550 else if (grp == 0 && fn == 2)
4551 {
4552 OUTS (outf, "OUTC ");
4553 OUTS (outf, dregs (reg));
4554 }
4555 else if (fn == 0)
4556 {
4557 OUTS (outf, "DBG ");
4558 OUTS (outf, allregs (reg, grp));
4559 }
4560 else if (fn == 1)
4561 {
4562 OUTS (outf, "PRNT ");
4563 OUTS (outf, allregs (reg, grp));
4564 }
4565 else
4566 return 0;
4567
4568 return 2;
4569 }
4570
4571 static int
4572 decode_pseudoOChar_0 (TIword iw0, disassemble_info *outf)
4573 {
4574 /* psedoOChar
4575 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4576 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................|
4577 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4578 int ch = ((iw0 >> PseudoChr_ch_bits) & PseudoChr_ch_mask);
4579
4580 if (parallel)
4581 return 0;
4582
4583 OUTS (outf, "OUTC ");
4584 OUTS (outf, uimm8 (ch));
4585
4586 return 2;
4587 }
4588
4589 static int
4590 decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4591 {
4592 /* pseudodbg_assert
4593 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4594 | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
4595 |.expected......................................................|
4596 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4597 int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
4598 int dbgop = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
4599 int grp = ((iw0 >> (PseudoDbg_Assert_grp_bits - 16)) & PseudoDbg_Assert_grp_mask);
4600 int regtest = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
4601
4602 if (parallel)
4603 return 0;
4604
4605 if (dbgop == 0)
4606 {
4607 OUTS (outf, "DBGA (");
4608 OUTS (outf, regs_lo (regtest, grp));
4609 OUTS (outf, ", ");
4610 OUTS (outf, uimm16 (expected));
4611 OUTS (outf, ")");
4612 }
4613 else if (dbgop == 1)
4614 {
4615 OUTS (outf, "DBGA (");
4616 OUTS (outf, regs_hi (regtest, grp));
4617 OUTS (outf, ", ");
4618 OUTS (outf, uimm16 (expected));
4619 OUTS (outf, ")");
4620 }
4621 else if (dbgop == 2)
4622 {
4623 OUTS (outf, "DBGAL (");
4624 OUTS (outf, allregs (regtest, grp));
4625 OUTS (outf, ", ");
4626 OUTS (outf, uimm16 (expected));
4627 OUTS (outf, ")");
4628 }
4629 else if (dbgop == 3)
4630 {
4631 OUTS (outf, "DBGAH (");
4632 OUTS (outf, allregs (regtest, grp));
4633 OUTS (outf, ", ");
4634 OUTS (outf, uimm16 (expected));
4635 OUTS (outf, ")");
4636 }
4637 else
4638 return 0;
4639 return 4;
4640 }
4641
4642 static int
4643 ifetch (bfd_vma pc, disassemble_info *outf, TIword *iw)
4644 {
4645 bfd_byte buf[2];
4646 int status;
4647
4648 status = (*outf->read_memory_func) (pc, buf, 2, outf);
4649 if (status != 0)
4650 {
4651 (*outf->memory_error_func) (status, pc, outf);
4652 return -1;
4653 }
4654
4655 *iw = bfd_getl16 (buf);
4656 return 0;
4657 }
4658
4659 static int
4660 _print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4661 {
4662 TIword iw0;
4663 TIword iw1;
4664 int rv = 0;
4665
4666 /* The PC must be 16-bit aligned. */
4667 if (pc & 1)
4668 {
4669 OUTS (outf, "ILLEGAL (UNALIGNED)");
4670 /* For people dumping data, just re-align the return value. */
4671 return 1;
4672 }
4673
4674 if (ifetch (pc, outf, &iw0))
4675 return -1;
4676
4677 if ((iw0 & 0xc000) == 0xc000)
4678 {
4679 /* 32-bit insn. */
4680 if (ifetch (pc + 2, outf, &iw1))
4681 return -1;
4682 }
4683 else
4684 /* 16-bit insn. */
4685 iw1 = 0;
4686
4687 if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800)
4688 {
4689 if (parallel)
4690 {
4691 OUTS (outf, "ILLEGAL");
4692 return 0;
4693 }
4694 OUTS (outf, "MNOP");
4695 return 4;
4696 }
4697 else if ((iw0 & 0xff00) == 0x0000)
4698 rv = decode_ProgCtrl_0 (iw0, outf);
4699 else if ((iw0 & 0xffc0) == 0x0240)
4700 rv = decode_CaCTRL_0 (iw0, outf);
4701 else if ((iw0 & 0xff80) == 0x0100)
4702 rv = decode_PushPopReg_0 (iw0, outf);
4703 else if ((iw0 & 0xfe00) == 0x0400)
4704 rv = decode_PushPopMultiple_0 (iw0, outf);
4705 else if ((iw0 & 0xfe00) == 0x0600)
4706 rv = decode_ccMV_0 (iw0, outf);
4707 else if ((iw0 & 0xf800) == 0x0800)
4708 rv = decode_CCflag_0 (iw0, outf);
4709 else if ((iw0 & 0xffe0) == 0x0200)
4710 rv = decode_CC2dreg_0 (iw0, outf);
4711 else if ((iw0 & 0xff00) == 0x0300)
4712 rv = decode_CC2stat_0 (iw0, outf);
4713 else if ((iw0 & 0xf000) == 0x1000)
4714 rv = decode_BRCC_0 (iw0, pc, outf);
4715 else if ((iw0 & 0xf000) == 0x2000)
4716 rv = decode_UJUMP_0 (iw0, pc, outf);
4717 else if ((iw0 & 0xf000) == 0x3000)
4718 rv = decode_REGMV_0 (iw0, outf);
4719 else if ((iw0 & 0xfc00) == 0x4000)
4720 rv = decode_ALU2op_0 (iw0, outf);
4721 else if ((iw0 & 0xfe00) == 0x4400)
4722 rv = decode_PTR2op_0 (iw0, outf);
4723 else if ((iw0 & 0xf800) == 0x4800)
4724 rv = decode_LOGI2op_0 (iw0, outf);
4725 else if ((iw0 & 0xf000) == 0x5000)
4726 rv = decode_COMP3op_0 (iw0, outf);
4727 else if ((iw0 & 0xf800) == 0x6000)
4728 rv = decode_COMPI2opD_0 (iw0, outf);
4729 else if ((iw0 & 0xf800) == 0x6800)
4730 rv = decode_COMPI2opP_0 (iw0, outf);
4731 else if ((iw0 & 0xf000) == 0x8000)
4732 rv = decode_LDSTpmod_0 (iw0, outf);
4733 else if ((iw0 & 0xff60) == 0x9e60)
4734 rv = decode_dagMODim_0 (iw0, outf);
4735 else if ((iw0 & 0xfff0) == 0x9f60)
4736 rv = decode_dagMODik_0 (iw0, outf);
4737 else if ((iw0 & 0xfc00) == 0x9c00)
4738 rv = decode_dspLDST_0 (iw0, outf);
4739 else if ((iw0 & 0xf000) == 0x9000)
4740 rv = decode_LDST_0 (iw0, outf);
4741 else if ((iw0 & 0xfc00) == 0xb800)
4742 rv = decode_LDSTiiFP_0 (iw0, outf);
4743 else if ((iw0 & 0xe000) == 0xA000)
4744 rv = decode_LDSTii_0 (iw0, outf);
4745 else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000)
4746 rv = decode_LoopSetup_0 (iw0, iw1, pc, outf);
4747 else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000)
4748 rv = decode_LDIMMhalf_0 (iw0, iw1, outf);
4749 else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000)
4750 rv = decode_CALLa_0 (iw0, iw1, pc, outf);
4751 else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000)
4752 rv = decode_LDSTidxI_0 (iw0, iw1, outf);
4753 else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000)
4754 rv = decode_linkage_0 (iw0, iw1, outf);
4755 else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000)
4756 rv = decode_dsp32mac_0 (iw0, iw1, outf);
4757 else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000)
4758 rv = decode_dsp32mult_0 (iw0, iw1, outf);
4759 else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000)
4760 rv = decode_dsp32alu_0 (iw0, iw1, outf);
4761 else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000)
4762 rv = decode_dsp32shift_0 (iw0, iw1, outf);
4763 else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000)
4764 rv = decode_dsp32shiftimm_0 (iw0, iw1, outf);
4765 else if ((iw0 & 0xff00) == 0xf800)
4766 rv = decode_pseudoDEBUG_0 (iw0, outf);
4767 else if ((iw0 & 0xFF00) == 0xF900)
4768 rv = decode_pseudoOChar_0 (iw0, outf);
4769 else if ((iw0 & 0xFF00) == 0xf000 && (iw1 & 0x0000) == 0x0000)
4770 rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
4771
4772 if (rv == 0)
4773 OUTS (outf, "ILLEGAL");
4774
4775 return rv;
4776 }
4777
4778 int
4779 print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4780 {
4781 TIword iw0;
4782 int count;
4783
4784 if (ifetch (pc, outf, &iw0) == -1)
4785 return -1;
4786
4787 count = _print_insn_bfin (pc, outf);
4788 if (count == -1)
4789 return -1;
4790
4791 /* Proper display of multiple issue instructions. */
4792
4793 if (count == 4 && (iw0 & 0xc000) == 0xc000 && (iw0 & BIT_MULTI_INS)
4794 && ((iw0 & 0xe800) != 0xe800 /* Not Linkage. */ ))
4795 {
4796 int legal = 1;
4797 int len;
4798
4799 parallel = 1;
4800 OUTS (outf, " || ");
4801 len = _print_insn_bfin (pc + 4, outf);
4802 if (len == -1)
4803 return -1;
4804 OUTS (outf, " || ");
4805 if (len != 2)
4806 legal = 0;
4807 len = _print_insn_bfin (pc + 6, outf);
4808 if (len == -1)
4809 return -1;
4810 if (len != 2)
4811 legal = 0;
4812
4813 if (legal)
4814 count = 8;
4815 else
4816 {
4817 OUTS (outf, ";\t\t/* ILLEGAL PARALLEL INSTRUCTION */");
4818 comment = 1;
4819 count = 0;
4820 }
4821 parallel = 0;
4822 }
4823
4824 if (!comment)
4825 OUTS (outf, ";");
4826
4827 if (count == 0)
4828 return 2;
4829
4830 comment = 0;
4831
4832 return count;
4833 }
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