opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VCMP_Fixup (int, int);
  99 static void VPCMP_Fixup (int, int);
 100 static void VPCOM_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void NOP_Fixup1 (int, int);
 105 static void NOP_Fixup2 (int, int);
 106 static void OP_3DNowSuffix (int, int);
 107 static void CMP_Fixup (int, int);
 108 static void BadOp (void);
 109 static void REP_Fixup (int, int);
 110 static void SEP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void NOTRACK_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void PCMPESTR_Fixup (int, int);
 121 static void OP_LWPCB_E (int, int);
 122 static void OP_LWP_E (int, int);
 123 static void OP_Vex_2src_1 (int, int);
 124 static void OP_Vex_2src_2 (int, int);
 125
 126 static void MOVBE_Fixup (int, int);
 127 static void MOVSXD_Fixup (int, int);
 128
 129 static void OP_Mask (int, int);
 130
 131 struct dis_private {
 132   /* Points to first byte not fetched.  */
 133   bfd_byte *max_fetched;
 134   bfd_byte the_buffer[MAX_MNEM_SIZE];
 135   bfd_vma insn_start;
 136   int orig_sizeflag;
 137   OPCODES_SIGJMP_BUF bailout;
 138 };
 139
 140 enum address_mode
 141 {
 142   mode_16bit,
 143   mode_32bit,
 144   mode_64bit
 145 };
 146
 147 enum address_mode address_mode;
 148
 149 /* Flags for the prefixes for the current instruction.  See below.  */
 150 static int prefixes;
 151
 152 /* REX prefix the current instruction.  See below.  */
 153 static int rex;
 154 /* Bits of REX we've already used.  */
 155 static int rex_used;
 156 /* REX bits in original REX prefix ignored.  */
 157 static int rex_ignored;
 158 /* Mark parts used in the REX prefix.  When we are testing for
 159    empty prefix (for 8bit register REX extension), just mask it
 160    out.  Otherwise test for REX bit is excuse for existence of REX
 161    only in case value is nonzero.  */
 162 #define USED_REX(value)                                 \
 163   {                                                     \
 164     if (value)                                          \
 165       {                                                 \
 166         if ((rex & value))                              \
 167           rex_used |= (value) | REX_OPCODE;             \
 168       }                                                 \
 169     else                                                \
 170       rex_used |= REX_OPCODE;                           \
 171   }
 172
 173 /* Flags for prefixes which we somehow handled when printing the
 174    current instruction.  */
 175 static int used_prefixes;
 176
 177 /* Flags stored in PREFIXES.  */
 178 #define PREFIX_REPZ 1
 179 #define PREFIX_REPNZ 2
 180 #define PREFIX_LOCK 4
 181 #define PREFIX_CS 8
 182 #define PREFIX_SS 0x10
 183 #define PREFIX_DS 0x20
 184 #define PREFIX_ES 0x40
 185 #define PREFIX_FS 0x80
 186 #define PREFIX_GS 0x100
 187 #define PREFIX_DATA 0x200
 188 #define PREFIX_ADDR 0x400
 189 #define PREFIX_FWAIT 0x800
 190
 191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 192    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 193    on error.  */
 194 #define FETCH_DATA(info, addr) \
 195   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 196    ? 1 : fetch_data ((info), (addr)))
 197
 198 static int
 199 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 200 {
 201   int status;
 202   struct dis_private *priv = (struct dis_private *) info->private_data;
 203   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 204
 205   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 206     status = (*info->read_memory_func) (start,
 207                                         priv->max_fetched,
 208                                         addr - priv->max_fetched,
 209                                         info);
 210   else
 211     status = -1;
 212   if (status != 0)
 213     {
 214       /* If we did manage to read at least one byte, then
 215          print_insn_i386 will do something sensible.  Otherwise, print
 216          an error.  We do that here because this is where we know
 217          STATUS.  */
 218       if (priv->max_fetched == priv->the_buffer)
 219         (*info->memory_error_func) (status, start, info);
 220       OPCODES_SIGLONGJMP (priv->bailout, 1);
 221     }
 222   else
 223     priv->max_fetched = addr;
 224   return 1;
 225 }
 226
 227 /* Possible values for prefix requirement.  */
 228 #define PREFIX_IGNORED_SHIFT    16
 229 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 233 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 234
 235 /* Opcode prefixes.  */
 236 #define PREFIX_OPCODE           (PREFIX_REPZ \
 237                                  | PREFIX_REPNZ \
 238                                  | PREFIX_DATA)
 239
 240 /* Prefixes ignored.  */
 241 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 242                                  | PREFIX_IGNORED_REPNZ \
 243                                  | PREFIX_IGNORED_DATA)
 244
 245 #define XX { NULL, 0 }
 246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 247
 248 #define Eb { OP_E, b_mode }
 249 #define Ebnd { OP_E, bnd_mode }
 250 #define EbS { OP_E, b_swap_mode }
 251 #define EbndS { OP_E, bnd_swap_mode }
 252 #define Ev { OP_E, v_mode }
 253 #define Eva { OP_E, va_mode }
 254 #define Ev_bnd { OP_E, v_bnd_mode }
 255 #define EvS { OP_E, v_swap_mode }
 256 #define Ed { OP_E, d_mode }
 257 #define Edq { OP_E, dq_mode }
 258 #define Edqw { OP_E, dqw_mode }
 259 #define Edqb { OP_E, dqb_mode }
 260 #define Edb { OP_E, db_mode }
 261 #define Edw { OP_E, dw_mode }
 262 #define Edqd { OP_E, dqd_mode }
 263 #define Eq { OP_E, q_mode }
 264 #define indirEv { OP_indirE, indir_v_mode }
 265 #define indirEp { OP_indirE, f_mode }
 266 #define stackEv { OP_E, stack_v_mode }
 267 #define Em { OP_E, m_mode }
 268 #define Ew { OP_E, w_mode }
 269 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 270 #define Ma { OP_M, a_mode }
 271 #define Mb { OP_M, b_mode }
 272 #define Md { OP_M, d_mode }
 273 #define Mo { OP_M, o_mode }
 274 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 275 #define Mq { OP_M, q_mode }
 276 #define Mv_bnd { OP_M, v_bndmk_mode }
 277 #define Mx { OP_M, x_mode }
 278 #define Mxmm { OP_M, xmm_mode }
 279 #define Gb { OP_G, b_mode }
 280 #define Gbnd { OP_G, bnd_mode }
 281 #define Gv { OP_G, v_mode }
 282 #define Gd { OP_G, d_mode }
 283 #define Gdq { OP_G, dq_mode }
 284 #define Gm { OP_G, m_mode }
 285 #define Gva { OP_G, va_mode }
 286 #define Gw { OP_G, w_mode }
 287 #define Rd { OP_R, d_mode }
 288 #define Rdq { OP_R, dq_mode }
 289 #define Rm { OP_R, m_mode }
 290 #define Ib { OP_I, b_mode }
 291 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 292 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 293 #define Iv { OP_I, v_mode }
 294 #define sIv { OP_sI, v_mode }
 295 #define Iv64 { OP_I64, v_mode }
 296 #define Id { OP_I, d_mode }
 297 #define Iw { OP_I, w_mode }
 298 #define I1 { OP_I, const_1_mode }
 299 #define Jb { OP_J, b_mode }
 300 #define Jv { OP_J, v_mode }
 301 #define Jdqw { OP_J, dqw_mode }
 302 #define Cm { OP_C, m_mode }
 303 #define Dm { OP_D, m_mode }
 304 #define Td { OP_T, d_mode }
 305 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 306
 307 #define RMeAX { OP_REG, eAX_reg }
 308 #define RMeBX { OP_REG, eBX_reg }
 309 #define RMeCX { OP_REG, eCX_reg }
 310 #define RMeDX { OP_REG, eDX_reg }
 311 #define RMeSP { OP_REG, eSP_reg }
 312 #define RMeBP { OP_REG, eBP_reg }
 313 #define RMeSI { OP_REG, eSI_reg }
 314 #define RMeDI { OP_REG, eDI_reg }
 315 #define RMrAX { OP_REG, rAX_reg }
 316 #define RMrBX { OP_REG, rBX_reg }
 317 #define RMrCX { OP_REG, rCX_reg }
 318 #define RMrDX { OP_REG, rDX_reg }
 319 #define RMrSP { OP_REG, rSP_reg }
 320 #define RMrBP { OP_REG, rBP_reg }
 321 #define RMrSI { OP_REG, rSI_reg }
 322 #define RMrDI { OP_REG, rDI_reg }
 323 #define RMAL { OP_REG, al_reg }
 324 #define RMCL { OP_REG, cl_reg }
 325 #define RMDL { OP_REG, dl_reg }
 326 #define RMBL { OP_REG, bl_reg }
 327 #define RMAH { OP_REG, ah_reg }
 328 #define RMCH { OP_REG, ch_reg }
 329 #define RMDH { OP_REG, dh_reg }
 330 #define RMBH { OP_REG, bh_reg }
 331 #define RMAX { OP_REG, ax_reg }
 332 #define RMDX { OP_REG, dx_reg }
 333
 334 #define eAX { OP_IMREG, eAX_reg }
 335 #define eBX { OP_IMREG, eBX_reg }
 336 #define eCX { OP_IMREG, eCX_reg }
 337 #define eDX { OP_IMREG, eDX_reg }
 338 #define eSP { OP_IMREG, eSP_reg }
 339 #define eBP { OP_IMREG, eBP_reg }
 340 #define eSI { OP_IMREG, eSI_reg }
 341 #define eDI { OP_IMREG, eDI_reg }
 342 #define AL { OP_IMREG, al_reg }
 343 #define CL { OP_IMREG, cl_reg }
 344 #define DL { OP_IMREG, dl_reg }
 345 #define BL { OP_IMREG, bl_reg }
 346 #define AH { OP_IMREG, ah_reg }
 347 #define CH { OP_IMREG, ch_reg }
 348 #define DH { OP_IMREG, dh_reg }
 349 #define BH { OP_IMREG, bh_reg }
 350 #define AX { OP_IMREG, ax_reg }
 351 #define DX { OP_IMREG, dx_reg }
 352 #define zAX { OP_IMREG, z_mode_ax_reg }
 353 #define indirDX { OP_IMREG, indir_dx_reg }
 354
 355 #define Sw { OP_SEG, w_mode }
 356 #define Sv { OP_SEG, v_mode }
 357 #define Ap { OP_DIR, 0 }
 358 #define Ob { OP_OFF64, b_mode }
 359 #define Ov { OP_OFF64, v_mode }
 360 #define Xb { OP_DSreg, eSI_reg }
 361 #define Xv { OP_DSreg, eSI_reg }
 362 #define Xz { OP_DSreg, eSI_reg }
 363 #define Yb { OP_ESreg, eDI_reg }
 364 #define Yv { OP_ESreg, eDI_reg }
 365 #define DSBX { OP_DSreg, eBX_reg }
 366
 367 #define es { OP_REG, es_reg }
 368 #define ss { OP_REG, ss_reg }
 369 #define cs { OP_REG, cs_reg }
 370 #define ds { OP_REG, ds_reg }
 371 #define fs { OP_REG, fs_reg }
 372 #define gs { OP_REG, gs_reg }
 373
 374 #define MX { OP_MMX, 0 }
 375 #define XM { OP_XMM, 0 }
 376 #define XMScalar { OP_XMM, scalar_mode }
 377 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 378 #define XMM { OP_XMM, xmm_mode }
 379 #define XMxmmq { OP_XMM, xmmq_mode }
 380 #define EM { OP_EM, v_mode }
 381 #define EMS { OP_EM, v_swap_mode }
 382 #define EMd { OP_EM, d_mode }
 383 #define EMx { OP_EM, x_mode }
 384 #define EXbScalar { OP_EX, b_scalar_mode }
 385 #define EXw { OP_EX, w_mode }
 386 #define EXwScalar { OP_EX, w_scalar_mode }
 387 #define EXd { OP_EX, d_mode }
 388 #define EXdScalar { OP_EX, d_scalar_mode }
 389 #define EXdS { OP_EX, d_swap_mode }
 390 #define EXq { OP_EX, q_mode }
 391 #define EXqScalar { OP_EX, q_scalar_mode }
 392 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 393 #define EXqS { OP_EX, q_swap_mode }
 394 #define EXx { OP_EX, x_mode }
 395 #define EXxS { OP_EX, x_swap_mode }
 396 #define EXxmm { OP_EX, xmm_mode }
 397 #define EXymm { OP_EX, ymm_mode }
 398 #define EXxmmq { OP_EX, xmmq_mode }
 399 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 400 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 401 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 402 #define EXxmm_md { OP_EX, xmm_md_mode }
 403 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 404 #define EXxmmdw { OP_EX, xmmdw_mode }
 405 #define EXxmmqd { OP_EX, xmmqd_mode }
 406 #define EXymmq { OP_EX, ymmq_mode }
 407 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 408 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 409 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 410 #define MS { OP_MS, v_mode }
 411 #define XS { OP_XS, v_mode }
 412 #define EMCq { OP_EMC, q_mode }
 413 #define MXC { OP_MXC, 0 }
 414 #define OPSUF { OP_3DNowSuffix, 0 }
 415 #define SEP { SEP_Fixup, 0 }
 416 #define CMP { CMP_Fixup, 0 }
 417 #define XMM0 { XMM_Fixup, 0 }
 418 #define FXSAVE { FXSAVE_Fixup, 0 }
 419 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 420 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 421
 422 #define Vex { OP_VEX, vex_mode }
 423 #define VexScalar { OP_VEX, vex_scalar_mode }
 424 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 425 #define Vex128 { OP_VEX, vex128_mode }
 426 #define Vex256 { OP_VEX, vex256_mode }
 427 #define VexGdq { OP_VEX, dq_mode }
 428 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 429 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 430 #define EXVexW { OP_EX_VexW, x_mode }
 431 #define EXdVexW { OP_EX_VexW, d_mode }
 432 #define EXqVexW { OP_EX_VexW, q_mode }
 433 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 434 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 435 #define XMVexW { OP_XMM_VexW, 0 }
 436 #define XMVexI4 { OP_REG_VexI4, x_mode }
 437 #define PCLMUL { PCLMUL_Fixup, 0 }
 438 #define VCMP { VCMP_Fixup, 0 }
 439 #define VPCMP { VPCMP_Fixup, 0 }
 440 #define VPCOM { VPCOM_Fixup, 0 }
 441
 442 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 443 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 444 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 445
 446 #define XMask { OP_Mask, mask_mode }
 447 #define MaskG { OP_G, mask_mode }
 448 #define MaskE { OP_E, mask_mode }
 449 #define MaskBDE { OP_E, mask_bd_mode }
 450 #define MaskR { OP_R, mask_mode }
 451 #define MaskVex { OP_VEX, mask_mode }
 452
 453 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 454 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 455 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 456 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 457
 458 /* Used handle "rep" prefix for string instructions.  */
 459 #define Xbr { REP_Fixup, eSI_reg }
 460 #define Xvr { REP_Fixup, eSI_reg }
 461 #define Ybr { REP_Fixup, eDI_reg }
 462 #define Yvr { REP_Fixup, eDI_reg }
 463 #define Yzr { REP_Fixup, eDI_reg }
 464 #define indirDXr { REP_Fixup, indir_dx_reg }
 465 #define ALr { REP_Fixup, al_reg }
 466 #define eAXr { REP_Fixup, eAX_reg }
 467
 468 /* Used handle HLE prefix for lockable instructions.  */
 469 #define Ebh1 { HLE_Fixup1, b_mode }
 470 #define Evh1 { HLE_Fixup1, v_mode }
 471 #define Ebh2 { HLE_Fixup2, b_mode }
 472 #define Evh2 { HLE_Fixup2, v_mode }
 473 #define Ebh3 { HLE_Fixup3, b_mode }
 474 #define Evh3 { HLE_Fixup3, v_mode }
 475
 476 #define BND { BND_Fixup, 0 }
 477 #define NOTRACK { NOTRACK_Fixup, 0 }
 478
 479 #define cond_jump_flag { NULL, cond_jump_mode }
 480 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 481
 482 /* bits in sizeflag */
 483 #define SUFFIX_ALWAYS 4
 484 #define AFLAG 2
 485 #define DFLAG 1
 486
 487 enum
 488 {
 489   /* byte operand */
 490   b_mode = 1,
 491   /* byte operand with operand swapped */
 492   b_swap_mode,
 493   /* byte operand, sign extend like 'T' suffix */
 494   b_T_mode,
 495   /* operand size depends on prefixes */
 496   v_mode,
 497   /* operand size depends on prefixes with operand swapped */
 498   v_swap_mode,
 499   /* operand size depends on address prefix */
 500   va_mode,
 501   /* word operand */
 502   w_mode,
 503   /* double word operand  */
 504   d_mode,
 505   /* double word operand with operand swapped */
 506   d_swap_mode,
 507   /* quad word operand */
 508   q_mode,
 509   /* quad word operand with operand swapped */
 510   q_swap_mode,
 511   /* ten-byte operand */
 512   t_mode,
 513   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 514      broadcast enabled.  */
 515   x_mode,
 516   /* Similar to x_mode, but with different EVEX mem shifts.  */
 517   evex_x_gscat_mode,
 518   /* Similar to x_mode, but with disabled broadcast.  */
 519   evex_x_nobcst_mode,
 520   /* Similar to x_mode, but with operands swapped and disabled broadcast
 521      in EVEX.  */
 522   x_swap_mode,
 523   /* 16-byte XMM operand */
 524   xmm_mode,
 525   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 526      memory operand (depending on vector length).  Broadcast isn't
 527      allowed.  */
 528   xmmq_mode,
 529   /* Same as xmmq_mode, but broadcast is allowed.  */
 530   evex_half_bcst_xmmq_mode,
 531   /* XMM register or byte memory operand */
 532   xmm_mb_mode,
 533   /* XMM register or word memory operand */
 534   xmm_mw_mode,
 535   /* XMM register or double word memory operand */
 536   xmm_md_mode,
 537   /* XMM register or quad word memory operand */
 538   xmm_mq_mode,
 539   /* 16-byte XMM, word, double word or quad word operand.  */
 540   xmmdw_mode,
 541   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 542   xmmqd_mode,
 543   /* 32-byte YMM operand */
 544   ymm_mode,
 545   /* quad word, ymmword or zmmword memory operand.  */
 546   ymmq_mode,
 547   /* 32-byte YMM or 16-byte word operand */
 548   ymmxmm_mode,
 549   /* d_mode in 32bit, q_mode in 64bit mode.  */
 550   m_mode,
 551   /* pair of v_mode operands */
 552   a_mode,
 553   cond_jump_mode,
 554   loop_jcxz_mode,
 555   movsxd_mode,
 556   v_bnd_mode,
 557   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 558   v_bndmk_mode,
 559   /* operand size depends on REX prefixes.  */
 560   dq_mode,
 561   /* registers like dq_mode, memory like w_mode, displacements like
 562      v_mode without considering Intel64 ISA.  */
 563   dqw_mode,
 564   /* bounds operand */
 565   bnd_mode,
 566   /* bounds operand with operand swapped */
 567   bnd_swap_mode,
 568   /* 4- or 6-byte pointer operand */
 569   f_mode,
 570   const_1_mode,
 571   /* v_mode for indirect branch opcodes.  */
 572   indir_v_mode,
 573   /* v_mode for stack-related opcodes.  */
 574   stack_v_mode,
 575   /* non-quad operand size depends on prefixes */
 576   z_mode,
 577   /* 16-byte operand */
 578   o_mode,
 579   /* registers like dq_mode, memory like b_mode.  */
 580   dqb_mode,
 581   /* registers like d_mode, memory like b_mode.  */
 582   db_mode,
 583   /* registers like d_mode, memory like w_mode.  */
 584   dw_mode,
 585   /* registers like dq_mode, memory like d_mode.  */
 586   dqd_mode,
 587   /* normal vex mode */
 588   vex_mode,
 589   /* 128bit vex mode */
 590   vex128_mode,
 591   /* 256bit vex mode */
 592   vex256_mode,
 593
 594   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 595   vex_vsib_d_w_dq_mode,
 596   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 597   vex_vsib_d_w_d_mode,
 598   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 599   vex_vsib_q_w_dq_mode,
 600   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 601   vex_vsib_q_w_d_mode,
 602
 603   /* scalar, ignore vector length.  */
 604   scalar_mode,
 605   /* like b_mode, ignore vector length.  */
 606   b_scalar_mode,
 607   /* like w_mode, ignore vector length.  */
 608   w_scalar_mode,
 609   /* like d_mode, ignore vector length.  */
 610   d_scalar_mode,
 611   /* like d_swap_mode, ignore vector length.  */
 612   d_scalar_swap_mode,
 613   /* like q_mode, ignore vector length.  */
 614   q_scalar_mode,
 615   /* like q_swap_mode, ignore vector length.  */
 616   q_scalar_swap_mode,
 617   /* like vex_mode, ignore vector length.  */
 618   vex_scalar_mode,
 619   /* Operand size depends on the VEX.W bit, ignore vector length.  */
 620   vex_scalar_w_dq_mode,
 621
 622   /* Static rounding.  */
 623   evex_rounding_mode,
 624   /* Static rounding, 64-bit mode only.  */
 625   evex_rounding_64_mode,
 626   /* Supress all exceptions.  */
 627   evex_sae_mode,
 628
 629   /* Mask register operand.  */
 630   mask_mode,
 631   /* Mask register operand.  */
 632   mask_bd_mode,
 633
 634   es_reg,
 635   cs_reg,
 636   ss_reg,
 637   ds_reg,
 638   fs_reg,
 639   gs_reg,
 640
 641   eAX_reg,
 642   eCX_reg,
 643   eDX_reg,
 644   eBX_reg,
 645   eSP_reg,
 646   eBP_reg,
 647   eSI_reg,
 648   eDI_reg,
 649
 650   al_reg,
 651   cl_reg,
 652   dl_reg,
 653   bl_reg,
 654   ah_reg,
 655   ch_reg,
 656   dh_reg,
 657   bh_reg,
 658
 659   ax_reg,
 660   cx_reg,
 661   dx_reg,
 662   bx_reg,
 663   sp_reg,
 664   bp_reg,
 665   si_reg,
 666   di_reg,
 667
 668   rAX_reg,
 669   rCX_reg,
 670   rDX_reg,
 671   rBX_reg,
 672   rSP_reg,
 673   rBP_reg,
 674   rSI_reg,
 675   rDI_reg,
 676
 677   z_mode_ax_reg,
 678   indir_dx_reg
 679 };
 680
 681 enum
 682 {
 683   FLOATCODE = 1,
 684   USE_REG_TABLE,
 685   USE_MOD_TABLE,
 686   USE_RM_TABLE,
 687   USE_PREFIX_TABLE,
 688   USE_X86_64_TABLE,
 689   USE_3BYTE_TABLE,
 690   USE_XOP_8F_TABLE,
 691   USE_VEX_C4_TABLE,
 692   USE_VEX_C5_TABLE,
 693   USE_VEX_LEN_TABLE,
 694   USE_VEX_W_TABLE,
 695   USE_EVEX_TABLE,
 696   USE_EVEX_LEN_TABLE
 697 };
 698
 699 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 700
 701 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 702 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 703 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 704 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 705 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 706 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 707 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 708 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 709 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 710 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 711 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 712 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 713 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 714 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 715 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 716 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 717
 718 enum
 719 {
 720   REG_80 = 0,
 721   REG_81,
 722   REG_83,
 723   REG_8F,
 724   REG_C0,
 725   REG_C1,
 726   REG_C6,
 727   REG_C7,
 728   REG_D0,
 729   REG_D1,
 730   REG_D2,
 731   REG_D3,
 732   REG_F6,
 733   REG_F7,
 734   REG_FE,
 735   REG_FF,
 736   REG_0F00,
 737   REG_0F01,
 738   REG_0F0D,
 739   REG_0F18,
 740   REG_0F1C_P_0_MOD_0,
 741   REG_0F1E_P_1_MOD_3,
 742   REG_0F71,
 743   REG_0F72,
 744   REG_0F73,
 745   REG_0FA6,
 746   REG_0FA7,
 747   REG_0FAE,
 748   REG_0FBA,
 749   REG_0FC7,
 750   REG_VEX_0F71,
 751   REG_VEX_0F72,
 752   REG_VEX_0F73,
 753   REG_VEX_0FAE,
 754   REG_VEX_0F38F3,
 755   REG_XOP_LWPCB,
 756   REG_XOP_LWP,
 757   REG_XOP_TBM_01,
 758   REG_XOP_TBM_02,
 759
 760   REG_EVEX_0F71,
 761   REG_EVEX_0F72,
 762   REG_EVEX_0F73,
 763   REG_EVEX_0F38C6,
 764   REG_EVEX_0F38C7
 765 };
 766
 767 enum
 768 {
 769   MOD_8D = 0,
 770   MOD_C6_REG_7,
 771   MOD_C7_REG_7,
 772   MOD_FF_REG_3,
 773   MOD_FF_REG_5,
 774   MOD_0F01_REG_0,
 775   MOD_0F01_REG_1,
 776   MOD_0F01_REG_2,
 777   MOD_0F01_REG_3,
 778   MOD_0F01_REG_5,
 779   MOD_0F01_REG_7,
 780   MOD_0F12_PREFIX_0,
 781   MOD_0F13,
 782   MOD_0F16_PREFIX_0,
 783   MOD_0F17,
 784   MOD_0F18_REG_0,
 785   MOD_0F18_REG_1,
 786   MOD_0F18_REG_2,
 787   MOD_0F18_REG_3,
 788   MOD_0F18_REG_4,
 789   MOD_0F18_REG_5,
 790   MOD_0F18_REG_6,
 791   MOD_0F18_REG_7,
 792   MOD_0F1A_PREFIX_0,
 793   MOD_0F1B_PREFIX_0,
 794   MOD_0F1B_PREFIX_1,
 795   MOD_0F1C_PREFIX_0,
 796   MOD_0F1E_PREFIX_1,
 797   MOD_0F24,
 798   MOD_0F26,
 799   MOD_0F2B_PREFIX_0,
 800   MOD_0F2B_PREFIX_1,
 801   MOD_0F2B_PREFIX_2,
 802   MOD_0F2B_PREFIX_3,
 803   MOD_0F50,
 804   MOD_0F71_REG_2,
 805   MOD_0F71_REG_4,
 806   MOD_0F71_REG_6,
 807   MOD_0F72_REG_2,
 808   MOD_0F72_REG_4,
 809   MOD_0F72_REG_6,
 810   MOD_0F73_REG_2,
 811   MOD_0F73_REG_3,
 812   MOD_0F73_REG_6,
 813   MOD_0F73_REG_7,
 814   MOD_0FAE_REG_0,
 815   MOD_0FAE_REG_1,
 816   MOD_0FAE_REG_2,
 817   MOD_0FAE_REG_3,
 818   MOD_0FAE_REG_4,
 819   MOD_0FAE_REG_5,
 820   MOD_0FAE_REG_6,
 821   MOD_0FAE_REG_7,
 822   MOD_0FB2,
 823   MOD_0FB4,
 824   MOD_0FB5,
 825   MOD_0FC3,
 826   MOD_0FC7_REG_3,
 827   MOD_0FC7_REG_4,
 828   MOD_0FC7_REG_5,
 829   MOD_0FC7_REG_6,
 830   MOD_0FC7_REG_7,
 831   MOD_0FD7,
 832   MOD_0FE7_PREFIX_2,
 833   MOD_0FF0_PREFIX_3,
 834   MOD_0F382A_PREFIX_2,
 835   MOD_0F38F5_PREFIX_2,
 836   MOD_0F38F6_PREFIX_0,
 837   MOD_0F38F8_PREFIX_1,
 838   MOD_0F38F8_PREFIX_2,
 839   MOD_0F38F8_PREFIX_3,
 840   MOD_0F38F9_PREFIX_0,
 841   MOD_62_32BIT,
 842   MOD_C4_32BIT,
 843   MOD_C5_32BIT,
 844   MOD_VEX_0F12_PREFIX_0,
 845   MOD_VEX_0F13,
 846   MOD_VEX_0F16_PREFIX_0,
 847   MOD_VEX_0F17,
 848   MOD_VEX_0F2B,
 849   MOD_VEX_W_0_0F41_P_0_LEN_1,
 850   MOD_VEX_W_1_0F41_P_0_LEN_1,
 851   MOD_VEX_W_0_0F41_P_2_LEN_1,
 852   MOD_VEX_W_1_0F41_P_2_LEN_1,
 853   MOD_VEX_W_0_0F42_P_0_LEN_1,
 854   MOD_VEX_W_1_0F42_P_0_LEN_1,
 855   MOD_VEX_W_0_0F42_P_2_LEN_1,
 856   MOD_VEX_W_1_0F42_P_2_LEN_1,
 857   MOD_VEX_W_0_0F44_P_0_LEN_1,
 858   MOD_VEX_W_1_0F44_P_0_LEN_1,
 859   MOD_VEX_W_0_0F44_P_2_LEN_1,
 860   MOD_VEX_W_1_0F44_P_2_LEN_1,
 861   MOD_VEX_W_0_0F45_P_0_LEN_1,
 862   MOD_VEX_W_1_0F45_P_0_LEN_1,
 863   MOD_VEX_W_0_0F45_P_2_LEN_1,
 864   MOD_VEX_W_1_0F45_P_2_LEN_1,
 865   MOD_VEX_W_0_0F46_P_0_LEN_1,
 866   MOD_VEX_W_1_0F46_P_0_LEN_1,
 867   MOD_VEX_W_0_0F46_P_2_LEN_1,
 868   MOD_VEX_W_1_0F46_P_2_LEN_1,
 869   MOD_VEX_W_0_0F47_P_0_LEN_1,
 870   MOD_VEX_W_1_0F47_P_0_LEN_1,
 871   MOD_VEX_W_0_0F47_P_2_LEN_1,
 872   MOD_VEX_W_1_0F47_P_2_LEN_1,
 873   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 874   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 875   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 876   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 877   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 878   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 879   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 880   MOD_VEX_0F50,
 881   MOD_VEX_0F71_REG_2,
 882   MOD_VEX_0F71_REG_4,
 883   MOD_VEX_0F71_REG_6,
 884   MOD_VEX_0F72_REG_2,
 885   MOD_VEX_0F72_REG_4,
 886   MOD_VEX_0F72_REG_6,
 887   MOD_VEX_0F73_REG_2,
 888   MOD_VEX_0F73_REG_3,
 889   MOD_VEX_0F73_REG_6,
 890   MOD_VEX_0F73_REG_7,
 891   MOD_VEX_W_0_0F91_P_0_LEN_0,
 892   MOD_VEX_W_1_0F91_P_0_LEN_0,
 893   MOD_VEX_W_0_0F91_P_2_LEN_0,
 894   MOD_VEX_W_1_0F91_P_2_LEN_0,
 895   MOD_VEX_W_0_0F92_P_0_LEN_0,
 896   MOD_VEX_W_0_0F92_P_2_LEN_0,
 897   MOD_VEX_0F92_P_3_LEN_0,
 898   MOD_VEX_W_0_0F93_P_0_LEN_0,
 899   MOD_VEX_W_0_0F93_P_2_LEN_0,
 900   MOD_VEX_0F93_P_3_LEN_0,
 901   MOD_VEX_W_0_0F98_P_0_LEN_0,
 902   MOD_VEX_W_1_0F98_P_0_LEN_0,
 903   MOD_VEX_W_0_0F98_P_2_LEN_0,
 904   MOD_VEX_W_1_0F98_P_2_LEN_0,
 905   MOD_VEX_W_0_0F99_P_0_LEN_0,
 906   MOD_VEX_W_1_0F99_P_0_LEN_0,
 907   MOD_VEX_W_0_0F99_P_2_LEN_0,
 908   MOD_VEX_W_1_0F99_P_2_LEN_0,
 909   MOD_VEX_0FAE_REG_2,
 910   MOD_VEX_0FAE_REG_3,
 911   MOD_VEX_0FD7_PREFIX_2,
 912   MOD_VEX_0FE7_PREFIX_2,
 913   MOD_VEX_0FF0_PREFIX_3,
 914   MOD_VEX_0F381A_PREFIX_2,
 915   MOD_VEX_0F382A_PREFIX_2,
 916   MOD_VEX_0F382C_PREFIX_2,
 917   MOD_VEX_0F382D_PREFIX_2,
 918   MOD_VEX_0F382E_PREFIX_2,
 919   MOD_VEX_0F382F_PREFIX_2,
 920   MOD_VEX_0F385A_PREFIX_2,
 921   MOD_VEX_0F388C_PREFIX_2,
 922   MOD_VEX_0F388E_PREFIX_2,
 923   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 924   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 925   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 926   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 927   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 928   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 929   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 930   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 931
 932   MOD_EVEX_0F12_PREFIX_0,
 933   MOD_EVEX_0F16_PREFIX_0,
 934   MOD_EVEX_0F38C6_REG_1,
 935   MOD_EVEX_0F38C6_REG_2,
 936   MOD_EVEX_0F38C6_REG_5,
 937   MOD_EVEX_0F38C6_REG_6,
 938   MOD_EVEX_0F38C7_REG_1,
 939   MOD_EVEX_0F38C7_REG_2,
 940   MOD_EVEX_0F38C7_REG_5,
 941   MOD_EVEX_0F38C7_REG_6
 942 };
 943
 944 enum
 945 {
 946   RM_C6_REG_7 = 0,
 947   RM_C7_REG_7,
 948   RM_0F01_REG_0,
 949   RM_0F01_REG_1,
 950   RM_0F01_REG_2,
 951   RM_0F01_REG_3,
 952   RM_0F01_REG_5_MOD_3,
 953   RM_0F01_REG_7_MOD_3,
 954   RM_0F1E_P_1_MOD_3_REG_7,
 955   RM_0FAE_REG_6_MOD_3_P_0,
 956   RM_0FAE_REG_7_MOD_3,
 957 };
 958
 959 enum
 960 {
 961   PREFIX_90 = 0,
 962   PREFIX_0F01_REG_3_RM_1,
 963   PREFIX_0F01_REG_5_MOD_0,
 964   PREFIX_0F01_REG_5_MOD_3_RM_0,
 965   PREFIX_0F01_REG_5_MOD_3_RM_1,
 966   PREFIX_0F01_REG_5_MOD_3_RM_2,
 967   PREFIX_0F01_REG_7_MOD_3_RM_2,
 968   PREFIX_0F01_REG_7_MOD_3_RM_3,
 969   PREFIX_0F09,
 970   PREFIX_0F10,
 971   PREFIX_0F11,
 972   PREFIX_0F12,
 973   PREFIX_0F16,
 974   PREFIX_0F1A,
 975   PREFIX_0F1B,
 976   PREFIX_0F1C,
 977   PREFIX_0F1E,
 978   PREFIX_0F2A,
 979   PREFIX_0F2B,
 980   PREFIX_0F2C,
 981   PREFIX_0F2D,
 982   PREFIX_0F2E,
 983   PREFIX_0F2F,
 984   PREFIX_0F51,
 985   PREFIX_0F52,
 986   PREFIX_0F53,
 987   PREFIX_0F58,
 988   PREFIX_0F59,
 989   PREFIX_0F5A,
 990   PREFIX_0F5B,
 991   PREFIX_0F5C,
 992   PREFIX_0F5D,
 993   PREFIX_0F5E,
 994   PREFIX_0F5F,
 995   PREFIX_0F60,
 996   PREFIX_0F61,
 997   PREFIX_0F62,
 998   PREFIX_0F6C,
 999   PREFIX_0F6D,
1000   PREFIX_0F6F,
1001   PREFIX_0F70,
1002   PREFIX_0F73_REG_3,
1003   PREFIX_0F73_REG_7,
1004   PREFIX_0F78,
1005   PREFIX_0F79,
1006   PREFIX_0F7C,
1007   PREFIX_0F7D,
1008   PREFIX_0F7E,
1009   PREFIX_0F7F,
1010   PREFIX_0FAE_REG_0_MOD_3,
1011   PREFIX_0FAE_REG_1_MOD_3,
1012   PREFIX_0FAE_REG_2_MOD_3,
1013   PREFIX_0FAE_REG_3_MOD_3,
1014   PREFIX_0FAE_REG_4_MOD_0,
1015   PREFIX_0FAE_REG_4_MOD_3,
1016   PREFIX_0FAE_REG_5_MOD_0,
1017   PREFIX_0FAE_REG_5_MOD_3,
1018   PREFIX_0FAE_REG_6_MOD_0,
1019   PREFIX_0FAE_REG_6_MOD_3,
1020   PREFIX_0FAE_REG_7_MOD_0,
1021   PREFIX_0FB8,
1022   PREFIX_0FBC,
1023   PREFIX_0FBD,
1024   PREFIX_0FC2,
1025   PREFIX_0FC3_MOD_0,
1026   PREFIX_0FC7_REG_6_MOD_0,
1027   PREFIX_0FC7_REG_6_MOD_3,
1028   PREFIX_0FC7_REG_7_MOD_3,
1029   PREFIX_0FD0,
1030   PREFIX_0FD6,
1031   PREFIX_0FE6,
1032   PREFIX_0FE7,
1033   PREFIX_0FF0,
1034   PREFIX_0FF7,
1035   PREFIX_0F3810,
1036   PREFIX_0F3814,
1037   PREFIX_0F3815,
1038   PREFIX_0F3817,
1039   PREFIX_0F3820,
1040   PREFIX_0F3821,
1041   PREFIX_0F3822,
1042   PREFIX_0F3823,
1043   PREFIX_0F3824,
1044   PREFIX_0F3825,
1045   PREFIX_0F3828,
1046   PREFIX_0F3829,
1047   PREFIX_0F382A,
1048   PREFIX_0F382B,
1049   PREFIX_0F3830,
1050   PREFIX_0F3831,
1051   PREFIX_0F3832,
1052   PREFIX_0F3833,
1053   PREFIX_0F3834,
1054   PREFIX_0F3835,
1055   PREFIX_0F3837,
1056   PREFIX_0F3838,
1057   PREFIX_0F3839,
1058   PREFIX_0F383A,
1059   PREFIX_0F383B,
1060   PREFIX_0F383C,
1061   PREFIX_0F383D,
1062   PREFIX_0F383E,
1063   PREFIX_0F383F,
1064   PREFIX_0F3840,
1065   PREFIX_0F3841,
1066   PREFIX_0F3880,
1067   PREFIX_0F3881,
1068   PREFIX_0F3882,
1069   PREFIX_0F38C8,
1070   PREFIX_0F38C9,
1071   PREFIX_0F38CA,
1072   PREFIX_0F38CB,
1073   PREFIX_0F38CC,
1074   PREFIX_0F38CD,
1075   PREFIX_0F38CF,
1076   PREFIX_0F38DB,
1077   PREFIX_0F38DC,
1078   PREFIX_0F38DD,
1079   PREFIX_0F38DE,
1080   PREFIX_0F38DF,
1081   PREFIX_0F38F0,
1082   PREFIX_0F38F1,
1083   PREFIX_0F38F5,
1084   PREFIX_0F38F6,
1085   PREFIX_0F38F8,
1086   PREFIX_0F38F9,
1087   PREFIX_0F3A08,
1088   PREFIX_0F3A09,
1089   PREFIX_0F3A0A,
1090   PREFIX_0F3A0B,
1091   PREFIX_0F3A0C,
1092   PREFIX_0F3A0D,
1093   PREFIX_0F3A0E,
1094   PREFIX_0F3A14,
1095   PREFIX_0F3A15,
1096   PREFIX_0F3A16,
1097   PREFIX_0F3A17,
1098   PREFIX_0F3A20,
1099   PREFIX_0F3A21,
1100   PREFIX_0F3A22,
1101   PREFIX_0F3A40,
1102   PREFIX_0F3A41,
1103   PREFIX_0F3A42,
1104   PREFIX_0F3A44,
1105   PREFIX_0F3A60,
1106   PREFIX_0F3A61,
1107   PREFIX_0F3A62,
1108   PREFIX_0F3A63,
1109   PREFIX_0F3ACC,
1110   PREFIX_0F3ACE,
1111   PREFIX_0F3ACF,
1112   PREFIX_0F3ADF,
1113   PREFIX_VEX_0F10,
1114   PREFIX_VEX_0F11,
1115   PREFIX_VEX_0F12,
1116   PREFIX_VEX_0F16,
1117   PREFIX_VEX_0F2A,
1118   PREFIX_VEX_0F2C,
1119   PREFIX_VEX_0F2D,
1120   PREFIX_VEX_0F2E,
1121   PREFIX_VEX_0F2F,
1122   PREFIX_VEX_0F41,
1123   PREFIX_VEX_0F42,
1124   PREFIX_VEX_0F44,
1125   PREFIX_VEX_0F45,
1126   PREFIX_VEX_0F46,
1127   PREFIX_VEX_0F47,
1128   PREFIX_VEX_0F4A,
1129   PREFIX_VEX_0F4B,
1130   PREFIX_VEX_0F51,
1131   PREFIX_VEX_0F52,
1132   PREFIX_VEX_0F53,
1133   PREFIX_VEX_0F58,
1134   PREFIX_VEX_0F59,
1135   PREFIX_VEX_0F5A,
1136   PREFIX_VEX_0F5B,
1137   PREFIX_VEX_0F5C,
1138   PREFIX_VEX_0F5D,
1139   PREFIX_VEX_0F5E,
1140   PREFIX_VEX_0F5F,
1141   PREFIX_VEX_0F60,
1142   PREFIX_VEX_0F61,
1143   PREFIX_VEX_0F62,
1144   PREFIX_VEX_0F63,
1145   PREFIX_VEX_0F64,
1146   PREFIX_VEX_0F65,
1147   PREFIX_VEX_0F66,
1148   PREFIX_VEX_0F67,
1149   PREFIX_VEX_0F68,
1150   PREFIX_VEX_0F69,
1151   PREFIX_VEX_0F6A,
1152   PREFIX_VEX_0F6B,
1153   PREFIX_VEX_0F6C,
1154   PREFIX_VEX_0F6D,
1155   PREFIX_VEX_0F6E,
1156   PREFIX_VEX_0F6F,
1157   PREFIX_VEX_0F70,
1158   PREFIX_VEX_0F71_REG_2,
1159   PREFIX_VEX_0F71_REG_4,
1160   PREFIX_VEX_0F71_REG_6,
1161   PREFIX_VEX_0F72_REG_2,
1162   PREFIX_VEX_0F72_REG_4,
1163   PREFIX_VEX_0F72_REG_6,
1164   PREFIX_VEX_0F73_REG_2,
1165   PREFIX_VEX_0F73_REG_3,
1166   PREFIX_VEX_0F73_REG_6,
1167   PREFIX_VEX_0F73_REG_7,
1168   PREFIX_VEX_0F74,
1169   PREFIX_VEX_0F75,
1170   PREFIX_VEX_0F76,
1171   PREFIX_VEX_0F77,
1172   PREFIX_VEX_0F7C,
1173   PREFIX_VEX_0F7D,
1174   PREFIX_VEX_0F7E,
1175   PREFIX_VEX_0F7F,
1176   PREFIX_VEX_0F90,
1177   PREFIX_VEX_0F91,
1178   PREFIX_VEX_0F92,
1179   PREFIX_VEX_0F93,
1180   PREFIX_VEX_0F98,
1181   PREFIX_VEX_0F99,
1182   PREFIX_VEX_0FC2,
1183   PREFIX_VEX_0FC4,
1184   PREFIX_VEX_0FC5,
1185   PREFIX_VEX_0FD0,
1186   PREFIX_VEX_0FD1,
1187   PREFIX_VEX_0FD2,
1188   PREFIX_VEX_0FD3,
1189   PREFIX_VEX_0FD4,
1190   PREFIX_VEX_0FD5,
1191   PREFIX_VEX_0FD6,
1192   PREFIX_VEX_0FD7,
1193   PREFIX_VEX_0FD8,
1194   PREFIX_VEX_0FD9,
1195   PREFIX_VEX_0FDA,
1196   PREFIX_VEX_0FDB,
1197   PREFIX_VEX_0FDC,
1198   PREFIX_VEX_0FDD,
1199   PREFIX_VEX_0FDE,
1200   PREFIX_VEX_0FDF,
1201   PREFIX_VEX_0FE0,
1202   PREFIX_VEX_0FE1,
1203   PREFIX_VEX_0FE2,
1204   PREFIX_VEX_0FE3,
1205   PREFIX_VEX_0FE4,
1206   PREFIX_VEX_0FE5,
1207   PREFIX_VEX_0FE6,
1208   PREFIX_VEX_0FE7,
1209   PREFIX_VEX_0FE8,
1210   PREFIX_VEX_0FE9,
1211   PREFIX_VEX_0FEA,
1212   PREFIX_VEX_0FEB,
1213   PREFIX_VEX_0FEC,
1214   PREFIX_VEX_0FED,
1215   PREFIX_VEX_0FEE,
1216   PREFIX_VEX_0FEF,
1217   PREFIX_VEX_0FF0,
1218   PREFIX_VEX_0FF1,
1219   PREFIX_VEX_0FF2,
1220   PREFIX_VEX_0FF3,
1221   PREFIX_VEX_0FF4,
1222   PREFIX_VEX_0FF5,
1223   PREFIX_VEX_0FF6,
1224   PREFIX_VEX_0FF7,
1225   PREFIX_VEX_0FF8,
1226   PREFIX_VEX_0FF9,
1227   PREFIX_VEX_0FFA,
1228   PREFIX_VEX_0FFB,
1229   PREFIX_VEX_0FFC,
1230   PREFIX_VEX_0FFD,
1231   PREFIX_VEX_0FFE,
1232   PREFIX_VEX_0F3800,
1233   PREFIX_VEX_0F3801,
1234   PREFIX_VEX_0F3802,
1235   PREFIX_VEX_0F3803,
1236   PREFIX_VEX_0F3804,
1237   PREFIX_VEX_0F3805,
1238   PREFIX_VEX_0F3806,
1239   PREFIX_VEX_0F3807,
1240   PREFIX_VEX_0F3808,
1241   PREFIX_VEX_0F3809,
1242   PREFIX_VEX_0F380A,
1243   PREFIX_VEX_0F380B,
1244   PREFIX_VEX_0F380C,
1245   PREFIX_VEX_0F380D,
1246   PREFIX_VEX_0F380E,
1247   PREFIX_VEX_0F380F,
1248   PREFIX_VEX_0F3813,
1249   PREFIX_VEX_0F3816,
1250   PREFIX_VEX_0F3817,
1251   PREFIX_VEX_0F3818,
1252   PREFIX_VEX_0F3819,
1253   PREFIX_VEX_0F381A,
1254   PREFIX_VEX_0F381C,
1255   PREFIX_VEX_0F381D,
1256   PREFIX_VEX_0F381E,
1257   PREFIX_VEX_0F3820,
1258   PREFIX_VEX_0F3821,
1259   PREFIX_VEX_0F3822,
1260   PREFIX_VEX_0F3823,
1261   PREFIX_VEX_0F3824,
1262   PREFIX_VEX_0F3825,
1263   PREFIX_VEX_0F3828,
1264   PREFIX_VEX_0F3829,
1265   PREFIX_VEX_0F382A,
1266   PREFIX_VEX_0F382B,
1267   PREFIX_VEX_0F382C,
1268   PREFIX_VEX_0F382D,
1269   PREFIX_VEX_0F382E,
1270   PREFIX_VEX_0F382F,
1271   PREFIX_VEX_0F3830,
1272   PREFIX_VEX_0F3831,
1273   PREFIX_VEX_0F3832,
1274   PREFIX_VEX_0F3833,
1275   PREFIX_VEX_0F3834,
1276   PREFIX_VEX_0F3835,
1277   PREFIX_VEX_0F3836,
1278   PREFIX_VEX_0F3837,
1279   PREFIX_VEX_0F3838,
1280   PREFIX_VEX_0F3839,
1281   PREFIX_VEX_0F383A,
1282   PREFIX_VEX_0F383B,
1283   PREFIX_VEX_0F383C,
1284   PREFIX_VEX_0F383D,
1285   PREFIX_VEX_0F383E,
1286   PREFIX_VEX_0F383F,
1287   PREFIX_VEX_0F3840,
1288   PREFIX_VEX_0F3841,
1289   PREFIX_VEX_0F3845,
1290   PREFIX_VEX_0F3846,
1291   PREFIX_VEX_0F3847,
1292   PREFIX_VEX_0F3858,
1293   PREFIX_VEX_0F3859,
1294   PREFIX_VEX_0F385A,
1295   PREFIX_VEX_0F3878,
1296   PREFIX_VEX_0F3879,
1297   PREFIX_VEX_0F388C,
1298   PREFIX_VEX_0F388E,
1299   PREFIX_VEX_0F3890,
1300   PREFIX_VEX_0F3891,
1301   PREFIX_VEX_0F3892,
1302   PREFIX_VEX_0F3893,
1303   PREFIX_VEX_0F3896,
1304   PREFIX_VEX_0F3897,
1305   PREFIX_VEX_0F3898,
1306   PREFIX_VEX_0F3899,
1307   PREFIX_VEX_0F389A,
1308   PREFIX_VEX_0F389B,
1309   PREFIX_VEX_0F389C,
1310   PREFIX_VEX_0F389D,
1311   PREFIX_VEX_0F389E,
1312   PREFIX_VEX_0F389F,
1313   PREFIX_VEX_0F38A6,
1314   PREFIX_VEX_0F38A7,
1315   PREFIX_VEX_0F38A8,
1316   PREFIX_VEX_0F38A9,
1317   PREFIX_VEX_0F38AA,
1318   PREFIX_VEX_0F38AB,
1319   PREFIX_VEX_0F38AC,
1320   PREFIX_VEX_0F38AD,
1321   PREFIX_VEX_0F38AE,
1322   PREFIX_VEX_0F38AF,
1323   PREFIX_VEX_0F38B6,
1324   PREFIX_VEX_0F38B7,
1325   PREFIX_VEX_0F38B8,
1326   PREFIX_VEX_0F38B9,
1327   PREFIX_VEX_0F38BA,
1328   PREFIX_VEX_0F38BB,
1329   PREFIX_VEX_0F38BC,
1330   PREFIX_VEX_0F38BD,
1331   PREFIX_VEX_0F38BE,
1332   PREFIX_VEX_0F38BF,
1333   PREFIX_VEX_0F38CF,
1334   PREFIX_VEX_0F38DB,
1335   PREFIX_VEX_0F38DC,
1336   PREFIX_VEX_0F38DD,
1337   PREFIX_VEX_0F38DE,
1338   PREFIX_VEX_0F38DF,
1339   PREFIX_VEX_0F38F2,
1340   PREFIX_VEX_0F38F3_REG_1,
1341   PREFIX_VEX_0F38F3_REG_2,
1342   PREFIX_VEX_0F38F3_REG_3,
1343   PREFIX_VEX_0F38F5,
1344   PREFIX_VEX_0F38F6,
1345   PREFIX_VEX_0F38F7,
1346   PREFIX_VEX_0F3A00,
1347   PREFIX_VEX_0F3A01,
1348   PREFIX_VEX_0F3A02,
1349   PREFIX_VEX_0F3A04,
1350   PREFIX_VEX_0F3A05,
1351   PREFIX_VEX_0F3A06,
1352   PREFIX_VEX_0F3A08,
1353   PREFIX_VEX_0F3A09,
1354   PREFIX_VEX_0F3A0A,
1355   PREFIX_VEX_0F3A0B,
1356   PREFIX_VEX_0F3A0C,
1357   PREFIX_VEX_0F3A0D,
1358   PREFIX_VEX_0F3A0E,
1359   PREFIX_VEX_0F3A0F,
1360   PREFIX_VEX_0F3A14,
1361   PREFIX_VEX_0F3A15,
1362   PREFIX_VEX_0F3A16,
1363   PREFIX_VEX_0F3A17,
1364   PREFIX_VEX_0F3A18,
1365   PREFIX_VEX_0F3A19,
1366   PREFIX_VEX_0F3A1D,
1367   PREFIX_VEX_0F3A20,
1368   PREFIX_VEX_0F3A21,
1369   PREFIX_VEX_0F3A22,
1370   PREFIX_VEX_0F3A30,
1371   PREFIX_VEX_0F3A31,
1372   PREFIX_VEX_0F3A32,
1373   PREFIX_VEX_0F3A33,
1374   PREFIX_VEX_0F3A38,
1375   PREFIX_VEX_0F3A39,
1376   PREFIX_VEX_0F3A40,
1377   PREFIX_VEX_0F3A41,
1378   PREFIX_VEX_0F3A42,
1379   PREFIX_VEX_0F3A44,
1380   PREFIX_VEX_0F3A46,
1381   PREFIX_VEX_0F3A48,
1382   PREFIX_VEX_0F3A49,
1383   PREFIX_VEX_0F3A4A,
1384   PREFIX_VEX_0F3A4B,
1385   PREFIX_VEX_0F3A4C,
1386   PREFIX_VEX_0F3A5C,
1387   PREFIX_VEX_0F3A5D,
1388   PREFIX_VEX_0F3A5E,
1389   PREFIX_VEX_0F3A5F,
1390   PREFIX_VEX_0F3A60,
1391   PREFIX_VEX_0F3A61,
1392   PREFIX_VEX_0F3A62,
1393   PREFIX_VEX_0F3A63,
1394   PREFIX_VEX_0F3A68,
1395   PREFIX_VEX_0F3A69,
1396   PREFIX_VEX_0F3A6A,
1397   PREFIX_VEX_0F3A6B,
1398   PREFIX_VEX_0F3A6C,
1399   PREFIX_VEX_0F3A6D,
1400   PREFIX_VEX_0F3A6E,
1401   PREFIX_VEX_0F3A6F,
1402   PREFIX_VEX_0F3A78,
1403   PREFIX_VEX_0F3A79,
1404   PREFIX_VEX_0F3A7A,
1405   PREFIX_VEX_0F3A7B,
1406   PREFIX_VEX_0F3A7C,
1407   PREFIX_VEX_0F3A7D,
1408   PREFIX_VEX_0F3A7E,
1409   PREFIX_VEX_0F3A7F,
1410   PREFIX_VEX_0F3ACE,
1411   PREFIX_VEX_0F3ACF,
1412   PREFIX_VEX_0F3ADF,
1413   PREFIX_VEX_0F3AF0,
1414
1415   PREFIX_EVEX_0F10,
1416   PREFIX_EVEX_0F11,
1417   PREFIX_EVEX_0F12,
1418   PREFIX_EVEX_0F13,
1419   PREFIX_EVEX_0F14,
1420   PREFIX_EVEX_0F15,
1421   PREFIX_EVEX_0F16,
1422   PREFIX_EVEX_0F17,
1423   PREFIX_EVEX_0F28,
1424   PREFIX_EVEX_0F29,
1425   PREFIX_EVEX_0F2A,
1426   PREFIX_EVEX_0F2B,
1427   PREFIX_EVEX_0F2C,
1428   PREFIX_EVEX_0F2D,
1429   PREFIX_EVEX_0F2E,
1430   PREFIX_EVEX_0F2F,
1431   PREFIX_EVEX_0F51,
1432   PREFIX_EVEX_0F54,
1433   PREFIX_EVEX_0F55,
1434   PREFIX_EVEX_0F56,
1435   PREFIX_EVEX_0F57,
1436   PREFIX_EVEX_0F58,
1437   PREFIX_EVEX_0F59,
1438   PREFIX_EVEX_0F5A,
1439   PREFIX_EVEX_0F5B,
1440   PREFIX_EVEX_0F5C,
1441   PREFIX_EVEX_0F5D,
1442   PREFIX_EVEX_0F5E,
1443   PREFIX_EVEX_0F5F,
1444   PREFIX_EVEX_0F60,
1445   PREFIX_EVEX_0F61,
1446   PREFIX_EVEX_0F62,
1447   PREFIX_EVEX_0F63,
1448   PREFIX_EVEX_0F64,
1449   PREFIX_EVEX_0F65,
1450   PREFIX_EVEX_0F66,
1451   PREFIX_EVEX_0F67,
1452   PREFIX_EVEX_0F68,
1453   PREFIX_EVEX_0F69,
1454   PREFIX_EVEX_0F6A,
1455   PREFIX_EVEX_0F6B,
1456   PREFIX_EVEX_0F6C,
1457   PREFIX_EVEX_0F6D,
1458   PREFIX_EVEX_0F6E,
1459   PREFIX_EVEX_0F6F,
1460   PREFIX_EVEX_0F70,
1461   PREFIX_EVEX_0F71_REG_2,
1462   PREFIX_EVEX_0F71_REG_4,
1463   PREFIX_EVEX_0F71_REG_6,
1464   PREFIX_EVEX_0F72_REG_0,
1465   PREFIX_EVEX_0F72_REG_1,
1466   PREFIX_EVEX_0F72_REG_2,
1467   PREFIX_EVEX_0F72_REG_4,
1468   PREFIX_EVEX_0F72_REG_6,
1469   PREFIX_EVEX_0F73_REG_2,
1470   PREFIX_EVEX_0F73_REG_3,
1471   PREFIX_EVEX_0F73_REG_6,
1472   PREFIX_EVEX_0F73_REG_7,
1473   PREFIX_EVEX_0F74,
1474   PREFIX_EVEX_0F75,
1475   PREFIX_EVEX_0F76,
1476   PREFIX_EVEX_0F78,
1477   PREFIX_EVEX_0F79,
1478   PREFIX_EVEX_0F7A,
1479   PREFIX_EVEX_0F7B,
1480   PREFIX_EVEX_0F7E,
1481   PREFIX_EVEX_0F7F,
1482   PREFIX_EVEX_0FC2,
1483   PREFIX_EVEX_0FC4,
1484   PREFIX_EVEX_0FC5,
1485   PREFIX_EVEX_0FC6,
1486   PREFIX_EVEX_0FD1,
1487   PREFIX_EVEX_0FD2,
1488   PREFIX_EVEX_0FD3,
1489   PREFIX_EVEX_0FD4,
1490   PREFIX_EVEX_0FD5,
1491   PREFIX_EVEX_0FD6,
1492   PREFIX_EVEX_0FD8,
1493   PREFIX_EVEX_0FD9,
1494   PREFIX_EVEX_0FDA,
1495   PREFIX_EVEX_0FDB,
1496   PREFIX_EVEX_0FDC,
1497   PREFIX_EVEX_0FDD,
1498   PREFIX_EVEX_0FDE,
1499   PREFIX_EVEX_0FDF,
1500   PREFIX_EVEX_0FE0,
1501   PREFIX_EVEX_0FE1,
1502   PREFIX_EVEX_0FE2,
1503   PREFIX_EVEX_0FE3,
1504   PREFIX_EVEX_0FE4,
1505   PREFIX_EVEX_0FE5,
1506   PREFIX_EVEX_0FE6,
1507   PREFIX_EVEX_0FE7,
1508   PREFIX_EVEX_0FE8,
1509   PREFIX_EVEX_0FE9,
1510   PREFIX_EVEX_0FEA,
1511   PREFIX_EVEX_0FEB,
1512   PREFIX_EVEX_0FEC,
1513   PREFIX_EVEX_0FED,
1514   PREFIX_EVEX_0FEE,
1515   PREFIX_EVEX_0FEF,
1516   PREFIX_EVEX_0FF1,
1517   PREFIX_EVEX_0FF2,
1518   PREFIX_EVEX_0FF3,
1519   PREFIX_EVEX_0FF4,
1520   PREFIX_EVEX_0FF5,
1521   PREFIX_EVEX_0FF6,
1522   PREFIX_EVEX_0FF8,
1523   PREFIX_EVEX_0FF9,
1524   PREFIX_EVEX_0FFA,
1525   PREFIX_EVEX_0FFB,
1526   PREFIX_EVEX_0FFC,
1527   PREFIX_EVEX_0FFD,
1528   PREFIX_EVEX_0FFE,
1529   PREFIX_EVEX_0F3800,
1530   PREFIX_EVEX_0F3804,
1531   PREFIX_EVEX_0F380B,
1532   PREFIX_EVEX_0F380C,
1533   PREFIX_EVEX_0F380D,
1534   PREFIX_EVEX_0F3810,
1535   PREFIX_EVEX_0F3811,
1536   PREFIX_EVEX_0F3812,
1537   PREFIX_EVEX_0F3813,
1538   PREFIX_EVEX_0F3814,
1539   PREFIX_EVEX_0F3815,
1540   PREFIX_EVEX_0F3816,
1541   PREFIX_EVEX_0F3818,
1542   PREFIX_EVEX_0F3819,
1543   PREFIX_EVEX_0F381A,
1544   PREFIX_EVEX_0F381B,
1545   PREFIX_EVEX_0F381C,
1546   PREFIX_EVEX_0F381D,
1547   PREFIX_EVEX_0F381E,
1548   PREFIX_EVEX_0F381F,
1549   PREFIX_EVEX_0F3820,
1550   PREFIX_EVEX_0F3821,
1551   PREFIX_EVEX_0F3822,
1552   PREFIX_EVEX_0F3823,
1553   PREFIX_EVEX_0F3824,
1554   PREFIX_EVEX_0F3825,
1555   PREFIX_EVEX_0F3826,
1556   PREFIX_EVEX_0F3827,
1557   PREFIX_EVEX_0F3828,
1558   PREFIX_EVEX_0F3829,
1559   PREFIX_EVEX_0F382A,
1560   PREFIX_EVEX_0F382B,
1561   PREFIX_EVEX_0F382C,
1562   PREFIX_EVEX_0F382D,
1563   PREFIX_EVEX_0F3830,
1564   PREFIX_EVEX_0F3831,
1565   PREFIX_EVEX_0F3832,
1566   PREFIX_EVEX_0F3833,
1567   PREFIX_EVEX_0F3834,
1568   PREFIX_EVEX_0F3835,
1569   PREFIX_EVEX_0F3836,
1570   PREFIX_EVEX_0F3837,
1571   PREFIX_EVEX_0F3838,
1572   PREFIX_EVEX_0F3839,
1573   PREFIX_EVEX_0F383A,
1574   PREFIX_EVEX_0F383B,
1575   PREFIX_EVEX_0F383C,
1576   PREFIX_EVEX_0F383D,
1577   PREFIX_EVEX_0F383E,
1578   PREFIX_EVEX_0F383F,
1579   PREFIX_EVEX_0F3840,
1580   PREFIX_EVEX_0F3842,
1581   PREFIX_EVEX_0F3843,
1582   PREFIX_EVEX_0F3844,
1583   PREFIX_EVEX_0F3845,
1584   PREFIX_EVEX_0F3846,
1585   PREFIX_EVEX_0F3847,
1586   PREFIX_EVEX_0F384C,
1587   PREFIX_EVEX_0F384D,
1588   PREFIX_EVEX_0F384E,
1589   PREFIX_EVEX_0F384F,
1590   PREFIX_EVEX_0F3850,
1591   PREFIX_EVEX_0F3851,
1592   PREFIX_EVEX_0F3852,
1593   PREFIX_EVEX_0F3853,
1594   PREFIX_EVEX_0F3854,
1595   PREFIX_EVEX_0F3855,
1596   PREFIX_EVEX_0F3858,
1597   PREFIX_EVEX_0F3859,
1598   PREFIX_EVEX_0F385A,
1599   PREFIX_EVEX_0F385B,
1600   PREFIX_EVEX_0F3862,
1601   PREFIX_EVEX_0F3863,
1602   PREFIX_EVEX_0F3864,
1603   PREFIX_EVEX_0F3865,
1604   PREFIX_EVEX_0F3866,
1605   PREFIX_EVEX_0F3868,
1606   PREFIX_EVEX_0F3870,
1607   PREFIX_EVEX_0F3871,
1608   PREFIX_EVEX_0F3872,
1609   PREFIX_EVEX_0F3873,
1610   PREFIX_EVEX_0F3875,
1611   PREFIX_EVEX_0F3876,
1612   PREFIX_EVEX_0F3877,
1613   PREFIX_EVEX_0F3878,
1614   PREFIX_EVEX_0F3879,
1615   PREFIX_EVEX_0F387A,
1616   PREFIX_EVEX_0F387B,
1617   PREFIX_EVEX_0F387C,
1618   PREFIX_EVEX_0F387D,
1619   PREFIX_EVEX_0F387E,
1620   PREFIX_EVEX_0F387F,
1621   PREFIX_EVEX_0F3883,
1622   PREFIX_EVEX_0F3888,
1623   PREFIX_EVEX_0F3889,
1624   PREFIX_EVEX_0F388A,
1625   PREFIX_EVEX_0F388B,
1626   PREFIX_EVEX_0F388D,
1627   PREFIX_EVEX_0F388F,
1628   PREFIX_EVEX_0F3890,
1629   PREFIX_EVEX_0F3891,
1630   PREFIX_EVEX_0F3892,
1631   PREFIX_EVEX_0F3893,
1632   PREFIX_EVEX_0F3896,
1633   PREFIX_EVEX_0F3897,
1634   PREFIX_EVEX_0F3898,
1635   PREFIX_EVEX_0F3899,
1636   PREFIX_EVEX_0F389A,
1637   PREFIX_EVEX_0F389B,
1638   PREFIX_EVEX_0F389C,
1639   PREFIX_EVEX_0F389D,
1640   PREFIX_EVEX_0F389E,
1641   PREFIX_EVEX_0F389F,
1642   PREFIX_EVEX_0F38A0,
1643   PREFIX_EVEX_0F38A1,
1644   PREFIX_EVEX_0F38A2,
1645   PREFIX_EVEX_0F38A3,
1646   PREFIX_EVEX_0F38A6,
1647   PREFIX_EVEX_0F38A7,
1648   PREFIX_EVEX_0F38A8,
1649   PREFIX_EVEX_0F38A9,
1650   PREFIX_EVEX_0F38AA,
1651   PREFIX_EVEX_0F38AB,
1652   PREFIX_EVEX_0F38AC,
1653   PREFIX_EVEX_0F38AD,
1654   PREFIX_EVEX_0F38AE,
1655   PREFIX_EVEX_0F38AF,
1656   PREFIX_EVEX_0F38B4,
1657   PREFIX_EVEX_0F38B5,
1658   PREFIX_EVEX_0F38B6,
1659   PREFIX_EVEX_0F38B7,
1660   PREFIX_EVEX_0F38B8,
1661   PREFIX_EVEX_0F38B9,
1662   PREFIX_EVEX_0F38BA,
1663   PREFIX_EVEX_0F38BB,
1664   PREFIX_EVEX_0F38BC,
1665   PREFIX_EVEX_0F38BD,
1666   PREFIX_EVEX_0F38BE,
1667   PREFIX_EVEX_0F38BF,
1668   PREFIX_EVEX_0F38C4,
1669   PREFIX_EVEX_0F38C6_REG_1,
1670   PREFIX_EVEX_0F38C6_REG_2,
1671   PREFIX_EVEX_0F38C6_REG_5,
1672   PREFIX_EVEX_0F38C6_REG_6,
1673   PREFIX_EVEX_0F38C7_REG_1,
1674   PREFIX_EVEX_0F38C7_REG_2,
1675   PREFIX_EVEX_0F38C7_REG_5,
1676   PREFIX_EVEX_0F38C7_REG_6,
1677   PREFIX_EVEX_0F38C8,
1678   PREFIX_EVEX_0F38CA,
1679   PREFIX_EVEX_0F38CB,
1680   PREFIX_EVEX_0F38CC,
1681   PREFIX_EVEX_0F38CD,
1682   PREFIX_EVEX_0F38CF,
1683   PREFIX_EVEX_0F38DC,
1684   PREFIX_EVEX_0F38DD,
1685   PREFIX_EVEX_0F38DE,
1686   PREFIX_EVEX_0F38DF,
1687
1688   PREFIX_EVEX_0F3A00,
1689   PREFIX_EVEX_0F3A01,
1690   PREFIX_EVEX_0F3A03,
1691   PREFIX_EVEX_0F3A04,
1692   PREFIX_EVEX_0F3A05,
1693   PREFIX_EVEX_0F3A08,
1694   PREFIX_EVEX_0F3A09,
1695   PREFIX_EVEX_0F3A0A,
1696   PREFIX_EVEX_0F3A0B,
1697   PREFIX_EVEX_0F3A0F,
1698   PREFIX_EVEX_0F3A14,
1699   PREFIX_EVEX_0F3A15,
1700   PREFIX_EVEX_0F3A16,
1701   PREFIX_EVEX_0F3A17,
1702   PREFIX_EVEX_0F3A18,
1703   PREFIX_EVEX_0F3A19,
1704   PREFIX_EVEX_0F3A1A,
1705   PREFIX_EVEX_0F3A1B,
1706   PREFIX_EVEX_0F3A1D,
1707   PREFIX_EVEX_0F3A1E,
1708   PREFIX_EVEX_0F3A1F,
1709   PREFIX_EVEX_0F3A20,
1710   PREFIX_EVEX_0F3A21,
1711   PREFIX_EVEX_0F3A22,
1712   PREFIX_EVEX_0F3A23,
1713   PREFIX_EVEX_0F3A25,
1714   PREFIX_EVEX_0F3A26,
1715   PREFIX_EVEX_0F3A27,
1716   PREFIX_EVEX_0F3A38,
1717   PREFIX_EVEX_0F3A39,
1718   PREFIX_EVEX_0F3A3A,
1719   PREFIX_EVEX_0F3A3B,
1720   PREFIX_EVEX_0F3A3E,
1721   PREFIX_EVEX_0F3A3F,
1722   PREFIX_EVEX_0F3A42,
1723   PREFIX_EVEX_0F3A43,
1724   PREFIX_EVEX_0F3A44,
1725   PREFIX_EVEX_0F3A50,
1726   PREFIX_EVEX_0F3A51,
1727   PREFIX_EVEX_0F3A54,
1728   PREFIX_EVEX_0F3A55,
1729   PREFIX_EVEX_0F3A56,
1730   PREFIX_EVEX_0F3A57,
1731   PREFIX_EVEX_0F3A66,
1732   PREFIX_EVEX_0F3A67,
1733   PREFIX_EVEX_0F3A70,
1734   PREFIX_EVEX_0F3A71,
1735   PREFIX_EVEX_0F3A72,
1736   PREFIX_EVEX_0F3A73,
1737   PREFIX_EVEX_0F3ACE,
1738   PREFIX_EVEX_0F3ACF
1739 };
1740
1741 enum
1742 {
1743   X86_64_06 = 0,
1744   X86_64_07,
1745   X86_64_0E,
1746   X86_64_16,
1747   X86_64_17,
1748   X86_64_1E,
1749   X86_64_1F,
1750   X86_64_27,
1751   X86_64_2F,
1752   X86_64_37,
1753   X86_64_3F,
1754   X86_64_60,
1755   X86_64_61,
1756   X86_64_62,
1757   X86_64_63,
1758   X86_64_6D,
1759   X86_64_6F,
1760   X86_64_82,
1761   X86_64_9A,
1762   X86_64_C2,
1763   X86_64_C3,
1764   X86_64_C4,
1765   X86_64_C5,
1766   X86_64_CE,
1767   X86_64_D4,
1768   X86_64_D5,
1769   X86_64_E8,
1770   X86_64_E9,
1771   X86_64_EA,
1772   X86_64_0F01_REG_0,
1773   X86_64_0F01_REG_1,
1774   X86_64_0F01_REG_2,
1775   X86_64_0F01_REG_3
1776 };
1777
1778 enum
1779 {
1780   THREE_BYTE_0F38 = 0,
1781   THREE_BYTE_0F3A
1782 };
1783
1784 enum
1785 {
1786   XOP_08 = 0,
1787   XOP_09,
1788   XOP_0A
1789 };
1790
1791 enum
1792 {
1793   VEX_0F = 0,
1794   VEX_0F38,
1795   VEX_0F3A
1796 };
1797
1798 enum
1799 {
1800   EVEX_0F = 0,
1801   EVEX_0F38,
1802   EVEX_0F3A
1803 };
1804
1805 enum
1806 {
1807   VEX_LEN_0F12_P_0_M_0 = 0,
1808   VEX_LEN_0F12_P_0_M_1,
1809   VEX_LEN_0F12_P_2,
1810   VEX_LEN_0F13_M_0,
1811   VEX_LEN_0F16_P_0_M_0,
1812   VEX_LEN_0F16_P_0_M_1,
1813   VEX_LEN_0F16_P_2,
1814   VEX_LEN_0F17_M_0,
1815   VEX_LEN_0F41_P_0,
1816   VEX_LEN_0F41_P_2,
1817   VEX_LEN_0F42_P_0,
1818   VEX_LEN_0F42_P_2,
1819   VEX_LEN_0F44_P_0,
1820   VEX_LEN_0F44_P_2,
1821   VEX_LEN_0F45_P_0,
1822   VEX_LEN_0F45_P_2,
1823   VEX_LEN_0F46_P_0,
1824   VEX_LEN_0F46_P_2,
1825   VEX_LEN_0F47_P_0,
1826   VEX_LEN_0F47_P_2,
1827   VEX_LEN_0F4A_P_0,
1828   VEX_LEN_0F4A_P_2,
1829   VEX_LEN_0F4B_P_0,
1830   VEX_LEN_0F4B_P_2,
1831   VEX_LEN_0F6E_P_2,
1832   VEX_LEN_0F77_P_0,
1833   VEX_LEN_0F7E_P_1,
1834   VEX_LEN_0F7E_P_2,
1835   VEX_LEN_0F90_P_0,
1836   VEX_LEN_0F90_P_2,
1837   VEX_LEN_0F91_P_0,
1838   VEX_LEN_0F91_P_2,
1839   VEX_LEN_0F92_P_0,
1840   VEX_LEN_0F92_P_2,
1841   VEX_LEN_0F92_P_3,
1842   VEX_LEN_0F93_P_0,
1843   VEX_LEN_0F93_P_2,
1844   VEX_LEN_0F93_P_3,
1845   VEX_LEN_0F98_P_0,
1846   VEX_LEN_0F98_P_2,
1847   VEX_LEN_0F99_P_0,
1848   VEX_LEN_0F99_P_2,
1849   VEX_LEN_0FAE_R_2_M_0,
1850   VEX_LEN_0FAE_R_3_M_0,
1851   VEX_LEN_0FC4_P_2,
1852   VEX_LEN_0FC5_P_2,
1853   VEX_LEN_0FD6_P_2,
1854   VEX_LEN_0FF7_P_2,
1855   VEX_LEN_0F3816_P_2,
1856   VEX_LEN_0F3819_P_2,
1857   VEX_LEN_0F381A_P_2_M_0,
1858   VEX_LEN_0F3836_P_2,
1859   VEX_LEN_0F3841_P_2,
1860   VEX_LEN_0F385A_P_2_M_0,
1861   VEX_LEN_0F38DB_P_2,
1862   VEX_LEN_0F38F2_P_0,
1863   VEX_LEN_0F38F3_R_1_P_0,
1864   VEX_LEN_0F38F3_R_2_P_0,
1865   VEX_LEN_0F38F3_R_3_P_0,
1866   VEX_LEN_0F38F5_P_0,
1867   VEX_LEN_0F38F5_P_1,
1868   VEX_LEN_0F38F5_P_3,
1869   VEX_LEN_0F38F6_P_3,
1870   VEX_LEN_0F38F7_P_0,
1871   VEX_LEN_0F38F7_P_1,
1872   VEX_LEN_0F38F7_P_2,
1873   VEX_LEN_0F38F7_P_3,
1874   VEX_LEN_0F3A00_P_2,
1875   VEX_LEN_0F3A01_P_2,
1876   VEX_LEN_0F3A06_P_2,
1877   VEX_LEN_0F3A14_P_2,
1878   VEX_LEN_0F3A15_P_2,
1879   VEX_LEN_0F3A16_P_2,
1880   VEX_LEN_0F3A17_P_2,
1881   VEX_LEN_0F3A18_P_2,
1882   VEX_LEN_0F3A19_P_2,
1883   VEX_LEN_0F3A20_P_2,
1884   VEX_LEN_0F3A21_P_2,
1885   VEX_LEN_0F3A22_P_2,
1886   VEX_LEN_0F3A30_P_2,
1887   VEX_LEN_0F3A31_P_2,
1888   VEX_LEN_0F3A32_P_2,
1889   VEX_LEN_0F3A33_P_2,
1890   VEX_LEN_0F3A38_P_2,
1891   VEX_LEN_0F3A39_P_2,
1892   VEX_LEN_0F3A41_P_2,
1893   VEX_LEN_0F3A46_P_2,
1894   VEX_LEN_0F3A60_P_2,
1895   VEX_LEN_0F3A61_P_2,
1896   VEX_LEN_0F3A62_P_2,
1897   VEX_LEN_0F3A63_P_2,
1898   VEX_LEN_0F3A6A_P_2,
1899   VEX_LEN_0F3A6B_P_2,
1900   VEX_LEN_0F3A6E_P_2,
1901   VEX_LEN_0F3A6F_P_2,
1902   VEX_LEN_0F3A7A_P_2,
1903   VEX_LEN_0F3A7B_P_2,
1904   VEX_LEN_0F3A7E_P_2,
1905   VEX_LEN_0F3A7F_P_2,
1906   VEX_LEN_0F3ADF_P_2,
1907   VEX_LEN_0F3AF0_P_3,
1908   VEX_LEN_0FXOP_08_CC,
1909   VEX_LEN_0FXOP_08_CD,
1910   VEX_LEN_0FXOP_08_CE,
1911   VEX_LEN_0FXOP_08_CF,
1912   VEX_LEN_0FXOP_08_EC,
1913   VEX_LEN_0FXOP_08_ED,
1914   VEX_LEN_0FXOP_08_EE,
1915   VEX_LEN_0FXOP_08_EF,
1916   VEX_LEN_0FXOP_09_80,
1917   VEX_LEN_0FXOP_09_81
1918 };
1919
1920 enum
1921 {
1922   EVEX_LEN_0F6E_P_2 = 0,
1923   EVEX_LEN_0F7E_P_1,
1924   EVEX_LEN_0F7E_P_2,
1925   EVEX_LEN_0FD6_P_2,
1926   EVEX_LEN_0F3819_P_2_W_0,
1927   EVEX_LEN_0F3819_P_2_W_1,
1928   EVEX_LEN_0F381A_P_2_W_0,
1929   EVEX_LEN_0F381A_P_2_W_1,
1930   EVEX_LEN_0F381B_P_2_W_0,
1931   EVEX_LEN_0F381B_P_2_W_1,
1932   EVEX_LEN_0F385A_P_2_W_0,
1933   EVEX_LEN_0F385A_P_2_W_1,
1934   EVEX_LEN_0F385B_P_2_W_0,
1935   EVEX_LEN_0F385B_P_2_W_1,
1936   EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1937   EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1938   EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1939   EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1940   EVEX_LEN_0F38C7_R_1_P_2_W_0,
1941   EVEX_LEN_0F38C7_R_1_P_2_W_1,
1942   EVEX_LEN_0F38C7_R_2_P_2_W_0,
1943   EVEX_LEN_0F38C7_R_2_P_2_W_1,
1944   EVEX_LEN_0F38C7_R_5_P_2_W_0,
1945   EVEX_LEN_0F38C7_R_5_P_2_W_1,
1946   EVEX_LEN_0F38C7_R_6_P_2_W_0,
1947   EVEX_LEN_0F38C7_R_6_P_2_W_1,
1948   EVEX_LEN_0F3A18_P_2_W_0,
1949   EVEX_LEN_0F3A18_P_2_W_1,
1950   EVEX_LEN_0F3A19_P_2_W_0,
1951   EVEX_LEN_0F3A19_P_2_W_1,
1952   EVEX_LEN_0F3A1A_P_2_W_0,
1953   EVEX_LEN_0F3A1A_P_2_W_1,
1954   EVEX_LEN_0F3A1B_P_2_W_0,
1955   EVEX_LEN_0F3A1B_P_2_W_1,
1956   EVEX_LEN_0F3A23_P_2_W_0,
1957   EVEX_LEN_0F3A23_P_2_W_1,
1958   EVEX_LEN_0F3A38_P_2_W_0,
1959   EVEX_LEN_0F3A38_P_2_W_1,
1960   EVEX_LEN_0F3A39_P_2_W_0,
1961   EVEX_LEN_0F3A39_P_2_W_1,
1962   EVEX_LEN_0F3A3A_P_2_W_0,
1963   EVEX_LEN_0F3A3A_P_2_W_1,
1964   EVEX_LEN_0F3A3B_P_2_W_0,
1965   EVEX_LEN_0F3A3B_P_2_W_1,
1966   EVEX_LEN_0F3A43_P_2_W_0,
1967   EVEX_LEN_0F3A43_P_2_W_1
1968 };
1969
1970 enum
1971 {
1972   VEX_W_0F41_P_0_LEN_1 = 0,
1973   VEX_W_0F41_P_2_LEN_1,
1974   VEX_W_0F42_P_0_LEN_1,
1975   VEX_W_0F42_P_2_LEN_1,
1976   VEX_W_0F44_P_0_LEN_0,
1977   VEX_W_0F44_P_2_LEN_0,
1978   VEX_W_0F45_P_0_LEN_1,
1979   VEX_W_0F45_P_2_LEN_1,
1980   VEX_W_0F46_P_0_LEN_1,
1981   VEX_W_0F46_P_2_LEN_1,
1982   VEX_W_0F47_P_0_LEN_1,
1983   VEX_W_0F47_P_2_LEN_1,
1984   VEX_W_0F4A_P_0_LEN_1,
1985   VEX_W_0F4A_P_2_LEN_1,
1986   VEX_W_0F4B_P_0_LEN_1,
1987   VEX_W_0F4B_P_2_LEN_1,
1988   VEX_W_0F90_P_0_LEN_0,
1989   VEX_W_0F90_P_2_LEN_0,
1990   VEX_W_0F91_P_0_LEN_0,
1991   VEX_W_0F91_P_2_LEN_0,
1992   VEX_W_0F92_P_0_LEN_0,
1993   VEX_W_0F92_P_2_LEN_0,
1994   VEX_W_0F93_P_0_LEN_0,
1995   VEX_W_0F93_P_2_LEN_0,
1996   VEX_W_0F98_P_0_LEN_0,
1997   VEX_W_0F98_P_2_LEN_0,
1998   VEX_W_0F99_P_0_LEN_0,
1999   VEX_W_0F99_P_2_LEN_0,
2000   VEX_W_0F380C_P_2,
2001   VEX_W_0F380D_P_2,
2002   VEX_W_0F380E_P_2,
2003   VEX_W_0F380F_P_2,
2004   VEX_W_0F3816_P_2,
2005   VEX_W_0F3818_P_2,
2006   VEX_W_0F3819_P_2,
2007   VEX_W_0F381A_P_2_M_0,
2008   VEX_W_0F382C_P_2_M_0,
2009   VEX_W_0F382D_P_2_M_0,
2010   VEX_W_0F382E_P_2_M_0,
2011   VEX_W_0F382F_P_2_M_0,
2012   VEX_W_0F3836_P_2,
2013   VEX_W_0F3846_P_2,
2014   VEX_W_0F3858_P_2,
2015   VEX_W_0F3859_P_2,
2016   VEX_W_0F385A_P_2_M_0,
2017   VEX_W_0F3878_P_2,
2018   VEX_W_0F3879_P_2,
2019   VEX_W_0F38CF_P_2,
2020   VEX_W_0F3A00_P_2,
2021   VEX_W_0F3A01_P_2,
2022   VEX_W_0F3A02_P_2,
2023   VEX_W_0F3A04_P_2,
2024   VEX_W_0F3A05_P_2,
2025   VEX_W_0F3A06_P_2,
2026   VEX_W_0F3A18_P_2,
2027   VEX_W_0F3A19_P_2,
2028   VEX_W_0F3A30_P_2_LEN_0,
2029   VEX_W_0F3A31_P_2_LEN_0,
2030   VEX_W_0F3A32_P_2_LEN_0,
2031   VEX_W_0F3A33_P_2_LEN_0,
2032   VEX_W_0F3A38_P_2,
2033   VEX_W_0F3A39_P_2,
2034   VEX_W_0F3A46_P_2,
2035   VEX_W_0F3A48_P_2,
2036   VEX_W_0F3A49_P_2,
2037   VEX_W_0F3A4A_P_2,
2038   VEX_W_0F3A4B_P_2,
2039   VEX_W_0F3A4C_P_2,
2040   VEX_W_0F3ACE_P_2,
2041   VEX_W_0F3ACF_P_2,
2042
2043   EVEX_W_0F10_P_0,
2044   EVEX_W_0F10_P_1,
2045   EVEX_W_0F10_P_2,
2046   EVEX_W_0F10_P_3,
2047   EVEX_W_0F11_P_0,
2048   EVEX_W_0F11_P_1,
2049   EVEX_W_0F11_P_2,
2050   EVEX_W_0F11_P_3,
2051   EVEX_W_0F12_P_0_M_0,
2052   EVEX_W_0F12_P_0_M_1,
2053   EVEX_W_0F12_P_1,
2054   EVEX_W_0F12_P_2,
2055   EVEX_W_0F12_P_3,
2056   EVEX_W_0F13_P_0,
2057   EVEX_W_0F13_P_2,
2058   EVEX_W_0F14_P_0,
2059   EVEX_W_0F14_P_2,
2060   EVEX_W_0F15_P_0,
2061   EVEX_W_0F15_P_2,
2062   EVEX_W_0F16_P_0_M_0,
2063   EVEX_W_0F16_P_0_M_1,
2064   EVEX_W_0F16_P_1,
2065   EVEX_W_0F16_P_2,
2066   EVEX_W_0F17_P_0,
2067   EVEX_W_0F17_P_2,
2068   EVEX_W_0F28_P_0,
2069   EVEX_W_0F28_P_2,
2070   EVEX_W_0F29_P_0,
2071   EVEX_W_0F29_P_2,
2072   EVEX_W_0F2A_P_3,
2073   EVEX_W_0F2B_P_0,
2074   EVEX_W_0F2B_P_2,
2075   EVEX_W_0F2E_P_0,
2076   EVEX_W_0F2E_P_2,
2077   EVEX_W_0F2F_P_0,
2078   EVEX_W_0F2F_P_2,
2079   EVEX_W_0F51_P_0,
2080   EVEX_W_0F51_P_1,
2081   EVEX_W_0F51_P_2,
2082   EVEX_W_0F51_P_3,
2083   EVEX_W_0F54_P_0,
2084   EVEX_W_0F54_P_2,
2085   EVEX_W_0F55_P_0,
2086   EVEX_W_0F55_P_2,
2087   EVEX_W_0F56_P_0,
2088   EVEX_W_0F56_P_2,
2089   EVEX_W_0F57_P_0,
2090   EVEX_W_0F57_P_2,
2091   EVEX_W_0F58_P_0,
2092   EVEX_W_0F58_P_1,
2093   EVEX_W_0F58_P_2,
2094   EVEX_W_0F58_P_3,
2095   EVEX_W_0F59_P_0,
2096   EVEX_W_0F59_P_1,
2097   EVEX_W_0F59_P_2,
2098   EVEX_W_0F59_P_3,
2099   EVEX_W_0F5A_P_0,
2100   EVEX_W_0F5A_P_1,
2101   EVEX_W_0F5A_P_2,
2102   EVEX_W_0F5A_P_3,
2103   EVEX_W_0F5B_P_0,
2104   EVEX_W_0F5B_P_1,
2105   EVEX_W_0F5B_P_2,
2106   EVEX_W_0F5C_P_0,
2107   EVEX_W_0F5C_P_1,
2108   EVEX_W_0F5C_P_2,
2109   EVEX_W_0F5C_P_3,
2110   EVEX_W_0F5D_P_0,
2111   EVEX_W_0F5D_P_1,
2112   EVEX_W_0F5D_P_2,
2113   EVEX_W_0F5D_P_3,
2114   EVEX_W_0F5E_P_0,
2115   EVEX_W_0F5E_P_1,
2116   EVEX_W_0F5E_P_2,
2117   EVEX_W_0F5E_P_3,
2118   EVEX_W_0F5F_P_0,
2119   EVEX_W_0F5F_P_1,
2120   EVEX_W_0F5F_P_2,
2121   EVEX_W_0F5F_P_3,
2122   EVEX_W_0F62_P_2,
2123   EVEX_W_0F66_P_2,
2124   EVEX_W_0F6A_P_2,
2125   EVEX_W_0F6B_P_2,
2126   EVEX_W_0F6C_P_2,
2127   EVEX_W_0F6D_P_2,
2128   EVEX_W_0F6F_P_1,
2129   EVEX_W_0F6F_P_2,
2130   EVEX_W_0F6F_P_3,
2131   EVEX_W_0F70_P_2,
2132   EVEX_W_0F72_R_2_P_2,
2133   EVEX_W_0F72_R_6_P_2,
2134   EVEX_W_0F73_R_2_P_2,
2135   EVEX_W_0F73_R_6_P_2,
2136   EVEX_W_0F76_P_2,
2137   EVEX_W_0F78_P_0,
2138   EVEX_W_0F78_P_2,
2139   EVEX_W_0F79_P_0,
2140   EVEX_W_0F79_P_2,
2141   EVEX_W_0F7A_P_1,
2142   EVEX_W_0F7A_P_2,
2143   EVEX_W_0F7A_P_3,
2144   EVEX_W_0F7B_P_2,
2145   EVEX_W_0F7B_P_3,
2146   EVEX_W_0F7E_P_1,
2147   EVEX_W_0F7F_P_1,
2148   EVEX_W_0F7F_P_2,
2149   EVEX_W_0F7F_P_3,
2150   EVEX_W_0FC2_P_0,
2151   EVEX_W_0FC2_P_1,
2152   EVEX_W_0FC2_P_2,
2153   EVEX_W_0FC2_P_3,
2154   EVEX_W_0FC6_P_0,
2155   EVEX_W_0FC6_P_2,
2156   EVEX_W_0FD2_P_2,
2157   EVEX_W_0FD3_P_2,
2158   EVEX_W_0FD4_P_2,
2159   EVEX_W_0FD6_P_2,
2160   EVEX_W_0FE6_P_1,
2161   EVEX_W_0FE6_P_2,
2162   EVEX_W_0FE6_P_3,
2163   EVEX_W_0FE7_P_2,
2164   EVEX_W_0FF2_P_2,
2165   EVEX_W_0FF3_P_2,
2166   EVEX_W_0FF4_P_2,
2167   EVEX_W_0FFA_P_2,
2168   EVEX_W_0FFB_P_2,
2169   EVEX_W_0FFE_P_2,
2170   EVEX_W_0F380C_P_2,
2171   EVEX_W_0F380D_P_2,
2172   EVEX_W_0F3810_P_1,
2173   EVEX_W_0F3810_P_2,
2174   EVEX_W_0F3811_P_1,
2175   EVEX_W_0F3811_P_2,
2176   EVEX_W_0F3812_P_1,
2177   EVEX_W_0F3812_P_2,
2178   EVEX_W_0F3813_P_1,
2179   EVEX_W_0F3813_P_2,
2180   EVEX_W_0F3814_P_1,
2181   EVEX_W_0F3815_P_1,
2182   EVEX_W_0F3818_P_2,
2183   EVEX_W_0F3819_P_2,
2184   EVEX_W_0F381A_P_2,
2185   EVEX_W_0F381B_P_2,
2186   EVEX_W_0F381E_P_2,
2187   EVEX_W_0F381F_P_2,
2188   EVEX_W_0F3820_P_1,
2189   EVEX_W_0F3821_P_1,
2190   EVEX_W_0F3822_P_1,
2191   EVEX_W_0F3823_P_1,
2192   EVEX_W_0F3824_P_1,
2193   EVEX_W_0F3825_P_1,
2194   EVEX_W_0F3825_P_2,
2195   EVEX_W_0F3826_P_1,
2196   EVEX_W_0F3826_P_2,
2197   EVEX_W_0F3828_P_1,
2198   EVEX_W_0F3828_P_2,
2199   EVEX_W_0F3829_P_1,
2200   EVEX_W_0F3829_P_2,
2201   EVEX_W_0F382A_P_1,
2202   EVEX_W_0F382A_P_2,
2203   EVEX_W_0F382B_P_2,
2204   EVEX_W_0F3830_P_1,
2205   EVEX_W_0F3831_P_1,
2206   EVEX_W_0F3832_P_1,
2207   EVEX_W_0F3833_P_1,
2208   EVEX_W_0F3834_P_1,
2209   EVEX_W_0F3835_P_1,
2210   EVEX_W_0F3835_P_2,
2211   EVEX_W_0F3837_P_2,
2212   EVEX_W_0F3838_P_1,
2213   EVEX_W_0F3839_P_1,
2214   EVEX_W_0F383A_P_1,
2215   EVEX_W_0F3840_P_2,
2216   EVEX_W_0F3852_P_1,
2217   EVEX_W_0F3854_P_2,
2218   EVEX_W_0F3855_P_2,
2219   EVEX_W_0F3858_P_2,
2220   EVEX_W_0F3859_P_2,
2221   EVEX_W_0F385A_P_2,
2222   EVEX_W_0F385B_P_2,
2223   EVEX_W_0F3862_P_2,
2224   EVEX_W_0F3863_P_2,
2225   EVEX_W_0F3866_P_2,
2226   EVEX_W_0F3868_P_3,
2227   EVEX_W_0F3870_P_2,
2228   EVEX_W_0F3871_P_2,
2229   EVEX_W_0F3872_P_1,
2230   EVEX_W_0F3872_P_2,
2231   EVEX_W_0F3872_P_3,
2232   EVEX_W_0F3873_P_2,
2233   EVEX_W_0F3875_P_2,
2234   EVEX_W_0F3878_P_2,
2235   EVEX_W_0F3879_P_2,
2236   EVEX_W_0F387A_P_2,
2237   EVEX_W_0F387B_P_2,
2238   EVEX_W_0F387D_P_2,
2239   EVEX_W_0F3883_P_2,
2240   EVEX_W_0F388D_P_2,
2241   EVEX_W_0F3891_P_2,
2242   EVEX_W_0F3893_P_2,
2243   EVEX_W_0F38A1_P_2,
2244   EVEX_W_0F38A3_P_2,
2245   EVEX_W_0F38C7_R_1_P_2,
2246   EVEX_W_0F38C7_R_2_P_2,
2247   EVEX_W_0F38C7_R_5_P_2,
2248   EVEX_W_0F38C7_R_6_P_2,
2249
2250   EVEX_W_0F3A00_P_2,
2251   EVEX_W_0F3A01_P_2,
2252   EVEX_W_0F3A04_P_2,
2253   EVEX_W_0F3A05_P_2,
2254   EVEX_W_0F3A08_P_2,
2255   EVEX_W_0F3A09_P_2,
2256   EVEX_W_0F3A0A_P_2,
2257   EVEX_W_0F3A0B_P_2,
2258   EVEX_W_0F3A18_P_2,
2259   EVEX_W_0F3A19_P_2,
2260   EVEX_W_0F3A1A_P_2,
2261   EVEX_W_0F3A1B_P_2,
2262   EVEX_W_0F3A1D_P_2,
2263   EVEX_W_0F3A21_P_2,
2264   EVEX_W_0F3A23_P_2,
2265   EVEX_W_0F3A38_P_2,
2266   EVEX_W_0F3A39_P_2,
2267   EVEX_W_0F3A3A_P_2,
2268   EVEX_W_0F3A3B_P_2,
2269   EVEX_W_0F3A3E_P_2,
2270   EVEX_W_0F3A3F_P_2,
2271   EVEX_W_0F3A42_P_2,
2272   EVEX_W_0F3A43_P_2,
2273   EVEX_W_0F3A50_P_2,
2274   EVEX_W_0F3A51_P_2,
2275   EVEX_W_0F3A56_P_2,
2276   EVEX_W_0F3A57_P_2,
2277   EVEX_W_0F3A66_P_2,
2278   EVEX_W_0F3A67_P_2,
2279   EVEX_W_0F3A70_P_2,
2280   EVEX_W_0F3A71_P_2,
2281   EVEX_W_0F3A72_P_2,
2282   EVEX_W_0F3A73_P_2,
2283   EVEX_W_0F3ACE_P_2,
2284   EVEX_W_0F3ACF_P_2
2285 };
2286
2287 typedef void (*op_rtn) (int bytemode, int sizeflag);
2288
2289 struct dis386 {
2290   const char *name;
2291   struct
2292     {
2293       op_rtn rtn;
2294       int bytemode;
2295     } op[MAX_OPERANDS];
2296   unsigned int prefix_requirement;
2297 };
2298
2299 /* Upper case letters in the instruction names here are macros.
2300    'A' => print 'b' if no register operands or suffix_always is true
2301    'B' => print 'b' if suffix_always is true
2302    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2303           size prefix
2304    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2305           suffix_always is true
2306    'E' => print 'e' if 32-bit form of jcxz
2307    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2308    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2309    'H' => print ",pt" or ",pn" branch hint
2310    'I' => honor following macro letter even in Intel mode (implemented only
2311           for some of the macro letters)
2312    'J' => print 'l'
2313    'K' => print 'd' or 'q' if rex prefix is present.
2314    'L' => print 'l' if suffix_always is true
2315    'M' => print 'r' if intel_mnemonic is false.
2316    'N' => print 'n' if instruction has no wait "prefix"
2317    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2318    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2319           or suffix_always is true.  print 'q' if rex prefix is present.
2320    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2321           is true
2322    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2323    'S' => print 'w', 'l' or 'q' if suffix_always is true
2324    'T' => print 'q' in 64bit mode if instruction has no operand size
2325           prefix and behave as 'P' otherwise
2326    'U' => print 'q' in 64bit mode if instruction has no operand size
2327           prefix and behave as 'Q' otherwise
2328    'V' => print 'q' in 64bit mode if instruction has no operand size
2329           prefix and behave as 'S' otherwise
2330    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2331    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2332    'Y' unused.
2333    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2334    '!' => change condition from true to false or from false to true.
2335    '%' => add 1 upper case letter to the macro.
2336    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
2337           prefix or suffix_always is true (lcall/ljmp).
2338    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2339           on operand size prefix.
2340    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2341           has no operand size prefix for AMD64 ISA, behave as 'P'
2342           otherwise
2343
2344    2 upper case letter macros:
2345    "XY" => print 'x' or 'y' if suffix_always is true or no register
2346            operands and no broadcast.
2347    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2348            register operands and no broadcast.
2349    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2350    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2351            or suffix_always is true
2352    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2353    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2354    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2355    "LW" => print 'd', 'q' depending on the VEX.W bit
2356    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2357            an operand size prefix, or suffix_always is true.  print
2358            'q' if rex prefix is present.
2359
2360    Many of the above letters print nothing in Intel mode.  See "putop"
2361    for the details.
2362
2363    Braces '{' and '}', and vertical bars '|', indicate alternative
2364    mnemonic strings for AT&T and Intel.  */
2365
2366 static const struct dis386 dis386[] = {
2367   /* 00 */
2368   { "addB",             { Ebh1, Gb }, 0 },
2369   { "addS",             { Evh1, Gv }, 0 },
2370   { "addB",             { Gb, EbS }, 0 },
2371   { "addS",             { Gv, EvS }, 0 },
2372   { "addB",             { AL, Ib }, 0 },
2373   { "addS",             { eAX, Iv }, 0 },
2374   { X86_64_TABLE (X86_64_06) },
2375   { X86_64_TABLE (X86_64_07) },
2376   /* 08 */
2377   { "orB",              { Ebh1, Gb }, 0 },
2378   { "orS",              { Evh1, Gv }, 0 },
2379   { "orB",              { Gb, EbS }, 0 },
2380   { "orS",              { Gv, EvS }, 0 },
2381   { "orB",              { AL, Ib }, 0 },
2382   { "orS",              { eAX, Iv }, 0 },
2383   { X86_64_TABLE (X86_64_0E) },
2384   { Bad_Opcode },       /* 0x0f extended opcode escape */
2385   /* 10 */
2386   { "adcB",             { Ebh1, Gb }, 0 },
2387   { "adcS",             { Evh1, Gv }, 0 },
2388   { "adcB",             { Gb, EbS }, 0 },
2389   { "adcS",             { Gv, EvS }, 0 },
2390   { "adcB",             { AL, Ib }, 0 },
2391   { "adcS",             { eAX, Iv }, 0 },
2392   { X86_64_TABLE (X86_64_16) },
2393   { X86_64_TABLE (X86_64_17) },
2394   /* 18 */
2395   { "sbbB",             { Ebh1, Gb }, 0 },
2396   { "sbbS",             { Evh1, Gv }, 0 },
2397   { "sbbB",             { Gb, EbS }, 0 },
2398   { "sbbS",             { Gv, EvS }, 0 },
2399   { "sbbB",             { AL, Ib }, 0 },
2400   { "sbbS",             { eAX, Iv }, 0 },
2401   { X86_64_TABLE (X86_64_1E) },
2402   { X86_64_TABLE (X86_64_1F) },
2403   /* 20 */
2404   { "andB",             { Ebh1, Gb }, 0 },
2405   { "andS",             { Evh1, Gv }, 0 },
2406   { "andB",             { Gb, EbS }, 0 },
2407   { "andS",             { Gv, EvS }, 0 },
2408   { "andB",             { AL, Ib }, 0 },
2409   { "andS",             { eAX, Iv }, 0 },
2410   { Bad_Opcode },       /* SEG ES prefix */
2411   { X86_64_TABLE (X86_64_27) },
2412   /* 28 */
2413   { "subB",             { Ebh1, Gb }, 0 },
2414   { "subS",             { Evh1, Gv }, 0 },
2415   { "subB",             { Gb, EbS }, 0 },
2416   { "subS",             { Gv, EvS }, 0 },
2417   { "subB",             { AL, Ib }, 0 },
2418   { "subS",             { eAX, Iv }, 0 },
2419   { Bad_Opcode },       /* SEG CS prefix */
2420   { X86_64_TABLE (X86_64_2F) },
2421   /* 30 */
2422   { "xorB",             { Ebh1, Gb }, 0 },
2423   { "xorS",             { Evh1, Gv }, 0 },
2424   { "xorB",             { Gb, EbS }, 0 },
2425   { "xorS",             { Gv, EvS }, 0 },
2426   { "xorB",             { AL, Ib }, 0 },
2427   { "xorS",             { eAX, Iv }, 0 },
2428   { Bad_Opcode },       /* SEG SS prefix */
2429   { X86_64_TABLE (X86_64_37) },
2430   /* 38 */
2431   { "cmpB",             { Eb, Gb }, 0 },
2432   { "cmpS",             { Ev, Gv }, 0 },
2433   { "cmpB",             { Gb, EbS }, 0 },
2434   { "cmpS",             { Gv, EvS }, 0 },
2435   { "cmpB",             { AL, Ib }, 0 },
2436   { "cmpS",             { eAX, Iv }, 0 },
2437   { Bad_Opcode },       /* SEG DS prefix */
2438   { X86_64_TABLE (X86_64_3F) },
2439   /* 40 */
2440   { "inc{S|}",          { RMeAX }, 0 },
2441   { "inc{S|}",          { RMeCX }, 0 },
2442   { "inc{S|}",          { RMeDX }, 0 },
2443   { "inc{S|}",          { RMeBX }, 0 },
2444   { "inc{S|}",          { RMeSP }, 0 },
2445   { "inc{S|}",          { RMeBP }, 0 },
2446   { "inc{S|}",          { RMeSI }, 0 },
2447   { "inc{S|}",          { RMeDI }, 0 },
2448   /* 48 */
2449   { "dec{S|}",          { RMeAX }, 0 },
2450   { "dec{S|}",          { RMeCX }, 0 },
2451   { "dec{S|}",          { RMeDX }, 0 },
2452   { "dec{S|}",          { RMeBX }, 0 },
2453   { "dec{S|}",          { RMeSP }, 0 },
2454   { "dec{S|}",          { RMeBP }, 0 },
2455   { "dec{S|}",          { RMeSI }, 0 },
2456   { "dec{S|}",          { RMeDI }, 0 },
2457   /* 50 */
2458   { "pushV",            { RMrAX }, 0 },
2459   { "pushV",            { RMrCX }, 0 },
2460   { "pushV",            { RMrDX }, 0 },
2461   { "pushV",            { RMrBX }, 0 },
2462   { "pushV",            { RMrSP }, 0 },
2463   { "pushV",            { RMrBP }, 0 },
2464   { "pushV",            { RMrSI }, 0 },
2465   { "pushV",            { RMrDI }, 0 },
2466   /* 58 */
2467   { "popV",             { RMrAX }, 0 },
2468   { "popV",             { RMrCX }, 0 },
2469   { "popV",             { RMrDX }, 0 },
2470   { "popV",             { RMrBX }, 0 },
2471   { "popV",             { RMrSP }, 0 },
2472   { "popV",             { RMrBP }, 0 },
2473   { "popV",             { RMrSI }, 0 },
2474   { "popV",             { RMrDI }, 0 },
2475   /* 60 */
2476   { X86_64_TABLE (X86_64_60) },
2477   { X86_64_TABLE (X86_64_61) },
2478   { X86_64_TABLE (X86_64_62) },
2479   { X86_64_TABLE (X86_64_63) },
2480   { Bad_Opcode },       /* seg fs */
2481   { Bad_Opcode },       /* seg gs */
2482   { Bad_Opcode },       /* op size prefix */
2483   { Bad_Opcode },       /* adr size prefix */
2484   /* 68 */
2485   { "pushT",            { sIv }, 0 },
2486   { "imulS",            { Gv, Ev, Iv }, 0 },
2487   { "pushT",            { sIbT }, 0 },
2488   { "imulS",            { Gv, Ev, sIb }, 0 },
2489   { "ins{b|}",          { Ybr, indirDX }, 0 },
2490   { X86_64_TABLE (X86_64_6D) },
2491   { "outs{b|}",         { indirDXr, Xb }, 0 },
2492   { X86_64_TABLE (X86_64_6F) },
2493   /* 70 */
2494   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2495   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2496   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2497   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2498   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2499   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2500   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2501   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2502   /* 78 */
2503   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2504   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2505   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2506   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2507   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2508   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2509   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2510   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2511   /* 80 */
2512   { REG_TABLE (REG_80) },
2513   { REG_TABLE (REG_81) },
2514   { X86_64_TABLE (X86_64_82) },
2515   { REG_TABLE (REG_83) },
2516   { "testB",            { Eb, Gb }, 0 },
2517   { "testS",            { Ev, Gv }, 0 },
2518   { "xchgB",            { Ebh2, Gb }, 0 },
2519   { "xchgS",            { Evh2, Gv }, 0 },
2520   /* 88 */
2521   { "movB",             { Ebh3, Gb }, 0 },
2522   { "movS",             { Evh3, Gv }, 0 },
2523   { "movB",             { Gb, EbS }, 0 },
2524   { "movS",             { Gv, EvS }, 0 },
2525   { "movD",             { Sv, Sw }, 0 },
2526   { MOD_TABLE (MOD_8D) },
2527   { "movD",             { Sw, Sv }, 0 },
2528   { REG_TABLE (REG_8F) },
2529   /* 90 */
2530   { PREFIX_TABLE (PREFIX_90) },
2531   { "xchgS",            { RMeCX, eAX }, 0 },
2532   { "xchgS",            { RMeDX, eAX }, 0 },
2533   { "xchgS",            { RMeBX, eAX }, 0 },
2534   { "xchgS",            { RMeSP, eAX }, 0 },
2535   { "xchgS",            { RMeBP, eAX }, 0 },
2536   { "xchgS",            { RMeSI, eAX }, 0 },
2537   { "xchgS",            { RMeDI, eAX }, 0 },
2538   /* 98 */
2539   { "cW{t|}R",          { XX }, 0 },
2540   { "cR{t|}O",          { XX }, 0 },
2541   { X86_64_TABLE (X86_64_9A) },
2542   { Bad_Opcode },       /* fwait */
2543   { "pushfT",           { XX }, 0 },
2544   { "popfT",            { XX }, 0 },
2545   { "sahf",             { XX }, 0 },
2546   { "lahf",             { XX }, 0 },
2547   /* a0 */
2548   { "mov%LB",           { AL, Ob }, 0 },
2549   { "mov%LS",           { eAX, Ov }, 0 },
2550   { "mov%LB",           { Ob, AL }, 0 },
2551   { "mov%LS",           { Ov, eAX }, 0 },
2552   { "movs{b|}",         { Ybr, Xb }, 0 },
2553   { "movs{R|}",         { Yvr, Xv }, 0 },
2554   { "cmps{b|}",         { Xb, Yb }, 0 },
2555   { "cmps{R|}",         { Xv, Yv }, 0 },
2556   /* a8 */
2557   { "testB",            { AL, Ib }, 0 },
2558   { "testS",            { eAX, Iv }, 0 },
2559   { "stosB",            { Ybr, AL }, 0 },
2560   { "stosS",            { Yvr, eAX }, 0 },
2561   { "lodsB",            { ALr, Xb }, 0 },
2562   { "lodsS",            { eAXr, Xv }, 0 },
2563   { "scasB",            { AL, Yb }, 0 },
2564   { "scasS",            { eAX, Yv }, 0 },
2565   /* b0 */
2566   { "movB",             { RMAL, Ib }, 0 },
2567   { "movB",             { RMCL, Ib }, 0 },
2568   { "movB",             { RMDL, Ib }, 0 },
2569   { "movB",             { RMBL, Ib }, 0 },
2570   { "movB",             { RMAH, Ib }, 0 },
2571   { "movB",             { RMCH, Ib }, 0 },
2572   { "movB",             { RMDH, Ib }, 0 },
2573   { "movB",             { RMBH, Ib }, 0 },
2574   /* b8 */
2575   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2576   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2577   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2578   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2579   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2580   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2581   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2582   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2583   /* c0 */
2584   { REG_TABLE (REG_C0) },
2585   { REG_TABLE (REG_C1) },
2586   { X86_64_TABLE (X86_64_C2) },
2587   { X86_64_TABLE (X86_64_C3) },
2588   { X86_64_TABLE (X86_64_C4) },
2589   { X86_64_TABLE (X86_64_C5) },
2590   { REG_TABLE (REG_C6) },
2591   { REG_TABLE (REG_C7) },
2592   /* c8 */
2593   { "enterT",           { Iw, Ib }, 0 },
2594   { "leaveT",           { XX }, 0 },
2595   { "Jret{|f}P",        { Iw }, 0 },
2596   { "Jret{|f}P",        { XX }, 0 },
2597   { "int3",             { XX }, 0 },
2598   { "int",              { Ib }, 0 },
2599   { X86_64_TABLE (X86_64_CE) },
2600   { "iret%LP",          { XX }, 0 },
2601   /* d0 */
2602   { REG_TABLE (REG_D0) },
2603   { REG_TABLE (REG_D1) },
2604   { REG_TABLE (REG_D2) },
2605   { REG_TABLE (REG_D3) },
2606   { X86_64_TABLE (X86_64_D4) },
2607   { X86_64_TABLE (X86_64_D5) },
2608   { Bad_Opcode },
2609   { "xlat",             { DSBX }, 0 },
2610   /* d8 */
2611   { FLOAT },
2612   { FLOAT },
2613   { FLOAT },
2614   { FLOAT },
2615   { FLOAT },
2616   { FLOAT },
2617   { FLOAT },
2618   { FLOAT },
2619   /* e0 */
2620   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2621   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2622   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2623   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2624   { "inB",              { AL, Ib }, 0 },
2625   { "inG",              { zAX, Ib }, 0 },
2626   { "outB",             { Ib, AL }, 0 },
2627   { "outG",             { Ib, zAX }, 0 },
2628   /* e8 */
2629   { X86_64_TABLE (X86_64_E8) },
2630   { X86_64_TABLE (X86_64_E9) },
2631   { X86_64_TABLE (X86_64_EA) },
2632   { "jmp",              { Jb, BND }, 0 },
2633   { "inB",              { AL, indirDX }, 0 },
2634   { "inG",              { zAX, indirDX }, 0 },
2635   { "outB",             { indirDX, AL }, 0 },
2636   { "outG",             { indirDX, zAX }, 0 },
2637   /* f0 */
2638   { Bad_Opcode },       /* lock prefix */
2639   { "icebp",            { XX }, 0 },
2640   { Bad_Opcode },       /* repne */
2641   { Bad_Opcode },       /* repz */
2642   { "hlt",              { XX }, 0 },
2643   { "cmc",              { XX }, 0 },
2644   { REG_TABLE (REG_F6) },
2645   { REG_TABLE (REG_F7) },
2646   /* f8 */
2647   { "clc",              { XX }, 0 },
2648   { "stc",              { XX }, 0 },
2649   { "cli",              { XX }, 0 },
2650   { "sti",              { XX }, 0 },
2651   { "cld",              { XX }, 0 },
2652   { "std",              { XX }, 0 },
2653   { REG_TABLE (REG_FE) },
2654   { REG_TABLE (REG_FF) },
2655 };
2656
2657 static const struct dis386 dis386_twobyte[] = {
2658   /* 00 */
2659   { REG_TABLE (REG_0F00 ) },
2660   { REG_TABLE (REG_0F01 ) },
2661   { "larS",             { Gv, Ew }, 0 },
2662   { "lslS",             { Gv, Ew }, 0 },
2663   { Bad_Opcode },
2664   { "syscall",          { XX }, 0 },
2665   { "clts",             { XX }, 0 },
2666   { "sysret%LP",                { XX }, 0 },
2667   /* 08 */
2668   { "invd",             { XX }, 0 },
2669   { PREFIX_TABLE (PREFIX_0F09) },
2670   { Bad_Opcode },
2671   { "ud2",              { XX }, 0 },
2672   { Bad_Opcode },
2673   { REG_TABLE (REG_0F0D) },
2674   { "femms",            { XX }, 0 },
2675   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2676   /* 10 */
2677   { PREFIX_TABLE (PREFIX_0F10) },
2678   { PREFIX_TABLE (PREFIX_0F11) },
2679   { PREFIX_TABLE (PREFIX_0F12) },
2680   { MOD_TABLE (MOD_0F13) },
2681   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2682   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2683   { PREFIX_TABLE (PREFIX_0F16) },
2684   { MOD_TABLE (MOD_0F17) },
2685   /* 18 */
2686   { REG_TABLE (REG_0F18) },
2687   { "nopQ",             { Ev }, 0 },
2688   { PREFIX_TABLE (PREFIX_0F1A) },
2689   { PREFIX_TABLE (PREFIX_0F1B) },
2690   { PREFIX_TABLE (PREFIX_0F1C) },
2691   { "nopQ",             { Ev }, 0 },
2692   { PREFIX_TABLE (PREFIX_0F1E) },
2693   { "nopQ",             { Ev }, 0 },
2694   /* 20 */
2695   { "movZ",             { Rm, Cm }, 0 },
2696   { "movZ",             { Rm, Dm }, 0 },
2697   { "movZ",             { Cm, Rm }, 0 },
2698   { "movZ",             { Dm, Rm }, 0 },
2699   { MOD_TABLE (MOD_0F24) },
2700   { Bad_Opcode },
2701   { MOD_TABLE (MOD_0F26) },
2702   { Bad_Opcode },
2703   /* 28 */
2704   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2705   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2706   { PREFIX_TABLE (PREFIX_0F2A) },
2707   { PREFIX_TABLE (PREFIX_0F2B) },
2708   { PREFIX_TABLE (PREFIX_0F2C) },
2709   { PREFIX_TABLE (PREFIX_0F2D) },
2710   { PREFIX_TABLE (PREFIX_0F2E) },
2711   { PREFIX_TABLE (PREFIX_0F2F) },
2712   /* 30 */
2713   { "wrmsr",            { XX }, 0 },
2714   { "rdtsc",            { XX }, 0 },
2715   { "rdmsr",            { XX }, 0 },
2716   { "rdpmc",            { XX }, 0 },
2717   { "sysenter",         { SEP }, 0 },
2718   { "sysexit",          { SEP }, 0 },
2719   { Bad_Opcode },
2720   { "getsec",           { XX }, 0 },
2721   /* 38 */
2722   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2723   { Bad_Opcode },
2724   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2725   { Bad_Opcode },
2726   { Bad_Opcode },
2727   { Bad_Opcode },
2728   { Bad_Opcode },
2729   { Bad_Opcode },
2730   /* 40 */
2731   { "cmovoS",           { Gv, Ev }, 0 },
2732   { "cmovnoS",          { Gv, Ev }, 0 },
2733   { "cmovbS",           { Gv, Ev }, 0 },
2734   { "cmovaeS",          { Gv, Ev }, 0 },
2735   { "cmoveS",           { Gv, Ev }, 0 },
2736   { "cmovneS",          { Gv, Ev }, 0 },
2737   { "cmovbeS",          { Gv, Ev }, 0 },
2738   { "cmovaS",           { Gv, Ev }, 0 },
2739   /* 48 */
2740   { "cmovsS",           { Gv, Ev }, 0 },
2741   { "cmovnsS",          { Gv, Ev }, 0 },
2742   { "cmovpS",           { Gv, Ev }, 0 },
2743   { "cmovnpS",          { Gv, Ev }, 0 },
2744   { "cmovlS",           { Gv, Ev }, 0 },
2745   { "cmovgeS",          { Gv, Ev }, 0 },
2746   { "cmovleS",          { Gv, Ev }, 0 },
2747   { "cmovgS",           { Gv, Ev }, 0 },
2748   /* 50 */
2749   { MOD_TABLE (MOD_0F50) },
2750   { PREFIX_TABLE (PREFIX_0F51) },
2751   { PREFIX_TABLE (PREFIX_0F52) },
2752   { PREFIX_TABLE (PREFIX_0F53) },
2753   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2754   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2755   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2756   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2757   /* 58 */
2758   { PREFIX_TABLE (PREFIX_0F58) },
2759   { PREFIX_TABLE (PREFIX_0F59) },
2760   { PREFIX_TABLE (PREFIX_0F5A) },
2761   { PREFIX_TABLE (PREFIX_0F5B) },
2762   { PREFIX_TABLE (PREFIX_0F5C) },
2763   { PREFIX_TABLE (PREFIX_0F5D) },
2764   { PREFIX_TABLE (PREFIX_0F5E) },
2765   { PREFIX_TABLE (PREFIX_0F5F) },
2766   /* 60 */
2767   { PREFIX_TABLE (PREFIX_0F60) },
2768   { PREFIX_TABLE (PREFIX_0F61) },
2769   { PREFIX_TABLE (PREFIX_0F62) },
2770   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2771   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2772   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2773   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2774   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2775   /* 68 */
2776   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2777   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2778   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2779   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2780   { PREFIX_TABLE (PREFIX_0F6C) },
2781   { PREFIX_TABLE (PREFIX_0F6D) },
2782   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2783   { PREFIX_TABLE (PREFIX_0F6F) },
2784   /* 70 */
2785   { PREFIX_TABLE (PREFIX_0F70) },
2786   { REG_TABLE (REG_0F71) },
2787   { REG_TABLE (REG_0F72) },
2788   { REG_TABLE (REG_0F73) },
2789   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2790   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2791   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2792   { "emms",             { XX }, PREFIX_OPCODE },
2793   /* 78 */
2794   { PREFIX_TABLE (PREFIX_0F78) },
2795   { PREFIX_TABLE (PREFIX_0F79) },
2796   { Bad_Opcode },
2797   { Bad_Opcode },
2798   { PREFIX_TABLE (PREFIX_0F7C) },
2799   { PREFIX_TABLE (PREFIX_0F7D) },
2800   { PREFIX_TABLE (PREFIX_0F7E) },
2801   { PREFIX_TABLE (PREFIX_0F7F) },
2802   /* 80 */
2803   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2804   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2805   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2806   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2807   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2808   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2809   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2810   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2811   /* 88 */
2812   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2813   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2814   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2815   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2816   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2817   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2818   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2819   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2820   /* 90 */
2821   { "seto",             { Eb }, 0 },
2822   { "setno",            { Eb }, 0 },
2823   { "setb",             { Eb }, 0 },
2824   { "setae",            { Eb }, 0 },
2825   { "sete",             { Eb }, 0 },
2826   { "setne",            { Eb }, 0 },
2827   { "setbe",            { Eb }, 0 },
2828   { "seta",             { Eb }, 0 },
2829   /* 98 */
2830   { "sets",             { Eb }, 0 },
2831   { "setns",            { Eb }, 0 },
2832   { "setp",             { Eb }, 0 },
2833   { "setnp",            { Eb }, 0 },
2834   { "setl",             { Eb }, 0 },
2835   { "setge",            { Eb }, 0 },
2836   { "setle",            { Eb }, 0 },
2837   { "setg",             { Eb }, 0 },
2838   /* a0 */
2839   { "pushT",            { fs }, 0 },
2840   { "popT",             { fs }, 0 },
2841   { "cpuid",            { XX }, 0 },
2842   { "btS",              { Ev, Gv }, 0 },
2843   { "shldS",            { Ev, Gv, Ib }, 0 },
2844   { "shldS",            { Ev, Gv, CL }, 0 },
2845   { REG_TABLE (REG_0FA6) },
2846   { REG_TABLE (REG_0FA7) },
2847   /* a8 */
2848   { "pushT",            { gs }, 0 },
2849   { "popT",             { gs }, 0 },
2850   { "rsm",              { XX }, 0 },
2851   { "btsS",             { Evh1, Gv }, 0 },
2852   { "shrdS",            { Ev, Gv, Ib }, 0 },
2853   { "shrdS",            { Ev, Gv, CL }, 0 },
2854   { REG_TABLE (REG_0FAE) },
2855   { "imulS",            { Gv, Ev }, 0 },
2856   /* b0 */
2857   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2858   { "cmpxchgS",         { Evh1, Gv }, 0 },
2859   { MOD_TABLE (MOD_0FB2) },
2860   { "btrS",             { Evh1, Gv }, 0 },
2861   { MOD_TABLE (MOD_0FB4) },
2862   { MOD_TABLE (MOD_0FB5) },
2863   { "movz{bR|x}",       { Gv, Eb }, 0 },
2864   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2865   /* b8 */
2866   { PREFIX_TABLE (PREFIX_0FB8) },
2867   { "ud1S",             { Gv, Ev }, 0 },
2868   { REG_TABLE (REG_0FBA) },
2869   { "btcS",             { Evh1, Gv }, 0 },
2870   { PREFIX_TABLE (PREFIX_0FBC) },
2871   { PREFIX_TABLE (PREFIX_0FBD) },
2872   { "movs{bR|x}",       { Gv, Eb }, 0 },
2873   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2874   /* c0 */
2875   { "xaddB",            { Ebh1, Gb }, 0 },
2876   { "xaddS",            { Evh1, Gv }, 0 },
2877   { PREFIX_TABLE (PREFIX_0FC2) },
2878   { MOD_TABLE (MOD_0FC3) },
2879   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2880   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2881   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2882   { REG_TABLE (REG_0FC7) },
2883   /* c8 */
2884   { "bswap",            { RMeAX }, 0 },
2885   { "bswap",            { RMeCX }, 0 },
2886   { "bswap",            { RMeDX }, 0 },
2887   { "bswap",            { RMeBX }, 0 },
2888   { "bswap",            { RMeSP }, 0 },
2889   { "bswap",            { RMeBP }, 0 },
2890   { "bswap",            { RMeSI }, 0 },
2891   { "bswap",            { RMeDI }, 0 },
2892   /* d0 */
2893   { PREFIX_TABLE (PREFIX_0FD0) },
2894   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2895   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2896   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2897   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2898   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2899   { PREFIX_TABLE (PREFIX_0FD6) },
2900   { MOD_TABLE (MOD_0FD7) },
2901   /* d8 */
2902   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2903   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2904   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2905   { "pand",             { MX, EM }, PREFIX_OPCODE },
2906   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2907   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2908   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2909   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2910   /* e0 */
2911   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2912   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2913   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2914   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2915   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2916   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2917   { PREFIX_TABLE (PREFIX_0FE6) },
2918   { PREFIX_TABLE (PREFIX_0FE7) },
2919   /* e8 */
2920   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2921   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2922   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2923   { "por",              { MX, EM }, PREFIX_OPCODE },
2924   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2925   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2926   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2927   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2928   /* f0 */
2929   { PREFIX_TABLE (PREFIX_0FF0) },
2930   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2931   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2932   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2933   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2934   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2935   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2936   { PREFIX_TABLE (PREFIX_0FF7) },
2937   /* f8 */
2938   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2939   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2940   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2941   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2942   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2943   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2944   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2945   { "ud0S",             { Gv, Ev }, 0 },
2946 };
2947
2948 static const unsigned char onebyte_has_modrm[256] = {
2949   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2950   /*       -------------------------------        */
2951   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2952   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2953   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2954   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2955   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2956   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2957   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2958   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2959   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2960   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2961   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2962   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2963   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2964   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2965   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2966   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2967   /*       -------------------------------        */
2968   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2969 };
2970
2971 static const unsigned char twobyte_has_modrm[256] = {
2972   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2973   /*       -------------------------------        */
2974   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2975   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2976   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2977   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2978   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2979   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2980   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2981   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2982   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2983   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2984   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2985   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2986   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2987   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2988   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2989   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2990   /*       -------------------------------        */
2991   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2992 };
2993
2994 static char obuf[100];
2995 static char *obufp;
2996 static char *mnemonicendp;
2997 static char scratchbuf[100];
2998 static unsigned char *start_codep;
2999 static unsigned char *insn_codep;
3000 static unsigned char *codep;
3001 static unsigned char *end_codep;
3002 static int last_lock_prefix;
3003 static int last_repz_prefix;
3004 static int last_repnz_prefix;
3005 static int last_data_prefix;
3006 static int last_addr_prefix;
3007 static int last_rex_prefix;
3008 static int last_seg_prefix;
3009 static int fwait_prefix;
3010 /* The active segment register prefix.  */
3011 static int active_seg_prefix;
3012 #define MAX_CODE_LENGTH 15
3013 /* We can up to 14 prefixes since the maximum instruction length is
3014    15bytes.  */
3015 static int all_prefixes[MAX_CODE_LENGTH - 1];
3016 static disassemble_info *the_info;
3017 static struct
3018   {
3019     int mod;
3020     int reg;
3021     int rm;
3022   }
3023 modrm;
3024 static unsigned char need_modrm;
3025 static struct
3026   {
3027     int scale;
3028     int index;
3029     int base;
3030   }
3031 sib;
3032 static struct
3033   {
3034     int register_specifier;
3035     int length;
3036     int prefix;
3037     int w;
3038     int evex;
3039     int r;
3040     int v;
3041     int mask_register_specifier;
3042     int zeroing;
3043     int ll;
3044     int b;
3045   }
3046 vex;
3047 static unsigned char need_vex;
3048 static unsigned char need_vex_reg;
3049 static unsigned char vex_w_done;
3050
3051 struct op
3052   {
3053     const char *name;
3054     unsigned int len;
3055   };
3056
3057 /* If we are accessing mod/rm/reg without need_modrm set, then the
3058    values are stale.  Hitting this abort likely indicates that you
3059    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3060 #define MODRM_CHECK  if (!need_modrm) abort ()
3061
3062 static const char **names64;
3063 static const char **names32;
3064 static const char **names16;
3065 static const char **names8;
3066 static const char **names8rex;
3067 static const char **names_seg;
3068 static const char *index64;
3069 static const char *index32;
3070 static const char **index16;
3071 static const char **names_bnd;
3072
3073 static const char *intel_names64[] = {
3074   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3075   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3076 };
3077 static const char *intel_names32[] = {
3078   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3079   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3080 };
3081 static const char *intel_names16[] = {
3082   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3083   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3084 };
3085 static const char *intel_names8[] = {
3086   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3087 };
3088 static const char *intel_names8rex[] = {
3089   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3090   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3091 };
3092 static const char *intel_names_seg[] = {
3093   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3094 };
3095 static const char *intel_index64 = "riz";
3096 static const char *intel_index32 = "eiz";
3097 static const char *intel_index16[] = {
3098   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3099 };
3100
3101 static const char *att_names64[] = {
3102   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3103   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3104 };
3105 static const char *att_names32[] = {
3106   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3107   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3108 };
3109 static const char *att_names16[] = {
3110   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3111   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3112 };
3113 static const char *att_names8[] = {
3114   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3115 };
3116 static const char *att_names8rex[] = {
3117   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3118   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3119 };
3120 static const char *att_names_seg[] = {
3121   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3122 };
3123 static const char *att_index64 = "%riz";
3124 static const char *att_index32 = "%eiz";
3125 static const char *att_index16[] = {
3126   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3127 };
3128
3129 static const char **names_mm;
3130 static const char *intel_names_mm[] = {
3131   "mm0", "mm1", "mm2", "mm3",
3132   "mm4", "mm5", "mm6", "mm7"
3133 };
3134 static const char *att_names_mm[] = {
3135   "%mm0", "%mm1", "%mm2", "%mm3",
3136   "%mm4", "%mm5", "%mm6", "%mm7"
3137 };
3138
3139 static const char *intel_names_bnd[] = {
3140   "bnd0", "bnd1", "bnd2", "bnd3"
3141 };
3142
3143 static const char *att_names_bnd[] = {
3144   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3145 };
3146
3147 static const char **names_xmm;
3148 static const char *intel_names_xmm[] = {
3149   "xmm0", "xmm1", "xmm2", "xmm3",
3150   "xmm4", "xmm5", "xmm6", "xmm7",
3151   "xmm8", "xmm9", "xmm10", "xmm11",
3152   "xmm12", "xmm13", "xmm14", "xmm15",
3153   "xmm16", "xmm17", "xmm18", "xmm19",
3154   "xmm20", "xmm21", "xmm22", "xmm23",
3155   "xmm24", "xmm25", "xmm26", "xmm27",
3156   "xmm28", "xmm29", "xmm30", "xmm31"
3157 };
3158 static const char *att_names_xmm[] = {
3159   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3160   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3161   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3162   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3163   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3164   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3165   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3166   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3167 };
3168
3169 static const char **names_ymm;
3170 static const char *intel_names_ymm[] = {
3171   "ymm0", "ymm1", "ymm2", "ymm3",
3172   "ymm4", "ymm5", "ymm6", "ymm7",
3173   "ymm8", "ymm9", "ymm10", "ymm11",
3174   "ymm12", "ymm13", "ymm14", "ymm15",
3175   "ymm16", "ymm17", "ymm18", "ymm19",
3176   "ymm20", "ymm21", "ymm22", "ymm23",
3177   "ymm24", "ymm25", "ymm26", "ymm27",
3178   "ymm28", "ymm29", "ymm30", "ymm31"
3179 };
3180 static const char *att_names_ymm[] = {
3181   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3182   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3183   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3184   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3185   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3186   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3187   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3188   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3189 };
3190
3191 static const char **names_zmm;
3192 static const char *intel_names_zmm[] = {
3193   "zmm0", "zmm1", "zmm2", "zmm3",
3194   "zmm4", "zmm5", "zmm6", "zmm7",
3195   "zmm8", "zmm9", "zmm10", "zmm11",
3196   "zmm12", "zmm13", "zmm14", "zmm15",
3197   "zmm16", "zmm17", "zmm18", "zmm19",
3198   "zmm20", "zmm21", "zmm22", "zmm23",
3199   "zmm24", "zmm25", "zmm26", "zmm27",
3200   "zmm28", "zmm29", "zmm30", "zmm31"
3201 };
3202 static const char *att_names_zmm[] = {
3203   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3204   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3205   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3206   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3207   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3208   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3209   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3210   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3211 };
3212
3213 static const char **names_mask;
3214 static const char *intel_names_mask[] = {
3215   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3216 };
3217 static const char *att_names_mask[] = {
3218   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3219 };
3220
3221 static const char *names_rounding[] =
3222 {
3223   "{rn-sae}",
3224   "{rd-sae}",
3225   "{ru-sae}",
3226   "{rz-sae}"
3227 };
3228
3229 static const struct dis386 reg_table[][8] = {
3230   /* REG_80 */
3231   {
3232     { "addA",   { Ebh1, Ib }, 0 },
3233     { "orA",    { Ebh1, Ib }, 0 },
3234     { "adcA",   { Ebh1, Ib }, 0 },
3235     { "sbbA",   { Ebh1, Ib }, 0 },
3236     { "andA",   { Ebh1, Ib }, 0 },
3237     { "subA",   { Ebh1, Ib }, 0 },
3238     { "xorA",   { Ebh1, Ib }, 0 },
3239     { "cmpA",   { Eb, Ib }, 0 },
3240   },
3241   /* REG_81 */
3242   {
3243     { "addQ",   { Evh1, Iv }, 0 },
3244     { "orQ",    { Evh1, Iv }, 0 },
3245     { "adcQ",   { Evh1, Iv }, 0 },
3246     { "sbbQ",   { Evh1, Iv }, 0 },
3247     { "andQ",   { Evh1, Iv }, 0 },
3248     { "subQ",   { Evh1, Iv }, 0 },
3249     { "xorQ",   { Evh1, Iv }, 0 },
3250     { "cmpQ",   { Ev, Iv }, 0 },
3251   },
3252   /* REG_83 */
3253   {
3254     { "addQ",   { Evh1, sIb }, 0 },
3255     { "orQ",    { Evh1, sIb }, 0 },
3256     { "adcQ",   { Evh1, sIb }, 0 },
3257     { "sbbQ",   { Evh1, sIb }, 0 },
3258     { "andQ",   { Evh1, sIb }, 0 },
3259     { "subQ",   { Evh1, sIb }, 0 },
3260     { "xorQ",   { Evh1, sIb }, 0 },
3261     { "cmpQ",   { Ev, sIb }, 0 },
3262   },
3263   /* REG_8F */
3264   {
3265     { "popU",   { stackEv }, 0 },
3266     { XOP_8F_TABLE (XOP_09) },
3267     { Bad_Opcode },
3268     { Bad_Opcode },
3269     { Bad_Opcode },
3270     { XOP_8F_TABLE (XOP_09) },
3271   },
3272   /* REG_C0 */
3273   {
3274     { "rolA",   { Eb, Ib }, 0 },
3275     { "rorA",   { Eb, Ib }, 0 },
3276     { "rclA",   { Eb, Ib }, 0 },
3277     { "rcrA",   { Eb, Ib }, 0 },
3278     { "shlA",   { Eb, Ib }, 0 },
3279     { "shrA",   { Eb, Ib }, 0 },
3280     { "shlA",   { Eb, Ib }, 0 },
3281     { "sarA",   { Eb, Ib }, 0 },
3282   },
3283   /* REG_C1 */
3284   {
3285     { "rolQ",   { Ev, Ib }, 0 },
3286     { "rorQ",   { Ev, Ib }, 0 },
3287     { "rclQ",   { Ev, Ib }, 0 },
3288     { "rcrQ",   { Ev, Ib }, 0 },
3289     { "shlQ",   { Ev, Ib }, 0 },
3290     { "shrQ",   { Ev, Ib }, 0 },
3291     { "shlQ",   { Ev, Ib }, 0 },
3292     { "sarQ",   { Ev, Ib }, 0 },
3293   },
3294   /* REG_C6 */
3295   {
3296     { "movA",   { Ebh3, Ib }, 0 },
3297     { Bad_Opcode },
3298     { Bad_Opcode },
3299     { Bad_Opcode },
3300     { Bad_Opcode },
3301     { Bad_Opcode },
3302     { Bad_Opcode },
3303     { MOD_TABLE (MOD_C6_REG_7) },
3304   },
3305   /* REG_C7 */
3306   {
3307     { "movQ",   { Evh3, Iv }, 0 },
3308     { Bad_Opcode },
3309     { Bad_Opcode },
3310     { Bad_Opcode },
3311     { Bad_Opcode },
3312     { Bad_Opcode },
3313     { Bad_Opcode },
3314     { MOD_TABLE (MOD_C7_REG_7) },
3315   },
3316   /* REG_D0 */
3317   {
3318     { "rolA",   { Eb, I1 }, 0 },
3319     { "rorA",   { Eb, I1 }, 0 },
3320     { "rclA",   { Eb, I1 }, 0 },
3321     { "rcrA",   { Eb, I1 }, 0 },
3322     { "shlA",   { Eb, I1 }, 0 },
3323     { "shrA",   { Eb, I1 }, 0 },
3324     { "shlA",   { Eb, I1 }, 0 },
3325     { "sarA",   { Eb, I1 }, 0 },
3326   },
3327   /* REG_D1 */
3328   {
3329     { "rolQ",   { Ev, I1 }, 0 },
3330     { "rorQ",   { Ev, I1 }, 0 },
3331     { "rclQ",   { Ev, I1 }, 0 },
3332     { "rcrQ",   { Ev, I1 }, 0 },
3333     { "shlQ",   { Ev, I1 }, 0 },
3334     { "shrQ",   { Ev, I1 }, 0 },
3335     { "shlQ",   { Ev, I1 }, 0 },
3336     { "sarQ",   { Ev, I1 }, 0 },
3337   },
3338   /* REG_D2 */
3339   {
3340     { "rolA",   { Eb, CL }, 0 },
3341     { "rorA",   { Eb, CL }, 0 },
3342     { "rclA",   { Eb, CL }, 0 },
3343     { "rcrA",   { Eb, CL }, 0 },
3344     { "shlA",   { Eb, CL }, 0 },
3345     { "shrA",   { Eb, CL }, 0 },
3346     { "shlA",   { Eb, CL }, 0 },
3347     { "sarA",   { Eb, CL }, 0 },
3348   },
3349   /* REG_D3 */
3350   {
3351     { "rolQ",   { Ev, CL }, 0 },
3352     { "rorQ",   { Ev, CL }, 0 },
3353     { "rclQ",   { Ev, CL }, 0 },
3354     { "rcrQ",   { Ev, CL }, 0 },
3355     { "shlQ",   { Ev, CL }, 0 },
3356     { "shrQ",   { Ev, CL }, 0 },
3357     { "shlQ",   { Ev, CL }, 0 },
3358     { "sarQ",   { Ev, CL }, 0 },
3359   },
3360   /* REG_F6 */
3361   {
3362     { "testA",  { Eb, Ib }, 0 },
3363     { "testA",  { Eb, Ib }, 0 },
3364     { "notA",   { Ebh1 }, 0 },
3365     { "negA",   { Ebh1 }, 0 },
3366     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3367     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3368     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3369     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3370   },
3371   /* REG_F7 */
3372   {
3373     { "testQ",  { Ev, Iv }, 0 },
3374     { "testQ",  { Ev, Iv }, 0 },
3375     { "notQ",   { Evh1 }, 0 },
3376     { "negQ",   { Evh1 }, 0 },
3377     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3378     { "imulQ",  { Ev }, 0 },
3379     { "divQ",   { Ev }, 0 },
3380     { "idivQ",  { Ev }, 0 },
3381   },
3382   /* REG_FE */
3383   {
3384     { "incA",   { Ebh1 }, 0 },
3385     { "decA",   { Ebh1 }, 0 },
3386   },
3387   /* REG_FF */
3388   {
3389     { "incQ",   { Evh1 }, 0 },
3390     { "decQ",   { Evh1 }, 0 },
3391     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3392     { MOD_TABLE (MOD_FF_REG_3) },
3393     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3394     { MOD_TABLE (MOD_FF_REG_5) },
3395     { "pushU",  { stackEv }, 0 },
3396     { Bad_Opcode },
3397   },
3398   /* REG_0F00 */
3399   {
3400     { "sldtD",  { Sv }, 0 },
3401     { "strD",   { Sv }, 0 },
3402     { "lldt",   { Ew }, 0 },
3403     { "ltr",    { Ew }, 0 },
3404     { "verr",   { Ew }, 0 },
3405     { "verw",   { Ew }, 0 },
3406     { Bad_Opcode },
3407     { Bad_Opcode },
3408   },
3409   /* REG_0F01 */
3410   {
3411     { MOD_TABLE (MOD_0F01_REG_0) },
3412     { MOD_TABLE (MOD_0F01_REG_1) },
3413     { MOD_TABLE (MOD_0F01_REG_2) },
3414     { MOD_TABLE (MOD_0F01_REG_3) },
3415     { "smswD",  { Sv }, 0 },
3416     { MOD_TABLE (MOD_0F01_REG_5) },
3417     { "lmsw",   { Ew }, 0 },
3418     { MOD_TABLE (MOD_0F01_REG_7) },
3419   },
3420   /* REG_0F0D */
3421   {
3422     { "prefetch",       { Mb }, 0 },
3423     { "prefetchw",      { Mb }, 0 },
3424     { "prefetchwt1",    { Mb }, 0 },
3425     { "prefetch",       { Mb }, 0 },
3426     { "prefetch",       { Mb }, 0 },
3427     { "prefetch",       { Mb }, 0 },
3428     { "prefetch",       { Mb }, 0 },
3429     { "prefetch",       { Mb }, 0 },
3430   },
3431   /* REG_0F18 */
3432   {
3433     { MOD_TABLE (MOD_0F18_REG_0) },
3434     { MOD_TABLE (MOD_0F18_REG_1) },
3435     { MOD_TABLE (MOD_0F18_REG_2) },
3436     { MOD_TABLE (MOD_0F18_REG_3) },
3437     { MOD_TABLE (MOD_0F18_REG_4) },
3438     { MOD_TABLE (MOD_0F18_REG_5) },
3439     { MOD_TABLE (MOD_0F18_REG_6) },
3440     { MOD_TABLE (MOD_0F18_REG_7) },
3441   },
3442   /* REG_0F1C_P_0_MOD_0 */
3443   {
3444     { "cldemote",       { Mb }, 0 },
3445     { "nopQ",           { Ev }, 0 },
3446     { "nopQ",           { Ev }, 0 },
3447     { "nopQ",           { Ev }, 0 },
3448     { "nopQ",           { Ev }, 0 },
3449     { "nopQ",           { Ev }, 0 },
3450     { "nopQ",           { Ev }, 0 },
3451     { "nopQ",           { Ev }, 0 },
3452   },
3453   /* REG_0F1E_P_1_MOD_3 */
3454   {
3455     { "nopQ",           { Ev }, 0 },
3456     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3457     { "nopQ",           { Ev }, 0 },
3458     { "nopQ",           { Ev }, 0 },
3459     { "nopQ",           { Ev }, 0 },
3460     { "nopQ",           { Ev }, 0 },
3461     { "nopQ",           { Ev }, 0 },
3462     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
3463   },
3464   /* REG_0F71 */
3465   {
3466     { Bad_Opcode },
3467     { Bad_Opcode },
3468     { MOD_TABLE (MOD_0F71_REG_2) },
3469     { Bad_Opcode },
3470     { MOD_TABLE (MOD_0F71_REG_4) },
3471     { Bad_Opcode },
3472     { MOD_TABLE (MOD_0F71_REG_6) },
3473   },
3474   /* REG_0F72 */
3475   {
3476     { Bad_Opcode },
3477     { Bad_Opcode },
3478     { MOD_TABLE (MOD_0F72_REG_2) },
3479     { Bad_Opcode },
3480     { MOD_TABLE (MOD_0F72_REG_4) },
3481     { Bad_Opcode },
3482     { MOD_TABLE (MOD_0F72_REG_6) },
3483   },
3484   /* REG_0F73 */
3485   {
3486     { Bad_Opcode },
3487     { Bad_Opcode },
3488     { MOD_TABLE (MOD_0F73_REG_2) },
3489     { MOD_TABLE (MOD_0F73_REG_3) },
3490     { Bad_Opcode },
3491     { Bad_Opcode },
3492     { MOD_TABLE (MOD_0F73_REG_6) },
3493     { MOD_TABLE (MOD_0F73_REG_7) },
3494   },
3495   /* REG_0FA6 */
3496   {
3497     { "montmul",        { { OP_0f07, 0 } }, 0 },
3498     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3499     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3500   },
3501   /* REG_0FA7 */
3502   {
3503     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3504     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3505     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3506     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3507     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3508     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3509   },
3510   /* REG_0FAE */
3511   {
3512     { MOD_TABLE (MOD_0FAE_REG_0) },
3513     { MOD_TABLE (MOD_0FAE_REG_1) },
3514     { MOD_TABLE (MOD_0FAE_REG_2) },
3515     { MOD_TABLE (MOD_0FAE_REG_3) },
3516     { MOD_TABLE (MOD_0FAE_REG_4) },
3517     { MOD_TABLE (MOD_0FAE_REG_5) },
3518     { MOD_TABLE (MOD_0FAE_REG_6) },
3519     { MOD_TABLE (MOD_0FAE_REG_7) },
3520   },
3521   /* REG_0FBA */
3522   {
3523     { Bad_Opcode },
3524     { Bad_Opcode },
3525     { Bad_Opcode },
3526     { Bad_Opcode },
3527     { "btQ",    { Ev, Ib }, 0 },
3528     { "btsQ",   { Evh1, Ib }, 0 },
3529     { "btrQ",   { Evh1, Ib }, 0 },
3530     { "btcQ",   { Evh1, Ib }, 0 },
3531   },
3532   /* REG_0FC7 */
3533   {
3534     { Bad_Opcode },
3535     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3536     { Bad_Opcode },
3537     { MOD_TABLE (MOD_0FC7_REG_3) },
3538     { MOD_TABLE (MOD_0FC7_REG_4) },
3539     { MOD_TABLE (MOD_0FC7_REG_5) },
3540     { MOD_TABLE (MOD_0FC7_REG_6) },
3541     { MOD_TABLE (MOD_0FC7_REG_7) },
3542   },
3543   /* REG_VEX_0F71 */
3544   {
3545     { Bad_Opcode },
3546     { Bad_Opcode },
3547     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3548     { Bad_Opcode },
3549     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3550     { Bad_Opcode },
3551     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3552   },
3553   /* REG_VEX_0F72 */
3554   {
3555     { Bad_Opcode },
3556     { Bad_Opcode },
3557     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3558     { Bad_Opcode },
3559     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3560     { Bad_Opcode },
3561     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3562   },
3563   /* REG_VEX_0F73 */
3564   {
3565     { Bad_Opcode },
3566     { Bad_Opcode },
3567     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3568     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3569     { Bad_Opcode },
3570     { Bad_Opcode },
3571     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3572     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3573   },
3574   /* REG_VEX_0FAE */
3575   {
3576     { Bad_Opcode },
3577     { Bad_Opcode },
3578     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3579     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3580   },
3581   /* REG_VEX_0F38F3 */
3582   {
3583     { Bad_Opcode },
3584     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3585     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3586     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3587   },
3588   /* REG_XOP_LWPCB */
3589   {
3590     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3591     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3592   },
3593   /* REG_XOP_LWP */
3594   {
3595     { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3596     { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3597   },
3598   /* REG_XOP_TBM_01 */
3599   {
3600     { Bad_Opcode },
3601     { "blcfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3602     { "blsfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3603     { "blcs",   { { OP_LWP_E, 0 }, Edq }, 0 },
3604     { "tzmsk",  { { OP_LWP_E, 0 }, Edq }, 0 },
3605     { "blcic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3606     { "blsic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3607     { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 },
3608   },
3609   /* REG_XOP_TBM_02 */
3610   {
3611     { Bad_Opcode },
3612     { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
3613     { Bad_Opcode },
3614     { Bad_Opcode },
3615     { Bad_Opcode },
3616     { Bad_Opcode },
3617     { "blci",   { { OP_LWP_E, 0 }, Edq }, 0 },
3618   },
3619
3620 #include "i386-dis-evex-reg.h"
3621 };
3622
3623 static const struct dis386 prefix_table[][4] = {
3624   /* PREFIX_90 */
3625   {
3626     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3627     { "pause", { XX }, 0 },
3628     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3629     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3630   },
3631
3632   /* PREFIX_0F01_REG_3_MOD_1 */
3633   {
3634     { "vmmcall",        { Skip_MODRM }, 0 },
3635     { "vmgexit",        { Skip_MODRM }, 0 },
3636     { Bad_Opcode },
3637     { "vmgexit",        { Skip_MODRM }, 0 },
3638   },
3639
3640   /* PREFIX_0F01_REG_5_MOD_0 */
3641   {
3642     { Bad_Opcode },
3643     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3644   },
3645
3646   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3647   {
3648     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3649     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3650     { Bad_Opcode },
3651     { "xsuspldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3652   },
3653
3654   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3655   {
3656     { Bad_Opcode },
3657     { Bad_Opcode },
3658     { Bad_Opcode },
3659     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3660   },
3661
3662   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3663   {
3664     { Bad_Opcode },
3665     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3666   },
3667
3668   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3669   {
3670     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3671     { "mcommit",        { Skip_MODRM }, 0 },
3672   },
3673
3674   /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3675   {
3676     { "mwaitx",         { { OP_Mwait, eBX_reg } }, 0  },
3677   },
3678
3679   /* PREFIX_0F09 */
3680   {
3681     { "wbinvd",   { XX }, 0 },
3682     { "wbnoinvd", { XX }, 0 },
3683   },
3684
3685   /* PREFIX_0F10 */
3686   {
3687     { "movups", { XM, EXx }, PREFIX_OPCODE },
3688     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3689     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3690     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3691   },
3692
3693   /* PREFIX_0F11 */
3694   {
3695     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3696     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3697     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3698     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3699   },
3700
3701   /* PREFIX_0F12 */
3702   {
3703     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3704     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3705     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3706     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3707   },
3708
3709   /* PREFIX_0F16 */
3710   {
3711     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3712     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3713     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3714   },
3715
3716   /* PREFIX_0F1A */
3717   {
3718     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3719     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3720     { "bndmov", { Gbnd, Ebnd }, 0 },
3721     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3722   },
3723
3724   /* PREFIX_0F1B */
3725   {
3726     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3727     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3728     { "bndmov", { EbndS, Gbnd }, 0 },
3729     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3730   },
3731
3732   /* PREFIX_0F1C */
3733   {
3734     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3735     { "nopQ",   { Ev }, PREFIX_OPCODE },
3736     { "nopQ",   { Ev }, PREFIX_OPCODE },
3737     { "nopQ",   { Ev }, PREFIX_OPCODE },
3738   },
3739
3740   /* PREFIX_0F1E */
3741   {
3742     { "nopQ",   { Ev }, PREFIX_OPCODE },
3743     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3744     { "nopQ",   { Ev }, PREFIX_OPCODE },
3745     { "nopQ",   { Ev }, PREFIX_OPCODE },
3746   },
3747
3748   /* PREFIX_0F2A */
3749   {
3750     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3751     { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
3752     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3753     { "cvtsi2sd%LQ", { XM, Edq }, 0 },
3754   },
3755
3756   /* PREFIX_0F2B */
3757   {
3758     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3759     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3760     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3761     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3762   },
3763
3764   /* PREFIX_0F2C */
3765   {
3766     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3767     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3768     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3769     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3770   },
3771
3772   /* PREFIX_0F2D */
3773   {
3774     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3775     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3776     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3777     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3778   },
3779
3780   /* PREFIX_0F2E */
3781   {
3782     { "ucomiss",{ XM, EXd }, 0 },
3783     { Bad_Opcode },
3784     { "ucomisd",{ XM, EXq }, 0 },
3785   },
3786
3787   /* PREFIX_0F2F */
3788   {
3789     { "comiss", { XM, EXd }, 0 },
3790     { Bad_Opcode },
3791     { "comisd", { XM, EXq }, 0 },
3792   },
3793
3794   /* PREFIX_0F51 */
3795   {
3796     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3797     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3798     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3799     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3800   },
3801
3802   /* PREFIX_0F52 */
3803   {
3804     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3805     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3806   },
3807
3808   /* PREFIX_0F53 */
3809   {
3810     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3811     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3812   },
3813
3814   /* PREFIX_0F58 */
3815   {
3816     { "addps", { XM, EXx }, PREFIX_OPCODE },
3817     { "addss", { XM, EXd }, PREFIX_OPCODE },
3818     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3819     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3820   },
3821
3822   /* PREFIX_0F59 */
3823   {
3824     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3825     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3826     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3827     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3828   },
3829
3830   /* PREFIX_0F5A */
3831   {
3832     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3833     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3834     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3835     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3836   },
3837
3838   /* PREFIX_0F5B */
3839   {
3840     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3841     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3842     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3843   },
3844
3845   /* PREFIX_0F5C */
3846   {
3847     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3848     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3849     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3850     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3851   },
3852
3853   /* PREFIX_0F5D */
3854   {
3855     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3856     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3857     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3858     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3859   },
3860
3861   /* PREFIX_0F5E */
3862   {
3863     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3864     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3865     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3866     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3867   },
3868
3869   /* PREFIX_0F5F */
3870   {
3871     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3872     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3873     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3874     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3875   },
3876
3877   /* PREFIX_0F60 */
3878   {
3879     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3880     { Bad_Opcode },
3881     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3882   },
3883
3884   /* PREFIX_0F61 */
3885   {
3886     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3887     { Bad_Opcode },
3888     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3889   },
3890
3891   /* PREFIX_0F62 */
3892   {
3893     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3894     { Bad_Opcode },
3895     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3896   },
3897
3898   /* PREFIX_0F6C */
3899   {
3900     { Bad_Opcode },
3901     { Bad_Opcode },
3902     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3903   },
3904
3905   /* PREFIX_0F6D */
3906   {
3907     { Bad_Opcode },
3908     { Bad_Opcode },
3909     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3910   },
3911
3912   /* PREFIX_0F6F */
3913   {
3914     { "movq",   { MX, EM }, PREFIX_OPCODE },
3915     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3916     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3917   },
3918
3919   /* PREFIX_0F70 */
3920   {
3921     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3922     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3923     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3924     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3925   },
3926
3927   /* PREFIX_0F73_REG_3 */
3928   {
3929     { Bad_Opcode },
3930     { Bad_Opcode },
3931     { "psrldq", { XS, Ib }, 0 },
3932   },
3933
3934   /* PREFIX_0F73_REG_7 */
3935   {
3936     { Bad_Opcode },
3937     { Bad_Opcode },
3938     { "pslldq", { XS, Ib }, 0 },
3939   },
3940
3941   /* PREFIX_0F78 */
3942   {
3943     {"vmread",  { Em, Gm }, 0 },
3944     { Bad_Opcode },
3945     {"extrq",   { XS, Ib, Ib }, 0 },
3946     {"insertq", { XM, XS, Ib, Ib }, 0 },
3947   },
3948
3949   /* PREFIX_0F79 */
3950   {
3951     {"vmwrite", { Gm, Em }, 0 },
3952     { Bad_Opcode },
3953     {"extrq",   { XM, XS }, 0 },
3954     {"insertq", { XM, XS }, 0 },
3955   },
3956
3957   /* PREFIX_0F7C */
3958   {
3959     { Bad_Opcode },
3960     { Bad_Opcode },
3961     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3962     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3963   },
3964
3965   /* PREFIX_0F7D */
3966   {
3967     { Bad_Opcode },
3968     { Bad_Opcode },
3969     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3970     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3971   },
3972
3973   /* PREFIX_0F7E */
3974   {
3975     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3976     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3977     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3978   },
3979
3980   /* PREFIX_0F7F */
3981   {
3982     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3983     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3984     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3985   },
3986
3987   /* PREFIX_0FAE_REG_0_MOD_3 */
3988   {
3989     { Bad_Opcode },
3990     { "rdfsbase", { Ev }, 0 },
3991   },
3992
3993   /* PREFIX_0FAE_REG_1_MOD_3 */
3994   {
3995     { Bad_Opcode },
3996     { "rdgsbase", { Ev }, 0 },
3997   },
3998
3999   /* PREFIX_0FAE_REG_2_MOD_3 */
4000   {
4001     { Bad_Opcode },
4002     { "wrfsbase", { Ev }, 0 },
4003   },
4004
4005   /* PREFIX_0FAE_REG_3_MOD_3 */
4006   {
4007     { Bad_Opcode },
4008     { "wrgsbase", { Ev }, 0 },
4009   },
4010
4011   /* PREFIX_0FAE_REG_4_MOD_0 */
4012   {
4013     { "xsave",  { FXSAVE }, 0 },
4014     { "ptwrite%LQ", { Edq }, 0 },
4015   },
4016
4017   /* PREFIX_0FAE_REG_4_MOD_3 */
4018   {
4019     { Bad_Opcode },
4020     { "ptwrite%LQ", { Edq }, 0 },
4021   },
4022
4023   /* PREFIX_0FAE_REG_5_MOD_0 */
4024   {
4025     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
4026   },
4027
4028   /* PREFIX_0FAE_REG_5_MOD_3 */
4029   {
4030     { "lfence",         { Skip_MODRM }, 0 },
4031     { "incsspK",        { Rdq }, PREFIX_OPCODE },
4032   },
4033
4034   /* PREFIX_0FAE_REG_6_MOD_0 */
4035   {
4036     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
4037     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
4038     { "clwb",   { Mb }, PREFIX_OPCODE },
4039   },
4040
4041   /* PREFIX_0FAE_REG_6_MOD_3 */
4042   {
4043     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
4044     { "umonitor",       { Eva }, PREFIX_OPCODE },
4045     { "tpause", { Edq }, PREFIX_OPCODE },
4046     { "umwait", { Edq }, PREFIX_OPCODE },
4047   },
4048
4049   /* PREFIX_0FAE_REG_7_MOD_0 */
4050   {
4051     { "clflush",        { Mb }, 0 },
4052     { Bad_Opcode },
4053     { "clflushopt",     { Mb }, 0 },
4054   },
4055
4056   /* PREFIX_0FB8 */
4057   {
4058     { Bad_Opcode },
4059     { "popcntS", { Gv, Ev }, 0 },
4060   },
4061
4062   /* PREFIX_0FBC */
4063   {
4064     { "bsfS",   { Gv, Ev }, 0 },
4065     { "tzcntS", { Gv, Ev }, 0 },
4066     { "bsfS",   { Gv, Ev }, 0 },
4067   },
4068
4069   /* PREFIX_0FBD */
4070   {
4071     { "bsrS",   { Gv, Ev }, 0 },
4072     { "lzcntS", { Gv, Ev }, 0 },
4073     { "bsrS",   { Gv, Ev }, 0 },
4074   },
4075
4076   /* PREFIX_0FC2 */
4077   {
4078     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4079     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4080     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4081     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4082   },
4083
4084   /* PREFIX_0FC3_MOD_0 */
4085   {
4086     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
4087   },
4088
4089   /* PREFIX_0FC7_REG_6_MOD_0 */
4090   {
4091     { "vmptrld",{ Mq }, 0 },
4092     { "vmxon",  { Mq }, 0 },
4093     { "vmclear",{ Mq }, 0 },
4094   },
4095
4096   /* PREFIX_0FC7_REG_6_MOD_3 */
4097   {
4098     { "rdrand", { Ev }, 0 },
4099     { Bad_Opcode },
4100     { "rdrand", { Ev }, 0 }
4101   },
4102
4103   /* PREFIX_0FC7_REG_7_MOD_3 */
4104   {
4105     { "rdseed", { Ev }, 0 },
4106     { "rdpid",  { Em }, 0 },
4107     { "rdseed", { Ev }, 0 },
4108   },
4109
4110   /* PREFIX_0FD0 */
4111   {
4112     { Bad_Opcode },
4113     { Bad_Opcode },
4114     { "addsubpd", { XM, EXx }, 0 },
4115     { "addsubps", { XM, EXx }, 0 },
4116   },
4117
4118   /* PREFIX_0FD6 */
4119   {
4120     { Bad_Opcode },
4121     { "movq2dq",{ XM, MS }, 0 },
4122     { "movq",   { EXqS, XM }, 0 },
4123     { "movdq2q",{ MX, XS }, 0 },
4124   },
4125
4126   /* PREFIX_0FE6 */
4127   {
4128     { Bad_Opcode },
4129     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4130     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4131     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4132   },
4133
4134   /* PREFIX_0FE7 */
4135   {
4136     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4137     { Bad_Opcode },
4138     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4139   },
4140
4141   /* PREFIX_0FF0 */
4142   {
4143     { Bad_Opcode },
4144     { Bad_Opcode },
4145     { Bad_Opcode },
4146     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4147   },
4148
4149   /* PREFIX_0FF7 */
4150   {
4151     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4152     { Bad_Opcode },
4153     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4154   },
4155
4156   /* PREFIX_0F3810 */
4157   {
4158     { Bad_Opcode },
4159     { Bad_Opcode },
4160     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4161   },
4162
4163   /* PREFIX_0F3814 */
4164   {
4165     { Bad_Opcode },
4166     { Bad_Opcode },
4167     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4168   },
4169
4170   /* PREFIX_0F3815 */
4171   {
4172     { Bad_Opcode },
4173     { Bad_Opcode },
4174     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4175   },
4176
4177   /* PREFIX_0F3817 */
4178   {
4179     { Bad_Opcode },
4180     { Bad_Opcode },
4181     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4182   },
4183
4184   /* PREFIX_0F3820 */
4185   {
4186     { Bad_Opcode },
4187     { Bad_Opcode },
4188     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4189   },
4190
4191   /* PREFIX_0F3821 */
4192   {
4193     { Bad_Opcode },
4194     { Bad_Opcode },
4195     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4196   },
4197
4198   /* PREFIX_0F3822 */
4199   {
4200     { Bad_Opcode },
4201     { Bad_Opcode },
4202     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4203   },
4204
4205   /* PREFIX_0F3823 */
4206   {
4207     { Bad_Opcode },
4208     { Bad_Opcode },
4209     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4210   },
4211
4212   /* PREFIX_0F3824 */
4213   {
4214     { Bad_Opcode },
4215     { Bad_Opcode },
4216     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4217   },
4218
4219   /* PREFIX_0F3825 */
4220   {
4221     { Bad_Opcode },
4222     { Bad_Opcode },
4223     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4224   },
4225
4226   /* PREFIX_0F3828 */
4227   {
4228     { Bad_Opcode },
4229     { Bad_Opcode },
4230     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4231   },
4232
4233   /* PREFIX_0F3829 */
4234   {
4235     { Bad_Opcode },
4236     { Bad_Opcode },
4237     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4238   },
4239
4240   /* PREFIX_0F382A */
4241   {
4242     { Bad_Opcode },
4243     { Bad_Opcode },
4244     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4245   },
4246
4247   /* PREFIX_0F382B */
4248   {
4249     { Bad_Opcode },
4250     { Bad_Opcode },
4251     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4252   },
4253
4254   /* PREFIX_0F3830 */
4255   {
4256     { Bad_Opcode },
4257     { Bad_Opcode },
4258     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4259   },
4260
4261   /* PREFIX_0F3831 */
4262   {
4263     { Bad_Opcode },
4264     { Bad_Opcode },
4265     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4266   },
4267
4268   /* PREFIX_0F3832 */
4269   {
4270     { Bad_Opcode },
4271     { Bad_Opcode },
4272     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4273   },
4274
4275   /* PREFIX_0F3833 */
4276   {
4277     { Bad_Opcode },
4278     { Bad_Opcode },
4279     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4280   },
4281
4282   /* PREFIX_0F3834 */
4283   {
4284     { Bad_Opcode },
4285     { Bad_Opcode },
4286     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4287   },
4288
4289   /* PREFIX_0F3835 */
4290   {
4291     { Bad_Opcode },
4292     { Bad_Opcode },
4293     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4294   },
4295
4296   /* PREFIX_0F3837 */
4297   {
4298     { Bad_Opcode },
4299     { Bad_Opcode },
4300     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4301   },
4302
4303   /* PREFIX_0F3838 */
4304   {
4305     { Bad_Opcode },
4306     { Bad_Opcode },
4307     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4308   },
4309
4310   /* PREFIX_0F3839 */
4311   {
4312     { Bad_Opcode },
4313     { Bad_Opcode },
4314     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4315   },
4316
4317   /* PREFIX_0F383A */
4318   {
4319     { Bad_Opcode },
4320     { Bad_Opcode },
4321     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4322   },
4323
4324   /* PREFIX_0F383B */
4325   {
4326     { Bad_Opcode },
4327     { Bad_Opcode },
4328     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4329   },
4330
4331   /* PREFIX_0F383C */
4332   {
4333     { Bad_Opcode },
4334     { Bad_Opcode },
4335     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4336   },
4337
4338   /* PREFIX_0F383D */
4339   {
4340     { Bad_Opcode },
4341     { Bad_Opcode },
4342     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4343   },
4344
4345   /* PREFIX_0F383E */
4346   {
4347     { Bad_Opcode },
4348     { Bad_Opcode },
4349     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4350   },
4351
4352   /* PREFIX_0F383F */
4353   {
4354     { Bad_Opcode },
4355     { Bad_Opcode },
4356     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4357   },
4358
4359   /* PREFIX_0F3840 */
4360   {
4361     { Bad_Opcode },
4362     { Bad_Opcode },
4363     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4364   },
4365
4366   /* PREFIX_0F3841 */
4367   {
4368     { Bad_Opcode },
4369     { Bad_Opcode },
4370     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4371   },
4372
4373   /* PREFIX_0F3880 */
4374   {
4375     { Bad_Opcode },
4376     { Bad_Opcode },
4377     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4378   },
4379
4380   /* PREFIX_0F3881 */
4381   {
4382     { Bad_Opcode },
4383     { Bad_Opcode },
4384     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4385   },
4386
4387   /* PREFIX_0F3882 */
4388   {
4389     { Bad_Opcode },
4390     { Bad_Opcode },
4391     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4392   },
4393
4394   /* PREFIX_0F38C8 */
4395   {
4396     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4397   },
4398
4399   /* PREFIX_0F38C9 */
4400   {
4401     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4402   },
4403
4404   /* PREFIX_0F38CA */
4405   {
4406     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4407   },
4408
4409   /* PREFIX_0F38CB */
4410   {
4411     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4412   },
4413
4414   /* PREFIX_0F38CC */
4415   {
4416     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4417   },
4418
4419   /* PREFIX_0F38CD */
4420   {
4421     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4422   },
4423
4424   /* PREFIX_0F38CF */
4425   {
4426     { Bad_Opcode },
4427     { Bad_Opcode },
4428     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4429   },
4430
4431   /* PREFIX_0F38DB */
4432   {
4433     { Bad_Opcode },
4434     { Bad_Opcode },
4435     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4436   },
4437
4438   /* PREFIX_0F38DC */
4439   {
4440     { Bad_Opcode },
4441     { Bad_Opcode },
4442     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4443   },
4444
4445   /* PREFIX_0F38DD */
4446   {
4447     { Bad_Opcode },
4448     { Bad_Opcode },
4449     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4450   },
4451
4452   /* PREFIX_0F38DE */
4453   {
4454     { Bad_Opcode },
4455     { Bad_Opcode },
4456     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4457   },
4458
4459   /* PREFIX_0F38DF */
4460   {
4461     { Bad_Opcode },
4462     { Bad_Opcode },
4463     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4464   },
4465
4466   /* PREFIX_0F38F0 */
4467   {
4468     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4469     { Bad_Opcode },
4470     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4471     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4472   },
4473
4474   /* PREFIX_0F38F1 */
4475   {
4476     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4477     { Bad_Opcode },
4478     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4479     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4480   },
4481
4482   /* PREFIX_0F38F5 */
4483   {
4484     { Bad_Opcode },
4485     { Bad_Opcode },
4486     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4487   },
4488
4489   /* PREFIX_0F38F6 */
4490   {
4491     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4492     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4493     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4494     { Bad_Opcode },
4495   },
4496
4497   /* PREFIX_0F38F8 */
4498   {
4499     { Bad_Opcode },
4500     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4501     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4502     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4503   },
4504
4505   /* PREFIX_0F38F9 */
4506   {
4507     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4508   },
4509
4510   /* PREFIX_0F3A08 */
4511   {
4512     { Bad_Opcode },
4513     { Bad_Opcode },
4514     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4515   },
4516
4517   /* PREFIX_0F3A09 */
4518   {
4519     { Bad_Opcode },
4520     { Bad_Opcode },
4521     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4522   },
4523
4524   /* PREFIX_0F3A0A */
4525   {
4526     { Bad_Opcode },
4527     { Bad_Opcode },
4528     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4529   },
4530
4531   /* PREFIX_0F3A0B */
4532   {
4533     { Bad_Opcode },
4534     { Bad_Opcode },
4535     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4536   },
4537
4538   /* PREFIX_0F3A0C */
4539   {
4540     { Bad_Opcode },
4541     { Bad_Opcode },
4542     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4543   },
4544
4545   /* PREFIX_0F3A0D */
4546   {
4547     { Bad_Opcode },
4548     { Bad_Opcode },
4549     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4550   },
4551
4552   /* PREFIX_0F3A0E */
4553   {
4554     { Bad_Opcode },
4555     { Bad_Opcode },
4556     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4557   },
4558
4559   /* PREFIX_0F3A14 */
4560   {
4561     { Bad_Opcode },
4562     { Bad_Opcode },
4563     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4564   },
4565
4566   /* PREFIX_0F3A15 */
4567   {
4568     { Bad_Opcode },
4569     { Bad_Opcode },
4570     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4571   },
4572
4573   /* PREFIX_0F3A16 */
4574   {
4575     { Bad_Opcode },
4576     { Bad_Opcode },
4577     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4578   },
4579
4580   /* PREFIX_0F3A17 */
4581   {
4582     { Bad_Opcode },
4583     { Bad_Opcode },
4584     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4585   },
4586
4587   /* PREFIX_0F3A20 */
4588   {
4589     { Bad_Opcode },
4590     { Bad_Opcode },
4591     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4592   },
4593
4594   /* PREFIX_0F3A21 */
4595   {
4596     { Bad_Opcode },
4597     { Bad_Opcode },
4598     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4599   },
4600
4601   /* PREFIX_0F3A22 */
4602   {
4603     { Bad_Opcode },
4604     { Bad_Opcode },
4605     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4606   },
4607
4608   /* PREFIX_0F3A40 */
4609   {
4610     { Bad_Opcode },
4611     { Bad_Opcode },
4612     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4613   },
4614
4615   /* PREFIX_0F3A41 */
4616   {
4617     { Bad_Opcode },
4618     { Bad_Opcode },
4619     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4620   },
4621
4622   /* PREFIX_0F3A42 */
4623   {
4624     { Bad_Opcode },
4625     { Bad_Opcode },
4626     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4627   },
4628
4629   /* PREFIX_0F3A44 */
4630   {
4631     { Bad_Opcode },
4632     { Bad_Opcode },
4633     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4634   },
4635
4636   /* PREFIX_0F3A60 */
4637   {
4638     { Bad_Opcode },
4639     { Bad_Opcode },
4640     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4641   },
4642
4643   /* PREFIX_0F3A61 */
4644   {
4645     { Bad_Opcode },
4646     { Bad_Opcode },
4647     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4648   },
4649
4650   /* PREFIX_0F3A62 */
4651   {
4652     { Bad_Opcode },
4653     { Bad_Opcode },
4654     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4655   },
4656
4657   /* PREFIX_0F3A63 */
4658   {
4659     { Bad_Opcode },
4660     { Bad_Opcode },
4661     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4662   },
4663
4664   /* PREFIX_0F3ACC */
4665   {
4666     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4667   },
4668
4669   /* PREFIX_0F3ACE */
4670   {
4671     { Bad_Opcode },
4672     { Bad_Opcode },
4673     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4674   },
4675
4676   /* PREFIX_0F3ACF */
4677   {
4678     { Bad_Opcode },
4679     { Bad_Opcode },
4680     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4681   },
4682
4683   /* PREFIX_0F3ADF */
4684   {
4685     { Bad_Opcode },
4686     { Bad_Opcode },
4687     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4688   },
4689
4690   /* PREFIX_VEX_0F10 */
4691   {
4692     { "vmovups",        { XM, EXx }, 0 },
4693     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
4694     { "vmovupd",        { XM, EXx }, 0 },
4695     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
4696   },
4697
4698   /* PREFIX_VEX_0F11 */
4699   {
4700     { "vmovups",        { EXxS, XM }, 0 },
4701     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4702     { "vmovupd",        { EXxS, XM }, 0 },
4703     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4704   },
4705
4706   /* PREFIX_VEX_0F12 */
4707   {
4708     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4709     { "vmovsldup",      { XM, EXx }, 0 },
4710     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4711     { "vmovddup",       { XM, EXymmq }, 0 },
4712   },
4713
4714   /* PREFIX_VEX_0F16 */
4715   {
4716     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4717     { "vmovshdup",      { XM, EXx }, 0 },
4718     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4719   },
4720
4721   /* PREFIX_VEX_0F2A */
4722   {
4723     { Bad_Opcode },
4724     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4725     { Bad_Opcode },
4726     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4727   },
4728
4729   /* PREFIX_VEX_0F2C */
4730   {
4731     { Bad_Opcode },
4732     { "vcvttss2si",     { Gdq, EXdScalar }, 0 },
4733     { Bad_Opcode },
4734     { "vcvttsd2si",     { Gdq, EXqScalar }, 0 },
4735   },
4736
4737   /* PREFIX_VEX_0F2D */
4738   {
4739     { Bad_Opcode },
4740     { "vcvtss2si",      { Gdq, EXdScalar }, 0 },
4741     { Bad_Opcode },
4742     { "vcvtsd2si",      { Gdq, EXqScalar }, 0 },
4743   },
4744
4745   /* PREFIX_VEX_0F2E */
4746   {
4747     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
4748     { Bad_Opcode },
4749     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
4750   },
4751
4752   /* PREFIX_VEX_0F2F */
4753   {
4754     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
4755     { Bad_Opcode },
4756     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
4757   },
4758
4759   /* PREFIX_VEX_0F41 */
4760   {
4761     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4762     { Bad_Opcode },
4763     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4764   },
4765
4766   /* PREFIX_VEX_0F42 */
4767   {
4768     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4769     { Bad_Opcode },
4770     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4771   },
4772
4773   /* PREFIX_VEX_0F44 */
4774   {
4775     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4776     { Bad_Opcode },
4777     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4778   },
4779
4780   /* PREFIX_VEX_0F45 */
4781   {
4782     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4783     { Bad_Opcode },
4784     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4785   },
4786
4787   /* PREFIX_VEX_0F46 */
4788   {
4789     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4790     { Bad_Opcode },
4791     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4792   },
4793
4794   /* PREFIX_VEX_0F47 */
4795   {
4796     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4797     { Bad_Opcode },
4798     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4799   },
4800
4801   /* PREFIX_VEX_0F4A */
4802   {
4803     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4804     { Bad_Opcode },
4805     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4806   },
4807
4808   /* PREFIX_VEX_0F4B */
4809   {
4810     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4811     { Bad_Opcode },
4812     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4813   },
4814
4815   /* PREFIX_VEX_0F51 */
4816   {
4817     { "vsqrtps",        { XM, EXx }, 0 },
4818     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
4819     { "vsqrtpd",        { XM, EXx }, 0 },
4820     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
4821   },
4822
4823   /* PREFIX_VEX_0F52 */
4824   {
4825     { "vrsqrtps",       { XM, EXx }, 0 },
4826     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
4827   },
4828
4829   /* PREFIX_VEX_0F53 */
4830   {
4831     { "vrcpps",         { XM, EXx }, 0 },
4832     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4833   },
4834
4835   /* PREFIX_VEX_0F58 */
4836   {
4837     { "vaddps",         { XM, Vex, EXx }, 0 },
4838     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4839     { "vaddpd",         { XM, Vex, EXx }, 0 },
4840     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4841   },
4842
4843   /* PREFIX_VEX_0F59 */
4844   {
4845     { "vmulps",         { XM, Vex, EXx }, 0 },
4846     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4847     { "vmulpd",         { XM, Vex, EXx }, 0 },
4848     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4849   },
4850
4851   /* PREFIX_VEX_0F5A */
4852   {
4853     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4854     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
4855     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4856     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
4857   },
4858
4859   /* PREFIX_VEX_0F5B */
4860   {
4861     { "vcvtdq2ps",      { XM, EXx }, 0 },
4862     { "vcvttps2dq",     { XM, EXx }, 0 },
4863     { "vcvtps2dq",      { XM, EXx }, 0 },
4864   },
4865
4866   /* PREFIX_VEX_0F5C */
4867   {
4868     { "vsubps",         { XM, Vex, EXx }, 0 },
4869     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4870     { "vsubpd",         { XM, Vex, EXx }, 0 },
4871     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4872   },
4873
4874   /* PREFIX_VEX_0F5D */
4875   {
4876     { "vminps",         { XM, Vex, EXx }, 0 },
4877     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4878     { "vminpd",         { XM, Vex, EXx }, 0 },
4879     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4880   },
4881
4882   /* PREFIX_VEX_0F5E */
4883   {
4884     { "vdivps",         { XM, Vex, EXx }, 0 },
4885     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4886     { "vdivpd",         { XM, Vex, EXx }, 0 },
4887     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4888   },
4889
4890   /* PREFIX_VEX_0F5F */
4891   {
4892     { "vmaxps",         { XM, Vex, EXx }, 0 },
4893     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4894     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4895     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4896   },
4897
4898   /* PREFIX_VEX_0F60 */
4899   {
4900     { Bad_Opcode },
4901     { Bad_Opcode },
4902     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4903   },
4904
4905   /* PREFIX_VEX_0F61 */
4906   {
4907     { Bad_Opcode },
4908     { Bad_Opcode },
4909     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4910   },
4911
4912   /* PREFIX_VEX_0F62 */
4913   {
4914     { Bad_Opcode },
4915     { Bad_Opcode },
4916     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4917   },
4918
4919   /* PREFIX_VEX_0F63 */
4920   {
4921     { Bad_Opcode },
4922     { Bad_Opcode },
4923     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4924   },
4925
4926   /* PREFIX_VEX_0F64 */
4927   {
4928     { Bad_Opcode },
4929     { Bad_Opcode },
4930     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4931   },
4932
4933   /* PREFIX_VEX_0F65 */
4934   {
4935     { Bad_Opcode },
4936     { Bad_Opcode },
4937     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4938   },
4939
4940   /* PREFIX_VEX_0F66 */
4941   {
4942     { Bad_Opcode },
4943     { Bad_Opcode },
4944     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4945   },
4946
4947   /* PREFIX_VEX_0F67 */
4948   {
4949     { Bad_Opcode },
4950     { Bad_Opcode },
4951     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4952   },
4953
4954   /* PREFIX_VEX_0F68 */
4955   {
4956     { Bad_Opcode },
4957     { Bad_Opcode },
4958     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4959   },
4960
4961   /* PREFIX_VEX_0F69 */
4962   {
4963     { Bad_Opcode },
4964     { Bad_Opcode },
4965     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4966   },
4967
4968   /* PREFIX_VEX_0F6A */
4969   {
4970     { Bad_Opcode },
4971     { Bad_Opcode },
4972     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4973   },
4974
4975   /* PREFIX_VEX_0F6B */
4976   {
4977     { Bad_Opcode },
4978     { Bad_Opcode },
4979     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4980   },
4981
4982   /* PREFIX_VEX_0F6C */
4983   {
4984     { Bad_Opcode },
4985     { Bad_Opcode },
4986     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4987   },
4988
4989   /* PREFIX_VEX_0F6D */
4990   {
4991     { Bad_Opcode },
4992     { Bad_Opcode },
4993     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4994   },
4995
4996   /* PREFIX_VEX_0F6E */
4997   {
4998     { Bad_Opcode },
4999     { Bad_Opcode },
5000     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5001   },
5002
5003   /* PREFIX_VEX_0F6F */
5004   {
5005     { Bad_Opcode },
5006     { "vmovdqu",        { XM, EXx }, 0 },
5007     { "vmovdqa",        { XM, EXx }, 0 },
5008   },
5009
5010   /* PREFIX_VEX_0F70 */
5011   {
5012     { Bad_Opcode },
5013     { "vpshufhw",       { XM, EXx, Ib }, 0 },
5014     { "vpshufd",        { XM, EXx, Ib }, 0 },
5015     { "vpshuflw",       { XM, EXx, Ib }, 0 },
5016   },
5017
5018   /* PREFIX_VEX_0F71_REG_2 */
5019   {
5020     { Bad_Opcode },
5021     { Bad_Opcode },
5022     { "vpsrlw",         { Vex, XS, Ib }, 0 },
5023   },
5024
5025   /* PREFIX_VEX_0F71_REG_4 */
5026   {
5027     { Bad_Opcode },
5028     { Bad_Opcode },
5029     { "vpsraw",         { Vex, XS, Ib }, 0 },
5030   },
5031
5032   /* PREFIX_VEX_0F71_REG_6 */
5033   {
5034     { Bad_Opcode },
5035     { Bad_Opcode },
5036     { "vpsllw",         { Vex, XS, Ib }, 0 },
5037   },
5038
5039   /* PREFIX_VEX_0F72_REG_2 */
5040   {
5041     { Bad_Opcode },
5042     { Bad_Opcode },
5043     { "vpsrld",         { Vex, XS, Ib }, 0 },
5044   },
5045
5046   /* PREFIX_VEX_0F72_REG_4 */
5047   {
5048     { Bad_Opcode },
5049     { Bad_Opcode },
5050     { "vpsrad",         { Vex, XS, Ib }, 0 },
5051   },
5052
5053   /* PREFIX_VEX_0F72_REG_6 */
5054   {
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { "vpslld",         { Vex, XS, Ib }, 0 },
5058   },
5059
5060   /* PREFIX_VEX_0F73_REG_2 */
5061   {
5062     { Bad_Opcode },
5063     { Bad_Opcode },
5064     { "vpsrlq",         { Vex, XS, Ib }, 0 },
5065   },
5066
5067   /* PREFIX_VEX_0F73_REG_3 */
5068   {
5069     { Bad_Opcode },
5070     { Bad_Opcode },
5071     { "vpsrldq",        { Vex, XS, Ib }, 0 },
5072   },
5073
5074   /* PREFIX_VEX_0F73_REG_6 */
5075   {
5076     { Bad_Opcode },
5077     { Bad_Opcode },
5078     { "vpsllq",         { Vex, XS, Ib }, 0 },
5079   },
5080
5081   /* PREFIX_VEX_0F73_REG_7 */
5082   {
5083     { Bad_Opcode },
5084     { Bad_Opcode },
5085     { "vpslldq",        { Vex, XS, Ib }, 0 },
5086   },
5087
5088   /* PREFIX_VEX_0F74 */
5089   {
5090     { Bad_Opcode },
5091     { Bad_Opcode },
5092     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
5093   },
5094
5095   /* PREFIX_VEX_0F75 */
5096   {
5097     { Bad_Opcode },
5098     { Bad_Opcode },
5099     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5100   },
5101
5102   /* PREFIX_VEX_0F76 */
5103   {
5104     { Bad_Opcode },
5105     { Bad_Opcode },
5106     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5107   },
5108
5109   /* PREFIX_VEX_0F77 */
5110   {
5111     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5112   },
5113
5114   /* PREFIX_VEX_0F7C */
5115   {
5116     { Bad_Opcode },
5117     { Bad_Opcode },
5118     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5119     { "vhaddps",        { XM, Vex, EXx }, 0 },
5120   },
5121
5122   /* PREFIX_VEX_0F7D */
5123   {
5124     { Bad_Opcode },
5125     { Bad_Opcode },
5126     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5127     { "vhsubps",        { XM, Vex, EXx }, 0 },
5128   },
5129
5130   /* PREFIX_VEX_0F7E */
5131   {
5132     { Bad_Opcode },
5133     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5134     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5135   },
5136
5137   /* PREFIX_VEX_0F7F */
5138   {
5139     { Bad_Opcode },
5140     { "vmovdqu",        { EXxS, XM }, 0 },
5141     { "vmovdqa",        { EXxS, XM }, 0 },
5142   },
5143
5144   /* PREFIX_VEX_0F90 */
5145   {
5146     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5147     { Bad_Opcode },
5148     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5149   },
5150
5151   /* PREFIX_VEX_0F91 */
5152   {
5153     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5154     { Bad_Opcode },
5155     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5156   },
5157
5158   /* PREFIX_VEX_0F92 */
5159   {
5160     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5161     { Bad_Opcode },
5162     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5163     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5164   },
5165
5166   /* PREFIX_VEX_0F93 */
5167   {
5168     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5169     { Bad_Opcode },
5170     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5171     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5172   },
5173
5174   /* PREFIX_VEX_0F98 */
5175   {
5176     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5177     { Bad_Opcode },
5178     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5179   },
5180
5181   /* PREFIX_VEX_0F99 */
5182   {
5183     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5184     { Bad_Opcode },
5185     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5186   },
5187
5188   /* PREFIX_VEX_0FC2 */
5189   {
5190     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5191     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
5192     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5193     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
5194   },
5195
5196   /* PREFIX_VEX_0FC4 */
5197   {
5198     { Bad_Opcode },
5199     { Bad_Opcode },
5200     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5201   },
5202
5203   /* PREFIX_VEX_0FC5 */
5204   {
5205     { Bad_Opcode },
5206     { Bad_Opcode },
5207     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5208   },
5209
5210   /* PREFIX_VEX_0FD0 */
5211   {
5212     { Bad_Opcode },
5213     { Bad_Opcode },
5214     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5215     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5216   },
5217
5218   /* PREFIX_VEX_0FD1 */
5219   {
5220     { Bad_Opcode },
5221     { Bad_Opcode },
5222     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5223   },
5224
5225   /* PREFIX_VEX_0FD2 */
5226   {
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5230   },
5231
5232   /* PREFIX_VEX_0FD3 */
5233   {
5234     { Bad_Opcode },
5235     { Bad_Opcode },
5236     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5237   },
5238
5239   /* PREFIX_VEX_0FD4 */
5240   {
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { "vpaddq",         { XM, Vex, EXx }, 0 },
5244   },
5245
5246   /* PREFIX_VEX_0FD5 */
5247   {
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { "vpmullw",        { XM, Vex, EXx }, 0 },
5251   },
5252
5253   /* PREFIX_VEX_0FD6 */
5254   {
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5258   },
5259
5260   /* PREFIX_VEX_0FD7 */
5261   {
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5265   },
5266
5267   /* PREFIX_VEX_0FD8 */
5268   {
5269     { Bad_Opcode },
5270     { Bad_Opcode },
5271     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5272   },
5273
5274   /* PREFIX_VEX_0FD9 */
5275   {
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5279   },
5280
5281   /* PREFIX_VEX_0FDA */
5282   {
5283     { Bad_Opcode },
5284     { Bad_Opcode },
5285     { "vpminub",        { XM, Vex, EXx }, 0 },
5286   },
5287
5288   /* PREFIX_VEX_0FDB */
5289   {
5290     { Bad_Opcode },
5291     { Bad_Opcode },
5292     { "vpand",          { XM, Vex, EXx }, 0 },
5293   },
5294
5295   /* PREFIX_VEX_0FDC */
5296   {
5297     { Bad_Opcode },
5298     { Bad_Opcode },
5299     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5300   },
5301
5302   /* PREFIX_VEX_0FDD */
5303   {
5304     { Bad_Opcode },
5305     { Bad_Opcode },
5306     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5307   },
5308
5309   /* PREFIX_VEX_0FDE */
5310   {
5311     { Bad_Opcode },
5312     { Bad_Opcode },
5313     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5314   },
5315
5316   /* PREFIX_VEX_0FDF */
5317   {
5318     { Bad_Opcode },
5319     { Bad_Opcode },
5320     { "vpandn",         { XM, Vex, EXx }, 0 },
5321   },
5322
5323   /* PREFIX_VEX_0FE0 */
5324   {
5325     { Bad_Opcode },
5326     { Bad_Opcode },
5327     { "vpavgb",         { XM, Vex, EXx }, 0 },
5328   },
5329
5330   /* PREFIX_VEX_0FE1 */
5331   {
5332     { Bad_Opcode },
5333     { Bad_Opcode },
5334     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5335   },
5336
5337   /* PREFIX_VEX_0FE2 */
5338   {
5339     { Bad_Opcode },
5340     { Bad_Opcode },
5341     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5342   },
5343
5344   /* PREFIX_VEX_0FE3 */
5345   {
5346     { Bad_Opcode },
5347     { Bad_Opcode },
5348     { "vpavgw",         { XM, Vex, EXx }, 0 },
5349   },
5350
5351   /* PREFIX_VEX_0FE4 */
5352   {
5353     { Bad_Opcode },
5354     { Bad_Opcode },
5355     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5356   },
5357
5358   /* PREFIX_VEX_0FE5 */
5359   {
5360     { Bad_Opcode },
5361     { Bad_Opcode },
5362     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5363   },
5364
5365   /* PREFIX_VEX_0FE6 */
5366   {
5367     { Bad_Opcode },
5368     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5369     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5370     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5371   },
5372
5373   /* PREFIX_VEX_0FE7 */
5374   {
5375     { Bad_Opcode },
5376     { Bad_Opcode },
5377     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5378   },
5379
5380   /* PREFIX_VEX_0FE8 */
5381   {
5382     { Bad_Opcode },
5383     { Bad_Opcode },
5384     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5385   },
5386
5387   /* PREFIX_VEX_0FE9 */
5388   {
5389     { Bad_Opcode },
5390     { Bad_Opcode },
5391     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5392   },
5393
5394   /* PREFIX_VEX_0FEA */
5395   {
5396     { Bad_Opcode },
5397     { Bad_Opcode },
5398     { "vpminsw",        { XM, Vex, EXx }, 0 },
5399   },
5400
5401   /* PREFIX_VEX_0FEB */
5402   {
5403     { Bad_Opcode },
5404     { Bad_Opcode },
5405     { "vpor",           { XM, Vex, EXx }, 0 },
5406   },
5407
5408   /* PREFIX_VEX_0FEC */
5409   {
5410     { Bad_Opcode },
5411     { Bad_Opcode },
5412     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5413   },
5414
5415   /* PREFIX_VEX_0FED */
5416   {
5417     { Bad_Opcode },
5418     { Bad_Opcode },
5419     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5420   },
5421
5422   /* PREFIX_VEX_0FEE */
5423   {
5424     { Bad_Opcode },
5425     { Bad_Opcode },
5426     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5427   },
5428
5429   /* PREFIX_VEX_0FEF */
5430   {
5431     { Bad_Opcode },
5432     { Bad_Opcode },
5433     { "vpxor",          { XM, Vex, EXx }, 0 },
5434   },
5435
5436   /* PREFIX_VEX_0FF0 */
5437   {
5438     { Bad_Opcode },
5439     { Bad_Opcode },
5440     { Bad_Opcode },
5441     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5442   },
5443
5444   /* PREFIX_VEX_0FF1 */
5445   {
5446     { Bad_Opcode },
5447     { Bad_Opcode },
5448     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5449   },
5450
5451   /* PREFIX_VEX_0FF2 */
5452   {
5453     { Bad_Opcode },
5454     { Bad_Opcode },
5455     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5456   },
5457
5458   /* PREFIX_VEX_0FF3 */
5459   {
5460     { Bad_Opcode },
5461     { Bad_Opcode },
5462     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5463   },
5464
5465   /* PREFIX_VEX_0FF4 */
5466   {
5467     { Bad_Opcode },
5468     { Bad_Opcode },
5469     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5470   },
5471
5472   /* PREFIX_VEX_0FF5 */
5473   {
5474     { Bad_Opcode },
5475     { Bad_Opcode },
5476     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5477   },
5478
5479   /* PREFIX_VEX_0FF6 */
5480   {
5481     { Bad_Opcode },
5482     { Bad_Opcode },
5483     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5484   },
5485
5486   /* PREFIX_VEX_0FF7 */
5487   {
5488     { Bad_Opcode },
5489     { Bad_Opcode },
5490     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5491   },
5492
5493   /* PREFIX_VEX_0FF8 */
5494   {
5495     { Bad_Opcode },
5496     { Bad_Opcode },
5497     { "vpsubb",         { XM, Vex, EXx }, 0 },
5498   },
5499
5500   /* PREFIX_VEX_0FF9 */
5501   {
5502     { Bad_Opcode },
5503     { Bad_Opcode },
5504     { "vpsubw",         { XM, Vex, EXx }, 0 },
5505   },
5506
5507   /* PREFIX_VEX_0FFA */
5508   {
5509     { Bad_Opcode },
5510     { Bad_Opcode },
5511     { "vpsubd",         { XM, Vex, EXx }, 0 },
5512   },
5513
5514   /* PREFIX_VEX_0FFB */
5515   {
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     { "vpsubq",         { XM, Vex, EXx }, 0 },
5519   },
5520
5521   /* PREFIX_VEX_0FFC */
5522   {
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     { "vpaddb",         { XM, Vex, EXx }, 0 },
5526   },
5527
5528   /* PREFIX_VEX_0FFD */
5529   {
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     { "vpaddw",         { XM, Vex, EXx }, 0 },
5533   },
5534
5535   /* PREFIX_VEX_0FFE */
5536   {
5537     { Bad_Opcode },
5538     { Bad_Opcode },
5539     { "vpaddd",         { XM, Vex, EXx }, 0 },
5540   },
5541
5542   /* PREFIX_VEX_0F3800 */
5543   {
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     { "vpshufb",        { XM, Vex, EXx }, 0 },
5547   },
5548
5549   /* PREFIX_VEX_0F3801 */
5550   {
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { "vphaddw",        { XM, Vex, EXx }, 0 },
5554   },
5555
5556   /* PREFIX_VEX_0F3802 */
5557   {
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { "vphaddd",        { XM, Vex, EXx }, 0 },
5561   },
5562
5563   /* PREFIX_VEX_0F3803 */
5564   {
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5568   },
5569
5570   /* PREFIX_VEX_0F3804 */
5571   {
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5575   },
5576
5577   /* PREFIX_VEX_0F3805 */
5578   {
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { "vphsubw",        { XM, Vex, EXx }, 0 },
5582   },
5583
5584   /* PREFIX_VEX_0F3806 */
5585   {
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { "vphsubd",        { XM, Vex, EXx }, 0 },
5589   },
5590
5591   /* PREFIX_VEX_0F3807 */
5592   {
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5596   },
5597
5598   /* PREFIX_VEX_0F3808 */
5599   {
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { "vpsignb",        { XM, Vex, EXx }, 0 },
5603   },
5604
5605   /* PREFIX_VEX_0F3809 */
5606   {
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     { "vpsignw",        { XM, Vex, EXx }, 0 },
5610   },
5611
5612   /* PREFIX_VEX_0F380A */
5613   {
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { "vpsignd",        { XM, Vex, EXx }, 0 },
5617   },
5618
5619   /* PREFIX_VEX_0F380B */
5620   {
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5624   },
5625
5626   /* PREFIX_VEX_0F380C */
5627   {
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5631   },
5632
5633   /* PREFIX_VEX_0F380D */
5634   {
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5638   },
5639
5640   /* PREFIX_VEX_0F380E */
5641   {
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5645   },
5646
5647   /* PREFIX_VEX_0F380F */
5648   {
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5652   },
5653
5654   /* PREFIX_VEX_0F3813 */
5655   {
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5659   },
5660
5661   /* PREFIX_VEX_0F3816 */
5662   {
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5666   },
5667
5668   /* PREFIX_VEX_0F3817 */
5669   {
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     { "vptest",         { XM, EXx }, 0 },
5673   },
5674
5675   /* PREFIX_VEX_0F3818 */
5676   {
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5680   },
5681
5682   /* PREFIX_VEX_0F3819 */
5683   {
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5687   },
5688
5689   /* PREFIX_VEX_0F381A */
5690   {
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5694   },
5695
5696   /* PREFIX_VEX_0F381C */
5697   {
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { "vpabsb",         { XM, EXx }, 0 },
5701   },
5702
5703   /* PREFIX_VEX_0F381D */
5704   {
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { "vpabsw",         { XM, EXx }, 0 },
5708   },
5709
5710   /* PREFIX_VEX_0F381E */
5711   {
5712     { Bad_Opcode },
5713     { Bad_Opcode },
5714     { "vpabsd",         { XM, EXx }, 0 },
5715   },
5716
5717   /* PREFIX_VEX_0F3820 */
5718   {
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5722   },
5723
5724   /* PREFIX_VEX_0F3821 */
5725   {
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5729   },
5730
5731   /* PREFIX_VEX_0F3822 */
5732   {
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5736   },
5737
5738   /* PREFIX_VEX_0F3823 */
5739   {
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5743   },
5744
5745   /* PREFIX_VEX_0F3824 */
5746   {
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5750   },
5751
5752   /* PREFIX_VEX_0F3825 */
5753   {
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5757   },
5758
5759   /* PREFIX_VEX_0F3828 */
5760   {
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5764   },
5765
5766   /* PREFIX_VEX_0F3829 */
5767   {
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5771   },
5772
5773   /* PREFIX_VEX_0F382A */
5774   {
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5778   },
5779
5780   /* PREFIX_VEX_0F382B */
5781   {
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5785   },
5786
5787   /* PREFIX_VEX_0F382C */
5788   {
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5792   },
5793
5794   /* PREFIX_VEX_0F382D */
5795   {
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5799   },
5800
5801   /* PREFIX_VEX_0F382E */
5802   {
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5806   },
5807
5808   /* PREFIX_VEX_0F382F */
5809   {
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5813   },
5814
5815   /* PREFIX_VEX_0F3830 */
5816   {
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5820   },
5821
5822   /* PREFIX_VEX_0F3831 */
5823   {
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5827   },
5828
5829   /* PREFIX_VEX_0F3832 */
5830   {
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5834   },
5835
5836   /* PREFIX_VEX_0F3833 */
5837   {
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5841   },
5842
5843   /* PREFIX_VEX_0F3834 */
5844   {
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5848   },
5849
5850   /* PREFIX_VEX_0F3835 */
5851   {
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5855   },
5856
5857   /* PREFIX_VEX_0F3836 */
5858   {
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5862   },
5863
5864   /* PREFIX_VEX_0F3837 */
5865   {
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5869   },
5870
5871   /* PREFIX_VEX_0F3838 */
5872   {
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { "vpminsb",        { XM, Vex, EXx }, 0 },
5876   },
5877
5878   /* PREFIX_VEX_0F3839 */
5879   {
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     { "vpminsd",        { XM, Vex, EXx }, 0 },
5883   },
5884
5885   /* PREFIX_VEX_0F383A */
5886   {
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     { "vpminuw",        { XM, Vex, EXx }, 0 },
5890   },
5891
5892   /* PREFIX_VEX_0F383B */
5893   {
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { "vpminud",        { XM, Vex, EXx }, 0 },
5897   },
5898
5899   /* PREFIX_VEX_0F383C */
5900   {
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5904   },
5905
5906   /* PREFIX_VEX_0F383D */
5907   {
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5911   },
5912
5913   /* PREFIX_VEX_0F383E */
5914   {
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5918   },
5919
5920   /* PREFIX_VEX_0F383F */
5921   {
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5925   },
5926
5927   /* PREFIX_VEX_0F3840 */
5928   {
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { "vpmulld",        { XM, Vex, EXx }, 0 },
5932   },
5933
5934   /* PREFIX_VEX_0F3841 */
5935   {
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5939   },
5940
5941   /* PREFIX_VEX_0F3845 */
5942   {
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5946   },
5947
5948   /* PREFIX_VEX_0F3846 */
5949   {
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5953   },
5954
5955   /* PREFIX_VEX_0F3847 */
5956   {
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5960   },
5961
5962   /* PREFIX_VEX_0F3858 */
5963   {
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5967   },
5968
5969   /* PREFIX_VEX_0F3859 */
5970   {
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5974   },
5975
5976   /* PREFIX_VEX_0F385A */
5977   {
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5981   },
5982
5983   /* PREFIX_VEX_0F3878 */
5984   {
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5988   },
5989
5990   /* PREFIX_VEX_0F3879 */
5991   {
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5995   },
5996
5997   /* PREFIX_VEX_0F388C */
5998   {
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6002   },
6003
6004   /* PREFIX_VEX_0F388E */
6005   {
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6009   },
6010
6011   /* PREFIX_VEX_0F3890 */
6012   {
6013     { Bad_Opcode },
6014     { Bad_Opcode },
6015     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6016   },
6017
6018   /* PREFIX_VEX_0F3891 */
6019   {
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6023   },
6024
6025   /* PREFIX_VEX_0F3892 */
6026   {
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6030   },
6031
6032   /* PREFIX_VEX_0F3893 */
6033   {
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6037   },
6038
6039   /* PREFIX_VEX_0F3896 */
6040   {
6041     { Bad_Opcode },
6042     { Bad_Opcode },
6043     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6044   },
6045
6046   /* PREFIX_VEX_0F3897 */
6047   {
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6051   },
6052
6053   /* PREFIX_VEX_0F3898 */
6054   {
6055     { Bad_Opcode },
6056     { Bad_Opcode },
6057     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6058   },
6059
6060   /* PREFIX_VEX_0F3899 */
6061   {
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6065   },
6066
6067   /* PREFIX_VEX_0F389A */
6068   {
6069     { Bad_Opcode },
6070     { Bad_Opcode },
6071     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6072   },
6073
6074   /* PREFIX_VEX_0F389B */
6075   {
6076     { Bad_Opcode },
6077     { Bad_Opcode },
6078     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6079   },
6080
6081   /* PREFIX_VEX_0F389C */
6082   {
6083     { Bad_Opcode },
6084     { Bad_Opcode },
6085     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6086   },
6087
6088   /* PREFIX_VEX_0F389D */
6089   {
6090     { Bad_Opcode },
6091     { Bad_Opcode },
6092     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6093   },
6094
6095   /* PREFIX_VEX_0F389E */
6096   {
6097     { Bad_Opcode },
6098     { Bad_Opcode },
6099     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6100   },
6101
6102   /* PREFIX_VEX_0F389F */
6103   {
6104     { Bad_Opcode },
6105     { Bad_Opcode },
6106     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6107   },
6108
6109   /* PREFIX_VEX_0F38A6 */
6110   {
6111     { Bad_Opcode },
6112     { Bad_Opcode },
6113     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6114     { Bad_Opcode },
6115   },
6116
6117   /* PREFIX_VEX_0F38A7 */
6118   {
6119     { Bad_Opcode },
6120     { Bad_Opcode },
6121     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6122   },
6123
6124   /* PREFIX_VEX_0F38A8 */
6125   {
6126     { Bad_Opcode },
6127     { Bad_Opcode },
6128     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6129   },
6130
6131   /* PREFIX_VEX_0F38A9 */
6132   {
6133     { Bad_Opcode },
6134     { Bad_Opcode },
6135     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6136   },
6137
6138   /* PREFIX_VEX_0F38AA */
6139   {
6140     { Bad_Opcode },
6141     { Bad_Opcode },
6142     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6143   },
6144
6145   /* PREFIX_VEX_0F38AB */
6146   {
6147     { Bad_Opcode },
6148     { Bad_Opcode },
6149     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6150   },
6151
6152   /* PREFIX_VEX_0F38AC */
6153   {
6154     { Bad_Opcode },
6155     { Bad_Opcode },
6156     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6157   },
6158
6159   /* PREFIX_VEX_0F38AD */
6160   {
6161     { Bad_Opcode },
6162     { Bad_Opcode },
6163     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6164   },
6165
6166   /* PREFIX_VEX_0F38AE */
6167   {
6168     { Bad_Opcode },
6169     { Bad_Opcode },
6170     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6171   },
6172
6173   /* PREFIX_VEX_0F38AF */
6174   {
6175     { Bad_Opcode },
6176     { Bad_Opcode },
6177     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6178   },
6179
6180   /* PREFIX_VEX_0F38B6 */
6181   {
6182     { Bad_Opcode },
6183     { Bad_Opcode },
6184     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6185   },
6186
6187   /* PREFIX_VEX_0F38B7 */
6188   {
6189     { Bad_Opcode },
6190     { Bad_Opcode },
6191     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6192   },
6193
6194   /* PREFIX_VEX_0F38B8 */
6195   {
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6199   },
6200
6201   /* PREFIX_VEX_0F38B9 */
6202   {
6203     { Bad_Opcode },
6204     { Bad_Opcode },
6205     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6206   },
6207
6208   /* PREFIX_VEX_0F38BA */
6209   {
6210     { Bad_Opcode },
6211     { Bad_Opcode },
6212     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6213   },
6214
6215   /* PREFIX_VEX_0F38BB */
6216   {
6217     { Bad_Opcode },
6218     { Bad_Opcode },
6219     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6220   },
6221
6222   /* PREFIX_VEX_0F38BC */
6223   {
6224     { Bad_Opcode },
6225     { Bad_Opcode },
6226     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6227   },
6228
6229   /* PREFIX_VEX_0F38BD */
6230   {
6231     { Bad_Opcode },
6232     { Bad_Opcode },
6233     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6234   },
6235
6236   /* PREFIX_VEX_0F38BE */
6237   {
6238     { Bad_Opcode },
6239     { Bad_Opcode },
6240     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6241   },
6242
6243   /* PREFIX_VEX_0F38BF */
6244   {
6245     { Bad_Opcode },
6246     { Bad_Opcode },
6247     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6248   },
6249
6250   /* PREFIX_VEX_0F38CF */
6251   {
6252     { Bad_Opcode },
6253     { Bad_Opcode },
6254     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6255   },
6256
6257   /* PREFIX_VEX_0F38DB */
6258   {
6259     { Bad_Opcode },
6260     { Bad_Opcode },
6261     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6262   },
6263
6264   /* PREFIX_VEX_0F38DC */
6265   {
6266     { Bad_Opcode },
6267     { Bad_Opcode },
6268     { "vaesenc",        { XM, Vex, EXx }, 0 },
6269   },
6270
6271   /* PREFIX_VEX_0F38DD */
6272   {
6273     { Bad_Opcode },
6274     { Bad_Opcode },
6275     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6276   },
6277
6278   /* PREFIX_VEX_0F38DE */
6279   {
6280     { Bad_Opcode },
6281     { Bad_Opcode },
6282     { "vaesdec",        { XM, Vex, EXx }, 0 },
6283   },
6284
6285   /* PREFIX_VEX_0F38DF */
6286   {
6287     { Bad_Opcode },
6288     { Bad_Opcode },
6289     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6290   },
6291
6292   /* PREFIX_VEX_0F38F2 */
6293   {
6294     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6295   },
6296
6297   /* PREFIX_VEX_0F38F3_REG_1 */
6298   {
6299     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6300   },
6301
6302   /* PREFIX_VEX_0F38F3_REG_2 */
6303   {
6304     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6305   },
6306
6307   /* PREFIX_VEX_0F38F3_REG_3 */
6308   {
6309     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6310   },
6311
6312   /* PREFIX_VEX_0F38F5 */
6313   {
6314     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6315     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6316     { Bad_Opcode },
6317     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6318   },
6319
6320   /* PREFIX_VEX_0F38F6 */
6321   {
6322     { Bad_Opcode },
6323     { Bad_Opcode },
6324     { Bad_Opcode },
6325     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6326   },
6327
6328   /* PREFIX_VEX_0F38F7 */
6329   {
6330     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6331     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6332     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6333     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6334   },
6335
6336   /* PREFIX_VEX_0F3A00 */
6337   {
6338     { Bad_Opcode },
6339     { Bad_Opcode },
6340     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6341   },
6342
6343   /* PREFIX_VEX_0F3A01 */
6344   {
6345     { Bad_Opcode },
6346     { Bad_Opcode },
6347     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6348   },
6349
6350   /* PREFIX_VEX_0F3A02 */
6351   {
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6355   },
6356
6357   /* PREFIX_VEX_0F3A04 */
6358   {
6359     { Bad_Opcode },
6360     { Bad_Opcode },
6361     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6362   },
6363
6364   /* PREFIX_VEX_0F3A05 */
6365   {
6366     { Bad_Opcode },
6367     { Bad_Opcode },
6368     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6369   },
6370
6371   /* PREFIX_VEX_0F3A06 */
6372   {
6373     { Bad_Opcode },
6374     { Bad_Opcode },
6375     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6376   },
6377
6378   /* PREFIX_VEX_0F3A08 */
6379   {
6380     { Bad_Opcode },
6381     { Bad_Opcode },
6382     { "vroundps",       { XM, EXx, Ib }, 0 },
6383   },
6384
6385   /* PREFIX_VEX_0F3A09 */
6386   {
6387     { Bad_Opcode },
6388     { Bad_Opcode },
6389     { "vroundpd",       { XM, EXx, Ib }, 0 },
6390   },
6391
6392   /* PREFIX_VEX_0F3A0A */
6393   {
6394     { Bad_Opcode },
6395     { Bad_Opcode },
6396     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
6397   },
6398
6399   /* PREFIX_VEX_0F3A0B */
6400   {
6401     { Bad_Opcode },
6402     { Bad_Opcode },
6403     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
6404   },
6405
6406   /* PREFIX_VEX_0F3A0C */
6407   {
6408     { Bad_Opcode },
6409     { Bad_Opcode },
6410     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6411   },
6412
6413   /* PREFIX_VEX_0F3A0D */
6414   {
6415     { Bad_Opcode },
6416     { Bad_Opcode },
6417     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6418   },
6419
6420   /* PREFIX_VEX_0F3A0E */
6421   {
6422     { Bad_Opcode },
6423     { Bad_Opcode },
6424     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6425   },
6426
6427   /* PREFIX_VEX_0F3A0F */
6428   {
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6432   },
6433
6434   /* PREFIX_VEX_0F3A14 */
6435   {
6436     { Bad_Opcode },
6437     { Bad_Opcode },
6438     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6439   },
6440
6441   /* PREFIX_VEX_0F3A15 */
6442   {
6443     { Bad_Opcode },
6444     { Bad_Opcode },
6445     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6446   },
6447
6448   /* PREFIX_VEX_0F3A16 */
6449   {
6450     { Bad_Opcode },
6451     { Bad_Opcode },
6452     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6453   },
6454
6455   /* PREFIX_VEX_0F3A17 */
6456   {
6457     { Bad_Opcode },
6458     { Bad_Opcode },
6459     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6460   },
6461
6462   /* PREFIX_VEX_0F3A18 */
6463   {
6464     { Bad_Opcode },
6465     { Bad_Opcode },
6466     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6467   },
6468
6469   /* PREFIX_VEX_0F3A19 */
6470   {
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6474   },
6475
6476   /* PREFIX_VEX_0F3A1D */
6477   {
6478     { Bad_Opcode },
6479     { Bad_Opcode },
6480     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6481   },
6482
6483   /* PREFIX_VEX_0F3A20 */
6484   {
6485     { Bad_Opcode },
6486     { Bad_Opcode },
6487     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6488   },
6489
6490   /* PREFIX_VEX_0F3A21 */
6491   {
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6495   },
6496
6497   /* PREFIX_VEX_0F3A22 */
6498   {
6499     { Bad_Opcode },
6500     { Bad_Opcode },
6501     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6502   },
6503
6504   /* PREFIX_VEX_0F3A30 */
6505   {
6506     { Bad_Opcode },
6507     { Bad_Opcode },
6508     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6509   },
6510
6511   /* PREFIX_VEX_0F3A31 */
6512   {
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6516   },
6517
6518   /* PREFIX_VEX_0F3A32 */
6519   {
6520     { Bad_Opcode },
6521     { Bad_Opcode },
6522     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6523   },
6524
6525   /* PREFIX_VEX_0F3A33 */
6526   {
6527     { Bad_Opcode },
6528     { Bad_Opcode },
6529     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6530   },
6531
6532   /* PREFIX_VEX_0F3A38 */
6533   {
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6537   },
6538
6539   /* PREFIX_VEX_0F3A39 */
6540   {
6541     { Bad_Opcode },
6542     { Bad_Opcode },
6543     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6544   },
6545
6546   /* PREFIX_VEX_0F3A40 */
6547   {
6548     { Bad_Opcode },
6549     { Bad_Opcode },
6550     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6551   },
6552
6553   /* PREFIX_VEX_0F3A41 */
6554   {
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6558   },
6559
6560   /* PREFIX_VEX_0F3A42 */
6561   {
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6565   },
6566
6567   /* PREFIX_VEX_0F3A44 */
6568   {
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6572   },
6573
6574   /* PREFIX_VEX_0F3A46 */
6575   {
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6579   },
6580
6581   /* PREFIX_VEX_0F3A48 */
6582   {
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6586   },
6587
6588   /* PREFIX_VEX_0F3A49 */
6589   {
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6593   },
6594
6595   /* PREFIX_VEX_0F3A4A */
6596   {
6597     { Bad_Opcode },
6598     { Bad_Opcode },
6599     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6600   },
6601
6602   /* PREFIX_VEX_0F3A4B */
6603   {
6604     { Bad_Opcode },
6605     { Bad_Opcode },
6606     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6607   },
6608
6609   /* PREFIX_VEX_0F3A4C */
6610   {
6611     { Bad_Opcode },
6612     { Bad_Opcode },
6613     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6614   },
6615
6616   /* PREFIX_VEX_0F3A5C */
6617   {
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6621   },
6622
6623   /* PREFIX_VEX_0F3A5D */
6624   {
6625     { Bad_Opcode },
6626     { Bad_Opcode },
6627     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6628   },
6629
6630   /* PREFIX_VEX_0F3A5E */
6631   {
6632     { Bad_Opcode },
6633     { Bad_Opcode },
6634     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6635   },
6636
6637   /* PREFIX_VEX_0F3A5F */
6638   {
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6642   },
6643
6644   /* PREFIX_VEX_0F3A60 */
6645   {
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6649     { Bad_Opcode },
6650   },
6651
6652   /* PREFIX_VEX_0F3A61 */
6653   {
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6657   },
6658
6659   /* PREFIX_VEX_0F3A62 */
6660   {
6661     { Bad_Opcode },
6662     { Bad_Opcode },
6663     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6664   },
6665
6666   /* PREFIX_VEX_0F3A63 */
6667   {
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6671   },
6672
6673   /* PREFIX_VEX_0F3A68 */
6674   {
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6678   },
6679
6680   /* PREFIX_VEX_0F3A69 */
6681   {
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6685   },
6686
6687   /* PREFIX_VEX_0F3A6A */
6688   {
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6692   },
6693
6694   /* PREFIX_VEX_0F3A6B */
6695   {
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6699   },
6700
6701   /* PREFIX_VEX_0F3A6C */
6702   {
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6706   },
6707
6708   /* PREFIX_VEX_0F3A6D */
6709   {
6710     { Bad_Opcode },
6711     { Bad_Opcode },
6712     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6713   },
6714
6715   /* PREFIX_VEX_0F3A6E */
6716   {
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6720   },
6721
6722   /* PREFIX_VEX_0F3A6F */
6723   {
6724     { Bad_Opcode },
6725     { Bad_Opcode },
6726     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6727   },
6728
6729   /* PREFIX_VEX_0F3A78 */
6730   {
6731     { Bad_Opcode },
6732     { Bad_Opcode },
6733     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6734   },
6735
6736   /* PREFIX_VEX_0F3A79 */
6737   {
6738     { Bad_Opcode },
6739     { Bad_Opcode },
6740     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6741   },
6742
6743   /* PREFIX_VEX_0F3A7A */
6744   {
6745     { Bad_Opcode },
6746     { Bad_Opcode },
6747     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6748   },
6749
6750   /* PREFIX_VEX_0F3A7B */
6751   {
6752     { Bad_Opcode },
6753     { Bad_Opcode },
6754     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6755   },
6756
6757   /* PREFIX_VEX_0F3A7C */
6758   {
6759     { Bad_Opcode },
6760     { Bad_Opcode },
6761     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6762     { Bad_Opcode },
6763   },
6764
6765   /* PREFIX_VEX_0F3A7D */
6766   {
6767     { Bad_Opcode },
6768     { Bad_Opcode },
6769     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6770   },
6771
6772   /* PREFIX_VEX_0F3A7E */
6773   {
6774     { Bad_Opcode },
6775     { Bad_Opcode },
6776     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6777   },
6778
6779   /* PREFIX_VEX_0F3A7F */
6780   {
6781     { Bad_Opcode },
6782     { Bad_Opcode },
6783     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6784   },
6785
6786   /* PREFIX_VEX_0F3ACE */
6787   {
6788     { Bad_Opcode },
6789     { Bad_Opcode },
6790     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6791   },
6792
6793   /* PREFIX_VEX_0F3ACF */
6794   {
6795     { Bad_Opcode },
6796     { Bad_Opcode },
6797     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6798   },
6799
6800   /* PREFIX_VEX_0F3ADF */
6801   {
6802     { Bad_Opcode },
6803     { Bad_Opcode },
6804     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6805   },
6806
6807   /* PREFIX_VEX_0F3AF0 */
6808   {
6809     { Bad_Opcode },
6810     { Bad_Opcode },
6811     { Bad_Opcode },
6812     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6813   },
6814
6815 #include "i386-dis-evex-prefix.h"
6816 };
6817
6818 static const struct dis386 x86_64_table[][2] = {
6819   /* X86_64_06 */
6820   {
6821     { "pushP", { es }, 0 },
6822   },
6823
6824   /* X86_64_07 */
6825   {
6826     { "popP", { es }, 0 },
6827   },
6828
6829   /* X86_64_0E */
6830   {
6831     { "pushP", { cs }, 0 },
6832   },
6833
6834   /* X86_64_16 */
6835   {
6836     { "pushP", { ss }, 0 },
6837   },
6838
6839   /* X86_64_17 */
6840   {
6841     { "popP", { ss }, 0 },
6842   },
6843
6844   /* X86_64_1E */
6845   {
6846     { "pushP", { ds }, 0 },
6847   },
6848
6849   /* X86_64_1F */
6850   {
6851     { "popP", { ds }, 0 },
6852   },
6853
6854   /* X86_64_27 */
6855   {
6856     { "daa", { XX }, 0 },
6857   },
6858
6859   /* X86_64_2F */
6860   {
6861     { "das", { XX }, 0 },
6862   },
6863
6864   /* X86_64_37 */
6865   {
6866     { "aaa", { XX }, 0 },
6867   },
6868
6869   /* X86_64_3F */
6870   {
6871     { "aas", { XX }, 0 },
6872   },
6873
6874   /* X86_64_60 */
6875   {
6876     { "pushaP", { XX }, 0 },
6877   },
6878
6879   /* X86_64_61 */
6880   {
6881     { "popaP", { XX }, 0 },
6882   },
6883
6884   /* X86_64_62 */
6885   {
6886     { MOD_TABLE (MOD_62_32BIT) },
6887     { EVEX_TABLE (EVEX_0F) },
6888   },
6889
6890   /* X86_64_63 */
6891   {
6892     { "arpl", { Ew, Gw }, 0 },
6893     { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
6894   },
6895
6896   /* X86_64_6D */
6897   {
6898     { "ins{R|}", { Yzr, indirDX }, 0 },
6899     { "ins{G|}", { Yzr, indirDX }, 0 },
6900   },
6901
6902   /* X86_64_6F */
6903   {
6904     { "outs{R|}", { indirDXr, Xz }, 0 },
6905     { "outs{G|}", { indirDXr, Xz }, 0 },
6906   },
6907
6908   /* X86_64_82 */
6909   {
6910     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6911     { REG_TABLE (REG_80) },
6912   },
6913
6914   /* X86_64_9A */
6915   {
6916     { "Jcall{T|}", { Ap }, 0 },
6917   },
6918
6919   /* X86_64_C2 */
6920   {
6921     { "retP",           { Iw, BND }, 0 },
6922     { "ret@",           { Iw, BND }, 0 },
6923   },
6924
6925   /* X86_64_C3 */
6926   {
6927     { "retP",           { BND }, 0 },
6928     { "ret@",           { BND }, 0 },
6929   },
6930
6931   /* X86_64_C4 */
6932   {
6933     { MOD_TABLE (MOD_C4_32BIT) },
6934     { VEX_C4_TABLE (VEX_0F) },
6935   },
6936
6937   /* X86_64_C5 */
6938   {
6939     { MOD_TABLE (MOD_C5_32BIT) },
6940     { VEX_C5_TABLE (VEX_0F) },
6941   },
6942
6943   /* X86_64_CE */
6944   {
6945     { "into", { XX }, 0 },
6946   },
6947
6948   /* X86_64_D4 */
6949   {
6950     { "aam", { Ib }, 0 },
6951   },
6952
6953   /* X86_64_D5 */
6954   {
6955     { "aad", { Ib }, 0 },
6956   },
6957
6958   /* X86_64_E8 */
6959   {
6960     { "callP",          { Jv, BND }, 0 },
6961     { "call@",          { Jv, BND }, 0 }
6962   },
6963
6964   /* X86_64_E9 */
6965   {
6966     { "jmpP",           { Jv, BND }, 0 },
6967     { "jmp@",           { Jv, BND }, 0 }
6968   },
6969
6970   /* X86_64_EA */
6971   {
6972     { "Jjmp{T|}", { Ap }, 0 },
6973   },
6974
6975   /* X86_64_0F01_REG_0 */
6976   {
6977     { "sgdt{Q|IQ}", { M }, 0 },
6978     { "sgdt", { M }, 0 },
6979   },
6980
6981   /* X86_64_0F01_REG_1 */
6982   {
6983     { "sidt{Q|IQ}", { M }, 0 },
6984     { "sidt", { M }, 0 },
6985   },
6986
6987   /* X86_64_0F01_REG_2 */
6988   {
6989     { "lgdt{Q|Q}", { M }, 0 },
6990     { "lgdt", { M }, 0 },
6991   },
6992
6993   /* X86_64_0F01_REG_3 */
6994   {
6995     { "lidt{Q|Q}", { M }, 0 },
6996     { "lidt", { M }, 0 },
6997   },
6998 };
6999
7000 static const struct dis386 three_byte_table[][256] = {
7001
7002   /* THREE_BYTE_0F38 */
7003   {
7004     /* 00 */
7005     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
7006     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
7007     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
7008     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
7009     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
7010     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
7011     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
7012     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
7013     /* 08 */
7014     { "psignb",         { MX, EM }, PREFIX_OPCODE },
7015     { "psignw",         { MX, EM }, PREFIX_OPCODE },
7016     { "psignd",         { MX, EM }, PREFIX_OPCODE },
7017     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     /* 10 */
7023     { PREFIX_TABLE (PREFIX_0F3810) },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { PREFIX_TABLE (PREFIX_0F3814) },
7028     { PREFIX_TABLE (PREFIX_0F3815) },
7029     { Bad_Opcode },
7030     { PREFIX_TABLE (PREFIX_0F3817) },
7031     /* 18 */
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7037     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7038     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7039     { Bad_Opcode },
7040     /* 20 */
7041     { PREFIX_TABLE (PREFIX_0F3820) },
7042     { PREFIX_TABLE (PREFIX_0F3821) },
7043     { PREFIX_TABLE (PREFIX_0F3822) },
7044     { PREFIX_TABLE (PREFIX_0F3823) },
7045     { PREFIX_TABLE (PREFIX_0F3824) },
7046     { PREFIX_TABLE (PREFIX_0F3825) },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     /* 28 */
7050     { PREFIX_TABLE (PREFIX_0F3828) },
7051     { PREFIX_TABLE (PREFIX_0F3829) },
7052     { PREFIX_TABLE (PREFIX_0F382A) },
7053     { PREFIX_TABLE (PREFIX_0F382B) },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     /* 30 */
7059     { PREFIX_TABLE (PREFIX_0F3830) },
7060     { PREFIX_TABLE (PREFIX_0F3831) },
7061     { PREFIX_TABLE (PREFIX_0F3832) },
7062     { PREFIX_TABLE (PREFIX_0F3833) },
7063     { PREFIX_TABLE (PREFIX_0F3834) },
7064     { PREFIX_TABLE (PREFIX_0F3835) },
7065     { Bad_Opcode },
7066     { PREFIX_TABLE (PREFIX_0F3837) },
7067     /* 38 */
7068     { PREFIX_TABLE (PREFIX_0F3838) },
7069     { PREFIX_TABLE (PREFIX_0F3839) },
7070     { PREFIX_TABLE (PREFIX_0F383A) },
7071     { PREFIX_TABLE (PREFIX_0F383B) },
7072     { PREFIX_TABLE (PREFIX_0F383C) },
7073     { PREFIX_TABLE (PREFIX_0F383D) },
7074     { PREFIX_TABLE (PREFIX_0F383E) },
7075     { PREFIX_TABLE (PREFIX_0F383F) },
7076     /* 40 */
7077     { PREFIX_TABLE (PREFIX_0F3840) },
7078     { PREFIX_TABLE (PREFIX_0F3841) },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     /* 48 */
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     /* 50 */
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     /* 58 */
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     /* 60 */
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     /* 68 */
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     /* 70 */
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     /* 78 */
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     /* 80 */
7149     { PREFIX_TABLE (PREFIX_0F3880) },
7150     { PREFIX_TABLE (PREFIX_0F3881) },
7151     { PREFIX_TABLE (PREFIX_0F3882) },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     /* 88 */
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     /* 90 */
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     /* 98 */
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     /* a0 */
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     /* a8 */
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     /* b0 */
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     /* b8 */
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     /* c0 */
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     /* c8 */
7230     { PREFIX_TABLE (PREFIX_0F38C8) },
7231     { PREFIX_TABLE (PREFIX_0F38C9) },
7232     { PREFIX_TABLE (PREFIX_0F38CA) },
7233     { PREFIX_TABLE (PREFIX_0F38CB) },
7234     { PREFIX_TABLE (PREFIX_0F38CC) },
7235     { PREFIX_TABLE (PREFIX_0F38CD) },
7236     { Bad_Opcode },
7237     { PREFIX_TABLE (PREFIX_0F38CF) },
7238     /* d0 */
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     /* d8 */
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { PREFIX_TABLE (PREFIX_0F38DB) },
7252     { PREFIX_TABLE (PREFIX_0F38DC) },
7253     { PREFIX_TABLE (PREFIX_0F38DD) },
7254     { PREFIX_TABLE (PREFIX_0F38DE) },
7255     { PREFIX_TABLE (PREFIX_0F38DF) },
7256     /* e0 */
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     /* e8 */
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     /* f0 */
7275     { PREFIX_TABLE (PREFIX_0F38F0) },
7276     { PREFIX_TABLE (PREFIX_0F38F1) },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { PREFIX_TABLE (PREFIX_0F38F5) },
7281     { PREFIX_TABLE (PREFIX_0F38F6) },
7282     { Bad_Opcode },
7283     /* f8 */
7284     { PREFIX_TABLE (PREFIX_0F38F8) },
7285     { PREFIX_TABLE (PREFIX_0F38F9) },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292   },
7293   /* THREE_BYTE_0F3A */
7294   {
7295     /* 00 */
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     /* 08 */
7305     { PREFIX_TABLE (PREFIX_0F3A08) },
7306     { PREFIX_TABLE (PREFIX_0F3A09) },
7307     { PREFIX_TABLE (PREFIX_0F3A0A) },
7308     { PREFIX_TABLE (PREFIX_0F3A0B) },
7309     { PREFIX_TABLE (PREFIX_0F3A0C) },
7310     { PREFIX_TABLE (PREFIX_0F3A0D) },
7311     { PREFIX_TABLE (PREFIX_0F3A0E) },
7312     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7313     /* 10 */
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { PREFIX_TABLE (PREFIX_0F3A14) },
7319     { PREFIX_TABLE (PREFIX_0F3A15) },
7320     { PREFIX_TABLE (PREFIX_0F3A16) },
7321     { PREFIX_TABLE (PREFIX_0F3A17) },
7322     /* 18 */
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     /* 20 */
7332     { PREFIX_TABLE (PREFIX_0F3A20) },
7333     { PREFIX_TABLE (PREFIX_0F3A21) },
7334     { PREFIX_TABLE (PREFIX_0F3A22) },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     /* 28 */
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     /* 30 */
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     /* 38 */
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     /* 40 */
7368     { PREFIX_TABLE (PREFIX_0F3A40) },
7369     { PREFIX_TABLE (PREFIX_0F3A41) },
7370     { PREFIX_TABLE (PREFIX_0F3A42) },
7371     { Bad_Opcode },
7372     { PREFIX_TABLE (PREFIX_0F3A44) },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     /* 48 */
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     /* 50 */
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     /* 58 */
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     /* 60 */
7404     { PREFIX_TABLE (PREFIX_0F3A60) },
7405     { PREFIX_TABLE (PREFIX_0F3A61) },
7406     { PREFIX_TABLE (PREFIX_0F3A62) },
7407     { PREFIX_TABLE (PREFIX_0F3A63) },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     /* 68 */
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     /* 70 */
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     /* 78 */
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     /* 80 */
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     /* 88 */
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     /* 90 */
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     /* 98 */
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     /* a0 */
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     /* a8 */
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     /* b0 */
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     /* b8 */
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     /* c0 */
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     /* c8 */
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { PREFIX_TABLE (PREFIX_0F3ACC) },
7526     { Bad_Opcode },
7527     { PREFIX_TABLE (PREFIX_0F3ACE) },
7528     { PREFIX_TABLE (PREFIX_0F3ACF) },
7529     /* d0 */
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     /* d8 */
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { PREFIX_TABLE (PREFIX_0F3ADF) },
7547     /* e0 */
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     /* e8 */
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     /* f0 */
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     /* f8 */
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583   },
7584 };
7585
7586 static const struct dis386 xop_table[][256] = {
7587   /* XOP_08 */
7588   {
7589     /* 00 */
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     /* 08 */
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     /* 10 */
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     /* 18 */
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     /* 20 */
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     /* 28 */
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     /* 30 */
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     /* 38 */
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     /* 40 */
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     /* 48 */
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     /* 50 */
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     /* 58 */
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     /* 60 */
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     /* 68 */
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     /* 70 */
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     /* 78 */
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     /* 80 */
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7740     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7741     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7742     /* 88 */
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7750     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7751     /* 90 */
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7758     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7759     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7760     /* 98 */
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7768     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7769     /* a0 */
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7773     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7777     { Bad_Opcode },
7778     /* a8 */
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     /* b0 */
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7795     { Bad_Opcode },
7796     /* b8 */
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     /* c0 */
7806     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7807     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7808     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7809     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     /* c8 */
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7820     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7821     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7822     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7823     /* d0 */
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     /* d8 */
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     /* e0 */
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     /* e8 */
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7856     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7857     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7858     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7859     /* f0 */
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     /* f8 */
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877   },
7878   /* XOP_09 */
7879   {
7880     /* 00 */
7881     { Bad_Opcode },
7882     { REG_TABLE (REG_XOP_TBM_01) },
7883     { REG_TABLE (REG_XOP_TBM_02) },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     /* 08 */
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     /* 10 */
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { REG_TABLE (REG_XOP_LWPCB) },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     /* 18 */
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     /* 20 */
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     /* 28 */
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     /* 30 */
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     /* 38 */
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     /* 40 */
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     /* 48 */
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     /* 50 */
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     /* 58 */
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     /* 60 */
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     /* 68 */
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     /* 70 */
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     /* 78 */
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     /* 80 */
8025     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8026     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8027     { "vfrczss",        { XM, EXd }, 0 },
8028     { "vfrczsd",        { XM, EXq }, 0 },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     /* 88 */
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     /* 90 */
8043     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8044     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8045     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8046     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8047     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8048     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8049     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8050     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8051     /* 98 */
8052     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8053     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8054     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8055     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     /* a0 */
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     /* a8 */
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     /* b0 */
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     /* b8 */
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     /* c0 */
8097     { Bad_Opcode },
8098     { "vphaddbw",       { XM, EXxmm }, 0 },
8099     { "vphaddbd",       { XM, EXxmm }, 0 },
8100     { "vphaddbq",       { XM, EXxmm }, 0 },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { "vphaddwd",       { XM, EXxmm }, 0 },
8104     { "vphaddwq",       { XM, EXxmm }, 0 },
8105     /* c8 */
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { "vphadddq",       { XM, EXxmm }, 0 },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     /* d0 */
8115     { Bad_Opcode },
8116     { "vphaddubw",      { XM, EXxmm }, 0 },
8117     { "vphaddubd",      { XM, EXxmm }, 0 },
8118     { "vphaddubq",      { XM, EXxmm }, 0 },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { "vphadduwd",      { XM, EXxmm }, 0 },
8122     { "vphadduwq",      { XM, EXxmm }, 0 },
8123     /* d8 */
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { "vphaddudq",      { XM, EXxmm }, 0 },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     /* e0 */
8133     { Bad_Opcode },
8134     { "vphsubbw",       { XM, EXxmm }, 0 },
8135     { "vphsubwd",       { XM, EXxmm }, 0 },
8136     { "vphsubdq",       { XM, EXxmm }, 0 },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     /* e8 */
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     /* f0 */
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     /* f8 */
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168   },
8169   /* XOP_0A */
8170   {
8171     /* 00 */
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     /* 08 */
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     /* 10 */
8190     { "bextrS", { Gdq, Edq, Id }, 0 },
8191     { Bad_Opcode },
8192     { REG_TABLE (REG_XOP_LWP) },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     /* 18 */
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     /* 20 */
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     /* 28 */
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     /* 30 */
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     /* 38 */
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     /* 40 */
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     /* 48 */
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     /* 50 */
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     /* 58 */
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     /* 60 */
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     /* 68 */
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     /* 70 */
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     /* 78 */
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     /* 80 */
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     /* 88 */
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     /* 90 */
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     /* 98 */
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     /* a0 */
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     /* a8 */
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     /* b0 */
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     /* b8 */
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     /* c0 */
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     /* c8 */
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     /* d0 */
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     /* d8 */
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     /* e0 */
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     /* e8 */
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     /* f0 */
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     /* f8 */
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459   },
8460 };
8461
8462 static const struct dis386 vex_table[][256] = {
8463   /* VEX_0F */
8464   {
8465     /* 00 */
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     /* 08 */
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     /* 10 */
8484     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8485     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8486     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8487     { MOD_TABLE (MOD_VEX_0F13) },
8488     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8489     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8490     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8491     { MOD_TABLE (MOD_VEX_0F17) },
8492     /* 18 */
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     /* 20 */
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     /* 28 */
8511     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
8512     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
8513     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8514     { MOD_TABLE (MOD_VEX_0F2B) },
8515     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8516     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8517     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8518     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8519     /* 30 */
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     /* 38 */
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     /* 40 */
8538     { Bad_Opcode },
8539     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8540     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8541     { Bad_Opcode },
8542     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8543     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8544     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8545     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8546     /* 48 */
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8550     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     /* 50 */
8556     { MOD_TABLE (MOD_VEX_0F50) },
8557     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8558     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8559     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8560     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8561     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
8562     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
8563     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8564     /* 58 */
8565     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8566     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8567     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8568     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8569     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8570     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8571     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8572     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8573     /* 60 */
8574     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8575     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8576     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8577     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8578     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8579     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8580     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8581     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8582     /* 68 */
8583     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8584     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8585     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8586     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8587     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8588     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8589     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8590     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8591     /* 70 */
8592     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8593     { REG_TABLE (REG_VEX_0F71) },
8594     { REG_TABLE (REG_VEX_0F72) },
8595     { REG_TABLE (REG_VEX_0F73) },
8596     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8597     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8598     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8599     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8600     /* 78 */
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8606     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8607     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8608     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8609     /* 80 */
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     /* 88 */
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     /* 90 */
8628     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8629     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8630     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8631     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     /* 98 */
8637     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8638     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     { Bad_Opcode },
8644     { Bad_Opcode },
8645     /* a0 */
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     { Bad_Opcode },
8653     { Bad_Opcode },
8654     /* a8 */
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     { Bad_Opcode },
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     { REG_TABLE (REG_VEX_0FAE) },
8662     { Bad_Opcode },
8663     /* b0 */
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     { Bad_Opcode },
8668     { Bad_Opcode },
8669     { Bad_Opcode },
8670     { Bad_Opcode },
8671     { Bad_Opcode },
8672     /* b8 */
8673     { Bad_Opcode },
8674     { Bad_Opcode },
8675     { Bad_Opcode },
8676     { Bad_Opcode },
8677     { Bad_Opcode },
8678     { Bad_Opcode },
8679     { Bad_Opcode },
8680     { Bad_Opcode },
8681     /* c0 */
8682     { Bad_Opcode },
8683     { Bad_Opcode },
8684     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8685     { Bad_Opcode },
8686     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8687     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8688     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
8689     { Bad_Opcode },
8690     /* c8 */
8691     { Bad_Opcode },
8692     { Bad_Opcode },
8693     { Bad_Opcode },
8694     { Bad_Opcode },
8695     { Bad_Opcode },
8696     { Bad_Opcode },
8697     { Bad_Opcode },
8698     { Bad_Opcode },
8699     /* d0 */
8700     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8701     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8702     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8703     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8704     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8705     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8706     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8707     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8708     /* d8 */
8709     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8710     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8711     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8712     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8713     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8714     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8715     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8716     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8717     /* e0 */
8718     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8719     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8720     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8721     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8722     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8723     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8724     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8725     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8726     /* e8 */
8727     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8728     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8729     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8730     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8731     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8732     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8733     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8734     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8735     /* f0 */
8736     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8737     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8738     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8739     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8740     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8741     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8742     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8743     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8744     /* f8 */
8745     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8746     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8747     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8748     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8749     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8750     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8751     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8752     { Bad_Opcode },
8753   },
8754   /* VEX_0F38 */
8755   {
8756     /* 00 */
8757     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8760     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8763     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8764     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8765     /* 08 */
8766     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8767     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8768     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8769     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8770     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8774     /* 10 */
8775     { Bad_Opcode },
8776     { Bad_Opcode },
8777     { Bad_Opcode },
8778     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8779     { Bad_Opcode },
8780     { Bad_Opcode },
8781     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8782     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8783     /* 18 */
8784     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8785     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8786     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8787     { Bad_Opcode },
8788     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8789     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8790     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8791     { Bad_Opcode },
8792     /* 20 */
8793     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8795     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8796     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8797     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8798     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     /* 28 */
8802     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8803     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8804     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8805     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8806     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8807     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8808     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8809     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8810     /* 30 */
8811     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8812     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8813     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8814     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8815     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8816     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8817     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8818     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8819     /* 38 */
8820     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8821     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8822     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8823     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8824     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8825     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8826     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8827     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8828     /* 40 */
8829     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8830     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8835     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8836     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8837     /* 48 */
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     /* 50 */
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     /* 58 */
8856     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8857     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8858     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8859     { Bad_Opcode },
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     /* 60 */
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { Bad_Opcode },
8868     { Bad_Opcode },
8869     { Bad_Opcode },
8870     { Bad_Opcode },
8871     { Bad_Opcode },
8872     { Bad_Opcode },
8873     /* 68 */
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     { Bad_Opcode },
8881     { Bad_Opcode },
8882     /* 70 */
8883     { Bad_Opcode },
8884     { Bad_Opcode },
8885     { Bad_Opcode },
8886     { Bad_Opcode },
8887     { Bad_Opcode },
8888     { Bad_Opcode },
8889     { Bad_Opcode },
8890     { Bad_Opcode },
8891     /* 78 */
8892     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8893     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8894     { Bad_Opcode },
8895     { Bad_Opcode },
8896     { Bad_Opcode },
8897     { Bad_Opcode },
8898     { Bad_Opcode },
8899     { Bad_Opcode },
8900     /* 80 */
8901     { Bad_Opcode },
8902     { Bad_Opcode },
8903     { Bad_Opcode },
8904     { Bad_Opcode },
8905     { Bad_Opcode },
8906     { Bad_Opcode },
8907     { Bad_Opcode },
8908     { Bad_Opcode },
8909     /* 88 */
8910     { Bad_Opcode },
8911     { Bad_Opcode },
8912     { Bad_Opcode },
8913     { Bad_Opcode },
8914     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8915     { Bad_Opcode },
8916     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8917     { Bad_Opcode },
8918     /* 90 */
8919     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8920     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8921     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8922     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8926     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8927     /* 98 */
8928     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8929     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8930     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8931     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8932     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8933     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8934     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8935     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8936     /* a0 */
8937     { Bad_Opcode },
8938     { Bad_Opcode },
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8944     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8945     /* a8 */
8946     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8947     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8948     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8949     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8950     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8951     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8952     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8953     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8954     /* b0 */
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8962     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8963     /* b8 */
8964     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8965     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8966     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8967     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8968     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8969     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8970     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8971     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8972     /* c0 */
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     /* c8 */
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     { Bad_Opcode },
8989     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8990     /* d0 */
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     { Bad_Opcode },
8998     { Bad_Opcode },
8999     /* d8 */
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9004     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9005     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9006     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9007     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9008     /* e0 */
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015     { Bad_Opcode },
9016     { Bad_Opcode },
9017     /* e8 */
9018     { Bad_Opcode },
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     /* f0 */
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9030     { REG_TABLE (REG_VEX_0F38F3) },
9031     { Bad_Opcode },
9032     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9033     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9034     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9035     /* f8 */
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     { Bad_Opcode },
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044   },
9045   /* VEX_0F3A */
9046   {
9047     /* 00 */
9048     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9049     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9050     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9051     { Bad_Opcode },
9052     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9053     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9054     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9055     { Bad_Opcode },
9056     /* 08 */
9057     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9058     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9059     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9060     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9061     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9062     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9063     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9064     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9065     /* 10 */
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9071     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9072     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9073     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9074     /* 18 */
9075     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9076     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     /* 20 */
9084     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9085     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9086     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     { Bad_Opcode },
9091     { Bad_Opcode },
9092     /* 28 */
9093     { Bad_Opcode },
9094     { Bad_Opcode },
9095     { Bad_Opcode },
9096     { Bad_Opcode },
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     /* 30 */
9102     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9103     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9104     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9105     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     /* 38 */
9111     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9112     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     /* 40 */
9120     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9121     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9122     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9123     { Bad_Opcode },
9124     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9125     { Bad_Opcode },
9126     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9127     { Bad_Opcode },
9128     /* 48 */
9129     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9130     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9131     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9132     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9133     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     /* 50 */
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     /* 58 */
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9152     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9153     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9154     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9155     /* 60 */
9156     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9157     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9158     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9159     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     /* 68 */
9165     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9166     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9167     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9168     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9169     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9170     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9171     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9172     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9173     /* 70 */
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     /* 78 */
9183     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9184     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9185     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9186     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9187     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9188     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9189     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9190     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9191     /* 80 */
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     /* 88 */
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     /* 90 */
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     /* 98 */
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     /* a0 */
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     /* a8 */
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     /* b0 */
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     /* b8 */
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     /* c0 */
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     /* c8 */
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9280     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9281     /* d0 */
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     { Bad_Opcode },
9285     { Bad_Opcode },
9286     { Bad_Opcode },
9287     { Bad_Opcode },
9288     { Bad_Opcode },
9289     { Bad_Opcode },
9290     /* d8 */
9291     { Bad_Opcode },
9292     { Bad_Opcode },
9293     { Bad_Opcode },
9294     { Bad_Opcode },
9295     { Bad_Opcode },
9296     { Bad_Opcode },
9297     { Bad_Opcode },
9298     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9299     /* e0 */
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303     { Bad_Opcode },
9304     { Bad_Opcode },
9305     { Bad_Opcode },
9306     { Bad_Opcode },
9307     { Bad_Opcode },
9308     /* e8 */
9309     { Bad_Opcode },
9310     { Bad_Opcode },
9311     { Bad_Opcode },
9312     { Bad_Opcode },
9313     { Bad_Opcode },
9314     { Bad_Opcode },
9315     { Bad_Opcode },
9316     { Bad_Opcode },
9317     /* f0 */
9318     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9319     { Bad_Opcode },
9320     { Bad_Opcode },
9321     { Bad_Opcode },
9322     { Bad_Opcode },
9323     { Bad_Opcode },
9324     { Bad_Opcode },
9325     { Bad_Opcode },
9326     /* f8 */
9327     { Bad_Opcode },
9328     { Bad_Opcode },
9329     { Bad_Opcode },
9330     { Bad_Opcode },
9331     { Bad_Opcode },
9332     { Bad_Opcode },
9333     { Bad_Opcode },
9334     { Bad_Opcode },
9335   },
9336 };
9337
9338 #include "i386-dis-evex.h"
9339
9340 static const struct dis386 vex_len_table[][2] = {
9341   /* VEX_LEN_0F12_P_0_M_0 */
9342   {
9343     { "vmovlps",        { XM, Vex128, EXq }, 0 },
9344   },
9345
9346   /* VEX_LEN_0F12_P_0_M_1 */
9347   {
9348     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9349   },
9350
9351   /* VEX_LEN_0F12_P_2 */
9352   {
9353     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
9354   },
9355
9356   /* VEX_LEN_0F13_M_0 */
9357   {
9358     { "vmovlpX",        { EXq, XM }, PREFIX_OPCODE },
9359   },
9360
9361   /* VEX_LEN_0F16_P_0_M_0 */
9362   {
9363     { "vmovhps",        { XM, Vex128, EXq }, 0 },
9364   },
9365
9366   /* VEX_LEN_0F16_P_0_M_1 */
9367   {
9368     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9369   },
9370
9371   /* VEX_LEN_0F16_P_2 */
9372   {
9373     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
9374   },
9375
9376   /* VEX_LEN_0F17_M_0 */
9377   {
9378     { "vmovhpX",        { EXq, XM }, PREFIX_OPCODE },
9379   },
9380
9381   /* VEX_LEN_0F41_P_0 */
9382   {
9383     { Bad_Opcode },
9384     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9385   },
9386   /* VEX_LEN_0F41_P_2 */
9387   {
9388     { Bad_Opcode },
9389     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9390   },
9391   /* VEX_LEN_0F42_P_0 */
9392   {
9393     { Bad_Opcode },
9394     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9395   },
9396   /* VEX_LEN_0F42_P_2 */
9397   {
9398     { Bad_Opcode },
9399     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9400   },
9401   /* VEX_LEN_0F44_P_0 */
9402   {
9403     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9404   },
9405   /* VEX_LEN_0F44_P_2 */
9406   {
9407     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9408   },
9409   /* VEX_LEN_0F45_P_0 */
9410   {
9411     { Bad_Opcode },
9412     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9413   },
9414   /* VEX_LEN_0F45_P_2 */
9415   {
9416     { Bad_Opcode },
9417     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9418   },
9419   /* VEX_LEN_0F46_P_0 */
9420   {
9421     { Bad_Opcode },
9422     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9423   },
9424   /* VEX_LEN_0F46_P_2 */
9425   {
9426     { Bad_Opcode },
9427     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9428   },
9429   /* VEX_LEN_0F47_P_0 */
9430   {
9431     { Bad_Opcode },
9432     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9433   },
9434   /* VEX_LEN_0F47_P_2 */
9435   {
9436     { Bad_Opcode },
9437     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9438   },
9439   /* VEX_LEN_0F4A_P_0 */
9440   {
9441     { Bad_Opcode },
9442     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9443   },
9444   /* VEX_LEN_0F4A_P_2 */
9445   {
9446     { Bad_Opcode },
9447     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9448   },
9449   /* VEX_LEN_0F4B_P_0 */
9450   {
9451     { Bad_Opcode },
9452     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9453   },
9454   /* VEX_LEN_0F4B_P_2 */
9455   {
9456     { Bad_Opcode },
9457     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9458   },
9459
9460   /* VEX_LEN_0F6E_P_2 */
9461   {
9462     { "vmovK",          { XMScalar, Edq }, 0 },
9463   },
9464
9465   /* VEX_LEN_0F77_P_1 */
9466   {
9467     { "vzeroupper",     { XX }, 0 },
9468     { "vzeroall",       { XX }, 0 },
9469   },
9470
9471   /* VEX_LEN_0F7E_P_1 */
9472   {
9473     { "vmovq",          { XMScalar, EXqScalar }, 0 },
9474   },
9475
9476   /* VEX_LEN_0F7E_P_2 */
9477   {
9478     { "vmovK",          { Edq, XMScalar }, 0 },
9479   },
9480
9481   /* VEX_LEN_0F90_P_0 */
9482   {
9483     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9484   },
9485
9486   /* VEX_LEN_0F90_P_2 */
9487   {
9488     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9489   },
9490
9491   /* VEX_LEN_0F91_P_0 */
9492   {
9493     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9494   },
9495
9496   /* VEX_LEN_0F91_P_2 */
9497   {
9498     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9499   },
9500
9501   /* VEX_LEN_0F92_P_0 */
9502   {
9503     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9504   },
9505
9506   /* VEX_LEN_0F92_P_2 */
9507   {
9508     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9509   },
9510
9511   /* VEX_LEN_0F92_P_3 */
9512   {
9513     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9514   },
9515
9516   /* VEX_LEN_0F93_P_0 */
9517   {
9518     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9519   },
9520
9521   /* VEX_LEN_0F93_P_2 */
9522   {
9523     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9524   },
9525
9526   /* VEX_LEN_0F93_P_3 */
9527   {
9528     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9529   },
9530
9531   /* VEX_LEN_0F98_P_0 */
9532   {
9533     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9534   },
9535
9536   /* VEX_LEN_0F98_P_2 */
9537   {
9538     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9539   },
9540
9541   /* VEX_LEN_0F99_P_0 */
9542   {
9543     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9544   },
9545
9546   /* VEX_LEN_0F99_P_2 */
9547   {
9548     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9549   },
9550
9551   /* VEX_LEN_0FAE_R_2_M_0 */
9552   {
9553     { "vldmxcsr",       { Md }, 0 },
9554   },
9555
9556   /* VEX_LEN_0FAE_R_3_M_0 */
9557   {
9558     { "vstmxcsr",       { Md }, 0 },
9559   },
9560
9561   /* VEX_LEN_0FC4_P_2 */
9562   {
9563     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9564   },
9565
9566   /* VEX_LEN_0FC5_P_2 */
9567   {
9568     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9569   },
9570
9571   /* VEX_LEN_0FD6_P_2 */
9572   {
9573     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
9574   },
9575
9576   /* VEX_LEN_0FF7_P_2 */
9577   {
9578     { "vmaskmovdqu",    { XM, XS }, 0 },
9579   },
9580
9581   /* VEX_LEN_0F3816_P_2 */
9582   {
9583     { Bad_Opcode },
9584     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9585   },
9586
9587   /* VEX_LEN_0F3819_P_2 */
9588   {
9589     { Bad_Opcode },
9590     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9591   },
9592
9593   /* VEX_LEN_0F381A_P_2_M_0 */
9594   {
9595     { Bad_Opcode },
9596     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9597   },
9598
9599   /* VEX_LEN_0F3836_P_2 */
9600   {
9601     { Bad_Opcode },
9602     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9603   },
9604
9605   /* VEX_LEN_0F3841_P_2 */
9606   {
9607     { "vphminposuw",    { XM, EXx }, 0 },
9608   },
9609
9610   /* VEX_LEN_0F385A_P_2_M_0 */
9611   {
9612     { Bad_Opcode },
9613     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9614   },
9615
9616   /* VEX_LEN_0F38DB_P_2 */
9617   {
9618     { "vaesimc",        { XM, EXx }, 0 },
9619   },
9620
9621   /* VEX_LEN_0F38F2_P_0 */
9622   {
9623     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9624   },
9625
9626   /* VEX_LEN_0F38F3_R_1_P_0 */
9627   {
9628     { "blsrS",          { VexGdq, Edq }, 0 },
9629   },
9630
9631   /* VEX_LEN_0F38F3_R_2_P_0 */
9632   {
9633     { "blsmskS",        { VexGdq, Edq }, 0 },
9634   },
9635
9636   /* VEX_LEN_0F38F3_R_3_P_0 */
9637   {
9638     { "blsiS",          { VexGdq, Edq }, 0 },
9639   },
9640
9641   /* VEX_LEN_0F38F5_P_0 */
9642   {
9643     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9644   },
9645
9646   /* VEX_LEN_0F38F5_P_1 */
9647   {
9648     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9649   },
9650
9651   /* VEX_LEN_0F38F5_P_3 */
9652   {
9653     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9654   },
9655
9656   /* VEX_LEN_0F38F6_P_3 */
9657   {
9658     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9659   },
9660
9661   /* VEX_LEN_0F38F7_P_0 */
9662   {
9663     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9664   },
9665
9666   /* VEX_LEN_0F38F7_P_1 */
9667   {
9668     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9669   },
9670
9671   /* VEX_LEN_0F38F7_P_2 */
9672   {
9673     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9674   },
9675
9676   /* VEX_LEN_0F38F7_P_3 */
9677   {
9678     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9679   },
9680
9681   /* VEX_LEN_0F3A00_P_2 */
9682   {
9683     { Bad_Opcode },
9684     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9685   },
9686
9687   /* VEX_LEN_0F3A01_P_2 */
9688   {
9689     { Bad_Opcode },
9690     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9691   },
9692
9693   /* VEX_LEN_0F3A06_P_2 */
9694   {
9695     { Bad_Opcode },
9696     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9697   },
9698
9699   /* VEX_LEN_0F3A14_P_2 */
9700   {
9701     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9702   },
9703
9704   /* VEX_LEN_0F3A15_P_2 */
9705   {
9706     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9707   },
9708
9709   /* VEX_LEN_0F3A16_P_2  */
9710   {
9711     { "vpextrK",        { Edq, XM, Ib }, 0 },
9712   },
9713
9714   /* VEX_LEN_0F3A17_P_2 */
9715   {
9716     { "vextractps",     { Edqd, XM, Ib }, 0 },
9717   },
9718
9719   /* VEX_LEN_0F3A18_P_2 */
9720   {
9721     { Bad_Opcode },
9722     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9723   },
9724
9725   /* VEX_LEN_0F3A19_P_2 */
9726   {
9727     { Bad_Opcode },
9728     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9729   },
9730
9731   /* VEX_LEN_0F3A20_P_2 */
9732   {
9733     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9734   },
9735
9736   /* VEX_LEN_0F3A21_P_2 */
9737   {
9738     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9739   },
9740
9741   /* VEX_LEN_0F3A22_P_2 */
9742   {
9743     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9744   },
9745
9746   /* VEX_LEN_0F3A30_P_2 */
9747   {
9748     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9749   },
9750
9751   /* VEX_LEN_0F3A31_P_2 */
9752   {
9753     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9754   },
9755
9756   /* VEX_LEN_0F3A32_P_2 */
9757   {
9758     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9759   },
9760
9761   /* VEX_LEN_0F3A33_P_2 */
9762   {
9763     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9764   },
9765
9766   /* VEX_LEN_0F3A38_P_2 */
9767   {
9768     { Bad_Opcode },
9769     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9770   },
9771
9772   /* VEX_LEN_0F3A39_P_2 */
9773   {
9774     { Bad_Opcode },
9775     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9776   },
9777
9778   /* VEX_LEN_0F3A41_P_2 */
9779   {
9780     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9781   },
9782
9783   /* VEX_LEN_0F3A46_P_2 */
9784   {
9785     { Bad_Opcode },
9786     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9787   },
9788
9789   /* VEX_LEN_0F3A60_P_2 */
9790   {
9791     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9792   },
9793
9794   /* VEX_LEN_0F3A61_P_2 */
9795   {
9796     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9797   },
9798
9799   /* VEX_LEN_0F3A62_P_2 */
9800   {
9801     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9802   },
9803
9804   /* VEX_LEN_0F3A63_P_2 */
9805   {
9806     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9807   },
9808
9809   /* VEX_LEN_0F3A6A_P_2 */
9810   {
9811     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9812   },
9813
9814   /* VEX_LEN_0F3A6B_P_2 */
9815   {
9816     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9817   },
9818
9819   /* VEX_LEN_0F3A6E_P_2 */
9820   {
9821     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9822   },
9823
9824   /* VEX_LEN_0F3A6F_P_2 */
9825   {
9826     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9827   },
9828
9829   /* VEX_LEN_0F3A7A_P_2 */
9830   {
9831     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9832   },
9833
9834   /* VEX_LEN_0F3A7B_P_2 */
9835   {
9836     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9837   },
9838
9839   /* VEX_LEN_0F3A7E_P_2 */
9840   {
9841     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9842   },
9843
9844   /* VEX_LEN_0F3A7F_P_2 */
9845   {
9846     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9847   },
9848
9849   /* VEX_LEN_0F3ADF_P_2 */
9850   {
9851     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9852   },
9853
9854   /* VEX_LEN_0F3AF0_P_3 */
9855   {
9856     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9857   },
9858
9859   /* VEX_LEN_0FXOP_08_CC */
9860   {
9861      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9862   },
9863
9864   /* VEX_LEN_0FXOP_08_CD */
9865   {
9866      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9867   },
9868
9869   /* VEX_LEN_0FXOP_08_CE */
9870   {
9871      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9872   },
9873
9874   /* VEX_LEN_0FXOP_08_CF */
9875   {
9876      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9877   },
9878
9879   /* VEX_LEN_0FXOP_08_EC */
9880   {
9881      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9882   },
9883
9884   /* VEX_LEN_0FXOP_08_ED */
9885   {
9886      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9887   },
9888
9889   /* VEX_LEN_0FXOP_08_EE */
9890   {
9891      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9892   },
9893
9894   /* VEX_LEN_0FXOP_08_EF */
9895   {
9896      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9897   },
9898
9899   /* VEX_LEN_0FXOP_09_80 */
9900   {
9901     { "vfrczps",        { XM, EXxmm }, 0 },
9902     { "vfrczps",        { XM, EXymmq }, 0 },
9903   },
9904
9905   /* VEX_LEN_0FXOP_09_81 */
9906   {
9907     { "vfrczpd",        { XM, EXxmm }, 0 },
9908     { "vfrczpd",        { XM, EXymmq }, 0 },
9909   },
9910 };
9911
9912 #include "i386-dis-evex-len.h"
9913
9914 static const struct dis386 vex_w_table[][2] = {
9915   {
9916     /* VEX_W_0F41_P_0_LEN_1 */
9917     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9918     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9919   },
9920   {
9921     /* VEX_W_0F41_P_2_LEN_1 */
9922     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9923     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9924   },
9925   {
9926     /* VEX_W_0F42_P_0_LEN_1 */
9927     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9928     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9929   },
9930   {
9931     /* VEX_W_0F42_P_2_LEN_1 */
9932     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9933     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9934   },
9935   {
9936     /* VEX_W_0F44_P_0_LEN_0 */
9937     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9938     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9939   },
9940   {
9941     /* VEX_W_0F44_P_2_LEN_0 */
9942     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9943     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9944   },
9945   {
9946     /* VEX_W_0F45_P_0_LEN_1 */
9947     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9948     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9949   },
9950   {
9951     /* VEX_W_0F45_P_2_LEN_1 */
9952     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9953     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9954   },
9955   {
9956     /* VEX_W_0F46_P_0_LEN_1 */
9957     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9958     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9959   },
9960   {
9961     /* VEX_W_0F46_P_2_LEN_1 */
9962     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9963     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9964   },
9965   {
9966     /* VEX_W_0F47_P_0_LEN_1 */
9967     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9968     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9969   },
9970   {
9971     /* VEX_W_0F47_P_2_LEN_1 */
9972     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9973     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9974   },
9975   {
9976     /* VEX_W_0F4A_P_0_LEN_1 */
9977     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9978     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9979   },
9980   {
9981     /* VEX_W_0F4A_P_2_LEN_1 */
9982     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9983     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9984   },
9985   {
9986     /* VEX_W_0F4B_P_0_LEN_1 */
9987     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9988     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9989   },
9990   {
9991     /* VEX_W_0F4B_P_2_LEN_1 */
9992     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9993   },
9994   {
9995     /* VEX_W_0F90_P_0_LEN_0 */
9996     { "kmovw",          { MaskG, MaskE }, 0 },
9997     { "kmovq",          { MaskG, MaskE }, 0 },
9998   },
9999   {
10000     /* VEX_W_0F90_P_2_LEN_0 */
10001     { "kmovb",          { MaskG, MaskBDE }, 0 },
10002     { "kmovd",          { MaskG, MaskBDE }, 0 },
10003   },
10004   {
10005     /* VEX_W_0F91_P_0_LEN_0 */
10006     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10007     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10008   },
10009   {
10010     /* VEX_W_0F91_P_2_LEN_0 */
10011     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10012     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10013   },
10014   {
10015     /* VEX_W_0F92_P_0_LEN_0 */
10016     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10017   },
10018   {
10019     /* VEX_W_0F92_P_2_LEN_0 */
10020     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10021   },
10022   {
10023     /* VEX_W_0F93_P_0_LEN_0 */
10024     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10025   },
10026   {
10027     /* VEX_W_0F93_P_2_LEN_0 */
10028     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10029   },
10030   {
10031     /* VEX_W_0F98_P_0_LEN_0 */
10032     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10033     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10034   },
10035   {
10036     /* VEX_W_0F98_P_2_LEN_0 */
10037     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10038     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10039   },
10040   {
10041     /* VEX_W_0F99_P_0_LEN_0 */
10042     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10043     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10044   },
10045   {
10046     /* VEX_W_0F99_P_2_LEN_0 */
10047     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10048     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10049   },
10050   {
10051     /* VEX_W_0F380C_P_2  */
10052     { "vpermilps",      { XM, Vex, EXx }, 0 },
10053   },
10054   {
10055     /* VEX_W_0F380D_P_2  */
10056     { "vpermilpd",      { XM, Vex, EXx }, 0 },
10057   },
10058   {
10059     /* VEX_W_0F380E_P_2  */
10060     { "vtestps",        { XM, EXx }, 0 },
10061   },
10062   {
10063     /* VEX_W_0F380F_P_2  */
10064     { "vtestpd",        { XM, EXx }, 0 },
10065   },
10066   {
10067     /* VEX_W_0F3816_P_2  */
10068     { "vpermps",        { XM, Vex, EXx }, 0 },
10069   },
10070   {
10071     /* VEX_W_0F3818_P_2 */
10072     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10073   },
10074   {
10075     /* VEX_W_0F3819_P_2 */
10076     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10077   },
10078   {
10079     /* VEX_W_0F381A_P_2_M_0 */
10080     { "vbroadcastf128", { XM, Mxmm }, 0 },
10081   },
10082   {
10083     /* VEX_W_0F382C_P_2_M_0 */
10084     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10085   },
10086   {
10087     /* VEX_W_0F382D_P_2_M_0 */
10088     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10089   },
10090   {
10091     /* VEX_W_0F382E_P_2_M_0 */
10092     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10093   },
10094   {
10095     /* VEX_W_0F382F_P_2_M_0 */
10096     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10097   },
10098   {
10099     /* VEX_W_0F3836_P_2  */
10100     { "vpermd",         { XM, Vex, EXx }, 0 },
10101   },
10102   {
10103     /* VEX_W_0F3846_P_2 */
10104     { "vpsravd",        { XM, Vex, EXx }, 0 },
10105   },
10106   {
10107     /* VEX_W_0F3858_P_2 */
10108     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10109   },
10110   {
10111     /* VEX_W_0F3859_P_2 */
10112     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10113   },
10114   {
10115     /* VEX_W_0F385A_P_2_M_0 */
10116     { "vbroadcasti128", { XM, Mxmm }, 0 },
10117   },
10118   {
10119     /* VEX_W_0F3878_P_2 */
10120     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10121   },
10122   {
10123     /* VEX_W_0F3879_P_2 */
10124     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10125   },
10126   {
10127     /* VEX_W_0F38CF_P_2 */
10128     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10129   },
10130   {
10131     /* VEX_W_0F3A00_P_2 */
10132     { Bad_Opcode },
10133     { "vpermq",         { XM, EXx, Ib }, 0 },
10134   },
10135   {
10136     /* VEX_W_0F3A01_P_2 */
10137     { Bad_Opcode },
10138     { "vpermpd",        { XM, EXx, Ib }, 0 },
10139   },
10140   {
10141     /* VEX_W_0F3A02_P_2 */
10142     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10143   },
10144   {
10145     /* VEX_W_0F3A04_P_2 */
10146     { "vpermilps",      { XM, EXx, Ib }, 0 },
10147   },
10148   {
10149     /* VEX_W_0F3A05_P_2 */
10150     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10151   },
10152   {
10153     /* VEX_W_0F3A06_P_2 */
10154     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
10155   },
10156   {
10157     /* VEX_W_0F3A18_P_2 */
10158     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
10159   },
10160   {
10161     /* VEX_W_0F3A19_P_2 */
10162     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10163   },
10164   {
10165     /* VEX_W_0F3A30_P_2_LEN_0 */
10166     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10167     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10168   },
10169   {
10170     /* VEX_W_0F3A31_P_2_LEN_0 */
10171     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10172     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10173   },
10174   {
10175     /* VEX_W_0F3A32_P_2_LEN_0 */
10176     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10177     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10178   },
10179   {
10180     /* VEX_W_0F3A33_P_2_LEN_0 */
10181     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10182     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10183   },
10184   {
10185     /* VEX_W_0F3A38_P_2 */
10186     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10187   },
10188   {
10189     /* VEX_W_0F3A39_P_2 */
10190     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10191   },
10192   {
10193     /* VEX_W_0F3A46_P_2 */
10194     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10195   },
10196   {
10197     /* VEX_W_0F3A48_P_2 */
10198     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10199     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10200   },
10201   {
10202     /* VEX_W_0F3A49_P_2 */
10203     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10204     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10205   },
10206   {
10207     /* VEX_W_0F3A4A_P_2 */
10208     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10209   },
10210   {
10211     /* VEX_W_0F3A4B_P_2 */
10212     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10213   },
10214   {
10215     /* VEX_W_0F3A4C_P_2 */
10216     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10217   },
10218   {
10219     /* VEX_W_0F3ACE_P_2 */
10220     { Bad_Opcode },
10221     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10222   },
10223   {
10224     /* VEX_W_0F3ACF_P_2 */
10225     { Bad_Opcode },
10226     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10227   },
10228
10229 #include "i386-dis-evex-w.h"
10230 };
10231
10232 static const struct dis386 mod_table[][2] = {
10233   {
10234     /* MOD_8D */
10235     { "leaS",           { Gv, M }, 0 },
10236   },
10237   {
10238     /* MOD_C6_REG_7 */
10239     { Bad_Opcode },
10240     { RM_TABLE (RM_C6_REG_7) },
10241   },
10242   {
10243     /* MOD_C7_REG_7 */
10244     { Bad_Opcode },
10245     { RM_TABLE (RM_C7_REG_7) },
10246   },
10247   {
10248     /* MOD_FF_REG_3 */
10249     { "Jcall^", { indirEp }, 0 },
10250   },
10251   {
10252     /* MOD_FF_REG_5 */
10253     { "Jjmp^", { indirEp }, 0 },
10254   },
10255   {
10256     /* MOD_0F01_REG_0 */
10257     { X86_64_TABLE (X86_64_0F01_REG_0) },
10258     { RM_TABLE (RM_0F01_REG_0) },
10259   },
10260   {
10261     /* MOD_0F01_REG_1 */
10262     { X86_64_TABLE (X86_64_0F01_REG_1) },
10263     { RM_TABLE (RM_0F01_REG_1) },
10264   },
10265   {
10266     /* MOD_0F01_REG_2 */
10267     { X86_64_TABLE (X86_64_0F01_REG_2) },
10268     { RM_TABLE (RM_0F01_REG_2) },
10269   },
10270   {
10271     /* MOD_0F01_REG_3 */
10272     { X86_64_TABLE (X86_64_0F01_REG_3) },
10273     { RM_TABLE (RM_0F01_REG_3) },
10274   },
10275   {
10276     /* MOD_0F01_REG_5 */
10277     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
10278     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
10279   },
10280   {
10281     /* MOD_0F01_REG_7 */
10282     { "invlpg",         { Mb }, 0 },
10283     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
10284   },
10285   {
10286     /* MOD_0F12_PREFIX_0 */
10287     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
10288     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
10289   },
10290   {
10291     /* MOD_0F13 */
10292     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10293   },
10294   {
10295     /* MOD_0F16_PREFIX_0 */
10296     { "movhps",         { XM, EXq }, 0 },
10297     { "movlhps",        { XM, EXq }, 0 },
10298   },
10299   {
10300     /* MOD_0F17 */
10301     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10302   },
10303   {
10304     /* MOD_0F18_REG_0 */
10305     { "prefetchnta",    { Mb }, 0 },
10306   },
10307   {
10308     /* MOD_0F18_REG_1 */
10309     { "prefetcht0",     { Mb }, 0 },
10310   },
10311   {
10312     /* MOD_0F18_REG_2 */
10313     { "prefetcht1",     { Mb }, 0 },
10314   },
10315   {
10316     /* MOD_0F18_REG_3 */
10317     { "prefetcht2",     { Mb }, 0 },
10318   },
10319   {
10320     /* MOD_0F18_REG_4 */
10321     { "nop/reserved",   { Mb }, 0 },
10322   },
10323   {
10324     /* MOD_0F18_REG_5 */
10325     { "nop/reserved",   { Mb }, 0 },
10326   },
10327   {
10328     /* MOD_0F18_REG_6 */
10329     { "nop/reserved",   { Mb }, 0 },
10330   },
10331   {
10332     /* MOD_0F18_REG_7 */
10333     { "nop/reserved",   { Mb }, 0 },
10334   },
10335   {
10336     /* MOD_0F1A_PREFIX_0 */
10337     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10338     { "nopQ",           { Ev }, 0 },
10339   },
10340   {
10341     /* MOD_0F1B_PREFIX_0 */
10342     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10343     { "nopQ",           { Ev }, 0 },
10344   },
10345   {
10346     /* MOD_0F1B_PREFIX_1 */
10347     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10348     { "nopQ",           { Ev }, 0 },
10349   },
10350   {
10351     /* MOD_0F1C_PREFIX_0 */
10352     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
10353     { "nopQ",           { Ev }, 0 },
10354   },
10355   {
10356     /* MOD_0F1E_PREFIX_1 */
10357     { "nopQ",           { Ev }, 0 },
10358     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
10359   },
10360   {
10361     /* MOD_0F24 */
10362     { Bad_Opcode },
10363     { "movL",           { Rd, Td }, 0 },
10364   },
10365   {
10366     /* MOD_0F26 */
10367     { Bad_Opcode },
10368     { "movL",           { Td, Rd }, 0 },
10369   },
10370   {
10371     /* MOD_0F2B_PREFIX_0 */
10372     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10373   },
10374   {
10375     /* MOD_0F2B_PREFIX_1 */
10376     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10377   },
10378   {
10379     /* MOD_0F2B_PREFIX_2 */
10380     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10381   },
10382   {
10383     /* MOD_0F2B_PREFIX_3 */
10384     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10385   },
10386   {
10387     /* MOD_0F50 */
10388     { Bad_Opcode },
10389     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10390   },
10391   {
10392     /* MOD_0F71_REG_2 */
10393     { Bad_Opcode },
10394     { "psrlw",          { MS, Ib }, 0 },
10395   },
10396   {
10397     /* MOD_0F71_REG_4 */
10398     { Bad_Opcode },
10399     { "psraw",          { MS, Ib }, 0 },
10400   },
10401   {
10402     /* MOD_0F71_REG_6 */
10403     { Bad_Opcode },
10404     { "psllw",          { MS, Ib }, 0 },
10405   },
10406   {
10407     /* MOD_0F72_REG_2 */
10408     { Bad_Opcode },
10409     { "psrld",          { MS, Ib }, 0 },
10410   },
10411   {
10412     /* MOD_0F72_REG_4 */
10413     { Bad_Opcode },
10414     { "psrad",          { MS, Ib }, 0 },
10415   },
10416   {
10417     /* MOD_0F72_REG_6 */
10418     { Bad_Opcode },
10419     { "pslld",          { MS, Ib }, 0 },
10420   },
10421   {
10422     /* MOD_0F73_REG_2 */
10423     { Bad_Opcode },
10424     { "psrlq",          { MS, Ib }, 0 },
10425   },
10426   {
10427     /* MOD_0F73_REG_3 */
10428     { Bad_Opcode },
10429     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10430   },
10431   {
10432     /* MOD_0F73_REG_6 */
10433     { Bad_Opcode },
10434     { "psllq",          { MS, Ib }, 0 },
10435   },
10436   {
10437     /* MOD_0F73_REG_7 */
10438     { Bad_Opcode },
10439     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10440   },
10441   {
10442     /* MOD_0FAE_REG_0 */
10443     { "fxsave",         { FXSAVE }, 0 },
10444     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
10445   },
10446   {
10447     /* MOD_0FAE_REG_1 */
10448     { "fxrstor",        { FXSAVE }, 0 },
10449     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
10450   },
10451   {
10452     /* MOD_0FAE_REG_2 */
10453     { "ldmxcsr",        { Md }, 0 },
10454     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
10455   },
10456   {
10457     /* MOD_0FAE_REG_3 */
10458     { "stmxcsr",        { Md }, 0 },
10459     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
10460   },
10461   {
10462     /* MOD_0FAE_REG_4 */
10463     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
10464     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
10465   },
10466   {
10467     /* MOD_0FAE_REG_5 */
10468     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
10469     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
10470   },
10471   {
10472     /* MOD_0FAE_REG_6 */
10473     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
10474     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
10475   },
10476   {
10477     /* MOD_0FAE_REG_7 */
10478     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
10479     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
10480   },
10481   {
10482     /* MOD_0FB2 */
10483     { "lssS",           { Gv, Mp }, 0 },
10484   },
10485   {
10486     /* MOD_0FB4 */
10487     { "lfsS",           { Gv, Mp }, 0 },
10488   },
10489   {
10490     /* MOD_0FB5 */
10491     { "lgsS",           { Gv, Mp }, 0 },
10492   },
10493   {
10494     /* MOD_0FC3 */
10495     { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
10496   },
10497   {
10498     /* MOD_0FC7_REG_3 */
10499     { "xrstors",        { FXSAVE }, 0 },
10500   },
10501   {
10502     /* MOD_0FC7_REG_4 */
10503     { "xsavec",         { FXSAVE }, 0 },
10504   },
10505   {
10506     /* MOD_0FC7_REG_5 */
10507     { "xsaves",         { FXSAVE }, 0 },
10508   },
10509   {
10510     /* MOD_0FC7_REG_6 */
10511     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
10512     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
10513   },
10514   {
10515     /* MOD_0FC7_REG_7 */
10516     { "vmptrst",        { Mq }, 0 },
10517     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
10518   },
10519   {
10520     /* MOD_0FD7 */
10521     { Bad_Opcode },
10522     { "pmovmskb",       { Gdq, MS }, 0 },
10523   },
10524   {
10525     /* MOD_0FE7_PREFIX_2 */
10526     { "movntdq",        { Mx, XM }, 0 },
10527   },
10528   {
10529     /* MOD_0FF0_PREFIX_3 */
10530     { "lddqu",          { XM, M }, 0 },
10531   },
10532   {
10533     /* MOD_0F382A_PREFIX_2 */
10534     { "movntdqa",       { XM, Mx }, 0 },
10535   },
10536   {
10537     /* MOD_0F38F5_PREFIX_2 */
10538     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10539   },
10540   {
10541     /* MOD_0F38F6_PREFIX_0 */
10542     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10543   },
10544   {
10545     /* MOD_0F38F8_PREFIX_1 */
10546     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
10547   },
10548   {
10549     /* MOD_0F38F8_PREFIX_2 */
10550     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10551   },
10552   {
10553     /* MOD_0F38F8_PREFIX_3 */
10554     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
10555   },
10556   {
10557     /* MOD_0F38F9_PREFIX_0 */
10558     { "movdiri",        { Ev, Gv }, PREFIX_OPCODE },
10559   },
10560   {
10561     /* MOD_62_32BIT */
10562     { "bound{S|}",      { Gv, Ma }, 0 },
10563     { EVEX_TABLE (EVEX_0F) },
10564   },
10565   {
10566     /* MOD_C4_32BIT */
10567     { "lesS",           { Gv, Mp }, 0 },
10568     { VEX_C4_TABLE (VEX_0F) },
10569   },
10570   {
10571     /* MOD_C5_32BIT */
10572     { "ldsS",           { Gv, Mp }, 0 },
10573     { VEX_C5_TABLE (VEX_0F) },
10574   },
10575   {
10576     /* MOD_VEX_0F12_PREFIX_0 */
10577     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10578     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10579   },
10580   {
10581     /* MOD_VEX_0F13 */
10582     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10583   },
10584   {
10585     /* MOD_VEX_0F16_PREFIX_0 */
10586     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10587     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10588   },
10589   {
10590     /* MOD_VEX_0F17 */
10591     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10592   },
10593   {
10594     /* MOD_VEX_0F2B */
10595     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
10596   },
10597   {
10598     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10599     { Bad_Opcode },
10600     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10601   },
10602   {
10603     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10604     { Bad_Opcode },
10605     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10606   },
10607   {
10608     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10609     { Bad_Opcode },
10610     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10611   },
10612   {
10613     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10614     { Bad_Opcode },
10615     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10616   },
10617   {
10618     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10619     { Bad_Opcode },
10620     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10621   },
10622   {
10623     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10624     { Bad_Opcode },
10625     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10626   },
10627   {
10628     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10629     { Bad_Opcode },
10630     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10631   },
10632   {
10633     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10634     { Bad_Opcode },
10635     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10636   },
10637   {
10638     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10639     { Bad_Opcode },
10640     { "knotw",          { MaskG, MaskR }, 0 },
10641   },
10642   {
10643     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10644     { Bad_Opcode },
10645     { "knotq",          { MaskG, MaskR }, 0 },
10646   },
10647   {
10648     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10649     { Bad_Opcode },
10650     { "knotb",          { MaskG, MaskR }, 0 },
10651   },
10652   {
10653     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10654     { Bad_Opcode },
10655     { "knotd",          { MaskG, MaskR }, 0 },
10656   },
10657   {
10658     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10659     { Bad_Opcode },
10660     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10661   },
10662   {
10663     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10664     { Bad_Opcode },
10665     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10666   },
10667   {
10668     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10669     { Bad_Opcode },
10670     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10671   },
10672   {
10673     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10674     { Bad_Opcode },
10675     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10676   },
10677  {
10678     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10679     { Bad_Opcode },
10680     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10681   },
10682   {
10683     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10684     { Bad_Opcode },
10685     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10686   },
10687   {
10688     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10689     { Bad_Opcode },
10690     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10691   },
10692   {
10693     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10694     { Bad_Opcode },
10695     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10696   },
10697   {
10698     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10699     { Bad_Opcode },
10700     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10701   },
10702   {
10703     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10704     { Bad_Opcode },
10705     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10706   },
10707   {
10708     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10709     { Bad_Opcode },
10710     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10711   },
10712   {
10713     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10714     { Bad_Opcode },
10715     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10716   },
10717   {
10718     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10719     { Bad_Opcode },
10720     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10721   },
10722   {
10723     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10724     { Bad_Opcode },
10725     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10726   },
10727   {
10728     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10729     { Bad_Opcode },
10730     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10731   },
10732   {
10733     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10734     { Bad_Opcode },
10735     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10736   },
10737   {
10738     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10739     { Bad_Opcode },
10740     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10741   },
10742   {
10743     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10744     { Bad_Opcode },
10745     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10746   },
10747   {
10748     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10749     { Bad_Opcode },
10750     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10751   },
10752   {
10753     /* MOD_VEX_0F50 */
10754     { Bad_Opcode },
10755     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
10756   },
10757   {
10758     /* MOD_VEX_0F71_REG_2 */
10759     { Bad_Opcode },
10760     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10761   },
10762   {
10763     /* MOD_VEX_0F71_REG_4 */
10764     { Bad_Opcode },
10765     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10766   },
10767   {
10768     /* MOD_VEX_0F71_REG_6 */
10769     { Bad_Opcode },
10770     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10771   },
10772   {
10773     /* MOD_VEX_0F72_REG_2 */
10774     { Bad_Opcode },
10775     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10776   },
10777   {
10778     /* MOD_VEX_0F72_REG_4 */
10779     { Bad_Opcode },
10780     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10781   },
10782   {
10783     /* MOD_VEX_0F72_REG_6 */
10784     { Bad_Opcode },
10785     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10786   },
10787   {
10788     /* MOD_VEX_0F73_REG_2 */
10789     { Bad_Opcode },
10790     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10791   },
10792   {
10793     /* MOD_VEX_0F73_REG_3 */
10794     { Bad_Opcode },
10795     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10796   },
10797   {
10798     /* MOD_VEX_0F73_REG_6 */
10799     { Bad_Opcode },
10800     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10801   },
10802   {
10803     /* MOD_VEX_0F73_REG_7 */
10804     { Bad_Opcode },
10805     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10806   },
10807   {
10808     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10809     { "kmovw",          { Ew, MaskG }, 0 },
10810     { Bad_Opcode },
10811   },
10812   {
10813     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10814     { "kmovq",          { Eq, MaskG }, 0 },
10815     { Bad_Opcode },
10816   },
10817   {
10818     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10819     { "kmovb",          { Eb, MaskG }, 0 },
10820     { Bad_Opcode },
10821   },
10822   {
10823     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10824     { "kmovd",          { Ed, MaskG }, 0 },
10825     { Bad_Opcode },
10826   },
10827   {
10828     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10829     { Bad_Opcode },
10830     { "kmovw",          { MaskG, Rdq }, 0 },
10831   },
10832   {
10833     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10834     { Bad_Opcode },
10835     { "kmovb",          { MaskG, Rdq }, 0 },
10836   },
10837   {
10838     /* MOD_VEX_0F92_P_3_LEN_0 */
10839     { Bad_Opcode },
10840     { "kmovK",          { MaskG, Rdq }, 0 },
10841   },
10842   {
10843     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10844     { Bad_Opcode },
10845     { "kmovw",          { Gdq, MaskR }, 0 },
10846   },
10847   {
10848     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10849     { Bad_Opcode },
10850     { "kmovb",          { Gdq, MaskR }, 0 },
10851   },
10852   {
10853     /* MOD_VEX_0F93_P_3_LEN_0 */
10854     { Bad_Opcode },
10855     { "kmovK",          { Gdq, MaskR }, 0 },
10856   },
10857   {
10858     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10859     { Bad_Opcode },
10860     { "kortestw", { MaskG, MaskR }, 0 },
10861   },
10862   {
10863     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10864     { Bad_Opcode },
10865     { "kortestq", { MaskG, MaskR }, 0 },
10866   },
10867   {
10868     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10869     { Bad_Opcode },
10870     { "kortestb", { MaskG, MaskR }, 0 },
10871   },
10872   {
10873     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10874     { Bad_Opcode },
10875     { "kortestd", { MaskG, MaskR }, 0 },
10876   },
10877   {
10878     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10879     { Bad_Opcode },
10880     { "ktestw", { MaskG, MaskR }, 0 },
10881   },
10882   {
10883     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10884     { Bad_Opcode },
10885     { "ktestq", { MaskG, MaskR }, 0 },
10886   },
10887   {
10888     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10889     { Bad_Opcode },
10890     { "ktestb", { MaskG, MaskR }, 0 },
10891   },
10892   {
10893     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10894     { Bad_Opcode },
10895     { "ktestd", { MaskG, MaskR }, 0 },
10896   },
10897   {
10898     /* MOD_VEX_0FAE_REG_2 */
10899     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10900   },
10901   {
10902     /* MOD_VEX_0FAE_REG_3 */
10903     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10904   },
10905   {
10906     /* MOD_VEX_0FD7_PREFIX_2 */
10907     { Bad_Opcode },
10908     { "vpmovmskb",      { Gdq, XS }, 0 },
10909   },
10910   {
10911     /* MOD_VEX_0FE7_PREFIX_2 */
10912     { "vmovntdq",       { Mx, XM }, 0 },
10913   },
10914   {
10915     /* MOD_VEX_0FF0_PREFIX_3 */
10916     { "vlddqu",         { XM, M }, 0 },
10917   },
10918   {
10919     /* MOD_VEX_0F381A_PREFIX_2 */
10920     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10921   },
10922   {
10923     /* MOD_VEX_0F382A_PREFIX_2 */
10924     { "vmovntdqa",      { XM, Mx }, 0 },
10925   },
10926   {
10927     /* MOD_VEX_0F382C_PREFIX_2 */
10928     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10929   },
10930   {
10931     /* MOD_VEX_0F382D_PREFIX_2 */
10932     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10933   },
10934   {
10935     /* MOD_VEX_0F382E_PREFIX_2 */
10936     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10937   },
10938   {
10939     /* MOD_VEX_0F382F_PREFIX_2 */
10940     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10941   },
10942   {
10943     /* MOD_VEX_0F385A_PREFIX_2 */
10944     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10945   },
10946   {
10947     /* MOD_VEX_0F388C_PREFIX_2 */
10948     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10949   },
10950   {
10951     /* MOD_VEX_0F388E_PREFIX_2 */
10952     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10953   },
10954   {
10955     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10956     { Bad_Opcode },
10957     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10958   },
10959   {
10960     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10961     { Bad_Opcode },
10962     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10963   },
10964   {
10965     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10966     { Bad_Opcode },
10967     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10968   },
10969   {
10970     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10971     { Bad_Opcode },
10972     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10973   },
10974   {
10975     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10976     { Bad_Opcode },
10977     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10978   },
10979   {
10980     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10981     { Bad_Opcode },
10982     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10983   },
10984   {
10985     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10986     { Bad_Opcode },
10987     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10988   },
10989   {
10990     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10991     { Bad_Opcode },
10992     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10993   },
10994
10995 #include "i386-dis-evex-mod.h"
10996 };
10997
10998 static const struct dis386 rm_table[][8] = {
10999   {
11000     /* RM_C6_REG_7 */
11001     { "xabort",         { Skip_MODRM, Ib }, 0 },
11002   },
11003   {
11004     /* RM_C7_REG_7 */
11005     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
11006   },
11007   {
11008     /* RM_0F01_REG_0 */
11009     { "enclv",          { Skip_MODRM }, 0 },
11010     { "vmcall",         { Skip_MODRM }, 0 },
11011     { "vmlaunch",       { Skip_MODRM }, 0 },
11012     { "vmresume",       { Skip_MODRM }, 0 },
11013     { "vmxoff",         { Skip_MODRM }, 0 },
11014     { "pconfig",        { Skip_MODRM }, 0 },
11015   },
11016   {
11017     /* RM_0F01_REG_1 */
11018     { "monitor",        { { OP_Monitor, 0 } }, 0 },
11019     { "mwait",          { { OP_Mwait, 0 } }, 0 },
11020     { "clac",           { Skip_MODRM }, 0 },
11021     { "stac",           { Skip_MODRM }, 0 },
11022     { Bad_Opcode },
11023     { Bad_Opcode },
11024     { Bad_Opcode },
11025     { "encls",          { Skip_MODRM }, 0 },
11026   },
11027   {
11028     /* RM_0F01_REG_2 */
11029     { "xgetbv",         { Skip_MODRM }, 0 },
11030     { "xsetbv",         { Skip_MODRM }, 0 },
11031     { Bad_Opcode },
11032     { Bad_Opcode },
11033     { "vmfunc",         { Skip_MODRM }, 0 },
11034     { "xend",           { Skip_MODRM }, 0 },
11035     { "xtest",          { Skip_MODRM }, 0 },
11036     { "enclu",          { Skip_MODRM }, 0 },
11037   },
11038   {
11039     /* RM_0F01_REG_3 */
11040     { "vmrun",          { Skip_MODRM }, 0 },
11041     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
11042     { "vmload",         { Skip_MODRM }, 0 },
11043     { "vmsave",         { Skip_MODRM }, 0 },
11044     { "stgi",           { Skip_MODRM }, 0 },
11045     { "clgi",           { Skip_MODRM }, 0 },
11046     { "skinit",         { Skip_MODRM }, 0 },
11047     { "invlpga",        { Skip_MODRM }, 0 },
11048   },
11049   {
11050     /* RM_0F01_REG_5_MOD_3 */
11051     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
11052     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
11053     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
11054     { Bad_Opcode },
11055     { Bad_Opcode },
11056     { Bad_Opcode },
11057     { "rdpkru",         { Skip_MODRM }, 0 },
11058     { "wrpkru",         { Skip_MODRM }, 0 },
11059   },
11060   {
11061     /* RM_0F01_REG_7_MOD_3 */
11062     { "swapgs",         { Skip_MODRM }, 0  },
11063     { "rdtscp",         { Skip_MODRM }, 0  },
11064     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
11065     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
11066     { "clzero",         { Skip_MODRM }, 0  },
11067     { "rdpru",          { Skip_MODRM }, 0  },
11068   },
11069   {
11070     /* RM_0F1E_P_1_MOD_3_REG_7 */
11071     { "nopQ",           { Ev }, 0 },
11072     { "nopQ",           { Ev }, 0 },
11073     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11074     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11075     { "nopQ",           { Ev }, 0 },
11076     { "nopQ",           { Ev }, 0 },
11077     { "nopQ",           { Ev }, 0 },
11078     { "nopQ",           { Ev }, 0 },
11079   },
11080   {
11081     /* RM_0FAE_REG_6_MOD_3 */
11082     { "mfence",         { Skip_MODRM }, 0 },
11083   },
11084   {
11085     /* RM_0FAE_REG_7_MOD_3 */
11086     { "sfence",         { Skip_MODRM }, 0 },
11087
11088   },
11089 };
11090
11091 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11092
11093 /* We use the high bit to indicate different name for the same
11094    prefix.  */
11095 #define REP_PREFIX      (0xf3 | 0x100)
11096 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11097 #define XRELEASE_PREFIX (0xf3 | 0x400)
11098 #define BND_PREFIX      (0xf2 | 0x400)
11099 #define NOTRACK_PREFIX  (0x3e | 0x100)
11100
11101 /* Remember if the current op is a jump instruction.  */
11102 static bfd_boolean op_is_jump = FALSE;
11103
11104 static int
11105 ckprefix (void)
11106 {
11107   int newrex, i, length;
11108   rex = 0;
11109   rex_ignored = 0;
11110   prefixes = 0;
11111   used_prefixes = 0;
11112   rex_used = 0;
11113   last_lock_prefix = -1;
11114   last_repz_prefix = -1;
11115   last_repnz_prefix = -1;
11116   last_data_prefix = -1;
11117   last_addr_prefix = -1;
11118   last_rex_prefix = -1;
11119   last_seg_prefix = -1;
11120   fwait_prefix = -1;
11121   active_seg_prefix = 0;
11122   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11123     all_prefixes[i] = 0;
11124   i = 0;
11125   length = 0;
11126   /* The maximum instruction length is 15bytes.  */
11127   while (length < MAX_CODE_LENGTH - 1)
11128     {
11129       FETCH_DATA (the_info, codep + 1);
11130       newrex = 0;
11131       switch (*codep)
11132         {
11133         /* REX prefixes family.  */
11134         case 0x40:
11135         case 0x41:
11136         case 0x42:
11137         case 0x43:
11138         case 0x44:
11139         case 0x45:
11140         case 0x46:
11141         case 0x47:
11142         case 0x48:
11143         case 0x49:
11144         case 0x4a:
11145         case 0x4b:
11146         case 0x4c:
11147         case 0x4d:
11148         case 0x4e:
11149         case 0x4f:
11150           if (address_mode == mode_64bit)
11151             newrex = *codep;
11152           else
11153             return 1;
11154           last_rex_prefix = i;
11155           break;
11156         case 0xf3:
11157           prefixes |= PREFIX_REPZ;
11158           last_repz_prefix = i;
11159           break;
11160         case 0xf2:
11161           prefixes |= PREFIX_REPNZ;
11162           last_repnz_prefix = i;
11163           break;
11164         case 0xf0:
11165           prefixes |= PREFIX_LOCK;
11166           last_lock_prefix = i;
11167           break;
11168         case 0x2e:
11169           prefixes |= PREFIX_CS;
11170           last_seg_prefix = i;
11171           active_seg_prefix = PREFIX_CS;
11172           break;
11173         case 0x36:
11174           prefixes |= PREFIX_SS;
11175           last_seg_prefix = i;
11176           active_seg_prefix = PREFIX_SS;
11177           break;
11178         case 0x3e:
11179           prefixes |= PREFIX_DS;
11180           last_seg_prefix = i;
11181           active_seg_prefix = PREFIX_DS;
11182           break;
11183         case 0x26:
11184           prefixes |= PREFIX_ES;
11185           last_seg_prefix = i;
11186           active_seg_prefix = PREFIX_ES;
11187           break;
11188         case 0x64:
11189           prefixes |= PREFIX_FS;
11190           last_seg_prefix = i;
11191           active_seg_prefix = PREFIX_FS;
11192           break;
11193         case 0x65:
11194           prefixes |= PREFIX_GS;
11195           last_seg_prefix = i;
11196           active_seg_prefix = PREFIX_GS;
11197           break;
11198         case 0x66:
11199           prefixes |= PREFIX_DATA;
11200           last_data_prefix = i;
11201           break;
11202         case 0x67:
11203           prefixes |= PREFIX_ADDR;
11204           last_addr_prefix = i;
11205           break;
11206         case FWAIT_OPCODE:
11207           /* fwait is really an instruction.  If there are prefixes
11208              before the fwait, they belong to the fwait, *not* to the
11209              following instruction.  */
11210           fwait_prefix = i;
11211           if (prefixes || rex)
11212             {
11213               prefixes |= PREFIX_FWAIT;
11214               codep++;
11215               /* This ensures that the previous REX prefixes are noticed
11216                  as unused prefixes, as in the return case below.  */
11217               rex_used = rex;
11218               return 1;
11219             }
11220           prefixes = PREFIX_FWAIT;
11221           break;
11222         default:
11223           return 1;
11224         }
11225       /* Rex is ignored when followed by another prefix.  */
11226       if (rex)
11227         {
11228           rex_used = rex;
11229           return 1;
11230         }
11231       if (*codep != FWAIT_OPCODE)
11232         all_prefixes[i++] = *codep;
11233       rex = newrex;
11234       codep++;
11235       length++;
11236     }
11237   return 0;
11238 }
11239
11240 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11241    prefix byte.  */
11242
11243 static const char *
11244 prefix_name (int pref, int sizeflag)
11245 {
11246   static const char *rexes [16] =
11247     {
11248       "rex",            /* 0x40 */
11249       "rex.B",          /* 0x41 */
11250       "rex.X",          /* 0x42 */
11251       "rex.XB",         /* 0x43 */
11252       "rex.R",          /* 0x44 */
11253       "rex.RB",         /* 0x45 */
11254       "rex.RX",         /* 0x46 */
11255       "rex.RXB",        /* 0x47 */
11256       "rex.W",          /* 0x48 */
11257       "rex.WB",         /* 0x49 */
11258       "rex.WX",         /* 0x4a */
11259       "rex.WXB",        /* 0x4b */
11260       "rex.WR",         /* 0x4c */
11261       "rex.WRB",        /* 0x4d */
11262       "rex.WRX",        /* 0x4e */
11263       "rex.WRXB",       /* 0x4f */
11264     };
11265
11266   switch (pref)
11267     {
11268     /* REX prefixes family.  */
11269     case 0x40:
11270     case 0x41:
11271     case 0x42:
11272     case 0x43:
11273     case 0x44:
11274     case 0x45:
11275     case 0x46:
11276     case 0x47:
11277     case 0x48:
11278     case 0x49:
11279     case 0x4a:
11280     case 0x4b:
11281     case 0x4c:
11282     case 0x4d:
11283     case 0x4e:
11284     case 0x4f:
11285       return rexes [pref - 0x40];
11286     case 0xf3:
11287       return "repz";
11288     case 0xf2:
11289       return "repnz";
11290     case 0xf0:
11291       return "lock";
11292     case 0x2e:
11293       return "cs";
11294     case 0x36:
11295       return "ss";
11296     case 0x3e:
11297       return "ds";
11298     case 0x26:
11299       return "es";
11300     case 0x64:
11301       return "fs";
11302     case 0x65:
11303       return "gs";
11304     case 0x66:
11305       return (sizeflag & DFLAG) ? "data16" : "data32";
11306     case 0x67:
11307       if (address_mode == mode_64bit)
11308         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11309       else
11310         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11311     case FWAIT_OPCODE:
11312       return "fwait";
11313     case REP_PREFIX:
11314       return "rep";
11315     case XACQUIRE_PREFIX:
11316       return "xacquire";
11317     case XRELEASE_PREFIX:
11318       return "xrelease";
11319     case BND_PREFIX:
11320       return "bnd";
11321     case NOTRACK_PREFIX:
11322       return "notrack";
11323     default:
11324       return NULL;
11325     }
11326 }
11327
11328 static char op_out[MAX_OPERANDS][100];
11329 static int op_ad, op_index[MAX_OPERANDS];
11330 static int two_source_ops;
11331 static bfd_vma op_address[MAX_OPERANDS];
11332 static bfd_vma op_riprel[MAX_OPERANDS];
11333 static bfd_vma start_pc;
11334
11335 /*
11336  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11337  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11338  *   section of the "Virtual 8086 Mode" chapter.)
11339  * 'pc' should be the address of this instruction, it will
11340  *   be used to print the target address if this is a relative jump or call
11341  * The function returns the length of this instruction in bytes.
11342  */
11343
11344 static char intel_syntax;
11345 static char intel_mnemonic = !SYSV386_COMPAT;
11346 static char open_char;
11347 static char close_char;
11348 static char separator_char;
11349 static char scale_char;
11350
11351 enum x86_64_isa
11352 {
11353   amd64 = 1,
11354   intel64
11355 };
11356
11357 static enum x86_64_isa isa64;
11358
11359 /* Here for backwards compatibility.  When gdb stops using
11360    print_insn_i386_att and print_insn_i386_intel these functions can
11361    disappear, and print_insn_i386 be merged into print_insn.  */
11362 int
11363 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11364 {
11365   intel_syntax = 0;
11366
11367   return print_insn (pc, info);
11368 }
11369
11370 int
11371 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11372 {
11373   intel_syntax = 1;
11374
11375   return print_insn (pc, info);
11376 }
11377
11378 int
11379 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11380 {
11381   intel_syntax = -1;
11382
11383   return print_insn (pc, info);
11384 }
11385
11386 void
11387 print_i386_disassembler_options (FILE *stream)
11388 {
11389   fprintf (stream, _("\n\
11390 The following i386/x86-64 specific disassembler options are supported for use\n\
11391 with the -M switch (multiple options should be separated by commas):\n"));
11392
11393   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11394   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11395   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11396   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11397   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11398   fprintf (stream, _("  att-mnemonic\n"
11399                      "              Display instruction in AT&T mnemonic\n"));
11400   fprintf (stream, _("  intel-mnemonic\n"
11401                      "              Display instruction in Intel mnemonic\n"));
11402   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11403   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11404   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11405   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11406   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11407   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11408   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11409   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11410 }
11411
11412 /* Bad opcode.  */
11413 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11414
11415 /* Get a pointer to struct dis386 with a valid name.  */
11416
11417 static const struct dis386 *
11418 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11419 {
11420   int vindex, vex_table_index;
11421
11422   if (dp->name != NULL)
11423     return dp;
11424
11425   switch (dp->op[0].bytemode)
11426     {
11427     case USE_REG_TABLE:
11428       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11429       break;
11430
11431     case USE_MOD_TABLE:
11432       vindex = modrm.mod == 0x3 ? 1 : 0;
11433       dp = &mod_table[dp->op[1].bytemode][vindex];
11434       break;
11435
11436     case USE_RM_TABLE:
11437       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11438       break;
11439
11440     case USE_PREFIX_TABLE:
11441       if (need_vex)
11442         {
11443           /* The prefix in VEX is implicit.  */
11444           switch (vex.prefix)
11445             {
11446             case 0:
11447               vindex = 0;
11448               break;
11449             case REPE_PREFIX_OPCODE:
11450               vindex = 1;
11451               break;
11452             case DATA_PREFIX_OPCODE:
11453               vindex = 2;
11454               break;
11455             case REPNE_PREFIX_OPCODE:
11456               vindex = 3;
11457               break;
11458             default:
11459               abort ();
11460               break;
11461             }
11462         }
11463       else
11464         {
11465           int last_prefix = -1;
11466           int prefix = 0;
11467           vindex = 0;
11468           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11469              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11470              last one wins.  */
11471           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11472             {
11473               if (last_repz_prefix > last_repnz_prefix)
11474                 {
11475                   vindex = 1;
11476                   prefix = PREFIX_REPZ;
11477                   last_prefix = last_repz_prefix;
11478                 }
11479               else
11480                 {
11481                   vindex = 3;
11482                   prefix = PREFIX_REPNZ;
11483                   last_prefix = last_repnz_prefix;
11484                 }
11485
11486               /* Check if prefix should be ignored.  */
11487               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11488                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11489                    & prefix) != 0)
11490                 vindex = 0;
11491             }
11492
11493           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11494             {
11495               vindex = 2;
11496               prefix = PREFIX_DATA;
11497               last_prefix = last_data_prefix;
11498             }
11499
11500           if (vindex != 0)
11501             {
11502               used_prefixes |= prefix;
11503               all_prefixes[last_prefix] = 0;
11504             }
11505         }
11506       dp = &prefix_table[dp->op[1].bytemode][vindex];
11507       break;
11508
11509     case USE_X86_64_TABLE:
11510       vindex = address_mode == mode_64bit ? 1 : 0;
11511       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11512       break;
11513
11514     case USE_3BYTE_TABLE:
11515       FETCH_DATA (info, codep + 2);
11516       vindex = *codep++;
11517       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11518       end_codep = codep;
11519       modrm.mod = (*codep >> 6) & 3;
11520       modrm.reg = (*codep >> 3) & 7;
11521       modrm.rm = *codep & 7;
11522       break;
11523
11524     case USE_VEX_LEN_TABLE:
11525       if (!need_vex)
11526         abort ();
11527
11528       switch (vex.length)
11529         {
11530         case 128:
11531           vindex = 0;
11532           break;
11533         case 256:
11534           vindex = 1;
11535           break;
11536         default:
11537           abort ();
11538           break;
11539         }
11540
11541       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11542       break;
11543
11544     case USE_EVEX_LEN_TABLE:
11545       if (!vex.evex)
11546         abort ();
11547
11548       switch (vex.length)
11549         {
11550         case 128:
11551           vindex = 0;
11552           break;
11553         case 256:
11554           vindex = 1;
11555           break;
11556         case 512:
11557           vindex = 2;
11558           break;
11559         default:
11560           abort ();
11561           break;
11562         }
11563
11564       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11565       break;
11566
11567     case USE_XOP_8F_TABLE:
11568       FETCH_DATA (info, codep + 3);
11569       /* All bits in the REX prefix are ignored.  */
11570       rex_ignored = rex;
11571       rex = ~(*codep >> 5) & 0x7;
11572
11573       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11574       switch ((*codep & 0x1f))
11575         {
11576         default:
11577           dp = &bad_opcode;
11578           return dp;
11579         case 0x8:
11580           vex_table_index = XOP_08;
11581           break;
11582         case 0x9:
11583           vex_table_index = XOP_09;
11584           break;
11585         case 0xa:
11586           vex_table_index = XOP_0A;
11587           break;
11588         }
11589       codep++;
11590       vex.w = *codep & 0x80;
11591       if (vex.w && address_mode == mode_64bit)
11592         rex |= REX_W;
11593
11594       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11595       if (address_mode != mode_64bit)
11596         {
11597           /* In 16/32-bit mode REX_B is silently ignored.  */
11598           rex &= ~REX_B;
11599         }
11600
11601       vex.length = (*codep & 0x4) ? 256 : 128;
11602       switch ((*codep & 0x3))
11603         {
11604         case 0:
11605           break;
11606         case 1:
11607           vex.prefix = DATA_PREFIX_OPCODE;
11608           break;
11609         case 2:
11610           vex.prefix = REPE_PREFIX_OPCODE;
11611           break;
11612         case 3:
11613           vex.prefix = REPNE_PREFIX_OPCODE;
11614           break;
11615         }
11616       need_vex = 1;
11617       need_vex_reg = 1;
11618       codep++;
11619       vindex = *codep++;
11620       dp = &xop_table[vex_table_index][vindex];
11621
11622       end_codep = codep;
11623       FETCH_DATA (info, codep + 1);
11624       modrm.mod = (*codep >> 6) & 3;
11625       modrm.reg = (*codep >> 3) & 7;
11626       modrm.rm = *codep & 7;
11627       break;
11628
11629     case USE_VEX_C4_TABLE:
11630       /* VEX prefix.  */
11631       FETCH_DATA (info, codep + 3);
11632       /* All bits in the REX prefix are ignored.  */
11633       rex_ignored = rex;
11634       rex = ~(*codep >> 5) & 0x7;
11635       switch ((*codep & 0x1f))
11636         {
11637         default:
11638           dp = &bad_opcode;
11639           return dp;
11640         case 0x1:
11641           vex_table_index = VEX_0F;
11642           break;
11643         case 0x2:
11644           vex_table_index = VEX_0F38;
11645           break;
11646         case 0x3:
11647           vex_table_index = VEX_0F3A;
11648           break;
11649         }
11650       codep++;
11651       vex.w = *codep & 0x80;
11652       if (address_mode == mode_64bit)
11653         {
11654           if (vex.w)
11655             rex |= REX_W;
11656         }
11657       else
11658         {
11659           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11660              is ignored, other REX bits are 0 and the highest bit in
11661              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11662           rex = 0;
11663         }
11664       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11665       vex.length = (*codep & 0x4) ? 256 : 128;
11666       switch ((*codep & 0x3))
11667         {
11668         case 0:
11669           break;
11670         case 1:
11671           vex.prefix = DATA_PREFIX_OPCODE;
11672           break;
11673         case 2:
11674           vex.prefix = REPE_PREFIX_OPCODE;
11675           break;
11676         case 3:
11677           vex.prefix = REPNE_PREFIX_OPCODE;
11678           break;
11679         }
11680       need_vex = 1;
11681       need_vex_reg = 1;
11682       codep++;
11683       vindex = *codep++;
11684       dp = &vex_table[vex_table_index][vindex];
11685       end_codep = codep;
11686       /* There is no MODRM byte for VEX0F 77.  */
11687       if (vex_table_index != VEX_0F || vindex != 0x77)
11688         {
11689           FETCH_DATA (info, codep + 1);
11690           modrm.mod = (*codep >> 6) & 3;
11691           modrm.reg = (*codep >> 3) & 7;
11692           modrm.rm = *codep & 7;
11693         }
11694       break;
11695
11696     case USE_VEX_C5_TABLE:
11697       /* VEX prefix.  */
11698       FETCH_DATA (info, codep + 2);
11699       /* All bits in the REX prefix are ignored.  */
11700       rex_ignored = rex;
11701       rex = (*codep & 0x80) ? 0 : REX_R;
11702
11703       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11704          VEX.vvvv is 1.  */
11705       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11706       vex.length = (*codep & 0x4) ? 256 : 128;
11707       switch ((*codep & 0x3))
11708         {
11709         case 0:
11710           break;
11711         case 1:
11712           vex.prefix = DATA_PREFIX_OPCODE;
11713           break;
11714         case 2:
11715           vex.prefix = REPE_PREFIX_OPCODE;
11716           break;
11717         case 3:
11718           vex.prefix = REPNE_PREFIX_OPCODE;
11719           break;
11720         }
11721       need_vex = 1;
11722       need_vex_reg = 1;
11723       codep++;
11724       vindex = *codep++;
11725       dp = &vex_table[dp->op[1].bytemode][vindex];
11726       end_codep = codep;
11727       /* There is no MODRM byte for VEX 77.  */
11728       if (vindex != 0x77)
11729         {
11730           FETCH_DATA (info, codep + 1);
11731           modrm.mod = (*codep >> 6) & 3;
11732           modrm.reg = (*codep >> 3) & 7;
11733           modrm.rm = *codep & 7;
11734         }
11735       break;
11736
11737     case USE_VEX_W_TABLE:
11738       if (!need_vex)
11739         abort ();
11740
11741       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11742       break;
11743
11744     case USE_EVEX_TABLE:
11745       two_source_ops = 0;
11746       /* EVEX prefix.  */
11747       vex.evex = 1;
11748       FETCH_DATA (info, codep + 4);
11749       /* All bits in the REX prefix are ignored.  */
11750       rex_ignored = rex;
11751       /* The first byte after 0x62.  */
11752       rex = ~(*codep >> 5) & 0x7;
11753       vex.r = *codep & 0x10;
11754       switch ((*codep & 0xf))
11755         {
11756         default:
11757           return &bad_opcode;
11758         case 0x1:
11759           vex_table_index = EVEX_0F;
11760           break;
11761         case 0x2:
11762           vex_table_index = EVEX_0F38;
11763           break;
11764         case 0x3:
11765           vex_table_index = EVEX_0F3A;
11766           break;
11767         }
11768
11769       /* The second byte after 0x62.  */
11770       codep++;
11771       vex.w = *codep & 0x80;
11772       if (vex.w && address_mode == mode_64bit)
11773         rex |= REX_W;
11774
11775       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11776
11777       /* The U bit.  */
11778       if (!(*codep & 0x4))
11779         return &bad_opcode;
11780
11781       switch ((*codep & 0x3))
11782         {
11783         case 0:
11784           break;
11785         case 1:
11786           vex.prefix = DATA_PREFIX_OPCODE;
11787           break;
11788         case 2:
11789           vex.prefix = REPE_PREFIX_OPCODE;
11790           break;
11791         case 3:
11792           vex.prefix = REPNE_PREFIX_OPCODE;
11793           break;
11794         }
11795
11796       /* The third byte after 0x62.  */
11797       codep++;
11798
11799       /* Remember the static rounding bits.  */
11800       vex.ll = (*codep >> 5) & 3;
11801       vex.b = (*codep & 0x10) != 0;
11802
11803       vex.v = *codep & 0x8;
11804       vex.mask_register_specifier = *codep & 0x7;
11805       vex.zeroing = *codep & 0x80;
11806
11807       if (address_mode != mode_64bit)
11808         {
11809           /* In 16/32-bit mode silently ignore following bits.  */
11810           rex &= ~REX_B;
11811           vex.r = 1;
11812           vex.v = 1;
11813         }
11814
11815       need_vex = 1;
11816       need_vex_reg = 1;
11817       codep++;
11818       vindex = *codep++;
11819       dp = &evex_table[vex_table_index][vindex];
11820       end_codep = codep;
11821       FETCH_DATA (info, codep + 1);
11822       modrm.mod = (*codep >> 6) & 3;
11823       modrm.reg = (*codep >> 3) & 7;
11824       modrm.rm = *codep & 7;
11825
11826       /* Set vector length.  */
11827       if (modrm.mod == 3 && vex.b)
11828         vex.length = 512;
11829       else
11830         {
11831           switch (vex.ll)
11832             {
11833             case 0x0:
11834               vex.length = 128;
11835               break;
11836             case 0x1:
11837               vex.length = 256;
11838               break;
11839             case 0x2:
11840               vex.length = 512;
11841               break;
11842             default:
11843               return &bad_opcode;
11844             }
11845         }
11846       break;
11847
11848     case 0:
11849       dp = &bad_opcode;
11850       break;
11851
11852     default:
11853       abort ();
11854     }
11855
11856   if (dp->name != NULL)
11857     return dp;
11858   else
11859     return get_valid_dis386 (dp, info);
11860 }
11861
11862 static void
11863 get_sib (disassemble_info *info, int sizeflag)
11864 {
11865   /* If modrm.mod == 3, operand must be register.  */
11866   if (need_modrm
11867       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11868       && modrm.mod != 3
11869       && modrm.rm == 4)
11870     {
11871       FETCH_DATA (info, codep + 2);
11872       sib.index = (codep [1] >> 3) & 7;
11873       sib.scale = (codep [1] >> 6) & 3;
11874       sib.base = codep [1] & 7;
11875     }
11876 }
11877
11878 static int
11879 print_insn (bfd_vma pc, disassemble_info *info)
11880 {
11881   const struct dis386 *dp;
11882   int i;
11883   char *op_txt[MAX_OPERANDS];
11884   int needcomma;
11885   int sizeflag, orig_sizeflag;
11886   const char *p;
11887   struct dis_private priv;
11888   int prefix_length;
11889
11890   priv.orig_sizeflag = AFLAG | DFLAG;
11891   if ((info->mach & bfd_mach_i386_i386) != 0)
11892     address_mode = mode_32bit;
11893   else if (info->mach == bfd_mach_i386_i8086)
11894     {
11895       address_mode = mode_16bit;
11896       priv.orig_sizeflag = 0;
11897     }
11898   else
11899     address_mode = mode_64bit;
11900
11901   if (intel_syntax == (char) -1)
11902     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11903
11904   for (p = info->disassembler_options; p != NULL; )
11905     {
11906       if (CONST_STRNEQ (p, "amd64"))
11907         isa64 = amd64;
11908       else if (CONST_STRNEQ (p, "intel64"))
11909         isa64 = intel64;
11910       else if (CONST_STRNEQ (p, "x86-64"))
11911         {
11912           address_mode = mode_64bit;
11913           priv.orig_sizeflag = AFLAG | DFLAG;
11914         }
11915       else if (CONST_STRNEQ (p, "i386"))
11916         {
11917           address_mode = mode_32bit;
11918           priv.orig_sizeflag = AFLAG | DFLAG;
11919         }
11920       else if (CONST_STRNEQ (p, "i8086"))
11921         {
11922           address_mode = mode_16bit;
11923           priv.orig_sizeflag = 0;
11924         }
11925       else if (CONST_STRNEQ (p, "intel"))
11926         {
11927           intel_syntax = 1;
11928           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11929             intel_mnemonic = 1;
11930         }
11931       else if (CONST_STRNEQ (p, "att"))
11932         {
11933           intel_syntax = 0;
11934           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11935             intel_mnemonic = 0;
11936         }
11937       else if (CONST_STRNEQ (p, "addr"))
11938         {
11939           if (address_mode == mode_64bit)
11940             {
11941               if (p[4] == '3' && p[5] == '2')
11942                 priv.orig_sizeflag &= ~AFLAG;
11943               else if (p[4] == '6' && p[5] == '4')
11944                 priv.orig_sizeflag |= AFLAG;
11945             }
11946           else
11947             {
11948               if (p[4] == '1' && p[5] == '6')
11949                 priv.orig_sizeflag &= ~AFLAG;
11950               else if (p[4] == '3' && p[5] == '2')
11951                 priv.orig_sizeflag |= AFLAG;
11952             }
11953         }
11954       else if (CONST_STRNEQ (p, "data"))
11955         {
11956           if (p[4] == '1' && p[5] == '6')
11957             priv.orig_sizeflag &= ~DFLAG;
11958           else if (p[4] == '3' && p[5] == '2')
11959             priv.orig_sizeflag |= DFLAG;
11960         }
11961       else if (CONST_STRNEQ (p, "suffix"))
11962         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11963
11964       p = strchr (p, ',');
11965       if (p != NULL)
11966         p++;
11967     }
11968
11969   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11970     {
11971       (*info->fprintf_func) (info->stream,
11972                              _("64-bit address is disabled"));
11973       return -1;
11974     }
11975
11976   if (intel_syntax)
11977     {
11978       names64 = intel_names64;
11979       names32 = intel_names32;
11980       names16 = intel_names16;
11981       names8 = intel_names8;
11982       names8rex = intel_names8rex;
11983       names_seg = intel_names_seg;
11984       names_mm = intel_names_mm;
11985       names_bnd = intel_names_bnd;
11986       names_xmm = intel_names_xmm;
11987       names_ymm = intel_names_ymm;
11988       names_zmm = intel_names_zmm;
11989       index64 = intel_index64;
11990       index32 = intel_index32;
11991       names_mask = intel_names_mask;
11992       index16 = intel_index16;
11993       open_char = '[';
11994       close_char = ']';
11995       separator_char = '+';
11996       scale_char = '*';
11997     }
11998   else
11999     {
12000       names64 = att_names64;
12001       names32 = att_names32;
12002       names16 = att_names16;
12003       names8 = att_names8;
12004       names8rex = att_names8rex;
12005       names_seg = att_names_seg;
12006       names_mm = att_names_mm;
12007       names_bnd = att_names_bnd;
12008       names_xmm = att_names_xmm;
12009       names_ymm = att_names_ymm;
12010       names_zmm = att_names_zmm;
12011       index64 = att_index64;
12012       index32 = att_index32;
12013       names_mask = att_names_mask;
12014       index16 = att_index16;
12015       open_char = '(';
12016       close_char =  ')';
12017       separator_char = ',';
12018       scale_char = ',';
12019     }
12020
12021   /* The output looks better if we put 7 bytes on a line, since that
12022      puts most long word instructions on a single line.  Use 8 bytes
12023      for Intel L1OM.  */
12024   if ((info->mach & bfd_mach_l1om) != 0)
12025     info->bytes_per_line = 8;
12026   else
12027     info->bytes_per_line = 7;
12028
12029   info->private_data = &priv;
12030   priv.max_fetched = priv.the_buffer;
12031   priv.insn_start = pc;
12032
12033   obuf[0] = 0;
12034   for (i = 0; i < MAX_OPERANDS; ++i)
12035     {
12036       op_out[i][0] = 0;
12037       op_index[i] = -1;
12038     }
12039
12040   the_info = info;
12041   start_pc = pc;
12042   start_codep = priv.the_buffer;
12043   codep = priv.the_buffer;
12044
12045   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12046     {
12047       const char *name;
12048
12049       /* Getting here means we tried for data but didn't get it.  That
12050          means we have an incomplete instruction of some sort.  Just
12051          print the first byte as a prefix or a .byte pseudo-op.  */
12052       if (codep > priv.the_buffer)
12053         {
12054           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12055           if (name != NULL)
12056             (*info->fprintf_func) (info->stream, "%s", name);
12057           else
12058             {
12059               /* Just print the first byte as a .byte instruction.  */
12060               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12061                                      (unsigned int) priv.the_buffer[0]);
12062             }
12063
12064           return 1;
12065         }
12066
12067       return -1;
12068     }
12069
12070   obufp = obuf;
12071   sizeflag = priv.orig_sizeflag;
12072
12073   if (!ckprefix () || rex_used)
12074     {
12075       /* Too many prefixes or unused REX prefixes.  */
12076       for (i = 0;
12077            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12078            i++)
12079         (*info->fprintf_func) (info->stream, "%s%s",
12080                                i == 0 ? "" : " ",
12081                                prefix_name (all_prefixes[i], sizeflag));
12082       return i;
12083     }
12084
12085   insn_codep = codep;
12086
12087   FETCH_DATA (info, codep + 1);
12088   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12089
12090   if (((prefixes & PREFIX_FWAIT)
12091        && ((*codep < 0xd8) || (*codep > 0xdf))))
12092     {
12093       /* Handle prefixes before fwait.  */
12094       for (i = 0; i < fwait_prefix && all_prefixes[i];
12095            i++)
12096         (*info->fprintf_func) (info->stream, "%s ",
12097                                prefix_name (all_prefixes[i], sizeflag));
12098       (*info->fprintf_func) (info->stream, "fwait");
12099       return i + 1;
12100     }
12101
12102   if (*codep == 0x0f)
12103     {
12104       unsigned char threebyte;
12105
12106       codep++;
12107       FETCH_DATA (info, codep + 1);
12108       threebyte = *codep;
12109       dp = &dis386_twobyte[threebyte];
12110       need_modrm = twobyte_has_modrm[*codep];
12111       codep++;
12112     }
12113   else
12114     {
12115       dp = &dis386[*codep];
12116       need_modrm = onebyte_has_modrm[*codep];
12117       codep++;
12118     }
12119
12120   /* Save sizeflag for printing the extra prefixes later before updating
12121      it for mnemonic and operand processing.  The prefix names depend
12122      only on the address mode.  */
12123   orig_sizeflag = sizeflag;
12124   if (prefixes & PREFIX_ADDR)
12125     sizeflag ^= AFLAG;
12126   if ((prefixes & PREFIX_DATA))
12127     sizeflag ^= DFLAG;
12128
12129   end_codep = codep;
12130   if (need_modrm)
12131     {
12132       FETCH_DATA (info, codep + 1);
12133       modrm.mod = (*codep >> 6) & 3;
12134       modrm.reg = (*codep >> 3) & 7;
12135       modrm.rm = *codep & 7;
12136     }
12137
12138   need_vex = 0;
12139   need_vex_reg = 0;
12140   vex_w_done = 0;
12141   memset (&vex, 0, sizeof (vex));
12142
12143   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12144     {
12145       get_sib (info, sizeflag);
12146       dofloat (sizeflag);
12147     }
12148   else
12149     {
12150       dp = get_valid_dis386 (dp, info);
12151       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12152         {
12153           get_sib (info, sizeflag);
12154           for (i = 0; i < MAX_OPERANDS; ++i)
12155             {
12156               obufp = op_out[i];
12157               op_ad = MAX_OPERANDS - 1 - i;
12158               if (dp->op[i].rtn)
12159                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12160               /* For EVEX instruction after the last operand masking
12161                  should be printed.  */
12162               if (i == 0 && vex.evex)
12163                 {
12164                   /* Don't print {%k0}.  */
12165                   if (vex.mask_register_specifier)
12166                     {
12167                       oappend ("{");
12168                       oappend (names_mask[vex.mask_register_specifier]);
12169                       oappend ("}");
12170                     }
12171                   if (vex.zeroing)
12172                     oappend ("{z}");
12173                 }
12174             }
12175         }
12176     }
12177
12178   /* Clear instruction information.  */
12179   if (the_info)
12180     {
12181       the_info->insn_info_valid = 0;
12182       the_info->branch_delay_insns = 0;
12183       the_info->data_size = 0;
12184       the_info->insn_type = dis_noninsn;
12185       the_info->target = 0;
12186       the_info->target2 = 0;
12187     }
12188
12189   /* Reset jump operation indicator.  */
12190   op_is_jump = FALSE;
12191
12192   {
12193     int jump_detection = 0;
12194
12195     /* Extract flags.  */
12196     for (i = 0; i < MAX_OPERANDS; ++i)
12197       {
12198         if ((dp->op[i].rtn == OP_J)
12199             || (dp->op[i].rtn == OP_indirE))
12200           jump_detection |= 1;
12201         else if ((dp->op[i].rtn == BND_Fixup)
12202                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
12203           jump_detection |= 2;
12204         else if ((dp->op[i].bytemode == cond_jump_mode)
12205                  || (dp->op[i].bytemode == loop_jcxz_mode))
12206           jump_detection |= 4;
12207       }
12208
12209     /* Determine if this is a jump or branch.  */
12210     if ((jump_detection & 0x3) == 0x3)
12211       {
12212         op_is_jump = TRUE;
12213         if (jump_detection & 0x4)
12214           the_info->insn_type = dis_condbranch;
12215         else
12216           the_info->insn_type =
12217             (dp->name && !strncmp(dp->name, "call", 4))
12218             ? dis_jsr : dis_branch;
12219       }
12220   }
12221
12222   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12223      are all 0s in inverted form.  */
12224   if (need_vex && vex.register_specifier != 0)
12225     {
12226       (*info->fprintf_func) (info->stream, "(bad)");
12227       return end_codep - priv.the_buffer;
12228     }
12229
12230   /* Check if the REX prefix is used.  */
12231   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12232     all_prefixes[last_rex_prefix] = 0;
12233
12234   /* Check if the SEG prefix is used.  */
12235   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12236                    | PREFIX_FS | PREFIX_GS)) != 0
12237       && (used_prefixes & active_seg_prefix) != 0)
12238     all_prefixes[last_seg_prefix] = 0;
12239
12240   /* Check if the ADDR prefix is used.  */
12241   if ((prefixes & PREFIX_ADDR) != 0
12242       && (used_prefixes & PREFIX_ADDR) != 0)
12243     all_prefixes[last_addr_prefix] = 0;
12244
12245   /* Check if the DATA prefix is used.  */
12246   if ((prefixes & PREFIX_DATA) != 0
12247       && (used_prefixes & PREFIX_DATA) != 0)
12248     all_prefixes[last_data_prefix] = 0;
12249
12250   /* Print the extra prefixes.  */
12251   prefix_length = 0;
12252   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12253     if (all_prefixes[i])
12254       {
12255         const char *name;
12256         name = prefix_name (all_prefixes[i], orig_sizeflag);
12257         if (name == NULL)
12258           abort ();
12259         prefix_length += strlen (name) + 1;
12260         (*info->fprintf_func) (info->stream, "%s ", name);
12261       }
12262
12263   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12264      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12265      used by putop and MMX/SSE operand and may be overriden by the
12266      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12267      separately.  */
12268   if (dp->prefix_requirement == PREFIX_OPCODE
12269       && (((need_vex
12270             ? vex.prefix == REPE_PREFIX_OPCODE
12271               || vex.prefix == REPNE_PREFIX_OPCODE
12272             : (prefixes
12273                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12274            && (used_prefixes
12275                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12276           || (((need_vex
12277                 ? vex.prefix == DATA_PREFIX_OPCODE
12278                 : ((prefixes
12279                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12280                    == PREFIX_DATA))
12281                && (used_prefixes & PREFIX_DATA) == 0))))
12282     {
12283       (*info->fprintf_func) (info->stream, "(bad)");
12284       return end_codep - priv.the_buffer;
12285     }
12286
12287   /* Check maximum code length.  */
12288   if ((codep - start_codep) > MAX_CODE_LENGTH)
12289     {
12290       (*info->fprintf_func) (info->stream, "(bad)");
12291       return MAX_CODE_LENGTH;
12292     }
12293
12294   obufp = mnemonicendp;
12295   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12296     oappend (" ");
12297   oappend (" ");
12298   (*info->fprintf_func) (info->stream, "%s", obuf);
12299
12300   /* The enter and bound instructions are printed with operands in the same
12301      order as the intel book; everything else is printed in reverse order.  */
12302   if (intel_syntax || two_source_ops)
12303     {
12304       bfd_vma riprel;
12305
12306       for (i = 0; i < MAX_OPERANDS; ++i)
12307         op_txt[i] = op_out[i];
12308
12309       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12310           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12311         {
12312           op_txt[2] = op_out[3];
12313           op_txt[3] = op_out[2];
12314         }
12315
12316       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12317         {
12318           op_ad = op_index[i];
12319           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12320           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12321           riprel = op_riprel[i];
12322           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12323           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12324         }
12325     }
12326   else
12327     {
12328       for (i = 0; i < MAX_OPERANDS; ++i)
12329         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12330     }
12331
12332   needcomma = 0;
12333   for (i = 0; i < MAX_OPERANDS; ++i)
12334     if (*op_txt[i])
12335       {
12336         if (needcomma)
12337           (*info->fprintf_func) (info->stream, ",");
12338         if (op_index[i] != -1 && !op_riprel[i])
12339           {
12340             bfd_vma target = (bfd_vma) op_address[op_index[i]];
12341
12342             if (the_info && op_is_jump)
12343               {
12344                 the_info->insn_info_valid = 1;
12345                 the_info->branch_delay_insns = 0;
12346                 the_info->data_size = 0;
12347                 the_info->target = target;
12348                 the_info->target2 = 0;
12349               }
12350             (*info->print_address_func) (target, info);
12351           }
12352         else
12353           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12354         needcomma = 1;
12355       }
12356
12357   for (i = 0; i < MAX_OPERANDS; i++)
12358     if (op_index[i] != -1 && op_riprel[i])
12359       {
12360         (*info->fprintf_func) (info->stream, "        # ");
12361         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12362                                                 + op_address[op_index[i]]), info);
12363         break;
12364       }
12365   return codep - priv.the_buffer;
12366 }
12367
12368 static const char *float_mem[] = {
12369   /* d8 */
12370   "fadd{s|}",
12371   "fmul{s|}",
12372   "fcom{s|}",
12373   "fcomp{s|}",
12374   "fsub{s|}",
12375   "fsubr{s|}",
12376   "fdiv{s|}",
12377   "fdivr{s|}",
12378   /* d9 */
12379   "fld{s|}",
12380   "(bad)",
12381   "fst{s|}",
12382   "fstp{s|}",
12383   "fldenvIC",
12384   "fldcw",
12385   "fNstenvIC",
12386   "fNstcw",
12387   /* da */
12388   "fiadd{l|}",
12389   "fimul{l|}",
12390   "ficom{l|}",
12391   "ficomp{l|}",
12392   "fisub{l|}",
12393   "fisubr{l|}",
12394   "fidiv{l|}",
12395   "fidivr{l|}",
12396   /* db */
12397   "fild{l|}",
12398   "fisttp{l|}",
12399   "fist{l|}",
12400   "fistp{l|}",
12401   "(bad)",
12402   "fld{t||t|}",
12403   "(bad)",
12404   "fstp{t||t|}",
12405   /* dc */
12406   "fadd{l|}",
12407   "fmul{l|}",
12408   "fcom{l|}",
12409   "fcomp{l|}",
12410   "fsub{l|}",
12411   "fsubr{l|}",
12412   "fdiv{l|}",
12413   "fdivr{l|}",
12414   /* dd */
12415   "fld{l|}",
12416   "fisttp{ll|}",
12417   "fst{l||}",
12418   "fstp{l|}",
12419   "frstorIC",
12420   "(bad)",
12421   "fNsaveIC",
12422   "fNstsw",
12423   /* de */
12424   "fiadd{s|}",
12425   "fimul{s|}",
12426   "ficom{s|}",
12427   "ficomp{s|}",
12428   "fisub{s|}",
12429   "fisubr{s|}",
12430   "fidiv{s|}",
12431   "fidivr{s|}",
12432   /* df */
12433   "fild{s|}",
12434   "fisttp{s|}",
12435   "fist{s|}",
12436   "fistp{s|}",
12437   "fbld",
12438   "fild{ll|}",
12439   "fbstp",
12440   "fistp{ll|}",
12441 };
12442
12443 static const unsigned char float_mem_mode[] = {
12444   /* d8 */
12445   d_mode,
12446   d_mode,
12447   d_mode,
12448   d_mode,
12449   d_mode,
12450   d_mode,
12451   d_mode,
12452   d_mode,
12453   /* d9 */
12454   d_mode,
12455   0,
12456   d_mode,
12457   d_mode,
12458   0,
12459   w_mode,
12460   0,
12461   w_mode,
12462   /* da */
12463   d_mode,
12464   d_mode,
12465   d_mode,
12466   d_mode,
12467   d_mode,
12468   d_mode,
12469   d_mode,
12470   d_mode,
12471   /* db */
12472   d_mode,
12473   d_mode,
12474   d_mode,
12475   d_mode,
12476   0,
12477   t_mode,
12478   0,
12479   t_mode,
12480   /* dc */
12481   q_mode,
12482   q_mode,
12483   q_mode,
12484   q_mode,
12485   q_mode,
12486   q_mode,
12487   q_mode,
12488   q_mode,
12489   /* dd */
12490   q_mode,
12491   q_mode,
12492   q_mode,
12493   q_mode,
12494   0,
12495   0,
12496   0,
12497   w_mode,
12498   /* de */
12499   w_mode,
12500   w_mode,
12501   w_mode,
12502   w_mode,
12503   w_mode,
12504   w_mode,
12505   w_mode,
12506   w_mode,
12507   /* df */
12508   w_mode,
12509   w_mode,
12510   w_mode,
12511   w_mode,
12512   t_mode,
12513   q_mode,
12514   t_mode,
12515   q_mode
12516 };
12517
12518 #define ST { OP_ST, 0 }
12519 #define STi { OP_STi, 0 }
12520
12521 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12522 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12523 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12524 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12525 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12526 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12527 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12528 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12529 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12530
12531 static const struct dis386 float_reg[][8] = {
12532   /* d8 */
12533   {
12534     { "fadd",   { ST, STi }, 0 },
12535     { "fmul",   { ST, STi }, 0 },
12536     { "fcom",   { STi }, 0 },
12537     { "fcomp",  { STi }, 0 },
12538     { "fsub",   { ST, STi }, 0 },
12539     { "fsubr",  { ST, STi }, 0 },
12540     { "fdiv",   { ST, STi }, 0 },
12541     { "fdivr",  { ST, STi }, 0 },
12542   },
12543   /* d9 */
12544   {
12545     { "fld",    { STi }, 0 },
12546     { "fxch",   { STi }, 0 },
12547     { FGRPd9_2 },
12548     { Bad_Opcode },
12549     { FGRPd9_4 },
12550     { FGRPd9_5 },
12551     { FGRPd9_6 },
12552     { FGRPd9_7 },
12553   },
12554   /* da */
12555   {
12556     { "fcmovb", { ST, STi }, 0 },
12557     { "fcmove", { ST, STi }, 0 },
12558     { "fcmovbe",{ ST, STi }, 0 },
12559     { "fcmovu", { ST, STi }, 0 },
12560     { Bad_Opcode },
12561     { FGRPda_5 },
12562     { Bad_Opcode },
12563     { Bad_Opcode },
12564   },
12565   /* db */
12566   {
12567     { "fcmovnb",{ ST, STi }, 0 },
12568     { "fcmovne",{ ST, STi }, 0 },
12569     { "fcmovnbe",{ ST, STi }, 0 },
12570     { "fcmovnu",{ ST, STi }, 0 },
12571     { FGRPdb_4 },
12572     { "fucomi", { ST, STi }, 0 },
12573     { "fcomi",  { ST, STi }, 0 },
12574     { Bad_Opcode },
12575   },
12576   /* dc */
12577   {
12578     { "fadd",   { STi, ST }, 0 },
12579     { "fmul",   { STi, ST }, 0 },
12580     { Bad_Opcode },
12581     { Bad_Opcode },
12582     { "fsub{!M|r}",     { STi, ST }, 0 },
12583     { "fsub{M|}",       { STi, ST }, 0 },
12584     { "fdiv{!M|r}",     { STi, ST }, 0 },
12585     { "fdiv{M|}",       { STi, ST }, 0 },
12586   },
12587   /* dd */
12588   {
12589     { "ffree",  { STi }, 0 },
12590     { Bad_Opcode },
12591     { "fst",    { STi }, 0 },
12592     { "fstp",   { STi }, 0 },
12593     { "fucom",  { STi }, 0 },
12594     { "fucomp", { STi }, 0 },
12595     { Bad_Opcode },
12596     { Bad_Opcode },
12597   },
12598   /* de */
12599   {
12600     { "faddp",  { STi, ST }, 0 },
12601     { "fmulp",  { STi, ST }, 0 },
12602     { Bad_Opcode },
12603     { FGRPde_3 },
12604     { "fsub{!M|r}p",    { STi, ST }, 0 },
12605     { "fsub{M|}p",      { STi, ST }, 0 },
12606     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12607     { "fdiv{M|}p",      { STi, ST }, 0 },
12608   },
12609   /* df */
12610   {
12611     { "ffreep", { STi }, 0 },
12612     { Bad_Opcode },
12613     { Bad_Opcode },
12614     { Bad_Opcode },
12615     { FGRPdf_4 },
12616     { "fucomip", { ST, STi }, 0 },
12617     { "fcomip", { ST, STi }, 0 },
12618     { Bad_Opcode },
12619   },
12620 };
12621
12622 static char *fgrps[][8] = {
12623   /* Bad opcode 0 */
12624   {
12625     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12626   },
12627
12628   /* d9_2  1 */
12629   {
12630     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12631   },
12632
12633   /* d9_4  2 */
12634   {
12635     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12636   },
12637
12638   /* d9_5  3 */
12639   {
12640     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12641   },
12642
12643   /* d9_6  4 */
12644   {
12645     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12646   },
12647
12648   /* d9_7  5 */
12649   {
12650     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12651   },
12652
12653   /* da_5  6 */
12654   {
12655     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12656   },
12657
12658   /* db_4  7 */
12659   {
12660     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12661     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12662   },
12663
12664   /* de_3  8 */
12665   {
12666     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12667   },
12668
12669   /* df_4  9 */
12670   {
12671     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12672   },
12673 };
12674
12675 static void
12676 swap_operand (void)
12677 {
12678   mnemonicendp[0] = '.';
12679   mnemonicendp[1] = 's';
12680   mnemonicendp += 2;
12681 }
12682
12683 static void
12684 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12685                int sizeflag ATTRIBUTE_UNUSED)
12686 {
12687   /* Skip mod/rm byte.  */
12688   MODRM_CHECK;
12689   codep++;
12690 }
12691
12692 static void
12693 dofloat (int sizeflag)
12694 {
12695   const struct dis386 *dp;
12696   unsigned char floatop;
12697
12698   floatop = codep[-1];
12699
12700   if (modrm.mod != 3)
12701     {
12702       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12703
12704       putop (float_mem[fp_indx], sizeflag);
12705       obufp = op_out[0];
12706       op_ad = 2;
12707       OP_E (float_mem_mode[fp_indx], sizeflag);
12708       return;
12709     }
12710   /* Skip mod/rm byte.  */
12711   MODRM_CHECK;
12712   codep++;
12713
12714   dp = &float_reg[floatop - 0xd8][modrm.reg];
12715   if (dp->name == NULL)
12716     {
12717       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12718
12719       /* Instruction fnstsw is only one with strange arg.  */
12720       if (floatop == 0xdf && codep[-1] == 0xe0)
12721         strcpy (op_out[0], names16[0]);
12722     }
12723   else
12724     {
12725       putop (dp->name, sizeflag);
12726
12727       obufp = op_out[0];
12728       op_ad = 2;
12729       if (dp->op[0].rtn)
12730         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12731
12732       obufp = op_out[1];
12733       op_ad = 1;
12734       if (dp->op[1].rtn)
12735         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12736     }
12737 }
12738
12739 /* Like oappend (below), but S is a string starting with '%'.
12740    In Intel syntax, the '%' is elided.  */
12741 static void
12742 oappend_maybe_intel (const char *s)
12743 {
12744   oappend (s + intel_syntax);
12745 }
12746
12747 static void
12748 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12749 {
12750   oappend_maybe_intel ("%st");
12751 }
12752
12753 static void
12754 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12755 {
12756   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12757   oappend_maybe_intel (scratchbuf);
12758 }
12759
12760 /* Capital letters in template are macros.  */
12761 static int
12762 putop (const char *in_template, int sizeflag)
12763 {
12764   const char *p;
12765   int alt = 0;
12766   int cond = 1;
12767   unsigned int l = 0, len = 1;
12768   char last[4];
12769
12770 #define SAVE_LAST(c)                    \
12771   if (l < len && l < sizeof (last))     \
12772     last[l++] = c;                      \
12773   else                                  \
12774     abort ();
12775
12776   for (p = in_template; *p; p++)
12777     {
12778       switch (*p)
12779         {
12780         default:
12781           *obufp++ = *p;
12782           break;
12783         case '%':
12784           len++;
12785           break;
12786         case '!':
12787           cond = 0;
12788           break;
12789         case '{':
12790           if (intel_syntax)
12791             {
12792               while (*++p != '|')
12793                 if (*p == '}' || *p == '\0')
12794                   abort ();
12795             }
12796           /* Fall through.  */
12797         case 'I':
12798           alt = 1;
12799           continue;
12800         case '|':
12801           while (*++p != '}')
12802             {
12803               if (*p == '\0')
12804                 abort ();
12805             }
12806           break;
12807         case '}':
12808           break;
12809         case 'A':
12810           if (intel_syntax)
12811             break;
12812           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12813             *obufp++ = 'b';
12814           break;
12815         case 'B':
12816           if (l == 0 && len == 1)
12817             {
12818             case_B:
12819               if (intel_syntax)
12820                 break;
12821               if (sizeflag & SUFFIX_ALWAYS)
12822                 *obufp++ = 'b';
12823             }
12824           else
12825             {
12826               if (l != 1
12827                   || len != 2
12828                   || last[0] != 'L')
12829                 {
12830                   SAVE_LAST (*p);
12831                   break;
12832                 }
12833
12834               if (address_mode == mode_64bit
12835                   && !(prefixes & PREFIX_ADDR))
12836                 {
12837                   *obufp++ = 'a';
12838                   *obufp++ = 'b';
12839                   *obufp++ = 's';
12840                 }
12841
12842               goto case_B;
12843             }
12844           break;
12845         case 'C':
12846           if (intel_syntax && !alt)
12847             break;
12848           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12849             {
12850               if (sizeflag & DFLAG)
12851                 *obufp++ = intel_syntax ? 'd' : 'l';
12852               else
12853                 *obufp++ = intel_syntax ? 'w' : 's';
12854               used_prefixes |= (prefixes & PREFIX_DATA);
12855             }
12856           break;
12857         case 'D':
12858           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12859             break;
12860           USED_REX (REX_W);
12861           if (modrm.mod == 3)
12862             {
12863               if (rex & REX_W)
12864                 *obufp++ = 'q';
12865               else
12866                 {
12867                   if (sizeflag & DFLAG)
12868                     *obufp++ = intel_syntax ? 'd' : 'l';
12869                   else
12870                     *obufp++ = 'w';
12871                   used_prefixes |= (prefixes & PREFIX_DATA);
12872                 }
12873             }
12874           else
12875             *obufp++ = 'w';
12876           break;
12877         case 'E':               /* For jcxz/jecxz */
12878           if (address_mode == mode_64bit)
12879             {
12880               if (sizeflag & AFLAG)
12881                 *obufp++ = 'r';
12882               else
12883                 *obufp++ = 'e';
12884             }
12885           else
12886             if (sizeflag & AFLAG)
12887               *obufp++ = 'e';
12888           used_prefixes |= (prefixes & PREFIX_ADDR);
12889           break;
12890         case 'F':
12891           if (intel_syntax)
12892             break;
12893           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12894             {
12895               if (sizeflag & AFLAG)
12896                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12897               else
12898                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12899               used_prefixes |= (prefixes & PREFIX_ADDR);
12900             }
12901           break;
12902         case 'G':
12903           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12904             break;
12905           if ((rex & REX_W) || (sizeflag & DFLAG))
12906             *obufp++ = 'l';
12907           else
12908             *obufp++ = 'w';
12909           if (!(rex & REX_W))
12910             used_prefixes |= (prefixes & PREFIX_DATA);
12911           break;
12912         case 'H':
12913           if (intel_syntax)
12914             break;
12915           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12916               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12917             {
12918               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12919               *obufp++ = ',';
12920               *obufp++ = 'p';
12921               if (prefixes & PREFIX_DS)
12922                 *obufp++ = 't';
12923               else
12924                 *obufp++ = 'n';
12925             }
12926           break;
12927         case 'J':
12928           if (intel_syntax)
12929             break;
12930           *obufp++ = 'l';
12931           break;
12932         case 'K':
12933           USED_REX (REX_W);
12934           if (rex & REX_W)
12935             *obufp++ = 'q';
12936           else
12937             *obufp++ = 'd';
12938           break;
12939         case 'Z':
12940           if (l != 0 || len != 1)
12941             {
12942               if (l != 1 || len != 2 || last[0] != 'X')
12943                 {
12944                   SAVE_LAST (*p);
12945                   break;
12946                 }
12947               if (!need_vex || !vex.evex)
12948                 abort ();
12949               if (intel_syntax
12950                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12951                 break;
12952               switch (vex.length)
12953                 {
12954                 case 128:
12955                   *obufp++ = 'x';
12956                   break;
12957                 case 256:
12958                   *obufp++ = 'y';
12959                   break;
12960                 case 512:
12961                   *obufp++ = 'z';
12962                   break;
12963                 default:
12964                   abort ();
12965                 }
12966               break;
12967             }
12968           if (intel_syntax)
12969             break;
12970           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12971             {
12972               *obufp++ = 'q';
12973               break;
12974             }
12975           /* Fall through.  */
12976           goto case_L;
12977         case 'L':
12978           if (l != 0 || len != 1)
12979             {
12980               SAVE_LAST (*p);
12981               break;
12982             }
12983         case_L:
12984           if (intel_syntax)
12985             break;
12986           if (sizeflag & SUFFIX_ALWAYS)
12987             *obufp++ = 'l';
12988           break;
12989         case 'M':
12990           if (intel_mnemonic != cond)
12991             *obufp++ = 'r';
12992           break;
12993         case 'N':
12994           if ((prefixes & PREFIX_FWAIT) == 0)
12995             *obufp++ = 'n';
12996           else
12997             used_prefixes |= PREFIX_FWAIT;
12998           break;
12999         case 'O':
13000           USED_REX (REX_W);
13001           if (rex & REX_W)
13002             *obufp++ = 'o';
13003           else if (intel_syntax && (sizeflag & DFLAG))
13004             *obufp++ = 'q';
13005           else
13006             *obufp++ = 'd';
13007           if (!(rex & REX_W))
13008             used_prefixes |= (prefixes & PREFIX_DATA);
13009           break;
13010         case '&':
13011           if (!intel_syntax
13012               && address_mode == mode_64bit
13013               && isa64 == intel64)
13014             {
13015               *obufp++ = 'q';
13016               break;
13017             }
13018           /* Fall through.  */
13019         case 'T':
13020           if (!intel_syntax
13021               && address_mode == mode_64bit
13022               && ((sizeflag & DFLAG) || (rex & REX_W)))
13023             {
13024               *obufp++ = 'q';
13025               break;
13026             }
13027           /* Fall through.  */
13028           goto case_P;
13029         case 'P':
13030           if (l == 0 && len == 1)
13031             {
13032             case_P:
13033               if (intel_syntax)
13034                 {
13035                   if ((rex & REX_W) == 0
13036                       && (prefixes & PREFIX_DATA))
13037                     {
13038                       if ((sizeflag & DFLAG) == 0)
13039                         *obufp++ = 'w';
13040                       used_prefixes |= (prefixes & PREFIX_DATA);
13041                     }
13042                   break;
13043                 }
13044               if ((prefixes & PREFIX_DATA)
13045                   || (rex & REX_W)
13046                   || (sizeflag & SUFFIX_ALWAYS))
13047                 {
13048                   USED_REX (REX_W);
13049                   if (rex & REX_W)
13050                     *obufp++ = 'q';
13051                   else
13052                     {
13053                       if (sizeflag & DFLAG)
13054                         *obufp++ = 'l';
13055                       else
13056                         *obufp++ = 'w';
13057                       used_prefixes |= (prefixes & PREFIX_DATA);
13058                     }
13059                 }
13060             }
13061           else
13062             {
13063               if (l != 1 || len != 2 || last[0] != 'L')
13064                 {
13065                   SAVE_LAST (*p);
13066                   break;
13067                 }
13068
13069               if ((prefixes & PREFIX_DATA)
13070                   || (rex & REX_W)
13071                   || (sizeflag & SUFFIX_ALWAYS))
13072                 {
13073                   USED_REX (REX_W);
13074                   if (rex & REX_W)
13075                     *obufp++ = 'q';
13076                   else
13077                     {
13078                       if (sizeflag & DFLAG)
13079                         *obufp++ = intel_syntax ? 'd' : 'l';
13080                       else
13081                         *obufp++ = 'w';
13082                       used_prefixes |= (prefixes & PREFIX_DATA);
13083                     }
13084                 }
13085             }
13086           break;
13087         case 'U':
13088           if (intel_syntax)
13089             break;
13090           if (address_mode == mode_64bit
13091               && ((sizeflag & DFLAG) || (rex & REX_W)))
13092             {
13093               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13094                 *obufp++ = 'q';
13095               break;
13096             }
13097           /* Fall through.  */
13098           goto case_Q;
13099         case 'Q':
13100           if (l == 0 && len == 1)
13101             {
13102             case_Q:
13103               if (intel_syntax && !alt)
13104                 break;
13105               USED_REX (REX_W);
13106               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13107                 {
13108                   if (rex & REX_W)
13109                     *obufp++ = 'q';
13110                   else
13111                     {
13112                       if (sizeflag & DFLAG)
13113                         *obufp++ = intel_syntax ? 'd' : 'l';
13114                       else
13115                         *obufp++ = 'w';
13116                       used_prefixes |= (prefixes & PREFIX_DATA);
13117                     }
13118                 }
13119             }
13120           else
13121             {
13122               if (l != 1 || len != 2 || last[0] != 'L')
13123                 {
13124                   SAVE_LAST (*p);
13125                   break;
13126                 }
13127               if (intel_syntax
13128                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13129                 break;
13130               if ((rex & REX_W))
13131                 {
13132                   USED_REX (REX_W);
13133                   *obufp++ = 'q';
13134                 }
13135               else
13136                 *obufp++ = 'l';
13137             }
13138           break;
13139         case 'R':
13140           USED_REX (REX_W);
13141           if (rex & REX_W)
13142             *obufp++ = 'q';
13143           else if (sizeflag & DFLAG)
13144             {
13145               if (intel_syntax)
13146                   *obufp++ = 'd';
13147               else
13148                   *obufp++ = 'l';
13149             }
13150           else
13151             *obufp++ = 'w';
13152           if (intel_syntax && !p[1]
13153               && ((rex & REX_W) || (sizeflag & DFLAG)))
13154             *obufp++ = 'e';
13155           if (!(rex & REX_W))
13156             used_prefixes |= (prefixes & PREFIX_DATA);
13157           break;
13158         case 'V':
13159           if (l == 0 && len == 1)
13160             {
13161               if (intel_syntax)
13162                 break;
13163               if (address_mode == mode_64bit
13164                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13165                 {
13166                   if (sizeflag & SUFFIX_ALWAYS)
13167                     *obufp++ = 'q';
13168                   break;
13169                 }
13170             }
13171           else
13172             {
13173               if (l != 1
13174                   || len != 2
13175                   || last[0] != 'L')
13176                 {
13177                   SAVE_LAST (*p);
13178                   break;
13179                 }
13180
13181               if (rex & REX_W)
13182                 {
13183                   *obufp++ = 'a';
13184                   *obufp++ = 'b';
13185                   *obufp++ = 's';
13186                 }
13187             }
13188           /* Fall through.  */
13189           goto case_S;
13190         case 'S':
13191           if (l == 0 && len == 1)
13192             {
13193             case_S:
13194               if (intel_syntax)
13195                 break;
13196               if (sizeflag & SUFFIX_ALWAYS)
13197                 {
13198                   if (rex & REX_W)
13199                     *obufp++ = 'q';
13200                   else
13201                     {
13202                       if (sizeflag & DFLAG)
13203                         *obufp++ = 'l';
13204                       else
13205                         *obufp++ = 'w';
13206                       used_prefixes |= (prefixes & PREFIX_DATA);
13207                     }
13208                 }
13209             }
13210           else
13211             {
13212               if (l != 1
13213                   || len != 2
13214                   || last[0] != 'L')
13215                 {
13216                   SAVE_LAST (*p);
13217                   break;
13218                 }
13219
13220               if (address_mode == mode_64bit
13221                   && !(prefixes & PREFIX_ADDR))
13222                 {
13223                   *obufp++ = 'a';
13224                   *obufp++ = 'b';
13225                   *obufp++ = 's';
13226                 }
13227
13228               goto case_S;
13229             }
13230           break;
13231         case 'X':
13232           if (l != 0 || len != 1)
13233             {
13234               SAVE_LAST (*p);
13235               break;
13236             }
13237           if (need_vex
13238               ? vex.prefix == DATA_PREFIX_OPCODE
13239               : prefixes & PREFIX_DATA)
13240             {
13241               *obufp++ = 'd';
13242               used_prefixes |= PREFIX_DATA;
13243             }
13244           else
13245             *obufp++ = 's';
13246           break;
13247         case 'Y':
13248           if (l == 0 && len == 1)
13249             abort ();
13250           else
13251             {
13252               if (l != 1 || len != 2 || last[0] != 'X')
13253                 {
13254                   SAVE_LAST (*p);
13255                   break;
13256                 }
13257               if (!need_vex)
13258                 abort ();
13259               if (intel_syntax
13260                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13261                 break;
13262               switch (vex.length)
13263                 {
13264                 case 128:
13265                   *obufp++ = 'x';
13266                   break;
13267                 case 256:
13268                   *obufp++ = 'y';
13269                   break;
13270                 case 512:
13271                   if (!vex.evex)
13272                 default:
13273                     abort ();
13274                 }
13275             }
13276           break;
13277         case 'W':
13278           if (l == 0 && len == 1)
13279             {
13280               /* operand size flag for cwtl, cbtw */
13281               USED_REX (REX_W);
13282               if (rex & REX_W)
13283                 {
13284                   if (intel_syntax)
13285                     *obufp++ = 'd';
13286                   else
13287                     *obufp++ = 'l';
13288                 }
13289               else if (sizeflag & DFLAG)
13290                 *obufp++ = 'w';
13291               else
13292                 *obufp++ = 'b';
13293               if (!(rex & REX_W))
13294                 used_prefixes |= (prefixes & PREFIX_DATA);
13295             }
13296           else
13297             {
13298               if (l != 1
13299                   || len != 2
13300                   || (last[0] != 'X'
13301                       && last[0] != 'L'))
13302                 {
13303                   SAVE_LAST (*p);
13304                   break;
13305                 }
13306               if (!need_vex)
13307                 abort ();
13308               if (last[0] == 'X')
13309                 *obufp++ = vex.w ? 'd': 's';
13310               else
13311                 *obufp++ = vex.w ? 'q': 'd';
13312             }
13313           break;
13314         case '^':
13315           if (intel_syntax)
13316             break;
13317           if (isa64 == intel64 && (rex & REX_W))
13318             {
13319               USED_REX (REX_W);
13320               *obufp++ = 'q';
13321               break;
13322             }
13323           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13324             {
13325               if (sizeflag & DFLAG)
13326                 *obufp++ = 'l';
13327               else
13328                 *obufp++ = 'w';
13329               used_prefixes |= (prefixes & PREFIX_DATA);
13330             }
13331           break;
13332         case '@':
13333           if (intel_syntax)
13334             break;
13335           if (address_mode == mode_64bit
13336               && (isa64 == intel64
13337                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13338               *obufp++ = 'q';
13339           else if ((prefixes & PREFIX_DATA))
13340             {
13341               if (!(sizeflag & DFLAG))
13342                 *obufp++ = 'w';
13343               used_prefixes |= (prefixes & PREFIX_DATA);
13344             }
13345           break;
13346         }
13347       alt = 0;
13348     }
13349   *obufp = 0;
13350   mnemonicendp = obufp;
13351   return 0;
13352 }
13353
13354 static void
13355 oappend (const char *s)
13356 {
13357   obufp = stpcpy (obufp, s);
13358 }
13359
13360 static void
13361 append_seg (void)
13362 {
13363   /* Only print the active segment register.  */
13364   if (!active_seg_prefix)
13365     return;
13366
13367   used_prefixes |= active_seg_prefix;
13368   switch (active_seg_prefix)
13369     {
13370     case PREFIX_CS:
13371       oappend_maybe_intel ("%cs:");
13372       break;
13373     case PREFIX_DS:
13374       oappend_maybe_intel ("%ds:");
13375       break;
13376     case PREFIX_SS:
13377       oappend_maybe_intel ("%ss:");
13378       break;
13379     case PREFIX_ES:
13380       oappend_maybe_intel ("%es:");
13381       break;
13382     case PREFIX_FS:
13383       oappend_maybe_intel ("%fs:");
13384       break;
13385     case PREFIX_GS:
13386       oappend_maybe_intel ("%gs:");
13387       break;
13388     default:
13389       break;
13390     }
13391 }
13392
13393 static void
13394 OP_indirE (int bytemode, int sizeflag)
13395 {
13396   if (!intel_syntax)
13397     oappend ("*");
13398   OP_E (bytemode, sizeflag);
13399 }
13400
13401 static void
13402 print_operand_value (char *buf, int hex, bfd_vma disp)
13403 {
13404   if (address_mode == mode_64bit)
13405     {
13406       if (hex)
13407         {
13408           char tmp[30];
13409           int i;
13410           buf[0] = '0';
13411           buf[1] = 'x';
13412           sprintf_vma (tmp, disp);
13413           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13414           strcpy (buf + 2, tmp + i);
13415         }
13416       else
13417         {
13418           bfd_signed_vma v = disp;
13419           char tmp[30];
13420           int i;
13421           if (v < 0)
13422             {
13423               *(buf++) = '-';
13424               v = -disp;
13425               /* Check for possible overflow on 0x8000000000000000.  */
13426               if (v < 0)
13427                 {
13428                   strcpy (buf, "9223372036854775808");
13429                   return;
13430                 }
13431             }
13432           if (!v)
13433             {
13434               strcpy (buf, "0");
13435               return;
13436             }
13437
13438           i = 0;
13439           tmp[29] = 0;
13440           while (v)
13441             {
13442               tmp[28 - i] = (v % 10) + '0';
13443               v /= 10;
13444               i++;
13445             }
13446           strcpy (buf, tmp + 29 - i);
13447         }
13448     }
13449   else
13450     {
13451       if (hex)
13452         sprintf (buf, "0x%x", (unsigned int) disp);
13453       else
13454         sprintf (buf, "%d", (int) disp);
13455     }
13456 }
13457
13458 /* Put DISP in BUF as signed hex number.  */
13459
13460 static void
13461 print_displacement (char *buf, bfd_vma disp)
13462 {
13463   bfd_signed_vma val = disp;
13464   char tmp[30];
13465   int i, j = 0;
13466
13467   if (val < 0)
13468     {
13469       buf[j++] = '-';
13470       val = -disp;
13471
13472       /* Check for possible overflow.  */
13473       if (val < 0)
13474         {
13475           switch (address_mode)
13476             {
13477             case mode_64bit:
13478               strcpy (buf + j, "0x8000000000000000");
13479               break;
13480             case mode_32bit:
13481               strcpy (buf + j, "0x80000000");
13482               break;
13483             case mode_16bit:
13484               strcpy (buf + j, "0x8000");
13485               break;
13486             }
13487           return;
13488         }
13489     }
13490
13491   buf[j++] = '0';
13492   buf[j++] = 'x';
13493
13494   sprintf_vma (tmp, (bfd_vma) val);
13495   for (i = 0; tmp[i] == '0'; i++)
13496     continue;
13497   if (tmp[i] == '\0')
13498     i--;
13499   strcpy (buf + j, tmp + i);
13500 }
13501
13502 static void
13503 intel_operand_size (int bytemode, int sizeflag)
13504 {
13505   if (vex.evex
13506       && vex.b
13507       && (bytemode == x_mode
13508           || bytemode == evex_half_bcst_xmmq_mode))
13509     {
13510       if (vex.w)
13511         oappend ("QWORD PTR ");
13512       else
13513         oappend ("DWORD PTR ");
13514       return;
13515     }
13516   switch (bytemode)
13517     {
13518     case b_mode:
13519     case b_swap_mode:
13520     case dqb_mode:
13521     case db_mode:
13522       oappend ("BYTE PTR ");
13523       break;
13524     case w_mode:
13525     case dw_mode:
13526     case dqw_mode:
13527       oappend ("WORD PTR ");
13528       break;
13529     case indir_v_mode:
13530       if (address_mode == mode_64bit && isa64 == intel64)
13531         {
13532           oappend ("QWORD PTR ");
13533           break;
13534         }
13535       /* Fall through.  */
13536     case stack_v_mode:
13537       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13538         {
13539           oappend ("QWORD PTR ");
13540           break;
13541         }
13542       /* Fall through.  */
13543     case v_mode:
13544     case v_swap_mode:
13545     case dq_mode:
13546       USED_REX (REX_W);
13547       if (rex & REX_W)
13548         oappend ("QWORD PTR ");
13549       else
13550         {
13551           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13552             oappend ("DWORD PTR ");
13553           else
13554             oappend ("WORD PTR ");
13555           used_prefixes |= (prefixes & PREFIX_DATA);
13556         }
13557       break;
13558     case z_mode:
13559       if ((rex & REX_W) || (sizeflag & DFLAG))
13560         *obufp++ = 'D';
13561       oappend ("WORD PTR ");
13562       if (!(rex & REX_W))
13563         used_prefixes |= (prefixes & PREFIX_DATA);
13564       break;
13565     case a_mode:
13566       if (sizeflag & DFLAG)
13567         oappend ("QWORD PTR ");
13568       else
13569         oappend ("DWORD PTR ");
13570       used_prefixes |= (prefixes & PREFIX_DATA);
13571       break;
13572     case movsxd_mode:
13573       if (!(sizeflag & DFLAG) && isa64 == intel64)
13574         oappend ("WORD PTR ");
13575       else
13576         oappend ("DWORD PTR ");
13577       used_prefixes |= (prefixes & PREFIX_DATA);
13578       break;
13579     case d_mode:
13580     case d_scalar_mode:
13581     case d_scalar_swap_mode:
13582     case d_swap_mode:
13583     case dqd_mode:
13584       oappend ("DWORD PTR ");
13585       break;
13586     case q_mode:
13587     case q_scalar_mode:
13588     case q_scalar_swap_mode:
13589     case q_swap_mode:
13590       oappend ("QWORD PTR ");
13591       break;
13592     case m_mode:
13593       if (address_mode == mode_64bit)
13594         oappend ("QWORD PTR ");
13595       else
13596         oappend ("DWORD PTR ");
13597       break;
13598     case f_mode:
13599       if (sizeflag & DFLAG)
13600         oappend ("FWORD PTR ");
13601       else
13602         oappend ("DWORD PTR ");
13603       used_prefixes |= (prefixes & PREFIX_DATA);
13604       break;
13605     case t_mode:
13606       oappend ("TBYTE PTR ");
13607       break;
13608     case x_mode:
13609     case x_swap_mode:
13610     case evex_x_gscat_mode:
13611     case evex_x_nobcst_mode:
13612     case b_scalar_mode:
13613     case w_scalar_mode:
13614       if (need_vex)
13615         {
13616           switch (vex.length)
13617             {
13618             case 128:
13619               oappend ("XMMWORD PTR ");
13620               break;
13621             case 256:
13622               oappend ("YMMWORD PTR ");
13623               break;
13624             case 512:
13625               oappend ("ZMMWORD PTR ");
13626               break;
13627             default:
13628               abort ();
13629             }
13630         }
13631       else
13632         oappend ("XMMWORD PTR ");
13633       break;
13634     case xmm_mode:
13635       oappend ("XMMWORD PTR ");
13636       break;
13637     case ymm_mode:
13638       oappend ("YMMWORD PTR ");
13639       break;
13640     case xmmq_mode:
13641     case evex_half_bcst_xmmq_mode:
13642       if (!need_vex)
13643         abort ();
13644
13645       switch (vex.length)
13646         {
13647         case 128:
13648           oappend ("QWORD PTR ");
13649           break;
13650         case 256:
13651           oappend ("XMMWORD PTR ");
13652           break;
13653         case 512:
13654           oappend ("YMMWORD PTR ");
13655           break;
13656         default:
13657           abort ();
13658         }
13659       break;
13660     case xmm_mb_mode:
13661       if (!need_vex)
13662         abort ();
13663
13664       switch (vex.length)
13665         {
13666         case 128:
13667         case 256:
13668         case 512:
13669           oappend ("BYTE PTR ");
13670           break;
13671         default:
13672           abort ();
13673         }
13674       break;
13675     case xmm_mw_mode:
13676       if (!need_vex)
13677         abort ();
13678
13679       switch (vex.length)
13680         {
13681         case 128:
13682         case 256:
13683         case 512:
13684           oappend ("WORD PTR ");
13685           break;
13686         default:
13687           abort ();
13688         }
13689       break;
13690     case xmm_md_mode:
13691       if (!need_vex)
13692         abort ();
13693
13694       switch (vex.length)
13695         {
13696         case 128:
13697         case 256:
13698         case 512:
13699           oappend ("DWORD PTR ");
13700           break;
13701         default:
13702           abort ();
13703         }
13704       break;
13705     case xmm_mq_mode:
13706       if (!need_vex)
13707         abort ();
13708
13709       switch (vex.length)
13710         {
13711         case 128:
13712         case 256:
13713         case 512:
13714           oappend ("QWORD PTR ");
13715           break;
13716         default:
13717           abort ();
13718         }
13719       break;
13720     case xmmdw_mode:
13721       if (!need_vex)
13722         abort ();
13723
13724       switch (vex.length)
13725         {
13726         case 128:
13727           oappend ("WORD PTR ");
13728           break;
13729         case 256:
13730           oappend ("DWORD PTR ");
13731           break;
13732         case 512:
13733           oappend ("QWORD PTR ");
13734           break;
13735         default:
13736           abort ();
13737         }
13738       break;
13739     case xmmqd_mode:
13740       if (!need_vex)
13741         abort ();
13742
13743       switch (vex.length)
13744         {
13745         case 128:
13746           oappend ("DWORD PTR ");
13747           break;
13748         case 256:
13749           oappend ("QWORD PTR ");
13750           break;
13751         case 512:
13752           oappend ("XMMWORD PTR ");
13753           break;
13754         default:
13755           abort ();
13756         }
13757       break;
13758     case ymmq_mode:
13759       if (!need_vex)
13760         abort ();
13761
13762       switch (vex.length)
13763         {
13764         case 128:
13765           oappend ("QWORD PTR ");
13766           break;
13767         case 256:
13768           oappend ("YMMWORD PTR ");
13769           break;
13770         case 512:
13771           oappend ("ZMMWORD PTR ");
13772           break;
13773         default:
13774           abort ();
13775         }
13776       break;
13777     case ymmxmm_mode:
13778       if (!need_vex)
13779         abort ();
13780
13781       switch (vex.length)
13782         {
13783         case 128:
13784         case 256:
13785           oappend ("XMMWORD PTR ");
13786           break;
13787         default:
13788           abort ();
13789         }
13790       break;
13791     case o_mode:
13792       oappend ("OWORD PTR ");
13793       break;
13794     case vex_scalar_w_dq_mode:
13795       if (!need_vex)
13796         abort ();
13797
13798       if (vex.w)
13799         oappend ("QWORD PTR ");
13800       else
13801         oappend ("DWORD PTR ");
13802       break;
13803     case vex_vsib_d_w_dq_mode:
13804     case vex_vsib_q_w_dq_mode:
13805       if (!need_vex)
13806         abort ();
13807
13808       if (!vex.evex)
13809         {
13810           if (vex.w)
13811             oappend ("QWORD PTR ");
13812           else
13813             oappend ("DWORD PTR ");
13814         }
13815       else
13816         {
13817           switch (vex.length)
13818             {
13819             case 128:
13820               oappend ("XMMWORD PTR ");
13821               break;
13822             case 256:
13823               oappend ("YMMWORD PTR ");
13824               break;
13825             case 512:
13826               oappend ("ZMMWORD PTR ");
13827               break;
13828             default:
13829               abort ();
13830             }
13831         }
13832       break;
13833     case vex_vsib_q_w_d_mode:
13834     case vex_vsib_d_w_d_mode:
13835       if (!need_vex || !vex.evex)
13836         abort ();
13837
13838       switch (vex.length)
13839         {
13840         case 128:
13841           oappend ("QWORD PTR ");
13842           break;
13843         case 256:
13844           oappend ("XMMWORD PTR ");
13845           break;
13846         case 512:
13847           oappend ("YMMWORD PTR ");
13848           break;
13849         default:
13850           abort ();
13851         }
13852
13853       break;
13854     case mask_bd_mode:
13855       if (!need_vex || vex.length != 128)
13856         abort ();
13857       if (vex.w)
13858         oappend ("DWORD PTR ");
13859       else
13860         oappend ("BYTE PTR ");
13861       break;
13862     case mask_mode:
13863       if (!need_vex)
13864         abort ();
13865       if (vex.w)
13866         oappend ("QWORD PTR ");
13867       else
13868         oappend ("WORD PTR ");
13869       break;
13870     case v_bnd_mode:
13871     case v_bndmk_mode:
13872     default:
13873       break;
13874     }
13875 }
13876
13877 static void
13878 OP_E_register (int bytemode, int sizeflag)
13879 {
13880   int reg = modrm.rm;
13881   const char **names;
13882
13883   USED_REX (REX_B);
13884   if ((rex & REX_B))
13885     reg += 8;
13886
13887   if ((sizeflag & SUFFIX_ALWAYS)
13888       && (bytemode == b_swap_mode
13889           || bytemode == bnd_swap_mode
13890           || bytemode == v_swap_mode))
13891     swap_operand ();
13892
13893   switch (bytemode)
13894     {
13895     case b_mode:
13896     case b_swap_mode:
13897       USED_REX (0);
13898       if (rex)
13899         names = names8rex;
13900       else
13901         names = names8;
13902       break;
13903     case w_mode:
13904       names = names16;
13905       break;
13906     case d_mode:
13907     case dw_mode:
13908     case db_mode:
13909       names = names32;
13910       break;
13911     case q_mode:
13912       names = names64;
13913       break;
13914     case m_mode:
13915     case v_bnd_mode:
13916       names = address_mode == mode_64bit ? names64 : names32;
13917       break;
13918     case bnd_mode:
13919     case bnd_swap_mode:
13920       if (reg > 0x3)
13921         {
13922           oappend ("(bad)");
13923           return;
13924         }
13925       names = names_bnd;
13926       break;
13927     case indir_v_mode:
13928       if (address_mode == mode_64bit && isa64 == intel64)
13929         {
13930           names = names64;
13931           break;
13932         }
13933       /* Fall through.  */
13934     case stack_v_mode:
13935       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13936         {
13937           names = names64;
13938           break;
13939         }
13940       bytemode = v_mode;
13941       /* Fall through.  */
13942     case v_mode:
13943     case v_swap_mode:
13944     case dq_mode:
13945     case dqb_mode:
13946     case dqd_mode:
13947     case dqw_mode:
13948       USED_REX (REX_W);
13949       if (rex & REX_W)
13950         names = names64;
13951       else
13952         {
13953           if ((sizeflag & DFLAG)
13954               || (bytemode != v_mode
13955                   && bytemode != v_swap_mode))
13956             names = names32;
13957           else
13958             names = names16;
13959           used_prefixes |= (prefixes & PREFIX_DATA);
13960         }
13961       break;
13962     case movsxd_mode:
13963       if (!(sizeflag & DFLAG) && isa64 == intel64)
13964         names = names16;
13965       else
13966         names = names32;
13967       used_prefixes |= (prefixes & PREFIX_DATA);
13968       break;
13969     case va_mode:
13970       names = (address_mode == mode_64bit
13971                ? names64 : names32);
13972       if (!(prefixes & PREFIX_ADDR))
13973         names = (address_mode == mode_16bit
13974                      ? names16 : names);
13975       else
13976         {
13977           /* Remove "addr16/addr32".  */
13978           all_prefixes[last_addr_prefix] = 0;
13979           names = (address_mode != mode_32bit
13980                        ? names32 : names16);
13981           used_prefixes |= PREFIX_ADDR;
13982         }
13983       break;
13984     case mask_bd_mode:
13985     case mask_mode:
13986       if (reg > 0x7)
13987         {
13988           oappend ("(bad)");
13989           return;
13990         }
13991       names = names_mask;
13992       break;
13993     case 0:
13994       return;
13995     default:
13996       oappend (INTERNAL_DISASSEMBLER_ERROR);
13997       return;
13998     }
13999   oappend (names[reg]);
14000 }
14001
14002 static void
14003 OP_E_memory (int bytemode, int sizeflag)
14004 {
14005   bfd_vma disp = 0;
14006   int add = (rex & REX_B) ? 8 : 0;
14007   int riprel = 0;
14008   int shift;
14009
14010   if (vex.evex)
14011     {
14012       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
14013       if (vex.b
14014           && bytemode != x_mode
14015           && bytemode != xmmq_mode
14016           && bytemode != evex_half_bcst_xmmq_mode)
14017         {
14018           BadOp ();
14019           return;
14020         }
14021       switch (bytemode)
14022         {
14023         case dqw_mode:
14024         case dw_mode:
14025           shift = 1;
14026           break;
14027         case dqb_mode:
14028         case db_mode:
14029           shift = 0;
14030           break;
14031         case dq_mode:
14032           if (address_mode != mode_64bit)
14033             {
14034               shift = 2;
14035               break;
14036             }
14037             /* fall through */
14038         case vex_scalar_w_dq_mode:
14039         case vex_vsib_d_w_dq_mode:
14040         case vex_vsib_d_w_d_mode:
14041         case vex_vsib_q_w_dq_mode:
14042         case vex_vsib_q_w_d_mode:
14043         case evex_x_gscat_mode:
14044           shift = vex.w ? 3 : 2;
14045           break;
14046         case x_mode:
14047         case evex_half_bcst_xmmq_mode:
14048         case xmmq_mode:
14049           if (vex.b)
14050             {
14051               shift = vex.w ? 3 : 2;
14052               break;
14053             }
14054           /* Fall through.  */
14055         case xmmqd_mode:
14056         case xmmdw_mode:
14057         case ymmq_mode:
14058         case evex_x_nobcst_mode:
14059         case x_swap_mode:
14060           switch (vex.length)
14061             {
14062             case 128:
14063               shift = 4;
14064               break;
14065             case 256:
14066               shift = 5;
14067               break;
14068             case 512:
14069               shift = 6;
14070               break;
14071             default:
14072               abort ();
14073             }
14074           break;
14075         case ymm_mode:
14076           shift = 5;
14077           break;
14078         case xmm_mode:
14079           shift = 4;
14080           break;
14081         case xmm_mq_mode:
14082         case q_mode:
14083         case q_scalar_mode:
14084         case q_swap_mode:
14085         case q_scalar_swap_mode:
14086           shift = 3;
14087           break;
14088         case dqd_mode:
14089         case xmm_md_mode:
14090         case d_mode:
14091         case d_scalar_mode:
14092         case d_swap_mode:
14093         case d_scalar_swap_mode:
14094           shift = 2;
14095           break;
14096         case w_scalar_mode:
14097         case xmm_mw_mode:
14098           shift = 1;
14099           break;
14100         case b_scalar_mode:
14101         case xmm_mb_mode:
14102           shift = 0;
14103           break;
14104         default:
14105           abort ();
14106         }
14107       /* Make necessary corrections to shift for modes that need it.
14108          For these modes we currently have shift 4, 5 or 6 depending on
14109          vex.length (it corresponds to xmmword, ymmword or zmmword
14110          operand).  We might want to make it 3, 4 or 5 (e.g. for
14111          xmmq_mode).  In case of broadcast enabled the corrections
14112          aren't needed, as element size is always 32 or 64 bits.  */
14113       if (!vex.b
14114           && (bytemode == xmmq_mode
14115               || bytemode == evex_half_bcst_xmmq_mode))
14116         shift -= 1;
14117       else if (bytemode == xmmqd_mode)
14118         shift -= 2;
14119       else if (bytemode == xmmdw_mode)
14120         shift -= 3;
14121       else if (bytemode == ymmq_mode && vex.length == 128)
14122         shift -= 1;
14123     }
14124   else
14125     shift = 0;
14126
14127   USED_REX (REX_B);
14128   if (intel_syntax)
14129     intel_operand_size (bytemode, sizeflag);
14130   append_seg ();
14131
14132   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14133     {
14134       /* 32/64 bit address mode */
14135       int havedisp;
14136       int havesib;
14137       int havebase;
14138       int haveindex;
14139       int needindex;
14140       int needaddr32;
14141       int base, rbase;
14142       int vindex = 0;
14143       int scale = 0;
14144       int addr32flag = !((sizeflag & AFLAG)
14145                          || bytemode == v_bnd_mode
14146                          || bytemode == v_bndmk_mode
14147                          || bytemode == bnd_mode
14148                          || bytemode == bnd_swap_mode);
14149       const char **indexes64 = names64;
14150       const char **indexes32 = names32;
14151
14152       havesib = 0;
14153       havebase = 1;
14154       haveindex = 0;
14155       base = modrm.rm;
14156
14157       if (base == 4)
14158         {
14159           havesib = 1;
14160           vindex = sib.index;
14161           USED_REX (REX_X);
14162           if (rex & REX_X)
14163             vindex += 8;
14164           switch (bytemode)
14165             {
14166             case vex_vsib_d_w_dq_mode:
14167             case vex_vsib_d_w_d_mode:
14168             case vex_vsib_q_w_dq_mode:
14169             case vex_vsib_q_w_d_mode:
14170               if (!need_vex)
14171                 abort ();
14172               if (vex.evex)
14173                 {
14174                   if (!vex.v)
14175                     vindex += 16;
14176                 }
14177
14178               haveindex = 1;
14179               switch (vex.length)
14180                 {
14181                 case 128:
14182                   indexes64 = indexes32 = names_xmm;
14183                   break;
14184                 case 256:
14185                   if (!vex.w
14186                       || bytemode == vex_vsib_q_w_dq_mode
14187                       || bytemode == vex_vsib_q_w_d_mode)
14188                     indexes64 = indexes32 = names_ymm;
14189                   else
14190                     indexes64 = indexes32 = names_xmm;
14191                   break;
14192                 case 512:
14193                   if (!vex.w
14194                       || bytemode == vex_vsib_q_w_dq_mode
14195                       || bytemode == vex_vsib_q_w_d_mode)
14196                     indexes64 = indexes32 = names_zmm;
14197                   else
14198                     indexes64 = indexes32 = names_ymm;
14199                   break;
14200                 default:
14201                   abort ();
14202                 }
14203               break;
14204             default:
14205               haveindex = vindex != 4;
14206               break;
14207             }
14208           scale = sib.scale;
14209           base = sib.base;
14210           codep++;
14211         }
14212       rbase = base + add;
14213
14214       switch (modrm.mod)
14215         {
14216         case 0:
14217           if (base == 5)
14218             {
14219               havebase = 0;
14220               if (address_mode == mode_64bit && !havesib)
14221                 riprel = 1;
14222               disp = get32s ();
14223               if (riprel && bytemode == v_bndmk_mode)
14224                 {
14225                   oappend ("(bad)");
14226                   return;
14227                 }
14228             }
14229           break;
14230         case 1:
14231           FETCH_DATA (the_info, codep + 1);
14232           disp = *codep++;
14233           if ((disp & 0x80) != 0)
14234             disp -= 0x100;
14235           if (vex.evex && shift > 0)
14236             disp <<= shift;
14237           break;
14238         case 2:
14239           disp = get32s ();
14240           break;
14241         }
14242
14243       needindex = 0;
14244       needaddr32 = 0;
14245       if (havesib
14246           && !havebase
14247           && !haveindex
14248           && address_mode != mode_16bit)
14249         {
14250           if (address_mode == mode_64bit)
14251             {
14252               /* Display eiz instead of addr32.  */
14253               needindex = addr32flag;
14254               needaddr32 = 1;
14255             }
14256           else
14257             {
14258               /* In 32-bit mode, we need index register to tell [offset]
14259                  from [eiz*1 + offset].  */
14260               needindex = 1;
14261             }
14262         }
14263
14264       havedisp = (havebase
14265                   || needindex
14266                   || (havesib && (haveindex || scale != 0)));
14267
14268       if (!intel_syntax)
14269         if (modrm.mod != 0 || base == 5)
14270           {
14271             if (havedisp || riprel)
14272               print_displacement (scratchbuf, disp);
14273             else
14274               print_operand_value (scratchbuf, 1, disp);
14275             oappend (scratchbuf);
14276             if (riprel)
14277               {
14278                 set_op (disp, 1);
14279                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14280               }
14281           }
14282
14283       if ((havebase || haveindex || needindex || needaddr32 || riprel)
14284           && (address_mode != mode_64bit
14285               || ((bytemode != v_bnd_mode)
14286                   && (bytemode != v_bndmk_mode)
14287                   && (bytemode != bnd_mode)
14288                   && (bytemode != bnd_swap_mode))))
14289         used_prefixes |= PREFIX_ADDR;
14290
14291       if (havedisp || (intel_syntax && riprel))
14292         {
14293           *obufp++ = open_char;
14294           if (intel_syntax && riprel)
14295             {
14296               set_op (disp, 1);
14297               oappend (!addr32flag ? "rip" : "eip");
14298             }
14299           *obufp = '\0';
14300           if (havebase)
14301             oappend (address_mode == mode_64bit && !addr32flag
14302                      ? names64[rbase] : names32[rbase]);
14303           if (havesib)
14304             {
14305               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14306                  print index to tell base + index from base.  */
14307               if (scale != 0
14308                   || needindex
14309                   || haveindex
14310                   || (havebase && base != ESP_REG_NUM))
14311                 {
14312                   if (!intel_syntax || havebase)
14313                     {
14314                       *obufp++ = separator_char;
14315                       *obufp = '\0';
14316                     }
14317                   if (haveindex)
14318                     oappend (address_mode == mode_64bit && !addr32flag
14319                              ? indexes64[vindex] : indexes32[vindex]);
14320                   else
14321                     oappend (address_mode == mode_64bit && !addr32flag
14322                              ? index64 : index32);
14323
14324                   *obufp++ = scale_char;
14325                   *obufp = '\0';
14326                   sprintf (scratchbuf, "%d", 1 << scale);
14327                   oappend (scratchbuf);
14328                 }
14329             }
14330           if (intel_syntax
14331               && (disp || modrm.mod != 0 || base == 5))
14332             {
14333               if (!havedisp || (bfd_signed_vma) disp >= 0)
14334                 {
14335                   *obufp++ = '+';
14336                   *obufp = '\0';
14337                 }
14338               else if (modrm.mod != 1 && disp != -disp)
14339                 {
14340                   *obufp++ = '-';
14341                   *obufp = '\0';
14342                   disp = - (bfd_signed_vma) disp;
14343                 }
14344
14345               if (havedisp)
14346                 print_displacement (scratchbuf, disp);
14347               else
14348                 print_operand_value (scratchbuf, 1, disp);
14349               oappend (scratchbuf);
14350             }
14351
14352           *obufp++ = close_char;
14353           *obufp = '\0';
14354         }
14355       else if (intel_syntax)
14356         {
14357           if (modrm.mod != 0 || base == 5)
14358             {
14359               if (!active_seg_prefix)
14360                 {
14361                   oappend (names_seg[ds_reg - es_reg]);
14362                   oappend (":");
14363                 }
14364               print_operand_value (scratchbuf, 1, disp);
14365               oappend (scratchbuf);
14366             }
14367         }
14368     }
14369   else if (bytemode == v_bnd_mode
14370            || bytemode == v_bndmk_mode
14371            || bytemode == bnd_mode
14372            || bytemode == bnd_swap_mode)
14373     {
14374       oappend ("(bad)");
14375       return;
14376     }
14377   else
14378     {
14379       /* 16 bit address mode */
14380       used_prefixes |= prefixes & PREFIX_ADDR;
14381       switch (modrm.mod)
14382         {
14383         case 0:
14384           if (modrm.rm == 6)
14385             {
14386               disp = get16 ();
14387               if ((disp & 0x8000) != 0)
14388                 disp -= 0x10000;
14389             }
14390           break;
14391         case 1:
14392           FETCH_DATA (the_info, codep + 1);
14393           disp = *codep++;
14394           if ((disp & 0x80) != 0)
14395             disp -= 0x100;
14396           if (vex.evex && shift > 0)
14397             disp <<= shift;
14398           break;
14399         case 2:
14400           disp = get16 ();
14401           if ((disp & 0x8000) != 0)
14402             disp -= 0x10000;
14403           break;
14404         }
14405
14406       if (!intel_syntax)
14407         if (modrm.mod != 0 || modrm.rm == 6)
14408           {
14409             print_displacement (scratchbuf, disp);
14410             oappend (scratchbuf);
14411           }
14412
14413       if (modrm.mod != 0 || modrm.rm != 6)
14414         {
14415           *obufp++ = open_char;
14416           *obufp = '\0';
14417           oappend (index16[modrm.rm]);
14418           if (intel_syntax
14419               && (disp || modrm.mod != 0 || modrm.rm == 6))
14420             {
14421               if ((bfd_signed_vma) disp >= 0)
14422                 {
14423                   *obufp++ = '+';
14424                   *obufp = '\0';
14425                 }
14426               else if (modrm.mod != 1)
14427                 {
14428                   *obufp++ = '-';
14429                   *obufp = '\0';
14430                   disp = - (bfd_signed_vma) disp;
14431                 }
14432
14433               print_displacement (scratchbuf, disp);
14434               oappend (scratchbuf);
14435             }
14436
14437           *obufp++ = close_char;
14438           *obufp = '\0';
14439         }
14440       else if (intel_syntax)
14441         {
14442           if (!active_seg_prefix)
14443             {
14444               oappend (names_seg[ds_reg - es_reg]);
14445               oappend (":");
14446             }
14447           print_operand_value (scratchbuf, 1, disp & 0xffff);
14448           oappend (scratchbuf);
14449         }
14450     }
14451   if (vex.evex && vex.b
14452       && (bytemode == x_mode
14453           || bytemode == xmmq_mode
14454           || bytemode == evex_half_bcst_xmmq_mode))
14455     {
14456       if (vex.w
14457           || bytemode == xmmq_mode
14458           || bytemode == evex_half_bcst_xmmq_mode)
14459         {
14460           switch (vex.length)
14461             {
14462             case 128:
14463               oappend ("{1to2}");
14464               break;
14465             case 256:
14466               oappend ("{1to4}");
14467               break;
14468             case 512:
14469               oappend ("{1to8}");
14470               break;
14471             default:
14472               abort ();
14473             }
14474         }
14475       else
14476         {
14477           switch (vex.length)
14478             {
14479             case 128:
14480               oappend ("{1to4}");
14481               break;
14482             case 256:
14483               oappend ("{1to8}");
14484               break;
14485             case 512:
14486               oappend ("{1to16}");
14487               break;
14488             default:
14489               abort ();
14490             }
14491         }
14492     }
14493 }
14494
14495 static void
14496 OP_E (int bytemode, int sizeflag)
14497 {
14498   /* Skip mod/rm byte.  */
14499   MODRM_CHECK;
14500   codep++;
14501
14502   if (modrm.mod == 3)
14503     OP_E_register (bytemode, sizeflag);
14504   else
14505     OP_E_memory (bytemode, sizeflag);
14506 }
14507
14508 static void
14509 OP_G (int bytemode, int sizeflag)
14510 {
14511   int add = 0;
14512   const char **names;
14513   USED_REX (REX_R);
14514   if (rex & REX_R)
14515     add += 8;
14516   switch (bytemode)
14517     {
14518     case b_mode:
14519       USED_REX (0);
14520       if (rex)
14521         oappend (names8rex[modrm.reg + add]);
14522       else
14523         oappend (names8[modrm.reg + add]);
14524       break;
14525     case w_mode:
14526       oappend (names16[modrm.reg + add]);
14527       break;
14528     case d_mode:
14529     case db_mode:
14530     case dw_mode:
14531       oappend (names32[modrm.reg + add]);
14532       break;
14533     case q_mode:
14534       oappend (names64[modrm.reg + add]);
14535       break;
14536     case bnd_mode:
14537       if (modrm.reg > 0x3)
14538         {
14539           oappend ("(bad)");
14540           return;
14541         }
14542       oappend (names_bnd[modrm.reg]);
14543       break;
14544     case v_mode:
14545     case dq_mode:
14546     case dqb_mode:
14547     case dqd_mode:
14548     case dqw_mode:
14549     case movsxd_mode:
14550       USED_REX (REX_W);
14551       if (rex & REX_W)
14552         oappend (names64[modrm.reg + add]);
14553       else
14554         {
14555           if ((sizeflag & DFLAG)
14556               || (bytemode != v_mode && bytemode != movsxd_mode))
14557             oappend (names32[modrm.reg + add]);
14558           else
14559             oappend (names16[modrm.reg + add]);
14560           used_prefixes |= (prefixes & PREFIX_DATA);
14561         }
14562       break;
14563     case va_mode:
14564       names = (address_mode == mode_64bit
14565                ? names64 : names32);
14566       if (!(prefixes & PREFIX_ADDR))
14567         {
14568           if (address_mode == mode_16bit)
14569             names = names16;
14570         }
14571       else
14572         {
14573           /* Remove "addr16/addr32".  */
14574           all_prefixes[last_addr_prefix] = 0;
14575           names = (address_mode != mode_32bit
14576                        ? names32 : names16);
14577           used_prefixes |= PREFIX_ADDR;
14578         }
14579       oappend (names[modrm.reg + add]);
14580       break;
14581     case m_mode:
14582       if (address_mode == mode_64bit)
14583         oappend (names64[modrm.reg + add]);
14584       else
14585         oappend (names32[modrm.reg + add]);
14586       break;
14587     case mask_bd_mode:
14588     case mask_mode:
14589       if ((modrm.reg + add) > 0x7)
14590         {
14591           oappend ("(bad)");
14592           return;
14593         }
14594       oappend (names_mask[modrm.reg + add]);
14595       break;
14596     default:
14597       oappend (INTERNAL_DISASSEMBLER_ERROR);
14598       break;
14599     }
14600 }
14601
14602 static bfd_vma
14603 get64 (void)
14604 {
14605   bfd_vma x;
14606 #ifdef BFD64
14607   unsigned int a;
14608   unsigned int b;
14609
14610   FETCH_DATA (the_info, codep + 8);
14611   a = *codep++ & 0xff;
14612   a |= (*codep++ & 0xff) << 8;
14613   a |= (*codep++ & 0xff) << 16;
14614   a |= (*codep++ & 0xffu) << 24;
14615   b = *codep++ & 0xff;
14616   b |= (*codep++ & 0xff) << 8;
14617   b |= (*codep++ & 0xff) << 16;
14618   b |= (*codep++ & 0xffu) << 24;
14619   x = a + ((bfd_vma) b << 32);
14620 #else
14621   abort ();
14622   x = 0;
14623 #endif
14624   return x;
14625 }
14626
14627 static bfd_signed_vma
14628 get32 (void)
14629 {
14630   bfd_signed_vma x = 0;
14631
14632   FETCH_DATA (the_info, codep + 4);
14633   x = *codep++ & (bfd_signed_vma) 0xff;
14634   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14635   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14636   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14637   return x;
14638 }
14639
14640 static bfd_signed_vma
14641 get32s (void)
14642 {
14643   bfd_signed_vma x = 0;
14644
14645   FETCH_DATA (the_info, codep + 4);
14646   x = *codep++ & (bfd_signed_vma) 0xff;
14647   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14648   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14649   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14650
14651   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14652
14653   return x;
14654 }
14655
14656 static int
14657 get16 (void)
14658 {
14659   int x = 0;
14660
14661   FETCH_DATA (the_info, codep + 2);
14662   x = *codep++ & 0xff;
14663   x |= (*codep++ & 0xff) << 8;
14664   return x;
14665 }
14666
14667 static void
14668 set_op (bfd_vma op, int riprel)
14669 {
14670   op_index[op_ad] = op_ad;
14671   if (address_mode == mode_64bit)
14672     {
14673       op_address[op_ad] = op;
14674       op_riprel[op_ad] = riprel;
14675     }
14676   else
14677     {
14678       /* Mask to get a 32-bit address.  */
14679       op_address[op_ad] = op & 0xffffffff;
14680       op_riprel[op_ad] = riprel & 0xffffffff;
14681     }
14682 }
14683
14684 static void
14685 OP_REG (int code, int sizeflag)
14686 {
14687   const char *s;
14688   int add;
14689
14690   switch (code)
14691     {
14692     case es_reg: case ss_reg: case cs_reg:
14693     case ds_reg: case fs_reg: case gs_reg:
14694       oappend (names_seg[code - es_reg]);
14695       return;
14696     }
14697
14698   USED_REX (REX_B);
14699   if (rex & REX_B)
14700     add = 8;
14701   else
14702     add = 0;
14703
14704   switch (code)
14705     {
14706     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14707     case sp_reg: case bp_reg: case si_reg: case di_reg:
14708       s = names16[code - ax_reg + add];
14709       break;
14710     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14711     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14712       USED_REX (0);
14713       if (rex)
14714         s = names8rex[code - al_reg + add];
14715       else
14716         s = names8[code - al_reg];
14717       break;
14718     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14719     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14720       if (address_mode == mode_64bit
14721           && ((sizeflag & DFLAG) || (rex & REX_W)))
14722         {
14723           s = names64[code - rAX_reg + add];
14724           break;
14725         }
14726       code += eAX_reg - rAX_reg;
14727       /* Fall through.  */
14728     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14729     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14730       USED_REX (REX_W);
14731       if (rex & REX_W)
14732         s = names64[code - eAX_reg + add];
14733       else
14734         {
14735           if (sizeflag & DFLAG)
14736             s = names32[code - eAX_reg + add];
14737           else
14738             s = names16[code - eAX_reg + add];
14739           used_prefixes |= (prefixes & PREFIX_DATA);
14740         }
14741       break;
14742     default:
14743       s = INTERNAL_DISASSEMBLER_ERROR;
14744       break;
14745     }
14746   oappend (s);
14747 }
14748
14749 static void
14750 OP_IMREG (int code, int sizeflag)
14751 {
14752   const char *s;
14753
14754   switch (code)
14755     {
14756     case indir_dx_reg:
14757       if (intel_syntax)
14758         s = "dx";
14759       else
14760         s = "(%dx)";
14761       break;
14762     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14763     case sp_reg: case bp_reg: case si_reg: case di_reg:
14764       s = names16[code - ax_reg];
14765       break;
14766     case es_reg: case ss_reg: case cs_reg:
14767     case ds_reg: case fs_reg: case gs_reg:
14768       s = names_seg[code - es_reg];
14769       break;
14770     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14771     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14772       USED_REX (0);
14773       if (rex)
14774         s = names8rex[code - al_reg];
14775       else
14776         s = names8[code - al_reg];
14777       break;
14778     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14779     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14780       USED_REX (REX_W);
14781       if (rex & REX_W)
14782         s = names64[code - eAX_reg];
14783       else
14784         {
14785           if (sizeflag & DFLAG)
14786             s = names32[code - eAX_reg];
14787           else
14788             s = names16[code - eAX_reg];
14789           used_prefixes |= (prefixes & PREFIX_DATA);
14790         }
14791       break;
14792     case z_mode_ax_reg:
14793       if ((rex & REX_W) || (sizeflag & DFLAG))
14794         s = *names32;
14795       else
14796         s = *names16;
14797       if (!(rex & REX_W))
14798         used_prefixes |= (prefixes & PREFIX_DATA);
14799       break;
14800     default:
14801       s = INTERNAL_DISASSEMBLER_ERROR;
14802       break;
14803     }
14804   oappend (s);
14805 }
14806
14807 static void
14808 OP_I (int bytemode, int sizeflag)
14809 {
14810   bfd_signed_vma op;
14811   bfd_signed_vma mask = -1;
14812
14813   switch (bytemode)
14814     {
14815     case b_mode:
14816       FETCH_DATA (the_info, codep + 1);
14817       op = *codep++;
14818       mask = 0xff;
14819       break;
14820     case v_mode:
14821       USED_REX (REX_W);
14822       if (rex & REX_W)
14823         op = get32s ();
14824       else
14825         {
14826           if (sizeflag & DFLAG)
14827             {
14828               op = get32 ();
14829               mask = 0xffffffff;
14830             }
14831           else
14832             {
14833               op = get16 ();
14834               mask = 0xfffff;
14835             }
14836           used_prefixes |= (prefixes & PREFIX_DATA);
14837         }
14838       break;
14839     case d_mode:
14840       mask = 0xffffffff;
14841       op = get32 ();
14842       break;
14843     case w_mode:
14844       mask = 0xfffff;
14845       op = get16 ();
14846       break;
14847     case const_1_mode:
14848       if (intel_syntax)
14849         oappend ("1");
14850       return;
14851     default:
14852       oappend (INTERNAL_DISASSEMBLER_ERROR);
14853       return;
14854     }
14855
14856   op &= mask;
14857   scratchbuf[0] = '$';
14858   print_operand_value (scratchbuf + 1, 1, op);
14859   oappend_maybe_intel (scratchbuf);
14860   scratchbuf[0] = '\0';
14861 }
14862
14863 static void
14864 OP_I64 (int bytemode, int sizeflag)
14865 {
14866   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
14867     {
14868       OP_I (bytemode, sizeflag);
14869       return;
14870     }
14871
14872   USED_REX (REX_W);
14873
14874   scratchbuf[0] = '$';
14875   print_operand_value (scratchbuf + 1, 1, get64 ());
14876   oappend_maybe_intel (scratchbuf);
14877   scratchbuf[0] = '\0';
14878 }
14879
14880 static void
14881 OP_sI (int bytemode, int sizeflag)
14882 {
14883   bfd_signed_vma op;
14884
14885   switch (bytemode)
14886     {
14887     case b_mode:
14888     case b_T_mode:
14889       FETCH_DATA (the_info, codep + 1);
14890       op = *codep++;
14891       if ((op & 0x80) != 0)
14892         op -= 0x100;
14893       if (bytemode == b_T_mode)
14894         {
14895           if (address_mode != mode_64bit
14896               || !((sizeflag & DFLAG) || (rex & REX_W)))
14897             {
14898               /* The operand-size prefix is overridden by a REX prefix.  */
14899               if ((sizeflag & DFLAG) || (rex & REX_W))
14900                 op &= 0xffffffff;
14901               else
14902                 op &= 0xffff;
14903           }
14904         }
14905       else
14906         {
14907           if (!(rex & REX_W))
14908             {
14909               if (sizeflag & DFLAG)
14910                 op &= 0xffffffff;
14911               else
14912                 op &= 0xffff;
14913             }
14914         }
14915       break;
14916     case v_mode:
14917       /* The operand-size prefix is overridden by a REX prefix.  */
14918       if ((sizeflag & DFLAG) || (rex & REX_W))
14919         op = get32s ();
14920       else
14921         op = get16 ();
14922       break;
14923     default:
14924       oappend (INTERNAL_DISASSEMBLER_ERROR);
14925       return;
14926     }
14927
14928   scratchbuf[0] = '$';
14929   print_operand_value (scratchbuf + 1, 1, op);
14930   oappend_maybe_intel (scratchbuf);
14931 }
14932
14933 static void
14934 OP_J (int bytemode, int sizeflag)
14935 {
14936   bfd_vma disp;
14937   bfd_vma mask = -1;
14938   bfd_vma segment = 0;
14939
14940   switch (bytemode)
14941     {
14942     case b_mode:
14943       FETCH_DATA (the_info, codep + 1);
14944       disp = *codep++;
14945       if ((disp & 0x80) != 0)
14946         disp -= 0x100;
14947       break;
14948     case v_mode:
14949       if (isa64 != intel64)
14950     case dqw_mode:
14951         USED_REX (REX_W);
14952       if ((sizeflag & DFLAG)
14953           || (address_mode == mode_64bit
14954               && ((isa64 == intel64 && bytemode != dqw_mode)
14955                   || (rex & REX_W))))
14956         disp = get32s ();
14957       else
14958         {
14959           disp = get16 ();
14960           if ((disp & 0x8000) != 0)
14961             disp -= 0x10000;
14962           /* In 16bit mode, address is wrapped around at 64k within
14963              the same segment.  Otherwise, a data16 prefix on a jump
14964              instruction means that the pc is masked to 16 bits after
14965              the displacement is added!  */
14966           mask = 0xffff;
14967           if ((prefixes & PREFIX_DATA) == 0)
14968             segment = ((start_pc + (codep - start_codep))
14969                        & ~((bfd_vma) 0xffff));
14970         }
14971       if (address_mode != mode_64bit
14972           || (isa64 != intel64 && !(rex & REX_W)))
14973         used_prefixes |= (prefixes & PREFIX_DATA);
14974       break;
14975     default:
14976       oappend (INTERNAL_DISASSEMBLER_ERROR);
14977       return;
14978     }
14979   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14980   set_op (disp, 0);
14981   print_operand_value (scratchbuf, 1, disp);
14982   oappend (scratchbuf);
14983 }
14984
14985 static void
14986 OP_SEG (int bytemode, int sizeflag)
14987 {
14988   if (bytemode == w_mode)
14989     oappend (names_seg[modrm.reg]);
14990   else
14991     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14992 }
14993
14994 static void
14995 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14996 {
14997   int seg, offset;
14998
14999   if (sizeflag & DFLAG)
15000     {
15001       offset = get32 ();
15002       seg = get16 ();
15003     }
15004   else
15005     {
15006       offset = get16 ();
15007       seg = get16 ();
15008     }
15009   used_prefixes |= (prefixes & PREFIX_DATA);
15010   if (intel_syntax)
15011     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15012   else
15013     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15014   oappend (scratchbuf);
15015 }
15016
15017 static void
15018 OP_OFF (int bytemode, int sizeflag)
15019 {
15020   bfd_vma off;
15021
15022   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15023     intel_operand_size (bytemode, sizeflag);
15024   append_seg ();
15025
15026   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15027     off = get32 ();
15028   else
15029     off = get16 ();
15030
15031   if (intel_syntax)
15032     {
15033       if (!active_seg_prefix)
15034         {
15035           oappend (names_seg[ds_reg - es_reg]);
15036           oappend (":");
15037         }
15038     }
15039   print_operand_value (scratchbuf, 1, off);
15040   oappend (scratchbuf);
15041 }
15042
15043 static void
15044 OP_OFF64 (int bytemode, int sizeflag)
15045 {
15046   bfd_vma off;
15047
15048   if (address_mode != mode_64bit
15049       || (prefixes & PREFIX_ADDR))
15050     {
15051       OP_OFF (bytemode, sizeflag);
15052       return;
15053     }
15054
15055   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15056     intel_operand_size (bytemode, sizeflag);
15057   append_seg ();
15058
15059   off = get64 ();
15060
15061   if (intel_syntax)
15062     {
15063       if (!active_seg_prefix)
15064         {
15065           oappend (names_seg[ds_reg - es_reg]);
15066           oappend (":");
15067         }
15068     }
15069   print_operand_value (scratchbuf, 1, off);
15070   oappend (scratchbuf);
15071 }
15072
15073 static void
15074 ptr_reg (int code, int sizeflag)
15075 {
15076   const char *s;
15077
15078   *obufp++ = open_char;
15079   used_prefixes |= (prefixes & PREFIX_ADDR);
15080   if (address_mode == mode_64bit)
15081     {
15082       if (!(sizeflag & AFLAG))
15083         s = names32[code - eAX_reg];
15084       else
15085         s = names64[code - eAX_reg];
15086     }
15087   else if (sizeflag & AFLAG)
15088     s = names32[code - eAX_reg];
15089   else
15090     s = names16[code - eAX_reg];
15091   oappend (s);
15092   *obufp++ = close_char;
15093   *obufp = 0;
15094 }
15095
15096 static void
15097 OP_ESreg (int code, int sizeflag)
15098 {
15099   if (intel_syntax)
15100     {
15101       switch (codep[-1])
15102         {
15103         case 0x6d:      /* insw/insl */
15104           intel_operand_size (z_mode, sizeflag);
15105           break;
15106         case 0xa5:      /* movsw/movsl/movsq */
15107         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15108         case 0xab:      /* stosw/stosl */
15109         case 0xaf:      /* scasw/scasl */
15110           intel_operand_size (v_mode, sizeflag);
15111           break;
15112         default:
15113           intel_operand_size (b_mode, sizeflag);
15114         }
15115     }
15116   oappend_maybe_intel ("%es:");
15117   ptr_reg (code, sizeflag);
15118 }
15119
15120 static void
15121 OP_DSreg (int code, int sizeflag)
15122 {
15123   if (intel_syntax)
15124     {
15125       switch (codep[-1])
15126         {
15127         case 0x6f:      /* outsw/outsl */
15128           intel_operand_size (z_mode, sizeflag);
15129           break;
15130         case 0xa5:      /* movsw/movsl/movsq */
15131         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15132         case 0xad:      /* lodsw/lodsl/lodsq */
15133           intel_operand_size (v_mode, sizeflag);
15134           break;
15135         default:
15136           intel_operand_size (b_mode, sizeflag);
15137         }
15138     }
15139   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15140      default segment register DS is printed.  */
15141   if (!active_seg_prefix)
15142     active_seg_prefix = PREFIX_DS;
15143   append_seg ();
15144   ptr_reg (code, sizeflag);
15145 }
15146
15147 static void
15148 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15149 {
15150   int add;
15151   if (rex & REX_R)
15152     {
15153       USED_REX (REX_R);
15154       add = 8;
15155     }
15156   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15157     {
15158       all_prefixes[last_lock_prefix] = 0;
15159       used_prefixes |= PREFIX_LOCK;
15160       add = 8;
15161     }
15162   else
15163     add = 0;
15164   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15165   oappend_maybe_intel (scratchbuf);
15166 }
15167
15168 static void
15169 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15170 {
15171   int add;
15172   USED_REX (REX_R);
15173   if (rex & REX_R)
15174     add = 8;
15175   else
15176     add = 0;
15177   if (intel_syntax)
15178     sprintf (scratchbuf, "db%d", modrm.reg + add);
15179   else
15180     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15181   oappend (scratchbuf);
15182 }
15183
15184 static void
15185 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15186 {
15187   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15188   oappend_maybe_intel (scratchbuf);
15189 }
15190
15191 static void
15192 OP_R (int bytemode, int sizeflag)
15193 {
15194   /* Skip mod/rm byte.  */
15195   MODRM_CHECK;
15196   codep++;
15197   OP_E_register (bytemode, sizeflag);
15198 }
15199
15200 static void
15201 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15202 {
15203   int reg = modrm.reg;
15204   const char **names;
15205
15206   used_prefixes |= (prefixes & PREFIX_DATA);
15207   if (prefixes & PREFIX_DATA)
15208     {
15209       names = names_xmm;
15210       USED_REX (REX_R);
15211       if (rex & REX_R)
15212         reg += 8;
15213     }
15214   else
15215     names = names_mm;
15216   oappend (names[reg]);
15217 }
15218
15219 static void
15220 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15221 {
15222   int reg = modrm.reg;
15223   const char **names;
15224
15225   USED_REX (REX_R);
15226   if (rex & REX_R)
15227     reg += 8;
15228   if (vex.evex)
15229     {
15230       if (!vex.r)
15231         reg += 16;
15232     }
15233
15234   if (need_vex
15235       && bytemode != xmm_mode
15236       && bytemode != xmmq_mode
15237       && bytemode != evex_half_bcst_xmmq_mode
15238       && bytemode != ymm_mode
15239       && bytemode != scalar_mode)
15240     {
15241       switch (vex.length)
15242         {
15243         case 128:
15244           names = names_xmm;
15245           break;
15246         case 256:
15247           if (vex.w
15248               || (bytemode != vex_vsib_q_w_dq_mode
15249                   && bytemode != vex_vsib_q_w_d_mode))
15250             names = names_ymm;
15251           else
15252             names = names_xmm;
15253           break;
15254         case 512:
15255           names = names_zmm;
15256           break;
15257         default:
15258           abort ();
15259         }
15260     }
15261   else if (bytemode == xmmq_mode
15262            || bytemode == evex_half_bcst_xmmq_mode)
15263     {
15264       switch (vex.length)
15265         {
15266         case 128:
15267         case 256:
15268           names = names_xmm;
15269           break;
15270         case 512:
15271           names = names_ymm;
15272           break;
15273         default:
15274           abort ();
15275         }
15276     }
15277   else if (bytemode == ymm_mode)
15278     names = names_ymm;
15279   else
15280     names = names_xmm;
15281   oappend (names[reg]);
15282 }
15283
15284 static void
15285 OP_EM (int bytemode, int sizeflag)
15286 {
15287   int reg;
15288   const char **names;
15289
15290   if (modrm.mod != 3)
15291     {
15292       if (intel_syntax
15293           && (bytemode == v_mode || bytemode == v_swap_mode))
15294         {
15295           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15296           used_prefixes |= (prefixes & PREFIX_DATA);
15297         }
15298       OP_E (bytemode, sizeflag);
15299       return;
15300     }
15301
15302   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15303     swap_operand ();
15304
15305   /* Skip mod/rm byte.  */
15306   MODRM_CHECK;
15307   codep++;
15308   used_prefixes |= (prefixes & PREFIX_DATA);
15309   reg = modrm.rm;
15310   if (prefixes & PREFIX_DATA)
15311     {
15312       names = names_xmm;
15313       USED_REX (REX_B);
15314       if (rex & REX_B)
15315         reg += 8;
15316     }
15317   else
15318     names = names_mm;
15319   oappend (names[reg]);
15320 }
15321
15322 /* cvt* are the only instructions in sse2 which have
15323    both SSE and MMX operands and also have 0x66 prefix
15324    in their opcode. 0x66 was originally used to differentiate
15325    between SSE and MMX instruction(operands). So we have to handle the
15326    cvt* separately using OP_EMC and OP_MXC */
15327 static void
15328 OP_EMC (int bytemode, int sizeflag)
15329 {
15330   if (modrm.mod != 3)
15331     {
15332       if (intel_syntax && bytemode == v_mode)
15333         {
15334           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15335           used_prefixes |= (prefixes & PREFIX_DATA);
15336         }
15337       OP_E (bytemode, sizeflag);
15338       return;
15339     }
15340
15341   /* Skip mod/rm byte.  */
15342   MODRM_CHECK;
15343   codep++;
15344   used_prefixes |= (prefixes & PREFIX_DATA);
15345   oappend (names_mm[modrm.rm]);
15346 }
15347
15348 static void
15349 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15350 {
15351   used_prefixes |= (prefixes & PREFIX_DATA);
15352   oappend (names_mm[modrm.reg]);
15353 }
15354
15355 static void
15356 OP_EX (int bytemode, int sizeflag)
15357 {
15358   int reg;
15359   const char **names;
15360
15361   /* Skip mod/rm byte.  */
15362   MODRM_CHECK;
15363   codep++;
15364
15365   if (modrm.mod != 3)
15366     {
15367       OP_E_memory (bytemode, sizeflag);
15368       return;
15369     }
15370
15371   reg = modrm.rm;
15372   USED_REX (REX_B);
15373   if (rex & REX_B)
15374     reg += 8;
15375   if (vex.evex)
15376     {
15377       USED_REX (REX_X);
15378       if ((rex & REX_X))
15379         reg += 16;
15380     }
15381
15382   if ((sizeflag & SUFFIX_ALWAYS)
15383       && (bytemode == x_swap_mode
15384           || bytemode == d_swap_mode
15385           || bytemode == d_scalar_swap_mode
15386           || bytemode == q_swap_mode
15387           || bytemode == q_scalar_swap_mode))
15388     swap_operand ();
15389
15390   if (need_vex
15391       && bytemode != xmm_mode
15392       && bytemode != xmmdw_mode
15393       && bytemode != xmmqd_mode
15394       && bytemode != xmm_mb_mode
15395       && bytemode != xmm_mw_mode
15396       && bytemode != xmm_md_mode
15397       && bytemode != xmm_mq_mode
15398       && bytemode != xmmq_mode
15399       && bytemode != evex_half_bcst_xmmq_mode
15400       && bytemode != ymm_mode
15401       && bytemode != d_scalar_mode
15402       && bytemode != d_scalar_swap_mode
15403       && bytemode != q_scalar_mode
15404       && bytemode != q_scalar_swap_mode
15405       && bytemode != vex_scalar_w_dq_mode)
15406     {
15407       switch (vex.length)
15408         {
15409         case 128:
15410           names = names_xmm;
15411           break;
15412         case 256:
15413           names = names_ymm;
15414           break;
15415         case 512:
15416           names = names_zmm;
15417           break;
15418         default:
15419           abort ();
15420         }
15421     }
15422   else if (bytemode == xmmq_mode
15423            || bytemode == evex_half_bcst_xmmq_mode)
15424     {
15425       switch (vex.length)
15426         {
15427         case 128:
15428         case 256:
15429           names = names_xmm;
15430           break;
15431         case 512:
15432           names = names_ymm;
15433           break;
15434         default:
15435           abort ();
15436         }
15437     }
15438   else if (bytemode == ymm_mode)
15439     names = names_ymm;
15440   else
15441     names = names_xmm;
15442   oappend (names[reg]);
15443 }
15444
15445 static void
15446 OP_MS (int bytemode, int sizeflag)
15447 {
15448   if (modrm.mod == 3)
15449     OP_EM (bytemode, sizeflag);
15450   else
15451     BadOp ();
15452 }
15453
15454 static void
15455 OP_XS (int bytemode, int sizeflag)
15456 {
15457   if (modrm.mod == 3)
15458     OP_EX (bytemode, sizeflag);
15459   else
15460     BadOp ();
15461 }
15462
15463 static void
15464 OP_M (int bytemode, int sizeflag)
15465 {
15466   if (modrm.mod == 3)
15467     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15468     BadOp ();
15469   else
15470     OP_E (bytemode, sizeflag);
15471 }
15472
15473 static void
15474 OP_0f07 (int bytemode, int sizeflag)
15475 {
15476   if (modrm.mod != 3 || modrm.rm != 0)
15477     BadOp ();
15478   else
15479     OP_E (bytemode, sizeflag);
15480 }
15481
15482 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15483    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15484
15485 static void
15486 NOP_Fixup1 (int bytemode, int sizeflag)
15487 {
15488   if ((prefixes & PREFIX_DATA) != 0
15489       || (rex != 0
15490           && rex != 0x48
15491           && address_mode == mode_64bit))
15492     OP_REG (bytemode, sizeflag);
15493   else
15494     strcpy (obuf, "nop");
15495 }
15496
15497 static void
15498 NOP_Fixup2 (int bytemode, int sizeflag)
15499 {
15500   if ((prefixes & PREFIX_DATA) != 0
15501       || (rex != 0
15502           && rex != 0x48
15503           && address_mode == mode_64bit))
15504     OP_IMREG (bytemode, sizeflag);
15505 }
15506
15507 static const char *const Suffix3DNow[] = {
15508 /* 00 */        NULL,           NULL,           NULL,           NULL,
15509 /* 04 */        NULL,           NULL,           NULL,           NULL,
15510 /* 08 */        NULL,           NULL,           NULL,           NULL,
15511 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15512 /* 10 */        NULL,           NULL,           NULL,           NULL,
15513 /* 14 */        NULL,           NULL,           NULL,           NULL,
15514 /* 18 */        NULL,           NULL,           NULL,           NULL,
15515 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15516 /* 20 */        NULL,           NULL,           NULL,           NULL,
15517 /* 24 */        NULL,           NULL,           NULL,           NULL,
15518 /* 28 */        NULL,           NULL,           NULL,           NULL,
15519 /* 2C */        NULL,           NULL,           NULL,           NULL,
15520 /* 30 */        NULL,           NULL,           NULL,           NULL,
15521 /* 34 */        NULL,           NULL,           NULL,           NULL,
15522 /* 38 */        NULL,           NULL,           NULL,           NULL,
15523 /* 3C */        NULL,           NULL,           NULL,           NULL,
15524 /* 40 */        NULL,           NULL,           NULL,           NULL,
15525 /* 44 */        NULL,           NULL,           NULL,           NULL,
15526 /* 48 */        NULL,           NULL,           NULL,           NULL,
15527 /* 4C */        NULL,           NULL,           NULL,           NULL,
15528 /* 50 */        NULL,           NULL,           NULL,           NULL,
15529 /* 54 */        NULL,           NULL,           NULL,           NULL,
15530 /* 58 */        NULL,           NULL,           NULL,           NULL,
15531 /* 5C */        NULL,           NULL,           NULL,           NULL,
15532 /* 60 */        NULL,           NULL,           NULL,           NULL,
15533 /* 64 */        NULL,           NULL,           NULL,           NULL,
15534 /* 68 */        NULL,           NULL,           NULL,           NULL,
15535 /* 6C */        NULL,           NULL,           NULL,           NULL,
15536 /* 70 */        NULL,           NULL,           NULL,           NULL,
15537 /* 74 */        NULL,           NULL,           NULL,           NULL,
15538 /* 78 */        NULL,           NULL,           NULL,           NULL,
15539 /* 7C */        NULL,           NULL,           NULL,           NULL,
15540 /* 80 */        NULL,           NULL,           NULL,           NULL,
15541 /* 84 */        NULL,           NULL,           NULL,           NULL,
15542 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15543 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15544 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15545 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15546 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15547 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15548 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15549 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15550 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15551 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15552 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15553 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15554 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15555 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15556 /* C0 */        NULL,           NULL,           NULL,           NULL,
15557 /* C4 */        NULL,           NULL,           NULL,           NULL,
15558 /* C8 */        NULL,           NULL,           NULL,           NULL,
15559 /* CC */        NULL,           NULL,           NULL,           NULL,
15560 /* D0 */        NULL,           NULL,           NULL,           NULL,
15561 /* D4 */        NULL,           NULL,           NULL,           NULL,
15562 /* D8 */        NULL,           NULL,           NULL,           NULL,
15563 /* DC */        NULL,           NULL,           NULL,           NULL,
15564 /* E0 */        NULL,           NULL,           NULL,           NULL,
15565 /* E4 */        NULL,           NULL,           NULL,           NULL,
15566 /* E8 */        NULL,           NULL,           NULL,           NULL,
15567 /* EC */        NULL,           NULL,           NULL,           NULL,
15568 /* F0 */        NULL,           NULL,           NULL,           NULL,
15569 /* F4 */        NULL,           NULL,           NULL,           NULL,
15570 /* F8 */        NULL,           NULL,           NULL,           NULL,
15571 /* FC */        NULL,           NULL,           NULL,           NULL,
15572 };
15573
15574 static void
15575 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15576 {
15577   const char *mnemonic;
15578
15579   FETCH_DATA (the_info, codep + 1);
15580   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15581      place where an 8-bit immediate would normally go.  ie. the last
15582      byte of the instruction.  */
15583   obufp = mnemonicendp;
15584   mnemonic = Suffix3DNow[*codep++ & 0xff];
15585   if (mnemonic)
15586     oappend (mnemonic);
15587   else
15588     {
15589       /* Since a variable sized modrm/sib chunk is between the start
15590          of the opcode (0x0f0f) and the opcode suffix, we need to do
15591          all the modrm processing first, and don't know until now that
15592          we have a bad opcode.  This necessitates some cleaning up.  */
15593       op_out[0][0] = '\0';
15594       op_out[1][0] = '\0';
15595       BadOp ();
15596     }
15597   mnemonicendp = obufp;
15598 }
15599
15600 static struct op simd_cmp_op[] =
15601 {
15602   { STRING_COMMA_LEN ("eq") },
15603   { STRING_COMMA_LEN ("lt") },
15604   { STRING_COMMA_LEN ("le") },
15605   { STRING_COMMA_LEN ("unord") },
15606   { STRING_COMMA_LEN ("neq") },
15607   { STRING_COMMA_LEN ("nlt") },
15608   { STRING_COMMA_LEN ("nle") },
15609   { STRING_COMMA_LEN ("ord") }
15610 };
15611
15612 static void
15613 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15614 {
15615   unsigned int cmp_type;
15616
15617   FETCH_DATA (the_info, codep + 1);
15618   cmp_type = *codep++ & 0xff;
15619   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15620     {
15621       char suffix [3];
15622       char *p = mnemonicendp - 2;
15623       suffix[0] = p[0];
15624       suffix[1] = p[1];
15625       suffix[2] = '\0';
15626       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15627       mnemonicendp += simd_cmp_op[cmp_type].len;
15628     }
15629   else
15630     {
15631       /* We have a reserved extension byte.  Output it directly.  */
15632       scratchbuf[0] = '$';
15633       print_operand_value (scratchbuf + 1, 1, cmp_type);
15634       oappend_maybe_intel (scratchbuf);
15635       scratchbuf[0] = '\0';
15636     }
15637 }
15638
15639 static void
15640 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15641 {
15642   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
15643   if (!intel_syntax)
15644     {
15645       strcpy (op_out[0], names32[0]);
15646       strcpy (op_out[1], names32[1]);
15647       if (bytemode == eBX_reg)
15648         strcpy (op_out[2], names32[3]);
15649       two_source_ops = 1;
15650     }
15651   /* Skip mod/rm byte.  */
15652   MODRM_CHECK;
15653   codep++;
15654 }
15655
15656 static void
15657 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15658             int sizeflag ATTRIBUTE_UNUSED)
15659 {
15660   /* monitor %{e,r,}ax,%ecx,%edx"  */
15661   if (!intel_syntax)
15662     {
15663       const char **names = (address_mode == mode_64bit
15664                             ? names64 : names32);
15665
15666       if (prefixes & PREFIX_ADDR)
15667         {
15668           /* Remove "addr16/addr32".  */
15669           all_prefixes[last_addr_prefix] = 0;
15670           names = (address_mode != mode_32bit
15671                    ? names32 : names16);
15672           used_prefixes |= PREFIX_ADDR;
15673         }
15674       else if (address_mode == mode_16bit)
15675         names = names16;
15676       strcpy (op_out[0], names[0]);
15677       strcpy (op_out[1], names32[1]);
15678       strcpy (op_out[2], names32[2]);
15679       two_source_ops = 1;
15680     }
15681   /* Skip mod/rm byte.  */
15682   MODRM_CHECK;
15683   codep++;
15684 }
15685
15686 static void
15687 BadOp (void)
15688 {
15689   /* Throw away prefixes and 1st. opcode byte.  */
15690   codep = insn_codep + 1;
15691   oappend ("(bad)");
15692 }
15693
15694 static void
15695 REP_Fixup (int bytemode, int sizeflag)
15696 {
15697   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15698      lods and stos.  */
15699   if (prefixes & PREFIX_REPZ)
15700     all_prefixes[last_repz_prefix] = REP_PREFIX;
15701
15702   switch (bytemode)
15703     {
15704     case al_reg:
15705     case eAX_reg:
15706     case indir_dx_reg:
15707       OP_IMREG (bytemode, sizeflag);
15708       break;
15709     case eDI_reg:
15710       OP_ESreg (bytemode, sizeflag);
15711       break;
15712     case eSI_reg:
15713       OP_DSreg (bytemode, sizeflag);
15714       break;
15715     default:
15716       abort ();
15717       break;
15718     }
15719 }
15720
15721 static void
15722 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15723 {
15724   if ( isa64 != amd64 )
15725     return;
15726
15727   obufp = obuf;
15728   BadOp ();
15729   mnemonicendp = obufp;
15730   ++codep;
15731 }
15732
15733 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15734    "bnd".  */
15735
15736 static void
15737 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15738 {
15739   if (prefixes & PREFIX_REPNZ)
15740     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15741 }
15742
15743 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15744    "notrack".  */
15745
15746 static void
15747 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15748                int sizeflag ATTRIBUTE_UNUSED)
15749 {
15750   if (active_seg_prefix == PREFIX_DS
15751       && (address_mode != mode_64bit || last_data_prefix < 0))
15752     {
15753       /* NOTRACK prefix is only valid on indirect branch instructions.
15754          NB: DATA prefix is unsupported for Intel64.  */
15755       active_seg_prefix = 0;
15756       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15757     }
15758 }
15759
15760 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15761    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15762  */
15763
15764 static void
15765 HLE_Fixup1 (int bytemode, int sizeflag)
15766 {
15767   if (modrm.mod != 3
15768       && (prefixes & PREFIX_LOCK) != 0)
15769     {
15770       if (prefixes & PREFIX_REPZ)
15771         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15772       if (prefixes & PREFIX_REPNZ)
15773         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15774     }
15775
15776   OP_E (bytemode, sizeflag);
15777 }
15778
15779 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15780    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15781  */
15782
15783 static void
15784 HLE_Fixup2 (int bytemode, int sizeflag)
15785 {
15786   if (modrm.mod != 3)
15787     {
15788       if (prefixes & PREFIX_REPZ)
15789         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15790       if (prefixes & PREFIX_REPNZ)
15791         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15792     }
15793
15794   OP_E (bytemode, sizeflag);
15795 }
15796
15797 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15798    "xrelease" for memory operand.  No check for LOCK prefix.   */
15799
15800 static void
15801 HLE_Fixup3 (int bytemode, int sizeflag)
15802 {
15803   if (modrm.mod != 3
15804       && last_repz_prefix > last_repnz_prefix
15805       && (prefixes & PREFIX_REPZ) != 0)
15806     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15807
15808   OP_E (bytemode, sizeflag);
15809 }
15810
15811 static void
15812 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15813 {
15814   USED_REX (REX_W);
15815   if (rex & REX_W)
15816     {
15817       /* Change cmpxchg8b to cmpxchg16b.  */
15818       char *p = mnemonicendp - 2;
15819       mnemonicendp = stpcpy (p, "16b");
15820       bytemode = o_mode;
15821     }
15822   else if ((prefixes & PREFIX_LOCK) != 0)
15823     {
15824       if (prefixes & PREFIX_REPZ)
15825         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15826       if (prefixes & PREFIX_REPNZ)
15827         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15828     }
15829
15830   OP_M (bytemode, sizeflag);
15831 }
15832
15833 static void
15834 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15835 {
15836   const char **names;
15837
15838   if (need_vex)
15839     {
15840       switch (vex.length)
15841         {
15842         case 128:
15843           names = names_xmm;
15844           break;
15845         case 256:
15846           names = names_ymm;
15847           break;
15848         default:
15849           abort ();
15850         }
15851     }
15852   else
15853     names = names_xmm;
15854   oappend (names[reg]);
15855 }
15856
15857 static void
15858 CRC32_Fixup (int bytemode, int sizeflag)
15859 {
15860   /* Add proper suffix to "crc32".  */
15861   char *p = mnemonicendp;
15862
15863   switch (bytemode)
15864     {
15865     case b_mode:
15866       if (intel_syntax)
15867         goto skip;
15868
15869       *p++ = 'b';
15870       break;
15871     case v_mode:
15872       if (intel_syntax)
15873         goto skip;
15874
15875       USED_REX (REX_W);
15876       if (rex & REX_W)
15877         *p++ = 'q';
15878       else
15879         {
15880           if (sizeflag & DFLAG)
15881             *p++ = 'l';
15882           else
15883             *p++ = 'w';
15884           used_prefixes |= (prefixes & PREFIX_DATA);
15885         }
15886       break;
15887     default:
15888       oappend (INTERNAL_DISASSEMBLER_ERROR);
15889       break;
15890     }
15891   mnemonicendp = p;
15892   *p = '\0';
15893
15894  skip:
15895   if (modrm.mod == 3)
15896     {
15897       int add;
15898
15899       /* Skip mod/rm byte.  */
15900       MODRM_CHECK;
15901       codep++;
15902
15903       USED_REX (REX_B);
15904       add = (rex & REX_B) ? 8 : 0;
15905       if (bytemode == b_mode)
15906         {
15907           USED_REX (0);
15908           if (rex)
15909             oappend (names8rex[modrm.rm + add]);
15910           else
15911             oappend (names8[modrm.rm + add]);
15912         }
15913       else
15914         {
15915           USED_REX (REX_W);
15916           if (rex & REX_W)
15917             oappend (names64[modrm.rm + add]);
15918           else if ((prefixes & PREFIX_DATA))
15919             oappend (names16[modrm.rm + add]);
15920           else
15921             oappend (names32[modrm.rm + add]);
15922         }
15923     }
15924   else
15925     OP_E (bytemode, sizeflag);
15926 }
15927
15928 static void
15929 FXSAVE_Fixup (int bytemode, int sizeflag)
15930 {
15931   /* Add proper suffix to "fxsave" and "fxrstor".  */
15932   USED_REX (REX_W);
15933   if (rex & REX_W)
15934     {
15935       char *p = mnemonicendp;
15936       *p++ = '6';
15937       *p++ = '4';
15938       *p = '\0';
15939       mnemonicendp = p;
15940     }
15941   OP_M (bytemode, sizeflag);
15942 }
15943
15944 static void
15945 PCMPESTR_Fixup (int bytemode, int sizeflag)
15946 {
15947   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15948   if (!intel_syntax)
15949     {
15950       char *p = mnemonicendp;
15951
15952       USED_REX (REX_W);
15953       if (rex & REX_W)
15954         *p++ = 'q';
15955       else if (sizeflag & SUFFIX_ALWAYS)
15956         *p++ = 'l';
15957
15958       *p = '\0';
15959       mnemonicendp = p;
15960     }
15961
15962   OP_EX (bytemode, sizeflag);
15963 }
15964
15965 /* Display the destination register operand for instructions with
15966    VEX. */
15967
15968 static void
15969 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15970 {
15971   int reg;
15972   const char **names;
15973
15974   if (!need_vex)
15975     abort ();
15976
15977   if (!need_vex_reg)
15978     return;
15979
15980   reg = vex.register_specifier;
15981   vex.register_specifier = 0;
15982   if (address_mode != mode_64bit)
15983     reg &= 7;
15984   else if (vex.evex && !vex.v)
15985     reg += 16;
15986
15987   if (bytemode == vex_scalar_mode)
15988     {
15989       oappend (names_xmm[reg]);
15990       return;
15991     }
15992
15993   switch (vex.length)
15994     {
15995     case 128:
15996       switch (bytemode)
15997         {
15998         case vex_mode:
15999         case vex128_mode:
16000         case vex_vsib_q_w_dq_mode:
16001         case vex_vsib_q_w_d_mode:
16002           names = names_xmm;
16003           break;
16004         case dq_mode:
16005           if (rex & REX_W)
16006             names = names64;
16007           else
16008             names = names32;
16009           break;
16010         case mask_bd_mode:
16011         case mask_mode:
16012           if (reg > 0x7)
16013             {
16014               oappend ("(bad)");
16015               return;
16016             }
16017           names = names_mask;
16018           break;
16019         default:
16020           abort ();
16021           return;
16022         }
16023       break;
16024     case 256:
16025       switch (bytemode)
16026         {
16027         case vex_mode:
16028         case vex256_mode:
16029           names = names_ymm;
16030           break;
16031         case vex_vsib_q_w_dq_mode:
16032         case vex_vsib_q_w_d_mode:
16033           names = vex.w ? names_ymm : names_xmm;
16034           break;
16035         case mask_bd_mode:
16036         case mask_mode:
16037           if (reg > 0x7)
16038             {
16039               oappend ("(bad)");
16040               return;
16041             }
16042           names = names_mask;
16043           break;
16044         default:
16045           /* See PR binutils/20893 for a reproducer.  */
16046           oappend ("(bad)");
16047           return;
16048         }
16049       break;
16050     case 512:
16051       names = names_zmm;
16052       break;
16053     default:
16054       abort ();
16055       break;
16056     }
16057   oappend (names[reg]);
16058 }
16059
16060 /* Get the VEX immediate byte without moving codep.  */
16061
16062 static unsigned char
16063 get_vex_imm8 (int sizeflag, int opnum)
16064 {
16065   int bytes_before_imm = 0;
16066
16067   if (modrm.mod != 3)
16068     {
16069       /* There are SIB/displacement bytes.  */
16070       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16071         {
16072           /* 32/64 bit address mode */
16073           int base = modrm.rm;
16074
16075           /* Check SIB byte.  */
16076           if (base == 4)
16077             {
16078               FETCH_DATA (the_info, codep + 1);
16079               base = *codep & 7;
16080               /* When decoding the third source, don't increase
16081                  bytes_before_imm as this has already been incremented
16082                  by one in OP_E_memory while decoding the second
16083                  source operand.  */
16084               if (opnum == 0)
16085                 bytes_before_imm++;
16086             }
16087
16088           /* Don't increase bytes_before_imm when decoding the third source,
16089              it has already been incremented by OP_E_memory while decoding
16090              the second source operand.  */
16091           if (opnum == 0)
16092             {
16093               switch (modrm.mod)
16094                 {
16095                   case 0:
16096                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16097                        SIB == 5, there is a 4 byte displacement.  */
16098                     if (base != 5)
16099                       /* No displacement. */
16100                       break;
16101                     /* Fall through.  */
16102                   case 2:
16103                     /* 4 byte displacement.  */
16104                     bytes_before_imm += 4;
16105                     break;
16106                   case 1:
16107                     /* 1 byte displacement.  */
16108                     bytes_before_imm++;
16109                     break;
16110                 }
16111             }
16112         }
16113       else
16114         {
16115           /* 16 bit address mode */
16116           /* Don't increase bytes_before_imm when decoding the third source,
16117              it has already been incremented by OP_E_memory while decoding
16118              the second source operand.  */
16119           if (opnum == 0)
16120             {
16121               switch (modrm.mod)
16122                 {
16123                 case 0:
16124                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16125                   if (modrm.rm != 6)
16126                     /* No displacement. */
16127                     break;
16128                   /* Fall through.  */
16129                 case 2:
16130                   /* 2 byte displacement.  */
16131                   bytes_before_imm += 2;
16132                   break;
16133                 case 1:
16134                   /* 1 byte displacement: when decoding the third source,
16135                      don't increase bytes_before_imm as this has already
16136                      been incremented by one in OP_E_memory while decoding
16137                      the second source operand.  */
16138                   if (opnum == 0)
16139                     bytes_before_imm++;
16140
16141                   break;
16142                 }
16143             }
16144         }
16145     }
16146
16147   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16148   return codep [bytes_before_imm];
16149 }
16150
16151 static void
16152 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16153 {
16154   const char **names;
16155
16156   if (reg == -1 && modrm.mod != 3)
16157     {
16158       OP_E_memory (bytemode, sizeflag);
16159       return;
16160     }
16161   else
16162     {
16163       if (reg == -1)
16164         {
16165           reg = modrm.rm;
16166           USED_REX (REX_B);
16167           if (rex & REX_B)
16168             reg += 8;
16169         }
16170       if (address_mode != mode_64bit)
16171         reg &= 7;
16172     }
16173
16174   switch (vex.length)
16175     {
16176     case 128:
16177       names = names_xmm;
16178       break;
16179     case 256:
16180       names = names_ymm;
16181       break;
16182     default:
16183       abort ();
16184     }
16185   oappend (names[reg]);
16186 }
16187
16188 static void
16189 OP_EX_VexImmW (int bytemode, int sizeflag)
16190 {
16191   int reg = -1;
16192   static unsigned char vex_imm8;
16193
16194   if (vex_w_done == 0)
16195     {
16196       vex_w_done = 1;
16197
16198       /* Skip mod/rm byte.  */
16199       MODRM_CHECK;
16200       codep++;
16201
16202       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16203
16204       if (vex.w)
16205           reg = vex_imm8 >> 4;
16206
16207       OP_EX_VexReg (bytemode, sizeflag, reg);
16208     }
16209   else if (vex_w_done == 1)
16210     {
16211       vex_w_done = 2;
16212
16213       if (!vex.w)
16214           reg = vex_imm8 >> 4;
16215
16216       OP_EX_VexReg (bytemode, sizeflag, reg);
16217     }
16218   else
16219     {
16220       /* Output the imm8 directly.  */
16221       scratchbuf[0] = '$';
16222       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16223       oappend_maybe_intel (scratchbuf);
16224       scratchbuf[0] = '\0';
16225       codep++;
16226     }
16227 }
16228
16229 static void
16230 OP_Vex_2src (int bytemode, int sizeflag)
16231 {
16232   if (modrm.mod == 3)
16233     {
16234       int reg = modrm.rm;
16235       USED_REX (REX_B);
16236       if (rex & REX_B)
16237         reg += 8;
16238       oappend (names_xmm[reg]);
16239     }
16240   else
16241     {
16242       if (intel_syntax
16243           && (bytemode == v_mode || bytemode == v_swap_mode))
16244         {
16245           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16246           used_prefixes |= (prefixes & PREFIX_DATA);
16247         }
16248       OP_E (bytemode, sizeflag);
16249     }
16250 }
16251
16252 static void
16253 OP_Vex_2src_1 (int bytemode, int sizeflag)
16254 {
16255   if (modrm.mod == 3)
16256     {
16257       /* Skip mod/rm byte.   */
16258       MODRM_CHECK;
16259       codep++;
16260     }
16261
16262   if (vex.w)
16263     {
16264       unsigned int reg = vex.register_specifier;
16265       vex.register_specifier = 0;
16266
16267       if (address_mode != mode_64bit)
16268         reg &= 7;
16269       oappend (names_xmm[reg]);
16270     }
16271   else
16272     OP_Vex_2src (bytemode, sizeflag);
16273 }
16274
16275 static void
16276 OP_Vex_2src_2 (int bytemode, int sizeflag)
16277 {
16278   if (vex.w)
16279     OP_Vex_2src (bytemode, sizeflag);
16280   else
16281     {
16282       unsigned int reg = vex.register_specifier;
16283       vex.register_specifier = 0;
16284
16285       if (address_mode != mode_64bit)
16286         reg &= 7;
16287       oappend (names_xmm[reg]);
16288     }
16289 }
16290
16291 static void
16292 OP_EX_VexW (int bytemode, int sizeflag)
16293 {
16294   int reg = -1;
16295
16296   if (!vex_w_done)
16297     {
16298       /* Skip mod/rm byte.  */
16299       MODRM_CHECK;
16300       codep++;
16301
16302       if (vex.w)
16303         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16304     }
16305   else
16306     {
16307       if (!vex.w)
16308         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16309     }
16310
16311   OP_EX_VexReg (bytemode, sizeflag, reg);
16312
16313   if (vex_w_done)
16314     codep++;
16315   vex_w_done = 1;
16316 }
16317
16318 static void
16319 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16320 {
16321   int reg;
16322   const char **names;
16323
16324   FETCH_DATA (the_info, codep + 1);
16325   reg = *codep++;
16326
16327   if (bytemode != x_mode)
16328     abort ();
16329
16330   reg >>= 4;
16331   if (address_mode != mode_64bit)
16332     reg &= 7;
16333
16334   switch (vex.length)
16335     {
16336     case 128:
16337       names = names_xmm;
16338       break;
16339     case 256:
16340       names = names_ymm;
16341       break;
16342     default:
16343       abort ();
16344     }
16345   oappend (names[reg]);
16346 }
16347
16348 static void
16349 OP_XMM_VexW (int bytemode, int sizeflag)
16350 {
16351   /* Turn off the REX.W bit since it is used for swapping operands
16352      now.  */
16353   rex &= ~REX_W;
16354   OP_XMM (bytemode, sizeflag);
16355 }
16356
16357 static void
16358 OP_EX_Vex (int bytemode, int sizeflag)
16359 {
16360   if (modrm.mod != 3)
16361     need_vex_reg = 0;
16362   OP_EX (bytemode, sizeflag);
16363 }
16364
16365 static void
16366 OP_XMM_Vex (int bytemode, int sizeflag)
16367 {
16368   if (modrm.mod != 3)
16369     need_vex_reg = 0;
16370   OP_XMM (bytemode, sizeflag);
16371 }
16372
16373 static struct op vex_cmp_op[] =
16374 {
16375   { STRING_COMMA_LEN ("eq") },
16376   { STRING_COMMA_LEN ("lt") },
16377   { STRING_COMMA_LEN ("le") },
16378   { STRING_COMMA_LEN ("unord") },
16379   { STRING_COMMA_LEN ("neq") },
16380   { STRING_COMMA_LEN ("nlt") },
16381   { STRING_COMMA_LEN ("nle") },
16382   { STRING_COMMA_LEN ("ord") },
16383   { STRING_COMMA_LEN ("eq_uq") },
16384   { STRING_COMMA_LEN ("nge") },
16385   { STRING_COMMA_LEN ("ngt") },
16386   { STRING_COMMA_LEN ("false") },
16387   { STRING_COMMA_LEN ("neq_oq") },
16388   { STRING_COMMA_LEN ("ge") },
16389   { STRING_COMMA_LEN ("gt") },
16390   { STRING_COMMA_LEN ("true") },
16391   { STRING_COMMA_LEN ("eq_os") },
16392   { STRING_COMMA_LEN ("lt_oq") },
16393   { STRING_COMMA_LEN ("le_oq") },
16394   { STRING_COMMA_LEN ("unord_s") },
16395   { STRING_COMMA_LEN ("neq_us") },
16396   { STRING_COMMA_LEN ("nlt_uq") },
16397   { STRING_COMMA_LEN ("nle_uq") },
16398   { STRING_COMMA_LEN ("ord_s") },
16399   { STRING_COMMA_LEN ("eq_us") },
16400   { STRING_COMMA_LEN ("nge_uq") },
16401   { STRING_COMMA_LEN ("ngt_uq") },
16402   { STRING_COMMA_LEN ("false_os") },
16403   { STRING_COMMA_LEN ("neq_os") },
16404   { STRING_COMMA_LEN ("ge_oq") },
16405   { STRING_COMMA_LEN ("gt_oq") },
16406   { STRING_COMMA_LEN ("true_us") },
16407 };
16408
16409 static void
16410 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16411 {
16412   unsigned int cmp_type;
16413
16414   FETCH_DATA (the_info, codep + 1);
16415   cmp_type = *codep++ & 0xff;
16416   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16417     {
16418       char suffix [3];
16419       char *p = mnemonicendp - 2;
16420       suffix[0] = p[0];
16421       suffix[1] = p[1];
16422       suffix[2] = '\0';
16423       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16424       mnemonicendp += vex_cmp_op[cmp_type].len;
16425     }
16426   else
16427     {
16428       /* We have a reserved extension byte.  Output it directly.  */
16429       scratchbuf[0] = '$';
16430       print_operand_value (scratchbuf + 1, 1, cmp_type);
16431       oappend_maybe_intel (scratchbuf);
16432       scratchbuf[0] = '\0';
16433     }
16434 }
16435
16436 static void
16437 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16438              int sizeflag ATTRIBUTE_UNUSED)
16439 {
16440   unsigned int cmp_type;
16441
16442   if (!vex.evex)
16443     abort ();
16444
16445   FETCH_DATA (the_info, codep + 1);
16446   cmp_type = *codep++ & 0xff;
16447   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16448      If it's the case, print suffix, otherwise - print the immediate.  */
16449   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16450       && cmp_type != 3
16451       && cmp_type != 7)
16452     {
16453       char suffix [3];
16454       char *p = mnemonicendp - 2;
16455
16456       /* vpcmp* can have both one- and two-lettered suffix.  */
16457       if (p[0] == 'p')
16458         {
16459           p++;
16460           suffix[0] = p[0];
16461           suffix[1] = '\0';
16462         }
16463       else
16464         {
16465           suffix[0] = p[0];
16466           suffix[1] = p[1];
16467           suffix[2] = '\0';
16468         }
16469
16470       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16471       mnemonicendp += simd_cmp_op[cmp_type].len;
16472     }
16473   else
16474     {
16475       /* We have a reserved extension byte.  Output it directly.  */
16476       scratchbuf[0] = '$';
16477       print_operand_value (scratchbuf + 1, 1, cmp_type);
16478       oappend_maybe_intel (scratchbuf);
16479       scratchbuf[0] = '\0';
16480     }
16481 }
16482
16483 static const struct op xop_cmp_op[] =
16484 {
16485   { STRING_COMMA_LEN ("lt") },
16486   { STRING_COMMA_LEN ("le") },
16487   { STRING_COMMA_LEN ("gt") },
16488   { STRING_COMMA_LEN ("ge") },
16489   { STRING_COMMA_LEN ("eq") },
16490   { STRING_COMMA_LEN ("neq") },
16491   { STRING_COMMA_LEN ("false") },
16492   { STRING_COMMA_LEN ("true") }
16493 };
16494
16495 static void
16496 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16497              int sizeflag ATTRIBUTE_UNUSED)
16498 {
16499   unsigned int cmp_type;
16500
16501   FETCH_DATA (the_info, codep + 1);
16502   cmp_type = *codep++ & 0xff;
16503   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16504     {
16505       char suffix[3];
16506       char *p = mnemonicendp - 2;
16507
16508       /* vpcom* can have both one- and two-lettered suffix.  */
16509       if (p[0] == 'm')
16510         {
16511           p++;
16512           suffix[0] = p[0];
16513           suffix[1] = '\0';
16514         }
16515       else
16516         {
16517           suffix[0] = p[0];
16518           suffix[1] = p[1];
16519           suffix[2] = '\0';
16520         }
16521
16522       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16523       mnemonicendp += xop_cmp_op[cmp_type].len;
16524     }
16525   else
16526     {
16527       /* We have a reserved extension byte.  Output it directly.  */
16528       scratchbuf[0] = '$';
16529       print_operand_value (scratchbuf + 1, 1, cmp_type);
16530       oappend_maybe_intel (scratchbuf);
16531       scratchbuf[0] = '\0';
16532     }
16533 }
16534
16535 static const struct op pclmul_op[] =
16536 {
16537   { STRING_COMMA_LEN ("lql") },
16538   { STRING_COMMA_LEN ("hql") },
16539   { STRING_COMMA_LEN ("lqh") },
16540   { STRING_COMMA_LEN ("hqh") }
16541 };
16542
16543 static void
16544 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16545               int sizeflag ATTRIBUTE_UNUSED)
16546 {
16547   unsigned int pclmul_type;
16548
16549   FETCH_DATA (the_info, codep + 1);
16550   pclmul_type = *codep++ & 0xff;
16551   switch (pclmul_type)
16552     {
16553     case 0x10:
16554       pclmul_type = 2;
16555       break;
16556     case 0x11:
16557       pclmul_type = 3;
16558       break;
16559     default:
16560       break;
16561     }
16562   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16563     {
16564       char suffix [4];
16565       char *p = mnemonicendp - 3;
16566       suffix[0] = p[0];
16567       suffix[1] = p[1];
16568       suffix[2] = p[2];
16569       suffix[3] = '\0';
16570       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16571       mnemonicendp += pclmul_op[pclmul_type].len;
16572     }
16573   else
16574     {
16575       /* We have a reserved extension byte.  Output it directly.  */
16576       scratchbuf[0] = '$';
16577       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16578       oappend_maybe_intel (scratchbuf);
16579       scratchbuf[0] = '\0';
16580     }
16581 }
16582
16583 static void
16584 MOVBE_Fixup (int bytemode, int sizeflag)
16585 {
16586   /* Add proper suffix to "movbe".  */
16587   char *p = mnemonicendp;
16588
16589   switch (bytemode)
16590     {
16591     case v_mode:
16592       if (intel_syntax)
16593         goto skip;
16594
16595       USED_REX (REX_W);
16596       if (sizeflag & SUFFIX_ALWAYS)
16597         {
16598           if (rex & REX_W)
16599             *p++ = 'q';
16600           else
16601             {
16602               if (sizeflag & DFLAG)
16603                 *p++ = 'l';
16604               else
16605                 *p++ = 'w';
16606               used_prefixes |= (prefixes & PREFIX_DATA);
16607             }
16608         }
16609       break;
16610     default:
16611       oappend (INTERNAL_DISASSEMBLER_ERROR);
16612       break;
16613     }
16614   mnemonicendp = p;
16615   *p = '\0';
16616
16617  skip:
16618   OP_M (bytemode, sizeflag);
16619 }
16620
16621 static void
16622 MOVSXD_Fixup (int bytemode, int sizeflag)
16623 {
16624   /* Add proper suffix to "movsxd".  */
16625   char *p = mnemonicendp;
16626
16627   switch (bytemode)
16628     {
16629     case movsxd_mode:
16630       if (intel_syntax)
16631         {
16632           *p++ = 'x';
16633           *p++ = 'd';
16634           goto skip;
16635         }
16636
16637       USED_REX (REX_W);
16638       if (rex & REX_W)
16639         {
16640           *p++ = 'l';
16641           *p++ = 'q';
16642         }
16643       else
16644         {
16645           *p++ = 'x';
16646           *p++ = 'd';
16647         }
16648       break;
16649     default:
16650       oappend (INTERNAL_DISASSEMBLER_ERROR);
16651       break;
16652     }
16653
16654  skip:
16655   mnemonicendp = p;
16656   *p = '\0';
16657   OP_E (bytemode, sizeflag);
16658 }
16659
16660 static void
16661 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16662 {
16663   int reg;
16664   const char **names;
16665
16666   /* Skip mod/rm byte.  */
16667   MODRM_CHECK;
16668   codep++;
16669
16670   if (rex & REX_W)
16671     names = names64;
16672   else
16673     names = names32;
16674
16675   reg = modrm.rm;
16676   USED_REX (REX_B);
16677   if (rex & REX_B)
16678     reg += 8;
16679
16680   oappend (names[reg]);
16681 }
16682
16683 static void
16684 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16685 {
16686   const char **names;
16687   unsigned int reg = vex.register_specifier;
16688   vex.register_specifier = 0;
16689
16690   if (rex & REX_W)
16691     names = names64;
16692   else
16693     names = names32;
16694
16695   if (address_mode != mode_64bit)
16696     reg &= 7;
16697   oappend (names[reg]);
16698 }
16699
16700 static void
16701 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16702 {
16703   if (!vex.evex
16704       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16705     abort ();
16706
16707   USED_REX (REX_R);
16708   if ((rex & REX_R) != 0 || !vex.r)
16709     {
16710       BadOp ();
16711       return;
16712     }
16713
16714   oappend (names_mask [modrm.reg]);
16715 }
16716
16717 static void
16718 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16719 {
16720   if (!vex.evex
16721       || (bytemode != evex_rounding_mode
16722           && bytemode != evex_rounding_64_mode
16723           && bytemode != evex_sae_mode))
16724     abort ();
16725   if (modrm.mod == 3 && vex.b)
16726     switch (bytemode)
16727       {
16728       case evex_rounding_64_mode:
16729         if (address_mode != mode_64bit)
16730           {
16731             oappend ("(bad)");
16732             break;
16733           }
16734         /* Fall through.  */
16735       case evex_rounding_mode:
16736         oappend (names_rounding[vex.ll]);
16737         break;
16738       case evex_sae_mode:
16739         oappend ("{sae}");
16740         break;
16741       default:
16742         break;
16743       }
16744 }