opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 #include <setjmp.h>
  43
  44 static int print_insn (bfd_vma, disassemble_info *);
  45 static void dofloat (int);
  46 static void OP_ST (int, int);
  47 static void OP_STi (int, int);
  48 static int putop (const char *, int);
  49 static void oappend (const char *);
  50 static void append_seg (void);
  51 static void OP_indirE (int, int);
  52 static void print_operand_value (char *, int, bfd_vma);
  53 static void OP_E_register (int, int);
  54 static void OP_E_memory (int, int);
  55 static void print_displacement (char *, bfd_vma);
  56 static void OP_E (int, int);
  57 static void OP_G (int, int);
  58 static bfd_vma get64 (void);
  59 static bfd_signed_vma get32 (void);
  60 static bfd_signed_vma get32s (void);
  61 static int get16 (void);
  62 static void set_op (bfd_vma, int);
  63 static void OP_Skip_MODRM (int, int);
  64 static void OP_REG (int, int);
  65 static void OP_IMREG (int, int);
  66 static void OP_I (int, int);
  67 static void OP_I64 (int, int);
  68 static void OP_sI (int, int);
  69 static void OP_J (int, int);
  70 static void OP_SEG (int, int);
  71 static void OP_DIR (int, int);
  72 static void OP_OFF (int, int);
  73 static void OP_OFF64 (int, int);
  74 static void ptr_reg (int, int);
  75 static void OP_ESreg (int, int);
  76 static void OP_DSreg (int, int);
  77 static void OP_C (int, int);
  78 static void OP_D (int, int);
  79 static void OP_T (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_VexR (int, int);
  91 static void OP_VexW (int, int);
  92 static void OP_Rounding (int, int);
  93 static void OP_REG_VexI4 (int, int);
  94 static void OP_VexI4 (int, int);
  95 static void PCLMUL_Fixup (int, int);
  96 static void VPCMP_Fixup (int, int);
  97 static void VPCOM_Fixup (int, int);
  98 static void OP_0f07 (int, int);
  99 static void OP_Monitor (int, int);
 100 static void OP_Mwait (int, int);
 101 static void NOP_Fixup1 (int, int);
 102 static void NOP_Fixup2 (int, int);
 103 static void OP_3DNowSuffix (int, int);
 104 static void CMP_Fixup (int, int);
 105 static void BadOp (void);
 106 static void REP_Fixup (int, int);
 107 static void SEP_Fixup (int, int);
 108 static void BND_Fixup (int, int);
 109 static void NOTRACK_Fixup (int, int);
 110 static void HLE_Fixup1 (int, int);
 111 static void HLE_Fixup2 (int, int);
 112 static void HLE_Fixup3 (int, int);
 113 static void CMPXCHG8B_Fixup (int, int);
 114 static void XMM_Fixup (int, int);
 115 static void FXSAVE_Fixup (int, int);
 116
 117 static void MOVSXD_Fixup (int, int);
 118
 119 static void OP_Mask (int, int);
 120
 121 struct dis_private {
 122   /* Points to first byte not fetched.  */
 123   bfd_byte *max_fetched;
 124   bfd_byte the_buffer[MAX_MNEM_SIZE];
 125   bfd_vma insn_start;
 126   int orig_sizeflag;
 127   OPCODES_SIGJMP_BUF bailout;
 128 };
 129
 130 enum address_mode
 131 {
 132   mode_16bit,
 133   mode_32bit,
 134   mode_64bit
 135 };
 136
 137 enum address_mode address_mode;
 138
 139 /* Flags for the prefixes for the current instruction.  See below.  */
 140 static int prefixes;
 141
 142 /* REX prefix the current instruction.  See below.  */
 143 static int rex;
 144 /* Bits of REX we've already used.  */
 145 static int rex_used;
 146 /* Mark parts used in the REX prefix.  When we are testing for
 147    empty prefix (for 8bit register REX extension), just mask it
 148    out.  Otherwise test for REX bit is excuse for existence of REX
 149    only in case value is nonzero.  */
 150 #define USED_REX(value)                                 \
 151   {                                                     \
 152     if (value)                                          \
 153       {                                                 \
 154         if ((rex & value))                              \
 155           rex_used |= (value) | REX_OPCODE;             \
 156       }                                                 \
 157     else                                                \
 158       rex_used |= REX_OPCODE;                           \
 159   }
 160
 161 /* Flags for prefixes which we somehow handled when printing the
 162    current instruction.  */
 163 static int used_prefixes;
 164
 165 /* Flags stored in PREFIXES.  */
 166 #define PREFIX_REPZ 1
 167 #define PREFIX_REPNZ 2
 168 #define PREFIX_LOCK 4
 169 #define PREFIX_CS 8
 170 #define PREFIX_SS 0x10
 171 #define PREFIX_DS 0x20
 172 #define PREFIX_ES 0x40
 173 #define PREFIX_FS 0x80
 174 #define PREFIX_GS 0x100
 175 #define PREFIX_DATA 0x200
 176 #define PREFIX_ADDR 0x400
 177 #define PREFIX_FWAIT 0x800
 178
 179 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 180    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 181    on error.  */
 182 #define FETCH_DATA(info, addr) \
 183   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 184    ? 1 : fetch_data ((info), (addr)))
 185
 186 static int
 187 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 188 {
 189   int status;
 190   struct dis_private *priv = (struct dis_private *) info->private_data;
 191   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 192
 193   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 194     status = (*info->read_memory_func) (start,
 195                                         priv->max_fetched,
 196                                         addr - priv->max_fetched,
 197                                         info);
 198   else
 199     status = -1;
 200   if (status != 0)
 201     {
 202       /* If we did manage to read at least one byte, then
 203          print_insn_i386 will do something sensible.  Otherwise, print
 204          an error.  We do that here because this is where we know
 205          STATUS.  */
 206       if (priv->max_fetched == priv->the_buffer)
 207         (*info->memory_error_func) (status, start, info);
 208       OPCODES_SIGLONGJMP (priv->bailout, 1);
 209     }
 210   else
 211     priv->max_fetched = addr;
 212   return 1;
 213 }
 214
 215 /* Possible values for prefix requirement.  */
 216 #define PREFIX_IGNORED_SHIFT    16
 217 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 218 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 219 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 220 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 221 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 222
 223 /* Opcode prefixes.  */
 224 #define PREFIX_OPCODE           (PREFIX_REPZ \
 225                                  | PREFIX_REPNZ \
 226                                  | PREFIX_DATA)
 227
 228 /* Prefixes ignored.  */
 229 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 230                                  | PREFIX_IGNORED_REPNZ \
 231                                  | PREFIX_IGNORED_DATA)
 232
 233 #define XX { NULL, 0 }
 234 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 235
 236 #define Eb { OP_E, b_mode }
 237 #define Ebnd { OP_E, bnd_mode }
 238 #define EbS { OP_E, b_swap_mode }
 239 #define EbndS { OP_E, bnd_swap_mode }
 240 #define Ev { OP_E, v_mode }
 241 #define Eva { OP_E, va_mode }
 242 #define Ev_bnd { OP_E, v_bnd_mode }
 243 #define EvS { OP_E, v_swap_mode }
 244 #define Ed { OP_E, d_mode }
 245 #define Edq { OP_E, dq_mode }
 246 #define Edqw { OP_E, dqw_mode }
 247 #define Edqb { OP_E, dqb_mode }
 248 #define Edb { OP_E, db_mode }
 249 #define Edw { OP_E, dw_mode }
 250 #define Edqd { OP_E, dqd_mode }
 251 #define Eq { OP_E, q_mode }
 252 #define indirEv { OP_indirE, indir_v_mode }
 253 #define indirEp { OP_indirE, f_mode }
 254 #define stackEv { OP_E, stack_v_mode }
 255 #define Em { OP_E, m_mode }
 256 #define Ew { OP_E, w_mode }
 257 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 258 #define Ma { OP_M, a_mode }
 259 #define Mb { OP_M, b_mode }
 260 #define Md { OP_M, d_mode }
 261 #define Mo { OP_M, o_mode }
 262 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 263 #define Mq { OP_M, q_mode }
 264 #define Mv { OP_M, v_mode }
 265 #define Mv_bnd { OP_M, v_bndmk_mode }
 266 #define Mx { OP_M, x_mode }
 267 #define Mxmm { OP_M, xmm_mode }
 268 #define Gb { OP_G, b_mode }
 269 #define Gbnd { OP_G, bnd_mode }
 270 #define Gv { OP_G, v_mode }
 271 #define Gd { OP_G, d_mode }
 272 #define Gdq { OP_G, dq_mode }
 273 #define Gm { OP_G, m_mode }
 274 #define Gva { OP_G, va_mode }
 275 #define Gw { OP_G, w_mode }
 276 #define Ib { OP_I, b_mode }
 277 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 278 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 279 #define Iv { OP_I, v_mode }
 280 #define sIv { OP_sI, v_mode }
 281 #define Iv64 { OP_I64, v_mode }
 282 #define Id { OP_I, d_mode }
 283 #define Iw { OP_I, w_mode }
 284 #define I1 { OP_I, const_1_mode }
 285 #define Jb { OP_J, b_mode }
 286 #define Jv { OP_J, v_mode }
 287 #define Jdqw { OP_J, dqw_mode }
 288 #define Cm { OP_C, m_mode }
 289 #define Dm { OP_D, m_mode }
 290 #define Td { OP_T, d_mode }
 291 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 292
 293 #define RMeAX { OP_REG, eAX_reg }
 294 #define RMeBX { OP_REG, eBX_reg }
 295 #define RMeCX { OP_REG, eCX_reg }
 296 #define RMeDX { OP_REG, eDX_reg }
 297 #define RMeSP { OP_REG, eSP_reg }
 298 #define RMeBP { OP_REG, eBP_reg }
 299 #define RMeSI { OP_REG, eSI_reg }
 300 #define RMeDI { OP_REG, eDI_reg }
 301 #define RMrAX { OP_REG, rAX_reg }
 302 #define RMrBX { OP_REG, rBX_reg }
 303 #define RMrCX { OP_REG, rCX_reg }
 304 #define RMrDX { OP_REG, rDX_reg }
 305 #define RMrSP { OP_REG, rSP_reg }
 306 #define RMrBP { OP_REG, rBP_reg }
 307 #define RMrSI { OP_REG, rSI_reg }
 308 #define RMrDI { OP_REG, rDI_reg }
 309 #define RMAL { OP_REG, al_reg }
 310 #define RMCL { OP_REG, cl_reg }
 311 #define RMDL { OP_REG, dl_reg }
 312 #define RMBL { OP_REG, bl_reg }
 313 #define RMAH { OP_REG, ah_reg }
 314 #define RMCH { OP_REG, ch_reg }
 315 #define RMDH { OP_REG, dh_reg }
 316 #define RMBH { OP_REG, bh_reg }
 317 #define RMAX { OP_REG, ax_reg }
 318 #define RMDX { OP_REG, dx_reg }
 319
 320 #define eAX { OP_IMREG, eAX_reg }
 321 #define AL { OP_IMREG, al_reg }
 322 #define CL { OP_IMREG, cl_reg }
 323 #define zAX { OP_IMREG, z_mode_ax_reg }
 324 #define indirDX { OP_IMREG, indir_dx_reg }
 325
 326 #define Sw { OP_SEG, w_mode }
 327 #define Sv { OP_SEG, v_mode }
 328 #define Ap { OP_DIR, 0 }
 329 #define Ob { OP_OFF64, b_mode }
 330 #define Ov { OP_OFF64, v_mode }
 331 #define Xb { OP_DSreg, eSI_reg }
 332 #define Xv { OP_DSreg, eSI_reg }
 333 #define Xz { OP_DSreg, eSI_reg }
 334 #define Yb { OP_ESreg, eDI_reg }
 335 #define Yv { OP_ESreg, eDI_reg }
 336 #define DSBX { OP_DSreg, eBX_reg }
 337
 338 #define es { OP_REG, es_reg }
 339 #define ss { OP_REG, ss_reg }
 340 #define cs { OP_REG, cs_reg }
 341 #define ds { OP_REG, ds_reg }
 342 #define fs { OP_REG, fs_reg }
 343 #define gs { OP_REG, gs_reg }
 344
 345 #define MX { OP_MMX, 0 }
 346 #define XM { OP_XMM, 0 }
 347 #define XMScalar { OP_XMM, scalar_mode }
 348 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 349 #define XMM { OP_XMM, xmm_mode }
 350 #define TMM { OP_XMM, tmm_mode }
 351 #define XMxmmq { OP_XMM, xmmq_mode }
 352 #define EM { OP_EM, v_mode }
 353 #define EMS { OP_EM, v_swap_mode }
 354 #define EMd { OP_EM, d_mode }
 355 #define EMx { OP_EM, x_mode }
 356 #define EXbwUnit { OP_EX, bw_unit_mode }
 357 #define EXw { OP_EX, w_mode }
 358 #define EXd { OP_EX, d_mode }
 359 #define EXdS { OP_EX, d_swap_mode }
 360 #define EXq { OP_EX, q_mode }
 361 #define EXqS { OP_EX, q_swap_mode }
 362 #define EXx { OP_EX, x_mode }
 363 #define EXxS { OP_EX, x_swap_mode }
 364 #define EXxmm { OP_EX, xmm_mode }
 365 #define EXymm { OP_EX, ymm_mode }
 366 #define EXtmm { OP_EX, tmm_mode }
 367 #define EXxmmq { OP_EX, xmmq_mode }
 368 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 369 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 370 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 371 #define EXxmm_md { OP_EX, xmm_md_mode }
 372 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 373 #define EXxmmdw { OP_EX, xmmdw_mode }
 374 #define EXxmmqd { OP_EX, xmmqd_mode }
 375 #define EXymmq { OP_EX, ymmq_mode }
 376 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 377 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 378 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 379 #define MS { OP_MS, v_mode }
 380 #define XS { OP_XS, v_mode }
 381 #define EMCq { OP_EMC, q_mode }
 382 #define MXC { OP_MXC, 0 }
 383 #define OPSUF { OP_3DNowSuffix, 0 }
 384 #define SEP { SEP_Fixup, 0 }
 385 #define CMP { CMP_Fixup, 0 }
 386 #define XMM0 { XMM_Fixup, 0 }
 387 #define FXSAVE { FXSAVE_Fixup, 0 }
 388
 389 #define Vex { OP_VEX, vex_mode }
 390 #define VexW { OP_VexW, vex_mode }
 391 #define VexScalar { OP_VEX, vex_scalar_mode }
 392 #define VexScalarR { OP_VexR, vex_scalar_mode }
 393 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 394 #define VexGdq { OP_VEX, dq_mode }
 395 #define VexTmm { OP_VEX, tmm_mode }
 396 #define XMVexI4 { OP_REG_VexI4, x_mode }
 397 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
 398 #define VexI4 { OP_VexI4, 0 }
 399 #define PCLMUL { PCLMUL_Fixup, 0 }
 400 #define VPCMP { VPCMP_Fixup, 0 }
 401 #define VPCOM { VPCOM_Fixup, 0 }
 402
 403 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 404 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 405 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 406
 407 #define XMask { OP_Mask, mask_mode }
 408 #define MaskG { OP_G, mask_mode }
 409 #define MaskE { OP_E, mask_mode }
 410 #define MaskBDE { OP_E, mask_bd_mode }
 411 #define MaskVex { OP_VEX, mask_mode }
 412
 413 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 414 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 415 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 416 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 417
 418 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
 419
 420 /* Used handle "rep" prefix for string instructions.  */
 421 #define Xbr { REP_Fixup, eSI_reg }
 422 #define Xvr { REP_Fixup, eSI_reg }
 423 #define Ybr { REP_Fixup, eDI_reg }
 424 #define Yvr { REP_Fixup, eDI_reg }
 425 #define Yzr { REP_Fixup, eDI_reg }
 426 #define indirDXr { REP_Fixup, indir_dx_reg }
 427 #define ALr { REP_Fixup, al_reg }
 428 #define eAXr { REP_Fixup, eAX_reg }
 429
 430 /* Used handle HLE prefix for lockable instructions.  */
 431 #define Ebh1 { HLE_Fixup1, b_mode }
 432 #define Evh1 { HLE_Fixup1, v_mode }
 433 #define Ebh2 { HLE_Fixup2, b_mode }
 434 #define Evh2 { HLE_Fixup2, v_mode }
 435 #define Ebh3 { HLE_Fixup3, b_mode }
 436 #define Evh3 { HLE_Fixup3, v_mode }
 437
 438 #define BND { BND_Fixup, 0 }
 439 #define NOTRACK { NOTRACK_Fixup, 0 }
 440
 441 #define cond_jump_flag { NULL, cond_jump_mode }
 442 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 443
 444 /* bits in sizeflag */
 445 #define SUFFIX_ALWAYS 4
 446 #define AFLAG 2
 447 #define DFLAG 1
 448
 449 enum
 450 {
 451   /* byte operand */
 452   b_mode = 1,
 453   /* byte operand with operand swapped */
 454   b_swap_mode,
 455   /* byte operand, sign extend like 'T' suffix */
 456   b_T_mode,
 457   /* operand size depends on prefixes */
 458   v_mode,
 459   /* operand size depends on prefixes with operand swapped */
 460   v_swap_mode,
 461   /* operand size depends on address prefix */
 462   va_mode,
 463   /* word operand */
 464   w_mode,
 465   /* double word operand  */
 466   d_mode,
 467   /* double word operand with operand swapped */
 468   d_swap_mode,
 469   /* quad word operand */
 470   q_mode,
 471   /* quad word operand with operand swapped */
 472   q_swap_mode,
 473   /* ten-byte operand */
 474   t_mode,
 475   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 476      broadcast enabled.  */
 477   x_mode,
 478   /* Similar to x_mode, but with different EVEX mem shifts.  */
 479   evex_x_gscat_mode,
 480   /* Similar to x_mode, but with yet different EVEX mem shifts.  */
 481   bw_unit_mode,
 482   /* Similar to x_mode, but with disabled broadcast.  */
 483   evex_x_nobcst_mode,
 484   /* Similar to x_mode, but with operands swapped and disabled broadcast
 485      in EVEX.  */
 486   x_swap_mode,
 487   /* 16-byte XMM operand */
 488   xmm_mode,
 489   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 490      memory operand (depending on vector length).  Broadcast isn't
 491      allowed.  */
 492   xmmq_mode,
 493   /* Same as xmmq_mode, but broadcast is allowed.  */
 494   evex_half_bcst_xmmq_mode,
 495   /* XMM register or byte memory operand */
 496   xmm_mb_mode,
 497   /* XMM register or word memory operand */
 498   xmm_mw_mode,
 499   /* XMM register or double word memory operand */
 500   xmm_md_mode,
 501   /* XMM register or quad word memory operand */
 502   xmm_mq_mode,
 503   /* 16-byte XMM, word, double word or quad word operand.  */
 504   xmmdw_mode,
 505   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 506   xmmqd_mode,
 507   /* 32-byte YMM operand */
 508   ymm_mode,
 509   /* quad word, ymmword or zmmword memory operand.  */
 510   ymmq_mode,
 511   /* 32-byte YMM or 16-byte word operand */
 512   ymmxmm_mode,
 513   /* TMM operand */
 514   tmm_mode,
 515   /* d_mode in 32bit, q_mode in 64bit mode.  */
 516   m_mode,
 517   /* pair of v_mode operands */
 518   a_mode,
 519   cond_jump_mode,
 520   loop_jcxz_mode,
 521   movsxd_mode,
 522   v_bnd_mode,
 523   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 524   v_bndmk_mode,
 525   /* operand size depends on REX prefixes.  */
 526   dq_mode,
 527   /* registers like dq_mode, memory like w_mode, displacements like
 528      v_mode without considering Intel64 ISA.  */
 529   dqw_mode,
 530   /* bounds operand */
 531   bnd_mode,
 532   /* bounds operand with operand swapped */
 533   bnd_swap_mode,
 534   /* 4- or 6-byte pointer operand */
 535   f_mode,
 536   const_1_mode,
 537   /* v_mode for indirect branch opcodes.  */
 538   indir_v_mode,
 539   /* v_mode for stack-related opcodes.  */
 540   stack_v_mode,
 541   /* non-quad operand size depends on prefixes */
 542   z_mode,
 543   /* 16-byte operand */
 544   o_mode,
 545   /* registers like dq_mode, memory like b_mode.  */
 546   dqb_mode,
 547   /* registers like d_mode, memory like b_mode.  */
 548   db_mode,
 549   /* registers like d_mode, memory like w_mode.  */
 550   dw_mode,
 551   /* registers like dq_mode, memory like d_mode.  */
 552   dqd_mode,
 553   /* normal vex mode */
 554   vex_mode,
 555
 556   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 557   vex_vsib_d_w_dq_mode,
 558   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 559   vex_vsib_d_w_d_mode,
 560   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 561   vex_vsib_q_w_dq_mode,
 562   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 563   vex_vsib_q_w_d_mode,
 564   /* mandatory non-vector SIB.  */
 565   vex_sibmem_mode,
 566
 567   /* scalar, ignore vector length.  */
 568   scalar_mode,
 569   /* like vex_mode, ignore vector length.  */
 570   vex_scalar_mode,
 571   /* Operand size depends on the VEX.W bit, ignore vector length.  */
 572   vex_scalar_w_dq_mode,
 573
 574   /* Static rounding.  */
 575   evex_rounding_mode,
 576   /* Static rounding, 64-bit mode only.  */
 577   evex_rounding_64_mode,
 578   /* Supress all exceptions.  */
 579   evex_sae_mode,
 580
 581   /* Mask register operand.  */
 582   mask_mode,
 583   /* Mask register operand.  */
 584   mask_bd_mode,
 585
 586   es_reg,
 587   cs_reg,
 588   ss_reg,
 589   ds_reg,
 590   fs_reg,
 591   gs_reg,
 592
 593   eAX_reg,
 594   eCX_reg,
 595   eDX_reg,
 596   eBX_reg,
 597   eSP_reg,
 598   eBP_reg,
 599   eSI_reg,
 600   eDI_reg,
 601
 602   al_reg,
 603   cl_reg,
 604   dl_reg,
 605   bl_reg,
 606   ah_reg,
 607   ch_reg,
 608   dh_reg,
 609   bh_reg,
 610
 611   ax_reg,
 612   cx_reg,
 613   dx_reg,
 614   bx_reg,
 615   sp_reg,
 616   bp_reg,
 617   si_reg,
 618   di_reg,
 619
 620   rAX_reg,
 621   rCX_reg,
 622   rDX_reg,
 623   rBX_reg,
 624   rSP_reg,
 625   rBP_reg,
 626   rSI_reg,
 627   rDI_reg,
 628
 629   z_mode_ax_reg,
 630   indir_dx_reg
 631 };
 632
 633 enum
 634 {
 635   FLOATCODE = 1,
 636   USE_REG_TABLE,
 637   USE_MOD_TABLE,
 638   USE_RM_TABLE,
 639   USE_PREFIX_TABLE,
 640   USE_X86_64_TABLE,
 641   USE_3BYTE_TABLE,
 642   USE_XOP_8F_TABLE,
 643   USE_VEX_C4_TABLE,
 644   USE_VEX_C5_TABLE,
 645   USE_VEX_LEN_TABLE,
 646   USE_VEX_W_TABLE,
 647   USE_EVEX_TABLE,
 648   USE_EVEX_LEN_TABLE
 649 };
 650
 651 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 652
 653 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 654 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 655 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 656 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 657 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 658 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 659 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 660 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 661 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 662 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 663 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 664 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 665 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 666 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 667 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 668 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 669
 670 enum
 671 {
 672   REG_80 = 0,
 673   REG_81,
 674   REG_83,
 675   REG_8F,
 676   REG_C0,
 677   REG_C1,
 678   REG_C6,
 679   REG_C7,
 680   REG_D0,
 681   REG_D1,
 682   REG_D2,
 683   REG_D3,
 684   REG_F6,
 685   REG_F7,
 686   REG_FE,
 687   REG_FF,
 688   REG_0F00,
 689   REG_0F01,
 690   REG_0F0D,
 691   REG_0F18,
 692   REG_0F1C_P_0_MOD_0,
 693   REG_0F1E_P_1_MOD_3,
 694   REG_0F38D8_PREFIX_1,
 695   REG_0F71,
 696   REG_0F72,
 697   REG_0F73,
 698   REG_0FA6,
 699   REG_0FA7,
 700   REG_0FAE,
 701   REG_0FBA,
 702   REG_0FC7,
 703   REG_VEX_0F71,
 704   REG_VEX_0F72,
 705   REG_VEX_0F73,
 706   REG_VEX_0FAE,
 707   REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
 708   REG_VEX_0F38F3,
 709
 710   REG_0FXOP_09_01_L_0,
 711   REG_0FXOP_09_02_L_0,
 712   REG_0FXOP_09_12_M_1_L_0,
 713   REG_0FXOP_0A_12_L_0,
 714
 715   REG_EVEX_0F71,
 716   REG_EVEX_0F72,
 717   REG_EVEX_0F73,
 718   REG_EVEX_0F38C6,
 719   REG_EVEX_0F38C7
 720 };
 721
 722 enum
 723 {
 724   MOD_8D = 0,
 725   MOD_C6_REG_7,
 726   MOD_C7_REG_7,
 727   MOD_FF_REG_3,
 728   MOD_FF_REG_5,
 729   MOD_0F01_REG_0,
 730   MOD_0F01_REG_1,
 731   MOD_0F01_REG_2,
 732   MOD_0F01_REG_3,
 733   MOD_0F01_REG_5,
 734   MOD_0F01_REG_7,
 735   MOD_0F12_PREFIX_0,
 736   MOD_0F12_PREFIX_2,
 737   MOD_0F13,
 738   MOD_0F16_PREFIX_0,
 739   MOD_0F16_PREFIX_2,
 740   MOD_0F17,
 741   MOD_0F18_REG_0,
 742   MOD_0F18_REG_1,
 743   MOD_0F18_REG_2,
 744   MOD_0F18_REG_3,
 745   MOD_0F18_REG_4,
 746   MOD_0F18_REG_5,
 747   MOD_0F18_REG_6,
 748   MOD_0F18_REG_7,
 749   MOD_0F1A_PREFIX_0,
 750   MOD_0F1B_PREFIX_0,
 751   MOD_0F1B_PREFIX_1,
 752   MOD_0F1C_PREFIX_0,
 753   MOD_0F1E_PREFIX_1,
 754   MOD_0F2B_PREFIX_0,
 755   MOD_0F2B_PREFIX_1,
 756   MOD_0F2B_PREFIX_2,
 757   MOD_0F2B_PREFIX_3,
 758   MOD_0F50,
 759   MOD_0F71_REG_2,
 760   MOD_0F71_REG_4,
 761   MOD_0F71_REG_6,
 762   MOD_0F72_REG_2,
 763   MOD_0F72_REG_4,
 764   MOD_0F72_REG_6,
 765   MOD_0F73_REG_2,
 766   MOD_0F73_REG_3,
 767   MOD_0F73_REG_6,
 768   MOD_0F73_REG_7,
 769   MOD_0FAE_REG_0,
 770   MOD_0FAE_REG_1,
 771   MOD_0FAE_REG_2,
 772   MOD_0FAE_REG_3,
 773   MOD_0FAE_REG_4,
 774   MOD_0FAE_REG_5,
 775   MOD_0FAE_REG_6,
 776   MOD_0FAE_REG_7,
 777   MOD_0FB2,
 778   MOD_0FB4,
 779   MOD_0FB5,
 780   MOD_0FC3,
 781   MOD_0FC7_REG_3,
 782   MOD_0FC7_REG_4,
 783   MOD_0FC7_REG_5,
 784   MOD_0FC7_REG_6,
 785   MOD_0FC7_REG_7,
 786   MOD_0FD7,
 787   MOD_0FE7_PREFIX_2,
 788   MOD_0FF0_PREFIX_3,
 789   MOD_0F382A,
 790   MOD_VEX_0F3849_X86_64_P_0_W_0,
 791   MOD_VEX_0F3849_X86_64_P_2_W_0,
 792   MOD_VEX_0F3849_X86_64_P_3_W_0,
 793   MOD_VEX_0F384B_X86_64_P_1_W_0,
 794   MOD_VEX_0F384B_X86_64_P_2_W_0,
 795   MOD_VEX_0F384B_X86_64_P_3_W_0,
 796   MOD_VEX_0F385C_X86_64_P_1_W_0,
 797   MOD_VEX_0F385E_X86_64_P_0_W_0,
 798   MOD_VEX_0F385E_X86_64_P_1_W_0,
 799   MOD_VEX_0F385E_X86_64_P_2_W_0,
 800   MOD_VEX_0F385E_X86_64_P_3_W_0,
 801   MOD_0F38DC_PREFIX_1,
 802   MOD_0F38DD_PREFIX_1,
 803   MOD_0F38DE_PREFIX_1,
 804   MOD_0F38DF_PREFIX_1,
 805   MOD_0F38F5,
 806   MOD_0F38F6_PREFIX_0,
 807   MOD_0F38F8_PREFIX_1,
 808   MOD_0F38F8_PREFIX_2,
 809   MOD_0F38F8_PREFIX_3,
 810   MOD_0F38F9,
 811   MOD_0F38FA_PREFIX_1,
 812   MOD_0F38FB_PREFIX_1,
 813   MOD_62_32BIT,
 814   MOD_C4_32BIT,
 815   MOD_C5_32BIT,
 816   MOD_VEX_0F12_PREFIX_0,
 817   MOD_VEX_0F12_PREFIX_2,
 818   MOD_VEX_0F13,
 819   MOD_VEX_0F16_PREFIX_0,
 820   MOD_VEX_0F16_PREFIX_2,
 821   MOD_VEX_0F17,
 822   MOD_VEX_0F2B,
 823   MOD_VEX_W_0_0F41_P_0_LEN_1,
 824   MOD_VEX_W_1_0F41_P_0_LEN_1,
 825   MOD_VEX_W_0_0F41_P_2_LEN_1,
 826   MOD_VEX_W_1_0F41_P_2_LEN_1,
 827   MOD_VEX_W_0_0F42_P_0_LEN_1,
 828   MOD_VEX_W_1_0F42_P_0_LEN_1,
 829   MOD_VEX_W_0_0F42_P_2_LEN_1,
 830   MOD_VEX_W_1_0F42_P_2_LEN_1,
 831   MOD_VEX_W_0_0F44_P_0_LEN_1,
 832   MOD_VEX_W_1_0F44_P_0_LEN_1,
 833   MOD_VEX_W_0_0F44_P_2_LEN_1,
 834   MOD_VEX_W_1_0F44_P_2_LEN_1,
 835   MOD_VEX_W_0_0F45_P_0_LEN_1,
 836   MOD_VEX_W_1_0F45_P_0_LEN_1,
 837   MOD_VEX_W_0_0F45_P_2_LEN_1,
 838   MOD_VEX_W_1_0F45_P_2_LEN_1,
 839   MOD_VEX_W_0_0F46_P_0_LEN_1,
 840   MOD_VEX_W_1_0F46_P_0_LEN_1,
 841   MOD_VEX_W_0_0F46_P_2_LEN_1,
 842   MOD_VEX_W_1_0F46_P_2_LEN_1,
 843   MOD_VEX_W_0_0F47_P_0_LEN_1,
 844   MOD_VEX_W_1_0F47_P_0_LEN_1,
 845   MOD_VEX_W_0_0F47_P_2_LEN_1,
 846   MOD_VEX_W_1_0F47_P_2_LEN_1,
 847   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 848   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 849   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 850   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 851   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 852   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 853   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 854   MOD_VEX_0F50,
 855   MOD_VEX_0F71_REG_2,
 856   MOD_VEX_0F71_REG_4,
 857   MOD_VEX_0F71_REG_6,
 858   MOD_VEX_0F72_REG_2,
 859   MOD_VEX_0F72_REG_4,
 860   MOD_VEX_0F72_REG_6,
 861   MOD_VEX_0F73_REG_2,
 862   MOD_VEX_0F73_REG_3,
 863   MOD_VEX_0F73_REG_6,
 864   MOD_VEX_0F73_REG_7,
 865   MOD_VEX_W_0_0F91_P_0_LEN_0,
 866   MOD_VEX_W_1_0F91_P_0_LEN_0,
 867   MOD_VEX_W_0_0F91_P_2_LEN_0,
 868   MOD_VEX_W_1_0F91_P_2_LEN_0,
 869   MOD_VEX_W_0_0F92_P_0_LEN_0,
 870   MOD_VEX_W_0_0F92_P_2_LEN_0,
 871   MOD_VEX_0F92_P_3_LEN_0,
 872   MOD_VEX_W_0_0F93_P_0_LEN_0,
 873   MOD_VEX_W_0_0F93_P_2_LEN_0,
 874   MOD_VEX_0F93_P_3_LEN_0,
 875   MOD_VEX_W_0_0F98_P_0_LEN_0,
 876   MOD_VEX_W_1_0F98_P_0_LEN_0,
 877   MOD_VEX_W_0_0F98_P_2_LEN_0,
 878   MOD_VEX_W_1_0F98_P_2_LEN_0,
 879   MOD_VEX_W_0_0F99_P_0_LEN_0,
 880   MOD_VEX_W_1_0F99_P_0_LEN_0,
 881   MOD_VEX_W_0_0F99_P_2_LEN_0,
 882   MOD_VEX_W_1_0F99_P_2_LEN_0,
 883   MOD_VEX_0FAE_REG_2,
 884   MOD_VEX_0FAE_REG_3,
 885   MOD_VEX_0FD7,
 886   MOD_VEX_0FE7,
 887   MOD_VEX_0FF0_PREFIX_3,
 888   MOD_VEX_0F381A,
 889   MOD_VEX_0F382A,
 890   MOD_VEX_0F382C,
 891   MOD_VEX_0F382D,
 892   MOD_VEX_0F382E,
 893   MOD_VEX_0F382F,
 894   MOD_VEX_0F385A,
 895   MOD_VEX_0F388C,
 896   MOD_VEX_0F388E,
 897   MOD_VEX_0F3A30_L_0,
 898   MOD_VEX_0F3A31_L_0,
 899   MOD_VEX_0F3A32_L_0,
 900   MOD_VEX_0F3A33_L_0,
 901
 902   MOD_VEX_0FXOP_09_12,
 903
 904   MOD_EVEX_0F12_PREFIX_0,
 905   MOD_EVEX_0F12_PREFIX_2,
 906   MOD_EVEX_0F13,
 907   MOD_EVEX_0F16_PREFIX_0,
 908   MOD_EVEX_0F16_PREFIX_2,
 909   MOD_EVEX_0F17,
 910   MOD_EVEX_0F2B,
 911   MOD_EVEX_0F381A_W_0,
 912   MOD_EVEX_0F381A_W_1,
 913   MOD_EVEX_0F381B_W_0,
 914   MOD_EVEX_0F381B_W_1,
 915   MOD_EVEX_0F3828_P_1,
 916   MOD_EVEX_0F382A_P_1_W_1,
 917   MOD_EVEX_0F3838_P_1,
 918   MOD_EVEX_0F383A_P_1_W_0,
 919   MOD_EVEX_0F385A_W_0,
 920   MOD_EVEX_0F385A_W_1,
 921   MOD_EVEX_0F385B_W_0,
 922   MOD_EVEX_0F385B_W_1,
 923   MOD_EVEX_0F387A_W_0,
 924   MOD_EVEX_0F387B_W_0,
 925   MOD_EVEX_0F387C,
 926   MOD_EVEX_0F38C6_REG_1,
 927   MOD_EVEX_0F38C6_REG_2,
 928   MOD_EVEX_0F38C6_REG_5,
 929   MOD_EVEX_0F38C6_REG_6,
 930   MOD_EVEX_0F38C7_REG_1,
 931   MOD_EVEX_0F38C7_REG_2,
 932   MOD_EVEX_0F38C7_REG_5,
 933   MOD_EVEX_0F38C7_REG_6
 934 };
 935
 936 enum
 937 {
 938   RM_C6_REG_7 = 0,
 939   RM_C7_REG_7,
 940   RM_0F01_REG_0,
 941   RM_0F01_REG_1,
 942   RM_0F01_REG_2,
 943   RM_0F01_REG_3,
 944   RM_0F01_REG_5_MOD_3,
 945   RM_0F01_REG_7_MOD_3,
 946   RM_0F1E_P_1_MOD_3_REG_7,
 947   RM_0FAE_REG_6_MOD_3_P_0,
 948   RM_0FAE_REG_7_MOD_3,
 949   RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
 950 };
 951
 952 enum
 953 {
 954   PREFIX_90 = 0,
 955   PREFIX_0F01_REG_3_RM_1,
 956   PREFIX_0F01_REG_5_MOD_0,
 957   PREFIX_0F01_REG_5_MOD_3_RM_0,
 958   PREFIX_0F01_REG_5_MOD_3_RM_1,
 959   PREFIX_0F01_REG_5_MOD_3_RM_2,
 960   PREFIX_0F01_REG_7_MOD_3_RM_2,
 961   PREFIX_0F09,
 962   PREFIX_0F10,
 963   PREFIX_0F11,
 964   PREFIX_0F12,
 965   PREFIX_0F16,
 966   PREFIX_0F1A,
 967   PREFIX_0F1B,
 968   PREFIX_0F1C,
 969   PREFIX_0F1E,
 970   PREFIX_0F2A,
 971   PREFIX_0F2B,
 972   PREFIX_0F2C,
 973   PREFIX_0F2D,
 974   PREFIX_0F2E,
 975   PREFIX_0F2F,
 976   PREFIX_0F51,
 977   PREFIX_0F52,
 978   PREFIX_0F53,
 979   PREFIX_0F58,
 980   PREFIX_0F59,
 981   PREFIX_0F5A,
 982   PREFIX_0F5B,
 983   PREFIX_0F5C,
 984   PREFIX_0F5D,
 985   PREFIX_0F5E,
 986   PREFIX_0F5F,
 987   PREFIX_0F60,
 988   PREFIX_0F61,
 989   PREFIX_0F62,
 990   PREFIX_0F6F,
 991   PREFIX_0F70,
 992   PREFIX_0F78,
 993   PREFIX_0F79,
 994   PREFIX_0F7C,
 995   PREFIX_0F7D,
 996   PREFIX_0F7E,
 997   PREFIX_0F7F,
 998   PREFIX_0FAE_REG_0_MOD_3,
 999   PREFIX_0FAE_REG_1_MOD_3,
1000   PREFIX_0FAE_REG_2_MOD_3,
1001   PREFIX_0FAE_REG_3_MOD_3,
1002   PREFIX_0FAE_REG_4_MOD_0,
1003   PREFIX_0FAE_REG_4_MOD_3,
1004   PREFIX_0FAE_REG_5_MOD_3,
1005   PREFIX_0FAE_REG_6_MOD_0,
1006   PREFIX_0FAE_REG_6_MOD_3,
1007   PREFIX_0FAE_REG_7_MOD_0,
1008   PREFIX_0FB8,
1009   PREFIX_0FBC,
1010   PREFIX_0FBD,
1011   PREFIX_0FC2,
1012   PREFIX_0FC7_REG_6_MOD_0,
1013   PREFIX_0FC7_REG_6_MOD_3,
1014   PREFIX_0FC7_REG_7_MOD_3,
1015   PREFIX_0FD0,
1016   PREFIX_0FD6,
1017   PREFIX_0FE6,
1018   PREFIX_0FE7,
1019   PREFIX_0FF0,
1020   PREFIX_0FF7,
1021   PREFIX_0F38D8,
1022   PREFIX_0F38DC,
1023   PREFIX_0F38DD,
1024   PREFIX_0F38DE,
1025   PREFIX_0F38DF,
1026   PREFIX_0F38F0,
1027   PREFIX_0F38F1,
1028   PREFIX_0F38F6,
1029   PREFIX_0F38F8,
1030   PREFIX_0F38FA,
1031   PREFIX_0F38FB,
1032   PREFIX_VEX_0F10,
1033   PREFIX_VEX_0F11,
1034   PREFIX_VEX_0F12,
1035   PREFIX_VEX_0F16,
1036   PREFIX_VEX_0F2A,
1037   PREFIX_VEX_0F2C,
1038   PREFIX_VEX_0F2D,
1039   PREFIX_VEX_0F2E,
1040   PREFIX_VEX_0F2F,
1041   PREFIX_VEX_0F41,
1042   PREFIX_VEX_0F42,
1043   PREFIX_VEX_0F44,
1044   PREFIX_VEX_0F45,
1045   PREFIX_VEX_0F46,
1046   PREFIX_VEX_0F47,
1047   PREFIX_VEX_0F4A,
1048   PREFIX_VEX_0F4B,
1049   PREFIX_VEX_0F51,
1050   PREFIX_VEX_0F52,
1051   PREFIX_VEX_0F53,
1052   PREFIX_VEX_0F58,
1053   PREFIX_VEX_0F59,
1054   PREFIX_VEX_0F5A,
1055   PREFIX_VEX_0F5B,
1056   PREFIX_VEX_0F5C,
1057   PREFIX_VEX_0F5D,
1058   PREFIX_VEX_0F5E,
1059   PREFIX_VEX_0F5F,
1060   PREFIX_VEX_0F6F,
1061   PREFIX_VEX_0F70,
1062   PREFIX_VEX_0F7C,
1063   PREFIX_VEX_0F7D,
1064   PREFIX_VEX_0F7E,
1065   PREFIX_VEX_0F7F,
1066   PREFIX_VEX_0F90,
1067   PREFIX_VEX_0F91,
1068   PREFIX_VEX_0F92,
1069   PREFIX_VEX_0F93,
1070   PREFIX_VEX_0F98,
1071   PREFIX_VEX_0F99,
1072   PREFIX_VEX_0FC2,
1073   PREFIX_VEX_0FD0,
1074   PREFIX_VEX_0FE6,
1075   PREFIX_VEX_0FF0,
1076   PREFIX_VEX_0F3849_X86_64,
1077   PREFIX_VEX_0F384B_X86_64,
1078   PREFIX_VEX_0F385C_X86_64,
1079   PREFIX_VEX_0F385E_X86_64,
1080   PREFIX_VEX_0F38F5,
1081   PREFIX_VEX_0F38F6,
1082   PREFIX_VEX_0F38F7,
1083   PREFIX_VEX_0F3AF0,
1084
1085   PREFIX_EVEX_0F10,
1086   PREFIX_EVEX_0F11,
1087   PREFIX_EVEX_0F12,
1088   PREFIX_EVEX_0F16,
1089   PREFIX_EVEX_0F2A,
1090   PREFIX_EVEX_0F51,
1091   PREFIX_EVEX_0F58,
1092   PREFIX_EVEX_0F59,
1093   PREFIX_EVEX_0F5A,
1094   PREFIX_EVEX_0F5B,
1095   PREFIX_EVEX_0F5C,
1096   PREFIX_EVEX_0F5D,
1097   PREFIX_EVEX_0F5E,
1098   PREFIX_EVEX_0F5F,
1099   PREFIX_EVEX_0F6F,
1100   PREFIX_EVEX_0F70,
1101   PREFIX_EVEX_0F78,
1102   PREFIX_EVEX_0F79,
1103   PREFIX_EVEX_0F7A,
1104   PREFIX_EVEX_0F7B,
1105   PREFIX_EVEX_0F7E,
1106   PREFIX_EVEX_0F7F,
1107   PREFIX_EVEX_0FC2,
1108   PREFIX_EVEX_0FE6,
1109   PREFIX_EVEX_0F3810,
1110   PREFIX_EVEX_0F3811,
1111   PREFIX_EVEX_0F3812,
1112   PREFIX_EVEX_0F3813,
1113   PREFIX_EVEX_0F3814,
1114   PREFIX_EVEX_0F3815,
1115   PREFIX_EVEX_0F3820,
1116   PREFIX_EVEX_0F3821,
1117   PREFIX_EVEX_0F3822,
1118   PREFIX_EVEX_0F3823,
1119   PREFIX_EVEX_0F3824,
1120   PREFIX_EVEX_0F3825,
1121   PREFIX_EVEX_0F3826,
1122   PREFIX_EVEX_0F3827,
1123   PREFIX_EVEX_0F3828,
1124   PREFIX_EVEX_0F3829,
1125   PREFIX_EVEX_0F382A,
1126   PREFIX_EVEX_0F3830,
1127   PREFIX_EVEX_0F3831,
1128   PREFIX_EVEX_0F3832,
1129   PREFIX_EVEX_0F3833,
1130   PREFIX_EVEX_0F3834,
1131   PREFIX_EVEX_0F3835,
1132   PREFIX_EVEX_0F3838,
1133   PREFIX_EVEX_0F3839,
1134   PREFIX_EVEX_0F383A,
1135   PREFIX_EVEX_0F3852,
1136   PREFIX_EVEX_0F3853,
1137   PREFIX_EVEX_0F3868,
1138   PREFIX_EVEX_0F3872,
1139   PREFIX_EVEX_0F389A,
1140   PREFIX_EVEX_0F389B,
1141   PREFIX_EVEX_0F38AA,
1142   PREFIX_EVEX_0F38AB,
1143 };
1144
1145 enum
1146 {
1147   X86_64_06 = 0,
1148   X86_64_07,
1149   X86_64_0E,
1150   X86_64_16,
1151   X86_64_17,
1152   X86_64_1E,
1153   X86_64_1F,
1154   X86_64_27,
1155   X86_64_2F,
1156   X86_64_37,
1157   X86_64_3F,
1158   X86_64_60,
1159   X86_64_61,
1160   X86_64_62,
1161   X86_64_63,
1162   X86_64_6D,
1163   X86_64_6F,
1164   X86_64_82,
1165   X86_64_9A,
1166   X86_64_C2,
1167   X86_64_C3,
1168   X86_64_C4,
1169   X86_64_C5,
1170   X86_64_CE,
1171   X86_64_D4,
1172   X86_64_D5,
1173   X86_64_E8,
1174   X86_64_E9,
1175   X86_64_EA,
1176   X86_64_0F01_REG_0,
1177   X86_64_0F01_REG_1,
1178   X86_64_0F01_REG_2,
1179   X86_64_0F01_REG_3,
1180   X86_64_0F24,
1181   X86_64_0F26,
1182   X86_64_VEX_0F3849,
1183   X86_64_VEX_0F384B,
1184   X86_64_VEX_0F385C,
1185   X86_64_VEX_0F385E
1186 };
1187
1188 enum
1189 {
1190   THREE_BYTE_0F38 = 0,
1191   THREE_BYTE_0F3A
1192 };
1193
1194 enum
1195 {
1196   XOP_08 = 0,
1197   XOP_09,
1198   XOP_0A
1199 };
1200
1201 enum
1202 {
1203   VEX_0F = 0,
1204   VEX_0F38,
1205   VEX_0F3A
1206 };
1207
1208 enum
1209 {
1210   EVEX_0F = 0,
1211   EVEX_0F38,
1212   EVEX_0F3A
1213 };
1214
1215 enum
1216 {
1217   VEX_LEN_0F12_P_0_M_0 = 0,
1218   VEX_LEN_0F12_P_0_M_1,
1219 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1220   VEX_LEN_0F13_M_0,
1221   VEX_LEN_0F16_P_0_M_0,
1222   VEX_LEN_0F16_P_0_M_1,
1223 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1224   VEX_LEN_0F17_M_0,
1225   VEX_LEN_0F41_P_0,
1226   VEX_LEN_0F41_P_2,
1227   VEX_LEN_0F42_P_0,
1228   VEX_LEN_0F42_P_2,
1229   VEX_LEN_0F44_P_0,
1230   VEX_LEN_0F44_P_2,
1231   VEX_LEN_0F45_P_0,
1232   VEX_LEN_0F45_P_2,
1233   VEX_LEN_0F46_P_0,
1234   VEX_LEN_0F46_P_2,
1235   VEX_LEN_0F47_P_0,
1236   VEX_LEN_0F47_P_2,
1237   VEX_LEN_0F4A_P_0,
1238   VEX_LEN_0F4A_P_2,
1239   VEX_LEN_0F4B_P_0,
1240   VEX_LEN_0F4B_P_2,
1241   VEX_LEN_0F6E,
1242   VEX_LEN_0F77,
1243   VEX_LEN_0F7E_P_1,
1244   VEX_LEN_0F7E_P_2,
1245   VEX_LEN_0F90_P_0,
1246   VEX_LEN_0F90_P_2,
1247   VEX_LEN_0F91_P_0,
1248   VEX_LEN_0F91_P_2,
1249   VEX_LEN_0F92_P_0,
1250   VEX_LEN_0F92_P_2,
1251   VEX_LEN_0F92_P_3,
1252   VEX_LEN_0F93_P_0,
1253   VEX_LEN_0F93_P_2,
1254   VEX_LEN_0F93_P_3,
1255   VEX_LEN_0F98_P_0,
1256   VEX_LEN_0F98_P_2,
1257   VEX_LEN_0F99_P_0,
1258   VEX_LEN_0F99_P_2,
1259   VEX_LEN_0FAE_R_2_M_0,
1260   VEX_LEN_0FAE_R_3_M_0,
1261   VEX_LEN_0FC4,
1262   VEX_LEN_0FC5,
1263   VEX_LEN_0FD6,
1264   VEX_LEN_0FF7,
1265   VEX_LEN_0F3816,
1266   VEX_LEN_0F3819,
1267   VEX_LEN_0F381A_M_0,
1268   VEX_LEN_0F3836,
1269   VEX_LEN_0F3841,
1270   VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
1271   VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
1272   VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
1273   VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
1274   VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
1275   VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
1276   VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
1277   VEX_LEN_0F385A_M_0,
1278   VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
1279   VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
1280   VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
1281   VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
1282   VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
1283   VEX_LEN_0F38DB,
1284   VEX_LEN_0F38F2,
1285   VEX_LEN_0F38F3_R_1,
1286   VEX_LEN_0F38F3_R_2,
1287   VEX_LEN_0F38F3_R_3,
1288   VEX_LEN_0F38F5_P_0,
1289   VEX_LEN_0F38F5_P_1,
1290   VEX_LEN_0F38F5_P_3,
1291   VEX_LEN_0F38F6_P_3,
1292   VEX_LEN_0F38F7_P_0,
1293   VEX_LEN_0F38F7_P_1,
1294   VEX_LEN_0F38F7_P_2,
1295   VEX_LEN_0F38F7_P_3,
1296   VEX_LEN_0F3A00,
1297   VEX_LEN_0F3A01,
1298   VEX_LEN_0F3A06,
1299   VEX_LEN_0F3A14,
1300   VEX_LEN_0F3A15,
1301   VEX_LEN_0F3A16,
1302   VEX_LEN_0F3A17,
1303   VEX_LEN_0F3A18,
1304   VEX_LEN_0F3A19,
1305   VEX_LEN_0F3A20,
1306   VEX_LEN_0F3A21,
1307   VEX_LEN_0F3A22,
1308   VEX_LEN_0F3A30,
1309   VEX_LEN_0F3A31,
1310   VEX_LEN_0F3A32,
1311   VEX_LEN_0F3A33,
1312   VEX_LEN_0F3A38,
1313   VEX_LEN_0F3A39,
1314   VEX_LEN_0F3A41,
1315   VEX_LEN_0F3A46,
1316   VEX_LEN_0F3A60,
1317   VEX_LEN_0F3A61,
1318   VEX_LEN_0F3A62,
1319   VEX_LEN_0F3A63,
1320   VEX_LEN_0F3ADF,
1321   VEX_LEN_0F3AF0_P_3,
1322   VEX_LEN_0FXOP_08_85,
1323   VEX_LEN_0FXOP_08_86,
1324   VEX_LEN_0FXOP_08_87,
1325   VEX_LEN_0FXOP_08_8E,
1326   VEX_LEN_0FXOP_08_8F,
1327   VEX_LEN_0FXOP_08_95,
1328   VEX_LEN_0FXOP_08_96,
1329   VEX_LEN_0FXOP_08_97,
1330   VEX_LEN_0FXOP_08_9E,
1331   VEX_LEN_0FXOP_08_9F,
1332   VEX_LEN_0FXOP_08_A3,
1333   VEX_LEN_0FXOP_08_A6,
1334   VEX_LEN_0FXOP_08_B6,
1335   VEX_LEN_0FXOP_08_C0,
1336   VEX_LEN_0FXOP_08_C1,
1337   VEX_LEN_0FXOP_08_C2,
1338   VEX_LEN_0FXOP_08_C3,
1339   VEX_LEN_0FXOP_08_CC,
1340   VEX_LEN_0FXOP_08_CD,
1341   VEX_LEN_0FXOP_08_CE,
1342   VEX_LEN_0FXOP_08_CF,
1343   VEX_LEN_0FXOP_08_EC,
1344   VEX_LEN_0FXOP_08_ED,
1345   VEX_LEN_0FXOP_08_EE,
1346   VEX_LEN_0FXOP_08_EF,
1347   VEX_LEN_0FXOP_09_01,
1348   VEX_LEN_0FXOP_09_02,
1349   VEX_LEN_0FXOP_09_12_M_1,
1350   VEX_LEN_0FXOP_09_82_W_0,
1351   VEX_LEN_0FXOP_09_83_W_0,
1352   VEX_LEN_0FXOP_09_90,
1353   VEX_LEN_0FXOP_09_91,
1354   VEX_LEN_0FXOP_09_92,
1355   VEX_LEN_0FXOP_09_93,
1356   VEX_LEN_0FXOP_09_94,
1357   VEX_LEN_0FXOP_09_95,
1358   VEX_LEN_0FXOP_09_96,
1359   VEX_LEN_0FXOP_09_97,
1360   VEX_LEN_0FXOP_09_98,
1361   VEX_LEN_0FXOP_09_99,
1362   VEX_LEN_0FXOP_09_9A,
1363   VEX_LEN_0FXOP_09_9B,
1364   VEX_LEN_0FXOP_09_C1,
1365   VEX_LEN_0FXOP_09_C2,
1366   VEX_LEN_0FXOP_09_C3,
1367   VEX_LEN_0FXOP_09_C6,
1368   VEX_LEN_0FXOP_09_C7,
1369   VEX_LEN_0FXOP_09_CB,
1370   VEX_LEN_0FXOP_09_D1,
1371   VEX_LEN_0FXOP_09_D2,
1372   VEX_LEN_0FXOP_09_D3,
1373   VEX_LEN_0FXOP_09_D6,
1374   VEX_LEN_0FXOP_09_D7,
1375   VEX_LEN_0FXOP_09_DB,
1376   VEX_LEN_0FXOP_09_E1,
1377   VEX_LEN_0FXOP_09_E2,
1378   VEX_LEN_0FXOP_09_E3,
1379   VEX_LEN_0FXOP_0A_12,
1380 };
1381
1382 enum
1383 {
1384   EVEX_LEN_0F6E = 0,
1385   EVEX_LEN_0F7E_P_1,
1386   EVEX_LEN_0F7E_P_2,
1387   EVEX_LEN_0FC4,
1388   EVEX_LEN_0FC5,
1389   EVEX_LEN_0FD6,
1390   EVEX_LEN_0F3816,
1391   EVEX_LEN_0F3819_W_0,
1392   EVEX_LEN_0F3819_W_1,
1393   EVEX_LEN_0F381A_W_0_M_0,
1394   EVEX_LEN_0F381A_W_1_M_0,
1395   EVEX_LEN_0F381B_W_0_M_0,
1396   EVEX_LEN_0F381B_W_1_M_0,
1397   EVEX_LEN_0F3836,
1398   EVEX_LEN_0F385A_W_0_M_0,
1399   EVEX_LEN_0F385A_W_1_M_0,
1400   EVEX_LEN_0F385B_W_0_M_0,
1401   EVEX_LEN_0F385B_W_1_M_0,
1402   EVEX_LEN_0F38C6_R_1_M_0,
1403   EVEX_LEN_0F38C6_R_2_M_0,
1404   EVEX_LEN_0F38C6_R_5_M_0,
1405   EVEX_LEN_0F38C6_R_6_M_0,
1406   EVEX_LEN_0F38C7_R_1_M_0_W_0,
1407   EVEX_LEN_0F38C7_R_1_M_0_W_1,
1408   EVEX_LEN_0F38C7_R_2_M_0_W_0,
1409   EVEX_LEN_0F38C7_R_2_M_0_W_1,
1410   EVEX_LEN_0F38C7_R_5_M_0_W_0,
1411   EVEX_LEN_0F38C7_R_5_M_0_W_1,
1412   EVEX_LEN_0F38C7_R_6_M_0_W_0,
1413   EVEX_LEN_0F38C7_R_6_M_0_W_1,
1414   EVEX_LEN_0F3A00_W_1,
1415   EVEX_LEN_0F3A01_W_1,
1416   EVEX_LEN_0F3A14,
1417   EVEX_LEN_0F3A15,
1418   EVEX_LEN_0F3A16,
1419   EVEX_LEN_0F3A17,
1420   EVEX_LEN_0F3A18_W_0,
1421   EVEX_LEN_0F3A18_W_1,
1422   EVEX_LEN_0F3A19_W_0,
1423   EVEX_LEN_0F3A19_W_1,
1424   EVEX_LEN_0F3A1A_W_0,
1425   EVEX_LEN_0F3A1A_W_1,
1426   EVEX_LEN_0F3A1B_W_0,
1427   EVEX_LEN_0F3A1B_W_1,
1428   EVEX_LEN_0F3A20,
1429   EVEX_LEN_0F3A21_W_0,
1430   EVEX_LEN_0F3A22,
1431   EVEX_LEN_0F3A23_W_0,
1432   EVEX_LEN_0F3A23_W_1,
1433   EVEX_LEN_0F3A38_W_0,
1434   EVEX_LEN_0F3A38_W_1,
1435   EVEX_LEN_0F3A39_W_0,
1436   EVEX_LEN_0F3A39_W_1,
1437   EVEX_LEN_0F3A3A_W_0,
1438   EVEX_LEN_0F3A3A_W_1,
1439   EVEX_LEN_0F3A3B_W_0,
1440   EVEX_LEN_0F3A3B_W_1,
1441   EVEX_LEN_0F3A43_W_0,
1442   EVEX_LEN_0F3A43_W_1
1443 };
1444
1445 enum
1446 {
1447   VEX_W_0F41_P_0_LEN_1 = 0,
1448   VEX_W_0F41_P_2_LEN_1,
1449   VEX_W_0F42_P_0_LEN_1,
1450   VEX_W_0F42_P_2_LEN_1,
1451   VEX_W_0F44_P_0_LEN_0,
1452   VEX_W_0F44_P_2_LEN_0,
1453   VEX_W_0F45_P_0_LEN_1,
1454   VEX_W_0F45_P_2_LEN_1,
1455   VEX_W_0F46_P_0_LEN_1,
1456   VEX_W_0F46_P_2_LEN_1,
1457   VEX_W_0F47_P_0_LEN_1,
1458   VEX_W_0F47_P_2_LEN_1,
1459   VEX_W_0F4A_P_0_LEN_1,
1460   VEX_W_0F4A_P_2_LEN_1,
1461   VEX_W_0F4B_P_0_LEN_1,
1462   VEX_W_0F4B_P_2_LEN_1,
1463   VEX_W_0F90_P_0_LEN_0,
1464   VEX_W_0F90_P_2_LEN_0,
1465   VEX_W_0F91_P_0_LEN_0,
1466   VEX_W_0F91_P_2_LEN_0,
1467   VEX_W_0F92_P_0_LEN_0,
1468   VEX_W_0F92_P_2_LEN_0,
1469   VEX_W_0F93_P_0_LEN_0,
1470   VEX_W_0F93_P_2_LEN_0,
1471   VEX_W_0F98_P_0_LEN_0,
1472   VEX_W_0F98_P_2_LEN_0,
1473   VEX_W_0F99_P_0_LEN_0,
1474   VEX_W_0F99_P_2_LEN_0,
1475   VEX_W_0F380C,
1476   VEX_W_0F380D,
1477   VEX_W_0F380E,
1478   VEX_W_0F380F,
1479   VEX_W_0F3813,
1480   VEX_W_0F3816_L_1,
1481   VEX_W_0F3818,
1482   VEX_W_0F3819_L_1,
1483   VEX_W_0F381A_M_0_L_1,
1484   VEX_W_0F382C_M_0,
1485   VEX_W_0F382D_M_0,
1486   VEX_W_0F382E_M_0,
1487   VEX_W_0F382F_M_0,
1488   VEX_W_0F3836,
1489   VEX_W_0F3846,
1490   VEX_W_0F3849_X86_64_P_0,
1491   VEX_W_0F3849_X86_64_P_2,
1492   VEX_W_0F3849_X86_64_P_3,
1493   VEX_W_0F384B_X86_64_P_1,
1494   VEX_W_0F384B_X86_64_P_2,
1495   VEX_W_0F384B_X86_64_P_3,
1496   VEX_W_0F3858,
1497   VEX_W_0F3859,
1498   VEX_W_0F385A_M_0_L_0,
1499   VEX_W_0F385C_X86_64_P_1,
1500   VEX_W_0F385E_X86_64_P_0,
1501   VEX_W_0F385E_X86_64_P_1,
1502   VEX_W_0F385E_X86_64_P_2,
1503   VEX_W_0F385E_X86_64_P_3,
1504   VEX_W_0F3878,
1505   VEX_W_0F3879,
1506   VEX_W_0F38CF,
1507   VEX_W_0F3A00_L_1,
1508   VEX_W_0F3A01_L_1,
1509   VEX_W_0F3A02,
1510   VEX_W_0F3A04,
1511   VEX_W_0F3A05,
1512   VEX_W_0F3A06_L_1,
1513   VEX_W_0F3A18_L_1,
1514   VEX_W_0F3A19_L_1,
1515   VEX_W_0F3A1D,
1516   VEX_W_0F3A38_L_1,
1517   VEX_W_0F3A39_L_1,
1518   VEX_W_0F3A46_L_1,
1519   VEX_W_0F3A4A,
1520   VEX_W_0F3A4B,
1521   VEX_W_0F3A4C,
1522   VEX_W_0F3ACE,
1523   VEX_W_0F3ACF,
1524
1525   VEX_W_0FXOP_08_85_L_0,
1526   VEX_W_0FXOP_08_86_L_0,
1527   VEX_W_0FXOP_08_87_L_0,
1528   VEX_W_0FXOP_08_8E_L_0,
1529   VEX_W_0FXOP_08_8F_L_0,
1530   VEX_W_0FXOP_08_95_L_0,
1531   VEX_W_0FXOP_08_96_L_0,
1532   VEX_W_0FXOP_08_97_L_0,
1533   VEX_W_0FXOP_08_9E_L_0,
1534   VEX_W_0FXOP_08_9F_L_0,
1535   VEX_W_0FXOP_08_A6_L_0,
1536   VEX_W_0FXOP_08_B6_L_0,
1537   VEX_W_0FXOP_08_C0_L_0,
1538   VEX_W_0FXOP_08_C1_L_0,
1539   VEX_W_0FXOP_08_C2_L_0,
1540   VEX_W_0FXOP_08_C3_L_0,
1541   VEX_W_0FXOP_08_CC_L_0,
1542   VEX_W_0FXOP_08_CD_L_0,
1543   VEX_W_0FXOP_08_CE_L_0,
1544   VEX_W_0FXOP_08_CF_L_0,
1545   VEX_W_0FXOP_08_EC_L_0,
1546   VEX_W_0FXOP_08_ED_L_0,
1547   VEX_W_0FXOP_08_EE_L_0,
1548   VEX_W_0FXOP_08_EF_L_0,
1549
1550   VEX_W_0FXOP_09_80,
1551   VEX_W_0FXOP_09_81,
1552   VEX_W_0FXOP_09_82,
1553   VEX_W_0FXOP_09_83,
1554   VEX_W_0FXOP_09_C1_L_0,
1555   VEX_W_0FXOP_09_C2_L_0,
1556   VEX_W_0FXOP_09_C3_L_0,
1557   VEX_W_0FXOP_09_C6_L_0,
1558   VEX_W_0FXOP_09_C7_L_0,
1559   VEX_W_0FXOP_09_CB_L_0,
1560   VEX_W_0FXOP_09_D1_L_0,
1561   VEX_W_0FXOP_09_D2_L_0,
1562   VEX_W_0FXOP_09_D3_L_0,
1563   VEX_W_0FXOP_09_D6_L_0,
1564   VEX_W_0FXOP_09_D7_L_0,
1565   VEX_W_0FXOP_09_DB_L_0,
1566   VEX_W_0FXOP_09_E1_L_0,
1567   VEX_W_0FXOP_09_E2_L_0,
1568   VEX_W_0FXOP_09_E3_L_0,
1569
1570   EVEX_W_0F10_P_1,
1571   EVEX_W_0F10_P_3,
1572   EVEX_W_0F11_P_1,
1573   EVEX_W_0F11_P_3,
1574   EVEX_W_0F12_P_0_M_1,
1575   EVEX_W_0F12_P_1,
1576   EVEX_W_0F12_P_3,
1577   EVEX_W_0F16_P_0_M_1,
1578   EVEX_W_0F16_P_1,
1579   EVEX_W_0F2A_P_3,
1580   EVEX_W_0F51_P_1,
1581   EVEX_W_0F51_P_3,
1582   EVEX_W_0F58_P_1,
1583   EVEX_W_0F58_P_3,
1584   EVEX_W_0F59_P_1,
1585   EVEX_W_0F59_P_3,
1586   EVEX_W_0F5A_P_0,
1587   EVEX_W_0F5A_P_1,
1588   EVEX_W_0F5A_P_2,
1589   EVEX_W_0F5A_P_3,
1590   EVEX_W_0F5B_P_0,
1591   EVEX_W_0F5B_P_1,
1592   EVEX_W_0F5B_P_2,
1593   EVEX_W_0F5C_P_1,
1594   EVEX_W_0F5C_P_3,
1595   EVEX_W_0F5D_P_1,
1596   EVEX_W_0F5D_P_3,
1597   EVEX_W_0F5E_P_1,
1598   EVEX_W_0F5E_P_3,
1599   EVEX_W_0F5F_P_1,
1600   EVEX_W_0F5F_P_3,
1601   EVEX_W_0F62,
1602   EVEX_W_0F66,
1603   EVEX_W_0F6A,
1604   EVEX_W_0F6B,
1605   EVEX_W_0F6C,
1606   EVEX_W_0F6D,
1607   EVEX_W_0F6F_P_1,
1608   EVEX_W_0F6F_P_2,
1609   EVEX_W_0F6F_P_3,
1610   EVEX_W_0F70_P_2,
1611   EVEX_W_0F72_R_2,
1612   EVEX_W_0F72_R_6,
1613   EVEX_W_0F73_R_2,
1614   EVEX_W_0F73_R_6,
1615   EVEX_W_0F76,
1616   EVEX_W_0F78_P_0,
1617   EVEX_W_0F78_P_2,
1618   EVEX_W_0F79_P_0,
1619   EVEX_W_0F79_P_2,
1620   EVEX_W_0F7A_P_1,
1621   EVEX_W_0F7A_P_2,
1622   EVEX_W_0F7A_P_3,
1623   EVEX_W_0F7B_P_2,
1624   EVEX_W_0F7B_P_3,
1625   EVEX_W_0F7E_P_1,
1626   EVEX_W_0F7F_P_1,
1627   EVEX_W_0F7F_P_2,
1628   EVEX_W_0F7F_P_3,
1629   EVEX_W_0FC2_P_1,
1630   EVEX_W_0FC2_P_3,
1631   EVEX_W_0FD2,
1632   EVEX_W_0FD3,
1633   EVEX_W_0FD4,
1634   EVEX_W_0FD6_L_0,
1635   EVEX_W_0FE6_P_1,
1636   EVEX_W_0FE6_P_2,
1637   EVEX_W_0FE6_P_3,
1638   EVEX_W_0FE7,
1639   EVEX_W_0FF2,
1640   EVEX_W_0FF3,
1641   EVEX_W_0FF4,
1642   EVEX_W_0FFA,
1643   EVEX_W_0FFB,
1644   EVEX_W_0FFE,
1645   EVEX_W_0F380D,
1646   EVEX_W_0F3810_P_1,
1647   EVEX_W_0F3810_P_2,
1648   EVEX_W_0F3811_P_1,
1649   EVEX_W_0F3811_P_2,
1650   EVEX_W_0F3812_P_1,
1651   EVEX_W_0F3812_P_2,
1652   EVEX_W_0F3813_P_1,
1653   EVEX_W_0F3813_P_2,
1654   EVEX_W_0F3814_P_1,
1655   EVEX_W_0F3815_P_1,
1656   EVEX_W_0F3819,
1657   EVEX_W_0F381A,
1658   EVEX_W_0F381B,
1659   EVEX_W_0F381E,
1660   EVEX_W_0F381F,
1661   EVEX_W_0F3820_P_1,
1662   EVEX_W_0F3821_P_1,
1663   EVEX_W_0F3822_P_1,
1664   EVEX_W_0F3823_P_1,
1665   EVEX_W_0F3824_P_1,
1666   EVEX_W_0F3825_P_1,
1667   EVEX_W_0F3825_P_2,
1668   EVEX_W_0F3828_P_2,
1669   EVEX_W_0F3829_P_2,
1670   EVEX_W_0F382A_P_1,
1671   EVEX_W_0F382A_P_2,
1672   EVEX_W_0F382B,
1673   EVEX_W_0F3830_P_1,
1674   EVEX_W_0F3831_P_1,
1675   EVEX_W_0F3832_P_1,
1676   EVEX_W_0F3833_P_1,
1677   EVEX_W_0F3834_P_1,
1678   EVEX_W_0F3835_P_1,
1679   EVEX_W_0F3835_P_2,
1680   EVEX_W_0F3837,
1681   EVEX_W_0F383A_P_1,
1682   EVEX_W_0F3852_P_1,
1683   EVEX_W_0F3859,
1684   EVEX_W_0F385A,
1685   EVEX_W_0F385B,
1686   EVEX_W_0F3870,
1687   EVEX_W_0F3872_P_1,
1688   EVEX_W_0F3872_P_2,
1689   EVEX_W_0F3872_P_3,
1690   EVEX_W_0F387A,
1691   EVEX_W_0F387B,
1692   EVEX_W_0F3883,
1693   EVEX_W_0F3891,
1694   EVEX_W_0F3893,
1695   EVEX_W_0F38A1,
1696   EVEX_W_0F38A3,
1697   EVEX_W_0F38C7_R_1_M_0,
1698   EVEX_W_0F38C7_R_2_M_0,
1699   EVEX_W_0F38C7_R_5_M_0,
1700   EVEX_W_0F38C7_R_6_M_0,
1701
1702   EVEX_W_0F3A00,
1703   EVEX_W_0F3A01,
1704   EVEX_W_0F3A05,
1705   EVEX_W_0F3A08,
1706   EVEX_W_0F3A09,
1707   EVEX_W_0F3A0A,
1708   EVEX_W_0F3A0B,
1709   EVEX_W_0F3A18,
1710   EVEX_W_0F3A19,
1711   EVEX_W_0F3A1A,
1712   EVEX_W_0F3A1B,
1713   EVEX_W_0F3A21,
1714   EVEX_W_0F3A23,
1715   EVEX_W_0F3A38,
1716   EVEX_W_0F3A39,
1717   EVEX_W_0F3A3A,
1718   EVEX_W_0F3A3B,
1719   EVEX_W_0F3A42,
1720   EVEX_W_0F3A43,
1721   EVEX_W_0F3A70,
1722   EVEX_W_0F3A72,
1723 };
1724
1725 typedef void (*op_rtn) (int bytemode, int sizeflag);
1726
1727 struct dis386 {
1728   const char *name;
1729   struct
1730     {
1731       op_rtn rtn;
1732       int bytemode;
1733     } op[MAX_OPERANDS];
1734   unsigned int prefix_requirement;
1735 };
1736
1737 /* Upper case letters in the instruction names here are macros.
1738    'A' => print 'b' if no register operands or suffix_always is true
1739    'B' => print 'b' if suffix_always is true
1740    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1741           size prefix
1742    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1743           suffix_always is true
1744    'E' => print 'e' if 32-bit form of jcxz
1745    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1746    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1747    'H' => print ",pt" or ",pn" branch hint
1748    'I' unused.
1749    'J' unused.
1750    'K' => print 'd' or 'q' if rex prefix is present.
1751    'L' unused.
1752    'M' => print 'r' if intel_mnemonic is false.
1753    'N' => print 'n' if instruction has no wait "prefix"
1754    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1755    'P' => behave as 'T' except with register operand outside of suffix_always
1756           mode
1757    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1758           is true
1759    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1760    'S' => print 'w', 'l' or 'q' if suffix_always is true
1761    'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1762           prefix or if suffix_always is true.
1763    'U' unused.
1764    'V' unused.
1765    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1766    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1767    'Y' unused.
1768    'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1769    '!' => change condition from true to false or from false to true.
1770    '%' => add 1 upper case letter to the macro.
1771    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1772           prefix or suffix_always is true (lcall/ljmp).
1773    '@' => in 64bit mode for Intel64 ISA or if instruction
1774           has no operand sizing prefix, print 'q' if suffix_always is true or
1775           nothing otherwise; behave as 'P' in all other cases
1776
1777    2 upper case letter macros:
1778    "XY" => print 'x' or 'y' if suffix_always is true or no register
1779            operands and no broadcast.
1780    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1781            register operands and no broadcast.
1782    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1783    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1784            being false, or no operand at all in 64bit mode, or if suffix_always
1785            is true.
1786    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1787    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1788    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1789    "DQ" => print 'd' or 'q' depending on the VEX.W bit
1790    "BW" => print 'b' or 'w' depending on the VEX.W bit
1791    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1792            an operand size prefix, or suffix_always is true.  print
1793            'q' if rex prefix is present.
1794
1795    Many of the above letters print nothing in Intel mode.  See "putop"
1796    for the details.
1797
1798    Braces '{' and '}', and vertical bars '|', indicate alternative
1799    mnemonic strings for AT&T and Intel.  */
1800
1801 static const struct dis386 dis386[] = {
1802   /* 00 */
1803   { "addB",             { Ebh1, Gb }, 0 },
1804   { "addS",             { Evh1, Gv }, 0 },
1805   { "addB",             { Gb, EbS }, 0 },
1806   { "addS",             { Gv, EvS }, 0 },
1807   { "addB",             { AL, Ib }, 0 },
1808   { "addS",             { eAX, Iv }, 0 },
1809   { X86_64_TABLE (X86_64_06) },
1810   { X86_64_TABLE (X86_64_07) },
1811   /* 08 */
1812   { "orB",              { Ebh1, Gb }, 0 },
1813   { "orS",              { Evh1, Gv }, 0 },
1814   { "orB",              { Gb, EbS }, 0 },
1815   { "orS",              { Gv, EvS }, 0 },
1816   { "orB",              { AL, Ib }, 0 },
1817   { "orS",              { eAX, Iv }, 0 },
1818   { X86_64_TABLE (X86_64_0E) },
1819   { Bad_Opcode },       /* 0x0f extended opcode escape */
1820   /* 10 */
1821   { "adcB",             { Ebh1, Gb }, 0 },
1822   { "adcS",             { Evh1, Gv }, 0 },
1823   { "adcB",             { Gb, EbS }, 0 },
1824   { "adcS",             { Gv, EvS }, 0 },
1825   { "adcB",             { AL, Ib }, 0 },
1826   { "adcS",             { eAX, Iv }, 0 },
1827   { X86_64_TABLE (X86_64_16) },
1828   { X86_64_TABLE (X86_64_17) },
1829   /* 18 */
1830   { "sbbB",             { Ebh1, Gb }, 0 },
1831   { "sbbS",             { Evh1, Gv }, 0 },
1832   { "sbbB",             { Gb, EbS }, 0 },
1833   { "sbbS",             { Gv, EvS }, 0 },
1834   { "sbbB",             { AL, Ib }, 0 },
1835   { "sbbS",             { eAX, Iv }, 0 },
1836   { X86_64_TABLE (X86_64_1E) },
1837   { X86_64_TABLE (X86_64_1F) },
1838   /* 20 */
1839   { "andB",             { Ebh1, Gb }, 0 },
1840   { "andS",             { Evh1, Gv }, 0 },
1841   { "andB",             { Gb, EbS }, 0 },
1842   { "andS",             { Gv, EvS }, 0 },
1843   { "andB",             { AL, Ib }, 0 },
1844   { "andS",             { eAX, Iv }, 0 },
1845   { Bad_Opcode },       /* SEG ES prefix */
1846   { X86_64_TABLE (X86_64_27) },
1847   /* 28 */
1848   { "subB",             { Ebh1, Gb }, 0 },
1849   { "subS",             { Evh1, Gv }, 0 },
1850   { "subB",             { Gb, EbS }, 0 },
1851   { "subS",             { Gv, EvS }, 0 },
1852   { "subB",             { AL, Ib }, 0 },
1853   { "subS",             { eAX, Iv }, 0 },
1854   { Bad_Opcode },       /* SEG CS prefix */
1855   { X86_64_TABLE (X86_64_2F) },
1856   /* 30 */
1857   { "xorB",             { Ebh1, Gb }, 0 },
1858   { "xorS",             { Evh1, Gv }, 0 },
1859   { "xorB",             { Gb, EbS }, 0 },
1860   { "xorS",             { Gv, EvS }, 0 },
1861   { "xorB",             { AL, Ib }, 0 },
1862   { "xorS",             { eAX, Iv }, 0 },
1863   { Bad_Opcode },       /* SEG SS prefix */
1864   { X86_64_TABLE (X86_64_37) },
1865   /* 38 */
1866   { "cmpB",             { Eb, Gb }, 0 },
1867   { "cmpS",             { Ev, Gv }, 0 },
1868   { "cmpB",             { Gb, EbS }, 0 },
1869   { "cmpS",             { Gv, EvS }, 0 },
1870   { "cmpB",             { AL, Ib }, 0 },
1871   { "cmpS",             { eAX, Iv }, 0 },
1872   { Bad_Opcode },       /* SEG DS prefix */
1873   { X86_64_TABLE (X86_64_3F) },
1874   /* 40 */
1875   { "inc{S|}",          { RMeAX }, 0 },
1876   { "inc{S|}",          { RMeCX }, 0 },
1877   { "inc{S|}",          { RMeDX }, 0 },
1878   { "inc{S|}",          { RMeBX }, 0 },
1879   { "inc{S|}",          { RMeSP }, 0 },
1880   { "inc{S|}",          { RMeBP }, 0 },
1881   { "inc{S|}",          { RMeSI }, 0 },
1882   { "inc{S|}",          { RMeDI }, 0 },
1883   /* 48 */
1884   { "dec{S|}",          { RMeAX }, 0 },
1885   { "dec{S|}",          { RMeCX }, 0 },
1886   { "dec{S|}",          { RMeDX }, 0 },
1887   { "dec{S|}",          { RMeBX }, 0 },
1888   { "dec{S|}",          { RMeSP }, 0 },
1889   { "dec{S|}",          { RMeBP }, 0 },
1890   { "dec{S|}",          { RMeSI }, 0 },
1891   { "dec{S|}",          { RMeDI }, 0 },
1892   /* 50 */
1893   { "push{!P|}",                { RMrAX }, 0 },
1894   { "push{!P|}",                { RMrCX }, 0 },
1895   { "push{!P|}",                { RMrDX }, 0 },
1896   { "push{!P|}",                { RMrBX }, 0 },
1897   { "push{!P|}",                { RMrSP }, 0 },
1898   { "push{!P|}",                { RMrBP }, 0 },
1899   { "push{!P|}",                { RMrSI }, 0 },
1900   { "push{!P|}",                { RMrDI }, 0 },
1901   /* 58 */
1902   { "pop{!P|}",         { RMrAX }, 0 },
1903   { "pop{!P|}",         { RMrCX }, 0 },
1904   { "pop{!P|}",         { RMrDX }, 0 },
1905   { "pop{!P|}",         { RMrBX }, 0 },
1906   { "pop{!P|}",         { RMrSP }, 0 },
1907   { "pop{!P|}",         { RMrBP }, 0 },
1908   { "pop{!P|}",         { RMrSI }, 0 },
1909   { "pop{!P|}",         { RMrDI }, 0 },
1910   /* 60 */
1911   { X86_64_TABLE (X86_64_60) },
1912   { X86_64_TABLE (X86_64_61) },
1913   { X86_64_TABLE (X86_64_62) },
1914   { X86_64_TABLE (X86_64_63) },
1915   { Bad_Opcode },       /* seg fs */
1916   { Bad_Opcode },       /* seg gs */
1917   { Bad_Opcode },       /* op size prefix */
1918   { Bad_Opcode },       /* adr size prefix */
1919   /* 68 */
1920   { "pushP",            { sIv }, 0 },
1921   { "imulS",            { Gv, Ev, Iv }, 0 },
1922   { "pushP",            { sIbT }, 0 },
1923   { "imulS",            { Gv, Ev, sIb }, 0 },
1924   { "ins{b|}",          { Ybr, indirDX }, 0 },
1925   { X86_64_TABLE (X86_64_6D) },
1926   { "outs{b|}",         { indirDXr, Xb }, 0 },
1927   { X86_64_TABLE (X86_64_6F) },
1928   /* 70 */
1929   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
1930   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
1931   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
1932   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
1933   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
1934   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
1935   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
1936   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
1937   /* 78 */
1938   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
1939   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
1940   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
1941   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
1942   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
1943   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
1944   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
1945   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
1946   /* 80 */
1947   { REG_TABLE (REG_80) },
1948   { REG_TABLE (REG_81) },
1949   { X86_64_TABLE (X86_64_82) },
1950   { REG_TABLE (REG_83) },
1951   { "testB",            { Eb, Gb }, 0 },
1952   { "testS",            { Ev, Gv }, 0 },
1953   { "xchgB",            { Ebh2, Gb }, 0 },
1954   { "xchgS",            { Evh2, Gv }, 0 },
1955   /* 88 */
1956   { "movB",             { Ebh3, Gb }, 0 },
1957   { "movS",             { Evh3, Gv }, 0 },
1958   { "movB",             { Gb, EbS }, 0 },
1959   { "movS",             { Gv, EvS }, 0 },
1960   { "movD",             { Sv, Sw }, 0 },
1961   { MOD_TABLE (MOD_8D) },
1962   { "movD",             { Sw, Sv }, 0 },
1963   { REG_TABLE (REG_8F) },
1964   /* 90 */
1965   { PREFIX_TABLE (PREFIX_90) },
1966   { "xchgS",            { RMeCX, eAX }, 0 },
1967   { "xchgS",            { RMeDX, eAX }, 0 },
1968   { "xchgS",            { RMeBX, eAX }, 0 },
1969   { "xchgS",            { RMeSP, eAX }, 0 },
1970   { "xchgS",            { RMeBP, eAX }, 0 },
1971   { "xchgS",            { RMeSI, eAX }, 0 },
1972   { "xchgS",            { RMeDI, eAX }, 0 },
1973   /* 98 */
1974   { "cW{t|}R",          { XX }, 0 },
1975   { "cR{t|}O",          { XX }, 0 },
1976   { X86_64_TABLE (X86_64_9A) },
1977   { Bad_Opcode },       /* fwait */
1978   { "pushfP",           { XX }, 0 },
1979   { "popfP",            { XX }, 0 },
1980   { "sahf",             { XX }, 0 },
1981   { "lahf",             { XX }, 0 },
1982   /* a0 */
1983   { "mov%LB",           { AL, Ob }, 0 },
1984   { "mov%LS",           { eAX, Ov }, 0 },
1985   { "mov%LB",           { Ob, AL }, 0 },
1986   { "mov%LS",           { Ov, eAX }, 0 },
1987   { "movs{b|}",         { Ybr, Xb }, 0 },
1988   { "movs{R|}",         { Yvr, Xv }, 0 },
1989   { "cmps{b|}",         { Xb, Yb }, 0 },
1990   { "cmps{R|}",         { Xv, Yv }, 0 },
1991   /* a8 */
1992   { "testB",            { AL, Ib }, 0 },
1993   { "testS",            { eAX, Iv }, 0 },
1994   { "stosB",            { Ybr, AL }, 0 },
1995   { "stosS",            { Yvr, eAX }, 0 },
1996   { "lodsB",            { ALr, Xb }, 0 },
1997   { "lodsS",            { eAXr, Xv }, 0 },
1998   { "scasB",            { AL, Yb }, 0 },
1999   { "scasS",            { eAX, Yv }, 0 },
2000   /* b0 */
2001   { "movB",             { RMAL, Ib }, 0 },
2002   { "movB",             { RMCL, Ib }, 0 },
2003   { "movB",             { RMDL, Ib }, 0 },
2004   { "movB",             { RMBL, Ib }, 0 },
2005   { "movB",             { RMAH, Ib }, 0 },
2006   { "movB",             { RMCH, Ib }, 0 },
2007   { "movB",             { RMDH, Ib }, 0 },
2008   { "movB",             { RMBH, Ib }, 0 },
2009   /* b8 */
2010   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2011   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2012   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2013   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2014   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2015   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2016   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2017   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2018   /* c0 */
2019   { REG_TABLE (REG_C0) },
2020   { REG_TABLE (REG_C1) },
2021   { X86_64_TABLE (X86_64_C2) },
2022   { X86_64_TABLE (X86_64_C3) },
2023   { X86_64_TABLE (X86_64_C4) },
2024   { X86_64_TABLE (X86_64_C5) },
2025   { REG_TABLE (REG_C6) },
2026   { REG_TABLE (REG_C7) },
2027   /* c8 */
2028   { "enterP",           { Iw, Ib }, 0 },
2029   { "leaveP",           { XX }, 0 },
2030   { "{l|}ret{|f}%LP",   { Iw }, 0 },
2031   { "{l|}ret{|f}%LP",   { XX }, 0 },
2032   { "int3",             { XX }, 0 },
2033   { "int",              { Ib }, 0 },
2034   { X86_64_TABLE (X86_64_CE) },
2035   { "iret%LP",          { XX }, 0 },
2036   /* d0 */
2037   { REG_TABLE (REG_D0) },
2038   { REG_TABLE (REG_D1) },
2039   { REG_TABLE (REG_D2) },
2040   { REG_TABLE (REG_D3) },
2041   { X86_64_TABLE (X86_64_D4) },
2042   { X86_64_TABLE (X86_64_D5) },
2043   { Bad_Opcode },
2044   { "xlat",             { DSBX }, 0 },
2045   /* d8 */
2046   { FLOAT },
2047   { FLOAT },
2048   { FLOAT },
2049   { FLOAT },
2050   { FLOAT },
2051   { FLOAT },
2052   { FLOAT },
2053   { FLOAT },
2054   /* e0 */
2055   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2056   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2057   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2058   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2059   { "inB",              { AL, Ib }, 0 },
2060   { "inG",              { zAX, Ib }, 0 },
2061   { "outB",             { Ib, AL }, 0 },
2062   { "outG",             { Ib, zAX }, 0 },
2063   /* e8 */
2064   { X86_64_TABLE (X86_64_E8) },
2065   { X86_64_TABLE (X86_64_E9) },
2066   { X86_64_TABLE (X86_64_EA) },
2067   { "jmp",              { Jb, BND }, 0 },
2068   { "inB",              { AL, indirDX }, 0 },
2069   { "inG",              { zAX, indirDX }, 0 },
2070   { "outB",             { indirDX, AL }, 0 },
2071   { "outG",             { indirDX, zAX }, 0 },
2072   /* f0 */
2073   { Bad_Opcode },       /* lock prefix */
2074   { "icebp",            { XX }, 0 },
2075   { Bad_Opcode },       /* repne */
2076   { Bad_Opcode },       /* repz */
2077   { "hlt",              { XX }, 0 },
2078   { "cmc",              { XX }, 0 },
2079   { REG_TABLE (REG_F6) },
2080   { REG_TABLE (REG_F7) },
2081   /* f8 */
2082   { "clc",              { XX }, 0 },
2083   { "stc",              { XX }, 0 },
2084   { "cli",              { XX }, 0 },
2085   { "sti",              { XX }, 0 },
2086   { "cld",              { XX }, 0 },
2087   { "std",              { XX }, 0 },
2088   { REG_TABLE (REG_FE) },
2089   { REG_TABLE (REG_FF) },
2090 };
2091
2092 static const struct dis386 dis386_twobyte[] = {
2093   /* 00 */
2094   { REG_TABLE (REG_0F00 ) },
2095   { REG_TABLE (REG_0F01 ) },
2096   { "larS",             { Gv, Ew }, 0 },
2097   { "lslS",             { Gv, Ew }, 0 },
2098   { Bad_Opcode },
2099   { "syscall",          { XX }, 0 },
2100   { "clts",             { XX }, 0 },
2101   { "sysret%LQ",                { XX }, 0 },
2102   /* 08 */
2103   { "invd",             { XX }, 0 },
2104   { PREFIX_TABLE (PREFIX_0F09) },
2105   { Bad_Opcode },
2106   { "ud2",              { XX }, 0 },
2107   { Bad_Opcode },
2108   { REG_TABLE (REG_0F0D) },
2109   { "femms",            { XX }, 0 },
2110   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2111   /* 10 */
2112   { PREFIX_TABLE (PREFIX_0F10) },
2113   { PREFIX_TABLE (PREFIX_0F11) },
2114   { PREFIX_TABLE (PREFIX_0F12) },
2115   { MOD_TABLE (MOD_0F13) },
2116   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2117   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2118   { PREFIX_TABLE (PREFIX_0F16) },
2119   { MOD_TABLE (MOD_0F17) },
2120   /* 18 */
2121   { REG_TABLE (REG_0F18) },
2122   { "nopQ",             { Ev }, 0 },
2123   { PREFIX_TABLE (PREFIX_0F1A) },
2124   { PREFIX_TABLE (PREFIX_0F1B) },
2125   { PREFIX_TABLE (PREFIX_0F1C) },
2126   { "nopQ",             { Ev }, 0 },
2127   { PREFIX_TABLE (PREFIX_0F1E) },
2128   { "nopQ",             { Ev }, 0 },
2129   /* 20 */
2130   { "movZ",             { Em, Cm }, 0 },
2131   { "movZ",             { Em, Dm }, 0 },
2132   { "movZ",             { Cm, Em }, 0 },
2133   { "movZ",             { Dm, Em }, 0 },
2134   { X86_64_TABLE (X86_64_0F24) },
2135   { Bad_Opcode },
2136   { X86_64_TABLE (X86_64_0F26) },
2137   { Bad_Opcode },
2138   /* 28 */
2139   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2140   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2141   { PREFIX_TABLE (PREFIX_0F2A) },
2142   { PREFIX_TABLE (PREFIX_0F2B) },
2143   { PREFIX_TABLE (PREFIX_0F2C) },
2144   { PREFIX_TABLE (PREFIX_0F2D) },
2145   { PREFIX_TABLE (PREFIX_0F2E) },
2146   { PREFIX_TABLE (PREFIX_0F2F) },
2147   /* 30 */
2148   { "wrmsr",            { XX }, 0 },
2149   { "rdtsc",            { XX }, 0 },
2150   { "rdmsr",            { XX }, 0 },
2151   { "rdpmc",            { XX }, 0 },
2152   { "sysenter",         { SEP }, 0 },
2153   { "sysexit",          { SEP }, 0 },
2154   { Bad_Opcode },
2155   { "getsec",           { XX }, 0 },
2156   /* 38 */
2157   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2158   { Bad_Opcode },
2159   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2160   { Bad_Opcode },
2161   { Bad_Opcode },
2162   { Bad_Opcode },
2163   { Bad_Opcode },
2164   { Bad_Opcode },
2165   /* 40 */
2166   { "cmovoS",           { Gv, Ev }, 0 },
2167   { "cmovnoS",          { Gv, Ev }, 0 },
2168   { "cmovbS",           { Gv, Ev }, 0 },
2169   { "cmovaeS",          { Gv, Ev }, 0 },
2170   { "cmoveS",           { Gv, Ev }, 0 },
2171   { "cmovneS",          { Gv, Ev }, 0 },
2172   { "cmovbeS",          { Gv, Ev }, 0 },
2173   { "cmovaS",           { Gv, Ev }, 0 },
2174   /* 48 */
2175   { "cmovsS",           { Gv, Ev }, 0 },
2176   { "cmovnsS",          { Gv, Ev }, 0 },
2177   { "cmovpS",           { Gv, Ev }, 0 },
2178   { "cmovnpS",          { Gv, Ev }, 0 },
2179   { "cmovlS",           { Gv, Ev }, 0 },
2180   { "cmovgeS",          { Gv, Ev }, 0 },
2181   { "cmovleS",          { Gv, Ev }, 0 },
2182   { "cmovgS",           { Gv, Ev }, 0 },
2183   /* 50 */
2184   { MOD_TABLE (MOD_0F50) },
2185   { PREFIX_TABLE (PREFIX_0F51) },
2186   { PREFIX_TABLE (PREFIX_0F52) },
2187   { PREFIX_TABLE (PREFIX_0F53) },
2188   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2189   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2190   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2191   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2192   /* 58 */
2193   { PREFIX_TABLE (PREFIX_0F58) },
2194   { PREFIX_TABLE (PREFIX_0F59) },
2195   { PREFIX_TABLE (PREFIX_0F5A) },
2196   { PREFIX_TABLE (PREFIX_0F5B) },
2197   { PREFIX_TABLE (PREFIX_0F5C) },
2198   { PREFIX_TABLE (PREFIX_0F5D) },
2199   { PREFIX_TABLE (PREFIX_0F5E) },
2200   { PREFIX_TABLE (PREFIX_0F5F) },
2201   /* 60 */
2202   { PREFIX_TABLE (PREFIX_0F60) },
2203   { PREFIX_TABLE (PREFIX_0F61) },
2204   { PREFIX_TABLE (PREFIX_0F62) },
2205   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2206   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2207   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2208   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2209   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2210   /* 68 */
2211   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2212   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2213   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2214   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2215   { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2216   { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2217   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2218   { PREFIX_TABLE (PREFIX_0F6F) },
2219   /* 70 */
2220   { PREFIX_TABLE (PREFIX_0F70) },
2221   { REG_TABLE (REG_0F71) },
2222   { REG_TABLE (REG_0F72) },
2223   { REG_TABLE (REG_0F73) },
2224   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2225   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2226   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2227   { "emms",             { XX }, PREFIX_OPCODE },
2228   /* 78 */
2229   { PREFIX_TABLE (PREFIX_0F78) },
2230   { PREFIX_TABLE (PREFIX_0F79) },
2231   { Bad_Opcode },
2232   { Bad_Opcode },
2233   { PREFIX_TABLE (PREFIX_0F7C) },
2234   { PREFIX_TABLE (PREFIX_0F7D) },
2235   { PREFIX_TABLE (PREFIX_0F7E) },
2236   { PREFIX_TABLE (PREFIX_0F7F) },
2237   /* 80 */
2238   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2239   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2240   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2241   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2242   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2243   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2244   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2245   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2246   /* 88 */
2247   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2248   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2249   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2250   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2251   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2252   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2253   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2254   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2255   /* 90 */
2256   { "seto",             { Eb }, 0 },
2257   { "setno",            { Eb }, 0 },
2258   { "setb",             { Eb }, 0 },
2259   { "setae",            { Eb }, 0 },
2260   { "sete",             { Eb }, 0 },
2261   { "setne",            { Eb }, 0 },
2262   { "setbe",            { Eb }, 0 },
2263   { "seta",             { Eb }, 0 },
2264   /* 98 */
2265   { "sets",             { Eb }, 0 },
2266   { "setns",            { Eb }, 0 },
2267   { "setp",             { Eb }, 0 },
2268   { "setnp",            { Eb }, 0 },
2269   { "setl",             { Eb }, 0 },
2270   { "setge",            { Eb }, 0 },
2271   { "setle",            { Eb }, 0 },
2272   { "setg",             { Eb }, 0 },
2273   /* a0 */
2274   { "pushP",            { fs }, 0 },
2275   { "popP",             { fs }, 0 },
2276   { "cpuid",            { XX }, 0 },
2277   { "btS",              { Ev, Gv }, 0 },
2278   { "shldS",            { Ev, Gv, Ib }, 0 },
2279   { "shldS",            { Ev, Gv, CL }, 0 },
2280   { REG_TABLE (REG_0FA6) },
2281   { REG_TABLE (REG_0FA7) },
2282   /* a8 */
2283   { "pushP",            { gs }, 0 },
2284   { "popP",             { gs }, 0 },
2285   { "rsm",              { XX }, 0 },
2286   { "btsS",             { Evh1, Gv }, 0 },
2287   { "shrdS",            { Ev, Gv, Ib }, 0 },
2288   { "shrdS",            { Ev, Gv, CL }, 0 },
2289   { REG_TABLE (REG_0FAE) },
2290   { "imulS",            { Gv, Ev }, 0 },
2291   /* b0 */
2292   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2293   { "cmpxchgS",         { Evh1, Gv }, 0 },
2294   { MOD_TABLE (MOD_0FB2) },
2295   { "btrS",             { Evh1, Gv }, 0 },
2296   { MOD_TABLE (MOD_0FB4) },
2297   { MOD_TABLE (MOD_0FB5) },
2298   { "movz{bR|x}",       { Gv, Eb }, 0 },
2299   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2300   /* b8 */
2301   { PREFIX_TABLE (PREFIX_0FB8) },
2302   { "ud1S",             { Gv, Ev }, 0 },
2303   { REG_TABLE (REG_0FBA) },
2304   { "btcS",             { Evh1, Gv }, 0 },
2305   { PREFIX_TABLE (PREFIX_0FBC) },
2306   { PREFIX_TABLE (PREFIX_0FBD) },
2307   { "movs{bR|x}",       { Gv, Eb }, 0 },
2308   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2309   /* c0 */
2310   { "xaddB",            { Ebh1, Gb }, 0 },
2311   { "xaddS",            { Evh1, Gv }, 0 },
2312   { PREFIX_TABLE (PREFIX_0FC2) },
2313   { MOD_TABLE (MOD_0FC3) },
2314   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2315   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2316   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2317   { REG_TABLE (REG_0FC7) },
2318   /* c8 */
2319   { "bswap",            { RMeAX }, 0 },
2320   { "bswap",            { RMeCX }, 0 },
2321   { "bswap",            { RMeDX }, 0 },
2322   { "bswap",            { RMeBX }, 0 },
2323   { "bswap",            { RMeSP }, 0 },
2324   { "bswap",            { RMeBP }, 0 },
2325   { "bswap",            { RMeSI }, 0 },
2326   { "bswap",            { RMeDI }, 0 },
2327   /* d0 */
2328   { PREFIX_TABLE (PREFIX_0FD0) },
2329   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2330   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2331   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2332   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2333   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2334   { PREFIX_TABLE (PREFIX_0FD6) },
2335   { MOD_TABLE (MOD_0FD7) },
2336   /* d8 */
2337   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2338   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2339   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2340   { "pand",             { MX, EM }, PREFIX_OPCODE },
2341   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2342   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2343   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2344   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2345   /* e0 */
2346   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2347   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2348   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2349   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2350   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2351   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2352   { PREFIX_TABLE (PREFIX_0FE6) },
2353   { PREFIX_TABLE (PREFIX_0FE7) },
2354   /* e8 */
2355   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2356   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2357   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2358   { "por",              { MX, EM }, PREFIX_OPCODE },
2359   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2360   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2361   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2362   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2363   /* f0 */
2364   { PREFIX_TABLE (PREFIX_0FF0) },
2365   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2366   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2367   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2368   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2369   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2370   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2371   { PREFIX_TABLE (PREFIX_0FF7) },
2372   /* f8 */
2373   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2374   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2375   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2376   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2377   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2378   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2379   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2380   { "ud0S",             { Gv, Ev }, 0 },
2381 };
2382
2383 static const unsigned char onebyte_has_modrm[256] = {
2384   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2385   /*       -------------------------------        */
2386   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2387   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2388   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2389   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2390   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2391   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2392   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2393   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2394   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2395   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2396   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2397   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2398   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2399   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2400   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2401   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2402   /*       -------------------------------        */
2403   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2404 };
2405
2406 static const unsigned char twobyte_has_modrm[256] = {
2407   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2408   /*       -------------------------------        */
2409   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2410   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2411   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2412   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2413   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2414   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2415   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2416   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2417   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2418   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2419   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2420   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2421   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2422   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2423   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2424   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2425   /*       -------------------------------        */
2426   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2427 };
2428
2429 static char obuf[100];
2430 static char *obufp;
2431 static char *mnemonicendp;
2432 static char scratchbuf[100];
2433 static unsigned char *start_codep;
2434 static unsigned char *insn_codep;
2435 static unsigned char *codep;
2436 static unsigned char *end_codep;
2437 static int last_lock_prefix;
2438 static int last_repz_prefix;
2439 static int last_repnz_prefix;
2440 static int last_data_prefix;
2441 static int last_addr_prefix;
2442 static int last_rex_prefix;
2443 static int last_seg_prefix;
2444 static int fwait_prefix;
2445 /* The active segment register prefix.  */
2446 static int active_seg_prefix;
2447 #define MAX_CODE_LENGTH 15
2448 /* We can up to 14 prefixes since the maximum instruction length is
2449    15bytes.  */
2450 static int all_prefixes[MAX_CODE_LENGTH - 1];
2451 static disassemble_info *the_info;
2452 static struct
2453   {
2454     int mod;
2455     int reg;
2456     int rm;
2457   }
2458 modrm;
2459 static unsigned char need_modrm;
2460 static struct
2461   {
2462     int scale;
2463     int index;
2464     int base;
2465   }
2466 sib;
2467 static struct
2468   {
2469     int register_specifier;
2470     int length;
2471     int prefix;
2472     int w;
2473     int evex;
2474     int r;
2475     int v;
2476     int mask_register_specifier;
2477     int zeroing;
2478     int ll;
2479     int b;
2480   }
2481 vex;
2482 static unsigned char need_vex;
2483
2484 struct op
2485   {
2486     const char *name;
2487     unsigned int len;
2488   };
2489
2490 /* If we are accessing mod/rm/reg without need_modrm set, then the
2491    values are stale.  Hitting this abort likely indicates that you
2492    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2493 #define MODRM_CHECK  if (!need_modrm) abort ()
2494
2495 static const char **names64;
2496 static const char **names32;
2497 static const char **names16;
2498 static const char **names8;
2499 static const char **names8rex;
2500 static const char **names_seg;
2501 static const char *index64;
2502 static const char *index32;
2503 static const char **index16;
2504 static const char **names_bnd;
2505
2506 static const char *intel_names64[] = {
2507   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2508   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2509 };
2510 static const char *intel_names32[] = {
2511   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2512   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2513 };
2514 static const char *intel_names16[] = {
2515   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2516   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2517 };
2518 static const char *intel_names8[] = {
2519   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2520 };
2521 static const char *intel_names8rex[] = {
2522   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2523   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2524 };
2525 static const char *intel_names_seg[] = {
2526   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2527 };
2528 static const char *intel_index64 = "riz";
2529 static const char *intel_index32 = "eiz";
2530 static const char *intel_index16[] = {
2531   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2532 };
2533
2534 static const char *att_names64[] = {
2535   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2536   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2537 };
2538 static const char *att_names32[] = {
2539   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2540   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2541 };
2542 static const char *att_names16[] = {
2543   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2544   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2545 };
2546 static const char *att_names8[] = {
2547   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2548 };
2549 static const char *att_names8rex[] = {
2550   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2551   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2552 };
2553 static const char *att_names_seg[] = {
2554   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2555 };
2556 static const char *att_index64 = "%riz";
2557 static const char *att_index32 = "%eiz";
2558 static const char *att_index16[] = {
2559   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2560 };
2561
2562 static const char **names_mm;
2563 static const char *intel_names_mm[] = {
2564   "mm0", "mm1", "mm2", "mm3",
2565   "mm4", "mm5", "mm6", "mm7"
2566 };
2567 static const char *att_names_mm[] = {
2568   "%mm0", "%mm1", "%mm2", "%mm3",
2569   "%mm4", "%mm5", "%mm6", "%mm7"
2570 };
2571
2572 static const char *intel_names_bnd[] = {
2573   "bnd0", "bnd1", "bnd2", "bnd3"
2574 };
2575
2576 static const char *att_names_bnd[] = {
2577   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2578 };
2579
2580 static const char **names_xmm;
2581 static const char *intel_names_xmm[] = {
2582   "xmm0", "xmm1", "xmm2", "xmm3",
2583   "xmm4", "xmm5", "xmm6", "xmm7",
2584   "xmm8", "xmm9", "xmm10", "xmm11",
2585   "xmm12", "xmm13", "xmm14", "xmm15",
2586   "xmm16", "xmm17", "xmm18", "xmm19",
2587   "xmm20", "xmm21", "xmm22", "xmm23",
2588   "xmm24", "xmm25", "xmm26", "xmm27",
2589   "xmm28", "xmm29", "xmm30", "xmm31"
2590 };
2591 static const char *att_names_xmm[] = {
2592   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2593   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2594   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2595   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2596   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2597   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2598   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2599   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2600 };
2601
2602 static const char **names_ymm;
2603 static const char *intel_names_ymm[] = {
2604   "ymm0", "ymm1", "ymm2", "ymm3",
2605   "ymm4", "ymm5", "ymm6", "ymm7",
2606   "ymm8", "ymm9", "ymm10", "ymm11",
2607   "ymm12", "ymm13", "ymm14", "ymm15",
2608   "ymm16", "ymm17", "ymm18", "ymm19",
2609   "ymm20", "ymm21", "ymm22", "ymm23",
2610   "ymm24", "ymm25", "ymm26", "ymm27",
2611   "ymm28", "ymm29", "ymm30", "ymm31"
2612 };
2613 static const char *att_names_ymm[] = {
2614   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2615   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2616   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2617   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2618   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2619   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2620   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2621   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2622 };
2623
2624 static const char **names_zmm;
2625 static const char *intel_names_zmm[] = {
2626   "zmm0", "zmm1", "zmm2", "zmm3",
2627   "zmm4", "zmm5", "zmm6", "zmm7",
2628   "zmm8", "zmm9", "zmm10", "zmm11",
2629   "zmm12", "zmm13", "zmm14", "zmm15",
2630   "zmm16", "zmm17", "zmm18", "zmm19",
2631   "zmm20", "zmm21", "zmm22", "zmm23",
2632   "zmm24", "zmm25", "zmm26", "zmm27",
2633   "zmm28", "zmm29", "zmm30", "zmm31"
2634 };
2635 static const char *att_names_zmm[] = {
2636   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2637   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2638   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2639   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2640   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2641   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2642   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2643   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2644 };
2645
2646 static const char **names_tmm;
2647 static const char *intel_names_tmm[] = {
2648   "tmm0", "tmm1", "tmm2", "tmm3",
2649   "tmm4", "tmm5", "tmm6", "tmm7"
2650 };
2651 static const char *att_names_tmm[] = {
2652   "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2653   "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2654 };
2655
2656 static const char **names_mask;
2657 static const char *intel_names_mask[] = {
2658   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
2659 };
2660 static const char *att_names_mask[] = {
2661   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2662 };
2663
2664 static const char *names_rounding[] =
2665 {
2666   "{rn-sae}",
2667   "{rd-sae}",
2668   "{ru-sae}",
2669   "{rz-sae}"
2670 };
2671
2672 static const struct dis386 reg_table[][8] = {
2673   /* REG_80 */
2674   {
2675     { "addA",   { Ebh1, Ib }, 0 },
2676     { "orA",    { Ebh1, Ib }, 0 },
2677     { "adcA",   { Ebh1, Ib }, 0 },
2678     { "sbbA",   { Ebh1, Ib }, 0 },
2679     { "andA",   { Ebh1, Ib }, 0 },
2680     { "subA",   { Ebh1, Ib }, 0 },
2681     { "xorA",   { Ebh1, Ib }, 0 },
2682     { "cmpA",   { Eb, Ib }, 0 },
2683   },
2684   /* REG_81 */
2685   {
2686     { "addQ",   { Evh1, Iv }, 0 },
2687     { "orQ",    { Evh1, Iv }, 0 },
2688     { "adcQ",   { Evh1, Iv }, 0 },
2689     { "sbbQ",   { Evh1, Iv }, 0 },
2690     { "andQ",   { Evh1, Iv }, 0 },
2691     { "subQ",   { Evh1, Iv }, 0 },
2692     { "xorQ",   { Evh1, Iv }, 0 },
2693     { "cmpQ",   { Ev, Iv }, 0 },
2694   },
2695   /* REG_83 */
2696   {
2697     { "addQ",   { Evh1, sIb }, 0 },
2698     { "orQ",    { Evh1, sIb }, 0 },
2699     { "adcQ",   { Evh1, sIb }, 0 },
2700     { "sbbQ",   { Evh1, sIb }, 0 },
2701     { "andQ",   { Evh1, sIb }, 0 },
2702     { "subQ",   { Evh1, sIb }, 0 },
2703     { "xorQ",   { Evh1, sIb }, 0 },
2704     { "cmpQ",   { Ev, sIb }, 0 },
2705   },
2706   /* REG_8F */
2707   {
2708     { "pop{P|}", { stackEv }, 0 },
2709     { XOP_8F_TABLE (XOP_09) },
2710     { Bad_Opcode },
2711     { Bad_Opcode },
2712     { Bad_Opcode },
2713     { XOP_8F_TABLE (XOP_09) },
2714   },
2715   /* REG_C0 */
2716   {
2717     { "rolA",   { Eb, Ib }, 0 },
2718     { "rorA",   { Eb, Ib }, 0 },
2719     { "rclA",   { Eb, Ib }, 0 },
2720     { "rcrA",   { Eb, Ib }, 0 },
2721     { "shlA",   { Eb, Ib }, 0 },
2722     { "shrA",   { Eb, Ib }, 0 },
2723     { "shlA",   { Eb, Ib }, 0 },
2724     { "sarA",   { Eb, Ib }, 0 },
2725   },
2726   /* REG_C1 */
2727   {
2728     { "rolQ",   { Ev, Ib }, 0 },
2729     { "rorQ",   { Ev, Ib }, 0 },
2730     { "rclQ",   { Ev, Ib }, 0 },
2731     { "rcrQ",   { Ev, Ib }, 0 },
2732     { "shlQ",   { Ev, Ib }, 0 },
2733     { "shrQ",   { Ev, Ib }, 0 },
2734     { "shlQ",   { Ev, Ib }, 0 },
2735     { "sarQ",   { Ev, Ib }, 0 },
2736   },
2737   /* REG_C6 */
2738   {
2739     { "movA",   { Ebh3, Ib }, 0 },
2740     { Bad_Opcode },
2741     { Bad_Opcode },
2742     { Bad_Opcode },
2743     { Bad_Opcode },
2744     { Bad_Opcode },
2745     { Bad_Opcode },
2746     { MOD_TABLE (MOD_C6_REG_7) },
2747   },
2748   /* REG_C7 */
2749   {
2750     { "movQ",   { Evh3, Iv }, 0 },
2751     { Bad_Opcode },
2752     { Bad_Opcode },
2753     { Bad_Opcode },
2754     { Bad_Opcode },
2755     { Bad_Opcode },
2756     { Bad_Opcode },
2757     { MOD_TABLE (MOD_C7_REG_7) },
2758   },
2759   /* REG_D0 */
2760   {
2761     { "rolA",   { Eb, I1 }, 0 },
2762     { "rorA",   { Eb, I1 }, 0 },
2763     { "rclA",   { Eb, I1 }, 0 },
2764     { "rcrA",   { Eb, I1 }, 0 },
2765     { "shlA",   { Eb, I1 }, 0 },
2766     { "shrA",   { Eb, I1 }, 0 },
2767     { "shlA",   { Eb, I1 }, 0 },
2768     { "sarA",   { Eb, I1 }, 0 },
2769   },
2770   /* REG_D1 */
2771   {
2772     { "rolQ",   { Ev, I1 }, 0 },
2773     { "rorQ",   { Ev, I1 }, 0 },
2774     { "rclQ",   { Ev, I1 }, 0 },
2775     { "rcrQ",   { Ev, I1 }, 0 },
2776     { "shlQ",   { Ev, I1 }, 0 },
2777     { "shrQ",   { Ev, I1 }, 0 },
2778     { "shlQ",   { Ev, I1 }, 0 },
2779     { "sarQ",   { Ev, I1 }, 0 },
2780   },
2781   /* REG_D2 */
2782   {
2783     { "rolA",   { Eb, CL }, 0 },
2784     { "rorA",   { Eb, CL }, 0 },
2785     { "rclA",   { Eb, CL }, 0 },
2786     { "rcrA",   { Eb, CL }, 0 },
2787     { "shlA",   { Eb, CL }, 0 },
2788     { "shrA",   { Eb, CL }, 0 },
2789     { "shlA",   { Eb, CL }, 0 },
2790     { "sarA",   { Eb, CL }, 0 },
2791   },
2792   /* REG_D3 */
2793   {
2794     { "rolQ",   { Ev, CL }, 0 },
2795     { "rorQ",   { Ev, CL }, 0 },
2796     { "rclQ",   { Ev, CL }, 0 },
2797     { "rcrQ",   { Ev, CL }, 0 },
2798     { "shlQ",   { Ev, CL }, 0 },
2799     { "shrQ",   { Ev, CL }, 0 },
2800     { "shlQ",   { Ev, CL }, 0 },
2801     { "sarQ",   { Ev, CL }, 0 },
2802   },
2803   /* REG_F6 */
2804   {
2805     { "testA",  { Eb, Ib }, 0 },
2806     { "testA",  { Eb, Ib }, 0 },
2807     { "notA",   { Ebh1 }, 0 },
2808     { "negA",   { Ebh1 }, 0 },
2809     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
2810     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
2811     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
2812     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
2813   },
2814   /* REG_F7 */
2815   {
2816     { "testQ",  { Ev, Iv }, 0 },
2817     { "testQ",  { Ev, Iv }, 0 },
2818     { "notQ",   { Evh1 }, 0 },
2819     { "negQ",   { Evh1 }, 0 },
2820     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
2821     { "imulQ",  { Ev }, 0 },
2822     { "divQ",   { Ev }, 0 },
2823     { "idivQ",  { Ev }, 0 },
2824   },
2825   /* REG_FE */
2826   {
2827     { "incA",   { Ebh1 }, 0 },
2828     { "decA",   { Ebh1 }, 0 },
2829   },
2830   /* REG_FF */
2831   {
2832     { "incQ",   { Evh1 }, 0 },
2833     { "decQ",   { Evh1 }, 0 },
2834     { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2835     { MOD_TABLE (MOD_FF_REG_3) },
2836     { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2837     { MOD_TABLE (MOD_FF_REG_5) },
2838     { "push{P|}", { stackEv }, 0 },
2839     { Bad_Opcode },
2840   },
2841   /* REG_0F00 */
2842   {
2843     { "sldtD",  { Sv }, 0 },
2844     { "strD",   { Sv }, 0 },
2845     { "lldt",   { Ew }, 0 },
2846     { "ltr",    { Ew }, 0 },
2847     { "verr",   { Ew }, 0 },
2848     { "verw",   { Ew }, 0 },
2849     { Bad_Opcode },
2850     { Bad_Opcode },
2851   },
2852   /* REG_0F01 */
2853   {
2854     { MOD_TABLE (MOD_0F01_REG_0) },
2855     { MOD_TABLE (MOD_0F01_REG_1) },
2856     { MOD_TABLE (MOD_0F01_REG_2) },
2857     { MOD_TABLE (MOD_0F01_REG_3) },
2858     { "smswD",  { Sv }, 0 },
2859     { MOD_TABLE (MOD_0F01_REG_5) },
2860     { "lmsw",   { Ew }, 0 },
2861     { MOD_TABLE (MOD_0F01_REG_7) },
2862   },
2863   /* REG_0F0D */
2864   {
2865     { "prefetch",       { Mb }, 0 },
2866     { "prefetchw",      { Mb }, 0 },
2867     { "prefetchwt1",    { Mb }, 0 },
2868     { "prefetch",       { Mb }, 0 },
2869     { "prefetch",       { Mb }, 0 },
2870     { "prefetch",       { Mb }, 0 },
2871     { "prefetch",       { Mb }, 0 },
2872     { "prefetch",       { Mb }, 0 },
2873   },
2874   /* REG_0F18 */
2875   {
2876     { MOD_TABLE (MOD_0F18_REG_0) },
2877     { MOD_TABLE (MOD_0F18_REG_1) },
2878     { MOD_TABLE (MOD_0F18_REG_2) },
2879     { MOD_TABLE (MOD_0F18_REG_3) },
2880     { MOD_TABLE (MOD_0F18_REG_4) },
2881     { MOD_TABLE (MOD_0F18_REG_5) },
2882     { MOD_TABLE (MOD_0F18_REG_6) },
2883     { MOD_TABLE (MOD_0F18_REG_7) },
2884   },
2885   /* REG_0F1C_P_0_MOD_0 */
2886   {
2887     { "cldemote",       { Mb }, 0 },
2888     { "nopQ",           { Ev }, 0 },
2889     { "nopQ",           { Ev }, 0 },
2890     { "nopQ",           { Ev }, 0 },
2891     { "nopQ",           { Ev }, 0 },
2892     { "nopQ",           { Ev }, 0 },
2893     { "nopQ",           { Ev }, 0 },
2894     { "nopQ",           { Ev }, 0 },
2895   },
2896   /* REG_0F1E_P_1_MOD_3 */
2897   {
2898     { "nopQ",           { Ev }, 0 },
2899     { "rdsspK",         { Edq }, PREFIX_OPCODE },
2900     { "nopQ",           { Ev }, 0 },
2901     { "nopQ",           { Ev }, 0 },
2902     { "nopQ",           { Ev }, 0 },
2903     { "nopQ",           { Ev }, 0 },
2904     { "nopQ",           { Ev }, 0 },
2905     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2906   },
2907   /* REG_0F38D8_PREFIX_1 */
2908   {
2909     { "aesencwide128kl",        { M }, 0 },
2910     { "aesdecwide128kl",        { M }, 0 },
2911     { "aesencwide256kl",        { M }, 0 },
2912     { "aesdecwide256kl",        { M }, 0 },
2913   },
2914   /* REG_0F71 */
2915   {
2916     { Bad_Opcode },
2917     { Bad_Opcode },
2918     { MOD_TABLE (MOD_0F71_REG_2) },
2919     { Bad_Opcode },
2920     { MOD_TABLE (MOD_0F71_REG_4) },
2921     { Bad_Opcode },
2922     { MOD_TABLE (MOD_0F71_REG_6) },
2923   },
2924   /* REG_0F72 */
2925   {
2926     { Bad_Opcode },
2927     { Bad_Opcode },
2928     { MOD_TABLE (MOD_0F72_REG_2) },
2929     { Bad_Opcode },
2930     { MOD_TABLE (MOD_0F72_REG_4) },
2931     { Bad_Opcode },
2932     { MOD_TABLE (MOD_0F72_REG_6) },
2933   },
2934   /* REG_0F73 */
2935   {
2936     { Bad_Opcode },
2937     { Bad_Opcode },
2938     { MOD_TABLE (MOD_0F73_REG_2) },
2939     { MOD_TABLE (MOD_0F73_REG_3) },
2940     { Bad_Opcode },
2941     { Bad_Opcode },
2942     { MOD_TABLE (MOD_0F73_REG_6) },
2943     { MOD_TABLE (MOD_0F73_REG_7) },
2944   },
2945   /* REG_0FA6 */
2946   {
2947     { "montmul",        { { OP_0f07, 0 } }, 0 },
2948     { "xsha1",          { { OP_0f07, 0 } }, 0 },
2949     { "xsha256",        { { OP_0f07, 0 } }, 0 },
2950   },
2951   /* REG_0FA7 */
2952   {
2953     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
2954     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
2955     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
2956     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
2957     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
2958     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
2959   },
2960   /* REG_0FAE */
2961   {
2962     { MOD_TABLE (MOD_0FAE_REG_0) },
2963     { MOD_TABLE (MOD_0FAE_REG_1) },
2964     { MOD_TABLE (MOD_0FAE_REG_2) },
2965     { MOD_TABLE (MOD_0FAE_REG_3) },
2966     { MOD_TABLE (MOD_0FAE_REG_4) },
2967     { MOD_TABLE (MOD_0FAE_REG_5) },
2968     { MOD_TABLE (MOD_0FAE_REG_6) },
2969     { MOD_TABLE (MOD_0FAE_REG_7) },
2970   },
2971   /* REG_0FBA */
2972   {
2973     { Bad_Opcode },
2974     { Bad_Opcode },
2975     { Bad_Opcode },
2976     { Bad_Opcode },
2977     { "btQ",    { Ev, Ib }, 0 },
2978     { "btsQ",   { Evh1, Ib }, 0 },
2979     { "btrQ",   { Evh1, Ib }, 0 },
2980     { "btcQ",   { Evh1, Ib }, 0 },
2981   },
2982   /* REG_0FC7 */
2983   {
2984     { Bad_Opcode },
2985     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
2986     { Bad_Opcode },
2987     { MOD_TABLE (MOD_0FC7_REG_3) },
2988     { MOD_TABLE (MOD_0FC7_REG_4) },
2989     { MOD_TABLE (MOD_0FC7_REG_5) },
2990     { MOD_TABLE (MOD_0FC7_REG_6) },
2991     { MOD_TABLE (MOD_0FC7_REG_7) },
2992   },
2993   /* REG_VEX_0F71 */
2994   {
2995     { Bad_Opcode },
2996     { Bad_Opcode },
2997     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
2998     { Bad_Opcode },
2999     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3000     { Bad_Opcode },
3001     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3002   },
3003   /* REG_VEX_0F72 */
3004   {
3005     { Bad_Opcode },
3006     { Bad_Opcode },
3007     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3008     { Bad_Opcode },
3009     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3010     { Bad_Opcode },
3011     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3012   },
3013   /* REG_VEX_0F73 */
3014   {
3015     { Bad_Opcode },
3016     { Bad_Opcode },
3017     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3018     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3019     { Bad_Opcode },
3020     { Bad_Opcode },
3021     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3022     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3023   },
3024   /* REG_VEX_0FAE */
3025   {
3026     { Bad_Opcode },
3027     { Bad_Opcode },
3028     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3029     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3030   },
3031   /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
3032   {
3033     { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
3034   },
3035   /* REG_VEX_0F38F3 */
3036   {
3037     { Bad_Opcode },
3038     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1) },
3039     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2) },
3040     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3) },
3041   },
3042   /* REG_0FXOP_09_01_L_0 */
3043   {
3044     { Bad_Opcode },
3045     { "blcfill",        { VexGdq, Edq }, 0 },
3046     { "blsfill",        { VexGdq, Edq }, 0 },
3047     { "blcs",   { VexGdq, Edq }, 0 },
3048     { "tzmsk",  { VexGdq, Edq }, 0 },
3049     { "blcic",  { VexGdq, Edq }, 0 },
3050     { "blsic",  { VexGdq, Edq }, 0 },
3051     { "t1mskc", { VexGdq, Edq }, 0 },
3052   },
3053   /* REG_0FXOP_09_02_L_0 */
3054   {
3055     { Bad_Opcode },
3056     { "blcmsk", { VexGdq, Edq }, 0 },
3057     { Bad_Opcode },
3058     { Bad_Opcode },
3059     { Bad_Opcode },
3060     { Bad_Opcode },
3061     { "blci",   { VexGdq, Edq }, 0 },
3062   },
3063   /* REG_0FXOP_09_12_M_1_L_0 */
3064   {
3065     { "llwpcb", { Edq }, 0 },
3066     { "slwpcb", { Edq }, 0 },
3067   },
3068   /* REG_0FXOP_0A_12_L_0 */
3069   {
3070     { "lwpins", { VexGdq, Ed, Id }, 0 },
3071     { "lwpval", { VexGdq, Ed, Id }, 0 },
3072   },
3073
3074 #include "i386-dis-evex-reg.h"
3075 };
3076
3077 static const struct dis386 prefix_table[][4] = {
3078   /* PREFIX_90 */
3079   {
3080     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3081     { "pause", { XX }, 0 },
3082     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3083     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3084   },
3085
3086   /* PREFIX_0F01_REG_3_RM_1 */
3087   {
3088     { "vmmcall",        { Skip_MODRM }, 0 },
3089     { "vmgexit",        { Skip_MODRM }, 0 },
3090     { Bad_Opcode },
3091     { "vmgexit",        { Skip_MODRM }, 0 },
3092   },
3093
3094   /* PREFIX_0F01_REG_5_MOD_0 */
3095   {
3096     { Bad_Opcode },
3097     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3098   },
3099
3100   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3101   {
3102     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3103     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3104     { Bad_Opcode },
3105     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3106   },
3107
3108   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3109   {
3110     { Bad_Opcode },
3111     { Bad_Opcode },
3112     { Bad_Opcode },
3113     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3114   },
3115
3116   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3117   {
3118     { Bad_Opcode },
3119     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3120   },
3121
3122   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3123   {
3124     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3125     { "mcommit",        { Skip_MODRM }, 0 },
3126   },
3127
3128   /* PREFIX_0F09 */
3129   {
3130     { "wbinvd",   { XX }, 0 },
3131     { "wbnoinvd", { XX }, 0 },
3132   },
3133
3134   /* PREFIX_0F10 */
3135   {
3136     { "movups", { XM, EXx }, PREFIX_OPCODE },
3137     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3138     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3139     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3140   },
3141
3142   /* PREFIX_0F11 */
3143   {
3144     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3145     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3146     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3147     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3148   },
3149
3150   /* PREFIX_0F12 */
3151   {
3152     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3153     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3154     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3155     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3156   },
3157
3158   /* PREFIX_0F16 */
3159   {
3160     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3161     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3162     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3163   },
3164
3165   /* PREFIX_0F1A */
3166   {
3167     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3168     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3169     { "bndmov", { Gbnd, Ebnd }, 0 },
3170     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3171   },
3172
3173   /* PREFIX_0F1B */
3174   {
3175     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3176     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3177     { "bndmov", { EbndS, Gbnd }, 0 },
3178     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3179   },
3180
3181   /* PREFIX_0F1C */
3182   {
3183     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3184     { "nopQ",   { Ev }, PREFIX_OPCODE },
3185     { "nopQ",   { Ev }, PREFIX_OPCODE },
3186     { "nopQ",   { Ev }, PREFIX_OPCODE },
3187   },
3188
3189   /* PREFIX_0F1E */
3190   {
3191     { "nopQ",   { Ev }, PREFIX_OPCODE },
3192     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3193     { "nopQ",   { Ev }, PREFIX_OPCODE },
3194     { "nopQ",   { Ev }, PREFIX_OPCODE },
3195   },
3196
3197   /* PREFIX_0F2A */
3198   {
3199     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3200     { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3201     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3202     { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3203   },
3204
3205   /* PREFIX_0F2B */
3206   {
3207     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3208     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3209     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3210     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3211   },
3212
3213   /* PREFIX_0F2C */
3214   {
3215     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3216     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3217     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3218     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3219   },
3220
3221   /* PREFIX_0F2D */
3222   {
3223     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3224     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3225     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3226     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3227   },
3228
3229   /* PREFIX_0F2E */
3230   {
3231     { "ucomiss",{ XM, EXd }, 0 },
3232     { Bad_Opcode },
3233     { "ucomisd",{ XM, EXq }, 0 },
3234   },
3235
3236   /* PREFIX_0F2F */
3237   {
3238     { "comiss", { XM, EXd }, 0 },
3239     { Bad_Opcode },
3240     { "comisd", { XM, EXq }, 0 },
3241   },
3242
3243   /* PREFIX_0F51 */
3244   {
3245     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3246     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3247     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3248     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3249   },
3250
3251   /* PREFIX_0F52 */
3252   {
3253     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3254     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3255   },
3256
3257   /* PREFIX_0F53 */
3258   {
3259     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3260     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3261   },
3262
3263   /* PREFIX_0F58 */
3264   {
3265     { "addps", { XM, EXx }, PREFIX_OPCODE },
3266     { "addss", { XM, EXd }, PREFIX_OPCODE },
3267     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3268     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3269   },
3270
3271   /* PREFIX_0F59 */
3272   {
3273     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3274     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3275     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3276     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3277   },
3278
3279   /* PREFIX_0F5A */
3280   {
3281     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3282     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3283     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3284     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3285   },
3286
3287   /* PREFIX_0F5B */
3288   {
3289     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3290     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3291     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3292   },
3293
3294   /* PREFIX_0F5C */
3295   {
3296     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3297     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3298     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3299     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3300   },
3301
3302   /* PREFIX_0F5D */
3303   {
3304     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3305     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3306     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3307     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3308   },
3309
3310   /* PREFIX_0F5E */
3311   {
3312     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3313     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3314     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3315     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3316   },
3317
3318   /* PREFIX_0F5F */
3319   {
3320     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3321     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3322     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3323     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3324   },
3325
3326   /* PREFIX_0F60 */
3327   {
3328     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3329     { Bad_Opcode },
3330     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3331   },
3332
3333   /* PREFIX_0F61 */
3334   {
3335     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3336     { Bad_Opcode },
3337     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3338   },
3339
3340   /* PREFIX_0F62 */
3341   {
3342     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3343     { Bad_Opcode },
3344     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3345   },
3346
3347   /* PREFIX_0F6F */
3348   {
3349     { "movq",   { MX, EM }, PREFIX_OPCODE },
3350     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3351     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3352   },
3353
3354   /* PREFIX_0F70 */
3355   {
3356     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3357     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3358     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3359     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3360   },
3361
3362   /* PREFIX_0F78 */
3363   {
3364     {"vmread",  { Em, Gm }, 0 },
3365     { Bad_Opcode },
3366     {"extrq",   { XS, Ib, Ib }, 0 },
3367     {"insertq", { XM, XS, Ib, Ib }, 0 },
3368   },
3369
3370   /* PREFIX_0F79 */
3371   {
3372     {"vmwrite", { Gm, Em }, 0 },
3373     { Bad_Opcode },
3374     {"extrq",   { XM, XS }, 0 },
3375     {"insertq", { XM, XS }, 0 },
3376   },
3377
3378   /* PREFIX_0F7C */
3379   {
3380     { Bad_Opcode },
3381     { Bad_Opcode },
3382     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3383     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3384   },
3385
3386   /* PREFIX_0F7D */
3387   {
3388     { Bad_Opcode },
3389     { Bad_Opcode },
3390     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3391     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3392   },
3393
3394   /* PREFIX_0F7E */
3395   {
3396     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3397     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3398     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3399   },
3400
3401   /* PREFIX_0F7F */
3402   {
3403     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3404     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3405     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3406   },
3407
3408   /* PREFIX_0FAE_REG_0_MOD_3 */
3409   {
3410     { Bad_Opcode },
3411     { "rdfsbase", { Ev }, 0 },
3412   },
3413
3414   /* PREFIX_0FAE_REG_1_MOD_3 */
3415   {
3416     { Bad_Opcode },
3417     { "rdgsbase", { Ev }, 0 },
3418   },
3419
3420   /* PREFIX_0FAE_REG_2_MOD_3 */
3421   {
3422     { Bad_Opcode },
3423     { "wrfsbase", { Ev }, 0 },
3424   },
3425
3426   /* PREFIX_0FAE_REG_3_MOD_3 */
3427   {
3428     { Bad_Opcode },
3429     { "wrgsbase", { Ev }, 0 },
3430   },
3431
3432   /* PREFIX_0FAE_REG_4_MOD_0 */
3433   {
3434     { "xsave",  { FXSAVE }, 0 },
3435     { "ptwrite{%LQ|}", { Edq }, 0 },
3436   },
3437
3438   /* PREFIX_0FAE_REG_4_MOD_3 */
3439   {
3440     { Bad_Opcode },
3441     { "ptwrite{%LQ|}", { Edq }, 0 },
3442   },
3443
3444   /* PREFIX_0FAE_REG_5_MOD_3 */
3445   {
3446     { "lfence",         { Skip_MODRM }, 0 },
3447     { "incsspK",        { Edq }, PREFIX_OPCODE },
3448   },
3449
3450   /* PREFIX_0FAE_REG_6_MOD_0 */
3451   {
3452     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3453     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3454     { "clwb",   { Mb }, PREFIX_OPCODE },
3455   },
3456
3457   /* PREFIX_0FAE_REG_6_MOD_3 */
3458   {
3459     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3460     { "umonitor",       { Eva }, PREFIX_OPCODE },
3461     { "tpause", { Edq }, PREFIX_OPCODE },
3462     { "umwait", { Edq }, PREFIX_OPCODE },
3463   },
3464
3465   /* PREFIX_0FAE_REG_7_MOD_0 */
3466   {
3467     { "clflush",        { Mb }, 0 },
3468     { Bad_Opcode },
3469     { "clflushopt",     { Mb }, 0 },
3470   },
3471
3472   /* PREFIX_0FB8 */
3473   {
3474     { Bad_Opcode },
3475     { "popcntS", { Gv, Ev }, 0 },
3476   },
3477
3478   /* PREFIX_0FBC */
3479   {
3480     { "bsfS",   { Gv, Ev }, 0 },
3481     { "tzcntS", { Gv, Ev }, 0 },
3482     { "bsfS",   { Gv, Ev }, 0 },
3483   },
3484
3485   /* PREFIX_0FBD */
3486   {
3487     { "bsrS",   { Gv, Ev }, 0 },
3488     { "lzcntS", { Gv, Ev }, 0 },
3489     { "bsrS",   { Gv, Ev }, 0 },
3490   },
3491
3492   /* PREFIX_0FC2 */
3493   {
3494     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
3495     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
3496     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
3497     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
3498   },
3499
3500   /* PREFIX_0FC7_REG_6_MOD_0 */
3501   {
3502     { "vmptrld",{ Mq }, 0 },
3503     { "vmxon",  { Mq }, 0 },
3504     { "vmclear",{ Mq }, 0 },
3505   },
3506
3507   /* PREFIX_0FC7_REG_6_MOD_3 */
3508   {
3509     { "rdrand", { Ev }, 0 },
3510     { Bad_Opcode },
3511     { "rdrand", { Ev }, 0 }
3512   },
3513
3514   /* PREFIX_0FC7_REG_7_MOD_3 */
3515   {
3516     { "rdseed", { Ev }, 0 },
3517     { "rdpid",  { Em }, 0 },
3518     { "rdseed", { Ev }, 0 },
3519   },
3520
3521   /* PREFIX_0FD0 */
3522   {
3523     { Bad_Opcode },
3524     { Bad_Opcode },
3525     { "addsubpd", { XM, EXx }, 0 },
3526     { "addsubps", { XM, EXx }, 0 },
3527   },
3528
3529   /* PREFIX_0FD6 */
3530   {
3531     { Bad_Opcode },
3532     { "movq2dq",{ XM, MS }, 0 },
3533     { "movq",   { EXqS, XM }, 0 },
3534     { "movdq2q",{ MX, XS }, 0 },
3535   },
3536
3537   /* PREFIX_0FE6 */
3538   {
3539     { Bad_Opcode },
3540     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3541     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3542     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3543   },
3544
3545   /* PREFIX_0FE7 */
3546   {
3547     { "movntq", { Mq, MX }, PREFIX_OPCODE },
3548     { Bad_Opcode },
3549     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3550   },
3551
3552   /* PREFIX_0FF0 */
3553   {
3554     { Bad_Opcode },
3555     { Bad_Opcode },
3556     { Bad_Opcode },
3557     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3558   },
3559
3560   /* PREFIX_0FF7 */
3561   {
3562     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3563     { Bad_Opcode },
3564     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3565   },
3566
3567   /* PREFIX_0F38D8 */
3568   {
3569     { Bad_Opcode },
3570     { REG_TABLE (REG_0F38D8_PREFIX_1) },
3571   },
3572
3573   /* PREFIX_0F38DC */
3574   {
3575     { Bad_Opcode },
3576     { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3577     { "aesenc", { XM, EXx }, 0 },
3578   },
3579
3580   /* PREFIX_0F38DD */
3581   {
3582     { Bad_Opcode },
3583     { MOD_TABLE (MOD_0F38DD_PREFIX_1) },
3584     { "aesenclast", { XM, EXx }, 0 },
3585   },
3586
3587   /* PREFIX_0F38DE */
3588   {
3589     { Bad_Opcode },
3590     { MOD_TABLE (MOD_0F38DE_PREFIX_1) },
3591     { "aesdec", { XM, EXx }, 0 },
3592   },
3593
3594   /* PREFIX_0F38DF */
3595   {
3596     { Bad_Opcode },
3597     { MOD_TABLE (MOD_0F38DF_PREFIX_1) },
3598     { "aesdeclast", { XM, EXx }, 0 },
3599   },
3600
3601   /* PREFIX_0F38F0 */
3602   {
3603     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3604     { Bad_Opcode },
3605     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3606     { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3607   },
3608
3609   /* PREFIX_0F38F1 */
3610   {
3611     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3612     { Bad_Opcode },
3613     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3614     { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3615   },
3616
3617   /* PREFIX_0F38F6 */
3618   {
3619     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
3620     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
3621     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
3622     { Bad_Opcode },
3623   },
3624
3625   /* PREFIX_0F38F8 */
3626   {
3627     { Bad_Opcode },
3628     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
3629     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
3630     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
3631   },
3632   /* PREFIX_0F38FA */
3633   {
3634     { Bad_Opcode },
3635     { MOD_TABLE (MOD_0F38FA_PREFIX_1) },
3636   },
3637
3638   /* PREFIX_0F38FB */
3639   {
3640     { Bad_Opcode },
3641     { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
3642   },
3643
3644   /* PREFIX_VEX_0F10 */
3645   {
3646     { "vmovups",        { XM, EXx }, 0 },
3647     { "vmovss",         { XMScalar, VexScalarR, EXxmm_md }, 0 },
3648     { "vmovupd",        { XM, EXx }, 0 },
3649     { "vmovsd",         { XMScalar, VexScalarR, EXxmm_mq }, 0 },
3650   },
3651
3652   /* PREFIX_VEX_0F11 */
3653   {
3654     { "vmovups",        { EXxS, XM }, 0 },
3655     { "vmovss",         { EXdS, VexScalarR, XMScalar }, 0 },
3656     { "vmovupd",        { EXxS, XM }, 0 },
3657     { "vmovsd",         { EXqS, VexScalarR, XMScalar }, 0 },
3658   },
3659
3660   /* PREFIX_VEX_0F12 */
3661   {
3662     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3663     { "vmovsldup",      { XM, EXx }, 0 },
3664     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
3665     { "vmovddup",       { XM, EXymmq }, 0 },
3666   },
3667
3668   /* PREFIX_VEX_0F16 */
3669   {
3670     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3671     { "vmovshdup",      { XM, EXx }, 0 },
3672     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
3673   },
3674
3675   /* PREFIX_VEX_0F2A */
3676   {
3677     { Bad_Opcode },
3678     { "vcvtsi2ss{%LQ|}",        { XMScalar, VexScalar, Edq }, 0 },
3679     { Bad_Opcode },
3680     { "vcvtsi2sd{%LQ|}",        { XMScalar, VexScalar, Edq }, 0 },
3681   },
3682
3683   /* PREFIX_VEX_0F2C */
3684   {
3685     { Bad_Opcode },
3686     { "vcvttss2si",     { Gdq, EXxmm_md, EXxEVexS }, 0 },
3687     { Bad_Opcode },
3688     { "vcvttsd2si",     { Gdq, EXxmm_mq, EXxEVexS }, 0 },
3689   },
3690
3691   /* PREFIX_VEX_0F2D */
3692   {
3693     { Bad_Opcode },
3694     { "vcvtss2si",      { Gdq, EXxmm_md, EXxEVexR }, 0 },
3695     { Bad_Opcode },
3696     { "vcvtsd2si",      { Gdq, EXxmm_mq, EXxEVexR }, 0 },
3697   },
3698
3699   /* PREFIX_VEX_0F2E */
3700   {
3701     { "vucomisX",       { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
3702     { Bad_Opcode },
3703     { "vucomisX",       { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
3704   },
3705
3706   /* PREFIX_VEX_0F2F */
3707   {
3708     { "vcomisX",        { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
3709     { Bad_Opcode },
3710     { "vcomisX",        { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
3711   },
3712
3713   /* PREFIX_VEX_0F41 */
3714   {
3715     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
3716     { Bad_Opcode },
3717     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
3718   },
3719
3720   /* PREFIX_VEX_0F42 */
3721   {
3722     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
3723     { Bad_Opcode },
3724     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
3725   },
3726
3727   /* PREFIX_VEX_0F44 */
3728   {
3729     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
3730     { Bad_Opcode },
3731     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
3732   },
3733
3734   /* PREFIX_VEX_0F45 */
3735   {
3736     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
3737     { Bad_Opcode },
3738     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
3739   },
3740
3741   /* PREFIX_VEX_0F46 */
3742   {
3743     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
3744     { Bad_Opcode },
3745     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
3746   },
3747
3748   /* PREFIX_VEX_0F47 */
3749   {
3750     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
3751     { Bad_Opcode },
3752     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
3753   },
3754
3755   /* PREFIX_VEX_0F4A */
3756   {
3757     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
3758     { Bad_Opcode },
3759     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
3760   },
3761
3762   /* PREFIX_VEX_0F4B */
3763   {
3764     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
3765     { Bad_Opcode },
3766     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
3767   },
3768
3769   /* PREFIX_VEX_0F51 */
3770   {
3771     { "vsqrtps",        { XM, EXx }, 0 },
3772     { "vsqrtss",        { XMScalar, VexScalar, EXxmm_md }, 0 },
3773     { "vsqrtpd",        { XM, EXx }, 0 },
3774     { "vsqrtsd",        { XMScalar, VexScalar, EXxmm_mq }, 0 },
3775   },
3776
3777   /* PREFIX_VEX_0F52 */
3778   {
3779     { "vrsqrtps",       { XM, EXx }, 0 },
3780     { "vrsqrtss",       { XMScalar, VexScalar, EXxmm_md }, 0 },
3781   },
3782
3783   /* PREFIX_VEX_0F53 */
3784   {
3785     { "vrcpps",         { XM, EXx }, 0 },
3786     { "vrcpss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3787   },
3788
3789   /* PREFIX_VEX_0F58 */
3790   {
3791     { "vaddps",         { XM, Vex, EXx }, 0 },
3792     { "vaddss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3793     { "vaddpd",         { XM, Vex, EXx }, 0 },
3794     { "vaddsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3795   },
3796
3797   /* PREFIX_VEX_0F59 */
3798   {
3799     { "vmulps",         { XM, Vex, EXx }, 0 },
3800     { "vmulss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3801     { "vmulpd",         { XM, Vex, EXx }, 0 },
3802     { "vmulsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3803   },
3804
3805   /* PREFIX_VEX_0F5A */
3806   {
3807     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
3808     { "vcvtss2sd",      { XMScalar, VexScalar, EXxmm_md }, 0 },
3809     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
3810     { "vcvtsd2ss",      { XMScalar, VexScalar, EXxmm_mq }, 0 },
3811   },
3812
3813   /* PREFIX_VEX_0F5B */
3814   {
3815     { "vcvtdq2ps",      { XM, EXx }, 0 },
3816     { "vcvttps2dq",     { XM, EXx }, 0 },
3817     { "vcvtps2dq",      { XM, EXx }, 0 },
3818   },
3819
3820   /* PREFIX_VEX_0F5C */
3821   {
3822     { "vsubps",         { XM, Vex, EXx }, 0 },
3823     { "vsubss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3824     { "vsubpd",         { XM, Vex, EXx }, 0 },
3825     { "vsubsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3826   },
3827
3828   /* PREFIX_VEX_0F5D */
3829   {
3830     { "vminps",         { XM, Vex, EXx }, 0 },
3831     { "vminss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3832     { "vminpd",         { XM, Vex, EXx }, 0 },
3833     { "vminsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3834   },
3835
3836   /* PREFIX_VEX_0F5E */
3837   {
3838     { "vdivps",         { XM, Vex, EXx }, 0 },
3839     { "vdivss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3840     { "vdivpd",         { XM, Vex, EXx }, 0 },
3841     { "vdivsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3842   },
3843
3844   /* PREFIX_VEX_0F5F */
3845   {
3846     { "vmaxps",         { XM, Vex, EXx }, 0 },
3847     { "vmaxss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3848     { "vmaxpd",         { XM, Vex, EXx }, 0 },
3849     { "vmaxsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3850   },
3851
3852   /* PREFIX_VEX_0F6F */
3853   {
3854     { Bad_Opcode },
3855     { "vmovdqu",        { XM, EXx }, 0 },
3856     { "vmovdqa",        { XM, EXx }, 0 },
3857   },
3858
3859   /* PREFIX_VEX_0F70 */
3860   {
3861     { Bad_Opcode },
3862     { "vpshufhw",       { XM, EXx, Ib }, 0 },
3863     { "vpshufd",        { XM, EXx, Ib }, 0 },
3864     { "vpshuflw",       { XM, EXx, Ib }, 0 },
3865   },
3866
3867   /* PREFIX_VEX_0F7C */
3868   {
3869     { Bad_Opcode },
3870     { Bad_Opcode },
3871     { "vhaddpd",        { XM, Vex, EXx }, 0 },
3872     { "vhaddps",        { XM, Vex, EXx }, 0 },
3873   },
3874
3875   /* PREFIX_VEX_0F7D */
3876   {
3877     { Bad_Opcode },
3878     { Bad_Opcode },
3879     { "vhsubpd",        { XM, Vex, EXx }, 0 },
3880     { "vhsubps",        { XM, Vex, EXx }, 0 },
3881   },
3882
3883   /* PREFIX_VEX_0F7E */
3884   {
3885     { Bad_Opcode },
3886     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3887     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3888   },
3889
3890   /* PREFIX_VEX_0F7F */
3891   {
3892     { Bad_Opcode },
3893     { "vmovdqu",        { EXxS, XM }, 0 },
3894     { "vmovdqa",        { EXxS, XM }, 0 },
3895   },
3896
3897   /* PREFIX_VEX_0F90 */
3898   {
3899     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
3900     { Bad_Opcode },
3901     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
3902   },
3903
3904   /* PREFIX_VEX_0F91 */
3905   {
3906     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
3907     { Bad_Opcode },
3908     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
3909   },
3910
3911   /* PREFIX_VEX_0F92 */
3912   {
3913     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
3914     { Bad_Opcode },
3915     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
3916     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
3917   },
3918
3919   /* PREFIX_VEX_0F93 */
3920   {
3921     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
3922     { Bad_Opcode },
3923     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
3924     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
3925   },
3926
3927   /* PREFIX_VEX_0F98 */
3928   {
3929     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
3930     { Bad_Opcode },
3931     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
3932   },
3933
3934   /* PREFIX_VEX_0F99 */
3935   {
3936     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
3937     { Bad_Opcode },
3938     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
3939   },
3940
3941   /* PREFIX_VEX_0FC2 */
3942   {
3943     { "vcmpps",         { XM, Vex, EXx, CMP }, 0 },
3944     { "vcmpss",         { XMScalar, VexScalar, EXxmm_md, CMP }, 0 },
3945     { "vcmppd",         { XM, Vex, EXx, CMP }, 0 },
3946     { "vcmpsd",         { XMScalar, VexScalar, EXxmm_mq, CMP }, 0 },
3947   },
3948
3949   /* PREFIX_VEX_0FD0 */
3950   {
3951     { Bad_Opcode },
3952     { Bad_Opcode },
3953     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
3954     { "vaddsubps",      { XM, Vex, EXx }, 0 },
3955   },
3956
3957   /* PREFIX_VEX_0FE6 */
3958   {
3959     { Bad_Opcode },
3960     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
3961     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
3962     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
3963   },
3964
3965   /* PREFIX_VEX_0FF0 */
3966   {
3967     { Bad_Opcode },
3968     { Bad_Opcode },
3969     { Bad_Opcode },
3970     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
3971   },
3972
3973   /* PREFIX_VEX_0F3849_X86_64 */
3974   {
3975     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
3976     { Bad_Opcode },
3977     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
3978     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
3979   },
3980
3981   /* PREFIX_VEX_0F384B_X86_64 */
3982   {
3983     { Bad_Opcode },
3984     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
3985     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
3986     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
3987   },
3988
3989   /* PREFIX_VEX_0F385C_X86_64 */
3990   {
3991     { Bad_Opcode },
3992     { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
3993     { Bad_Opcode },
3994   },
3995
3996   /* PREFIX_VEX_0F385E_X86_64 */
3997   {
3998     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
3999     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
4000     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
4001     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
4002   },
4003
4004   /* PREFIX_VEX_0F38F5 */
4005   {
4006     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
4007     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
4008     { Bad_Opcode },
4009     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
4010   },
4011
4012   /* PREFIX_VEX_0F38F6 */
4013   {
4014     { Bad_Opcode },
4015     { Bad_Opcode },
4016     { Bad_Opcode },
4017     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
4018   },
4019
4020   /* PREFIX_VEX_0F38F7 */
4021   {
4022     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
4023     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
4024     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
4025     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
4026   },
4027
4028   /* PREFIX_VEX_0F3AF0 */
4029   {
4030     { Bad_Opcode },
4031     { Bad_Opcode },
4032     { Bad_Opcode },
4033     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
4034   },
4035
4036 #include "i386-dis-evex-prefix.h"
4037 };
4038
4039 static const struct dis386 x86_64_table[][2] = {
4040   /* X86_64_06 */
4041   {
4042     { "pushP", { es }, 0 },
4043   },
4044
4045   /* X86_64_07 */
4046   {
4047     { "popP", { es }, 0 },
4048   },
4049
4050   /* X86_64_0E */
4051   {
4052     { "pushP", { cs }, 0 },
4053   },
4054
4055   /* X86_64_16 */
4056   {
4057     { "pushP", { ss }, 0 },
4058   },
4059
4060   /* X86_64_17 */
4061   {
4062     { "popP", { ss }, 0 },
4063   },
4064
4065   /* X86_64_1E */
4066   {
4067     { "pushP", { ds }, 0 },
4068   },
4069
4070   /* X86_64_1F */
4071   {
4072     { "popP", { ds }, 0 },
4073   },
4074
4075   /* X86_64_27 */
4076   {
4077     { "daa", { XX }, 0 },
4078   },
4079
4080   /* X86_64_2F */
4081   {
4082     { "das", { XX }, 0 },
4083   },
4084
4085   /* X86_64_37 */
4086   {
4087     { "aaa", { XX }, 0 },
4088   },
4089
4090   /* X86_64_3F */
4091   {
4092     { "aas", { XX }, 0 },
4093   },
4094
4095   /* X86_64_60 */
4096   {
4097     { "pushaP", { XX }, 0 },
4098   },
4099
4100   /* X86_64_61 */
4101   {
4102     { "popaP", { XX }, 0 },
4103   },
4104
4105   /* X86_64_62 */
4106   {
4107     { MOD_TABLE (MOD_62_32BIT) },
4108     { EVEX_TABLE (EVEX_0F) },
4109   },
4110
4111   /* X86_64_63 */
4112   {
4113     { "arpl", { Ew, Gw }, 0 },
4114     { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4115   },
4116
4117   /* X86_64_6D */
4118   {
4119     { "ins{R|}", { Yzr, indirDX }, 0 },
4120     { "ins{G|}", { Yzr, indirDX }, 0 },
4121   },
4122
4123   /* X86_64_6F */
4124   {
4125     { "outs{R|}", { indirDXr, Xz }, 0 },
4126     { "outs{G|}", { indirDXr, Xz }, 0 },
4127   },
4128
4129   /* X86_64_82 */
4130   {
4131     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
4132     { REG_TABLE (REG_80) },
4133   },
4134
4135   /* X86_64_9A */
4136   {
4137     { "{l|}call{P|}", { Ap }, 0 },
4138   },
4139
4140   /* X86_64_C2 */
4141   {
4142     { "retP",           { Iw, BND }, 0 },
4143     { "ret@",           { Iw, BND }, 0 },
4144   },
4145
4146   /* X86_64_C3 */
4147   {
4148     { "retP",           { BND }, 0 },
4149     { "ret@",           { BND }, 0 },
4150   },
4151
4152   /* X86_64_C4 */
4153   {
4154     { MOD_TABLE (MOD_C4_32BIT) },
4155     { VEX_C4_TABLE (VEX_0F) },
4156   },
4157
4158   /* X86_64_C5 */
4159   {
4160     { MOD_TABLE (MOD_C5_32BIT) },
4161     { VEX_C5_TABLE (VEX_0F) },
4162   },
4163
4164   /* X86_64_CE */
4165   {
4166     { "into", { XX }, 0 },
4167   },
4168
4169   /* X86_64_D4 */
4170   {
4171     { "aam", { Ib }, 0 },
4172   },
4173
4174   /* X86_64_D5 */
4175   {
4176     { "aad", { Ib }, 0 },
4177   },
4178
4179   /* X86_64_E8 */
4180   {
4181     { "callP",          { Jv, BND }, 0 },
4182     { "call@",          { Jv, BND }, 0 }
4183   },
4184
4185   /* X86_64_E9 */
4186   {
4187     { "jmpP",           { Jv, BND }, 0 },
4188     { "jmp@",           { Jv, BND }, 0 }
4189   },
4190
4191   /* X86_64_EA */
4192   {
4193     { "{l|}jmp{P|}", { Ap }, 0 },
4194   },
4195
4196   /* X86_64_0F01_REG_0 */
4197   {
4198     { "sgdt{Q|Q}", { M }, 0 },
4199     { "sgdt", { M }, 0 },
4200   },
4201
4202   /* X86_64_0F01_REG_1 */
4203   {
4204     { "sidt{Q|Q}", { M }, 0 },
4205     { "sidt", { M }, 0 },
4206   },
4207
4208   /* X86_64_0F01_REG_2 */
4209   {
4210     { "lgdt{Q|Q}", { M }, 0 },
4211     { "lgdt", { M }, 0 },
4212   },
4213
4214   /* X86_64_0F01_REG_3 */
4215   {
4216     { "lidt{Q|Q}", { M }, 0 },
4217     { "lidt", { M }, 0 },
4218   },
4219
4220   {
4221     /* X86_64_0F24 */
4222     { "movZ",           { Em, Td }, 0 },
4223   },
4224
4225   {
4226     /* X86_64_0F26 */
4227     { "movZ",           { Td, Em }, 0 },
4228   },
4229
4230   /* X86_64_VEX_0F3849 */
4231   {
4232     { Bad_Opcode },
4233     { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
4234   },
4235
4236   /* X86_64_VEX_0F384B */
4237   {
4238     { Bad_Opcode },
4239     { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
4240   },
4241
4242   /* X86_64_VEX_0F385C */
4243   {
4244     { Bad_Opcode },
4245     { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
4246   },
4247
4248   /* X86_64_VEX_0F385E */
4249   {
4250     { Bad_Opcode },
4251     { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
4252   },
4253 };
4254
4255 static const struct dis386 three_byte_table[][256] = {
4256
4257   /* THREE_BYTE_0F38 */
4258   {
4259     /* 00 */
4260     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
4261     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
4262     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
4263     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
4264     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
4265     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
4266     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
4267     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
4268     /* 08 */
4269     { "psignb",         { MX, EM }, PREFIX_OPCODE },
4270     { "psignw",         { MX, EM }, PREFIX_OPCODE },
4271     { "psignd",         { MX, EM }, PREFIX_OPCODE },
4272     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
4273     { Bad_Opcode },
4274     { Bad_Opcode },
4275     { Bad_Opcode },
4276     { Bad_Opcode },
4277     /* 10 */
4278     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4279     { Bad_Opcode },
4280     { Bad_Opcode },
4281     { Bad_Opcode },
4282     { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4283     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4284     { Bad_Opcode },
4285     { "ptest",  { XM, EXx }, PREFIX_DATA },
4286     /* 18 */
4287     { Bad_Opcode },
4288     { Bad_Opcode },
4289     { Bad_Opcode },
4290     { Bad_Opcode },
4291     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
4292     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
4293     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
4294     { Bad_Opcode },
4295     /* 20 */
4296     { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4297     { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4298     { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4299     { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4300     { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4301     { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4302     { Bad_Opcode },
4303     { Bad_Opcode },
4304     /* 28 */
4305     { "pmuldq", { XM, EXx }, PREFIX_DATA },
4306     { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4307     { MOD_TABLE (MOD_0F382A) },
4308     { "packusdw", { XM, EXx }, PREFIX_DATA },
4309     { Bad_Opcode },
4310     { Bad_Opcode },
4311     { Bad_Opcode },
4312     { Bad_Opcode },
4313     /* 30 */
4314     { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4315     { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4316     { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4317     { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4318     { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4319     { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4320     { Bad_Opcode },
4321     { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4322     /* 38 */
4323     { "pminsb", { XM, EXx }, PREFIX_DATA },
4324     { "pminsd", { XM, EXx }, PREFIX_DATA },
4325     { "pminuw", { XM, EXx }, PREFIX_DATA },
4326     { "pminud", { XM, EXx }, PREFIX_DATA },
4327     { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4328     { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4329     { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4330     { "pmaxud", { XM, EXx }, PREFIX_DATA },
4331     /* 40 */
4332     { "pmulld", { XM, EXx }, PREFIX_DATA },
4333     { "phminposuw", { XM, EXx }, PREFIX_DATA },
4334     { Bad_Opcode },
4335     { Bad_Opcode },
4336     { Bad_Opcode },
4337     { Bad_Opcode },
4338     { Bad_Opcode },
4339     { Bad_Opcode },
4340     /* 48 */
4341     { Bad_Opcode },
4342     { Bad_Opcode },
4343     { Bad_Opcode },
4344     { Bad_Opcode },
4345     { Bad_Opcode },
4346     { Bad_Opcode },
4347     { Bad_Opcode },
4348     { Bad_Opcode },
4349     /* 50 */
4350     { Bad_Opcode },
4351     { Bad_Opcode },
4352     { Bad_Opcode },
4353     { Bad_Opcode },
4354     { Bad_Opcode },
4355     { Bad_Opcode },
4356     { Bad_Opcode },
4357     { Bad_Opcode },
4358     /* 58 */
4359     { Bad_Opcode },
4360     { Bad_Opcode },
4361     { Bad_Opcode },
4362     { Bad_Opcode },
4363     { Bad_Opcode },
4364     { Bad_Opcode },
4365     { Bad_Opcode },
4366     { Bad_Opcode },
4367     /* 60 */
4368     { Bad_Opcode },
4369     { Bad_Opcode },
4370     { Bad_Opcode },
4371     { Bad_Opcode },
4372     { Bad_Opcode },
4373     { Bad_Opcode },
4374     { Bad_Opcode },
4375     { Bad_Opcode },
4376     /* 68 */
4377     { Bad_Opcode },
4378     { Bad_Opcode },
4379     { Bad_Opcode },
4380     { Bad_Opcode },
4381     { Bad_Opcode },
4382     { Bad_Opcode },
4383     { Bad_Opcode },
4384     { Bad_Opcode },
4385     /* 70 */
4386     { Bad_Opcode },
4387     { Bad_Opcode },
4388     { Bad_Opcode },
4389     { Bad_Opcode },
4390     { Bad_Opcode },
4391     { Bad_Opcode },
4392     { Bad_Opcode },
4393     { Bad_Opcode },
4394     /* 78 */
4395     { Bad_Opcode },
4396     { Bad_Opcode },
4397     { Bad_Opcode },
4398     { Bad_Opcode },
4399     { Bad_Opcode },
4400     { Bad_Opcode },
4401     { Bad_Opcode },
4402     { Bad_Opcode },
4403     /* 80 */
4404     { "invept", { Gm, Mo }, PREFIX_DATA },
4405     { "invvpid", { Gm, Mo }, PREFIX_DATA },
4406     { "invpcid", { Gm, M }, PREFIX_DATA },
4407     { Bad_Opcode },
4408     { Bad_Opcode },
4409     { Bad_Opcode },
4410     { Bad_Opcode },
4411     { Bad_Opcode },
4412     /* 88 */
4413     { Bad_Opcode },
4414     { Bad_Opcode },
4415     { Bad_Opcode },
4416     { Bad_Opcode },
4417     { Bad_Opcode },
4418     { Bad_Opcode },
4419     { Bad_Opcode },
4420     { Bad_Opcode },
4421     /* 90 */
4422     { Bad_Opcode },
4423     { Bad_Opcode },
4424     { Bad_Opcode },
4425     { Bad_Opcode },
4426     { Bad_Opcode },
4427     { Bad_Opcode },
4428     { Bad_Opcode },
4429     { Bad_Opcode },
4430     /* 98 */
4431     { Bad_Opcode },
4432     { Bad_Opcode },
4433     { Bad_Opcode },
4434     { Bad_Opcode },
4435     { Bad_Opcode },
4436     { Bad_Opcode },
4437     { Bad_Opcode },
4438     { Bad_Opcode },
4439     /* a0 */
4440     { Bad_Opcode },
4441     { Bad_Opcode },
4442     { Bad_Opcode },
4443     { Bad_Opcode },
4444     { Bad_Opcode },
4445     { Bad_Opcode },
4446     { Bad_Opcode },
4447     { Bad_Opcode },
4448     /* a8 */
4449     { Bad_Opcode },
4450     { Bad_Opcode },
4451     { Bad_Opcode },
4452     { Bad_Opcode },
4453     { Bad_Opcode },
4454     { Bad_Opcode },
4455     { Bad_Opcode },
4456     { Bad_Opcode },
4457     /* b0 */
4458     { Bad_Opcode },
4459     { Bad_Opcode },
4460     { Bad_Opcode },
4461     { Bad_Opcode },
4462     { Bad_Opcode },
4463     { Bad_Opcode },
4464     { Bad_Opcode },
4465     { Bad_Opcode },
4466     /* b8 */
4467     { Bad_Opcode },
4468     { Bad_Opcode },
4469     { Bad_Opcode },
4470     { Bad_Opcode },
4471     { Bad_Opcode },
4472     { Bad_Opcode },
4473     { Bad_Opcode },
4474     { Bad_Opcode },
4475     /* c0 */
4476     { Bad_Opcode },
4477     { Bad_Opcode },
4478     { Bad_Opcode },
4479     { Bad_Opcode },
4480     { Bad_Opcode },
4481     { Bad_Opcode },
4482     { Bad_Opcode },
4483     { Bad_Opcode },
4484     /* c8 */
4485     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4486     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4487     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4488     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4489     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4490     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4491     { Bad_Opcode },
4492     { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4493     /* d0 */
4494     { Bad_Opcode },
4495     { Bad_Opcode },
4496     { Bad_Opcode },
4497     { Bad_Opcode },
4498     { Bad_Opcode },
4499     { Bad_Opcode },
4500     { Bad_Opcode },
4501     { Bad_Opcode },
4502     /* d8 */
4503     { PREFIX_TABLE (PREFIX_0F38D8) },
4504     { Bad_Opcode },
4505     { Bad_Opcode },
4506     { "aesimc", { XM, EXx }, PREFIX_DATA },
4507     { PREFIX_TABLE (PREFIX_0F38DC) },
4508     { PREFIX_TABLE (PREFIX_0F38DD) },
4509     { PREFIX_TABLE (PREFIX_0F38DE) },
4510     { PREFIX_TABLE (PREFIX_0F38DF) },
4511     /* e0 */
4512     { Bad_Opcode },
4513     { Bad_Opcode },
4514     { Bad_Opcode },
4515     { Bad_Opcode },
4516     { Bad_Opcode },
4517     { Bad_Opcode },
4518     { Bad_Opcode },
4519     { Bad_Opcode },
4520     /* e8 */
4521     { Bad_Opcode },
4522     { Bad_Opcode },
4523     { Bad_Opcode },
4524     { Bad_Opcode },
4525     { Bad_Opcode },
4526     { Bad_Opcode },
4527     { Bad_Opcode },
4528     { Bad_Opcode },
4529     /* f0 */
4530     { PREFIX_TABLE (PREFIX_0F38F0) },
4531     { PREFIX_TABLE (PREFIX_0F38F1) },
4532     { Bad_Opcode },
4533     { Bad_Opcode },
4534     { Bad_Opcode },
4535     { MOD_TABLE (MOD_0F38F5) },
4536     { PREFIX_TABLE (PREFIX_0F38F6) },
4537     { Bad_Opcode },
4538     /* f8 */
4539     { PREFIX_TABLE (PREFIX_0F38F8) },
4540     { MOD_TABLE (MOD_0F38F9) },
4541     { PREFIX_TABLE (PREFIX_0F38FA) },
4542     { PREFIX_TABLE (PREFIX_0F38FB) },
4543     { Bad_Opcode },
4544     { Bad_Opcode },
4545     { Bad_Opcode },
4546     { Bad_Opcode },
4547   },
4548   /* THREE_BYTE_0F3A */
4549   {
4550     /* 00 */
4551     { Bad_Opcode },
4552     { Bad_Opcode },
4553     { Bad_Opcode },
4554     { Bad_Opcode },
4555     { Bad_Opcode },
4556     { Bad_Opcode },
4557     { Bad_Opcode },
4558     { Bad_Opcode },
4559     /* 08 */
4560     { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4561     { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4562     { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4563     { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4564     { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4565     { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4566     { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4567     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
4568     /* 10 */
4569     { Bad_Opcode },
4570     { Bad_Opcode },
4571     { Bad_Opcode },
4572     { Bad_Opcode },
4573     { "pextrb", { Edqb, XM, Ib }, PREFIX_DATA },
4574     { "pextrw", { Edqw, XM, Ib }, PREFIX_DATA },
4575     { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4576     { "extractps", { Edqd, XM, Ib }, PREFIX_DATA },
4577     /* 18 */
4578     { Bad_Opcode },
4579     { Bad_Opcode },
4580     { Bad_Opcode },
4581     { Bad_Opcode },
4582     { Bad_Opcode },
4583     { Bad_Opcode },
4584     { Bad_Opcode },
4585     { Bad_Opcode },
4586     /* 20 */
4587     { "pinsrb", { XM, Edqb, Ib }, PREFIX_DATA },
4588     { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4589     { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4590     { Bad_Opcode },
4591     { Bad_Opcode },
4592     { Bad_Opcode },
4593     { Bad_Opcode },
4594     { Bad_Opcode },
4595     /* 28 */
4596     { Bad_Opcode },
4597     { Bad_Opcode },
4598     { Bad_Opcode },
4599     { Bad_Opcode },
4600     { Bad_Opcode },
4601     { Bad_Opcode },
4602     { Bad_Opcode },
4603     { Bad_Opcode },
4604     /* 30 */
4605     { Bad_Opcode },
4606     { Bad_Opcode },
4607     { Bad_Opcode },
4608     { Bad_Opcode },
4609     { Bad_Opcode },
4610     { Bad_Opcode },
4611     { Bad_Opcode },
4612     { Bad_Opcode },
4613     /* 38 */
4614     { Bad_Opcode },
4615     { Bad_Opcode },
4616     { Bad_Opcode },
4617     { Bad_Opcode },
4618     { Bad_Opcode },
4619     { Bad_Opcode },
4620     { Bad_Opcode },
4621     { Bad_Opcode },
4622     /* 40 */
4623     { "dpps",   { XM, EXx, Ib }, PREFIX_DATA },
4624     { "dppd",   { XM, EXx, Ib }, PREFIX_DATA },
4625     { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4626     { Bad_Opcode },
4627     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4628     { Bad_Opcode },
4629     { Bad_Opcode },
4630     { Bad_Opcode },
4631     /* 48 */
4632     { Bad_Opcode },
4633     { Bad_Opcode },
4634     { Bad_Opcode },
4635     { Bad_Opcode },
4636     { Bad_Opcode },
4637     { Bad_Opcode },
4638     { Bad_Opcode },
4639     { Bad_Opcode },
4640     /* 50 */
4641     { Bad_Opcode },
4642     { Bad_Opcode },
4643     { Bad_Opcode },
4644     { Bad_Opcode },
4645     { Bad_Opcode },
4646     { Bad_Opcode },
4647     { Bad_Opcode },
4648     { Bad_Opcode },
4649     /* 58 */
4650     { Bad_Opcode },
4651     { Bad_Opcode },
4652     { Bad_Opcode },
4653     { Bad_Opcode },
4654     { Bad_Opcode },
4655     { Bad_Opcode },
4656     { Bad_Opcode },
4657     { Bad_Opcode },
4658     /* 60 */
4659     { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4660     { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4661     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
4662     { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
4663     { Bad_Opcode },
4664     { Bad_Opcode },
4665     { Bad_Opcode },
4666     { Bad_Opcode },
4667     /* 68 */
4668     { Bad_Opcode },
4669     { Bad_Opcode },
4670     { Bad_Opcode },
4671     { Bad_Opcode },
4672     { Bad_Opcode },
4673     { Bad_Opcode },
4674     { Bad_Opcode },
4675     { Bad_Opcode },
4676     /* 70 */
4677     { Bad_Opcode },
4678     { Bad_Opcode },
4679     { Bad_Opcode },
4680     { Bad_Opcode },
4681     { Bad_Opcode },
4682     { Bad_Opcode },
4683     { Bad_Opcode },
4684     { Bad_Opcode },
4685     /* 78 */
4686     { Bad_Opcode },
4687     { Bad_Opcode },
4688     { Bad_Opcode },
4689     { Bad_Opcode },
4690     { Bad_Opcode },
4691     { Bad_Opcode },
4692     { Bad_Opcode },
4693     { Bad_Opcode },
4694     /* 80 */
4695     { Bad_Opcode },
4696     { Bad_Opcode },
4697     { Bad_Opcode },
4698     { Bad_Opcode },
4699     { Bad_Opcode },
4700     { Bad_Opcode },
4701     { Bad_Opcode },
4702     { Bad_Opcode },
4703     /* 88 */
4704     { Bad_Opcode },
4705     { Bad_Opcode },
4706     { Bad_Opcode },
4707     { Bad_Opcode },
4708     { Bad_Opcode },
4709     { Bad_Opcode },
4710     { Bad_Opcode },
4711     { Bad_Opcode },
4712     /* 90 */
4713     { Bad_Opcode },
4714     { Bad_Opcode },
4715     { Bad_Opcode },
4716     { Bad_Opcode },
4717     { Bad_Opcode },
4718     { Bad_Opcode },
4719     { Bad_Opcode },
4720     { Bad_Opcode },
4721     /* 98 */
4722     { Bad_Opcode },
4723     { Bad_Opcode },
4724     { Bad_Opcode },
4725     { Bad_Opcode },
4726     { Bad_Opcode },
4727     { Bad_Opcode },
4728     { Bad_Opcode },
4729     { Bad_Opcode },
4730     /* a0 */
4731     { Bad_Opcode },
4732     { Bad_Opcode },
4733     { Bad_Opcode },
4734     { Bad_Opcode },
4735     { Bad_Opcode },
4736     { Bad_Opcode },
4737     { Bad_Opcode },
4738     { Bad_Opcode },
4739     /* a8 */
4740     { Bad_Opcode },
4741     { Bad_Opcode },
4742     { Bad_Opcode },
4743     { Bad_Opcode },
4744     { Bad_Opcode },
4745     { Bad_Opcode },
4746     { Bad_Opcode },
4747     { Bad_Opcode },
4748     /* b0 */
4749     { Bad_Opcode },
4750     { Bad_Opcode },
4751     { Bad_Opcode },
4752     { Bad_Opcode },
4753     { Bad_Opcode },
4754     { Bad_Opcode },
4755     { Bad_Opcode },
4756     { Bad_Opcode },
4757     /* b8 */
4758     { Bad_Opcode },
4759     { Bad_Opcode },
4760     { Bad_Opcode },
4761     { Bad_Opcode },
4762     { Bad_Opcode },
4763     { Bad_Opcode },
4764     { Bad_Opcode },
4765     { Bad_Opcode },
4766     /* c0 */
4767     { Bad_Opcode },
4768     { Bad_Opcode },
4769     { Bad_Opcode },
4770     { Bad_Opcode },
4771     { Bad_Opcode },
4772     { Bad_Opcode },
4773     { Bad_Opcode },
4774     { Bad_Opcode },
4775     /* c8 */
4776     { Bad_Opcode },
4777     { Bad_Opcode },
4778     { Bad_Opcode },
4779     { Bad_Opcode },
4780     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4781     { Bad_Opcode },
4782     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4783     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4784     /* d0 */
4785     { Bad_Opcode },
4786     { Bad_Opcode },
4787     { Bad_Opcode },
4788     { Bad_Opcode },
4789     { Bad_Opcode },
4790     { Bad_Opcode },
4791     { Bad_Opcode },
4792     { Bad_Opcode },
4793     /* d8 */
4794     { Bad_Opcode },
4795     { Bad_Opcode },
4796     { Bad_Opcode },
4797     { Bad_Opcode },
4798     { Bad_Opcode },
4799     { Bad_Opcode },
4800     { Bad_Opcode },
4801     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
4802     /* e0 */
4803     { Bad_Opcode },
4804     { Bad_Opcode },
4805     { Bad_Opcode },
4806     { Bad_Opcode },
4807     { Bad_Opcode },
4808     { Bad_Opcode },
4809     { Bad_Opcode },
4810     { Bad_Opcode },
4811     /* e8 */
4812     { Bad_Opcode },
4813     { Bad_Opcode },
4814     { Bad_Opcode },
4815     { Bad_Opcode },
4816     { Bad_Opcode },
4817     { Bad_Opcode },
4818     { Bad_Opcode },
4819     { Bad_Opcode },
4820     /* f0 */
4821     { Bad_Opcode },
4822     { Bad_Opcode },
4823     { Bad_Opcode },
4824     { Bad_Opcode },
4825     { Bad_Opcode },
4826     { Bad_Opcode },
4827     { Bad_Opcode },
4828     { Bad_Opcode },
4829     /* f8 */
4830     { Bad_Opcode },
4831     { Bad_Opcode },
4832     { Bad_Opcode },
4833     { Bad_Opcode },
4834     { Bad_Opcode },
4835     { Bad_Opcode },
4836     { Bad_Opcode },
4837     { Bad_Opcode },
4838   },
4839 };
4840
4841 static const struct dis386 xop_table[][256] = {
4842   /* XOP_08 */
4843   {
4844     /* 00 */
4845     { Bad_Opcode },
4846     { Bad_Opcode },
4847     { Bad_Opcode },
4848     { Bad_Opcode },
4849     { Bad_Opcode },
4850     { Bad_Opcode },
4851     { Bad_Opcode },
4852     { Bad_Opcode },
4853     /* 08 */
4854     { Bad_Opcode },
4855     { Bad_Opcode },
4856     { Bad_Opcode },
4857     { Bad_Opcode },
4858     { Bad_Opcode },
4859     { Bad_Opcode },
4860     { Bad_Opcode },
4861     { Bad_Opcode },
4862     /* 10 */
4863     { Bad_Opcode },
4864     { Bad_Opcode },
4865     { Bad_Opcode },
4866     { Bad_Opcode },
4867     { Bad_Opcode },
4868     { Bad_Opcode },
4869     { Bad_Opcode },
4870     { Bad_Opcode },
4871     /* 18 */
4872     { Bad_Opcode },
4873     { Bad_Opcode },
4874     { Bad_Opcode },
4875     { Bad_Opcode },
4876     { Bad_Opcode },
4877     { Bad_Opcode },
4878     { Bad_Opcode },
4879     { Bad_Opcode },
4880     /* 20 */
4881     { Bad_Opcode },
4882     { Bad_Opcode },
4883     { Bad_Opcode },
4884     { Bad_Opcode },
4885     { Bad_Opcode },
4886     { Bad_Opcode },
4887     { Bad_Opcode },
4888     { Bad_Opcode },
4889     /* 28 */
4890     { Bad_Opcode },
4891     { Bad_Opcode },
4892     { Bad_Opcode },
4893     { Bad_Opcode },
4894     { Bad_Opcode },
4895     { Bad_Opcode },
4896     { Bad_Opcode },
4897     { Bad_Opcode },
4898     /* 30 */
4899     { Bad_Opcode },
4900     { Bad_Opcode },
4901     { Bad_Opcode },
4902     { Bad_Opcode },
4903     { Bad_Opcode },
4904     { Bad_Opcode },
4905     { Bad_Opcode },
4906     { Bad_Opcode },
4907     /* 38 */
4908     { Bad_Opcode },
4909     { Bad_Opcode },
4910     { Bad_Opcode },
4911     { Bad_Opcode },
4912     { Bad_Opcode },
4913     { Bad_Opcode },
4914     { Bad_Opcode },
4915     { Bad_Opcode },
4916     /* 40 */
4917     { Bad_Opcode },
4918     { Bad_Opcode },
4919     { Bad_Opcode },
4920     { Bad_Opcode },
4921     { Bad_Opcode },
4922     { Bad_Opcode },
4923     { Bad_Opcode },
4924     { Bad_Opcode },
4925     /* 48 */
4926     { Bad_Opcode },
4927     { Bad_Opcode },
4928     { Bad_Opcode },
4929     { Bad_Opcode },
4930     { Bad_Opcode },
4931     { Bad_Opcode },
4932     { Bad_Opcode },
4933     { Bad_Opcode },
4934     /* 50 */
4935     { Bad_Opcode },
4936     { Bad_Opcode },
4937     { Bad_Opcode },
4938     { Bad_Opcode },
4939     { Bad_Opcode },
4940     { Bad_Opcode },
4941     { Bad_Opcode },
4942     { Bad_Opcode },
4943     /* 58 */
4944     { Bad_Opcode },
4945     { Bad_Opcode },
4946     { Bad_Opcode },
4947     { Bad_Opcode },
4948     { Bad_Opcode },
4949     { Bad_Opcode },
4950     { Bad_Opcode },
4951     { Bad_Opcode },
4952     /* 60 */
4953     { Bad_Opcode },
4954     { Bad_Opcode },
4955     { Bad_Opcode },
4956     { Bad_Opcode },
4957     { Bad_Opcode },
4958     { Bad_Opcode },
4959     { Bad_Opcode },
4960     { Bad_Opcode },
4961     /* 68 */
4962     { Bad_Opcode },
4963     { Bad_Opcode },
4964     { Bad_Opcode },
4965     { Bad_Opcode },
4966     { Bad_Opcode },
4967     { Bad_Opcode },
4968     { Bad_Opcode },
4969     { Bad_Opcode },
4970     /* 70 */
4971     { Bad_Opcode },
4972     { Bad_Opcode },
4973     { Bad_Opcode },
4974     { Bad_Opcode },
4975     { Bad_Opcode },
4976     { Bad_Opcode },
4977     { Bad_Opcode },
4978     { Bad_Opcode },
4979     /* 78 */
4980     { Bad_Opcode },
4981     { Bad_Opcode },
4982     { Bad_Opcode },
4983     { Bad_Opcode },
4984     { Bad_Opcode },
4985     { Bad_Opcode },
4986     { Bad_Opcode },
4987     { Bad_Opcode },
4988     /* 80 */
4989     { Bad_Opcode },
4990     { Bad_Opcode },
4991     { Bad_Opcode },
4992     { Bad_Opcode },
4993     { Bad_Opcode },
4994     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
4995     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
4996     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
4997     /* 88 */
4998     { Bad_Opcode },
4999     { Bad_Opcode },
5000     { Bad_Opcode },
5001     { Bad_Opcode },
5002     { Bad_Opcode },
5003     { Bad_Opcode },
5004     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
5005     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
5006     /* 90 */
5007     { Bad_Opcode },
5008     { Bad_Opcode },
5009     { Bad_Opcode },
5010     { Bad_Opcode },
5011     { Bad_Opcode },
5012     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
5013     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
5014     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
5015     /* 98 */
5016     { Bad_Opcode },
5017     { Bad_Opcode },
5018     { Bad_Opcode },
5019     { Bad_Opcode },
5020     { Bad_Opcode },
5021     { Bad_Opcode },
5022     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
5023     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
5024     /* a0 */
5025     { Bad_Opcode },
5026     { Bad_Opcode },
5027     { "vpcmov",         { XM, Vex, EXx, XMVexI4 }, 0 },
5028     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
5029     { Bad_Opcode },
5030     { Bad_Opcode },
5031     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
5032     { Bad_Opcode },
5033     /* a8 */
5034     { Bad_Opcode },
5035     { Bad_Opcode },
5036     { Bad_Opcode },
5037     { Bad_Opcode },
5038     { Bad_Opcode },
5039     { Bad_Opcode },
5040     { Bad_Opcode },
5041     { Bad_Opcode },
5042     /* b0 */
5043     { Bad_Opcode },
5044     { Bad_Opcode },
5045     { Bad_Opcode },
5046     { Bad_Opcode },
5047     { Bad_Opcode },
5048     { Bad_Opcode },
5049     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
5050     { Bad_Opcode },
5051     /* b8 */
5052     { Bad_Opcode },
5053     { Bad_Opcode },
5054     { Bad_Opcode },
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { Bad_Opcode },
5058     { Bad_Opcode },
5059     { Bad_Opcode },
5060     /* c0 */
5061     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
5062     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
5063     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
5064     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
5065     { Bad_Opcode },
5066     { Bad_Opcode },
5067     { Bad_Opcode },
5068     { Bad_Opcode },
5069     /* c8 */
5070     { Bad_Opcode },
5071     { Bad_Opcode },
5072     { Bad_Opcode },
5073     { Bad_Opcode },
5074     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
5075     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
5076     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
5077     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
5078     /* d0 */
5079     { Bad_Opcode },
5080     { Bad_Opcode },
5081     { Bad_Opcode },
5082     { Bad_Opcode },
5083     { Bad_Opcode },
5084     { Bad_Opcode },
5085     { Bad_Opcode },
5086     { Bad_Opcode },
5087     /* d8 */
5088     { Bad_Opcode },
5089     { Bad_Opcode },
5090     { Bad_Opcode },
5091     { Bad_Opcode },
5092     { Bad_Opcode },
5093     { Bad_Opcode },
5094     { Bad_Opcode },
5095     { Bad_Opcode },
5096     /* e0 */
5097     { Bad_Opcode },
5098     { Bad_Opcode },
5099     { Bad_Opcode },
5100     { Bad_Opcode },
5101     { Bad_Opcode },
5102     { Bad_Opcode },
5103     { Bad_Opcode },
5104     { Bad_Opcode },
5105     /* e8 */
5106     { Bad_Opcode },
5107     { Bad_Opcode },
5108     { Bad_Opcode },
5109     { Bad_Opcode },
5110     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
5111     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
5112     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
5113     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
5114     /* f0 */
5115     { Bad_Opcode },
5116     { Bad_Opcode },
5117     { Bad_Opcode },
5118     { Bad_Opcode },
5119     { Bad_Opcode },
5120     { Bad_Opcode },
5121     { Bad_Opcode },
5122     { Bad_Opcode },
5123     /* f8 */
5124     { Bad_Opcode },
5125     { Bad_Opcode },
5126     { Bad_Opcode },
5127     { Bad_Opcode },
5128     { Bad_Opcode },
5129     { Bad_Opcode },
5130     { Bad_Opcode },
5131     { Bad_Opcode },
5132   },
5133   /* XOP_09 */
5134   {
5135     /* 00 */
5136     { Bad_Opcode },
5137     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
5138     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
5139     { Bad_Opcode },
5140     { Bad_Opcode },
5141     { Bad_Opcode },
5142     { Bad_Opcode },
5143     { Bad_Opcode },
5144     /* 08 */
5145     { Bad_Opcode },
5146     { Bad_Opcode },
5147     { Bad_Opcode },
5148     { Bad_Opcode },
5149     { Bad_Opcode },
5150     { Bad_Opcode },
5151     { Bad_Opcode },
5152     { Bad_Opcode },
5153     /* 10 */
5154     { Bad_Opcode },
5155     { Bad_Opcode },
5156     { MOD_TABLE (MOD_VEX_0FXOP_09_12) },
5157     { Bad_Opcode },
5158     { Bad_Opcode },
5159     { Bad_Opcode },
5160     { Bad_Opcode },
5161     { Bad_Opcode },
5162     /* 18 */
5163     { Bad_Opcode },
5164     { Bad_Opcode },
5165     { Bad_Opcode },
5166     { Bad_Opcode },
5167     { Bad_Opcode },
5168     { Bad_Opcode },
5169     { Bad_Opcode },
5170     { Bad_Opcode },
5171     /* 20 */
5172     { Bad_Opcode },
5173     { Bad_Opcode },
5174     { Bad_Opcode },
5175     { Bad_Opcode },
5176     { Bad_Opcode },
5177     { Bad_Opcode },
5178     { Bad_Opcode },
5179     { Bad_Opcode },
5180     /* 28 */
5181     { Bad_Opcode },
5182     { Bad_Opcode },
5183     { Bad_Opcode },
5184     { Bad_Opcode },
5185     { Bad_Opcode },
5186     { Bad_Opcode },
5187     { Bad_Opcode },
5188     { Bad_Opcode },
5189     /* 30 */
5190     { Bad_Opcode },
5191     { Bad_Opcode },
5192     { Bad_Opcode },
5193     { Bad_Opcode },
5194     { Bad_Opcode },
5195     { Bad_Opcode },
5196     { Bad_Opcode },
5197     { Bad_Opcode },
5198     /* 38 */
5199     { Bad_Opcode },
5200     { Bad_Opcode },
5201     { Bad_Opcode },
5202     { Bad_Opcode },
5203     { Bad_Opcode },
5204     { Bad_Opcode },
5205     { Bad_Opcode },
5206     { Bad_Opcode },
5207     /* 40 */
5208     { Bad_Opcode },
5209     { Bad_Opcode },
5210     { Bad_Opcode },
5211     { Bad_Opcode },
5212     { Bad_Opcode },
5213     { Bad_Opcode },
5214     { Bad_Opcode },
5215     { Bad_Opcode },
5216     /* 48 */
5217     { Bad_Opcode },
5218     { Bad_Opcode },
5219     { Bad_Opcode },
5220     { Bad_Opcode },
5221     { Bad_Opcode },
5222     { Bad_Opcode },
5223     { Bad_Opcode },
5224     { Bad_Opcode },
5225     /* 50 */
5226     { Bad_Opcode },
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     { Bad_Opcode },
5230     { Bad_Opcode },
5231     { Bad_Opcode },
5232     { Bad_Opcode },
5233     { Bad_Opcode },
5234     /* 58 */
5235     { Bad_Opcode },
5236     { Bad_Opcode },
5237     { Bad_Opcode },
5238     { Bad_Opcode },
5239     { Bad_Opcode },
5240     { Bad_Opcode },
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     /* 60 */
5244     { Bad_Opcode },
5245     { Bad_Opcode },
5246     { Bad_Opcode },
5247     { Bad_Opcode },
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { Bad_Opcode },
5251     { Bad_Opcode },
5252     /* 68 */
5253     { Bad_Opcode },
5254     { Bad_Opcode },
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     { Bad_Opcode },
5258     { Bad_Opcode },
5259     { Bad_Opcode },
5260     { Bad_Opcode },
5261     /* 70 */
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     { Bad_Opcode },
5265     { Bad_Opcode },
5266     { Bad_Opcode },
5267     { Bad_Opcode },
5268     { Bad_Opcode },
5269     { Bad_Opcode },
5270     /* 78 */
5271     { Bad_Opcode },
5272     { Bad_Opcode },
5273     { Bad_Opcode },
5274     { Bad_Opcode },
5275     { Bad_Opcode },
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     { Bad_Opcode },
5279     /* 80 */
5280     { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
5281     { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
5282     { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
5283     { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
5284     { Bad_Opcode },
5285     { Bad_Opcode },
5286     { Bad_Opcode },
5287     { Bad_Opcode },
5288     /* 88 */
5289     { Bad_Opcode },
5290     { Bad_Opcode },
5291     { Bad_Opcode },
5292     { Bad_Opcode },
5293     { Bad_Opcode },
5294     { Bad_Opcode },
5295     { Bad_Opcode },
5296     { Bad_Opcode },
5297     /* 90 */
5298     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
5299     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
5300     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
5301     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
5302     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
5303     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
5304     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
5305     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
5306     /* 98 */
5307     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
5308     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
5309     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
5310     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
5311     { Bad_Opcode },
5312     { Bad_Opcode },
5313     { Bad_Opcode },
5314     { Bad_Opcode },
5315     /* a0 */
5316     { Bad_Opcode },
5317     { Bad_Opcode },
5318     { Bad_Opcode },
5319     { Bad_Opcode },
5320     { Bad_Opcode },
5321     { Bad_Opcode },
5322     { Bad_Opcode },
5323     { Bad_Opcode },
5324     /* a8 */
5325     { Bad_Opcode },
5326     { Bad_Opcode },
5327     { Bad_Opcode },
5328     { Bad_Opcode },
5329     { Bad_Opcode },
5330     { Bad_Opcode },
5331     { Bad_Opcode },
5332     { Bad_Opcode },
5333     /* b0 */
5334     { Bad_Opcode },
5335     { Bad_Opcode },
5336     { Bad_Opcode },
5337     { Bad_Opcode },
5338     { Bad_Opcode },
5339     { Bad_Opcode },
5340     { Bad_Opcode },
5341     { Bad_Opcode },
5342     /* b8 */
5343     { Bad_Opcode },
5344     { Bad_Opcode },
5345     { Bad_Opcode },
5346     { Bad_Opcode },
5347     { Bad_Opcode },
5348     { Bad_Opcode },
5349     { Bad_Opcode },
5350     { Bad_Opcode },
5351     /* c0 */
5352     { Bad_Opcode },
5353     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
5354     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
5355     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
5356     { Bad_Opcode },
5357     { Bad_Opcode },
5358     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
5359     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
5360     /* c8 */
5361     { Bad_Opcode },
5362     { Bad_Opcode },
5363     { Bad_Opcode },
5364     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
5365     { Bad_Opcode },
5366     { Bad_Opcode },
5367     { Bad_Opcode },
5368     { Bad_Opcode },
5369     /* d0 */
5370     { Bad_Opcode },
5371     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
5372     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
5373     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
5374     { Bad_Opcode },
5375     { Bad_Opcode },
5376     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
5377     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
5378     /* d8 */
5379     { Bad_Opcode },
5380     { Bad_Opcode },
5381     { Bad_Opcode },
5382     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
5383     { Bad_Opcode },
5384     { Bad_Opcode },
5385     { Bad_Opcode },
5386     { Bad_Opcode },
5387     /* e0 */
5388     { Bad_Opcode },
5389     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
5390     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
5391     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
5392     { Bad_Opcode },
5393     { Bad_Opcode },
5394     { Bad_Opcode },
5395     { Bad_Opcode },
5396     /* e8 */
5397     { Bad_Opcode },
5398     { Bad_Opcode },
5399     { Bad_Opcode },
5400     { Bad_Opcode },
5401     { Bad_Opcode },
5402     { Bad_Opcode },
5403     { Bad_Opcode },
5404     { Bad_Opcode },
5405     /* f0 */
5406     { Bad_Opcode },
5407     { Bad_Opcode },
5408     { Bad_Opcode },
5409     { Bad_Opcode },
5410     { Bad_Opcode },
5411     { Bad_Opcode },
5412     { Bad_Opcode },
5413     { Bad_Opcode },
5414     /* f8 */
5415     { Bad_Opcode },
5416     { Bad_Opcode },
5417     { Bad_Opcode },
5418     { Bad_Opcode },
5419     { Bad_Opcode },
5420     { Bad_Opcode },
5421     { Bad_Opcode },
5422     { Bad_Opcode },
5423   },
5424   /* XOP_0A */
5425   {
5426     /* 00 */
5427     { Bad_Opcode },
5428     { Bad_Opcode },
5429     { Bad_Opcode },
5430     { Bad_Opcode },
5431     { Bad_Opcode },
5432     { Bad_Opcode },
5433     { Bad_Opcode },
5434     { Bad_Opcode },
5435     /* 08 */
5436     { Bad_Opcode },
5437     { Bad_Opcode },
5438     { Bad_Opcode },
5439     { Bad_Opcode },
5440     { Bad_Opcode },
5441     { Bad_Opcode },
5442     { Bad_Opcode },
5443     { Bad_Opcode },
5444     /* 10 */
5445     { "bextrS", { Gdq, Edq, Id }, 0 },
5446     { Bad_Opcode },
5447     { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
5448     { Bad_Opcode },
5449     { Bad_Opcode },
5450     { Bad_Opcode },
5451     { Bad_Opcode },
5452     { Bad_Opcode },
5453     /* 18 */
5454     { Bad_Opcode },
5455     { Bad_Opcode },
5456     { Bad_Opcode },
5457     { Bad_Opcode },
5458     { Bad_Opcode },
5459     { Bad_Opcode },
5460     { Bad_Opcode },
5461     { Bad_Opcode },
5462     /* 20 */
5463     { Bad_Opcode },
5464     { Bad_Opcode },
5465     { Bad_Opcode },
5466     { Bad_Opcode },
5467     { Bad_Opcode },
5468     { Bad_Opcode },
5469     { Bad_Opcode },
5470     { Bad_Opcode },
5471     /* 28 */
5472     { Bad_Opcode },
5473     { Bad_Opcode },
5474     { Bad_Opcode },
5475     { Bad_Opcode },
5476     { Bad_Opcode },
5477     { Bad_Opcode },
5478     { Bad_Opcode },
5479     { Bad_Opcode },
5480     /* 30 */
5481     { Bad_Opcode },
5482     { Bad_Opcode },
5483     { Bad_Opcode },
5484     { Bad_Opcode },
5485     { Bad_Opcode },
5486     { Bad_Opcode },
5487     { Bad_Opcode },
5488     { Bad_Opcode },
5489     /* 38 */
5490     { Bad_Opcode },
5491     { Bad_Opcode },
5492     { Bad_Opcode },
5493     { Bad_Opcode },
5494     { Bad_Opcode },
5495     { Bad_Opcode },
5496     { Bad_Opcode },
5497     { Bad_Opcode },
5498     /* 40 */
5499     { Bad_Opcode },
5500     { Bad_Opcode },
5501     { Bad_Opcode },
5502     { Bad_Opcode },
5503     { Bad_Opcode },
5504     { Bad_Opcode },
5505     { Bad_Opcode },
5506     { Bad_Opcode },
5507     /* 48 */
5508     { Bad_Opcode },
5509     { Bad_Opcode },
5510     { Bad_Opcode },
5511     { Bad_Opcode },
5512     { Bad_Opcode },
5513     { Bad_Opcode },
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     /* 50 */
5517     { Bad_Opcode },
5518     { Bad_Opcode },
5519     { Bad_Opcode },
5520     { Bad_Opcode },
5521     { Bad_Opcode },
5522     { Bad_Opcode },
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     /* 58 */
5526     { Bad_Opcode },
5527     { Bad_Opcode },
5528     { Bad_Opcode },
5529     { Bad_Opcode },
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     /* 60 */
5535     { Bad_Opcode },
5536     { Bad_Opcode },
5537     { Bad_Opcode },
5538     { Bad_Opcode },
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { Bad_Opcode },
5542     { Bad_Opcode },
5543     /* 68 */
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     { Bad_Opcode },
5547     { Bad_Opcode },
5548     { Bad_Opcode },
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     /* 70 */
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     { Bad_Opcode },
5556     { Bad_Opcode },
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     /* 78 */
5562     { Bad_Opcode },
5563     { Bad_Opcode },
5564     { Bad_Opcode },
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     { Bad_Opcode },
5568     { Bad_Opcode },
5569     { Bad_Opcode },
5570     /* 80 */
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     { Bad_Opcode },
5575     { Bad_Opcode },
5576     { Bad_Opcode },
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     /* 88 */
5580     { Bad_Opcode },
5581     { Bad_Opcode },
5582     { Bad_Opcode },
5583     { Bad_Opcode },
5584     { Bad_Opcode },
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     /* 90 */
5589     { Bad_Opcode },
5590     { Bad_Opcode },
5591     { Bad_Opcode },
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     { Bad_Opcode },
5597     /* 98 */
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     { Bad_Opcode },
5606     /* a0 */
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     { Bad_Opcode },
5610     { Bad_Opcode },
5611     { Bad_Opcode },
5612     { Bad_Opcode },
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615     /* a8 */
5616     { Bad_Opcode },
5617     { Bad_Opcode },
5618     { Bad_Opcode },
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     /* b0 */
5625     { Bad_Opcode },
5626     { Bad_Opcode },
5627     { Bad_Opcode },
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     { Bad_Opcode },
5632     { Bad_Opcode },
5633     /* b8 */
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     { Bad_Opcode },
5638     { Bad_Opcode },
5639     { Bad_Opcode },
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642     /* c0 */
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645     { Bad_Opcode },
5646     { Bad_Opcode },
5647     { Bad_Opcode },
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     /* c8 */
5652     { Bad_Opcode },
5653     { Bad_Opcode },
5654     { Bad_Opcode },
5655     { Bad_Opcode },
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     { Bad_Opcode },
5660     /* d0 */
5661     { Bad_Opcode },
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     { Bad_Opcode },
5669     /* d8 */
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     { Bad_Opcode },
5673     { Bad_Opcode },
5674     { Bad_Opcode },
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     /* e0 */
5679     { Bad_Opcode },
5680     { Bad_Opcode },
5681     { Bad_Opcode },
5682     { Bad_Opcode },
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687     /* e8 */
5688     { Bad_Opcode },
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { Bad_Opcode },
5694     { Bad_Opcode },
5695     { Bad_Opcode },
5696     /* f0 */
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { Bad_Opcode },
5701     { Bad_Opcode },
5702     { Bad_Opcode },
5703     { Bad_Opcode },
5704     { Bad_Opcode },
5705     /* f8 */
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     { Bad_Opcode },
5709     { Bad_Opcode },
5710     { Bad_Opcode },
5711     { Bad_Opcode },
5712     { Bad_Opcode },
5713     { Bad_Opcode },
5714   },
5715 };
5716
5717 static const struct dis386 vex_table[][256] = {
5718   /* VEX_0F */
5719   {
5720     /* 00 */
5721     { Bad_Opcode },
5722     { Bad_Opcode },
5723     { Bad_Opcode },
5724     { Bad_Opcode },
5725     { Bad_Opcode },
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     { Bad_Opcode },
5729     /* 08 */
5730     { Bad_Opcode },
5731     { Bad_Opcode },
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     { Bad_Opcode },
5736     { Bad_Opcode },
5737     { Bad_Opcode },
5738     /* 10 */
5739     { PREFIX_TABLE (PREFIX_VEX_0F10) },
5740     { PREFIX_TABLE (PREFIX_VEX_0F11) },
5741     { PREFIX_TABLE (PREFIX_VEX_0F12) },
5742     { MOD_TABLE (MOD_VEX_0F13) },
5743     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
5744     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
5745     { PREFIX_TABLE (PREFIX_VEX_0F16) },
5746     { MOD_TABLE (MOD_VEX_0F17) },
5747     /* 18 */
5748     { Bad_Opcode },
5749     { Bad_Opcode },
5750     { Bad_Opcode },
5751     { Bad_Opcode },
5752     { Bad_Opcode },
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     /* 20 */
5757     { Bad_Opcode },
5758     { Bad_Opcode },
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     { Bad_Opcode },
5765     /* 28 */
5766     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
5767     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
5768     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
5769     { MOD_TABLE (MOD_VEX_0F2B) },
5770     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
5771     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
5772     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
5773     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
5774     /* 30 */
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778     { Bad_Opcode },
5779     { Bad_Opcode },
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     /* 38 */
5784     { Bad_Opcode },
5785     { Bad_Opcode },
5786     { Bad_Opcode },
5787     { Bad_Opcode },
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792     /* 40 */
5793     { Bad_Opcode },
5794     { PREFIX_TABLE (PREFIX_VEX_0F41) },
5795     { PREFIX_TABLE (PREFIX_VEX_0F42) },
5796     { Bad_Opcode },
5797     { PREFIX_TABLE (PREFIX_VEX_0F44) },
5798     { PREFIX_TABLE (PREFIX_VEX_0F45) },
5799     { PREFIX_TABLE (PREFIX_VEX_0F46) },
5800     { PREFIX_TABLE (PREFIX_VEX_0F47) },
5801     /* 48 */
5802     { Bad_Opcode },
5803     { Bad_Opcode },
5804     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
5805     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
5806     { Bad_Opcode },
5807     { Bad_Opcode },
5808     { Bad_Opcode },
5809     { Bad_Opcode },
5810     /* 50 */
5811     { MOD_TABLE (MOD_VEX_0F50) },
5812     { PREFIX_TABLE (PREFIX_VEX_0F51) },
5813     { PREFIX_TABLE (PREFIX_VEX_0F52) },
5814     { PREFIX_TABLE (PREFIX_VEX_0F53) },
5815     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
5816     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
5817     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
5818     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
5819     /* 58 */
5820     { PREFIX_TABLE (PREFIX_VEX_0F58) },
5821     { PREFIX_TABLE (PREFIX_VEX_0F59) },
5822     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
5823     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
5824     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
5825     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
5826     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
5827     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
5828     /* 60 */
5829     { "vpunpcklbw",     { XM, Vex, EXx }, PREFIX_DATA },
5830     { "vpunpcklwd",     { XM, Vex, EXx }, PREFIX_DATA },
5831     { "vpunpckldq",     { XM, Vex, EXx }, PREFIX_DATA },
5832     { "vpacksswb",      { XM, Vex, EXx }, PREFIX_DATA },
5833     { "vpcmpgtb",       { XM, Vex, EXx }, PREFIX_DATA },
5834     { "vpcmpgtw",       { XM, Vex, EXx }, PREFIX_DATA },
5835     { "vpcmpgtd",       { XM, Vex, EXx }, PREFIX_DATA },
5836     { "vpackuswb",      { XM, Vex, EXx }, PREFIX_DATA },
5837     /* 68 */
5838     { "vpunpckhbw",     { XM, Vex, EXx }, PREFIX_DATA },
5839     { "vpunpckhwd",     { XM, Vex, EXx }, PREFIX_DATA },
5840     { "vpunpckhdq",     { XM, Vex, EXx }, PREFIX_DATA },
5841     { "vpackssdw",      { XM, Vex, EXx }, PREFIX_DATA },
5842     { "vpunpcklqdq",    { XM, Vex, EXx }, PREFIX_DATA },
5843     { "vpunpckhqdq",    { XM, Vex, EXx }, PREFIX_DATA },
5844     { VEX_LEN_TABLE (VEX_LEN_0F6E) },
5845     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
5846     /* 70 */
5847     { PREFIX_TABLE (PREFIX_VEX_0F70) },
5848     { REG_TABLE (REG_VEX_0F71) },
5849     { REG_TABLE (REG_VEX_0F72) },
5850     { REG_TABLE (REG_VEX_0F73) },
5851     { "vpcmpeqb",       { XM, Vex, EXx }, PREFIX_DATA },
5852     { "vpcmpeqw",       { XM, Vex, EXx }, PREFIX_DATA },
5853     { "vpcmpeqd",       { XM, Vex, EXx }, PREFIX_DATA },
5854     { VEX_LEN_TABLE (VEX_LEN_0F77) },
5855     /* 78 */
5856     { Bad_Opcode },
5857     { Bad_Opcode },
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
5861     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
5862     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
5863     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
5864     /* 80 */
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     { Bad_Opcode },
5870     { Bad_Opcode },
5871     { Bad_Opcode },
5872     { Bad_Opcode },
5873     /* 88 */
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     { Bad_Opcode },
5877     { Bad_Opcode },
5878     { Bad_Opcode },
5879     { Bad_Opcode },
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     /* 90 */
5883     { PREFIX_TABLE (PREFIX_VEX_0F90) },
5884     { PREFIX_TABLE (PREFIX_VEX_0F91) },
5885     { PREFIX_TABLE (PREFIX_VEX_0F92) },
5886     { PREFIX_TABLE (PREFIX_VEX_0F93) },
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     { Bad_Opcode },
5891     /* 98 */
5892     { PREFIX_TABLE (PREFIX_VEX_0F98) },
5893     { PREFIX_TABLE (PREFIX_VEX_0F99) },
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { Bad_Opcode },
5898     { Bad_Opcode },
5899     { Bad_Opcode },
5900     /* a0 */
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     { Bad_Opcode },
5904     { Bad_Opcode },
5905     { Bad_Opcode },
5906     { Bad_Opcode },
5907     { Bad_Opcode },
5908     { Bad_Opcode },
5909     /* a8 */
5910     { Bad_Opcode },
5911     { Bad_Opcode },
5912     { Bad_Opcode },
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916     { REG_TABLE (REG_VEX_0FAE) },
5917     { Bad_Opcode },
5918     /* b0 */
5919     { Bad_Opcode },
5920     { Bad_Opcode },
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     { Bad_Opcode },
5926     { Bad_Opcode },
5927     /* b8 */
5928     { Bad_Opcode },
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { Bad_Opcode },
5932     { Bad_Opcode },
5933     { Bad_Opcode },
5934     { Bad_Opcode },
5935     { Bad_Opcode },
5936     /* c0 */
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
5940     { Bad_Opcode },
5941     { VEX_LEN_TABLE (VEX_LEN_0FC4) },
5942     { VEX_LEN_TABLE (VEX_LEN_0FC5) },
5943     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
5944     { Bad_Opcode },
5945     /* c8 */
5946     { Bad_Opcode },
5947     { Bad_Opcode },
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { Bad_Opcode },
5954     /* d0 */
5955     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
5956     { "vpsrlw",         { XM, Vex, EXxmm }, PREFIX_DATA },
5957     { "vpsrld",         { XM, Vex, EXxmm }, PREFIX_DATA },
5958     { "vpsrlq",         { XM, Vex, EXxmm }, PREFIX_DATA },
5959     { "vpaddq",         { XM, Vex, EXx }, PREFIX_DATA },
5960     { "vpmullw",        { XM, Vex, EXx }, PREFIX_DATA },
5961     { VEX_LEN_TABLE (VEX_LEN_0FD6) },
5962     { MOD_TABLE (MOD_VEX_0FD7) },
5963     /* d8 */
5964     { "vpsubusb",       { XM, Vex, EXx }, PREFIX_DATA },
5965     { "vpsubusw",       { XM, Vex, EXx }, PREFIX_DATA },
5966     { "vpminub",        { XM, Vex, EXx }, PREFIX_DATA },
5967     { "vpand",          { XM, Vex, EXx }, PREFIX_DATA },
5968     { "vpaddusb",       { XM, Vex, EXx }, PREFIX_DATA },
5969     { "vpaddusw",       { XM, Vex, EXx }, PREFIX_DATA },
5970     { "vpmaxub",        { XM, Vex, EXx }, PREFIX_DATA },
5971     { "vpandn",         { XM, Vex, EXx }, PREFIX_DATA },
5972     /* e0 */
5973     { "vpavgb",         { XM, Vex, EXx }, PREFIX_DATA },
5974     { "vpsraw",         { XM, Vex, EXxmm }, PREFIX_DATA },
5975     { "vpsrad",         { XM, Vex, EXxmm }, PREFIX_DATA },
5976     { "vpavgw",         { XM, Vex, EXx }, PREFIX_DATA },
5977     { "vpmulhuw",       { XM, Vex, EXx }, PREFIX_DATA },
5978     { "vpmulhw",        { XM, Vex, EXx }, PREFIX_DATA },
5979     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
5980     { MOD_TABLE (MOD_VEX_0FE7) },
5981     /* e8 */
5982     { "vpsubsb",        { XM, Vex, EXx }, PREFIX_DATA },
5983     { "vpsubsw",        { XM, Vex, EXx }, PREFIX_DATA },
5984     { "vpminsw",        { XM, Vex, EXx }, PREFIX_DATA },
5985     { "vpor",           { XM, Vex, EXx }, PREFIX_DATA },
5986     { "vpaddsb",        { XM, Vex, EXx }, PREFIX_DATA },
5987     { "vpaddsw",        { XM, Vex, EXx }, PREFIX_DATA },
5988     { "vpmaxsw",        { XM, Vex, EXx }, PREFIX_DATA },
5989     { "vpxor",          { XM, Vex, EXx }, PREFIX_DATA },
5990     /* f0 */
5991     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
5992     { "vpsllw",         { XM, Vex, EXxmm }, PREFIX_DATA },
5993     { "vpslld",         { XM, Vex, EXxmm }, PREFIX_DATA },
5994     { "vpsllq",         { XM, Vex, EXxmm }, PREFIX_DATA },
5995     { "vpmuludq",       { XM, Vex, EXx }, PREFIX_DATA },
5996     { "vpmaddwd",       { XM, Vex, EXx }, PREFIX_DATA },
5997     { "vpsadbw",        { XM, Vex, EXx }, PREFIX_DATA },
5998     { VEX_LEN_TABLE (VEX_LEN_0FF7) },
5999     /* f8 */
6000     { "vpsubb",         { XM, Vex, EXx }, PREFIX_DATA },
6001     { "vpsubw",         { XM, Vex, EXx }, PREFIX_DATA },
6002     { "vpsubd",         { XM, Vex, EXx }, PREFIX_DATA },
6003     { "vpsubq",         { XM, Vex, EXx }, PREFIX_DATA },
6004     { "vpaddb",         { XM, Vex, EXx }, PREFIX_DATA },
6005     { "vpaddw",         { XM, Vex, EXx }, PREFIX_DATA },
6006     { "vpaddd",         { XM, Vex, EXx }, PREFIX_DATA },
6007     { Bad_Opcode },
6008   },
6009   /* VEX_0F38 */
6010   {
6011     /* 00 */
6012     { "vpshufb",        { XM, Vex, EXx }, PREFIX_DATA },
6013     { "vphaddw",        { XM, Vex, EXx }, PREFIX_DATA },
6014     { "vphaddd",        { XM, Vex, EXx }, PREFIX_DATA },
6015     { "vphaddsw",       { XM, Vex, EXx }, PREFIX_DATA },
6016     { "vpmaddubsw",     { XM, Vex, EXx }, PREFIX_DATA },
6017     { "vphsubw",        { XM, Vex, EXx }, PREFIX_DATA },
6018     { "vphsubd",        { XM, Vex, EXx }, PREFIX_DATA },
6019     { "vphsubsw",       { XM, Vex, EXx }, PREFIX_DATA },
6020     /* 08 */
6021     { "vpsignb",        { XM, Vex, EXx }, PREFIX_DATA },
6022     { "vpsignw",        { XM, Vex, EXx }, PREFIX_DATA },
6023     { "vpsignd",        { XM, Vex, EXx }, PREFIX_DATA },
6024     { "vpmulhrsw",      { XM, Vex, EXx }, PREFIX_DATA },
6025     { VEX_W_TABLE (VEX_W_0F380C) },
6026     { VEX_W_TABLE (VEX_W_0F380D) },
6027     { VEX_W_TABLE (VEX_W_0F380E) },
6028     { VEX_W_TABLE (VEX_W_0F380F) },
6029     /* 10 */
6030     { Bad_Opcode },
6031     { Bad_Opcode },
6032     { Bad_Opcode },
6033     { VEX_W_TABLE (VEX_W_0F3813) },
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6037     { "vptest",         { XM, EXx }, PREFIX_DATA },
6038     /* 18 */
6039     { VEX_W_TABLE (VEX_W_0F3818) },
6040     { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6041     { MOD_TABLE (MOD_VEX_0F381A) },
6042     { Bad_Opcode },
6043     { "vpabsb",         { XM, EXx }, PREFIX_DATA },
6044     { "vpabsw",         { XM, EXx }, PREFIX_DATA },
6045     { "vpabsd",         { XM, EXx }, PREFIX_DATA },
6046     { Bad_Opcode },
6047     /* 20 */
6048     { "vpmovsxbw",      { XM, EXxmmq }, PREFIX_DATA },
6049     { "vpmovsxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6050     { "vpmovsxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6051     { "vpmovsxwd",      { XM, EXxmmq }, PREFIX_DATA },
6052     { "vpmovsxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6053     { "vpmovsxdq",      { XM, EXxmmq }, PREFIX_DATA },
6054     { Bad_Opcode },
6055     { Bad_Opcode },
6056     /* 28 */
6057     { "vpmuldq",        { XM, Vex, EXx }, PREFIX_DATA },
6058     { "vpcmpeqq",       { XM, Vex, EXx }, PREFIX_DATA },
6059     { MOD_TABLE (MOD_VEX_0F382A) },
6060     { "vpackusdw",      { XM, Vex, EXx }, PREFIX_DATA },
6061     { MOD_TABLE (MOD_VEX_0F382C) },
6062     { MOD_TABLE (MOD_VEX_0F382D) },
6063     { MOD_TABLE (MOD_VEX_0F382E) },
6064     { MOD_TABLE (MOD_VEX_0F382F) },
6065     /* 30 */
6066     { "vpmovzxbw",      { XM, EXxmmq }, PREFIX_DATA },
6067     { "vpmovzxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6068     { "vpmovzxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6069     { "vpmovzxwd",      { XM, EXxmmq }, PREFIX_DATA },
6070     { "vpmovzxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6071     { "vpmovzxdq",      { XM, EXxmmq }, PREFIX_DATA },
6072     { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6073     { "vpcmpgtq",       { XM, Vex, EXx }, PREFIX_DATA },
6074     /* 38 */
6075     { "vpminsb",        { XM, Vex, EXx }, PREFIX_DATA },
6076     { "vpminsd",        { XM, Vex, EXx }, PREFIX_DATA },
6077     { "vpminuw",        { XM, Vex, EXx }, PREFIX_DATA },
6078     { "vpminud",        { XM, Vex, EXx }, PREFIX_DATA },
6079     { "vpmaxsb",        { XM, Vex, EXx }, PREFIX_DATA },
6080     { "vpmaxsd",        { XM, Vex, EXx }, PREFIX_DATA },
6081     { "vpmaxuw",        { XM, Vex, EXx }, PREFIX_DATA },
6082     { "vpmaxud",        { XM, Vex, EXx }, PREFIX_DATA },
6083     /* 40 */
6084     { "vpmulld",        { XM, Vex, EXx }, PREFIX_DATA },
6085     { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     { Bad_Opcode },
6089     { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6090     { VEX_W_TABLE (VEX_W_0F3846) },
6091     { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6092     /* 48 */
6093     { Bad_Opcode },
6094     { X86_64_TABLE (X86_64_VEX_0F3849) },
6095     { Bad_Opcode },
6096     { X86_64_TABLE (X86_64_VEX_0F384B) },
6097     { Bad_Opcode },
6098     { Bad_Opcode },
6099     { Bad_Opcode },
6100     { Bad_Opcode },
6101     /* 50 */
6102     { Bad_Opcode },
6103     { Bad_Opcode },
6104     { Bad_Opcode },
6105     { Bad_Opcode },
6106     { Bad_Opcode },
6107     { Bad_Opcode },
6108     { Bad_Opcode },
6109     { Bad_Opcode },
6110     /* 58 */
6111     { VEX_W_TABLE (VEX_W_0F3858) },
6112     { VEX_W_TABLE (VEX_W_0F3859) },
6113     { MOD_TABLE (MOD_VEX_0F385A) },
6114     { Bad_Opcode },
6115     { X86_64_TABLE (X86_64_VEX_0F385C) },
6116     { Bad_Opcode },
6117     { X86_64_TABLE (X86_64_VEX_0F385E) },
6118     { Bad_Opcode },
6119     /* 60 */
6120     { Bad_Opcode },
6121     { Bad_Opcode },
6122     { Bad_Opcode },
6123     { Bad_Opcode },
6124     { Bad_Opcode },
6125     { Bad_Opcode },
6126     { Bad_Opcode },
6127     { Bad_Opcode },
6128     /* 68 */
6129     { Bad_Opcode },
6130     { Bad_Opcode },
6131     { Bad_Opcode },
6132     { Bad_Opcode },
6133     { Bad_Opcode },
6134     { Bad_Opcode },
6135     { Bad_Opcode },
6136     { Bad_Opcode },
6137     /* 70 */
6138     { Bad_Opcode },
6139     { Bad_Opcode },
6140     { Bad_Opcode },
6141     { Bad_Opcode },
6142     { Bad_Opcode },
6143     { Bad_Opcode },
6144     { Bad_Opcode },
6145     { Bad_Opcode },
6146     /* 78 */
6147     { VEX_W_TABLE (VEX_W_0F3878) },
6148     { VEX_W_TABLE (VEX_W_0F3879) },
6149     { Bad_Opcode },
6150     { Bad_Opcode },
6151     { Bad_Opcode },
6152     { Bad_Opcode },
6153     { Bad_Opcode },
6154     { Bad_Opcode },
6155     /* 80 */
6156     { Bad_Opcode },
6157     { Bad_Opcode },
6158     { Bad_Opcode },
6159     { Bad_Opcode },
6160     { Bad_Opcode },
6161     { Bad_Opcode },
6162     { Bad_Opcode },
6163     { Bad_Opcode },
6164     /* 88 */
6165     { Bad_Opcode },
6166     { Bad_Opcode },
6167     { Bad_Opcode },
6168     { Bad_Opcode },
6169     { MOD_TABLE (MOD_VEX_0F388C) },
6170     { Bad_Opcode },
6171     { MOD_TABLE (MOD_VEX_0F388E) },
6172     { Bad_Opcode },
6173     /* 90 */
6174     { "vpgatherd%DQ", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA },
6175     { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6176     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA },
6177     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6178     { Bad_Opcode },
6179     { Bad_Opcode },
6180     { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6181     { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6182     /* 98 */
6183     { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6184     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6185     { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6186     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6187     { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6188     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6189     { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6190     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6191     /* a0 */
6192     { Bad_Opcode },
6193     { Bad_Opcode },
6194     { Bad_Opcode },
6195     { Bad_Opcode },
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6199     { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6200     /* a8 */
6201     { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6202     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6203     { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6204     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6205     { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6206     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6207     { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6208     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6209     /* b0 */
6210     { Bad_Opcode },
6211     { Bad_Opcode },
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     { Bad_Opcode },
6215     { Bad_Opcode },
6216     { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6217     { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6218     /* b8 */
6219     { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6220     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6221     { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6222     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6223     { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6224     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6225     { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6226     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6227     /* c0 */
6228     { Bad_Opcode },
6229     { Bad_Opcode },
6230     { Bad_Opcode },
6231     { Bad_Opcode },
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     { Bad_Opcode },
6236     /* c8 */
6237     { Bad_Opcode },
6238     { Bad_Opcode },
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     { Bad_Opcode },
6243     { Bad_Opcode },
6244     { VEX_W_TABLE (VEX_W_0F38CF) },
6245     /* d0 */
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     { Bad_Opcode },
6249     { Bad_Opcode },
6250     { Bad_Opcode },
6251     { Bad_Opcode },
6252     { Bad_Opcode },
6253     { Bad_Opcode },
6254     /* d8 */
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     { Bad_Opcode },
6258     { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6259     { "vaesenc",        { XM, Vex, EXx }, PREFIX_DATA },
6260     { "vaesenclast",    { XM, Vex, EXx }, PREFIX_DATA },
6261     { "vaesdec",        { XM, Vex, EXx }, PREFIX_DATA },
6262     { "vaesdeclast",    { XM, Vex, EXx }, PREFIX_DATA },
6263     /* e0 */
6264     { Bad_Opcode },
6265     { Bad_Opcode },
6266     { Bad_Opcode },
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     { Bad_Opcode },
6270     { Bad_Opcode },
6271     { Bad_Opcode },
6272     /* e8 */
6273     { Bad_Opcode },
6274     { Bad_Opcode },
6275     { Bad_Opcode },
6276     { Bad_Opcode },
6277     { Bad_Opcode },
6278     { Bad_Opcode },
6279     { Bad_Opcode },
6280     { Bad_Opcode },
6281     /* f0 */
6282     { Bad_Opcode },
6283     { Bad_Opcode },
6284     { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6285     { REG_TABLE (REG_VEX_0F38F3) },
6286     { Bad_Opcode },
6287     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
6288     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
6289     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
6290     /* f8 */
6291     { Bad_Opcode },
6292     { Bad_Opcode },
6293     { Bad_Opcode },
6294     { Bad_Opcode },
6295     { Bad_Opcode },
6296     { Bad_Opcode },
6297     { Bad_Opcode },
6298     { Bad_Opcode },
6299   },
6300   /* VEX_0F3A */
6301   {
6302     /* 00 */
6303     { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6304     { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6305     { VEX_W_TABLE (VEX_W_0F3A02) },
6306     { Bad_Opcode },
6307     { VEX_W_TABLE (VEX_W_0F3A04) },
6308     { VEX_W_TABLE (VEX_W_0F3A05) },
6309     { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6310     { Bad_Opcode },
6311     /* 08 */
6312     { "vroundps",       { XM, EXx, Ib }, PREFIX_DATA },
6313     { "vroundpd",       { XM, EXx, Ib }, PREFIX_DATA },
6314     { "vroundss",       { XMScalar, VexScalar, EXxmm_md, Ib }, PREFIX_DATA },
6315     { "vroundsd",       { XMScalar, VexScalar, EXxmm_mq, Ib }, PREFIX_DATA },
6316     { "vblendps",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6317     { "vblendpd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6318     { "vpblendw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6319     { "vpalignr",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6320     /* 10 */
6321     { Bad_Opcode },
6322     { Bad_Opcode },
6323     { Bad_Opcode },
6324     { Bad_Opcode },
6325     { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6326     { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6327     { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6328     { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6329     /* 18 */
6330     { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6331     { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { Bad_Opcode },
6335     { VEX_W_TABLE (VEX_W_0F3A1D) },
6336     { Bad_Opcode },
6337     { Bad_Opcode },
6338     /* 20 */
6339     { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6340     { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6341     { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6342     { Bad_Opcode },
6343     { Bad_Opcode },
6344     { Bad_Opcode },
6345     { Bad_Opcode },
6346     { Bad_Opcode },
6347     /* 28 */
6348     { Bad_Opcode },
6349     { Bad_Opcode },
6350     { Bad_Opcode },
6351     { Bad_Opcode },
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356     /* 30 */
6357     { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6358     { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6359     { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6360     { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6361     { Bad_Opcode },
6362     { Bad_Opcode },
6363     { Bad_Opcode },
6364     { Bad_Opcode },
6365     /* 38 */
6366     { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6367     { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6368     { Bad_Opcode },
6369     { Bad_Opcode },
6370     { Bad_Opcode },
6371     { Bad_Opcode },
6372     { Bad_Opcode },
6373     { Bad_Opcode },
6374     /* 40 */
6375     { "vdpps",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
6376     { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6377     { "vmpsadbw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6378     { Bad_Opcode },
6379     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6380     { Bad_Opcode },
6381     { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6382     { Bad_Opcode },
6383     /* 48 */
6384     { "vpermil2ps",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6385     { "vpermil2pd",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6386     { VEX_W_TABLE (VEX_W_0F3A4A) },
6387     { VEX_W_TABLE (VEX_W_0F3A4B) },
6388     { VEX_W_TABLE (VEX_W_0F3A4C) },
6389     { Bad_Opcode },
6390     { Bad_Opcode },
6391     { Bad_Opcode },
6392     /* 50 */
6393     { Bad_Opcode },
6394     { Bad_Opcode },
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { Bad_Opcode },
6398     { Bad_Opcode },
6399     { Bad_Opcode },
6400     { Bad_Opcode },
6401     /* 58 */
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { Bad_Opcode },
6405     { Bad_Opcode },
6406     { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6407     { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6408     { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6409     { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6410     /* 60 */
6411     { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6412     { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6413     { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6414     { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6415     { Bad_Opcode },
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { Bad_Opcode },
6419     /* 68 */
6420     { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6421     { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6422     { "vfmaddss",       { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6423     { "vfmaddsd",       { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6424     { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6425     { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6426     { "vfmsubss",       { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6427     { "vfmsubsd",       { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6428     /* 70 */
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     { Bad_Opcode },
6434     { Bad_Opcode },
6435     { Bad_Opcode },
6436     { Bad_Opcode },
6437     /* 78 */
6438     { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6439     { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6440     { "vfnmaddss",      { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6441     { "vfnmaddsd",      { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6442     { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6443     { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6444     { "vfnmsubss",      { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6445     { "vfnmsubsd",      { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6446     /* 80 */
6447     { Bad_Opcode },
6448     { Bad_Opcode },
6449     { Bad_Opcode },
6450     { Bad_Opcode },
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { Bad_Opcode },
6455     /* 88 */
6456     { Bad_Opcode },
6457     { Bad_Opcode },
6458     { Bad_Opcode },
6459     { Bad_Opcode },
6460     { Bad_Opcode },
6461     { Bad_Opcode },
6462     { Bad_Opcode },
6463     { Bad_Opcode },
6464     /* 90 */
6465     { Bad_Opcode },
6466     { Bad_Opcode },
6467     { Bad_Opcode },
6468     { Bad_Opcode },
6469     { Bad_Opcode },
6470     { Bad_Opcode },
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     /* 98 */
6474     { Bad_Opcode },
6475     { Bad_Opcode },
6476     { Bad_Opcode },
6477     { Bad_Opcode },
6478     { Bad_Opcode },
6479     { Bad_Opcode },
6480     { Bad_Opcode },
6481     { Bad_Opcode },
6482     /* a0 */
6483     { Bad_Opcode },
6484     { Bad_Opcode },
6485     { Bad_Opcode },
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     { Bad_Opcode },
6489     { Bad_Opcode },
6490     { Bad_Opcode },
6491     /* a8 */
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     { Bad_Opcode },
6495     { Bad_Opcode },
6496     { Bad_Opcode },
6497     { Bad_Opcode },
6498     { Bad_Opcode },
6499     { Bad_Opcode },
6500     /* b0 */
6501     { Bad_Opcode },
6502     { Bad_Opcode },
6503     { Bad_Opcode },
6504     { Bad_Opcode },
6505     { Bad_Opcode },
6506     { Bad_Opcode },
6507     { Bad_Opcode },
6508     { Bad_Opcode },
6509     /* b8 */
6510     { Bad_Opcode },
6511     { Bad_Opcode },
6512     { Bad_Opcode },
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { Bad_Opcode },
6516     { Bad_Opcode },
6517     { Bad_Opcode },
6518     /* c0 */
6519     { Bad_Opcode },
6520     { Bad_Opcode },
6521     { Bad_Opcode },
6522     { Bad_Opcode },
6523     { Bad_Opcode },
6524     { Bad_Opcode },
6525     { Bad_Opcode },
6526     { Bad_Opcode },
6527     /* c8 */
6528     { Bad_Opcode },
6529     { Bad_Opcode },
6530     { Bad_Opcode },
6531     { Bad_Opcode },
6532     { Bad_Opcode },
6533     { Bad_Opcode },
6534     { VEX_W_TABLE (VEX_W_0F3ACE) },
6535     { VEX_W_TABLE (VEX_W_0F3ACF) },
6536     /* d0 */
6537     { Bad_Opcode },
6538     { Bad_Opcode },
6539     { Bad_Opcode },
6540     { Bad_Opcode },
6541     { Bad_Opcode },
6542     { Bad_Opcode },
6543     { Bad_Opcode },
6544     { Bad_Opcode },
6545     /* d8 */
6546     { Bad_Opcode },
6547     { Bad_Opcode },
6548     { Bad_Opcode },
6549     { Bad_Opcode },
6550     { Bad_Opcode },
6551     { Bad_Opcode },
6552     { Bad_Opcode },
6553     { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6554     /* e0 */
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     { Bad_Opcode },
6560     { Bad_Opcode },
6561     { Bad_Opcode },
6562     { Bad_Opcode },
6563     /* e8 */
6564     { Bad_Opcode },
6565     { Bad_Opcode },
6566     { Bad_Opcode },
6567     { Bad_Opcode },
6568     { Bad_Opcode },
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     { Bad_Opcode },
6572     /* f0 */
6573     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
6574     { Bad_Opcode },
6575     { Bad_Opcode },
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     { Bad_Opcode },
6580     { Bad_Opcode },
6581     /* f8 */
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     { Bad_Opcode },
6588     { Bad_Opcode },
6589     { Bad_Opcode },
6590   },
6591 };
6592
6593 #include "i386-dis-evex.h"
6594
6595 static const struct dis386 vex_len_table[][2] = {
6596   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6597   {
6598     { "vmovlpX",        { XM, Vex, EXq }, 0 },
6599   },
6600
6601   /* VEX_LEN_0F12_P_0_M_1 */
6602   {
6603     { "vmovhlps",       { XM, Vex, EXq }, 0 },
6604   },
6605
6606   /* VEX_LEN_0F13_M_0 */
6607   {
6608     { "vmovlpX",        { EXq, XM }, PREFIX_OPCODE },
6609   },
6610
6611   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6612   {
6613     { "vmovhpX",        { XM, Vex, EXq }, 0 },
6614   },
6615
6616   /* VEX_LEN_0F16_P_0_M_1 */
6617   {
6618     { "vmovlhps",       { XM, Vex, EXq }, 0 },
6619   },
6620
6621   /* VEX_LEN_0F17_M_0 */
6622   {
6623     { "vmovhpX",        { EXq, XM }, PREFIX_OPCODE },
6624   },
6625
6626   /* VEX_LEN_0F41_P_0 */
6627   {
6628     { Bad_Opcode },
6629     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
6630   },
6631   /* VEX_LEN_0F41_P_2 */
6632   {
6633     { Bad_Opcode },
6634     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
6635   },
6636   /* VEX_LEN_0F42_P_0 */
6637   {
6638     { Bad_Opcode },
6639     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
6640   },
6641   /* VEX_LEN_0F42_P_2 */
6642   {
6643     { Bad_Opcode },
6644     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
6645   },
6646   /* VEX_LEN_0F44_P_0 */
6647   {
6648     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
6649   },
6650   /* VEX_LEN_0F44_P_2 */
6651   {
6652     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
6653   },
6654   /* VEX_LEN_0F45_P_0 */
6655   {
6656     { Bad_Opcode },
6657     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
6658   },
6659   /* VEX_LEN_0F45_P_2 */
6660   {
6661     { Bad_Opcode },
6662     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
6663   },
6664   /* VEX_LEN_0F46_P_0 */
6665   {
6666     { Bad_Opcode },
6667     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
6668   },
6669   /* VEX_LEN_0F46_P_2 */
6670   {
6671     { Bad_Opcode },
6672     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
6673   },
6674   /* VEX_LEN_0F47_P_0 */
6675   {
6676     { Bad_Opcode },
6677     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
6678   },
6679   /* VEX_LEN_0F47_P_2 */
6680   {
6681     { Bad_Opcode },
6682     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
6683   },
6684   /* VEX_LEN_0F4A_P_0 */
6685   {
6686     { Bad_Opcode },
6687     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
6688   },
6689   /* VEX_LEN_0F4A_P_2 */
6690   {
6691     { Bad_Opcode },
6692     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
6693   },
6694   /* VEX_LEN_0F4B_P_0 */
6695   {
6696     { Bad_Opcode },
6697     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
6698   },
6699   /* VEX_LEN_0F4B_P_2 */
6700   {
6701     { Bad_Opcode },
6702     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
6703   },
6704
6705   /* VEX_LEN_0F6E */
6706   {
6707     { "vmovK",          { XMScalar, Edq }, PREFIX_DATA },
6708   },
6709
6710   /* VEX_LEN_0F77 */
6711   {
6712     { "vzeroupper",     { XX }, 0 },
6713     { "vzeroall",       { XX }, 0 },
6714   },
6715
6716   /* VEX_LEN_0F7E_P_1 */
6717   {
6718     { "vmovq",          { XMScalar, EXxmm_mq }, 0 },
6719   },
6720
6721   /* VEX_LEN_0F7E_P_2 */
6722   {
6723     { "vmovK",          { Edq, XMScalar }, 0 },
6724   },
6725
6726   /* VEX_LEN_0F90_P_0 */
6727   {
6728     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
6729   },
6730
6731   /* VEX_LEN_0F90_P_2 */
6732   {
6733     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
6734   },
6735
6736   /* VEX_LEN_0F91_P_0 */
6737   {
6738     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
6739   },
6740
6741   /* VEX_LEN_0F91_P_2 */
6742   {
6743     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
6744   },
6745
6746   /* VEX_LEN_0F92_P_0 */
6747   {
6748     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
6749   },
6750
6751   /* VEX_LEN_0F92_P_2 */
6752   {
6753     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
6754   },
6755
6756   /* VEX_LEN_0F92_P_3 */
6757   {
6758     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
6759   },
6760
6761   /* VEX_LEN_0F93_P_0 */
6762   {
6763     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
6764   },
6765
6766   /* VEX_LEN_0F93_P_2 */
6767   {
6768     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
6769   },
6770
6771   /* VEX_LEN_0F93_P_3 */
6772   {
6773     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
6774   },
6775
6776   /* VEX_LEN_0F98_P_0 */
6777   {
6778     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
6779   },
6780
6781   /* VEX_LEN_0F98_P_2 */
6782   {
6783     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
6784   },
6785
6786   /* VEX_LEN_0F99_P_0 */
6787   {
6788     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
6789   },
6790
6791   /* VEX_LEN_0F99_P_2 */
6792   {
6793     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
6794   },
6795
6796   /* VEX_LEN_0FAE_R_2_M_0 */
6797   {
6798     { "vldmxcsr",       { Md }, 0 },
6799   },
6800
6801   /* VEX_LEN_0FAE_R_3_M_0 */
6802   {
6803     { "vstmxcsr",       { Md }, 0 },
6804   },
6805
6806   /* VEX_LEN_0FC4 */
6807   {
6808     { "vpinsrw",        { XM, Vex, Edqw, Ib }, PREFIX_DATA },
6809   },
6810
6811   /* VEX_LEN_0FC5 */
6812   {
6813     { "vpextrw",        { Gdq, XS, Ib }, PREFIX_DATA },
6814   },
6815
6816   /* VEX_LEN_0FD6 */
6817   {
6818     { "vmovq",          { EXqS, XMScalar }, PREFIX_DATA },
6819   },
6820
6821   /* VEX_LEN_0FF7 */
6822   {
6823     { "vmaskmovdqu",    { XM, XS }, PREFIX_DATA },
6824   },
6825
6826   /* VEX_LEN_0F3816 */
6827   {
6828     { Bad_Opcode },
6829     { VEX_W_TABLE (VEX_W_0F3816_L_1) },
6830   },
6831
6832   /* VEX_LEN_0F3819 */
6833   {
6834     { Bad_Opcode },
6835     { VEX_W_TABLE (VEX_W_0F3819_L_1) },
6836   },
6837
6838   /* VEX_LEN_0F381A_M_0 */
6839   {
6840     { Bad_Opcode },
6841     { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) },
6842   },
6843
6844   /* VEX_LEN_0F3836 */
6845   {
6846     { Bad_Opcode },
6847     { VEX_W_TABLE (VEX_W_0F3836) },
6848   },
6849
6850   /* VEX_LEN_0F3841 */
6851   {
6852     { "vphminposuw",    { XM, EXx }, PREFIX_DATA },
6853   },
6854
6855    /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
6856   {
6857     { "ldtilecfg", { M }, 0 },
6858   },
6859
6860   /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
6861   {
6862     { "tilerelease", { Skip_MODRM }, 0 },
6863   },
6864
6865   /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
6866   {
6867     { "sttilecfg", { M }, 0 },
6868   },
6869
6870   /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
6871   {
6872     { "tilezero", { TMM, Skip_MODRM }, 0 },
6873   },
6874
6875   /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
6876   {
6877     { "tilestored", { MVexSIBMEM, TMM }, 0 },
6878   },
6879   /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
6880   {
6881     { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
6882   },
6883
6884   /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
6885   {
6886     { "tileloadd", { TMM, MVexSIBMEM }, 0 },
6887   },
6888
6889   /* VEX_LEN_0F385A_M_0 */
6890   {
6891     { Bad_Opcode },
6892     { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) },
6893   },
6894
6895   /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
6896   {
6897     { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
6898   },
6899
6900   /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
6901   {
6902     { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
6903   },
6904
6905   /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
6906   {
6907     { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
6908   },
6909
6910   /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
6911   {
6912     { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
6913   },
6914
6915   /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
6916   {
6917     { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
6918   },
6919
6920   /* VEX_LEN_0F38DB */
6921   {
6922     { "vaesimc",        { XM, EXx }, PREFIX_DATA },
6923   },
6924
6925   /* VEX_LEN_0F38F2 */
6926   {
6927     { "andnS",          { Gdq, VexGdq, Edq }, PREFIX_OPCODE },
6928   },
6929
6930   /* VEX_LEN_0F38F3_R_1 */
6931   {
6932     { "blsrS",          { VexGdq, Edq }, PREFIX_OPCODE },
6933   },
6934
6935   /* VEX_LEN_0F38F3_R_2 */
6936   {
6937     { "blsmskS",        { VexGdq, Edq }, PREFIX_OPCODE },
6938   },
6939
6940   /* VEX_LEN_0F38F3_R_3 */
6941   {
6942     { "blsiS",          { VexGdq, Edq }, PREFIX_OPCODE },
6943   },
6944
6945   /* VEX_LEN_0F38F5_P_0 */
6946   {
6947     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
6948   },
6949
6950   /* VEX_LEN_0F38F5_P_1 */
6951   {
6952     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
6953   },
6954
6955   /* VEX_LEN_0F38F5_P_3 */
6956   {
6957     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
6958   },
6959
6960   /* VEX_LEN_0F38F6_P_3 */
6961   {
6962     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
6963   },
6964
6965   /* VEX_LEN_0F38F7_P_0 */
6966   {
6967     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
6968   },
6969
6970   /* VEX_LEN_0F38F7_P_1 */
6971   {
6972     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
6973   },
6974
6975   /* VEX_LEN_0F38F7_P_2 */
6976   {
6977     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
6978   },
6979
6980   /* VEX_LEN_0F38F7_P_3 */
6981   {
6982     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
6983   },
6984
6985   /* VEX_LEN_0F3A00 */
6986   {
6987     { Bad_Opcode },
6988     { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
6989   },
6990
6991   /* VEX_LEN_0F3A01 */
6992   {
6993     { Bad_Opcode },
6994     { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
6995   },
6996
6997   /* VEX_LEN_0F3A06 */
6998   {
6999     { Bad_Opcode },
7000     { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
7001   },
7002
7003   /* VEX_LEN_0F3A14 */
7004   {
7005     { "vpextrb",        { Edqb, XM, Ib }, PREFIX_DATA },
7006   },
7007
7008   /* VEX_LEN_0F3A15 */
7009   {
7010     { "vpextrw",        { Edqw, XM, Ib }, PREFIX_DATA },
7011   },
7012
7013   /* VEX_LEN_0F3A16  */
7014   {
7015     { "vpextrK",        { Edq, XM, Ib }, PREFIX_DATA },
7016   },
7017
7018   /* VEX_LEN_0F3A17 */
7019   {
7020     { "vextractps",     { Edqd, XM, Ib }, PREFIX_DATA },
7021   },
7022
7023   /* VEX_LEN_0F3A18 */
7024   {
7025     { Bad_Opcode },
7026     { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
7027   },
7028
7029   /* VEX_LEN_0F3A19 */
7030   {
7031     { Bad_Opcode },
7032     { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7033   },
7034
7035   /* VEX_LEN_0F3A20 */
7036   {
7037     { "vpinsrb",        { XM, Vex, Edqb, Ib }, PREFIX_DATA },
7038   },
7039
7040   /* VEX_LEN_0F3A21 */
7041   {
7042     { "vinsertps",      { XM, Vex, EXd, Ib }, PREFIX_DATA },
7043   },
7044
7045   /* VEX_LEN_0F3A22 */
7046   {
7047     { "vpinsrK",        { XM, Vex, Edq, Ib }, PREFIX_DATA },
7048   },
7049
7050   /* VEX_LEN_0F3A30 */
7051   {
7052     { MOD_TABLE (MOD_VEX_0F3A30_L_0) },
7053   },
7054
7055   /* VEX_LEN_0F3A31 */
7056   {
7057     { MOD_TABLE (MOD_VEX_0F3A31_L_0) },
7058   },
7059
7060   /* VEX_LEN_0F3A32 */
7061   {
7062     { MOD_TABLE (MOD_VEX_0F3A32_L_0) },
7063   },
7064
7065   /* VEX_LEN_0F3A33 */
7066   {
7067     { MOD_TABLE (MOD_VEX_0F3A33_L_0) },
7068   },
7069
7070   /* VEX_LEN_0F3A38 */
7071   {
7072     { Bad_Opcode },
7073     { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7074   },
7075
7076   /* VEX_LEN_0F3A39 */
7077   {
7078     { Bad_Opcode },
7079     { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7080   },
7081
7082   /* VEX_LEN_0F3A41 */
7083   {
7084     { "vdppd",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
7085   },
7086
7087   /* VEX_LEN_0F3A46 */
7088   {
7089     { Bad_Opcode },
7090     { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7091   },
7092
7093   /* VEX_LEN_0F3A60 */
7094   {
7095     { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7096   },
7097
7098   /* VEX_LEN_0F3A61 */
7099   {
7100     { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7101   },
7102
7103   /* VEX_LEN_0F3A62 */
7104   {
7105     { "vpcmpistrm",     { XM, EXx, Ib }, PREFIX_DATA },
7106   },
7107
7108   /* VEX_LEN_0F3A63 */
7109   {
7110     { "vpcmpistri",     { XM, EXx, Ib }, PREFIX_DATA },
7111   },
7112
7113   /* VEX_LEN_0F3ADF */
7114   {
7115     { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7116   },
7117
7118   /* VEX_LEN_0F3AF0_P_3 */
7119   {
7120     { "rorxS",          { Gdq, Edq, Ib }, 0 },
7121   },
7122
7123   /* VEX_LEN_0FXOP_08_85 */
7124   {
7125     { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
7126   },
7127
7128   /* VEX_LEN_0FXOP_08_86 */
7129   {
7130     { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
7131   },
7132
7133   /* VEX_LEN_0FXOP_08_87 */
7134   {
7135     { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
7136   },
7137
7138   /* VEX_LEN_0FXOP_08_8E */
7139   {
7140     { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
7141   },
7142
7143   /* VEX_LEN_0FXOP_08_8F */
7144   {
7145     { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
7146   },
7147
7148   /* VEX_LEN_0FXOP_08_95 */
7149   {
7150     { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
7151   },
7152
7153   /* VEX_LEN_0FXOP_08_96 */
7154   {
7155     { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
7156   },
7157
7158   /* VEX_LEN_0FXOP_08_97 */
7159   {
7160     { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
7161   },
7162
7163   /* VEX_LEN_0FXOP_08_9E */
7164   {
7165     { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
7166   },
7167
7168   /* VEX_LEN_0FXOP_08_9F */
7169   {
7170     { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
7171   },
7172
7173   /* VEX_LEN_0FXOP_08_A3 */
7174   {
7175     { "vpperm",         { XM, Vex, EXx, XMVexI4 }, 0 },
7176   },
7177
7178   /* VEX_LEN_0FXOP_08_A6 */
7179   {
7180     { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
7181   },
7182
7183   /* VEX_LEN_0FXOP_08_B6 */
7184   {
7185     { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
7186   },
7187
7188   /* VEX_LEN_0FXOP_08_C0 */
7189   {
7190     { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
7191   },
7192
7193   /* VEX_LEN_0FXOP_08_C1 */
7194   {
7195     { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
7196   },
7197
7198   /* VEX_LEN_0FXOP_08_C2 */
7199   {
7200     { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
7201   },
7202
7203   /* VEX_LEN_0FXOP_08_C3 */
7204   {
7205     { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
7206   },
7207
7208   /* VEX_LEN_0FXOP_08_CC */
7209   {
7210     { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
7211   },
7212
7213   /* VEX_LEN_0FXOP_08_CD */
7214   {
7215     { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
7216   },
7217
7218   /* VEX_LEN_0FXOP_08_CE */
7219   {
7220     { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
7221   },
7222
7223   /* VEX_LEN_0FXOP_08_CF */
7224   {
7225     { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
7226   },
7227
7228   /* VEX_LEN_0FXOP_08_EC */
7229   {
7230     { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
7231   },
7232
7233   /* VEX_LEN_0FXOP_08_ED */
7234   {
7235     { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
7236   },
7237
7238   /* VEX_LEN_0FXOP_08_EE */
7239   {
7240     { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
7241   },
7242
7243   /* VEX_LEN_0FXOP_08_EF */
7244   {
7245     { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
7246   },
7247
7248   /* VEX_LEN_0FXOP_09_01 */
7249   {
7250     { REG_TABLE (REG_0FXOP_09_01_L_0) },
7251   },
7252
7253   /* VEX_LEN_0FXOP_09_02 */
7254   {
7255     { REG_TABLE (REG_0FXOP_09_02_L_0) },
7256   },
7257
7258   /* VEX_LEN_0FXOP_09_12_M_1 */
7259   {
7260     { REG_TABLE (REG_0FXOP_09_12_M_1_L_0) },
7261   },
7262
7263   /* VEX_LEN_0FXOP_09_82_W_0 */
7264   {
7265     { "vfrczss",        { XM, EXd }, 0 },
7266   },
7267
7268   /* VEX_LEN_0FXOP_09_83_W_0 */
7269   {
7270     { "vfrczsd",        { XM, EXq }, 0 },
7271   },
7272
7273   /* VEX_LEN_0FXOP_09_90 */
7274   {
7275     { "vprotb",         { XM, EXx, VexW }, 0 },
7276   },
7277
7278   /* VEX_LEN_0FXOP_09_91 */
7279   {
7280     { "vprotw",         { XM, EXx, VexW }, 0 },
7281   },
7282
7283   /* VEX_LEN_0FXOP_09_92 */
7284   {
7285     { "vprotd",         { XM, EXx, VexW }, 0 },
7286   },
7287
7288   /* VEX_LEN_0FXOP_09_93 */
7289   {
7290     { "vprotq",         { XM, EXx, VexW }, 0 },
7291   },
7292
7293   /* VEX_LEN_0FXOP_09_94 */
7294   {
7295     { "vpshlb",         { XM, EXx, VexW }, 0 },
7296   },
7297
7298   /* VEX_LEN_0FXOP_09_95 */
7299   {
7300     { "vpshlw",         { XM, EXx, VexW }, 0 },
7301   },
7302
7303   /* VEX_LEN_0FXOP_09_96 */
7304   {
7305     { "vpshld",         { XM, EXx, VexW }, 0 },
7306   },
7307
7308   /* VEX_LEN_0FXOP_09_97 */
7309   {
7310     { "vpshlq",         { XM, EXx, VexW }, 0 },
7311   },
7312
7313   /* VEX_LEN_0FXOP_09_98 */
7314   {
7315     { "vpshab",         { XM, EXx, VexW }, 0 },
7316   },
7317
7318   /* VEX_LEN_0FXOP_09_99 */
7319   {
7320     { "vpshaw",         { XM, EXx, VexW }, 0 },
7321   },
7322
7323   /* VEX_LEN_0FXOP_09_9A */
7324   {
7325     { "vpshad",         { XM, EXx, VexW }, 0 },
7326   },
7327
7328   /* VEX_LEN_0FXOP_09_9B */
7329   {
7330     { "vpshaq",         { XM, EXx, VexW }, 0 },
7331   },
7332
7333   /* VEX_LEN_0FXOP_09_C1 */
7334   {
7335     { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
7336   },
7337
7338   /* VEX_LEN_0FXOP_09_C2 */
7339   {
7340     { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
7341   },
7342
7343   /* VEX_LEN_0FXOP_09_C3 */
7344   {
7345     { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
7346   },
7347
7348   /* VEX_LEN_0FXOP_09_C6 */
7349   {
7350     { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
7351   },
7352
7353   /* VEX_LEN_0FXOP_09_C7 */
7354   {
7355     { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
7356   },
7357
7358   /* VEX_LEN_0FXOP_09_CB */
7359   {
7360     { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
7361   },
7362
7363   /* VEX_LEN_0FXOP_09_D1 */
7364   {
7365     { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
7366   },
7367
7368   /* VEX_LEN_0FXOP_09_D2 */
7369   {
7370     { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
7371   },
7372
7373   /* VEX_LEN_0FXOP_09_D3 */
7374   {
7375     { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
7376   },
7377
7378   /* VEX_LEN_0FXOP_09_D6 */
7379   {
7380     { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
7381   },
7382
7383   /* VEX_LEN_0FXOP_09_D7 */
7384   {
7385     { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
7386   },
7387
7388   /* VEX_LEN_0FXOP_09_DB */
7389   {
7390     { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
7391   },
7392
7393   /* VEX_LEN_0FXOP_09_E1 */
7394   {
7395     { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
7396   },
7397
7398   /* VEX_LEN_0FXOP_09_E2 */
7399   {
7400     { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
7401   },
7402
7403   /* VEX_LEN_0FXOP_09_E3 */
7404   {
7405     { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
7406   },
7407
7408   /* VEX_LEN_0FXOP_0A_12 */
7409   {
7410     { REG_TABLE (REG_0FXOP_0A_12_L_0) },
7411   },
7412 };
7413
7414 #include "i386-dis-evex-len.h"
7415
7416 static const struct dis386 vex_w_table[][2] = {
7417   {
7418     /* VEX_W_0F41_P_0_LEN_1 */
7419     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
7420     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
7421   },
7422   {
7423     /* VEX_W_0F41_P_2_LEN_1 */
7424     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
7425     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
7426   },
7427   {
7428     /* VEX_W_0F42_P_0_LEN_1 */
7429     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
7430     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
7431   },
7432   {
7433     /* VEX_W_0F42_P_2_LEN_1 */
7434     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
7435     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
7436   },
7437   {
7438     /* VEX_W_0F44_P_0_LEN_0 */
7439     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
7440     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
7441   },
7442   {
7443     /* VEX_W_0F44_P_2_LEN_0 */
7444     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
7445     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
7446   },
7447   {
7448     /* VEX_W_0F45_P_0_LEN_1 */
7449     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
7450     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
7451   },
7452   {
7453     /* VEX_W_0F45_P_2_LEN_1 */
7454     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
7455     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
7456   },
7457   {
7458     /* VEX_W_0F46_P_0_LEN_1 */
7459     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
7460     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
7461   },
7462   {
7463     /* VEX_W_0F46_P_2_LEN_1 */
7464     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
7465     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
7466   },
7467   {
7468     /* VEX_W_0F47_P_0_LEN_1 */
7469     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
7470     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
7471   },
7472   {
7473     /* VEX_W_0F47_P_2_LEN_1 */
7474     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
7475     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
7476   },
7477   {
7478     /* VEX_W_0F4A_P_0_LEN_1 */
7479     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
7480     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
7481   },
7482   {
7483     /* VEX_W_0F4A_P_2_LEN_1 */
7484     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
7485     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
7486   },
7487   {
7488     /* VEX_W_0F4B_P_0_LEN_1 */
7489     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
7490     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
7491   },
7492   {
7493     /* VEX_W_0F4B_P_2_LEN_1 */
7494     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
7495   },
7496   {
7497     /* VEX_W_0F90_P_0_LEN_0 */
7498     { "kmovw",          { MaskG, MaskE }, 0 },
7499     { "kmovq",          { MaskG, MaskE }, 0 },
7500   },
7501   {
7502     /* VEX_W_0F90_P_2_LEN_0 */
7503     { "kmovb",          { MaskG, MaskBDE }, 0 },
7504     { "kmovd",          { MaskG, MaskBDE }, 0 },
7505   },
7506   {
7507     /* VEX_W_0F91_P_0_LEN_0 */
7508     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
7509     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
7510   },
7511   {
7512     /* VEX_W_0F91_P_2_LEN_0 */
7513     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
7514     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
7515   },
7516   {
7517     /* VEX_W_0F92_P_0_LEN_0 */
7518     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
7519   },
7520   {
7521     /* VEX_W_0F92_P_2_LEN_0 */
7522     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
7523   },
7524   {
7525     /* VEX_W_0F93_P_0_LEN_0 */
7526     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
7527   },
7528   {
7529     /* VEX_W_0F93_P_2_LEN_0 */
7530     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
7531   },
7532   {
7533     /* VEX_W_0F98_P_0_LEN_0 */
7534     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
7535     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
7536   },
7537   {
7538     /* VEX_W_0F98_P_2_LEN_0 */
7539     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
7540     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
7541   },
7542   {
7543     /* VEX_W_0F99_P_0_LEN_0 */
7544     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
7545     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
7546   },
7547   {
7548     /* VEX_W_0F99_P_2_LEN_0 */
7549     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
7550     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
7551   },
7552   {
7553     /* VEX_W_0F380C  */
7554     { "vpermilps",      { XM, Vex, EXx }, PREFIX_DATA },
7555   },
7556   {
7557     /* VEX_W_0F380D  */
7558     { "vpermilpd",      { XM, Vex, EXx }, PREFIX_DATA },
7559   },
7560   {
7561     /* VEX_W_0F380E  */
7562     { "vtestps",        { XM, EXx }, PREFIX_DATA },
7563   },
7564   {
7565     /* VEX_W_0F380F  */
7566     { "vtestpd",        { XM, EXx }, PREFIX_DATA },
7567   },
7568   {
7569     /* VEX_W_0F3813 */
7570     { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7571   },
7572   {
7573     /* VEX_W_0F3816_L_1  */
7574     { "vpermps",        { XM, Vex, EXx }, PREFIX_DATA },
7575   },
7576   {
7577     /* VEX_W_0F3818 */
7578     { "vbroadcastss",   { XM, EXxmm_md }, PREFIX_DATA },
7579   },
7580   {
7581     /* VEX_W_0F3819_L_1 */
7582     { "vbroadcastsd",   { XM, EXxmm_mq }, PREFIX_DATA },
7583   },
7584   {
7585     /* VEX_W_0F381A_M_0_L_1 */
7586     { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7587   },
7588   {
7589     /* VEX_W_0F382C_M_0 */
7590     { "vmaskmovps",     { XM, Vex, Mx }, PREFIX_DATA },
7591   },
7592   {
7593     /* VEX_W_0F382D_M_0 */
7594     { "vmaskmovpd",     { XM, Vex, Mx }, PREFIX_DATA },
7595   },
7596   {
7597     /* VEX_W_0F382E_M_0 */
7598     { "vmaskmovps",     { Mx, Vex, XM }, PREFIX_DATA },
7599   },
7600   {
7601     /* VEX_W_0F382F_M_0 */
7602     { "vmaskmovpd",     { Mx, Vex, XM }, PREFIX_DATA },
7603   },
7604   {
7605     /* VEX_W_0F3836  */
7606     { "vpermd",         { XM, Vex, EXx }, PREFIX_DATA },
7607   },
7608   {
7609     /* VEX_W_0F3846 */
7610     { "vpsravd",        { XM, Vex, EXx }, PREFIX_DATA },
7611   },
7612   {
7613     /* VEX_W_0F3849_X86_64_P_0 */
7614     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
7615   },
7616   {
7617     /* VEX_W_0F3849_X86_64_P_2 */
7618     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
7619   },
7620   {
7621     /* VEX_W_0F3849_X86_64_P_3 */
7622     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
7623   },
7624   {
7625     /* VEX_W_0F384B_X86_64_P_1 */
7626     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
7627   },
7628   {
7629     /* VEX_W_0F384B_X86_64_P_2 */
7630     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
7631   },
7632   {
7633     /* VEX_W_0F384B_X86_64_P_3 */
7634     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
7635   },
7636   {
7637     /* VEX_W_0F3858 */
7638     { "vpbroadcastd", { XM, EXxmm_md }, PREFIX_DATA },
7639   },
7640   {
7641     /* VEX_W_0F3859 */
7642     { "vpbroadcastq",   { XM, EXxmm_mq }, PREFIX_DATA },
7643   },
7644   {
7645     /* VEX_W_0F385A_M_0_L_0 */
7646     { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7647   },
7648   {
7649     /* VEX_W_0F385C_X86_64_P_1 */
7650     { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
7651   },
7652   {
7653     /* VEX_W_0F385E_X86_64_P_0 */
7654     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
7655   },
7656   {
7657     /* VEX_W_0F385E_X86_64_P_1 */
7658     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
7659   },
7660   {
7661     /* VEX_W_0F385E_X86_64_P_2 */
7662     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
7663   },
7664   {
7665     /* VEX_W_0F385E_X86_64_P_3 */
7666     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
7667   },
7668   {
7669     /* VEX_W_0F3878 */
7670     { "vpbroadcastb",   { XM, EXxmm_mb }, PREFIX_DATA },
7671   },
7672   {
7673     /* VEX_W_0F3879 */
7674     { "vpbroadcastw",   { XM, EXxmm_mw }, PREFIX_DATA },
7675   },
7676   {
7677     /* VEX_W_0F38CF */
7678     { "vgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7679   },
7680   {
7681     /* VEX_W_0F3A00_L_1 */
7682     { Bad_Opcode },
7683     { "vpermq",         { XM, EXx, Ib }, PREFIX_DATA },
7684   },
7685   {
7686     /* VEX_W_0F3A01_L_1 */
7687     { Bad_Opcode },
7688     { "vpermpd",        { XM, EXx, Ib }, PREFIX_DATA },
7689   },
7690   {
7691     /* VEX_W_0F3A02 */
7692     { "vpblendd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
7693   },
7694   {
7695     /* VEX_W_0F3A04 */
7696     { "vpermilps",      { XM, EXx, Ib }, PREFIX_DATA },
7697   },
7698   {
7699     /* VEX_W_0F3A05 */
7700     { "vpermilpd",      { XM, EXx, Ib }, PREFIX_DATA },
7701   },
7702   {
7703     /* VEX_W_0F3A06_L_1 */
7704     { "vperm2f128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7705   },
7706   {
7707     /* VEX_W_0F3A18_L_1 */
7708     { "vinsertf128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7709   },
7710   {
7711     /* VEX_W_0F3A19_L_1 */
7712     { "vextractf128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7713   },
7714   {
7715     /* VEX_W_0F3A1D */
7716     { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7717   },
7718   {
7719     /* VEX_W_0F3A38_L_1 */
7720     { "vinserti128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7721   },
7722   {
7723     /* VEX_W_0F3A39_L_1 */
7724     { "vextracti128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7725   },
7726   {
7727     /* VEX_W_0F3A46_L_1 */
7728     { "vperm2i128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7729   },
7730   {
7731     /* VEX_W_0F3A4A */
7732     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7733   },
7734   {
7735     /* VEX_W_0F3A4B */
7736     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7737   },
7738   {
7739     /* VEX_W_0F3A4C */
7740     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7741   },
7742   {
7743     /* VEX_W_0F3ACE */
7744     { Bad_Opcode },
7745     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7746   },
7747   {
7748     /* VEX_W_0F3ACF */
7749     { Bad_Opcode },
7750     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, PREFIX_DATA },
7751   },
7752   /* VEX_W_0FXOP_08_85_L_0 */
7753   {
7754     { "vpmacssww",      { XM, Vex, EXx, XMVexI4 }, 0 },
7755   },
7756   /* VEX_W_0FXOP_08_86_L_0 */
7757   {
7758     { "vpmacsswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7759   },
7760   /* VEX_W_0FXOP_08_87_L_0 */
7761   {
7762     { "vpmacssdql",     { XM, Vex, EXx, XMVexI4 }, 0 },
7763   },
7764   /* VEX_W_0FXOP_08_8E_L_0 */
7765   {
7766     { "vpmacssdd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7767   },
7768   /* VEX_W_0FXOP_08_8F_L_0 */
7769   {
7770     { "vpmacssdqh",     { XM, Vex, EXx, XMVexI4 }, 0 },
7771   },
7772   /* VEX_W_0FXOP_08_95_L_0 */
7773   {
7774     { "vpmacsww",       { XM, Vex, EXx, XMVexI4 }, 0 },
7775   },
7776   /* VEX_W_0FXOP_08_96_L_0 */
7777   {
7778     { "vpmacswd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7779   },
7780   /* VEX_W_0FXOP_08_97_L_0 */
7781   {
7782     { "vpmacsdql",      { XM, Vex, EXx, XMVexI4 }, 0 },
7783   },
7784   /* VEX_W_0FXOP_08_9E_L_0 */
7785   {
7786     { "vpmacsdd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7787   },
7788   /* VEX_W_0FXOP_08_9F_L_0 */
7789   {
7790     { "vpmacsdqh",      { XM, Vex, EXx, XMVexI4 }, 0 },
7791   },
7792   /* VEX_W_0FXOP_08_A6_L_0 */
7793   {
7794     { "vpmadcsswd",     { XM, Vex, EXx, XMVexI4 }, 0 },
7795   },
7796   /* VEX_W_0FXOP_08_B6_L_0 */
7797   {
7798     { "vpmadcswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7799   },
7800   /* VEX_W_0FXOP_08_C0_L_0 */
7801   {
7802     { "vprotb",         { XM, EXx, Ib }, 0 },
7803   },
7804   /* VEX_W_0FXOP_08_C1_L_0 */
7805   {
7806     { "vprotw",         { XM, EXx, Ib }, 0 },
7807   },
7808   /* VEX_W_0FXOP_08_C2_L_0 */
7809   {
7810     { "vprotd",         { XM, EXx, Ib }, 0 },
7811   },
7812   /* VEX_W_0FXOP_08_C3_L_0 */
7813   {
7814     { "vprotq",         { XM, EXx, Ib }, 0 },
7815   },
7816   /* VEX_W_0FXOP_08_CC_L_0 */
7817   {
7818      { "vpcomb",        { XM, Vex, EXx, VPCOM }, 0 },
7819   },
7820   /* VEX_W_0FXOP_08_CD_L_0 */
7821   {
7822      { "vpcomw",        { XM, Vex, EXx, VPCOM }, 0 },
7823   },
7824   /* VEX_W_0FXOP_08_CE_L_0 */
7825   {
7826      { "vpcomd",        { XM, Vex, EXx, VPCOM }, 0 },
7827   },
7828   /* VEX_W_0FXOP_08_CF_L_0 */
7829   {
7830      { "vpcomq",        { XM, Vex, EXx, VPCOM }, 0 },
7831   },
7832   /* VEX_W_0FXOP_08_EC_L_0 */
7833   {
7834      { "vpcomub",       { XM, Vex, EXx, VPCOM }, 0 },
7835   },
7836   /* VEX_W_0FXOP_08_ED_L_0 */
7837   {
7838      { "vpcomuw",       { XM, Vex, EXx, VPCOM }, 0 },
7839   },
7840   /* VEX_W_0FXOP_08_EE_L_0 */
7841   {
7842      { "vpcomud",       { XM, Vex, EXx, VPCOM }, 0 },
7843   },
7844   /* VEX_W_0FXOP_08_EF_L_0 */
7845   {
7846      { "vpcomuq",       { XM, Vex, EXx, VPCOM }, 0 },
7847   },
7848   /* VEX_W_0FXOP_09_80 */
7849   {
7850     { "vfrczps",        { XM, EXx }, 0 },
7851   },
7852   /* VEX_W_0FXOP_09_81 */
7853   {
7854     { "vfrczpd",        { XM, EXx }, 0 },
7855   },
7856   /* VEX_W_0FXOP_09_82 */
7857   {
7858     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
7859   },
7860   /* VEX_W_0FXOP_09_83 */
7861   {
7862     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
7863   },
7864   /* VEX_W_0FXOP_09_C1_L_0 */
7865   {
7866     { "vphaddbw",       { XM, EXxmm }, 0 },
7867   },
7868   /* VEX_W_0FXOP_09_C2_L_0 */
7869   {
7870     { "vphaddbd",       { XM, EXxmm }, 0 },
7871   },
7872   /* VEX_W_0FXOP_09_C3_L_0 */
7873   {
7874     { "vphaddbq",       { XM, EXxmm }, 0 },
7875   },
7876   /* VEX_W_0FXOP_09_C6_L_0 */
7877   {
7878     { "vphaddwd",       { XM, EXxmm }, 0 },
7879   },
7880   /* VEX_W_0FXOP_09_C7_L_0 */
7881   {
7882     { "vphaddwq",       { XM, EXxmm }, 0 },
7883   },
7884   /* VEX_W_0FXOP_09_CB_L_0 */
7885   {
7886     { "vphadddq",       { XM, EXxmm }, 0 },
7887   },
7888   /* VEX_W_0FXOP_09_D1_L_0 */
7889   {
7890     { "vphaddubw",      { XM, EXxmm }, 0 },
7891   },
7892   /* VEX_W_0FXOP_09_D2_L_0 */
7893   {
7894     { "vphaddubd",      { XM, EXxmm }, 0 },
7895   },
7896   /* VEX_W_0FXOP_09_D3_L_0 */
7897   {
7898     { "vphaddubq",      { XM, EXxmm }, 0 },
7899   },
7900   /* VEX_W_0FXOP_09_D6_L_0 */
7901   {
7902     { "vphadduwd",      { XM, EXxmm }, 0 },
7903   },
7904   /* VEX_W_0FXOP_09_D7_L_0 */
7905   {
7906     { "vphadduwq",      { XM, EXxmm }, 0 },
7907   },
7908   /* VEX_W_0FXOP_09_DB_L_0 */
7909   {
7910     { "vphaddudq",      { XM, EXxmm }, 0 },
7911   },
7912   /* VEX_W_0FXOP_09_E1_L_0 */
7913   {
7914     { "vphsubbw",       { XM, EXxmm }, 0 },
7915   },
7916   /* VEX_W_0FXOP_09_E2_L_0 */
7917   {
7918     { "vphsubwd",       { XM, EXxmm }, 0 },
7919   },
7920   /* VEX_W_0FXOP_09_E3_L_0 */
7921   {
7922     { "vphsubdq",       { XM, EXxmm }, 0 },
7923   },
7924
7925 #include "i386-dis-evex-w.h"
7926 };
7927
7928 static const struct dis386 mod_table[][2] = {
7929   {
7930     /* MOD_8D */
7931     { "leaS",           { Gv, M }, 0 },
7932   },
7933   {
7934     /* MOD_C6_REG_7 */
7935     { Bad_Opcode },
7936     { RM_TABLE (RM_C6_REG_7) },
7937   },
7938   {
7939     /* MOD_C7_REG_7 */
7940     { Bad_Opcode },
7941     { RM_TABLE (RM_C7_REG_7) },
7942   },
7943   {
7944     /* MOD_FF_REG_3 */
7945     { "{l|}call^", { indirEp }, 0 },
7946   },
7947   {
7948     /* MOD_FF_REG_5 */
7949     { "{l|}jmp^", { indirEp }, 0 },
7950   },
7951   {
7952     /* MOD_0F01_REG_0 */
7953     { X86_64_TABLE (X86_64_0F01_REG_0) },
7954     { RM_TABLE (RM_0F01_REG_0) },
7955   },
7956   {
7957     /* MOD_0F01_REG_1 */
7958     { X86_64_TABLE (X86_64_0F01_REG_1) },
7959     { RM_TABLE (RM_0F01_REG_1) },
7960   },
7961   {
7962     /* MOD_0F01_REG_2 */
7963     { X86_64_TABLE (X86_64_0F01_REG_2) },
7964     { RM_TABLE (RM_0F01_REG_2) },
7965   },
7966   {
7967     /* MOD_0F01_REG_3 */
7968     { X86_64_TABLE (X86_64_0F01_REG_3) },
7969     { RM_TABLE (RM_0F01_REG_3) },
7970   },
7971   {
7972     /* MOD_0F01_REG_5 */
7973     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
7974     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
7975   },
7976   {
7977     /* MOD_0F01_REG_7 */
7978     { "invlpg",         { Mb }, 0 },
7979     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
7980   },
7981   {
7982     /* MOD_0F12_PREFIX_0 */
7983     { "movlpX",         { XM, EXq }, 0 },
7984     { "movhlps",        { XM, EXq }, 0 },
7985   },
7986   {
7987     /* MOD_0F12_PREFIX_2 */
7988     { "movlpX", { XM, EXq }, 0 },
7989   },
7990   {
7991     /* MOD_0F13 */
7992     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
7993   },
7994   {
7995     /* MOD_0F16_PREFIX_0 */
7996     { "movhpX",         { XM, EXq }, 0 },
7997     { "movlhps",        { XM, EXq }, 0 },
7998   },
7999   {
8000     /* MOD_0F16_PREFIX_2 */
8001     { "movhpX", { XM, EXq }, 0 },
8002   },
8003   {
8004     /* MOD_0F17 */
8005     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
8006   },
8007   {
8008     /* MOD_0F18_REG_0 */
8009     { "prefetchnta",    { Mb }, 0 },
8010   },
8011   {
8012     /* MOD_0F18_REG_1 */
8013     { "prefetcht0",     { Mb }, 0 },
8014   },
8015   {
8016     /* MOD_0F18_REG_2 */
8017     { "prefetcht1",     { Mb }, 0 },
8018   },
8019   {
8020     /* MOD_0F18_REG_3 */
8021     { "prefetcht2",     { Mb }, 0 },
8022   },
8023   {
8024     /* MOD_0F18_REG_4 */
8025     { "nop/reserved",   { Mb }, 0 },
8026   },
8027   {
8028     /* MOD_0F18_REG_5 */
8029     { "nop/reserved",   { Mb }, 0 },
8030   },
8031   {
8032     /* MOD_0F18_REG_6 */
8033     { "nop/reserved",   { Mb }, 0 },
8034   },
8035   {
8036     /* MOD_0F18_REG_7 */
8037     { "nop/reserved",   { Mb }, 0 },
8038   },
8039   {
8040     /* MOD_0F1A_PREFIX_0 */
8041     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
8042     { "nopQ",           { Ev }, 0 },
8043   },
8044   {
8045     /* MOD_0F1B_PREFIX_0 */
8046     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
8047     { "nopQ",           { Ev }, 0 },
8048   },
8049   {
8050     /* MOD_0F1B_PREFIX_1 */
8051     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
8052     { "nopQ",           { Ev }, 0 },
8053   },
8054   {
8055     /* MOD_0F1C_PREFIX_0 */
8056     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
8057     { "nopQ",           { Ev }, 0 },
8058   },
8059   {
8060     /* MOD_0F1E_PREFIX_1 */
8061     { "nopQ",           { Ev }, 0 },
8062     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
8063   },
8064   {
8065     /* MOD_0F2B_PREFIX_0 */
8066     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
8067   },
8068   {
8069     /* MOD_0F2B_PREFIX_1 */
8070     {"movntss",         { Md, XM }, PREFIX_OPCODE },
8071   },
8072   {
8073     /* MOD_0F2B_PREFIX_2 */
8074     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
8075   },
8076   {
8077     /* MOD_0F2B_PREFIX_3 */
8078     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
8079   },
8080   {
8081     /* MOD_0F50 */
8082     { Bad_Opcode },
8083     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
8084   },
8085   {
8086     /* MOD_0F71_REG_2 */
8087     { Bad_Opcode },
8088     { "psrlw",          { MS, Ib }, PREFIX_OPCODE },
8089   },
8090   {
8091     /* MOD_0F71_REG_4 */
8092     { Bad_Opcode },
8093     { "psraw",          { MS, Ib }, PREFIX_OPCODE },
8094   },
8095   {
8096     /* MOD_0F71_REG_6 */
8097     { Bad_Opcode },
8098     { "psllw",          { MS, Ib }, PREFIX_OPCODE },
8099   },
8100   {
8101     /* MOD_0F72_REG_2 */
8102     { Bad_Opcode },
8103     { "psrld",          { MS, Ib }, PREFIX_OPCODE },
8104   },
8105   {
8106     /* MOD_0F72_REG_4 */
8107     { Bad_Opcode },
8108     { "psrad",          { MS, Ib }, PREFIX_OPCODE },
8109   },
8110   {
8111     /* MOD_0F72_REG_6 */
8112     { Bad_Opcode },
8113     { "pslld",          { MS, Ib }, PREFIX_OPCODE },
8114   },
8115   {
8116     /* MOD_0F73_REG_2 */
8117     { Bad_Opcode },
8118     { "psrlq",          { MS, Ib }, PREFIX_OPCODE },
8119   },
8120   {
8121     /* MOD_0F73_REG_3 */
8122     { Bad_Opcode },
8123     { "psrldq",         { XS, Ib }, PREFIX_DATA },
8124   },
8125   {
8126     /* MOD_0F73_REG_6 */
8127     { Bad_Opcode },
8128     { "psllq",          { MS, Ib }, PREFIX_OPCODE },
8129   },
8130   {
8131     /* MOD_0F73_REG_7 */
8132     { Bad_Opcode },
8133     { "pslldq",         { XS, Ib }, PREFIX_DATA },
8134   },
8135   {
8136     /* MOD_0FAE_REG_0 */
8137     { "fxsave",         { FXSAVE }, 0 },
8138     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8139   },
8140   {
8141     /* MOD_0FAE_REG_1 */
8142     { "fxrstor",        { FXSAVE }, 0 },
8143     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8144   },
8145   {
8146     /* MOD_0FAE_REG_2 */
8147     { "ldmxcsr",        { Md }, 0 },
8148     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8149   },
8150   {
8151     /* MOD_0FAE_REG_3 */
8152     { "stmxcsr",        { Md }, 0 },
8153     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8154   },
8155   {
8156     /* MOD_0FAE_REG_4 */
8157     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8158     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8159   },
8160   {
8161     /* MOD_0FAE_REG_5 */
8162     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
8163     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8164   },
8165   {
8166     /* MOD_0FAE_REG_6 */
8167     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8168     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8169   },
8170   {
8171     /* MOD_0FAE_REG_7 */
8172     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8173     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8174   },
8175   {
8176     /* MOD_0FB2 */
8177     { "lssS",           { Gv, Mp }, 0 },
8178   },
8179   {
8180     /* MOD_0FB4 */
8181     { "lfsS",           { Gv, Mp }, 0 },
8182   },
8183   {
8184     /* MOD_0FB5 */
8185     { "lgsS",           { Gv, Mp }, 0 },
8186   },
8187   {
8188     /* MOD_0FC3 */
8189     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
8190   },
8191   {
8192     /* MOD_0FC7_REG_3 */
8193     { "xrstors",        { FXSAVE }, 0 },
8194   },
8195   {
8196     /* MOD_0FC7_REG_4 */
8197     { "xsavec",         { FXSAVE }, 0 },
8198   },
8199   {
8200     /* MOD_0FC7_REG_5 */
8201     { "xsaves",         { FXSAVE }, 0 },
8202   },
8203   {
8204     /* MOD_0FC7_REG_6 */
8205     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8206     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8207   },
8208   {
8209     /* MOD_0FC7_REG_7 */
8210     { "vmptrst",        { Mq }, 0 },
8211     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8212   },
8213   {
8214     /* MOD_0FD7 */
8215     { Bad_Opcode },
8216     { "pmovmskb",       { Gdq, MS }, 0 },
8217   },
8218   {
8219     /* MOD_0FE7_PREFIX_2 */
8220     { "movntdq",        { Mx, XM }, 0 },
8221   },
8222   {
8223     /* MOD_0FF0_PREFIX_3 */
8224     { "lddqu",          { XM, M }, 0 },
8225   },
8226   {
8227     /* MOD_0F382A */
8228     { "movntdqa",       { XM, Mx }, PREFIX_DATA },
8229   },
8230   {
8231     /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8232     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
8233     { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
8234   },
8235   {
8236     /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8237     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
8238   },
8239   {
8240     /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8241     { Bad_Opcode },
8242     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
8243   },
8244   {
8245     /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8246     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
8247   },
8248   {
8249     /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8250     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
8251   },
8252   {
8253     /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8254     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
8255   },
8256   {
8257     /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8258     { Bad_Opcode },
8259     { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
8260   },
8261   {
8262     /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8263     { Bad_Opcode },
8264     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
8265   },
8266   {
8267     /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8268     { Bad_Opcode },
8269     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
8270   },
8271   {
8272     /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8273     { Bad_Opcode },
8274     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
8275   },
8276   {
8277     /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8278     { Bad_Opcode },
8279     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
8280   },
8281   {
8282     /* MOD_0F38DC_PREFIX_1 */
8283     { "aesenc128kl",    { XM, M }, 0 },
8284     { "loadiwkey",      { XM, EXx }, 0 },
8285   },
8286   {
8287     /* MOD_0F38DD_PREFIX_1 */
8288     { "aesdec128kl",    { XM, M }, 0 },
8289   },
8290   {
8291     /* MOD_0F38DE_PREFIX_1 */
8292     { "aesenc256kl",    { XM, M }, 0 },
8293   },
8294   {
8295     /* MOD_0F38DF_PREFIX_1 */
8296     { "aesdec256kl",    { XM, M }, 0 },
8297   },
8298   {
8299     /* MOD_0F38F5 */
8300     { "wrussK",         { M, Gdq }, PREFIX_DATA },
8301   },
8302   {
8303     /* MOD_0F38F6_PREFIX_0 */
8304     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
8305   },
8306   {
8307     /* MOD_0F38F8_PREFIX_1 */
8308     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
8309   },
8310   {
8311     /* MOD_0F38F8_PREFIX_2 */
8312     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
8313   },
8314   {
8315     /* MOD_0F38F8_PREFIX_3 */
8316     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
8317   },
8318   {
8319     /* MOD_0F38F9 */
8320     { "movdiri",        { Edq, Gdq }, PREFIX_OPCODE },
8321   },
8322   {
8323     /* MOD_0F38FA_PREFIX_1 */
8324     { Bad_Opcode },
8325     { "encodekey128", { Gd, Ed }, 0 },
8326   },
8327   {
8328     /* MOD_0F38FB_PREFIX_1 */
8329     { Bad_Opcode },
8330     { "encodekey256", { Gd, Ed }, 0 },
8331   },
8332   {
8333     /* MOD_62_32BIT */
8334     { "bound{S|}",      { Gv, Ma }, 0 },
8335     { EVEX_TABLE (EVEX_0F) },
8336   },
8337   {
8338     /* MOD_C4_32BIT */
8339     { "lesS",           { Gv, Mp }, 0 },
8340     { VEX_C4_TABLE (VEX_0F) },
8341   },
8342   {
8343     /* MOD_C5_32BIT */
8344     { "ldsS",           { Gv, Mp }, 0 },
8345     { VEX_C5_TABLE (VEX_0F) },
8346   },
8347   {
8348     /* MOD_VEX_0F12_PREFIX_0 */
8349     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
8350     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
8351   },
8352   {
8353     /* MOD_VEX_0F12_PREFIX_2 */
8354     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
8355   },
8356   {
8357     /* MOD_VEX_0F13 */
8358     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
8359   },
8360   {
8361     /* MOD_VEX_0F16_PREFIX_0 */
8362     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
8363     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
8364   },
8365   {
8366     /* MOD_VEX_0F16_PREFIX_2 */
8367     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
8368   },
8369   {
8370     /* MOD_VEX_0F17 */
8371     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
8372   },
8373   {
8374     /* MOD_VEX_0F2B */
8375     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
8376   },
8377   {
8378     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
8379     { Bad_Opcode },
8380     { "kandw",          { MaskG, MaskVex, MaskE }, 0 },
8381   },
8382   {
8383     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
8384     { Bad_Opcode },
8385     { "kandq",          { MaskG, MaskVex, MaskE }, 0 },
8386   },
8387   {
8388     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
8389     { Bad_Opcode },
8390     { "kandb",          { MaskG, MaskVex, MaskE }, 0 },
8391   },
8392   {
8393     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
8394     { Bad_Opcode },
8395     { "kandd",          { MaskG, MaskVex, MaskE }, 0 },
8396   },
8397   {
8398     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
8399     { Bad_Opcode },
8400     { "kandnw",         { MaskG, MaskVex, MaskE }, 0 },
8401   },
8402   {
8403     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
8404     { Bad_Opcode },
8405     { "kandnq",         { MaskG, MaskVex, MaskE }, 0 },
8406   },
8407   {
8408     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
8409     { Bad_Opcode },
8410     { "kandnb",         { MaskG, MaskVex, MaskE }, 0 },
8411   },
8412   {
8413     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
8414     { Bad_Opcode },
8415     { "kandnd",         { MaskG, MaskVex, MaskE }, 0 },
8416   },
8417   {
8418     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
8419     { Bad_Opcode },
8420     { "knotw",          { MaskG, MaskE }, 0 },
8421   },
8422   {
8423     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
8424     { Bad_Opcode },
8425     { "knotq",          { MaskG, MaskE }, 0 },
8426   },
8427   {
8428     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
8429     { Bad_Opcode },
8430     { "knotb",          { MaskG, MaskE }, 0 },
8431   },
8432   {
8433     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
8434     { Bad_Opcode },
8435     { "knotd",          { MaskG, MaskE }, 0 },
8436   },
8437   {
8438     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
8439     { Bad_Opcode },
8440     { "korw",       { MaskG, MaskVex, MaskE }, 0 },
8441   },
8442   {
8443     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
8444     { Bad_Opcode },
8445     { "korq",       { MaskG, MaskVex, MaskE }, 0 },
8446   },
8447   {
8448     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
8449     { Bad_Opcode },
8450     { "korb",       { MaskG, MaskVex, MaskE }, 0 },
8451   },
8452   {
8453     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
8454     { Bad_Opcode },
8455     { "kord",       { MaskG, MaskVex, MaskE }, 0 },
8456   },
8457  {
8458     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
8459     { Bad_Opcode },
8460     { "kxnorw",     { MaskG, MaskVex, MaskE }, 0 },
8461   },
8462   {
8463     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
8464     { Bad_Opcode },
8465     { "kxnorq",     { MaskG, MaskVex, MaskE }, 0 },
8466   },
8467   {
8468     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
8469     { Bad_Opcode },
8470     { "kxnorb",     { MaskG, MaskVex, MaskE }, 0 },
8471   },
8472   {
8473     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
8474     { Bad_Opcode },
8475     { "kxnord",     { MaskG, MaskVex, MaskE }, 0 },
8476   },
8477   {
8478     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
8479     { Bad_Opcode },
8480     { "kxorw",      { MaskG, MaskVex, MaskE }, 0 },
8481   },
8482   {
8483     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
8484     { Bad_Opcode },
8485     { "kxorq",      { MaskG, MaskVex, MaskE }, 0 },
8486   },
8487   {
8488     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
8489     { Bad_Opcode },
8490     { "kxorb",      { MaskG, MaskVex, MaskE }, 0 },
8491   },
8492   {
8493     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
8494     { Bad_Opcode },
8495     { "kxord",      { MaskG, MaskVex, MaskE }, 0 },
8496   },
8497   {
8498     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
8499     { Bad_Opcode },
8500     { "kaddw",          { MaskG, MaskVex, MaskE }, 0 },
8501   },
8502   {
8503     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
8504     { Bad_Opcode },
8505     { "kaddq",          { MaskG, MaskVex, MaskE }, 0 },
8506   },
8507   {
8508     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
8509     { Bad_Opcode },
8510     { "kaddb",          { MaskG, MaskVex, MaskE }, 0 },
8511   },
8512   {
8513     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
8514     { Bad_Opcode },
8515     { "kaddd",          { MaskG, MaskVex, MaskE }, 0 },
8516   },
8517   {
8518     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
8519     { Bad_Opcode },
8520     { "kunpckwd",   { MaskG, MaskVex, MaskE }, 0 },
8521   },
8522   {
8523     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
8524     { Bad_Opcode },
8525     { "kunpckdq",   { MaskG, MaskVex, MaskE }, 0 },
8526   },
8527   {
8528     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
8529     { Bad_Opcode },
8530     { "kunpckbw",   { MaskG, MaskVex, MaskE }, 0 },
8531   },
8532   {
8533     /* MOD_VEX_0F50 */
8534     { Bad_Opcode },
8535     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
8536   },
8537   {
8538     /* MOD_VEX_0F71_REG_2 */
8539     { Bad_Opcode },
8540     { "vpsrlw",         { Vex, XS, Ib }, PREFIX_DATA },
8541   },
8542   {
8543     /* MOD_VEX_0F71_REG_4 */
8544     { Bad_Opcode },
8545     { "vpsraw",         { Vex, XS, Ib }, PREFIX_DATA },
8546   },
8547   {
8548     /* MOD_VEX_0F71_REG_6 */
8549     { Bad_Opcode },
8550     { "vpsllw",         { Vex, XS, Ib }, PREFIX_DATA },
8551   },
8552   {
8553     /* MOD_VEX_0F72_REG_2 */
8554     { Bad_Opcode },
8555     { "vpsrld",         { Vex, XS, Ib }, PREFIX_DATA },
8556   },
8557   {
8558     /* MOD_VEX_0F72_REG_4 */
8559     { Bad_Opcode },
8560     { "vpsrad",         { Vex, XS, Ib }, PREFIX_DATA },
8561   },
8562   {
8563     /* MOD_VEX_0F72_REG_6 */
8564     { Bad_Opcode },
8565     { "vpslld",         { Vex, XS, Ib }, PREFIX_DATA },
8566   },
8567   {
8568     /* MOD_VEX_0F73_REG_2 */
8569     { Bad_Opcode },
8570     { "vpsrlq",         { Vex, XS, Ib }, PREFIX_DATA },
8571   },
8572   {
8573     /* MOD_VEX_0F73_REG_3 */
8574     { Bad_Opcode },
8575     { "vpsrldq",        { Vex, XS, Ib }, PREFIX_DATA },
8576   },
8577   {
8578     /* MOD_VEX_0F73_REG_6 */
8579     { Bad_Opcode },
8580     { "vpsllq",         { Vex, XS, Ib }, PREFIX_DATA },
8581   },
8582   {
8583     /* MOD_VEX_0F73_REG_7 */
8584     { Bad_Opcode },
8585     { "vpslldq",        { Vex, XS, Ib }, PREFIX_DATA },
8586   },
8587   {
8588     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
8589     { "kmovw",          { Ew, MaskG }, 0 },
8590     { Bad_Opcode },
8591   },
8592   {
8593     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
8594     { "kmovq",          { Eq, MaskG }, 0 },
8595     { Bad_Opcode },
8596   },
8597   {
8598     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
8599     { "kmovb",          { Eb, MaskG }, 0 },
8600     { Bad_Opcode },
8601   },
8602   {
8603     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
8604     { "kmovd",          { Ed, MaskG }, 0 },
8605     { Bad_Opcode },
8606   },
8607   {
8608     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
8609     { Bad_Opcode },
8610     { "kmovw",          { MaskG, Edq }, 0 },
8611   },
8612   {
8613     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
8614     { Bad_Opcode },
8615     { "kmovb",          { MaskG, Edq }, 0 },
8616   },
8617   {
8618     /* MOD_VEX_0F92_P_3_LEN_0 */
8619     { Bad_Opcode },
8620     { "kmovK",          { MaskG, Edq }, 0 },
8621   },
8622   {
8623     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
8624     { Bad_Opcode },
8625     { "kmovw",          { Gdq, MaskE }, 0 },
8626   },
8627   {
8628     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
8629     { Bad_Opcode },
8630     { "kmovb",          { Gdq, MaskE }, 0 },
8631   },
8632   {
8633     /* MOD_VEX_0F93_P_3_LEN_0 */
8634     { Bad_Opcode },
8635     { "kmovK",          { Gdq, MaskE }, 0 },
8636   },
8637   {
8638     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
8639     { Bad_Opcode },
8640     { "kortestw", { MaskG, MaskE }, 0 },
8641   },
8642   {
8643     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
8644     { Bad_Opcode },
8645     { "kortestq", { MaskG, MaskE }, 0 },
8646   },
8647   {
8648     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
8649     { Bad_Opcode },
8650     { "kortestb", { MaskG, MaskE }, 0 },
8651   },
8652   {
8653     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
8654     { Bad_Opcode },
8655     { "kortestd", { MaskG, MaskE }, 0 },
8656   },
8657   {
8658     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
8659     { Bad_Opcode },
8660     { "ktestw", { MaskG, MaskE }, 0 },
8661   },
8662   {
8663     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
8664     { Bad_Opcode },
8665     { "ktestq", { MaskG, MaskE }, 0 },
8666   },
8667   {
8668     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
8669     { Bad_Opcode },
8670     { "ktestb", { MaskG, MaskE }, 0 },
8671   },
8672   {
8673     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
8674     { Bad_Opcode },
8675     { "ktestd", { MaskG, MaskE }, 0 },
8676   },
8677   {
8678     /* MOD_VEX_0FAE_REG_2 */
8679     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
8680   },
8681   {
8682     /* MOD_VEX_0FAE_REG_3 */
8683     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
8684   },
8685   {
8686     /* MOD_VEX_0FD7 */
8687     { Bad_Opcode },
8688     { "vpmovmskb",      { Gdq, XS }, PREFIX_DATA },
8689   },
8690   {
8691     /* MOD_VEX_0FE7 */
8692     { "vmovntdq",       { Mx, XM }, PREFIX_DATA },
8693   },
8694   {
8695     /* MOD_VEX_0FF0_PREFIX_3 */
8696     { "vlddqu",         { XM, M }, 0 },
8697   },
8698   {
8699     /* MOD_VEX_0F381A */
8700     { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) },
8701   },
8702   {
8703     /* MOD_VEX_0F382A */
8704     { "vmovntdqa",      { XM, Mx }, PREFIX_DATA },
8705   },
8706   {
8707     /* MOD_VEX_0F382C */
8708     { VEX_W_TABLE (VEX_W_0F382C_M_0) },
8709   },
8710   {
8711     /* MOD_VEX_0F382D */
8712     { VEX_W_TABLE (VEX_W_0F382D_M_0) },
8713   },
8714   {
8715     /* MOD_VEX_0F382E */
8716     { VEX_W_TABLE (VEX_W_0F382E_M_0) },
8717   },
8718   {
8719     /* MOD_VEX_0F382F */
8720     { VEX_W_TABLE (VEX_W_0F382F_M_0) },
8721   },
8722   {
8723     /* MOD_VEX_0F385A */
8724     { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) },
8725   },
8726   {
8727     /* MOD_VEX_0F388C */
8728     { "vpmaskmov%DQ",   { XM, Vex, Mx }, PREFIX_DATA },
8729   },
8730   {
8731     /* MOD_VEX_0F388E */
8732     { "vpmaskmov%DQ",   { Mx, Vex, XM }, PREFIX_DATA },
8733   },
8734   {
8735     /* MOD_VEX_0F3A30_L_0 */
8736     { Bad_Opcode },
8737     { "kshiftr%BW",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8738   },
8739   {
8740     /* MOD_VEX_0F3A31_L_0 */
8741     { Bad_Opcode },
8742     { "kshiftr%DQ",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8743   },
8744   {
8745     /* MOD_VEX_0F3A32_L_0 */
8746     { Bad_Opcode },
8747     { "kshiftl%BW",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8748   },
8749   {
8750     /* MOD_VEX_0F3A33_L_0 */
8751     { Bad_Opcode },
8752     { "kshiftl%DQ",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8753   },
8754   {
8755     /* MOD_VEX_0FXOP_09_12 */
8756     { Bad_Opcode },
8757     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
8758   },
8759
8760 #include "i386-dis-evex-mod.h"
8761 };
8762
8763 static const struct dis386 rm_table[][8] = {
8764   {
8765     /* RM_C6_REG_7 */
8766     { "xabort",         { Skip_MODRM, Ib }, 0 },
8767   },
8768   {
8769     /* RM_C7_REG_7 */
8770     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
8771   },
8772   {
8773     /* RM_0F01_REG_0 */
8774     { "enclv",          { Skip_MODRM }, 0 },
8775     { "vmcall",         { Skip_MODRM }, 0 },
8776     { "vmlaunch",       { Skip_MODRM }, 0 },
8777     { "vmresume",       { Skip_MODRM }, 0 },
8778     { "vmxoff",         { Skip_MODRM }, 0 },
8779     { "pconfig",        { Skip_MODRM }, 0 },
8780   },
8781   {
8782     /* RM_0F01_REG_1 */
8783     { "monitor",        { { OP_Monitor, 0 } }, 0 },
8784     { "mwait",          { { OP_Mwait, 0 } }, 0 },
8785     { "clac",           { Skip_MODRM }, 0 },
8786     { "stac",           { Skip_MODRM }, 0 },
8787     { Bad_Opcode },
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     { "encls",          { Skip_MODRM }, 0 },
8791   },
8792   {
8793     /* RM_0F01_REG_2 */
8794     { "xgetbv",         { Skip_MODRM }, 0 },
8795     { "xsetbv",         { Skip_MODRM }, 0 },
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     { "vmfunc",         { Skip_MODRM }, 0 },
8799     { "xend",           { Skip_MODRM }, 0 },
8800     { "xtest",          { Skip_MODRM }, 0 },
8801     { "enclu",          { Skip_MODRM }, 0 },
8802   },
8803   {
8804     /* RM_0F01_REG_3 */
8805     { "vmrun",          { Skip_MODRM }, 0 },
8806     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8807     { "vmload",         { Skip_MODRM }, 0 },
8808     { "vmsave",         { Skip_MODRM }, 0 },
8809     { "stgi",           { Skip_MODRM }, 0 },
8810     { "clgi",           { Skip_MODRM }, 0 },
8811     { "skinit",         { Skip_MODRM }, 0 },
8812     { "invlpga",        { Skip_MODRM }, 0 },
8813   },
8814   {
8815     /* RM_0F01_REG_5_MOD_3 */
8816     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8817     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8818     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { "rdpkru",         { Skip_MODRM }, 0 },
8823     { "wrpkru",         { Skip_MODRM }, 0 },
8824   },
8825   {
8826     /* RM_0F01_REG_7_MOD_3 */
8827     { "swapgs",         { Skip_MODRM }, 0  },
8828     { "rdtscp",         { Skip_MODRM }, 0  },
8829     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8830     { "mwaitx",         { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8831     { "clzero",         { Skip_MODRM }, 0  },
8832     { "rdpru",          { Skip_MODRM }, 0  },
8833   },
8834   {
8835     /* RM_0F1E_P_1_MOD_3_REG_7 */
8836     { "nopQ",           { Ev }, 0 },
8837     { "nopQ",           { Ev }, 0 },
8838     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
8839     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
8840     { "nopQ",           { Ev }, 0 },
8841     { "nopQ",           { Ev }, 0 },
8842     { "nopQ",           { Ev }, 0 },
8843     { "nopQ",           { Ev }, 0 },
8844   },
8845   {
8846     /* RM_0FAE_REG_6_MOD_3 */
8847     { "mfence",         { Skip_MODRM }, 0 },
8848   },
8849   {
8850     /* RM_0FAE_REG_7_MOD_3 */
8851     { "sfence",         { Skip_MODRM }, 0 },
8852
8853   },
8854   {
8855     /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
8856     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
8857   },
8858 };
8859
8860 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8861
8862 /* We use the high bit to indicate different name for the same
8863    prefix.  */
8864 #define REP_PREFIX      (0xf3 | 0x100)
8865 #define XACQUIRE_PREFIX (0xf2 | 0x200)
8866 #define XRELEASE_PREFIX (0xf3 | 0x400)
8867 #define BND_PREFIX      (0xf2 | 0x400)
8868 #define NOTRACK_PREFIX  (0x3e | 0x100)
8869
8870 /* Remember if the current op is a jump instruction.  */
8871 static bfd_boolean op_is_jump = FALSE;
8872
8873 static int
8874 ckprefix (void)
8875 {
8876   int newrex, i, length;
8877   rex = 0;
8878   prefixes = 0;
8879   used_prefixes = 0;
8880   rex_used = 0;
8881   last_lock_prefix = -1;
8882   last_repz_prefix = -1;
8883   last_repnz_prefix = -1;
8884   last_data_prefix = -1;
8885   last_addr_prefix = -1;
8886   last_rex_prefix = -1;
8887   last_seg_prefix = -1;
8888   fwait_prefix = -1;
8889   active_seg_prefix = 0;
8890   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
8891     all_prefixes[i] = 0;
8892   i = 0;
8893   length = 0;
8894   /* The maximum instruction length is 15bytes.  */
8895   while (length < MAX_CODE_LENGTH - 1)
8896     {
8897       FETCH_DATA (the_info, codep + 1);
8898       newrex = 0;
8899       switch (*codep)
8900         {
8901         /* REX prefixes family.  */
8902         case 0x40:
8903         case 0x41:
8904         case 0x42:
8905         case 0x43:
8906         case 0x44:
8907         case 0x45:
8908         case 0x46:
8909         case 0x47:
8910         case 0x48:
8911         case 0x49:
8912         case 0x4a:
8913         case 0x4b:
8914         case 0x4c:
8915         case 0x4d:
8916         case 0x4e:
8917         case 0x4f:
8918           if (address_mode == mode_64bit)
8919             newrex = *codep;
8920           else
8921             return 1;
8922           last_rex_prefix = i;
8923           break;
8924         case 0xf3:
8925           prefixes |= PREFIX_REPZ;
8926           last_repz_prefix = i;
8927           break;
8928         case 0xf2:
8929           prefixes |= PREFIX_REPNZ;
8930           last_repnz_prefix = i;
8931           break;
8932         case 0xf0:
8933           prefixes |= PREFIX_LOCK;
8934           last_lock_prefix = i;
8935           break;
8936         case 0x2e:
8937           prefixes |= PREFIX_CS;
8938           last_seg_prefix = i;
8939           active_seg_prefix = PREFIX_CS;
8940           break;
8941         case 0x36:
8942           prefixes |= PREFIX_SS;
8943           last_seg_prefix = i;
8944           active_seg_prefix = PREFIX_SS;
8945           break;
8946         case 0x3e:
8947           prefixes |= PREFIX_DS;
8948           last_seg_prefix = i;
8949           active_seg_prefix = PREFIX_DS;
8950           break;
8951         case 0x26:
8952           prefixes |= PREFIX_ES;
8953           last_seg_prefix = i;
8954           active_seg_prefix = PREFIX_ES;
8955           break;
8956         case 0x64:
8957           prefixes |= PREFIX_FS;
8958           last_seg_prefix = i;
8959           active_seg_prefix = PREFIX_FS;
8960           break;
8961         case 0x65:
8962           prefixes |= PREFIX_GS;
8963           last_seg_prefix = i;
8964           active_seg_prefix = PREFIX_GS;
8965           break;
8966         case 0x66:
8967           prefixes |= PREFIX_DATA;
8968           last_data_prefix = i;
8969           break;
8970         case 0x67:
8971           prefixes |= PREFIX_ADDR;
8972           last_addr_prefix = i;
8973           break;
8974         case FWAIT_OPCODE:
8975           /* fwait is really an instruction.  If there are prefixes
8976              before the fwait, they belong to the fwait, *not* to the
8977              following instruction.  */
8978           fwait_prefix = i;
8979           if (prefixes || rex)
8980             {
8981               prefixes |= PREFIX_FWAIT;
8982               codep++;
8983               /* This ensures that the previous REX prefixes are noticed
8984                  as unused prefixes, as in the return case below.  */
8985               rex_used = rex;
8986               return 1;
8987             }
8988           prefixes = PREFIX_FWAIT;
8989           break;
8990         default:
8991           return 1;
8992         }
8993       /* Rex is ignored when followed by another prefix.  */
8994       if (rex)
8995         {
8996           rex_used = rex;
8997           return 1;
8998         }
8999       if (*codep != FWAIT_OPCODE)
9000         all_prefixes[i++] = *codep;
9001       rex = newrex;
9002       codep++;
9003       length++;
9004     }
9005   return 0;
9006 }
9007
9008 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
9009    prefix byte.  */
9010
9011 static const char *
9012 prefix_name (int pref, int sizeflag)
9013 {
9014   static const char *rexes [16] =
9015     {
9016       "rex",            /* 0x40 */
9017       "rex.B",          /* 0x41 */
9018       "rex.X",          /* 0x42 */
9019       "rex.XB",         /* 0x43 */
9020       "rex.R",          /* 0x44 */
9021       "rex.RB",         /* 0x45 */
9022       "rex.RX",         /* 0x46 */
9023       "rex.RXB",        /* 0x47 */
9024       "rex.W",          /* 0x48 */
9025       "rex.WB",         /* 0x49 */
9026       "rex.WX",         /* 0x4a */
9027       "rex.WXB",        /* 0x4b */
9028       "rex.WR",         /* 0x4c */
9029       "rex.WRB",        /* 0x4d */
9030       "rex.WRX",        /* 0x4e */
9031       "rex.WRXB",       /* 0x4f */
9032     };
9033
9034   switch (pref)
9035     {
9036     /* REX prefixes family.  */
9037     case 0x40:
9038     case 0x41:
9039     case 0x42:
9040     case 0x43:
9041     case 0x44:
9042     case 0x45:
9043     case 0x46:
9044     case 0x47:
9045     case 0x48:
9046     case 0x49:
9047     case 0x4a:
9048     case 0x4b:
9049     case 0x4c:
9050     case 0x4d:
9051     case 0x4e:
9052     case 0x4f:
9053       return rexes [pref - 0x40];
9054     case 0xf3:
9055       return "repz";
9056     case 0xf2:
9057       return "repnz";
9058     case 0xf0:
9059       return "lock";
9060     case 0x2e:
9061       return "cs";
9062     case 0x36:
9063       return "ss";
9064     case 0x3e:
9065       return "ds";
9066     case 0x26:
9067       return "es";
9068     case 0x64:
9069       return "fs";
9070     case 0x65:
9071       return "gs";
9072     case 0x66:
9073       return (sizeflag & DFLAG) ? "data16" : "data32";
9074     case 0x67:
9075       if (address_mode == mode_64bit)
9076         return (sizeflag & AFLAG) ? "addr32" : "addr64";
9077       else
9078         return (sizeflag & AFLAG) ? "addr16" : "addr32";
9079     case FWAIT_OPCODE:
9080       return "fwait";
9081     case REP_PREFIX:
9082       return "rep";
9083     case XACQUIRE_PREFIX:
9084       return "xacquire";
9085     case XRELEASE_PREFIX:
9086       return "xrelease";
9087     case BND_PREFIX:
9088       return "bnd";
9089     case NOTRACK_PREFIX:
9090       return "notrack";
9091     default:
9092       return NULL;
9093     }
9094 }
9095
9096 static char op_out[MAX_OPERANDS][100];
9097 static int op_ad, op_index[MAX_OPERANDS];
9098 static int two_source_ops;
9099 static bfd_vma op_address[MAX_OPERANDS];
9100 static bfd_vma op_riprel[MAX_OPERANDS];
9101 static bfd_vma start_pc;
9102
9103 /*
9104  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9105  *   (see topic "Redundant prefixes" in the "Differences from 8086"
9106  *   section of the "Virtual 8086 Mode" chapter.)
9107  * 'pc' should be the address of this instruction, it will
9108  *   be used to print the target address if this is a relative jump or call
9109  * The function returns the length of this instruction in bytes.
9110  */
9111
9112 static char intel_syntax;
9113 static char intel_mnemonic = !SYSV386_COMPAT;
9114 static char open_char;
9115 static char close_char;
9116 static char separator_char;
9117 static char scale_char;
9118
9119 enum x86_64_isa
9120 {
9121   amd64 = 1,
9122   intel64
9123 };
9124
9125 static enum x86_64_isa isa64;
9126
9127 /* Here for backwards compatibility.  When gdb stops using
9128    print_insn_i386_att and print_insn_i386_intel these functions can
9129    disappear, and print_insn_i386 be merged into print_insn.  */
9130 int
9131 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9132 {
9133   intel_syntax = 0;
9134
9135   return print_insn (pc, info);
9136 }
9137
9138 int
9139 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9140 {
9141   intel_syntax = 1;
9142
9143   return print_insn (pc, info);
9144 }
9145
9146 int
9147 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9148 {
9149   intel_syntax = -1;
9150
9151   return print_insn (pc, info);
9152 }
9153
9154 void
9155 print_i386_disassembler_options (FILE *stream)
9156 {
9157   fprintf (stream, _("\n\
9158 The following i386/x86-64 specific disassembler options are supported for use\n\
9159 with the -M switch (multiple options should be separated by commas):\n"));
9160
9161   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
9162   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
9163   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
9164   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
9165   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
9166   fprintf (stream, _("  att-mnemonic\n"
9167                      "              Display instruction in AT&T mnemonic\n"));
9168   fprintf (stream, _("  intel-mnemonic\n"
9169                      "              Display instruction in Intel mnemonic\n"));
9170   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
9171   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
9172   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
9173   fprintf (stream, _("  data32      Assume 32bit data size\n"));
9174   fprintf (stream, _("  data16      Assume 16bit data size\n"));
9175   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
9176   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
9177   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
9178 }
9179
9180 /* Bad opcode.  */
9181 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
9182
9183 /* Get a pointer to struct dis386 with a valid name.  */
9184
9185 static const struct dis386 *
9186 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
9187 {
9188   int vindex, vex_table_index;
9189
9190   if (dp->name != NULL)
9191     return dp;
9192
9193   switch (dp->op[0].bytemode)
9194     {
9195     case USE_REG_TABLE:
9196       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
9197       break;
9198
9199     case USE_MOD_TABLE:
9200       vindex = modrm.mod == 0x3 ? 1 : 0;
9201       dp = &mod_table[dp->op[1].bytemode][vindex];
9202       break;
9203
9204     case USE_RM_TABLE:
9205       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
9206       break;
9207
9208     case USE_PREFIX_TABLE:
9209       if (need_vex)
9210         {
9211           /* The prefix in VEX is implicit.  */
9212           switch (vex.prefix)
9213             {
9214             case 0:
9215               vindex = 0;
9216               break;
9217             case REPE_PREFIX_OPCODE:
9218               vindex = 1;
9219               break;
9220             case DATA_PREFIX_OPCODE:
9221               vindex = 2;
9222               break;
9223             case REPNE_PREFIX_OPCODE:
9224               vindex = 3;
9225               break;
9226             default:
9227               abort ();
9228               break;
9229             }
9230         }
9231       else
9232         {
9233           int last_prefix = -1;
9234           int prefix = 0;
9235           vindex = 0;
9236           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
9237              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
9238              last one wins.  */
9239           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9240             {
9241               if (last_repz_prefix > last_repnz_prefix)
9242                 {
9243                   vindex = 1;
9244                   prefix = PREFIX_REPZ;
9245                   last_prefix = last_repz_prefix;
9246                 }
9247               else
9248                 {
9249                   vindex = 3;
9250                   prefix = PREFIX_REPNZ;
9251                   last_prefix = last_repnz_prefix;
9252                 }
9253
9254               /* Check if prefix should be ignored.  */
9255               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
9256                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
9257                    & prefix) != 0)
9258                 vindex = 0;
9259             }
9260
9261           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
9262             {
9263               vindex = 2;
9264               prefix = PREFIX_DATA;
9265               last_prefix = last_data_prefix;
9266             }
9267
9268           if (vindex != 0)
9269             {
9270               used_prefixes |= prefix;
9271               all_prefixes[last_prefix] = 0;
9272             }
9273         }
9274       dp = &prefix_table[dp->op[1].bytemode][vindex];
9275       break;
9276
9277     case USE_X86_64_TABLE:
9278       vindex = address_mode == mode_64bit ? 1 : 0;
9279       dp = &x86_64_table[dp->op[1].bytemode][vindex];
9280       break;
9281
9282     case USE_3BYTE_TABLE:
9283       FETCH_DATA (info, codep + 2);
9284       vindex = *codep++;
9285       dp = &three_byte_table[dp->op[1].bytemode][vindex];
9286       end_codep = codep;
9287       modrm.mod = (*codep >> 6) & 3;
9288       modrm.reg = (*codep >> 3) & 7;
9289       modrm.rm = *codep & 7;
9290       break;
9291
9292     case USE_VEX_LEN_TABLE:
9293       if (!need_vex)
9294         abort ();
9295
9296       switch (vex.length)
9297         {
9298         case 128:
9299           vindex = 0;
9300           break;
9301         case 256:
9302           vindex = 1;
9303           break;
9304         default:
9305           abort ();
9306           break;
9307         }
9308
9309       dp = &vex_len_table[dp->op[1].bytemode][vindex];
9310       break;
9311
9312     case USE_EVEX_LEN_TABLE:
9313       if (!vex.evex)
9314         abort ();
9315
9316       switch (vex.length)
9317         {
9318         case 128:
9319           vindex = 0;
9320           break;
9321         case 256:
9322           vindex = 1;
9323           break;
9324         case 512:
9325           vindex = 2;
9326           break;
9327         default:
9328           abort ();
9329           break;
9330         }
9331
9332       dp = &evex_len_table[dp->op[1].bytemode][vindex];
9333       break;
9334
9335     case USE_XOP_8F_TABLE:
9336       FETCH_DATA (info, codep + 3);
9337       rex = ~(*codep >> 5) & 0x7;
9338
9339       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
9340       switch ((*codep & 0x1f))
9341         {
9342         default:
9343           dp = &bad_opcode;
9344           return dp;
9345         case 0x8:
9346           vex_table_index = XOP_08;
9347           break;
9348         case 0x9:
9349           vex_table_index = XOP_09;
9350           break;
9351         case 0xa:
9352           vex_table_index = XOP_0A;
9353           break;
9354         }
9355       codep++;
9356       vex.w = *codep & 0x80;
9357       if (vex.w && address_mode == mode_64bit)
9358         rex |= REX_W;
9359
9360       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9361       if (address_mode != mode_64bit)
9362         {
9363           /* In 16/32-bit mode REX_B is silently ignored.  */
9364           rex &= ~REX_B;
9365         }
9366
9367       vex.length = (*codep & 0x4) ? 256 : 128;
9368       switch ((*codep & 0x3))
9369         {
9370         case 0:
9371           break;
9372         case 1:
9373           vex.prefix = DATA_PREFIX_OPCODE;
9374           break;
9375         case 2:
9376           vex.prefix = REPE_PREFIX_OPCODE;
9377           break;
9378         case 3:
9379           vex.prefix = REPNE_PREFIX_OPCODE;
9380           break;
9381         }
9382       need_vex = 1;
9383       codep++;
9384       vindex = *codep++;
9385       dp = &xop_table[vex_table_index][vindex];
9386
9387       end_codep = codep;
9388       FETCH_DATA (info, codep + 1);
9389       modrm.mod = (*codep >> 6) & 3;
9390       modrm.reg = (*codep >> 3) & 7;
9391       modrm.rm = *codep & 7;
9392
9393       /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9394          having to decode the bits for every otherwise valid encoding.  */
9395       if (vex.prefix)
9396         return &bad_opcode;
9397       break;
9398
9399     case USE_VEX_C4_TABLE:
9400       /* VEX prefix.  */
9401       FETCH_DATA (info, codep + 3);
9402       rex = ~(*codep >> 5) & 0x7;
9403       switch ((*codep & 0x1f))
9404         {
9405         default:
9406           dp = &bad_opcode;
9407           return dp;
9408         case 0x1:
9409           vex_table_index = VEX_0F;
9410           break;
9411         case 0x2:
9412           vex_table_index = VEX_0F38;
9413           break;
9414         case 0x3:
9415           vex_table_index = VEX_0F3A;
9416           break;
9417         }
9418       codep++;
9419       vex.w = *codep & 0x80;
9420       if (address_mode == mode_64bit)
9421         {
9422           if (vex.w)
9423             rex |= REX_W;
9424         }
9425       else
9426         {
9427           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9428              is ignored, other REX bits are 0 and the highest bit in
9429              VEX.vvvv is also ignored (but we mustn't clear it here).  */
9430           rex = 0;
9431         }
9432       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9433       vex.length = (*codep & 0x4) ? 256 : 128;
9434       switch ((*codep & 0x3))
9435         {
9436         case 0:
9437           break;
9438         case 1:
9439           vex.prefix = DATA_PREFIX_OPCODE;
9440           break;
9441         case 2:
9442           vex.prefix = REPE_PREFIX_OPCODE;
9443           break;
9444         case 3:
9445           vex.prefix = REPNE_PREFIX_OPCODE;
9446           break;
9447         }
9448       need_vex = 1;
9449       codep++;
9450       vindex = *codep++;
9451       dp = &vex_table[vex_table_index][vindex];
9452       end_codep = codep;
9453       /* There is no MODRM byte for VEX0F 77.  */
9454       if (vex_table_index != VEX_0F || vindex != 0x77)
9455         {
9456           FETCH_DATA (info, codep + 1);
9457           modrm.mod = (*codep >> 6) & 3;
9458           modrm.reg = (*codep >> 3) & 7;
9459           modrm.rm = *codep & 7;
9460         }
9461       break;
9462
9463     case USE_VEX_C5_TABLE:
9464       /* VEX prefix.  */
9465       FETCH_DATA (info, codep + 2);
9466       rex = (*codep & 0x80) ? 0 : REX_R;
9467
9468       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9469          VEX.vvvv is 1.  */
9470       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9471       vex.length = (*codep & 0x4) ? 256 : 128;
9472       switch ((*codep & 0x3))
9473         {
9474         case 0:
9475           break;
9476         case 1:
9477           vex.prefix = DATA_PREFIX_OPCODE;
9478           break;
9479         case 2:
9480           vex.prefix = REPE_PREFIX_OPCODE;
9481           break;
9482         case 3:
9483           vex.prefix = REPNE_PREFIX_OPCODE;
9484           break;
9485         }
9486       need_vex = 1;
9487       codep++;
9488       vindex = *codep++;
9489       dp = &vex_table[dp->op[1].bytemode][vindex];
9490       end_codep = codep;
9491       /* There is no MODRM byte for VEX 77.  */
9492       if (vindex != 0x77)
9493         {
9494           FETCH_DATA (info, codep + 1);
9495           modrm.mod = (*codep >> 6) & 3;
9496           modrm.reg = (*codep >> 3) & 7;
9497           modrm.rm = *codep & 7;
9498         }
9499       break;
9500
9501     case USE_VEX_W_TABLE:
9502       if (!need_vex)
9503         abort ();
9504
9505       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
9506       break;
9507
9508     case USE_EVEX_TABLE:
9509       two_source_ops = 0;
9510       /* EVEX prefix.  */
9511       vex.evex = 1;
9512       FETCH_DATA (info, codep + 4);
9513       /* The first byte after 0x62.  */
9514       rex = ~(*codep >> 5) & 0x7;
9515       vex.r = *codep & 0x10;
9516       switch ((*codep & 0xf))
9517         {
9518         default:
9519           return &bad_opcode;
9520         case 0x1:
9521           vex_table_index = EVEX_0F;
9522           break;
9523         case 0x2:
9524           vex_table_index = EVEX_0F38;
9525           break;
9526         case 0x3:
9527           vex_table_index = EVEX_0F3A;
9528           break;
9529         }
9530
9531       /* The second byte after 0x62.  */
9532       codep++;
9533       vex.w = *codep & 0x80;
9534       if (vex.w && address_mode == mode_64bit)
9535         rex |= REX_W;
9536
9537       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9538
9539       /* The U bit.  */
9540       if (!(*codep & 0x4))
9541         return &bad_opcode;
9542
9543       switch ((*codep & 0x3))
9544         {
9545         case 0:
9546           break;
9547         case 1:
9548           vex.prefix = DATA_PREFIX_OPCODE;
9549           break;
9550         case 2:
9551           vex.prefix = REPE_PREFIX_OPCODE;
9552           break;
9553         case 3:
9554           vex.prefix = REPNE_PREFIX_OPCODE;
9555           break;
9556         }
9557
9558       /* The third byte after 0x62.  */
9559       codep++;
9560
9561       /* Remember the static rounding bits.  */
9562       vex.ll = (*codep >> 5) & 3;
9563       vex.b = (*codep & 0x10) != 0;
9564
9565       vex.v = *codep & 0x8;
9566       vex.mask_register_specifier = *codep & 0x7;
9567       vex.zeroing = *codep & 0x80;
9568
9569       if (address_mode != mode_64bit)
9570         {
9571           /* In 16/32-bit mode silently ignore following bits.  */
9572           rex &= ~REX_B;
9573           vex.r = 1;
9574           vex.v = 1;
9575         }
9576
9577       need_vex = 1;
9578       codep++;
9579       vindex = *codep++;
9580       dp = &evex_table[vex_table_index][vindex];
9581       end_codep = codep;
9582       FETCH_DATA (info, codep + 1);
9583       modrm.mod = (*codep >> 6) & 3;
9584       modrm.reg = (*codep >> 3) & 7;
9585       modrm.rm = *codep & 7;
9586
9587       /* Set vector length.  */
9588       if (modrm.mod == 3 && vex.b)
9589         vex.length = 512;
9590       else
9591         {
9592           switch (vex.ll)
9593             {
9594             case 0x0:
9595               vex.length = 128;
9596               break;
9597             case 0x1:
9598               vex.length = 256;
9599               break;
9600             case 0x2:
9601               vex.length = 512;
9602               break;
9603             default:
9604               return &bad_opcode;
9605             }
9606         }
9607       break;
9608
9609     case 0:
9610       dp = &bad_opcode;
9611       break;
9612
9613     default:
9614       abort ();
9615     }
9616
9617   if (dp->name != NULL)
9618     return dp;
9619   else
9620     return get_valid_dis386 (dp, info);
9621 }
9622
9623 static void
9624 get_sib (disassemble_info *info, int sizeflag)
9625 {
9626   /* If modrm.mod == 3, operand must be register.  */
9627   if (need_modrm
9628       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
9629       && modrm.mod != 3
9630       && modrm.rm == 4)
9631     {
9632       FETCH_DATA (info, codep + 2);
9633       sib.index = (codep [1] >> 3) & 7;
9634       sib.scale = (codep [1] >> 6) & 3;
9635       sib.base = codep [1] & 7;
9636     }
9637 }
9638
9639 static int
9640 print_insn (bfd_vma pc, disassemble_info *info)
9641 {
9642   const struct dis386 *dp;
9643   int i;
9644   char *op_txt[MAX_OPERANDS];
9645   int needcomma;
9646   int sizeflag, orig_sizeflag;
9647   const char *p;
9648   struct dis_private priv;
9649   int prefix_length;
9650
9651   priv.orig_sizeflag = AFLAG | DFLAG;
9652   if ((info->mach & bfd_mach_i386_i386) != 0)
9653     address_mode = mode_32bit;
9654   else if (info->mach == bfd_mach_i386_i8086)
9655     {
9656       address_mode = mode_16bit;
9657       priv.orig_sizeflag = 0;
9658     }
9659   else
9660     address_mode = mode_64bit;
9661
9662   if (intel_syntax == (char) -1)
9663     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
9664
9665   for (p = info->disassembler_options; p != NULL; )
9666     {
9667       if (CONST_STRNEQ (p, "amd64"))
9668         isa64 = amd64;
9669       else if (CONST_STRNEQ (p, "intel64"))
9670         isa64 = intel64;
9671       else if (CONST_STRNEQ (p, "x86-64"))
9672         {
9673           address_mode = mode_64bit;
9674           priv.orig_sizeflag |= AFLAG | DFLAG;
9675         }
9676       else if (CONST_STRNEQ (p, "i386"))
9677         {
9678           address_mode = mode_32bit;
9679           priv.orig_sizeflag |= AFLAG | DFLAG;
9680         }
9681       else if (CONST_STRNEQ (p, "i8086"))
9682         {
9683           address_mode = mode_16bit;
9684           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9685         }
9686       else if (CONST_STRNEQ (p, "intel"))
9687         {
9688           intel_syntax = 1;
9689           if (CONST_STRNEQ (p + 5, "-mnemonic"))
9690             intel_mnemonic = 1;
9691         }
9692       else if (CONST_STRNEQ (p, "att"))
9693         {
9694           intel_syntax = 0;
9695           if (CONST_STRNEQ (p + 3, "-mnemonic"))
9696             intel_mnemonic = 0;
9697         }
9698       else if (CONST_STRNEQ (p, "addr"))
9699         {
9700           if (address_mode == mode_64bit)
9701             {
9702               if (p[4] == '3' && p[5] == '2')
9703                 priv.orig_sizeflag &= ~AFLAG;
9704               else if (p[4] == '6' && p[5] == '4')
9705                 priv.orig_sizeflag |= AFLAG;
9706             }
9707           else
9708             {
9709               if (p[4] == '1' && p[5] == '6')
9710                 priv.orig_sizeflag &= ~AFLAG;
9711               else if (p[4] == '3' && p[5] == '2')
9712                 priv.orig_sizeflag |= AFLAG;
9713             }
9714         }
9715       else if (CONST_STRNEQ (p, "data"))
9716         {
9717           if (p[4] == '1' && p[5] == '6')
9718             priv.orig_sizeflag &= ~DFLAG;
9719           else if (p[4] == '3' && p[5] == '2')
9720             priv.orig_sizeflag |= DFLAG;
9721         }
9722       else if (CONST_STRNEQ (p, "suffix"))
9723         priv.orig_sizeflag |= SUFFIX_ALWAYS;
9724
9725       p = strchr (p, ',');
9726       if (p != NULL)
9727         p++;
9728     }
9729
9730   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9731     {
9732       (*info->fprintf_func) (info->stream,
9733                              _("64-bit address is disabled"));
9734       return -1;
9735     }
9736
9737   if (intel_syntax)
9738     {
9739       names64 = intel_names64;
9740       names32 = intel_names32;
9741       names16 = intel_names16;
9742       names8 = intel_names8;
9743       names8rex = intel_names8rex;
9744       names_seg = intel_names_seg;
9745       names_mm = intel_names_mm;
9746       names_bnd = intel_names_bnd;
9747       names_xmm = intel_names_xmm;
9748       names_ymm = intel_names_ymm;
9749       names_zmm = intel_names_zmm;
9750       names_tmm = intel_names_tmm;
9751       index64 = intel_index64;
9752       index32 = intel_index32;
9753       names_mask = intel_names_mask;
9754       index16 = intel_index16;
9755       open_char = '[';
9756       close_char = ']';
9757       separator_char = '+';
9758       scale_char = '*';
9759     }
9760   else
9761     {
9762       names64 = att_names64;
9763       names32 = att_names32;
9764       names16 = att_names16;
9765       names8 = att_names8;
9766       names8rex = att_names8rex;
9767       names_seg = att_names_seg;
9768       names_mm = att_names_mm;
9769       names_bnd = att_names_bnd;
9770       names_xmm = att_names_xmm;
9771       names_ymm = att_names_ymm;
9772       names_zmm = att_names_zmm;
9773       names_tmm = att_names_tmm;
9774       index64 = att_index64;
9775       index32 = att_index32;
9776       names_mask = att_names_mask;
9777       index16 = att_index16;
9778       open_char = '(';
9779       close_char =  ')';
9780       separator_char = ',';
9781       scale_char = ',';
9782     }
9783
9784   /* The output looks better if we put 7 bytes on a line, since that
9785      puts most long word instructions on a single line.  Use 8 bytes
9786      for Intel L1OM.  */
9787   if ((info->mach & bfd_mach_l1om) != 0)
9788     info->bytes_per_line = 8;
9789   else
9790     info->bytes_per_line = 7;
9791
9792   info->private_data = &priv;
9793   priv.max_fetched = priv.the_buffer;
9794   priv.insn_start = pc;
9795
9796   obuf[0] = 0;
9797   for (i = 0; i < MAX_OPERANDS; ++i)
9798     {
9799       op_out[i][0] = 0;
9800       op_index[i] = -1;
9801     }
9802
9803   the_info = info;
9804   start_pc = pc;
9805   start_codep = priv.the_buffer;
9806   codep = priv.the_buffer;
9807
9808   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
9809     {
9810       const char *name;
9811
9812       /* Getting here means we tried for data but didn't get it.  That
9813          means we have an incomplete instruction of some sort.  Just
9814          print the first byte as a prefix or a .byte pseudo-op.  */
9815       if (codep > priv.the_buffer)
9816         {
9817           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
9818           if (name != NULL)
9819             (*info->fprintf_func) (info->stream, "%s", name);
9820           else
9821             {
9822               /* Just print the first byte as a .byte instruction.  */
9823               (*info->fprintf_func) (info->stream, ".byte 0x%x",
9824                                      (unsigned int) priv.the_buffer[0]);
9825             }
9826
9827           return 1;
9828         }
9829
9830       return -1;
9831     }
9832
9833   obufp = obuf;
9834   sizeflag = priv.orig_sizeflag;
9835
9836   if (!ckprefix () || rex_used)
9837     {
9838       /* Too many prefixes or unused REX prefixes.  */
9839       for (i = 0;
9840            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
9841            i++)
9842         (*info->fprintf_func) (info->stream, "%s%s",
9843                                i == 0 ? "" : " ",
9844                                prefix_name (all_prefixes[i], sizeflag));
9845       return i;
9846     }
9847
9848   insn_codep = codep;
9849
9850   FETCH_DATA (info, codep + 1);
9851   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
9852
9853   if (((prefixes & PREFIX_FWAIT)
9854        && ((*codep < 0xd8) || (*codep > 0xdf))))
9855     {
9856       /* Handle prefixes before fwait.  */
9857       for (i = 0; i < fwait_prefix && all_prefixes[i];
9858            i++)
9859         (*info->fprintf_func) (info->stream, "%s ",
9860                                prefix_name (all_prefixes[i], sizeflag));
9861       (*info->fprintf_func) (info->stream, "fwait");
9862       return i + 1;
9863     }
9864
9865   if (*codep == 0x0f)
9866     {
9867       unsigned char threebyte;
9868
9869       codep++;
9870       FETCH_DATA (info, codep + 1);
9871       threebyte = *codep;
9872       dp = &dis386_twobyte[threebyte];
9873       need_modrm = twobyte_has_modrm[*codep];
9874       codep++;
9875     }
9876   else
9877     {
9878       dp = &dis386[*codep];
9879       need_modrm = onebyte_has_modrm[*codep];
9880       codep++;
9881     }
9882
9883   /* Save sizeflag for printing the extra prefixes later before updating
9884      it for mnemonic and operand processing.  The prefix names depend
9885      only on the address mode.  */
9886   orig_sizeflag = sizeflag;
9887   if (prefixes & PREFIX_ADDR)
9888     sizeflag ^= AFLAG;
9889   if ((prefixes & PREFIX_DATA))
9890     sizeflag ^= DFLAG;
9891
9892   end_codep = codep;
9893   if (need_modrm)
9894     {
9895       FETCH_DATA (info, codep + 1);
9896       modrm.mod = (*codep >> 6) & 3;
9897       modrm.reg = (*codep >> 3) & 7;
9898       modrm.rm = *codep & 7;
9899     }
9900
9901   need_vex = 0;
9902   memset (&vex, 0, sizeof (vex));
9903
9904   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9905     {
9906       get_sib (info, sizeflag);
9907       dofloat (sizeflag);
9908     }
9909   else
9910     {
9911       dp = get_valid_dis386 (dp, info);
9912       if (dp != NULL && putop (dp->name, sizeflag) == 0)
9913         {
9914           get_sib (info, sizeflag);
9915           for (i = 0; i < MAX_OPERANDS; ++i)
9916             {
9917               obufp = op_out[i];
9918               op_ad = MAX_OPERANDS - 1 - i;
9919               if (dp->op[i].rtn)
9920                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
9921               /* For EVEX instruction after the last operand masking
9922                  should be printed.  */
9923               if (i == 0 && vex.evex)
9924                 {
9925                   /* Don't print {%k0}.  */
9926                   if (vex.mask_register_specifier)
9927                     {
9928                       oappend ("{");
9929                       oappend (names_mask[vex.mask_register_specifier]);
9930                       oappend ("}");
9931                     }
9932                   if (vex.zeroing)
9933                     oappend ("{z}");
9934                 }
9935             }
9936         }
9937     }
9938
9939   /* Clear instruction information.  */
9940   if (the_info)
9941     {
9942       the_info->insn_info_valid = 0;
9943       the_info->branch_delay_insns = 0;
9944       the_info->data_size = 0;
9945       the_info->insn_type = dis_noninsn;
9946       the_info->target = 0;
9947       the_info->target2 = 0;
9948     }
9949
9950   /* Reset jump operation indicator.  */
9951   op_is_jump = FALSE;
9952
9953   {
9954     int jump_detection = 0;
9955
9956     /* Extract flags.  */
9957     for (i = 0; i < MAX_OPERANDS; ++i)
9958       {
9959         if ((dp->op[i].rtn == OP_J)
9960             || (dp->op[i].rtn == OP_indirE))
9961           jump_detection |= 1;
9962         else if ((dp->op[i].rtn == BND_Fixup)
9963                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
9964           jump_detection |= 2;
9965         else if ((dp->op[i].bytemode == cond_jump_mode)
9966                  || (dp->op[i].bytemode == loop_jcxz_mode))
9967           jump_detection |= 4;
9968       }
9969
9970     /* Determine if this is a jump or branch.  */
9971     if ((jump_detection & 0x3) == 0x3)
9972       {
9973         op_is_jump = TRUE;
9974         if (jump_detection & 0x4)
9975           the_info->insn_type = dis_condbranch;
9976         else
9977           the_info->insn_type =
9978             (dp->name && !strncmp(dp->name, "call", 4))
9979             ? dis_jsr : dis_branch;
9980       }
9981   }
9982
9983   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9984      are all 0s in inverted form.  */
9985   if (need_vex && vex.register_specifier != 0)
9986     {
9987       (*info->fprintf_func) (info->stream, "(bad)");
9988       return end_codep - priv.the_buffer;
9989     }
9990
9991   switch (dp->prefix_requirement)
9992     {
9993     case PREFIX_DATA:
9994       /* If only the data prefix is marked as mandatory, its absence renders
9995          the encoding invalid.  Most other PREFIX_OPCODE rules still apply.  */
9996       if (need_vex ? !vex.prefix : !(prefixes & PREFIX_DATA))
9997         {
9998           (*info->fprintf_func) (info->stream, "(bad)");
9999           return end_codep - priv.the_buffer;
10000         }
10001       used_prefixes |= PREFIX_DATA;
10002       /* Fall through.  */
10003     case PREFIX_OPCODE:
10004       /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
10005          unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
10006          used by putop and MMX/SSE operand and may be overridden by the
10007          PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
10008          separately.  */
10009       if (((need_vex
10010             ? vex.prefix == REPE_PREFIX_OPCODE
10011               || vex.prefix == REPNE_PREFIX_OPCODE
10012             : (prefixes
10013                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
10014            && (used_prefixes
10015                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
10016           || (((need_vex
10017                 ? vex.prefix == DATA_PREFIX_OPCODE
10018                 : ((prefixes
10019                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
10020                    == PREFIX_DATA))
10021                && (used_prefixes & PREFIX_DATA) == 0))
10022           || (vex.evex && dp->prefix_requirement != PREFIX_DATA
10023               && !vex.w != !(used_prefixes & PREFIX_DATA)))
10024         {
10025           (*info->fprintf_func) (info->stream, "(bad)");
10026           return end_codep - priv.the_buffer;
10027         }
10028       break;
10029     }
10030
10031   /* Check if the REX prefix is used.  */
10032   if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
10033     all_prefixes[last_rex_prefix] = 0;
10034
10035   /* Check if the SEG prefix is used.  */
10036   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
10037                    | PREFIX_FS | PREFIX_GS)) != 0
10038       && (used_prefixes & active_seg_prefix) != 0)
10039     all_prefixes[last_seg_prefix] = 0;
10040
10041   /* Check if the ADDR prefix is used.  */
10042   if ((prefixes & PREFIX_ADDR) != 0
10043       && (used_prefixes & PREFIX_ADDR) != 0)
10044     all_prefixes[last_addr_prefix] = 0;
10045
10046   /* Check if the DATA prefix is used.  */
10047   if ((prefixes & PREFIX_DATA) != 0
10048       && (used_prefixes & PREFIX_DATA) != 0
10049       && !need_vex)
10050     all_prefixes[last_data_prefix] = 0;
10051
10052   /* Print the extra prefixes.  */
10053   prefix_length = 0;
10054   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10055     if (all_prefixes[i])
10056       {
10057         const char *name;
10058         name = prefix_name (all_prefixes[i], orig_sizeflag);
10059         if (name == NULL)
10060           abort ();
10061         prefix_length += strlen (name) + 1;
10062         (*info->fprintf_func) (info->stream, "%s ", name);
10063       }
10064
10065   /* Check maximum code length.  */
10066   if ((codep - start_codep) > MAX_CODE_LENGTH)
10067     {
10068       (*info->fprintf_func) (info->stream, "(bad)");
10069       return MAX_CODE_LENGTH;
10070     }
10071
10072   obufp = mnemonicendp;
10073   for (i = strlen (obuf) + prefix_length; i < 6; i++)
10074     oappend (" ");
10075   oappend (" ");
10076   (*info->fprintf_func) (info->stream, "%s", obuf);
10077
10078   /* The enter and bound instructions are printed with operands in the same
10079      order as the intel book; everything else is printed in reverse order.  */
10080   if (intel_syntax || two_source_ops)
10081     {
10082       bfd_vma riprel;
10083
10084       for (i = 0; i < MAX_OPERANDS; ++i)
10085         op_txt[i] = op_out[i];
10086
10087       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
10088           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
10089         {
10090           op_txt[2] = op_out[3];
10091           op_txt[3] = op_out[2];
10092         }
10093
10094       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10095         {
10096           op_ad = op_index[i];
10097           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
10098           op_index[MAX_OPERANDS - 1 - i] = op_ad;
10099           riprel = op_riprel[i];
10100           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
10101           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
10102         }
10103     }
10104   else
10105     {
10106       for (i = 0; i < MAX_OPERANDS; ++i)
10107         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
10108     }
10109
10110   needcomma = 0;
10111   for (i = 0; i < MAX_OPERANDS; ++i)
10112     if (*op_txt[i])
10113       {
10114         if (needcomma)
10115           (*info->fprintf_func) (info->stream, ",");
10116         if (op_index[i] != -1 && !op_riprel[i])
10117           {
10118             bfd_vma target = (bfd_vma) op_address[op_index[i]];
10119
10120             if (the_info && op_is_jump)
10121               {
10122                 the_info->insn_info_valid = 1;
10123                 the_info->branch_delay_insns = 0;
10124                 the_info->data_size = 0;
10125                 the_info->target = target;
10126                 the_info->target2 = 0;
10127               }
10128             (*info->print_address_func) (target, info);
10129           }
10130         else
10131           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
10132         needcomma = 1;
10133       }
10134
10135   for (i = 0; i < MAX_OPERANDS; i++)
10136     if (op_index[i] != -1 && op_riprel[i])
10137       {
10138         (*info->fprintf_func) (info->stream, "        # ");
10139         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
10140                                                 + op_address[op_index[i]]), info);
10141         break;
10142       }
10143   return codep - priv.the_buffer;
10144 }
10145
10146 static const char *float_mem[] = {
10147   /* d8 */
10148   "fadd{s|}",
10149   "fmul{s|}",
10150   "fcom{s|}",
10151   "fcomp{s|}",
10152   "fsub{s|}",
10153   "fsubr{s|}",
10154   "fdiv{s|}",
10155   "fdivr{s|}",
10156   /* d9 */
10157   "fld{s|}",
10158   "(bad)",
10159   "fst{s|}",
10160   "fstp{s|}",
10161   "fldenv{C|C}",
10162   "fldcw",
10163   "fNstenv{C|C}",
10164   "fNstcw",
10165   /* da */
10166   "fiadd{l|}",
10167   "fimul{l|}",
10168   "ficom{l|}",
10169   "ficomp{l|}",
10170   "fisub{l|}",
10171   "fisubr{l|}",
10172   "fidiv{l|}",
10173   "fidivr{l|}",
10174   /* db */
10175   "fild{l|}",
10176   "fisttp{l|}",
10177   "fist{l|}",
10178   "fistp{l|}",
10179   "(bad)",
10180   "fld{t|}",
10181   "(bad)",
10182   "fstp{t|}",
10183   /* dc */
10184   "fadd{l|}",
10185   "fmul{l|}",
10186   "fcom{l|}",
10187   "fcomp{l|}",
10188   "fsub{l|}",
10189   "fsubr{l|}",
10190   "fdiv{l|}",
10191   "fdivr{l|}",
10192   /* dd */
10193   "fld{l|}",
10194   "fisttp{ll|}",
10195   "fst{l||}",
10196   "fstp{l|}",
10197   "frstor{C|C}",
10198   "(bad)",
10199   "fNsave{C|C}",
10200   "fNstsw",
10201   /* de */
10202   "fiadd{s|}",
10203   "fimul{s|}",
10204   "ficom{s|}",
10205   "ficomp{s|}",
10206   "fisub{s|}",
10207   "fisubr{s|}",
10208   "fidiv{s|}",
10209   "fidivr{s|}",
10210   /* df */
10211   "fild{s|}",
10212   "fisttp{s|}",
10213   "fist{s|}",
10214   "fistp{s|}",
10215   "fbld",
10216   "fild{ll|}",
10217   "fbstp",
10218   "fistp{ll|}",
10219 };
10220
10221 static const unsigned char float_mem_mode[] = {
10222   /* d8 */
10223   d_mode,
10224   d_mode,
10225   d_mode,
10226   d_mode,
10227   d_mode,
10228   d_mode,
10229   d_mode,
10230   d_mode,
10231   /* d9 */
10232   d_mode,
10233   0,
10234   d_mode,
10235   d_mode,
10236   0,
10237   w_mode,
10238   0,
10239   w_mode,
10240   /* da */
10241   d_mode,
10242   d_mode,
10243   d_mode,
10244   d_mode,
10245   d_mode,
10246   d_mode,
10247   d_mode,
10248   d_mode,
10249   /* db */
10250   d_mode,
10251   d_mode,
10252   d_mode,
10253   d_mode,
10254   0,
10255   t_mode,
10256   0,
10257   t_mode,
10258   /* dc */
10259   q_mode,
10260   q_mode,
10261   q_mode,
10262   q_mode,
10263   q_mode,
10264   q_mode,
10265   q_mode,
10266   q_mode,
10267   /* dd */
10268   q_mode,
10269   q_mode,
10270   q_mode,
10271   q_mode,
10272   0,
10273   0,
10274   0,
10275   w_mode,
10276   /* de */
10277   w_mode,
10278   w_mode,
10279   w_mode,
10280   w_mode,
10281   w_mode,
10282   w_mode,
10283   w_mode,
10284   w_mode,
10285   /* df */
10286   w_mode,
10287   w_mode,
10288   w_mode,
10289   w_mode,
10290   t_mode,
10291   q_mode,
10292   t_mode,
10293   q_mode
10294 };
10295
10296 #define ST { OP_ST, 0 }
10297 #define STi { OP_STi, 0 }
10298
10299 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10300 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10301 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10302 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10303 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10304 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10305 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10306 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10307 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10308
10309 static const struct dis386 float_reg[][8] = {
10310   /* d8 */
10311   {
10312     { "fadd",   { ST, STi }, 0 },
10313     { "fmul",   { ST, STi }, 0 },
10314     { "fcom",   { STi }, 0 },
10315     { "fcomp",  { STi }, 0 },
10316     { "fsub",   { ST, STi }, 0 },
10317     { "fsubr",  { ST, STi }, 0 },
10318     { "fdiv",   { ST, STi }, 0 },
10319     { "fdivr",  { ST, STi }, 0 },
10320   },
10321   /* d9 */
10322   {
10323     { "fld",    { STi }, 0 },
10324     { "fxch",   { STi }, 0 },
10325     { FGRPd9_2 },
10326     { Bad_Opcode },
10327     { FGRPd9_4 },
10328     { FGRPd9_5 },
10329     { FGRPd9_6 },
10330     { FGRPd9_7 },
10331   },
10332   /* da */
10333   {
10334     { "fcmovb", { ST, STi }, 0 },
10335     { "fcmove", { ST, STi }, 0 },
10336     { "fcmovbe",{ ST, STi }, 0 },
10337     { "fcmovu", { ST, STi }, 0 },
10338     { Bad_Opcode },
10339     { FGRPda_5 },
10340     { Bad_Opcode },
10341     { Bad_Opcode },
10342   },
10343   /* db */
10344   {
10345     { "fcmovnb",{ ST, STi }, 0 },
10346     { "fcmovne",{ ST, STi }, 0 },
10347     { "fcmovnbe",{ ST, STi }, 0 },
10348     { "fcmovnu",{ ST, STi }, 0 },
10349     { FGRPdb_4 },
10350     { "fucomi", { ST, STi }, 0 },
10351     { "fcomi",  { ST, STi }, 0 },
10352     { Bad_Opcode },
10353   },
10354   /* dc */
10355   {
10356     { "fadd",   { STi, ST }, 0 },
10357     { "fmul",   { STi, ST }, 0 },
10358     { Bad_Opcode },
10359     { Bad_Opcode },
10360     { "fsub{!M|r}",     { STi, ST }, 0 },
10361     { "fsub{M|}",       { STi, ST }, 0 },
10362     { "fdiv{!M|r}",     { STi, ST }, 0 },
10363     { "fdiv{M|}",       { STi, ST }, 0 },
10364   },
10365   /* dd */
10366   {
10367     { "ffree",  { STi }, 0 },
10368     { Bad_Opcode },
10369     { "fst",    { STi }, 0 },
10370     { "fstp",   { STi }, 0 },
10371     { "fucom",  { STi }, 0 },
10372     { "fucomp", { STi }, 0 },
10373     { Bad_Opcode },
10374     { Bad_Opcode },
10375   },
10376   /* de */
10377   {
10378     { "faddp",  { STi, ST }, 0 },
10379     { "fmulp",  { STi, ST }, 0 },
10380     { Bad_Opcode },
10381     { FGRPde_3 },
10382     { "fsub{!M|r}p",    { STi, ST }, 0 },
10383     { "fsub{M|}p",      { STi, ST }, 0 },
10384     { "fdiv{!M|r}p",    { STi, ST }, 0 },
10385     { "fdiv{M|}p",      { STi, ST }, 0 },
10386   },
10387   /* df */
10388   {
10389     { "ffreep", { STi }, 0 },
10390     { Bad_Opcode },
10391     { Bad_Opcode },
10392     { Bad_Opcode },
10393     { FGRPdf_4 },
10394     { "fucomip", { ST, STi }, 0 },
10395     { "fcomip", { ST, STi }, 0 },
10396     { Bad_Opcode },
10397   },
10398 };
10399
10400 static char *fgrps[][8] = {
10401   /* Bad opcode 0 */
10402   {
10403     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10404   },
10405
10406   /* d9_2  1 */
10407   {
10408     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10409   },
10410
10411   /* d9_4  2 */
10412   {
10413     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10414   },
10415
10416   /* d9_5  3 */
10417   {
10418     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10419   },
10420
10421   /* d9_6  4 */
10422   {
10423     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10424   },
10425
10426   /* d9_7  5 */
10427   {
10428     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10429   },
10430
10431   /* da_5  6 */
10432   {
10433     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10434   },
10435
10436   /* db_4  7 */
10437   {
10438     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10439     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10440   },
10441
10442   /* de_3  8 */
10443   {
10444     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10445   },
10446
10447   /* df_4  9 */
10448   {
10449     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10450   },
10451 };
10452
10453 static void
10454 swap_operand (void)
10455 {
10456   mnemonicendp[0] = '.';
10457   mnemonicendp[1] = 's';
10458   mnemonicendp += 2;
10459 }
10460
10461 static void
10462 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10463                int sizeflag ATTRIBUTE_UNUSED)
10464 {
10465   /* Skip mod/rm byte.  */
10466   MODRM_CHECK;
10467   codep++;
10468 }
10469
10470 static void
10471 dofloat (int sizeflag)
10472 {
10473   const struct dis386 *dp;
10474   unsigned char floatop;
10475
10476   floatop = codep[-1];
10477
10478   if (modrm.mod != 3)
10479     {
10480       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
10481
10482       putop (float_mem[fp_indx], sizeflag);
10483       obufp = op_out[0];
10484       op_ad = 2;
10485       OP_E (float_mem_mode[fp_indx], sizeflag);
10486       return;
10487     }
10488   /* Skip mod/rm byte.  */
10489   MODRM_CHECK;
10490   codep++;
10491
10492   dp = &float_reg[floatop - 0xd8][modrm.reg];
10493   if (dp->name == NULL)
10494     {
10495       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
10496
10497       /* Instruction fnstsw is only one with strange arg.  */
10498       if (floatop == 0xdf && codep[-1] == 0xe0)
10499         strcpy (op_out[0], names16[0]);
10500     }
10501   else
10502     {
10503       putop (dp->name, sizeflag);
10504
10505       obufp = op_out[0];
10506       op_ad = 2;
10507       if (dp->op[0].rtn)
10508         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
10509
10510       obufp = op_out[1];
10511       op_ad = 1;
10512       if (dp->op[1].rtn)
10513         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
10514     }
10515 }
10516
10517 /* Like oappend (below), but S is a string starting with '%'.
10518    In Intel syntax, the '%' is elided.  */
10519 static void
10520 oappend_maybe_intel (const char *s)
10521 {
10522   oappend (s + intel_syntax);
10523 }
10524
10525 static void
10526 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10527 {
10528   oappend_maybe_intel ("%st");
10529 }
10530
10531 static void
10532 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10533 {
10534   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
10535   oappend_maybe_intel (scratchbuf);
10536 }
10537
10538 /* Capital letters in template are macros.  */
10539 static int
10540 putop (const char *in_template, int sizeflag)
10541 {
10542   const char *p;
10543   int alt = 0;
10544   int cond = 1;
10545   unsigned int l = 0, len = 0;
10546   char last[4];
10547
10548   for (p = in_template; *p; p++)
10549     {
10550       if (len > l)
10551         {
10552           if (l >= sizeof (last) || !ISUPPER (*p))
10553             abort ();
10554           last[l++] = *p;
10555           continue;
10556         }
10557       switch (*p)
10558         {
10559         default:
10560           *obufp++ = *p;
10561           break;
10562         case '%':
10563           len++;
10564           break;
10565         case '!':
10566           cond = 0;
10567           break;
10568         case '{':
10569           if (intel_syntax)
10570             {
10571               while (*++p != '|')
10572                 if (*p == '}' || *p == '\0')
10573                   abort ();
10574               alt = 1;
10575             }
10576           break;
10577         case '|':
10578           while (*++p != '}')
10579             {
10580               if (*p == '\0')
10581                 abort ();
10582             }
10583           break;
10584         case '}':
10585           alt = 0;
10586           break;
10587         case 'A':
10588           if (intel_syntax)
10589             break;
10590           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10591             *obufp++ = 'b';
10592           break;
10593         case 'B':
10594           if (l == 0)
10595             {
10596             case_B:
10597               if (intel_syntax)
10598                 break;
10599               if (sizeflag & SUFFIX_ALWAYS)
10600                 *obufp++ = 'b';
10601             }
10602           else if (l == 1 && last[0] == 'L')
10603             {
10604               if (address_mode == mode_64bit
10605                   && !(prefixes & PREFIX_ADDR))
10606                 {
10607                   *obufp++ = 'a';
10608                   *obufp++ = 'b';
10609                   *obufp++ = 's';
10610                 }
10611
10612               goto case_B;
10613             }
10614           else
10615             abort ();
10616           break;
10617         case 'C':
10618           if (intel_syntax && !alt)
10619             break;
10620           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10621             {
10622               if (sizeflag & DFLAG)
10623                 *obufp++ = intel_syntax ? 'd' : 'l';
10624               else
10625                 *obufp++ = intel_syntax ? 'w' : 's';
10626               used_prefixes |= (prefixes & PREFIX_DATA);
10627             }
10628           break;
10629         case 'D':
10630           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10631             break;
10632           USED_REX (REX_W);
10633           if (modrm.mod == 3)
10634             {
10635               if (rex & REX_W)
10636                 *obufp++ = 'q';
10637               else
10638                 {
10639                   if (sizeflag & DFLAG)
10640                     *obufp++ = intel_syntax ? 'd' : 'l';
10641                   else
10642                     *obufp++ = 'w';
10643                   used_prefixes |= (prefixes & PREFIX_DATA);
10644                 }
10645             }
10646           else
10647             *obufp++ = 'w';
10648           break;
10649         case 'E':               /* For jcxz/jecxz */
10650           if (address_mode == mode_64bit)
10651             {
10652               if (sizeflag & AFLAG)
10653                 *obufp++ = 'r';
10654               else
10655                 *obufp++ = 'e';
10656             }
10657           else
10658             if (sizeflag & AFLAG)
10659               *obufp++ = 'e';
10660           used_prefixes |= (prefixes & PREFIX_ADDR);
10661           break;
10662         case 'F':
10663           if (intel_syntax)
10664             break;
10665           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10666             {
10667               if (sizeflag & AFLAG)
10668                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10669               else
10670                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
10671               used_prefixes |= (prefixes & PREFIX_ADDR);
10672             }
10673           break;
10674         case 'G':
10675           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
10676             break;
10677           if ((rex & REX_W) || (sizeflag & DFLAG))
10678             *obufp++ = 'l';
10679           else
10680             *obufp++ = 'w';
10681           if (!(rex & REX_W))
10682             used_prefixes |= (prefixes & PREFIX_DATA);
10683           break;
10684         case 'H':
10685           if (intel_syntax)
10686             break;
10687           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10688               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10689             {
10690               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
10691               *obufp++ = ',';
10692               *obufp++ = 'p';
10693               if (prefixes & PREFIX_DS)
10694                 *obufp++ = 't';
10695               else
10696                 *obufp++ = 'n';
10697             }
10698           break;
10699         case 'K':
10700           USED_REX (REX_W);
10701           if (rex & REX_W)
10702             *obufp++ = 'q';
10703           else
10704             *obufp++ = 'd';
10705           break;
10706         case 'L':
10707           abort ();
10708         case 'M':
10709           if (intel_mnemonic != cond)
10710             *obufp++ = 'r';
10711           break;
10712         case 'N':
10713           if ((prefixes & PREFIX_FWAIT) == 0)
10714             *obufp++ = 'n';
10715           else
10716             used_prefixes |= PREFIX_FWAIT;
10717           break;
10718         case 'O':
10719           USED_REX (REX_W);
10720           if (rex & REX_W)
10721             *obufp++ = 'o';
10722           else if (intel_syntax && (sizeflag & DFLAG))
10723             *obufp++ = 'q';
10724           else
10725             *obufp++ = 'd';
10726           if (!(rex & REX_W))
10727             used_prefixes |= (prefixes & PREFIX_DATA);
10728           break;
10729         case '@':
10730           if (address_mode == mode_64bit
10731               && (isa64 == intel64 || (rex & REX_W)
10732                   || !(prefixes & PREFIX_DATA)))
10733             {
10734               if (sizeflag & SUFFIX_ALWAYS)
10735                 *obufp++ = 'q';
10736               break;
10737             }
10738           /* Fall through.  */
10739         case 'P':
10740           if (l == 0)
10741             {
10742               if (((need_modrm && modrm.mod == 3) || !cond)
10743                   && !(sizeflag & SUFFIX_ALWAYS))
10744                 break;
10745           /* Fall through.  */
10746         case 'T':
10747               if ((!(rex & REX_W) && (prefixes & PREFIX_DATA))
10748                   || ((sizeflag & SUFFIX_ALWAYS)
10749                       && address_mode != mode_64bit))
10750                 {
10751                   *obufp++ = (sizeflag & DFLAG) ?
10752                              intel_syntax ? 'd' : 'l' : 'w';
10753                   used_prefixes |= (prefixes & PREFIX_DATA);
10754                 }
10755               else if (sizeflag & SUFFIX_ALWAYS)
10756                 *obufp++ = 'q';
10757             }
10758           else if (l == 1 && last[0] == 'L')
10759             {
10760               if ((prefixes & PREFIX_DATA)
10761                   || (rex & REX_W)
10762                   || (sizeflag & SUFFIX_ALWAYS))
10763                 {
10764                   USED_REX (REX_W);
10765                   if (rex & REX_W)
10766                     *obufp++ = 'q';
10767                   else
10768                     {
10769                       if (sizeflag & DFLAG)
10770                         *obufp++ = intel_syntax ? 'd' : 'l';
10771                       else
10772                         *obufp++ = 'w';
10773                       used_prefixes |= (prefixes & PREFIX_DATA);
10774                     }
10775                 }
10776             }
10777           else
10778             abort ();
10779           break;
10780         case 'Q':
10781           if (l == 0)
10782             {
10783               if (intel_syntax && !alt)
10784                 break;
10785               USED_REX (REX_W);
10786               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10787                 {
10788                   if (rex & REX_W)
10789                     *obufp++ = 'q';
10790                   else
10791                     {
10792                       if (sizeflag & DFLAG)
10793                         *obufp++ = intel_syntax ? 'd' : 'l';
10794                       else
10795                         *obufp++ = 'w';
10796                       used_prefixes |= (prefixes & PREFIX_DATA);
10797                     }
10798                 }
10799             }
10800           else if (l == 1 && last[0] == 'D')
10801             *obufp++ = vex.w ? 'q' : 'd';
10802           else if (l == 1 && last[0] == 'L')
10803             {
10804               if (cond ? modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10805                        : address_mode != mode_64bit)
10806                 break;
10807               if ((rex & REX_W))
10808                 {
10809                   USED_REX (REX_W);
10810                   *obufp++ = 'q';
10811                 }
10812               else if((address_mode == mode_64bit && need_modrm && cond)
10813                       || (sizeflag & SUFFIX_ALWAYS))
10814                 *obufp++ = intel_syntax? 'd' : 'l';
10815             }
10816           else
10817             abort ();
10818           break;
10819         case 'R':
10820           USED_REX (REX_W);
10821           if (rex & REX_W)
10822             *obufp++ = 'q';
10823           else if (sizeflag & DFLAG)
10824             {
10825               if (intel_syntax)
10826                   *obufp++ = 'd';
10827               else
10828                   *obufp++ = 'l';
10829             }
10830           else
10831             *obufp++ = 'w';
10832           if (intel_syntax && !p[1]
10833               && ((rex & REX_W) || (sizeflag & DFLAG)))
10834             *obufp++ = 'e';
10835           if (!(rex & REX_W))
10836             used_prefixes |= (prefixes & PREFIX_DATA);
10837           break;
10838         case 'S':
10839           if (l == 0)
10840             {
10841             case_S:
10842               if (intel_syntax)
10843                 break;
10844               if (sizeflag & SUFFIX_ALWAYS)
10845                 {
10846                   if (rex & REX_W)
10847                     *obufp++ = 'q';
10848                   else
10849                     {
10850                       if (sizeflag & DFLAG)
10851                         *obufp++ = 'l';
10852                       else
10853                         *obufp++ = 'w';
10854                       used_prefixes |= (prefixes & PREFIX_DATA);
10855                     }
10856                 }
10857             }
10858           else if (l == 1 && last[0] == 'L')
10859             {
10860               if (address_mode == mode_64bit
10861                   && !(prefixes & PREFIX_ADDR))
10862                 {
10863                   *obufp++ = 'a';
10864                   *obufp++ = 'b';
10865                   *obufp++ = 's';
10866                 }
10867
10868               goto case_S;
10869             }
10870           else
10871             abort ();
10872           break;
10873         case 'V':
10874           if (l == 0)
10875             abort ();
10876           else if (l == 1 && last[0] == 'L')
10877             {
10878               if (rex & REX_W)
10879                 {
10880                   *obufp++ = 'a';
10881                   *obufp++ = 'b';
10882                   *obufp++ = 's';
10883                 }
10884             }
10885           else
10886             abort ();
10887           goto case_S;
10888         case 'W':
10889           if (l == 0)
10890             {
10891               /* operand size flag for cwtl, cbtw */
10892               USED_REX (REX_W);
10893               if (rex & REX_W)
10894                 {
10895                   if (intel_syntax)
10896                     *obufp++ = 'd';
10897                   else
10898                     *obufp++ = 'l';
10899                 }
10900               else if (sizeflag & DFLAG)
10901                 *obufp++ = 'w';
10902               else
10903                 *obufp++ = 'b';
10904               if (!(rex & REX_W))
10905                 used_prefixes |= (prefixes & PREFIX_DATA);
10906             }
10907           else if (l == 1)
10908             {
10909               if (!need_vex)
10910                 abort ();
10911               if (last[0] == 'X')
10912                 *obufp++ = vex.w ? 'd': 's';
10913               else if (last[0] == 'B')
10914                 *obufp++ = vex.w ? 'w': 'b';
10915               else
10916                 abort ();
10917             }
10918           else
10919             abort ();
10920           break;
10921         case 'X':
10922           if (l != 0)
10923             abort ();
10924           if (need_vex
10925               ? vex.prefix == DATA_PREFIX_OPCODE
10926               : prefixes & PREFIX_DATA)
10927             {
10928               *obufp++ = 'd';
10929               used_prefixes |= PREFIX_DATA;
10930             }
10931           else
10932             *obufp++ = 's';
10933           break;
10934         case 'Y':
10935           if (l == 1 && last[0] == 'X')
10936             {
10937               if (!need_vex)
10938                 abort ();
10939               if (intel_syntax
10940                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
10941                 break;
10942               switch (vex.length)
10943                 {
10944                 case 128:
10945                   *obufp++ = 'x';
10946                   break;
10947                 case 256:
10948                   *obufp++ = 'y';
10949                   break;
10950                 case 512:
10951                   if (!vex.evex)
10952                 default:
10953                     abort ();
10954                 }
10955             }
10956           else
10957             abort ();
10958           break;
10959         case 'Z':
10960           if (l == 0)
10961             {
10962               /* These insns ignore ModR/M.mod: Force it to 3 for OP_E().  */
10963               modrm.mod = 3;
10964               if (!intel_syntax && (sizeflag & SUFFIX_ALWAYS))
10965                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10966             }
10967           else if (l == 1 && last[0] == 'X')
10968             {
10969               if (!need_vex || !vex.evex)
10970                 abort ();
10971               if (intel_syntax
10972                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
10973                 break;
10974               switch (vex.length)
10975                 {
10976                 case 128:
10977                   *obufp++ = 'x';
10978                   break;
10979                 case 256:
10980                   *obufp++ = 'y';
10981                   break;
10982                 case 512:
10983                   *obufp++ = 'z';
10984                   break;
10985                 default:
10986                   abort ();
10987                 }
10988             }
10989           else
10990             abort ();
10991           break;
10992         case '^':
10993           if (intel_syntax)
10994             break;
10995           if (isa64 == intel64 && (rex & REX_W))
10996             {
10997               USED_REX (REX_W);
10998               *obufp++ = 'q';
10999               break;
11000             }
11001           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
11002             {
11003               if (sizeflag & DFLAG)
11004                 *obufp++ = 'l';
11005               else
11006                 *obufp++ = 'w';
11007               used_prefixes |= (prefixes & PREFIX_DATA);
11008             }
11009           break;
11010         }
11011
11012       if (len == l)
11013         len = l = 0;
11014     }
11015   *obufp = 0;
11016   mnemonicendp = obufp;
11017   return 0;
11018 }
11019
11020 static void
11021 oappend (const char *s)
11022 {
11023   obufp = stpcpy (obufp, s);
11024 }
11025
11026 static void
11027 append_seg (void)
11028 {
11029   /* Only print the active segment register.  */
11030   if (!active_seg_prefix)
11031     return;
11032
11033   used_prefixes |= active_seg_prefix;
11034   switch (active_seg_prefix)
11035     {
11036     case PREFIX_CS:
11037       oappend_maybe_intel ("%cs:");
11038       break;
11039     case PREFIX_DS:
11040       oappend_maybe_intel ("%ds:");
11041       break;
11042     case PREFIX_SS:
11043       oappend_maybe_intel ("%ss:");
11044       break;
11045     case PREFIX_ES:
11046       oappend_maybe_intel ("%es:");
11047       break;
11048     case PREFIX_FS:
11049       oappend_maybe_intel ("%fs:");
11050       break;
11051     case PREFIX_GS:
11052       oappend_maybe_intel ("%gs:");
11053       break;
11054     default:
11055       break;
11056     }
11057 }
11058
11059 static void
11060 OP_indirE (int bytemode, int sizeflag)
11061 {
11062   if (!intel_syntax)
11063     oappend ("*");
11064   OP_E (bytemode, sizeflag);
11065 }
11066
11067 static void
11068 print_operand_value (char *buf, int hex, bfd_vma disp)
11069 {
11070   if (address_mode == mode_64bit)
11071     {
11072       if (hex)
11073         {
11074           char tmp[30];
11075           int i;
11076           buf[0] = '0';
11077           buf[1] = 'x';
11078           sprintf_vma (tmp, disp);
11079           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
11080           strcpy (buf + 2, tmp + i);
11081         }
11082       else
11083         {
11084           bfd_signed_vma v = disp;
11085           char tmp[30];
11086           int i;
11087           if (v < 0)
11088             {
11089               *(buf++) = '-';
11090               v = -disp;
11091               /* Check for possible overflow on 0x8000000000000000.  */
11092               if (v < 0)
11093                 {
11094                   strcpy (buf, "9223372036854775808");
11095                   return;
11096                 }
11097             }
11098           if (!v)
11099             {
11100               strcpy (buf, "0");
11101               return;
11102             }
11103
11104           i = 0;
11105           tmp[29] = 0;
11106           while (v)
11107             {
11108               tmp[28 - i] = (v % 10) + '0';
11109               v /= 10;
11110               i++;
11111             }
11112           strcpy (buf, tmp + 29 - i);
11113         }
11114     }
11115   else
11116     {
11117       if (hex)
11118         sprintf (buf, "0x%x", (unsigned int) disp);
11119       else
11120         sprintf (buf, "%d", (int) disp);
11121     }
11122 }
11123
11124 /* Put DISP in BUF as signed hex number.  */
11125
11126 static void
11127 print_displacement (char *buf, bfd_vma disp)
11128 {
11129   bfd_signed_vma val = disp;
11130   char tmp[30];
11131   int i, j = 0;
11132
11133   if (val < 0)
11134     {
11135       buf[j++] = '-';
11136       val = -disp;
11137
11138       /* Check for possible overflow.  */
11139       if (val < 0)
11140         {
11141           switch (address_mode)
11142             {
11143             case mode_64bit:
11144               strcpy (buf + j, "0x8000000000000000");
11145               break;
11146             case mode_32bit:
11147               strcpy (buf + j, "0x80000000");
11148               break;
11149             case mode_16bit:
11150               strcpy (buf + j, "0x8000");
11151               break;
11152             }
11153           return;
11154         }
11155     }
11156
11157   buf[j++] = '0';
11158   buf[j++] = 'x';
11159
11160   sprintf_vma (tmp, (bfd_vma) val);
11161   for (i = 0; tmp[i] == '0'; i++)
11162     continue;
11163   if (tmp[i] == '\0')
11164     i--;
11165   strcpy (buf + j, tmp + i);
11166 }
11167
11168 static void
11169 intel_operand_size (int bytemode, int sizeflag)
11170 {
11171   if (vex.evex
11172       && vex.b
11173       && (bytemode == x_mode
11174           || bytemode == evex_half_bcst_xmmq_mode))
11175     {
11176       if (vex.w)
11177         oappend ("QWORD PTR ");
11178       else
11179         oappend ("DWORD PTR ");
11180       return;
11181     }
11182   switch (bytemode)
11183     {
11184     case b_mode:
11185     case b_swap_mode:
11186     case dqb_mode:
11187     case db_mode:
11188       oappend ("BYTE PTR ");
11189       break;
11190     case w_mode:
11191     case dw_mode:
11192     case dqw_mode:
11193       oappend ("WORD PTR ");
11194       break;
11195     case indir_v_mode:
11196       if (address_mode == mode_64bit && isa64 == intel64)
11197         {
11198           oappend ("QWORD PTR ");
11199           break;
11200         }
11201       /* Fall through.  */
11202     case stack_v_mode:
11203       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
11204         {
11205           oappend ("QWORD PTR ");
11206           break;
11207         }
11208       /* Fall through.  */
11209     case v_mode:
11210     case v_swap_mode:
11211     case dq_mode:
11212       USED_REX (REX_W);
11213       if (rex & REX_W)
11214         oappend ("QWORD PTR ");
11215       else if (bytemode == dq_mode)
11216         oappend ("DWORD PTR ");
11217       else
11218         {
11219           if (sizeflag & DFLAG)
11220             oappend ("DWORD PTR ");
11221           else
11222             oappend ("WORD PTR ");
11223           used_prefixes |= (prefixes & PREFIX_DATA);
11224         }
11225       break;
11226     case z_mode:
11227       if ((rex & REX_W) || (sizeflag & DFLAG))
11228         *obufp++ = 'D';
11229       oappend ("WORD PTR ");
11230       if (!(rex & REX_W))
11231         used_prefixes |= (prefixes & PREFIX_DATA);
11232       break;
11233     case a_mode:
11234       if (sizeflag & DFLAG)
11235         oappend ("QWORD PTR ");
11236       else
11237         oappend ("DWORD PTR ");
11238       used_prefixes |= (prefixes & PREFIX_DATA);
11239       break;
11240     case movsxd_mode:
11241       if (!(sizeflag & DFLAG) && isa64 == intel64)
11242         oappend ("WORD PTR ");
11243       else
11244         oappend ("DWORD PTR ");
11245       used_prefixes |= (prefixes & PREFIX_DATA);
11246       break;
11247     case d_mode:
11248     case d_swap_mode:
11249     case dqd_mode:
11250       oappend ("DWORD PTR ");
11251       break;
11252     case q_mode:
11253     case q_swap_mode:
11254       oappend ("QWORD PTR ");
11255       break;
11256     case m_mode:
11257       if (address_mode == mode_64bit)
11258         oappend ("QWORD PTR ");
11259       else
11260         oappend ("DWORD PTR ");
11261       break;
11262     case f_mode:
11263       if (sizeflag & DFLAG)
11264         oappend ("FWORD PTR ");
11265       else
11266         oappend ("DWORD PTR ");
11267       used_prefixes |= (prefixes & PREFIX_DATA);
11268       break;
11269     case t_mode:
11270       oappend ("TBYTE PTR ");
11271       break;
11272     case x_mode:
11273     case x_swap_mode:
11274     case evex_x_gscat_mode:
11275     case evex_x_nobcst_mode:
11276     case bw_unit_mode:
11277       if (need_vex)
11278         {
11279           switch (vex.length)
11280             {
11281             case 128:
11282               oappend ("XMMWORD PTR ");
11283               break;
11284             case 256:
11285               oappend ("YMMWORD PTR ");
11286               break;
11287             case 512:
11288               oappend ("ZMMWORD PTR ");
11289               break;
11290             default:
11291               abort ();
11292             }
11293         }
11294       else
11295         oappend ("XMMWORD PTR ");
11296       break;
11297     case xmm_mode:
11298       oappend ("XMMWORD PTR ");
11299       break;
11300     case ymm_mode:
11301       oappend ("YMMWORD PTR ");
11302       break;
11303     case xmmq_mode:
11304     case evex_half_bcst_xmmq_mode:
11305       if (!need_vex)
11306         abort ();
11307
11308       switch (vex.length)
11309         {
11310         case 128:
11311           oappend ("QWORD PTR ");
11312           break;
11313         case 256:
11314           oappend ("XMMWORD PTR ");
11315           break;
11316         case 512:
11317           oappend ("YMMWORD PTR ");
11318           break;
11319         default:
11320           abort ();
11321         }
11322       break;
11323     case xmm_mb_mode:
11324       if (!need_vex)
11325         abort ();
11326
11327       switch (vex.length)
11328         {
11329         case 128:
11330         case 256:
11331         case 512:
11332           oappend ("BYTE PTR ");
11333           break;
11334         default:
11335           abort ();
11336         }
11337       break;
11338     case xmm_mw_mode:
11339       if (!need_vex)
11340         abort ();
11341
11342       switch (vex.length)
11343         {
11344         case 128:
11345         case 256:
11346         case 512:
11347           oappend ("WORD PTR ");
11348           break;
11349         default:
11350           abort ();
11351         }
11352       break;
11353     case xmm_md_mode:
11354       if (!need_vex)
11355         abort ();
11356
11357       switch (vex.length)
11358         {
11359         case 128:
11360         case 256:
11361         case 512:
11362           oappend ("DWORD PTR ");
11363           break;
11364         default:
11365           abort ();
11366         }
11367       break;
11368     case xmm_mq_mode:
11369       if (!need_vex)
11370         abort ();
11371
11372       switch (vex.length)
11373         {
11374         case 128:
11375         case 256:
11376         case 512:
11377           oappend ("QWORD PTR ");
11378           break;
11379         default:
11380           abort ();
11381         }
11382       break;
11383     case xmmdw_mode:
11384       if (!need_vex)
11385         abort ();
11386
11387       switch (vex.length)
11388         {
11389         case 128:
11390           oappend ("WORD PTR ");
11391           break;
11392         case 256:
11393           oappend ("DWORD PTR ");
11394           break;
11395         case 512:
11396           oappend ("QWORD PTR ");
11397           break;
11398         default:
11399           abort ();
11400         }
11401       break;
11402     case xmmqd_mode:
11403       if (!need_vex)
11404         abort ();
11405
11406       switch (vex.length)
11407         {
11408         case 128:
11409           oappend ("DWORD PTR ");
11410           break;
11411         case 256:
11412           oappend ("QWORD PTR ");
11413           break;
11414         case 512:
11415           oappend ("XMMWORD PTR ");
11416           break;
11417         default:
11418           abort ();
11419         }
11420       break;
11421     case ymmq_mode:
11422       if (!need_vex)
11423         abort ();
11424
11425       switch (vex.length)
11426         {
11427         case 128:
11428           oappend ("QWORD PTR ");
11429           break;
11430         case 256:
11431           oappend ("YMMWORD PTR ");
11432           break;
11433         case 512:
11434           oappend ("ZMMWORD PTR ");
11435           break;
11436         default:
11437           abort ();
11438         }
11439       break;
11440     case ymmxmm_mode:
11441       if (!need_vex)
11442         abort ();
11443
11444       switch (vex.length)
11445         {
11446         case 128:
11447         case 256:
11448           oappend ("XMMWORD PTR ");
11449           break;
11450         default:
11451           abort ();
11452         }
11453       break;
11454     case o_mode:
11455       oappend ("OWORD PTR ");
11456       break;
11457     case vex_scalar_w_dq_mode:
11458       if (!need_vex)
11459         abort ();
11460
11461       if (vex.w)
11462         oappend ("QWORD PTR ");
11463       else
11464         oappend ("DWORD PTR ");
11465       break;
11466     case vex_vsib_d_w_dq_mode:
11467     case vex_vsib_q_w_dq_mode:
11468       if (!need_vex)
11469         abort ();
11470
11471       if (!vex.evex)
11472         {
11473           if (vex.w)
11474             oappend ("QWORD PTR ");
11475           else
11476             oappend ("DWORD PTR ");
11477         }
11478       else
11479         {
11480           switch (vex.length)
11481             {
11482             case 128:
11483               oappend ("XMMWORD PTR ");
11484               break;
11485             case 256:
11486               oappend ("YMMWORD PTR ");
11487               break;
11488             case 512:
11489               oappend ("ZMMWORD PTR ");
11490               break;
11491             default:
11492               abort ();
11493             }
11494         }
11495       break;
11496     case vex_vsib_q_w_d_mode:
11497     case vex_vsib_d_w_d_mode:
11498       if (!need_vex || !vex.evex)
11499         abort ();
11500
11501       switch (vex.length)
11502         {
11503         case 128:
11504           oappend ("QWORD PTR ");
11505           break;
11506         case 256:
11507           oappend ("XMMWORD PTR ");
11508           break;
11509         case 512:
11510           oappend ("YMMWORD PTR ");
11511           break;
11512         default:
11513           abort ();
11514         }
11515
11516       break;
11517     case mask_bd_mode:
11518       if (!need_vex || vex.length != 128)
11519         abort ();
11520       if (vex.w)
11521         oappend ("DWORD PTR ");
11522       else
11523         oappend ("BYTE PTR ");
11524       break;
11525     case mask_mode:
11526       if (!need_vex)
11527         abort ();
11528       if (vex.w)
11529         oappend ("QWORD PTR ");
11530       else
11531         oappend ("WORD PTR ");
11532       break;
11533     case v_bnd_mode:
11534     case v_bndmk_mode:
11535     default:
11536       break;
11537     }
11538 }
11539
11540 static void
11541 OP_E_register (int bytemode, int sizeflag)
11542 {
11543   int reg = modrm.rm;
11544   const char **names;
11545
11546   USED_REX (REX_B);
11547   if ((rex & REX_B))
11548     reg += 8;
11549
11550   if ((sizeflag & SUFFIX_ALWAYS)
11551       && (bytemode == b_swap_mode
11552           || bytemode == bnd_swap_mode
11553           || bytemode == v_swap_mode))
11554     swap_operand ();
11555
11556   switch (bytemode)
11557     {
11558     case b_mode:
11559     case b_swap_mode:
11560       if (reg & 4)
11561         USED_REX (0);
11562       if (rex)
11563         names = names8rex;
11564       else
11565         names = names8;
11566       break;
11567     case w_mode:
11568       names = names16;
11569       break;
11570     case d_mode:
11571     case dw_mode:
11572     case db_mode:
11573       names = names32;
11574       break;
11575     case q_mode:
11576       names = names64;
11577       break;
11578     case m_mode:
11579     case v_bnd_mode:
11580       names = address_mode == mode_64bit ? names64 : names32;
11581       break;
11582     case bnd_mode:
11583     case bnd_swap_mode:
11584       if (reg > 0x3)
11585         {
11586           oappend ("(bad)");
11587           return;
11588         }
11589       names = names_bnd;
11590       break;
11591     case indir_v_mode:
11592       if (address_mode == mode_64bit && isa64 == intel64)
11593         {
11594           names = names64;
11595           break;
11596         }
11597       /* Fall through.  */
11598     case stack_v_mode:
11599       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
11600         {
11601           names = names64;
11602           break;
11603         }
11604       bytemode = v_mode;
11605       /* Fall through.  */
11606     case v_mode:
11607     case v_swap_mode:
11608     case dq_mode:
11609     case dqb_mode:
11610     case dqd_mode:
11611     case dqw_mode:
11612       USED_REX (REX_W);
11613       if (rex & REX_W)
11614         names = names64;
11615       else if (bytemode != v_mode && bytemode != v_swap_mode)
11616         names = names32;
11617       else
11618         {
11619           if (sizeflag & DFLAG)
11620             names = names32;
11621           else
11622             names = names16;
11623           used_prefixes |= (prefixes & PREFIX_DATA);
11624         }
11625       break;
11626     case movsxd_mode:
11627       if (!(sizeflag & DFLAG) && isa64 == intel64)
11628         names = names16;
11629       else
11630         names = names32;
11631       used_prefixes |= (prefixes & PREFIX_DATA);
11632       break;
11633     case va_mode:
11634       names = (address_mode == mode_64bit
11635                ? names64 : names32);
11636       if (!(prefixes & PREFIX_ADDR))
11637         names = (address_mode == mode_16bit
11638                      ? names16 : names);
11639       else
11640         {
11641           /* Remove "addr16/addr32".  */
11642           all_prefixes[last_addr_prefix] = 0;
11643           names = (address_mode != mode_32bit
11644                        ? names32 : names16);
11645           used_prefixes |= PREFIX_ADDR;
11646         }
11647       break;
11648     case mask_bd_mode:
11649     case mask_mode:
11650       if (reg > 0x7)
11651         {
11652           oappend ("(bad)");
11653           return;
11654         }
11655       names = names_mask;
11656       break;
11657     case 0:
11658       return;
11659     default:
11660       oappend (INTERNAL_DISASSEMBLER_ERROR);
11661       return;
11662     }
11663   oappend (names[reg]);
11664 }
11665
11666 static void
11667 OP_E_memory (int bytemode, int sizeflag)
11668 {
11669   bfd_vma disp = 0;
11670   int add = (rex & REX_B) ? 8 : 0;
11671   int riprel = 0;
11672   int shift;
11673
11674   if (vex.evex)
11675     {
11676       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
11677       if (vex.b
11678           && bytemode != x_mode
11679           && bytemode != xmmq_mode
11680           && bytemode != evex_half_bcst_xmmq_mode)
11681         {
11682           BadOp ();
11683           return;
11684         }
11685       switch (bytemode)
11686         {
11687         case dqw_mode:
11688         case dw_mode:
11689         case xmm_mw_mode:
11690           shift = 1;
11691           break;
11692         case dqb_mode:
11693         case db_mode:
11694         case xmm_mb_mode:
11695           shift = 0;
11696           break;
11697         case dq_mode:
11698           if (address_mode != mode_64bit)
11699             {
11700         case dqd_mode:
11701         case xmm_md_mode:
11702         case d_mode:
11703         case d_swap_mode:
11704               shift = 2;
11705               break;
11706             }
11707             /* fall through */
11708         case vex_scalar_w_dq_mode:
11709         case vex_vsib_d_w_dq_mode:
11710         case vex_vsib_d_w_d_mode:
11711         case vex_vsib_q_w_dq_mode:
11712         case vex_vsib_q_w_d_mode:
11713         case evex_x_gscat_mode:
11714           shift = vex.w ? 3 : 2;
11715           break;
11716         case x_mode:
11717         case evex_half_bcst_xmmq_mode:
11718         case xmmq_mode:
11719           if (vex.b)
11720             {
11721               shift = vex.w ? 3 : 2;
11722               break;
11723             }
11724           /* Fall through.  */
11725         case xmmqd_mode:
11726         case xmmdw_mode:
11727         case ymmq_mode:
11728         case evex_x_nobcst_mode:
11729         case x_swap_mode:
11730           switch (vex.length)
11731             {
11732             case 128:
11733               shift = 4;
11734               break;
11735             case 256:
11736               shift = 5;
11737               break;
11738             case 512:
11739               shift = 6;
11740               break;
11741             default:
11742               abort ();
11743             }
11744           /* Make necessary corrections to shift for modes that need it.  */
11745           if (bytemode == xmmq_mode
11746               || bytemode == evex_half_bcst_xmmq_mode
11747               || (bytemode == ymmq_mode && vex.length == 128))
11748             shift -= 1;
11749           else if (bytemode == xmmqd_mode)
11750             shift -= 2;
11751           else if (bytemode == xmmdw_mode)
11752             shift -= 3;
11753           break;
11754         case ymm_mode:
11755           shift = 5;
11756           break;
11757         case xmm_mode:
11758           shift = 4;
11759           break;
11760         case xmm_mq_mode:
11761         case q_mode:
11762         case q_swap_mode:
11763           shift = 3;
11764           break;
11765         case bw_unit_mode:
11766           shift = vex.w ? 1 : 0;
11767           break;
11768         default:
11769           abort ();
11770         }
11771     }
11772   else
11773     shift = 0;
11774
11775   USED_REX (REX_B);
11776   if (intel_syntax)
11777     intel_operand_size (bytemode, sizeflag);
11778   append_seg ();
11779
11780   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11781     {
11782       /* 32/64 bit address mode */
11783       int havedisp;
11784       int havesib;
11785       int havebase;
11786       int haveindex;
11787       int needindex;
11788       int needaddr32;
11789       int base, rbase;
11790       int vindex = 0;
11791       int scale = 0;
11792       int addr32flag = !((sizeflag & AFLAG)
11793                          || bytemode == v_bnd_mode
11794                          || bytemode == v_bndmk_mode
11795                          || bytemode == bnd_mode
11796                          || bytemode == bnd_swap_mode);
11797       const char **indexes64 = names64;
11798       const char **indexes32 = names32;
11799
11800       havesib = 0;
11801       havebase = 1;
11802       haveindex = 0;
11803       base = modrm.rm;
11804
11805       if (base == 4)
11806         {
11807           havesib = 1;
11808           vindex = sib.index;
11809           USED_REX (REX_X);
11810           if (rex & REX_X)
11811             vindex += 8;
11812           switch (bytemode)
11813             {
11814             case vex_vsib_d_w_dq_mode:
11815             case vex_vsib_d_w_d_mode:
11816             case vex_vsib_q_w_dq_mode:
11817             case vex_vsib_q_w_d_mode:
11818               if (!need_vex)
11819                 abort ();
11820               if (vex.evex)
11821                 {
11822                   if (!vex.v)
11823                     vindex += 16;
11824                 }
11825
11826               haveindex = 1;
11827               switch (vex.length)
11828                 {
11829                 case 128:
11830                   indexes64 = indexes32 = names_xmm;
11831                   break;
11832                 case 256:
11833                   if (!vex.w
11834                       || bytemode == vex_vsib_q_w_dq_mode
11835                       || bytemode == vex_vsib_q_w_d_mode)
11836                     indexes64 = indexes32 = names_ymm;
11837                   else
11838                     indexes64 = indexes32 = names_xmm;
11839                   break;
11840                 case 512:
11841                   if (!vex.w
11842                       || bytemode == vex_vsib_q_w_dq_mode
11843                       || bytemode == vex_vsib_q_w_d_mode)
11844                     indexes64 = indexes32 = names_zmm;
11845                   else
11846                     indexes64 = indexes32 = names_ymm;
11847                   break;
11848                 default:
11849                   abort ();
11850                 }
11851               break;
11852             default:
11853               haveindex = vindex != 4;
11854               break;
11855             }
11856           scale = sib.scale;
11857           base = sib.base;
11858           codep++;
11859         }
11860       else
11861         {
11862           /* mandatory non-vector SIB must have sib */
11863           if (bytemode == vex_sibmem_mode)
11864             {
11865               oappend ("(bad)");
11866               return;
11867             }
11868         }
11869       rbase = base + add;
11870
11871       switch (modrm.mod)
11872         {
11873         case 0:
11874           if (base == 5)
11875             {
11876               havebase = 0;
11877               if (address_mode == mode_64bit && !havesib)
11878                 riprel = 1;
11879               disp = get32s ();
11880               if (riprel && bytemode == v_bndmk_mode)
11881                 {
11882                   oappend ("(bad)");
11883                   return;
11884                 }
11885             }
11886           break;
11887         case 1:
11888           FETCH_DATA (the_info, codep + 1);
11889           disp = *codep++;
11890           if ((disp & 0x80) != 0)
11891             disp -= 0x100;
11892           if (vex.evex && shift > 0)
11893             disp <<= shift;
11894           break;
11895         case 2:
11896           disp = get32s ();
11897           break;
11898         }
11899
11900       needindex = 0;
11901       needaddr32 = 0;
11902       if (havesib
11903           && !havebase
11904           && !haveindex
11905           && address_mode != mode_16bit)
11906         {
11907           if (address_mode == mode_64bit)
11908             {
11909               if (addr32flag)
11910                 {
11911                   /* Without base nor index registers, zero-extend the
11912                      lower 32-bit displacement to 64 bits.  */
11913                   disp = (unsigned int) disp;
11914                   needindex = 1;
11915                 }
11916               needaddr32 = 1;
11917             }
11918           else
11919             {
11920               /* In 32-bit mode, we need index register to tell [offset]
11921                  from [eiz*1 + offset].  */
11922               needindex = 1;
11923             }
11924         }
11925
11926       havedisp = (havebase
11927                   || needindex
11928                   || (havesib && (haveindex || scale != 0)));
11929
11930       if (!intel_syntax)
11931         if (modrm.mod != 0 || base == 5)
11932           {
11933             if (havedisp || riprel)
11934               print_displacement (scratchbuf, disp);
11935             else
11936               print_operand_value (scratchbuf, 1, disp);
11937             oappend (scratchbuf);
11938             if (riprel)
11939               {
11940                 set_op (disp, 1);
11941                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
11942               }
11943           }
11944
11945       if ((havebase || haveindex || needindex || needaddr32 || riprel)
11946           && (address_mode != mode_64bit
11947               || ((bytemode != v_bnd_mode)
11948                   && (bytemode != v_bndmk_mode)
11949                   && (bytemode != bnd_mode)
11950                   && (bytemode != bnd_swap_mode))))
11951         used_prefixes |= PREFIX_ADDR;
11952
11953       if (havedisp || (intel_syntax && riprel))
11954         {
11955           *obufp++ = open_char;
11956           if (intel_syntax && riprel)
11957             {
11958               set_op (disp, 1);
11959               oappend (!addr32flag ? "rip" : "eip");
11960             }
11961           *obufp = '\0';
11962           if (havebase)
11963             oappend (address_mode == mode_64bit && !addr32flag
11964                      ? names64[rbase] : names32[rbase]);
11965           if (havesib)
11966             {
11967               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
11968                  print index to tell base + index from base.  */
11969               if (scale != 0
11970                   || needindex
11971                   || haveindex
11972                   || (havebase && base != ESP_REG_NUM))
11973                 {
11974                   if (!intel_syntax || havebase)
11975                     {
11976                       *obufp++ = separator_char;
11977                       *obufp = '\0';
11978                     }
11979                   if (haveindex)
11980                     oappend (address_mode == mode_64bit && !addr32flag
11981                              ? indexes64[vindex] : indexes32[vindex]);
11982                   else
11983                     oappend (address_mode == mode_64bit && !addr32flag
11984                              ? index64 : index32);
11985
11986                   *obufp++ = scale_char;
11987                   *obufp = '\0';
11988                   sprintf (scratchbuf, "%d", 1 << scale);
11989                   oappend (scratchbuf);
11990                 }
11991             }
11992           if (intel_syntax
11993               && (disp || modrm.mod != 0 || base == 5))
11994             {
11995               if (!havedisp || (bfd_signed_vma) disp >= 0)
11996                 {
11997                   *obufp++ = '+';
11998                   *obufp = '\0';
11999                 }
12000               else if (modrm.mod != 1 && disp != -disp)
12001                 {
12002                   *obufp++ = '-';
12003                   *obufp = '\0';
12004                   disp = -disp;
12005                 }
12006
12007               if (havedisp)
12008                 print_displacement (scratchbuf, disp);
12009               else
12010                 print_operand_value (scratchbuf, 1, disp);
12011               oappend (scratchbuf);
12012             }
12013
12014           *obufp++ = close_char;
12015           *obufp = '\0';
12016         }
12017       else if (intel_syntax)
12018         {
12019           if (modrm.mod != 0 || base == 5)
12020             {
12021               if (!active_seg_prefix)
12022                 {
12023                   oappend (names_seg[ds_reg - es_reg]);
12024                   oappend (":");
12025                 }
12026               print_operand_value (scratchbuf, 1, disp);
12027               oappend (scratchbuf);
12028             }
12029         }
12030     }
12031   else if (bytemode == v_bnd_mode
12032            || bytemode == v_bndmk_mode
12033            || bytemode == bnd_mode
12034            || bytemode == bnd_swap_mode)
12035     {
12036       oappend ("(bad)");
12037       return;
12038     }
12039   else
12040     {
12041       /* 16 bit address mode */
12042       used_prefixes |= prefixes & PREFIX_ADDR;
12043       switch (modrm.mod)
12044         {
12045         case 0:
12046           if (modrm.rm == 6)
12047             {
12048               disp = get16 ();
12049               if ((disp & 0x8000) != 0)
12050                 disp -= 0x10000;
12051             }
12052           break;
12053         case 1:
12054           FETCH_DATA (the_info, codep + 1);
12055           disp = *codep++;
12056           if ((disp & 0x80) != 0)
12057             disp -= 0x100;
12058           if (vex.evex && shift > 0)
12059             disp <<= shift;
12060           break;
12061         case 2:
12062           disp = get16 ();
12063           if ((disp & 0x8000) != 0)
12064             disp -= 0x10000;
12065           break;
12066         }
12067
12068       if (!intel_syntax)
12069         if (modrm.mod != 0 || modrm.rm == 6)
12070           {
12071             print_displacement (scratchbuf, disp);
12072             oappend (scratchbuf);
12073           }
12074
12075       if (modrm.mod != 0 || modrm.rm != 6)
12076         {
12077           *obufp++ = open_char;
12078           *obufp = '\0';
12079           oappend (index16[modrm.rm]);
12080           if (intel_syntax
12081               && (disp || modrm.mod != 0 || modrm.rm == 6))
12082             {
12083               if ((bfd_signed_vma) disp >= 0)
12084                 {
12085                   *obufp++ = '+';
12086                   *obufp = '\0';
12087                 }
12088               else if (modrm.mod != 1)
12089                 {
12090                   *obufp++ = '-';
12091                   *obufp = '\0';
12092                   disp = -disp;
12093                 }
12094
12095               print_displacement (scratchbuf, disp);
12096               oappend (scratchbuf);
12097             }
12098
12099           *obufp++ = close_char;
12100           *obufp = '\0';
12101         }
12102       else if (intel_syntax)
12103         {
12104           if (!active_seg_prefix)
12105             {
12106               oappend (names_seg[ds_reg - es_reg]);
12107               oappend (":");
12108             }
12109           print_operand_value (scratchbuf, 1, disp & 0xffff);
12110           oappend (scratchbuf);
12111         }
12112     }
12113   if (vex.evex && vex.b
12114       && (bytemode == x_mode
12115           || bytemode == xmmq_mode
12116           || bytemode == evex_half_bcst_xmmq_mode))
12117     {
12118       if (vex.w
12119           || bytemode == xmmq_mode
12120           || bytemode == evex_half_bcst_xmmq_mode)
12121         {
12122           switch (vex.length)
12123             {
12124             case 128:
12125               oappend ("{1to2}");
12126               break;
12127             case 256:
12128               oappend ("{1to4}");
12129               break;
12130             case 512:
12131               oappend ("{1to8}");
12132               break;
12133             default:
12134               abort ();
12135             }
12136         }
12137       else
12138         {
12139           switch (vex.length)
12140             {
12141             case 128:
12142               oappend ("{1to4}");
12143               break;
12144             case 256:
12145               oappend ("{1to8}");
12146               break;
12147             case 512:
12148               oappend ("{1to16}");
12149               break;
12150             default:
12151               abort ();
12152             }
12153         }
12154     }
12155 }
12156
12157 static void
12158 OP_E (int bytemode, int sizeflag)
12159 {
12160   /* Skip mod/rm byte.  */
12161   MODRM_CHECK;
12162   codep++;
12163
12164   if (modrm.mod == 3)
12165     OP_E_register (bytemode, sizeflag);
12166   else
12167     OP_E_memory (bytemode, sizeflag);
12168 }
12169
12170 static void
12171 OP_G (int bytemode, int sizeflag)
12172 {
12173   int add = 0;
12174   const char **names;
12175   USED_REX (REX_R);
12176   if (rex & REX_R)
12177     add += 8;
12178   switch (bytemode)
12179     {
12180     case b_mode:
12181       if (modrm.reg & 4)
12182         USED_REX (0);
12183       if (rex)
12184         oappend (names8rex[modrm.reg + add]);
12185       else
12186         oappend (names8[modrm.reg + add]);
12187       break;
12188     case w_mode:
12189       oappend (names16[modrm.reg + add]);
12190       break;
12191     case d_mode:
12192     case db_mode:
12193     case dw_mode:
12194       oappend (names32[modrm.reg + add]);
12195       break;
12196     case q_mode:
12197       oappend (names64[modrm.reg + add]);
12198       break;
12199     case bnd_mode:
12200       if (modrm.reg > 0x3)
12201         {
12202           oappend ("(bad)");
12203           return;
12204         }
12205       oappend (names_bnd[modrm.reg]);
12206       break;
12207     case v_mode:
12208     case dq_mode:
12209     case dqb_mode:
12210     case dqd_mode:
12211     case dqw_mode:
12212     case movsxd_mode:
12213       USED_REX (REX_W);
12214       if (rex & REX_W)
12215         oappend (names64[modrm.reg + add]);
12216       else if (bytemode != v_mode && bytemode != movsxd_mode)
12217         oappend (names32[modrm.reg + add]);
12218       else
12219         {
12220           if (sizeflag & DFLAG)
12221             oappend (names32[modrm.reg + add]);
12222           else
12223             oappend (names16[modrm.reg + add]);
12224           used_prefixes |= (prefixes & PREFIX_DATA);
12225         }
12226       break;
12227     case va_mode:
12228       names = (address_mode == mode_64bit
12229                ? names64 : names32);
12230       if (!(prefixes & PREFIX_ADDR))
12231         {
12232           if (address_mode == mode_16bit)
12233             names = names16;
12234         }
12235       else
12236         {
12237           /* Remove "addr16/addr32".  */
12238           all_prefixes[last_addr_prefix] = 0;
12239           names = (address_mode != mode_32bit
12240                        ? names32 : names16);
12241           used_prefixes |= PREFIX_ADDR;
12242         }
12243       oappend (names[modrm.reg + add]);
12244       break;
12245     case m_mode:
12246       if (address_mode == mode_64bit)
12247         oappend (names64[modrm.reg + add]);
12248       else
12249         oappend (names32[modrm.reg + add]);
12250       break;
12251     case mask_bd_mode:
12252     case mask_mode:
12253       if ((modrm.reg + add) > 0x7)
12254         {
12255           oappend ("(bad)");
12256           return;
12257         }
12258       oappend (names_mask[modrm.reg + add]);
12259       break;
12260     default:
12261       oappend (INTERNAL_DISASSEMBLER_ERROR);
12262       break;
12263     }
12264 }
12265
12266 static bfd_vma
12267 get64 (void)
12268 {
12269   bfd_vma x;
12270 #ifdef BFD64
12271   unsigned int a;
12272   unsigned int b;
12273
12274   FETCH_DATA (the_info, codep + 8);
12275   a = *codep++ & 0xff;
12276   a |= (*codep++ & 0xff) << 8;
12277   a |= (*codep++ & 0xff) << 16;
12278   a |= (*codep++ & 0xffu) << 24;
12279   b = *codep++ & 0xff;
12280   b |= (*codep++ & 0xff) << 8;
12281   b |= (*codep++ & 0xff) << 16;
12282   b |= (*codep++ & 0xffu) << 24;
12283   x = a + ((bfd_vma) b << 32);
12284 #else
12285   abort ();
12286   x = 0;
12287 #endif
12288   return x;
12289 }
12290
12291 static bfd_signed_vma
12292 get32 (void)
12293 {
12294   bfd_vma x = 0;
12295
12296   FETCH_DATA (the_info, codep + 4);
12297   x = *codep++ & (bfd_vma) 0xff;
12298   x |= (*codep++ & (bfd_vma) 0xff) << 8;
12299   x |= (*codep++ & (bfd_vma) 0xff) << 16;
12300   x |= (*codep++ & (bfd_vma) 0xff) << 24;
12301   return x;
12302 }
12303
12304 static bfd_signed_vma
12305 get32s (void)
12306 {
12307   bfd_vma x = 0;
12308
12309   FETCH_DATA (the_info, codep + 4);
12310   x = *codep++ & (bfd_vma) 0xff;
12311   x |= (*codep++ & (bfd_vma) 0xff) << 8;
12312   x |= (*codep++ & (bfd_vma) 0xff) << 16;
12313   x |= (*codep++ & (bfd_vma) 0xff) << 24;
12314
12315   x = (x ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
12316
12317   return x;
12318 }
12319
12320 static int
12321 get16 (void)
12322 {
12323   int x = 0;
12324
12325   FETCH_DATA (the_info, codep + 2);
12326   x = *codep++ & 0xff;
12327   x |= (*codep++ & 0xff) << 8;
12328   return x;
12329 }
12330
12331 static void
12332 set_op (bfd_vma op, int riprel)
12333 {
12334   op_index[op_ad] = op_ad;
12335   if (address_mode == mode_64bit)
12336     {
12337       op_address[op_ad] = op;
12338       op_riprel[op_ad] = riprel;
12339     }
12340   else
12341     {
12342       /* Mask to get a 32-bit address.  */
12343       op_address[op_ad] = op & 0xffffffff;
12344       op_riprel[op_ad] = riprel & 0xffffffff;
12345     }
12346 }
12347
12348 static void
12349 OP_REG (int code, int sizeflag)
12350 {
12351   const char *s;
12352   int add;
12353
12354   switch (code)
12355     {
12356     case es_reg: case ss_reg: case cs_reg:
12357     case ds_reg: case fs_reg: case gs_reg:
12358       oappend (names_seg[code - es_reg]);
12359       return;
12360     }
12361
12362   USED_REX (REX_B);
12363   if (rex & REX_B)
12364     add = 8;
12365   else
12366     add = 0;
12367
12368   switch (code)
12369     {
12370     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12371     case sp_reg: case bp_reg: case si_reg: case di_reg:
12372       s = names16[code - ax_reg + add];
12373       break;
12374     case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12375       USED_REX (0);
12376       /* Fall through.  */
12377     case al_reg: case cl_reg: case dl_reg: case bl_reg:
12378       if (rex)
12379         s = names8rex[code - al_reg + add];
12380       else
12381         s = names8[code - al_reg];
12382       break;
12383     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12384     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12385       if (address_mode == mode_64bit
12386           && ((sizeflag & DFLAG) || (rex & REX_W)))
12387         {
12388           s = names64[code - rAX_reg + add];
12389           break;
12390         }
12391       code += eAX_reg - rAX_reg;
12392       /* Fall through.  */
12393     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12394     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12395       USED_REX (REX_W);
12396       if (rex & REX_W)
12397         s = names64[code - eAX_reg + add];
12398       else
12399         {
12400           if (sizeflag & DFLAG)
12401             s = names32[code - eAX_reg + add];
12402           else
12403             s = names16[code - eAX_reg + add];
12404           used_prefixes |= (prefixes & PREFIX_DATA);
12405         }
12406       break;
12407     default:
12408       s = INTERNAL_DISASSEMBLER_ERROR;
12409       break;
12410     }
12411   oappend (s);
12412 }
12413
12414 static void
12415 OP_IMREG (int code, int sizeflag)
12416 {
12417   const char *s;
12418
12419   switch (code)
12420     {
12421     case indir_dx_reg:
12422       if (intel_syntax)
12423         s = "dx";
12424       else
12425         s = "(%dx)";
12426       break;
12427     case al_reg: case cl_reg:
12428       s = names8[code - al_reg];
12429       break;
12430     case eAX_reg:
12431       USED_REX (REX_W);
12432       if (rex & REX_W)
12433         {
12434           s = *names64;
12435           break;
12436         }
12437       /* Fall through.  */
12438     case z_mode_ax_reg:
12439       if ((rex & REX_W) || (sizeflag & DFLAG))
12440         s = *names32;
12441       else
12442         s = *names16;
12443       if (!(rex & REX_W))
12444         used_prefixes |= (prefixes & PREFIX_DATA);
12445       break;
12446     default:
12447       s = INTERNAL_DISASSEMBLER_ERROR;
12448       break;
12449     }
12450   oappend (s);
12451 }
12452
12453 static void
12454 OP_I (int bytemode, int sizeflag)
12455 {
12456   bfd_signed_vma op;
12457   bfd_signed_vma mask = -1;
12458
12459   switch (bytemode)
12460     {
12461     case b_mode:
12462       FETCH_DATA (the_info, codep + 1);
12463       op = *codep++;
12464       mask = 0xff;
12465       break;
12466     case v_mode:
12467       USED_REX (REX_W);
12468       if (rex & REX_W)
12469         op = get32s ();
12470       else
12471         {
12472           if (sizeflag & DFLAG)
12473             {
12474               op = get32 ();
12475               mask = 0xffffffff;
12476             }
12477           else
12478             {
12479               op = get16 ();
12480               mask = 0xfffff;
12481             }
12482           used_prefixes |= (prefixes & PREFIX_DATA);
12483         }
12484       break;
12485     case d_mode:
12486       mask = 0xffffffff;
12487       op = get32 ();
12488       break;
12489     case w_mode:
12490       mask = 0xfffff;
12491       op = get16 ();
12492       break;
12493     case const_1_mode:
12494       if (intel_syntax)
12495         oappend ("1");
12496       return;
12497     default:
12498       oappend (INTERNAL_DISASSEMBLER_ERROR);
12499       return;
12500     }
12501
12502   op &= mask;
12503   scratchbuf[0] = '$';
12504   print_operand_value (scratchbuf + 1, 1, op);
12505   oappend_maybe_intel (scratchbuf);
12506   scratchbuf[0] = '\0';
12507 }
12508
12509 static void
12510 OP_I64 (int bytemode, int sizeflag)
12511 {
12512   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
12513     {
12514       OP_I (bytemode, sizeflag);
12515       return;
12516     }
12517
12518   USED_REX (REX_W);
12519
12520   scratchbuf[0] = '$';
12521   print_operand_value (scratchbuf + 1, 1, get64 ());
12522   oappend_maybe_intel (scratchbuf);
12523   scratchbuf[0] = '\0';
12524 }
12525
12526 static void
12527 OP_sI (int bytemode, int sizeflag)
12528 {
12529   bfd_signed_vma op;
12530
12531   switch (bytemode)
12532     {
12533     case b_mode:
12534     case b_T_mode:
12535       FETCH_DATA (the_info, codep + 1);
12536       op = *codep++;
12537       if ((op & 0x80) != 0)
12538         op -= 0x100;
12539       if (bytemode == b_T_mode)
12540         {
12541           if (address_mode != mode_64bit
12542               || !((sizeflag & DFLAG) || (rex & REX_W)))
12543             {
12544               /* The operand-size prefix is overridden by a REX prefix.  */
12545               if ((sizeflag & DFLAG) || (rex & REX_W))
12546                 op &= 0xffffffff;
12547               else
12548                 op &= 0xffff;
12549           }
12550         }
12551       else
12552         {
12553           if (!(rex & REX_W))
12554             {
12555               if (sizeflag & DFLAG)
12556                 op &= 0xffffffff;
12557               else
12558                 op &= 0xffff;
12559             }
12560         }
12561       break;
12562     case v_mode:
12563       /* The operand-size prefix is overridden by a REX prefix.  */
12564       if ((sizeflag & DFLAG) || (rex & REX_W))
12565         op = get32s ();
12566       else
12567         op = get16 ();
12568       break;
12569     default:
12570       oappend (INTERNAL_DISASSEMBLER_ERROR);
12571       return;
12572     }
12573
12574   scratchbuf[0] = '$';
12575   print_operand_value (scratchbuf + 1, 1, op);
12576   oappend_maybe_intel (scratchbuf);
12577 }
12578
12579 static void
12580 OP_J (int bytemode, int sizeflag)
12581 {
12582   bfd_vma disp;
12583   bfd_vma mask = -1;
12584   bfd_vma segment = 0;
12585
12586   switch (bytemode)
12587     {
12588     case b_mode:
12589       FETCH_DATA (the_info, codep + 1);
12590       disp = *codep++;
12591       if ((disp & 0x80) != 0)
12592         disp -= 0x100;
12593       break;
12594     case v_mode:
12595     case dqw_mode:
12596       if ((sizeflag & DFLAG)
12597           || (address_mode == mode_64bit
12598               && ((isa64 == intel64 && bytemode != dqw_mode)
12599                   || (rex & REX_W))))
12600         disp = get32s ();
12601       else
12602         {
12603           disp = get16 ();
12604           if ((disp & 0x8000) != 0)
12605             disp -= 0x10000;
12606           /* In 16bit mode, address is wrapped around at 64k within
12607              the same segment.  Otherwise, a data16 prefix on a jump
12608              instruction means that the pc is masked to 16 bits after
12609              the displacement is added!  */
12610           mask = 0xffff;
12611           if ((prefixes & PREFIX_DATA) == 0)
12612             segment = ((start_pc + (codep - start_codep))
12613                        & ~((bfd_vma) 0xffff));
12614         }
12615       if (address_mode != mode_64bit
12616           || (isa64 != intel64 && !(rex & REX_W)))
12617         used_prefixes |= (prefixes & PREFIX_DATA);
12618       break;
12619     default:
12620       oappend (INTERNAL_DISASSEMBLER_ERROR);
12621       return;
12622     }
12623   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
12624   set_op (disp, 0);
12625   print_operand_value (scratchbuf, 1, disp);
12626   oappend (scratchbuf);
12627 }
12628
12629 static void
12630 OP_SEG (int bytemode, int sizeflag)
12631 {
12632   if (bytemode == w_mode)
12633     oappend (names_seg[modrm.reg]);
12634   else
12635     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12636 }
12637
12638 static void
12639 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
12640 {
12641   int seg, offset;
12642
12643   if (sizeflag & DFLAG)
12644     {
12645       offset = get32 ();
12646       seg = get16 ();
12647     }
12648   else
12649     {
12650       offset = get16 ();
12651       seg = get16 ();
12652     }
12653   used_prefixes |= (prefixes & PREFIX_DATA);
12654   if (intel_syntax)
12655     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
12656   else
12657     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
12658   oappend (scratchbuf);
12659 }
12660
12661 static void
12662 OP_OFF (int bytemode, int sizeflag)
12663 {
12664   bfd_vma off;
12665
12666   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12667     intel_operand_size (bytemode, sizeflag);
12668   append_seg ();
12669
12670   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12671     off = get32 ();
12672   else
12673     off = get16 ();
12674
12675   if (intel_syntax)
12676     {
12677       if (!active_seg_prefix)
12678         {
12679           oappend (names_seg[ds_reg - es_reg]);
12680           oappend (":");
12681         }
12682     }
12683   print_operand_value (scratchbuf, 1, off);
12684   oappend (scratchbuf);
12685 }
12686
12687 static void
12688 OP_OFF64 (int bytemode, int sizeflag)
12689 {
12690   bfd_vma off;
12691
12692   if (address_mode != mode_64bit
12693       || (prefixes & PREFIX_ADDR))
12694     {
12695       OP_OFF (bytemode, sizeflag);
12696       return;
12697     }
12698
12699   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12700     intel_operand_size (bytemode, sizeflag);
12701   append_seg ();
12702
12703   off = get64 ();
12704
12705   if (intel_syntax)
12706     {
12707       if (!active_seg_prefix)
12708         {
12709           oappend (names_seg[ds_reg - es_reg]);
12710           oappend (":");
12711         }
12712     }
12713   print_operand_value (scratchbuf, 1, off);
12714   oappend (scratchbuf);
12715 }
12716
12717 static void
12718 ptr_reg (int code, int sizeflag)
12719 {
12720   const char *s;
12721
12722   *obufp++ = open_char;
12723   used_prefixes |= (prefixes & PREFIX_ADDR);
12724   if (address_mode == mode_64bit)
12725     {
12726       if (!(sizeflag & AFLAG))
12727         s = names32[code - eAX_reg];
12728       else
12729         s = names64[code - eAX_reg];
12730     }
12731   else if (sizeflag & AFLAG)
12732     s = names32[code - eAX_reg];
12733   else
12734     s = names16[code - eAX_reg];
12735   oappend (s);
12736   *obufp++ = close_char;
12737   *obufp = 0;
12738 }
12739
12740 static void
12741 OP_ESreg (int code, int sizeflag)
12742 {
12743   if (intel_syntax)
12744     {
12745       switch (codep[-1])
12746         {
12747         case 0x6d:      /* insw/insl */
12748           intel_operand_size (z_mode, sizeflag);
12749           break;
12750         case 0xa5:      /* movsw/movsl/movsq */
12751         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12752         case 0xab:      /* stosw/stosl */
12753         case 0xaf:      /* scasw/scasl */
12754           intel_operand_size (v_mode, sizeflag);
12755           break;
12756         default:
12757           intel_operand_size (b_mode, sizeflag);
12758         }
12759     }
12760   oappend_maybe_intel ("%es:");
12761   ptr_reg (code, sizeflag);
12762 }
12763
12764 static void
12765 OP_DSreg (int code, int sizeflag)
12766 {
12767   if (intel_syntax)
12768     {
12769       switch (codep[-1])
12770         {
12771         case 0x6f:      /* outsw/outsl */
12772           intel_operand_size (z_mode, sizeflag);
12773           break;
12774         case 0xa5:      /* movsw/movsl/movsq */
12775         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12776         case 0xad:      /* lodsw/lodsl/lodsq */
12777           intel_operand_size (v_mode, sizeflag);
12778           break;
12779         default:
12780           intel_operand_size (b_mode, sizeflag);
12781         }
12782     }
12783   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
12784      default segment register DS is printed.  */
12785   if (!active_seg_prefix)
12786     active_seg_prefix = PREFIX_DS;
12787   append_seg ();
12788   ptr_reg (code, sizeflag);
12789 }
12790
12791 static void
12792 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12793 {
12794   int add;
12795   if (rex & REX_R)
12796     {
12797       USED_REX (REX_R);
12798       add = 8;
12799     }
12800   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
12801     {
12802       all_prefixes[last_lock_prefix] = 0;
12803       used_prefixes |= PREFIX_LOCK;
12804       add = 8;
12805     }
12806   else
12807     add = 0;
12808   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
12809   oappend_maybe_intel (scratchbuf);
12810 }
12811
12812 static void
12813 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12814 {
12815   int add;
12816   USED_REX (REX_R);
12817   if (rex & REX_R)
12818     add = 8;
12819   else
12820     add = 0;
12821   if (intel_syntax)
12822     sprintf (scratchbuf, "dr%d", modrm.reg + add);
12823   else
12824     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
12825   oappend (scratchbuf);
12826 }
12827
12828 static void
12829 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12830 {
12831   sprintf (scratchbuf, "%%tr%d", modrm.reg);
12832   oappend_maybe_intel (scratchbuf);
12833 }
12834
12835 static void
12836 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12837 {
12838   int reg = modrm.reg;
12839   const char **names;
12840
12841   used_prefixes |= (prefixes & PREFIX_DATA);
12842   if (prefixes & PREFIX_DATA)
12843     {
12844       names = names_xmm;
12845       USED_REX (REX_R);
12846       if (rex & REX_R)
12847         reg += 8;
12848     }
12849   else
12850     names = names_mm;
12851   oappend (names[reg]);
12852 }
12853
12854 static void
12855 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12856 {
12857   int reg = modrm.reg;
12858   const char **names;
12859
12860   USED_REX (REX_R);
12861   if (rex & REX_R)
12862     reg += 8;
12863   if (vex.evex)
12864     {
12865       if (!vex.r)
12866         reg += 16;
12867     }
12868
12869   if (need_vex
12870       && bytemode != xmm_mode
12871       && bytemode != xmmq_mode
12872       && bytemode != evex_half_bcst_xmmq_mode
12873       && bytemode != ymm_mode
12874       && bytemode != tmm_mode
12875       && bytemode != scalar_mode)
12876     {
12877       switch (vex.length)
12878         {
12879         case 128:
12880           names = names_xmm;
12881           break;
12882         case 256:
12883           if (vex.w
12884               || (bytemode != vex_vsib_q_w_dq_mode
12885                   && bytemode != vex_vsib_q_w_d_mode))
12886             names = names_ymm;
12887           else
12888             names = names_xmm;
12889           break;
12890         case 512:
12891           names = names_zmm;
12892           break;
12893         default:
12894           abort ();
12895         }
12896     }
12897   else if (bytemode == xmmq_mode
12898            || bytemode == evex_half_bcst_xmmq_mode)
12899     {
12900       switch (vex.length)
12901         {
12902         case 128:
12903         case 256:
12904           names = names_xmm;
12905           break;
12906         case 512:
12907           names = names_ymm;
12908           break;
12909         default:
12910           abort ();
12911         }
12912     }
12913   else if (bytemode == tmm_mode)
12914     {
12915       modrm.reg = reg;
12916       if (reg >= 8)
12917         {
12918           oappend ("(bad)");
12919           return;
12920         }
12921       names = names_tmm;
12922     }
12923   else if (bytemode == ymm_mode)
12924     names = names_ymm;
12925   else
12926     names = names_xmm;
12927   oappend (names[reg]);
12928 }
12929
12930 static void
12931 OP_EM (int bytemode, int sizeflag)
12932 {
12933   int reg;
12934   const char **names;
12935
12936   if (modrm.mod != 3)
12937     {
12938       if (intel_syntax
12939           && (bytemode == v_mode || bytemode == v_swap_mode))
12940         {
12941           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12942           used_prefixes |= (prefixes & PREFIX_DATA);
12943         }
12944       OP_E (bytemode, sizeflag);
12945       return;
12946     }
12947
12948   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12949     swap_operand ();
12950
12951   /* Skip mod/rm byte.  */
12952   MODRM_CHECK;
12953   codep++;
12954   used_prefixes |= (prefixes & PREFIX_DATA);
12955   reg = modrm.rm;
12956   if (prefixes & PREFIX_DATA)
12957     {
12958       names = names_xmm;
12959       USED_REX (REX_B);
12960       if (rex & REX_B)
12961         reg += 8;
12962     }
12963   else
12964     names = names_mm;
12965   oappend (names[reg]);
12966 }
12967
12968 /* cvt* are the only instructions in sse2 which have
12969    both SSE and MMX operands and also have 0x66 prefix
12970    in their opcode. 0x66 was originally used to differentiate
12971    between SSE and MMX instruction(operands). So we have to handle the
12972    cvt* separately using OP_EMC and OP_MXC */
12973 static void
12974 OP_EMC (int bytemode, int sizeflag)
12975 {
12976   if (modrm.mod != 3)
12977     {
12978       if (intel_syntax && bytemode == v_mode)
12979         {
12980           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12981           used_prefixes |= (prefixes & PREFIX_DATA);
12982         }
12983       OP_E (bytemode, sizeflag);
12984       return;
12985     }
12986
12987   /* Skip mod/rm byte.  */
12988   MODRM_CHECK;
12989   codep++;
12990   used_prefixes |= (prefixes & PREFIX_DATA);
12991   oappend (names_mm[modrm.rm]);
12992 }
12993
12994 static void
12995 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12996 {
12997   used_prefixes |= (prefixes & PREFIX_DATA);
12998   oappend (names_mm[modrm.reg]);
12999 }
13000
13001 static void
13002 OP_EX (int bytemode, int sizeflag)
13003 {
13004   int reg;
13005   const char **names;
13006
13007   /* Skip mod/rm byte.  */
13008   MODRM_CHECK;
13009   codep++;
13010
13011   if (modrm.mod != 3)
13012     {
13013       OP_E_memory (bytemode, sizeflag);
13014       return;
13015     }
13016
13017   reg = modrm.rm;
13018   USED_REX (REX_B);
13019   if (rex & REX_B)
13020     reg += 8;
13021   if (vex.evex)
13022     {
13023       USED_REX (REX_X);
13024       if ((rex & REX_X))
13025         reg += 16;
13026     }
13027
13028   if ((sizeflag & SUFFIX_ALWAYS)
13029       && (bytemode == x_swap_mode
13030           || bytemode == d_swap_mode
13031           || bytemode == q_swap_mode))
13032     swap_operand ();
13033
13034   if (need_vex
13035       && bytemode != xmm_mode
13036       && bytemode != xmmdw_mode
13037       && bytemode != xmmqd_mode
13038       && bytemode != xmm_mb_mode
13039       && bytemode != xmm_mw_mode
13040       && bytemode != xmm_md_mode
13041       && bytemode != xmm_mq_mode
13042       && bytemode != xmmq_mode
13043       && bytemode != evex_half_bcst_xmmq_mode
13044       && bytemode != ymm_mode
13045       && bytemode != tmm_mode
13046       && bytemode != vex_scalar_w_dq_mode)
13047     {
13048       switch (vex.length)
13049         {
13050         case 128:
13051           names = names_xmm;
13052           break;
13053         case 256:
13054           names = names_ymm;
13055           break;
13056         case 512:
13057           names = names_zmm;
13058           break;
13059         default:
13060           abort ();
13061         }
13062     }
13063   else if (bytemode == xmmq_mode
13064            || bytemode == evex_half_bcst_xmmq_mode)
13065     {
13066       switch (vex.length)
13067         {
13068         case 128:
13069         case 256:
13070           names = names_xmm;
13071           break;
13072         case 512:
13073           names = names_ymm;
13074           break;
13075         default:
13076           abort ();
13077         }
13078     }
13079   else if (bytemode == tmm_mode)
13080     {
13081       modrm.rm = reg;
13082       if (reg >= 8)
13083         {
13084           oappend ("(bad)");
13085           return;
13086         }
13087       names = names_tmm;
13088     }
13089   else if (bytemode == ymm_mode)
13090     names = names_ymm;
13091   else
13092     names = names_xmm;
13093   oappend (names[reg]);
13094 }
13095
13096 static void
13097 OP_MS (int bytemode, int sizeflag)
13098 {
13099   if (modrm.mod == 3)
13100     OP_EM (bytemode, sizeflag);
13101   else
13102     BadOp ();
13103 }
13104
13105 static void
13106 OP_XS (int bytemode, int sizeflag)
13107 {
13108   if (modrm.mod == 3)
13109     OP_EX (bytemode, sizeflag);
13110   else
13111     BadOp ();
13112 }
13113
13114 static void
13115 OP_M (int bytemode, int sizeflag)
13116 {
13117   if (modrm.mod == 3)
13118     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13119     BadOp ();
13120   else
13121     OP_E (bytemode, sizeflag);
13122 }
13123
13124 static void
13125 OP_0f07 (int bytemode, int sizeflag)
13126 {
13127   if (modrm.mod != 3 || modrm.rm != 0)
13128     BadOp ();
13129   else
13130     OP_E (bytemode, sizeflag);
13131 }
13132
13133 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13134    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
13135
13136 static void
13137 NOP_Fixup1 (int bytemode, int sizeflag)
13138 {
13139   if ((prefixes & PREFIX_DATA) != 0
13140       || (rex != 0
13141           && rex != 0x48
13142           && address_mode == mode_64bit))
13143     OP_REG (bytemode, sizeflag);
13144   else
13145     strcpy (obuf, "nop");
13146 }
13147
13148 static void
13149 NOP_Fixup2 (int bytemode, int sizeflag)
13150 {
13151   if ((prefixes & PREFIX_DATA) != 0
13152       || (rex != 0
13153           && rex != 0x48
13154           && address_mode == mode_64bit))
13155     OP_IMREG (bytemode, sizeflag);
13156 }
13157
13158 static const char *const Suffix3DNow[] = {
13159 /* 00 */        NULL,           NULL,           NULL,           NULL,
13160 /* 04 */        NULL,           NULL,           NULL,           NULL,
13161 /* 08 */        NULL,           NULL,           NULL,           NULL,
13162 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
13163 /* 10 */        NULL,           NULL,           NULL,           NULL,
13164 /* 14 */        NULL,           NULL,           NULL,           NULL,
13165 /* 18 */        NULL,           NULL,           NULL,           NULL,
13166 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
13167 /* 20 */        NULL,           NULL,           NULL,           NULL,
13168 /* 24 */        NULL,           NULL,           NULL,           NULL,
13169 /* 28 */        NULL,           NULL,           NULL,           NULL,
13170 /* 2C */        NULL,           NULL,           NULL,           NULL,
13171 /* 30 */        NULL,           NULL,           NULL,           NULL,
13172 /* 34 */        NULL,           NULL,           NULL,           NULL,
13173 /* 38 */        NULL,           NULL,           NULL,           NULL,
13174 /* 3C */        NULL,           NULL,           NULL,           NULL,
13175 /* 40 */        NULL,           NULL,           NULL,           NULL,
13176 /* 44 */        NULL,           NULL,           NULL,           NULL,
13177 /* 48 */        NULL,           NULL,           NULL,           NULL,
13178 /* 4C */        NULL,           NULL,           NULL,           NULL,
13179 /* 50 */        NULL,           NULL,           NULL,           NULL,
13180 /* 54 */        NULL,           NULL,           NULL,           NULL,
13181 /* 58 */        NULL,           NULL,           NULL,           NULL,
13182 /* 5C */        NULL,           NULL,           NULL,           NULL,
13183 /* 60 */        NULL,           NULL,           NULL,           NULL,
13184 /* 64 */        NULL,           NULL,           NULL,           NULL,
13185 /* 68 */        NULL,           NULL,           NULL,           NULL,
13186 /* 6C */        NULL,           NULL,           NULL,           NULL,
13187 /* 70 */        NULL,           NULL,           NULL,           NULL,
13188 /* 74 */        NULL,           NULL,           NULL,           NULL,
13189 /* 78 */        NULL,           NULL,           NULL,           NULL,
13190 /* 7C */        NULL,           NULL,           NULL,           NULL,
13191 /* 80 */        NULL,           NULL,           NULL,           NULL,
13192 /* 84 */        NULL,           NULL,           NULL,           NULL,
13193 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
13194 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
13195 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
13196 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
13197 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
13198 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
13199 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
13200 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
13201 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
13202 /* AC */        NULL,           NULL,           "pfacc",        NULL,
13203 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
13204 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
13205 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
13206 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
13207 /* C0 */        NULL,           NULL,           NULL,           NULL,
13208 /* C4 */        NULL,           NULL,           NULL,           NULL,
13209 /* C8 */        NULL,           NULL,           NULL,           NULL,
13210 /* CC */        NULL,           NULL,           NULL,           NULL,
13211 /* D0 */        NULL,           NULL,           NULL,           NULL,
13212 /* D4 */        NULL,           NULL,           NULL,           NULL,
13213 /* D8 */        NULL,           NULL,           NULL,           NULL,
13214 /* DC */        NULL,           NULL,           NULL,           NULL,
13215 /* E0 */        NULL,           NULL,           NULL,           NULL,
13216 /* E4 */        NULL,           NULL,           NULL,           NULL,
13217 /* E8 */        NULL,           NULL,           NULL,           NULL,
13218 /* EC */        NULL,           NULL,           NULL,           NULL,
13219 /* F0 */        NULL,           NULL,           NULL,           NULL,
13220 /* F4 */        NULL,           NULL,           NULL,           NULL,
13221 /* F8 */        NULL,           NULL,           NULL,           NULL,
13222 /* FC */        NULL,           NULL,           NULL,           NULL,
13223 };
13224
13225 static void
13226 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13227 {
13228   const char *mnemonic;
13229
13230   FETCH_DATA (the_info, codep + 1);
13231   /* AMD 3DNow! instructions are specified by an opcode suffix in the
13232      place where an 8-bit immediate would normally go.  ie. the last
13233      byte of the instruction.  */
13234   obufp = mnemonicendp;
13235   mnemonic = Suffix3DNow[*codep++ & 0xff];
13236   if (mnemonic)
13237     oappend (mnemonic);
13238   else
13239     {
13240       /* Since a variable sized modrm/sib chunk is between the start
13241          of the opcode (0x0f0f) and the opcode suffix, we need to do
13242          all the modrm processing first, and don't know until now that
13243          we have a bad opcode.  This necessitates some cleaning up.  */
13244       op_out[0][0] = '\0';
13245       op_out[1][0] = '\0';
13246       BadOp ();
13247     }
13248   mnemonicendp = obufp;
13249 }
13250
13251 static const struct op simd_cmp_op[] =
13252 {
13253   { STRING_COMMA_LEN ("eq") },
13254   { STRING_COMMA_LEN ("lt") },
13255   { STRING_COMMA_LEN ("le") },
13256   { STRING_COMMA_LEN ("unord") },
13257   { STRING_COMMA_LEN ("neq") },
13258   { STRING_COMMA_LEN ("nlt") },
13259   { STRING_COMMA_LEN ("nle") },
13260   { STRING_COMMA_LEN ("ord") }
13261 };
13262
13263 static const struct op vex_cmp_op[] =
13264 {
13265   { STRING_COMMA_LEN ("eq_uq") },
13266   { STRING_COMMA_LEN ("nge") },
13267   { STRING_COMMA_LEN ("ngt") },
13268   { STRING_COMMA_LEN ("false") },
13269   { STRING_COMMA_LEN ("neq_oq") },
13270   { STRING_COMMA_LEN ("ge") },
13271   { STRING_COMMA_LEN ("gt") },
13272   { STRING_COMMA_LEN ("true") },
13273   { STRING_COMMA_LEN ("eq_os") },
13274   { STRING_COMMA_LEN ("lt_oq") },
13275   { STRING_COMMA_LEN ("le_oq") },
13276   { STRING_COMMA_LEN ("unord_s") },
13277   { STRING_COMMA_LEN ("neq_us") },
13278   { STRING_COMMA_LEN ("nlt_uq") },
13279   { STRING_COMMA_LEN ("nle_uq") },
13280   { STRING_COMMA_LEN ("ord_s") },
13281   { STRING_COMMA_LEN ("eq_us") },
13282   { STRING_COMMA_LEN ("nge_uq") },
13283   { STRING_COMMA_LEN ("ngt_uq") },
13284   { STRING_COMMA_LEN ("false_os") },
13285   { STRING_COMMA_LEN ("neq_os") },
13286   { STRING_COMMA_LEN ("ge_oq") },
13287   { STRING_COMMA_LEN ("gt_oq") },
13288   { STRING_COMMA_LEN ("true_us") },
13289 };
13290
13291 static void
13292 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13293 {
13294   unsigned int cmp_type;
13295
13296   FETCH_DATA (the_info, codep + 1);
13297   cmp_type = *codep++ & 0xff;
13298   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13299     {
13300       char suffix [3];
13301       char *p = mnemonicendp - 2;
13302       suffix[0] = p[0];
13303       suffix[1] = p[1];
13304       suffix[2] = '\0';
13305       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13306       mnemonicendp += simd_cmp_op[cmp_type].len;
13307     }
13308   else if (need_vex
13309            && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13310     {
13311       char suffix [3];
13312       char *p = mnemonicendp - 2;
13313       suffix[0] = p[0];
13314       suffix[1] = p[1];
13315       suffix[2] = '\0';
13316       cmp_type -= ARRAY_SIZE (simd_cmp_op);
13317       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13318       mnemonicendp += vex_cmp_op[cmp_type].len;
13319     }
13320   else
13321     {
13322       /* We have a reserved extension byte.  Output it directly.  */
13323       scratchbuf[0] = '$';
13324       print_operand_value (scratchbuf + 1, 1, cmp_type);
13325       oappend_maybe_intel (scratchbuf);
13326       scratchbuf[0] = '\0';
13327     }
13328 }
13329
13330 static void
13331 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13332 {
13333   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
13334   if (!intel_syntax)
13335     {
13336       strcpy (op_out[0], names32[0]);
13337       strcpy (op_out[1], names32[1]);
13338       if (bytemode == eBX_reg)
13339         strcpy (op_out[2], names32[3]);
13340       two_source_ops = 1;
13341     }
13342   /* Skip mod/rm byte.  */
13343   MODRM_CHECK;
13344   codep++;
13345 }
13346
13347 static void
13348 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
13349             int sizeflag ATTRIBUTE_UNUSED)
13350 {
13351   /* monitor %{e,r,}ax,%ecx,%edx"  */
13352   if (!intel_syntax)
13353     {
13354       const char **names = (address_mode == mode_64bit
13355                             ? names64 : names32);
13356
13357       if (prefixes & PREFIX_ADDR)
13358         {
13359           /* Remove "addr16/addr32".  */
13360           all_prefixes[last_addr_prefix] = 0;
13361           names = (address_mode != mode_32bit
13362                    ? names32 : names16);
13363           used_prefixes |= PREFIX_ADDR;
13364         }
13365       else if (address_mode == mode_16bit)
13366         names = names16;
13367       strcpy (op_out[0], names[0]);
13368       strcpy (op_out[1], names32[1]);
13369       strcpy (op_out[2], names32[2]);
13370       two_source_ops = 1;
13371     }
13372   /* Skip mod/rm byte.  */
13373   MODRM_CHECK;
13374   codep++;
13375 }
13376
13377 static void
13378 BadOp (void)
13379 {
13380   /* Throw away prefixes and 1st. opcode byte.  */
13381   codep = insn_codep + 1;
13382   oappend ("(bad)");
13383 }
13384
13385 static void
13386 REP_Fixup (int bytemode, int sizeflag)
13387 {
13388   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13389      lods and stos.  */
13390   if (prefixes & PREFIX_REPZ)
13391     all_prefixes[last_repz_prefix] = REP_PREFIX;
13392
13393   switch (bytemode)
13394     {
13395     case al_reg:
13396     case eAX_reg:
13397     case indir_dx_reg:
13398       OP_IMREG (bytemode, sizeflag);
13399       break;
13400     case eDI_reg:
13401       OP_ESreg (bytemode, sizeflag);
13402       break;
13403     case eSI_reg:
13404       OP_DSreg (bytemode, sizeflag);
13405       break;
13406     default:
13407       abort ();
13408       break;
13409     }
13410 }
13411
13412 static void
13413 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13414 {
13415   if ( isa64 != amd64 )
13416     return;
13417
13418   obufp = obuf;
13419   BadOp ();
13420   mnemonicendp = obufp;
13421   ++codep;
13422 }
13423
13424 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13425    "bnd".  */
13426
13427 static void
13428 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13429 {
13430   if (prefixes & PREFIX_REPNZ)
13431     all_prefixes[last_repnz_prefix] = BND_PREFIX;
13432 }
13433
13434 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13435    "notrack".  */
13436
13437 static void
13438 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
13439                int sizeflag ATTRIBUTE_UNUSED)
13440 {
13441   if (active_seg_prefix == PREFIX_DS
13442       && (address_mode != mode_64bit || last_data_prefix < 0))
13443     {
13444       /* NOTRACK prefix is only valid on indirect branch instructions.
13445          NB: DATA prefix is unsupported for Intel64.  */
13446       active_seg_prefix = 0;
13447       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
13448     }
13449 }
13450
13451 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
13452    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13453  */
13454
13455 static void
13456 HLE_Fixup1 (int bytemode, int sizeflag)
13457 {
13458   if (modrm.mod != 3
13459       && (prefixes & PREFIX_LOCK) != 0)
13460     {
13461       if (prefixes & PREFIX_REPZ)
13462         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13463       if (prefixes & PREFIX_REPNZ)
13464         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13465     }
13466
13467   OP_E (bytemode, sizeflag);
13468 }
13469
13470 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
13471    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
13472  */
13473
13474 static void
13475 HLE_Fixup2 (int bytemode, int sizeflag)
13476 {
13477   if (modrm.mod != 3)
13478     {
13479       if (prefixes & PREFIX_REPZ)
13480         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13481       if (prefixes & PREFIX_REPNZ)
13482         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13483     }
13484
13485   OP_E (bytemode, sizeflag);
13486 }
13487
13488 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
13489    "xrelease" for memory operand.  No check for LOCK prefix.   */
13490
13491 static void
13492 HLE_Fixup3 (int bytemode, int sizeflag)
13493 {
13494   if (modrm.mod != 3
13495       && last_repz_prefix > last_repnz_prefix
13496       && (prefixes & PREFIX_REPZ) != 0)
13497     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13498
13499   OP_E (bytemode, sizeflag);
13500 }
13501
13502 static void
13503 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
13504 {
13505   USED_REX (REX_W);
13506   if (rex & REX_W)
13507     {
13508       /* Change cmpxchg8b to cmpxchg16b.  */
13509       char *p = mnemonicendp - 2;
13510       mnemonicendp = stpcpy (p, "16b");
13511       bytemode = o_mode;
13512     }
13513   else if ((prefixes & PREFIX_LOCK) != 0)
13514     {
13515       if (prefixes & PREFIX_REPZ)
13516         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13517       if (prefixes & PREFIX_REPNZ)
13518         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13519     }
13520
13521   OP_M (bytemode, sizeflag);
13522 }
13523
13524 static void
13525 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
13526 {
13527   const char **names;
13528
13529   if (need_vex)
13530     {
13531       switch (vex.length)
13532         {
13533         case 128:
13534           names = names_xmm;
13535           break;
13536         case 256:
13537           names = names_ymm;
13538           break;
13539         default:
13540           abort ();
13541         }
13542     }
13543   else
13544     names = names_xmm;
13545   oappend (names[reg]);
13546 }
13547
13548 static void
13549 FXSAVE_Fixup (int bytemode, int sizeflag)
13550 {
13551   /* Add proper suffix to "fxsave" and "fxrstor".  */
13552   USED_REX (REX_W);
13553   if (rex & REX_W)
13554     {
13555       char *p = mnemonicendp;
13556       *p++ = '6';
13557       *p++ = '4';
13558       *p = '\0';
13559       mnemonicendp = p;
13560     }
13561   OP_M (bytemode, sizeflag);
13562 }
13563
13564 /* Display the destination register operand for instructions with
13565    VEX. */
13566
13567 static void
13568 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13569 {
13570   int reg;
13571   const char **names;
13572
13573   if (!need_vex)
13574     abort ();
13575
13576   reg = vex.register_specifier;
13577   vex.register_specifier = 0;
13578   if (address_mode != mode_64bit)
13579     reg &= 7;
13580   else if (vex.evex && !vex.v)
13581     reg += 16;
13582
13583   if (bytemode == vex_scalar_mode)
13584     {
13585       oappend (names_xmm[reg]);
13586       return;
13587     }
13588
13589   if (bytemode == tmm_mode)
13590     {
13591       /* All 3 TMM registers must be distinct.  */
13592       if (reg >= 8)
13593         oappend ("(bad)");
13594       else
13595         {
13596           /* This must be the 3rd operand.  */
13597           if (obufp != op_out[2])
13598             abort ();
13599           oappend (names_tmm[reg]);
13600           if (reg == modrm.reg || reg == modrm.rm)
13601             strcpy (obufp, "/(bad)");
13602         }
13603
13604       if (modrm.reg == modrm.rm || modrm.reg == reg || modrm.rm == reg)
13605         {
13606           if (modrm.reg <= 8
13607               && (modrm.reg == modrm.rm || modrm.reg == reg))
13608             strcat (op_out[0], "/(bad)");
13609           if (modrm.rm <= 8
13610               && (modrm.rm == modrm.reg || modrm.rm == reg))
13611             strcat (op_out[1], "/(bad)");
13612         }
13613
13614       return;
13615     }
13616
13617   switch (vex.length)
13618     {
13619     case 128:
13620       switch (bytemode)
13621         {
13622         case vex_mode:
13623         case vex_vsib_q_w_dq_mode:
13624         case vex_vsib_q_w_d_mode:
13625           names = names_xmm;
13626           break;
13627         case dq_mode:
13628           if (rex & REX_W)
13629             names = names64;
13630           else
13631             names = names32;
13632           break;
13633         case mask_bd_mode:
13634         case mask_mode:
13635           if (reg > 0x7)
13636             {
13637               oappend ("(bad)");
13638               return;
13639             }
13640           names = names_mask;
13641           break;
13642         default:
13643           abort ();
13644           return;
13645         }
13646       break;
13647     case 256:
13648       switch (bytemode)
13649         {
13650         case vex_mode:
13651           names = names_ymm;
13652           break;
13653         case vex_vsib_q_w_dq_mode:
13654         case vex_vsib_q_w_d_mode:
13655           names = vex.w ? names_ymm : names_xmm;
13656           break;
13657         case mask_bd_mode:
13658         case mask_mode:
13659           if (reg > 0x7)
13660             {
13661               oappend ("(bad)");
13662               return;
13663             }
13664           names = names_mask;
13665           break;
13666         default:
13667           /* See PR binutils/20893 for a reproducer.  */
13668           oappend ("(bad)");
13669           return;
13670         }
13671       break;
13672     case 512:
13673       names = names_zmm;
13674       break;
13675     default:
13676       abort ();
13677       break;
13678     }
13679   oappend (names[reg]);
13680 }
13681
13682 static void
13683 OP_VexR (int bytemode, int sizeflag)
13684 {
13685   if (modrm.mod == 3)
13686     OP_VEX (bytemode, sizeflag);
13687 }
13688
13689 static void
13690 OP_VexW (int bytemode, int sizeflag)
13691 {
13692   OP_VEX (bytemode, sizeflag);
13693
13694   if (vex.w)
13695     {
13696       /* Swap 2nd and 3rd operands.  */
13697       strcpy (scratchbuf, op_out[2]);
13698       strcpy (op_out[2], op_out[1]);
13699       strcpy (op_out[1], scratchbuf);
13700     }
13701 }
13702
13703 static void
13704 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13705 {
13706   int reg;
13707   const char **names = names_xmm;
13708
13709   FETCH_DATA (the_info, codep + 1);
13710   reg = *codep++;
13711
13712   if (bytemode != x_mode && bytemode != scalar_mode)
13713     abort ();
13714
13715   reg >>= 4;
13716   if (address_mode != mode_64bit)
13717     reg &= 7;
13718
13719   if (bytemode == x_mode && vex.length == 256)
13720     names = names_ymm;
13721
13722   oappend (names[reg]);
13723
13724   if (vex.w)
13725     {
13726       /* Swap 3rd and 4th operands.  */
13727       strcpy (scratchbuf, op_out[3]);
13728       strcpy (op_out[3], op_out[2]);
13729       strcpy (op_out[2], scratchbuf);
13730     }
13731 }
13732
13733 static void
13734 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED,
13735           int sizeflag ATTRIBUTE_UNUSED)
13736 {
13737   scratchbuf[0] = '$';
13738   print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf);
13739   oappend_maybe_intel (scratchbuf);
13740 }
13741
13742 static void
13743 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
13744              int sizeflag ATTRIBUTE_UNUSED)
13745 {
13746   unsigned int cmp_type;
13747
13748   if (!vex.evex)
13749     abort ();
13750
13751   FETCH_DATA (the_info, codep + 1);
13752   cmp_type = *codep++ & 0xff;
13753   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13754      If it's the case, print suffix, otherwise - print the immediate.  */
13755   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13756       && cmp_type != 3
13757       && cmp_type != 7)
13758     {
13759       char suffix [3];
13760       char *p = mnemonicendp - 2;
13761
13762       /* vpcmp* can have both one- and two-lettered suffix.  */
13763       if (p[0] == 'p')
13764         {
13765           p++;
13766           suffix[0] = p[0];
13767           suffix[1] = '\0';
13768         }
13769       else
13770         {
13771           suffix[0] = p[0];
13772           suffix[1] = p[1];
13773           suffix[2] = '\0';
13774         }
13775
13776       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13777       mnemonicendp += simd_cmp_op[cmp_type].len;
13778     }
13779   else
13780     {
13781       /* We have a reserved extension byte.  Output it directly.  */
13782       scratchbuf[0] = '$';
13783       print_operand_value (scratchbuf + 1, 1, cmp_type);
13784       oappend_maybe_intel (scratchbuf);
13785       scratchbuf[0] = '\0';
13786     }
13787 }
13788
13789 static const struct op xop_cmp_op[] =
13790 {
13791   { STRING_COMMA_LEN ("lt") },
13792   { STRING_COMMA_LEN ("le") },
13793   { STRING_COMMA_LEN ("gt") },
13794   { STRING_COMMA_LEN ("ge") },
13795   { STRING_COMMA_LEN ("eq") },
13796   { STRING_COMMA_LEN ("neq") },
13797   { STRING_COMMA_LEN ("false") },
13798   { STRING_COMMA_LEN ("true") }
13799 };
13800
13801 static void
13802 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
13803              int sizeflag ATTRIBUTE_UNUSED)
13804 {
13805   unsigned int cmp_type;
13806
13807   FETCH_DATA (the_info, codep + 1);
13808   cmp_type = *codep++ & 0xff;
13809   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13810     {
13811       char suffix[3];
13812       char *p = mnemonicendp - 2;
13813
13814       /* vpcom* can have both one- and two-lettered suffix.  */
13815       if (p[0] == 'm')
13816         {
13817           p++;
13818           suffix[0] = p[0];
13819           suffix[1] = '\0';
13820         }
13821       else
13822         {
13823           suffix[0] = p[0];
13824           suffix[1] = p[1];
13825           suffix[2] = '\0';
13826         }
13827
13828       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13829       mnemonicendp += xop_cmp_op[cmp_type].len;
13830     }
13831   else
13832     {
13833       /* We have a reserved extension byte.  Output it directly.  */
13834       scratchbuf[0] = '$';
13835       print_operand_value (scratchbuf + 1, 1, cmp_type);
13836       oappend_maybe_intel (scratchbuf);
13837       scratchbuf[0] = '\0';
13838     }
13839 }
13840
13841 static const struct op pclmul_op[] =
13842 {
13843   { STRING_COMMA_LEN ("lql") },
13844   { STRING_COMMA_LEN ("hql") },
13845   { STRING_COMMA_LEN ("lqh") },
13846   { STRING_COMMA_LEN ("hqh") }
13847 };
13848
13849 static void
13850 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
13851               int sizeflag ATTRIBUTE_UNUSED)
13852 {
13853   unsigned int pclmul_type;
13854
13855   FETCH_DATA (the_info, codep + 1);
13856   pclmul_type = *codep++ & 0xff;
13857   switch (pclmul_type)
13858     {
13859     case 0x10:
13860       pclmul_type = 2;
13861       break;
13862     case 0x11:
13863       pclmul_type = 3;
13864       break;
13865     default:
13866       break;
13867     }
13868   if (pclmul_type < ARRAY_SIZE (pclmul_op))
13869     {
13870       char suffix [4];
13871       char *p = mnemonicendp - 3;
13872       suffix[0] = p[0];
13873       suffix[1] = p[1];
13874       suffix[2] = p[2];
13875       suffix[3] = '\0';
13876       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13877       mnemonicendp += pclmul_op[pclmul_type].len;
13878     }
13879   else
13880     {
13881       /* We have a reserved extension byte.  Output it directly.  */
13882       scratchbuf[0] = '$';
13883       print_operand_value (scratchbuf + 1, 1, pclmul_type);
13884       oappend_maybe_intel (scratchbuf);
13885       scratchbuf[0] = '\0';
13886     }
13887 }
13888
13889 static void
13890 MOVSXD_Fixup (int bytemode, int sizeflag)
13891 {
13892   /* Add proper suffix to "movsxd".  */
13893   char *p = mnemonicendp;
13894
13895   switch (bytemode)
13896     {
13897     case movsxd_mode:
13898       if (intel_syntax)
13899         {
13900           *p++ = 'x';
13901           *p++ = 'd';
13902           goto skip;
13903         }
13904
13905       USED_REX (REX_W);
13906       if (rex & REX_W)
13907         {
13908           *p++ = 'l';
13909           *p++ = 'q';
13910         }
13911       else
13912         {
13913           *p++ = 'x';
13914           *p++ = 'd';
13915         }
13916       break;
13917     default:
13918       oappend (INTERNAL_DISASSEMBLER_ERROR);
13919       break;
13920     }
13921
13922  skip:
13923   mnemonicendp = p;
13924   *p = '\0';
13925   OP_E (bytemode, sizeflag);
13926 }
13927
13928 static void
13929 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13930 {
13931   if (!vex.evex
13932       || (bytemode != mask_mode && bytemode != mask_bd_mode))
13933     abort ();
13934
13935   USED_REX (REX_R);
13936   if ((rex & REX_R) != 0 || !vex.r)
13937     {
13938       BadOp ();
13939       return;
13940     }
13941
13942   oappend (names_mask [modrm.reg]);
13943 }
13944
13945 static void
13946 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13947 {
13948   if (modrm.mod == 3 && vex.b)
13949     switch (bytemode)
13950       {
13951       case evex_rounding_64_mode:
13952         if (address_mode != mode_64bit)
13953           {
13954             oappend ("(bad)");
13955             break;
13956           }
13957         /* Fall through.  */
13958       case evex_rounding_mode:
13959         oappend (names_rounding[vex.ll]);
13960         break;
13961       case evex_sae_mode:
13962         oappend ("{sae}");
13963         break;
13964       default:
13965         abort ();
13966         break;
13967       }
13968 }