1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2020 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VCMP_Fixup (int, int);
99 static void VPCMP_Fixup (int, int);
100 static void VPCOM_Fixup (int, int);
101 static void OP_0f07 (int, int);
102 static void OP_Monitor (int, int);
103 static void OP_Mwait (int, int);
104 static void NOP_Fixup1 (int, int);
105 static void NOP_Fixup2 (int, int);
106 static void OP_3DNowSuffix (int, int);
107 static void CMP_Fixup (int, int);
108 static void BadOp (void);
109 static void REP_Fixup (int, int);
110 static void SEP_Fixup (int, int);
111 static void BND_Fixup (int, int);
112 static void NOTRACK_Fixup (int, int);
113 static void HLE_Fixup1 (int, int);
114 static void HLE_Fixup2 (int, int);
115 static void HLE_Fixup3 (int, int);
116 static void CMPXCHG8B_Fixup (int, int);
117 static void XMM_Fixup (int, int);
118 static void CRC32_Fixup (int, int);
119 static void FXSAVE_Fixup (int, int);
120 static void PCMPESTR_Fixup (int, int);
121 static void OP_LWPCB_E (int, int);
122 static void OP_LWP_E (int, int);
123 static void OP_Vex_2src_1 (int, int);
124 static void OP_Vex_2src_2 (int, int);
126 static void MOVBE_Fixup (int, int);
127 static void MOVSXD_Fixup (int, int);
129 static void OP_Mask (int, int);
132 /* Points to first byte not fetched. */
133 bfd_byte
*max_fetched
;
134 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
137 OPCODES_SIGJMP_BUF bailout
;
147 enum address_mode address_mode
;
149 /* Flags for the prefixes for the current instruction. See below. */
152 /* REX prefix the current instruction. See below. */
154 /* Bits of REX we've already used. */
156 /* REX bits in original REX prefix ignored. */
157 static int rex_ignored
;
158 /* Mark parts used in the REX prefix. When we are testing for
159 empty prefix (for 8bit register REX extension), just mask it
160 out. Otherwise test for REX bit is excuse for existence of REX
161 only in case value is nonzero. */
162 #define USED_REX(value) \
167 rex_used |= (value) | REX_OPCODE; \
170 rex_used |= REX_OPCODE; \
173 /* Flags for prefixes which we somehow handled when printing the
174 current instruction. */
175 static int used_prefixes
;
177 /* Flags stored in PREFIXES. */
178 #define PREFIX_REPZ 1
179 #define PREFIX_REPNZ 2
180 #define PREFIX_LOCK 4
182 #define PREFIX_SS 0x10
183 #define PREFIX_DS 0x20
184 #define PREFIX_ES 0x40
185 #define PREFIX_FS 0x80
186 #define PREFIX_GS 0x100
187 #define PREFIX_DATA 0x200
188 #define PREFIX_ADDR 0x400
189 #define PREFIX_FWAIT 0x800
191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
192 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
194 #define FETCH_DATA(info, addr) \
195 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
196 ? 1 : fetch_data ((info), (addr)))
199 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
202 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
203 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
205 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
206 status
= (*info
->read_memory_func
) (start
,
208 addr
- priv
->max_fetched
,
214 /* If we did manage to read at least one byte, then
215 print_insn_i386 will do something sensible. Otherwise, print
216 an error. We do that here because this is where we know
218 if (priv
->max_fetched
== priv
->the_buffer
)
219 (*info
->memory_error_func
) (status
, start
, info
);
220 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
223 priv
->max_fetched
= addr
;
227 /* Possible values for prefix requirement. */
228 #define PREFIX_IGNORED_SHIFT 16
229 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
233 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
235 /* Opcode prefixes. */
236 #define PREFIX_OPCODE (PREFIX_REPZ \
240 /* Prefixes ignored. */
241 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
242 | PREFIX_IGNORED_REPNZ \
243 | PREFIX_IGNORED_DATA)
245 #define XX { NULL, 0 }
246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
248 #define Eb { OP_E, b_mode }
249 #define Ebnd { OP_E, bnd_mode }
250 #define EbS { OP_E, b_swap_mode }
251 #define EbndS { OP_E, bnd_swap_mode }
252 #define Ev { OP_E, v_mode }
253 #define Eva { OP_E, va_mode }
254 #define Ev_bnd { OP_E, v_bnd_mode }
255 #define EvS { OP_E, v_swap_mode }
256 #define Ed { OP_E, d_mode }
257 #define Edq { OP_E, dq_mode }
258 #define Edqw { OP_E, dqw_mode }
259 #define Edqb { OP_E, dqb_mode }
260 #define Edb { OP_E, db_mode }
261 #define Edw { OP_E, dw_mode }
262 #define Edqd { OP_E, dqd_mode }
263 #define Eq { OP_E, q_mode }
264 #define indirEv { OP_indirE, indir_v_mode }
265 #define indirEp { OP_indirE, f_mode }
266 #define stackEv { OP_E, stack_v_mode }
267 #define Em { OP_E, m_mode }
268 #define Ew { OP_E, w_mode }
269 #define M { OP_M, 0 } /* lea, lgdt, etc. */
270 #define Ma { OP_M, a_mode }
271 #define Mb { OP_M, b_mode }
272 #define Md { OP_M, d_mode }
273 #define Mo { OP_M, o_mode }
274 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
275 #define Mq { OP_M, q_mode }
276 #define Mv_bnd { OP_M, v_bndmk_mode }
277 #define Mx { OP_M, x_mode }
278 #define Mxmm { OP_M, xmm_mode }
279 #define Gb { OP_G, b_mode }
280 #define Gbnd { OP_G, bnd_mode }
281 #define Gv { OP_G, v_mode }
282 #define Gd { OP_G, d_mode }
283 #define Gdq { OP_G, dq_mode }
284 #define Gm { OP_G, m_mode }
285 #define Gva { OP_G, va_mode }
286 #define Gw { OP_G, w_mode }
287 #define Rd { OP_R, d_mode }
288 #define Rdq { OP_R, dq_mode }
289 #define Rm { OP_R, m_mode }
290 #define Ib { OP_I, b_mode }
291 #define sIb { OP_sI, b_mode } /* sign extened byte */
292 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
293 #define Iv { OP_I, v_mode }
294 #define sIv { OP_sI, v_mode }
295 #define Iv64 { OP_I64, v_mode }
296 #define Id { OP_I, d_mode }
297 #define Iw { OP_I, w_mode }
298 #define I1 { OP_I, const_1_mode }
299 #define Jb { OP_J, b_mode }
300 #define Jv { OP_J, v_mode }
301 #define Jdqw { OP_J, dqw_mode }
302 #define Cm { OP_C, m_mode }
303 #define Dm { OP_D, m_mode }
304 #define Td { OP_T, d_mode }
305 #define Skip_MODRM { OP_Skip_MODRM, 0 }
307 #define RMeAX { OP_REG, eAX_reg }
308 #define RMeBX { OP_REG, eBX_reg }
309 #define RMeCX { OP_REG, eCX_reg }
310 #define RMeDX { OP_REG, eDX_reg }
311 #define RMeSP { OP_REG, eSP_reg }
312 #define RMeBP { OP_REG, eBP_reg }
313 #define RMeSI { OP_REG, eSI_reg }
314 #define RMeDI { OP_REG, eDI_reg }
315 #define RMrAX { OP_REG, rAX_reg }
316 #define RMrBX { OP_REG, rBX_reg }
317 #define RMrCX { OP_REG, rCX_reg }
318 #define RMrDX { OP_REG, rDX_reg }
319 #define RMrSP { OP_REG, rSP_reg }
320 #define RMrBP { OP_REG, rBP_reg }
321 #define RMrSI { OP_REG, rSI_reg }
322 #define RMrDI { OP_REG, rDI_reg }
323 #define RMAL { OP_REG, al_reg }
324 #define RMCL { OP_REG, cl_reg }
325 #define RMDL { OP_REG, dl_reg }
326 #define RMBL { OP_REG, bl_reg }
327 #define RMAH { OP_REG, ah_reg }
328 #define RMCH { OP_REG, ch_reg }
329 #define RMDH { OP_REG, dh_reg }
330 #define RMBH { OP_REG, bh_reg }
331 #define RMAX { OP_REG, ax_reg }
332 #define RMDX { OP_REG, dx_reg }
334 #define eAX { OP_IMREG, eAX_reg }
335 #define eBX { OP_IMREG, eBX_reg }
336 #define eCX { OP_IMREG, eCX_reg }
337 #define eDX { OP_IMREG, eDX_reg }
338 #define eSP { OP_IMREG, eSP_reg }
339 #define eBP { OP_IMREG, eBP_reg }
340 #define eSI { OP_IMREG, eSI_reg }
341 #define eDI { OP_IMREG, eDI_reg }
342 #define AL { OP_IMREG, al_reg }
343 #define CL { OP_IMREG, cl_reg }
344 #define DL { OP_IMREG, dl_reg }
345 #define BL { OP_IMREG, bl_reg }
346 #define AH { OP_IMREG, ah_reg }
347 #define CH { OP_IMREG, ch_reg }
348 #define DH { OP_IMREG, dh_reg }
349 #define BH { OP_IMREG, bh_reg }
350 #define AX { OP_IMREG, ax_reg }
351 #define DX { OP_IMREG, dx_reg }
352 #define zAX { OP_IMREG, z_mode_ax_reg }
353 #define indirDX { OP_IMREG, indir_dx_reg }
355 #define Sw { OP_SEG, w_mode }
356 #define Sv { OP_SEG, v_mode }
357 #define Ap { OP_DIR, 0 }
358 #define Ob { OP_OFF64, b_mode }
359 #define Ov { OP_OFF64, v_mode }
360 #define Xb { OP_DSreg, eSI_reg }
361 #define Xv { OP_DSreg, eSI_reg }
362 #define Xz { OP_DSreg, eSI_reg }
363 #define Yb { OP_ESreg, eDI_reg }
364 #define Yv { OP_ESreg, eDI_reg }
365 #define DSBX { OP_DSreg, eBX_reg }
367 #define es { OP_REG, es_reg }
368 #define ss { OP_REG, ss_reg }
369 #define cs { OP_REG, cs_reg }
370 #define ds { OP_REG, ds_reg }
371 #define fs { OP_REG, fs_reg }
372 #define gs { OP_REG, gs_reg }
374 #define MX { OP_MMX, 0 }
375 #define XM { OP_XMM, 0 }
376 #define XMScalar { OP_XMM, scalar_mode }
377 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
378 #define XMM { OP_XMM, xmm_mode }
379 #define XMxmmq { OP_XMM, xmmq_mode }
380 #define EM { OP_EM, v_mode }
381 #define EMS { OP_EM, v_swap_mode }
382 #define EMd { OP_EM, d_mode }
383 #define EMx { OP_EM, x_mode }
384 #define EXbScalar { OP_EX, b_scalar_mode }
385 #define EXw { OP_EX, w_mode }
386 #define EXwScalar { OP_EX, w_scalar_mode }
387 #define EXd { OP_EX, d_mode }
388 #define EXdScalar { OP_EX, d_scalar_mode }
389 #define EXdS { OP_EX, d_swap_mode }
390 #define EXq { OP_EX, q_mode }
391 #define EXqScalar { OP_EX, q_scalar_mode }
392 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
393 #define EXqS { OP_EX, q_swap_mode }
394 #define EXx { OP_EX, x_mode }
395 #define EXxS { OP_EX, x_swap_mode }
396 #define EXxmm { OP_EX, xmm_mode }
397 #define EXymm { OP_EX, ymm_mode }
398 #define EXxmmq { OP_EX, xmmq_mode }
399 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
400 #define EXxmm_mb { OP_EX, xmm_mb_mode }
401 #define EXxmm_mw { OP_EX, xmm_mw_mode }
402 #define EXxmm_md { OP_EX, xmm_md_mode }
403 #define EXxmm_mq { OP_EX, xmm_mq_mode }
404 #define EXxmmdw { OP_EX, xmmdw_mode }
405 #define EXxmmqd { OP_EX, xmmqd_mode }
406 #define EXymmq { OP_EX, ymmq_mode }
407 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
408 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
409 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
410 #define MS { OP_MS, v_mode }
411 #define XS { OP_XS, v_mode }
412 #define EMCq { OP_EMC, q_mode }
413 #define MXC { OP_MXC, 0 }
414 #define OPSUF { OP_3DNowSuffix, 0 }
415 #define SEP { SEP_Fixup, 0 }
416 #define CMP { CMP_Fixup, 0 }
417 #define XMM0 { XMM_Fixup, 0 }
418 #define FXSAVE { FXSAVE_Fixup, 0 }
419 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
420 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
422 #define Vex { OP_VEX, vex_mode }
423 #define VexScalar { OP_VEX, vex_scalar_mode }
424 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
425 #define Vex128 { OP_VEX, vex128_mode }
426 #define Vex256 { OP_VEX, vex256_mode }
427 #define VexGdq { OP_VEX, dq_mode }
428 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
429 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
430 #define EXVexW { OP_EX_VexW, x_mode }
431 #define EXdVexW { OP_EX_VexW, d_mode }
432 #define EXqVexW { OP_EX_VexW, q_mode }
433 #define EXVexImmW { OP_EX_VexImmW, x_mode }
434 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
435 #define XMVexW { OP_XMM_VexW, 0 }
436 #define XMVexI4 { OP_REG_VexI4, x_mode }
437 #define PCLMUL { PCLMUL_Fixup, 0 }
438 #define VCMP { VCMP_Fixup, 0 }
439 #define VPCMP { VPCMP_Fixup, 0 }
440 #define VPCOM { VPCOM_Fixup, 0 }
442 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
443 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
444 #define EXxEVexS { OP_Rounding, evex_sae_mode }
446 #define XMask { OP_Mask, mask_mode }
447 #define MaskG { OP_G, mask_mode }
448 #define MaskE { OP_E, mask_mode }
449 #define MaskBDE { OP_E, mask_bd_mode }
450 #define MaskR { OP_R, mask_mode }
451 #define MaskVex { OP_VEX, mask_mode }
453 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
454 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
455 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
456 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
458 /* Used handle "rep" prefix for string instructions. */
459 #define Xbr { REP_Fixup, eSI_reg }
460 #define Xvr { REP_Fixup, eSI_reg }
461 #define Ybr { REP_Fixup, eDI_reg }
462 #define Yvr { REP_Fixup, eDI_reg }
463 #define Yzr { REP_Fixup, eDI_reg }
464 #define indirDXr { REP_Fixup, indir_dx_reg }
465 #define ALr { REP_Fixup, al_reg }
466 #define eAXr { REP_Fixup, eAX_reg }
468 /* Used handle HLE prefix for lockable instructions. */
469 #define Ebh1 { HLE_Fixup1, b_mode }
470 #define Evh1 { HLE_Fixup1, v_mode }
471 #define Ebh2 { HLE_Fixup2, b_mode }
472 #define Evh2 { HLE_Fixup2, v_mode }
473 #define Ebh3 { HLE_Fixup3, b_mode }
474 #define Evh3 { HLE_Fixup3, v_mode }
476 #define BND { BND_Fixup, 0 }
477 #define NOTRACK { NOTRACK_Fixup, 0 }
479 #define cond_jump_flag { NULL, cond_jump_mode }
480 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
482 /* bits in sizeflag */
483 #define SUFFIX_ALWAYS 4
491 /* byte operand with operand swapped */
493 /* byte operand, sign extend like 'T' suffix */
495 /* operand size depends on prefixes */
497 /* operand size depends on prefixes with operand swapped */
499 /* operand size depends on address prefix */
503 /* double word operand */
505 /* double word operand with operand swapped */
507 /* quad word operand */
509 /* quad word operand with operand swapped */
511 /* ten-byte operand */
513 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
514 broadcast enabled. */
516 /* Similar to x_mode, but with different EVEX mem shifts. */
518 /* Similar to x_mode, but with disabled broadcast. */
520 /* Similar to x_mode, but with operands swapped and disabled broadcast
523 /* 16-byte XMM operand */
525 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
526 memory operand (depending on vector length). Broadcast isn't
529 /* Same as xmmq_mode, but broadcast is allowed. */
530 evex_half_bcst_xmmq_mode
,
531 /* XMM register or byte memory operand */
533 /* XMM register or word memory operand */
535 /* XMM register or double word memory operand */
537 /* XMM register or quad word memory operand */
539 /* 16-byte XMM, word, double word or quad word operand. */
541 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
543 /* 32-byte YMM operand */
545 /* quad word, ymmword or zmmword memory operand. */
547 /* 32-byte YMM or 16-byte word operand */
549 /* d_mode in 32bit, q_mode in 64bit mode. */
551 /* pair of v_mode operands */
557 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
559 /* operand size depends on REX prefixes. */
561 /* registers like dq_mode, memory like w_mode, displacements like
562 v_mode without considering Intel64 ISA. */
566 /* bounds operand with operand swapped */
568 /* 4- or 6-byte pointer operand */
571 /* v_mode for indirect branch opcodes. */
573 /* v_mode for stack-related opcodes. */
575 /* non-quad operand size depends on prefixes */
577 /* 16-byte operand */
579 /* registers like dq_mode, memory like b_mode. */
581 /* registers like d_mode, memory like b_mode. */
583 /* registers like d_mode, memory like w_mode. */
585 /* registers like dq_mode, memory like d_mode. */
587 /* normal vex mode */
589 /* 128bit vex mode */
591 /* 256bit vex mode */
594 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
595 vex_vsib_d_w_dq_mode
,
596 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
598 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
599 vex_vsib_q_w_dq_mode
,
600 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
603 /* scalar, ignore vector length. */
605 /* like b_mode, ignore vector length. */
607 /* like w_mode, ignore vector length. */
609 /* like d_mode, ignore vector length. */
611 /* like d_swap_mode, ignore vector length. */
613 /* like q_mode, ignore vector length. */
615 /* like q_swap_mode, ignore vector length. */
617 /* like vex_mode, ignore vector length. */
619 /* Operand size depends on the VEX.W bit, ignore vector length. */
620 vex_scalar_w_dq_mode
,
622 /* Static rounding. */
624 /* Static rounding, 64-bit mode only. */
625 evex_rounding_64_mode
,
626 /* Supress all exceptions. */
629 /* Mask register operand. */
631 /* Mask register operand. */
699 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
701 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
702 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
703 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
704 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
705 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
706 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
707 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
708 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
709 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
710 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
711 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
712 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
713 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
714 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
715 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
716 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
844 MOD_VEX_0F12_PREFIX_0
,
846 MOD_VEX_0F16_PREFIX_0
,
849 MOD_VEX_W_0_0F41_P_0_LEN_1
,
850 MOD_VEX_W_1_0F41_P_0_LEN_1
,
851 MOD_VEX_W_0_0F41_P_2_LEN_1
,
852 MOD_VEX_W_1_0F41_P_2_LEN_1
,
853 MOD_VEX_W_0_0F42_P_0_LEN_1
,
854 MOD_VEX_W_1_0F42_P_0_LEN_1
,
855 MOD_VEX_W_0_0F42_P_2_LEN_1
,
856 MOD_VEX_W_1_0F42_P_2_LEN_1
,
857 MOD_VEX_W_0_0F44_P_0_LEN_1
,
858 MOD_VEX_W_1_0F44_P_0_LEN_1
,
859 MOD_VEX_W_0_0F44_P_2_LEN_1
,
860 MOD_VEX_W_1_0F44_P_2_LEN_1
,
861 MOD_VEX_W_0_0F45_P_0_LEN_1
,
862 MOD_VEX_W_1_0F45_P_0_LEN_1
,
863 MOD_VEX_W_0_0F45_P_2_LEN_1
,
864 MOD_VEX_W_1_0F45_P_2_LEN_1
,
865 MOD_VEX_W_0_0F46_P_0_LEN_1
,
866 MOD_VEX_W_1_0F46_P_0_LEN_1
,
867 MOD_VEX_W_0_0F46_P_2_LEN_1
,
868 MOD_VEX_W_1_0F46_P_2_LEN_1
,
869 MOD_VEX_W_0_0F47_P_0_LEN_1
,
870 MOD_VEX_W_1_0F47_P_0_LEN_1
,
871 MOD_VEX_W_0_0F47_P_2_LEN_1
,
872 MOD_VEX_W_1_0F47_P_2_LEN_1
,
873 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
874 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
875 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
876 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
877 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
878 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
879 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
891 MOD_VEX_W_0_0F91_P_0_LEN_0
,
892 MOD_VEX_W_1_0F91_P_0_LEN_0
,
893 MOD_VEX_W_0_0F91_P_2_LEN_0
,
894 MOD_VEX_W_1_0F91_P_2_LEN_0
,
895 MOD_VEX_W_0_0F92_P_0_LEN_0
,
896 MOD_VEX_W_0_0F92_P_2_LEN_0
,
897 MOD_VEX_0F92_P_3_LEN_0
,
898 MOD_VEX_W_0_0F93_P_0_LEN_0
,
899 MOD_VEX_W_0_0F93_P_2_LEN_0
,
900 MOD_VEX_0F93_P_3_LEN_0
,
901 MOD_VEX_W_0_0F98_P_0_LEN_0
,
902 MOD_VEX_W_1_0F98_P_0_LEN_0
,
903 MOD_VEX_W_0_0F98_P_2_LEN_0
,
904 MOD_VEX_W_1_0F98_P_2_LEN_0
,
905 MOD_VEX_W_0_0F99_P_0_LEN_0
,
906 MOD_VEX_W_1_0F99_P_0_LEN_0
,
907 MOD_VEX_W_0_0F99_P_2_LEN_0
,
908 MOD_VEX_W_1_0F99_P_2_LEN_0
,
911 MOD_VEX_0FD7_PREFIX_2
,
912 MOD_VEX_0FE7_PREFIX_2
,
913 MOD_VEX_0FF0_PREFIX_3
,
914 MOD_VEX_0F381A_PREFIX_2
,
915 MOD_VEX_0F382A_PREFIX_2
,
916 MOD_VEX_0F382C_PREFIX_2
,
917 MOD_VEX_0F382D_PREFIX_2
,
918 MOD_VEX_0F382E_PREFIX_2
,
919 MOD_VEX_0F382F_PREFIX_2
,
920 MOD_VEX_0F385A_PREFIX_2
,
921 MOD_VEX_0F388C_PREFIX_2
,
922 MOD_VEX_0F388E_PREFIX_2
,
923 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
924 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
925 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
926 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
927 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
928 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
929 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
930 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
932 MOD_EVEX_0F12_PREFIX_0
,
933 MOD_EVEX_0F16_PREFIX_0
,
934 MOD_EVEX_0F38C6_REG_1
,
935 MOD_EVEX_0F38C6_REG_2
,
936 MOD_EVEX_0F38C6_REG_5
,
937 MOD_EVEX_0F38C6_REG_6
,
938 MOD_EVEX_0F38C7_REG_1
,
939 MOD_EVEX_0F38C7_REG_2
,
940 MOD_EVEX_0F38C7_REG_5
,
941 MOD_EVEX_0F38C7_REG_6
954 RM_0F1E_P_1_MOD_3_REG_7
,
955 RM_0FAE_REG_6_MOD_3_P_0
,
962 PREFIX_0F01_REG_3_RM_1
,
963 PREFIX_0F01_REG_5_MOD_0
,
964 PREFIX_0F01_REG_5_MOD_3_RM_0
,
965 PREFIX_0F01_REG_5_MOD_3_RM_2
,
966 PREFIX_0F01_REG_7_MOD_3_RM_2
,
967 PREFIX_0F01_REG_7_MOD_3_RM_3
,
1009 PREFIX_0FAE_REG_0_MOD_3
,
1010 PREFIX_0FAE_REG_1_MOD_3
,
1011 PREFIX_0FAE_REG_2_MOD_3
,
1012 PREFIX_0FAE_REG_3_MOD_3
,
1013 PREFIX_0FAE_REG_4_MOD_0
,
1014 PREFIX_0FAE_REG_4_MOD_3
,
1015 PREFIX_0FAE_REG_5_MOD_0
,
1016 PREFIX_0FAE_REG_5_MOD_3
,
1017 PREFIX_0FAE_REG_6_MOD_0
,
1018 PREFIX_0FAE_REG_6_MOD_3
,
1019 PREFIX_0FAE_REG_7_MOD_0
,
1025 PREFIX_0FC7_REG_6_MOD_0
,
1026 PREFIX_0FC7_REG_6_MOD_3
,
1027 PREFIX_0FC7_REG_7_MOD_3
,
1157 PREFIX_VEX_0F71_REG_2
,
1158 PREFIX_VEX_0F71_REG_4
,
1159 PREFIX_VEX_0F71_REG_6
,
1160 PREFIX_VEX_0F72_REG_2
,
1161 PREFIX_VEX_0F72_REG_4
,
1162 PREFIX_VEX_0F72_REG_6
,
1163 PREFIX_VEX_0F73_REG_2
,
1164 PREFIX_VEX_0F73_REG_3
,
1165 PREFIX_VEX_0F73_REG_6
,
1166 PREFIX_VEX_0F73_REG_7
,
1339 PREFIX_VEX_0F38F3_REG_1
,
1340 PREFIX_VEX_0F38F3_REG_2
,
1341 PREFIX_VEX_0F38F3_REG_3
,
1460 PREFIX_EVEX_0F71_REG_2
,
1461 PREFIX_EVEX_0F71_REG_4
,
1462 PREFIX_EVEX_0F71_REG_6
,
1463 PREFIX_EVEX_0F72_REG_0
,
1464 PREFIX_EVEX_0F72_REG_1
,
1465 PREFIX_EVEX_0F72_REG_2
,
1466 PREFIX_EVEX_0F72_REG_4
,
1467 PREFIX_EVEX_0F72_REG_6
,
1468 PREFIX_EVEX_0F73_REG_2
,
1469 PREFIX_EVEX_0F73_REG_3
,
1470 PREFIX_EVEX_0F73_REG_6
,
1471 PREFIX_EVEX_0F73_REG_7
,
1668 PREFIX_EVEX_0F38C6_REG_1
,
1669 PREFIX_EVEX_0F38C6_REG_2
,
1670 PREFIX_EVEX_0F38C6_REG_5
,
1671 PREFIX_EVEX_0F38C6_REG_6
,
1672 PREFIX_EVEX_0F38C7_REG_1
,
1673 PREFIX_EVEX_0F38C7_REG_2
,
1674 PREFIX_EVEX_0F38C7_REG_5
,
1675 PREFIX_EVEX_0F38C7_REG_6
,
1779 THREE_BYTE_0F38
= 0,
1806 VEX_LEN_0F12_P_0_M_0
= 0,
1807 VEX_LEN_0F12_P_0_M_1
,
1810 VEX_LEN_0F16_P_0_M_0
,
1811 VEX_LEN_0F16_P_0_M_1
,
1848 VEX_LEN_0FAE_R_2_M_0
,
1849 VEX_LEN_0FAE_R_3_M_0
,
1856 VEX_LEN_0F381A_P_2_M_0
,
1859 VEX_LEN_0F385A_P_2_M_0
,
1862 VEX_LEN_0F38F3_R_1_P_0
,
1863 VEX_LEN_0F38F3_R_2_P_0
,
1864 VEX_LEN_0F38F3_R_3_P_0
,
1907 VEX_LEN_0FXOP_08_CC
,
1908 VEX_LEN_0FXOP_08_CD
,
1909 VEX_LEN_0FXOP_08_CE
,
1910 VEX_LEN_0FXOP_08_CF
,
1911 VEX_LEN_0FXOP_08_EC
,
1912 VEX_LEN_0FXOP_08_ED
,
1913 VEX_LEN_0FXOP_08_EE
,
1914 VEX_LEN_0FXOP_08_EF
,
1915 VEX_LEN_0FXOP_09_80
,
1921 EVEX_LEN_0F6E_P_2
= 0,
1925 EVEX_LEN_0F3819_P_2_W_0
,
1926 EVEX_LEN_0F3819_P_2_W_1
,
1927 EVEX_LEN_0F381A_P_2_W_0
,
1928 EVEX_LEN_0F381A_P_2_W_1
,
1929 EVEX_LEN_0F381B_P_2_W_0
,
1930 EVEX_LEN_0F381B_P_2_W_1
,
1931 EVEX_LEN_0F385A_P_2_W_0
,
1932 EVEX_LEN_0F385A_P_2_W_1
,
1933 EVEX_LEN_0F385B_P_2_W_0
,
1934 EVEX_LEN_0F385B_P_2_W_1
,
1935 EVEX_LEN_0F38C6_REG_1_PREFIX_2
,
1936 EVEX_LEN_0F38C6_REG_2_PREFIX_2
,
1937 EVEX_LEN_0F38C6_REG_5_PREFIX_2
,
1938 EVEX_LEN_0F38C6_REG_6_PREFIX_2
,
1939 EVEX_LEN_0F38C7_R_1_P_2_W_0
,
1940 EVEX_LEN_0F38C7_R_1_P_2_W_1
,
1941 EVEX_LEN_0F38C7_R_2_P_2_W_0
,
1942 EVEX_LEN_0F38C7_R_2_P_2_W_1
,
1943 EVEX_LEN_0F38C7_R_5_P_2_W_0
,
1944 EVEX_LEN_0F38C7_R_5_P_2_W_1
,
1945 EVEX_LEN_0F38C7_R_6_P_2_W_0
,
1946 EVEX_LEN_0F38C7_R_6_P_2_W_1
,
1947 EVEX_LEN_0F3A18_P_2_W_0
,
1948 EVEX_LEN_0F3A18_P_2_W_1
,
1949 EVEX_LEN_0F3A19_P_2_W_0
,
1950 EVEX_LEN_0F3A19_P_2_W_1
,
1951 EVEX_LEN_0F3A1A_P_2_W_0
,
1952 EVEX_LEN_0F3A1A_P_2_W_1
,
1953 EVEX_LEN_0F3A1B_P_2_W_0
,
1954 EVEX_LEN_0F3A1B_P_2_W_1
,
1955 EVEX_LEN_0F3A23_P_2_W_0
,
1956 EVEX_LEN_0F3A23_P_2_W_1
,
1957 EVEX_LEN_0F3A38_P_2_W_0
,
1958 EVEX_LEN_0F3A38_P_2_W_1
,
1959 EVEX_LEN_0F3A39_P_2_W_0
,
1960 EVEX_LEN_0F3A39_P_2_W_1
,
1961 EVEX_LEN_0F3A3A_P_2_W_0
,
1962 EVEX_LEN_0F3A3A_P_2_W_1
,
1963 EVEX_LEN_0F3A3B_P_2_W_0
,
1964 EVEX_LEN_0F3A3B_P_2_W_1
,
1965 EVEX_LEN_0F3A43_P_2_W_0
,
1966 EVEX_LEN_0F3A43_P_2_W_1
1971 VEX_W_0F41_P_0_LEN_1
= 0,
1972 VEX_W_0F41_P_2_LEN_1
,
1973 VEX_W_0F42_P_0_LEN_1
,
1974 VEX_W_0F42_P_2_LEN_1
,
1975 VEX_W_0F44_P_0_LEN_0
,
1976 VEX_W_0F44_P_2_LEN_0
,
1977 VEX_W_0F45_P_0_LEN_1
,
1978 VEX_W_0F45_P_2_LEN_1
,
1979 VEX_W_0F46_P_0_LEN_1
,
1980 VEX_W_0F46_P_2_LEN_1
,
1981 VEX_W_0F47_P_0_LEN_1
,
1982 VEX_W_0F47_P_2_LEN_1
,
1983 VEX_W_0F4A_P_0_LEN_1
,
1984 VEX_W_0F4A_P_2_LEN_1
,
1985 VEX_W_0F4B_P_0_LEN_1
,
1986 VEX_W_0F4B_P_2_LEN_1
,
1987 VEX_W_0F90_P_0_LEN_0
,
1988 VEX_W_0F90_P_2_LEN_0
,
1989 VEX_W_0F91_P_0_LEN_0
,
1990 VEX_W_0F91_P_2_LEN_0
,
1991 VEX_W_0F92_P_0_LEN_0
,
1992 VEX_W_0F92_P_2_LEN_0
,
1993 VEX_W_0F93_P_0_LEN_0
,
1994 VEX_W_0F93_P_2_LEN_0
,
1995 VEX_W_0F98_P_0_LEN_0
,
1996 VEX_W_0F98_P_2_LEN_0
,
1997 VEX_W_0F99_P_0_LEN_0
,
1998 VEX_W_0F99_P_2_LEN_0
,
2006 VEX_W_0F381A_P_2_M_0
,
2007 VEX_W_0F382C_P_2_M_0
,
2008 VEX_W_0F382D_P_2_M_0
,
2009 VEX_W_0F382E_P_2_M_0
,
2010 VEX_W_0F382F_P_2_M_0
,
2015 VEX_W_0F385A_P_2_M_0
,
2027 VEX_W_0F3A30_P_2_LEN_0
,
2028 VEX_W_0F3A31_P_2_LEN_0
,
2029 VEX_W_0F3A32_P_2_LEN_0
,
2030 VEX_W_0F3A33_P_2_LEN_0
,
2050 EVEX_W_0F12_P_0_M_0
,
2051 EVEX_W_0F12_P_0_M_1
,
2061 EVEX_W_0F16_P_0_M_0
,
2062 EVEX_W_0F16_P_0_M_1
,
2131 EVEX_W_0F72_R_2_P_2
,
2132 EVEX_W_0F72_R_6_P_2
,
2133 EVEX_W_0F73_R_2_P_2
,
2134 EVEX_W_0F73_R_6_P_2
,
2244 EVEX_W_0F38C7_R_1_P_2
,
2245 EVEX_W_0F38C7_R_2_P_2
,
2246 EVEX_W_0F38C7_R_5_P_2
,
2247 EVEX_W_0F38C7_R_6_P_2
,
2286 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2295 unsigned int prefix_requirement
;
2298 /* Upper case letters in the instruction names here are macros.
2299 'A' => print 'b' if no register operands or suffix_always is true
2300 'B' => print 'b' if suffix_always is true
2301 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2303 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2304 suffix_always is true
2305 'E' => print 'e' if 32-bit form of jcxz
2306 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2307 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2308 'H' => print ",pt" or ",pn" branch hint
2309 'I' => honor following macro letter even in Intel mode (implemented only
2310 for some of the macro letters)
2312 'K' => print 'd' or 'q' if rex prefix is present.
2313 'L' => print 'l' if suffix_always is true
2314 'M' => print 'r' if intel_mnemonic is false.
2315 'N' => print 'n' if instruction has no wait "prefix"
2316 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2317 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2318 or suffix_always is true. print 'q' if rex prefix is present.
2319 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2321 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2322 'S' => print 'w', 'l' or 'q' if suffix_always is true
2323 'T' => print 'q' in 64bit mode if instruction has no operand size
2324 prefix and behave as 'P' otherwise
2325 'U' => print 'q' in 64bit mode if instruction has no operand size
2326 prefix and behave as 'Q' otherwise
2327 'V' => print 'q' in 64bit mode if instruction has no operand size
2328 prefix and behave as 'S' otherwise
2329 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2330 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2332 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2333 '!' => change condition from true to false or from false to true.
2334 '%' => add 1 upper case letter to the macro.
2335 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
2336 prefix or suffix_always is true (lcall/ljmp).
2337 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2338 on operand size prefix.
2339 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2340 has no operand size prefix for AMD64 ISA, behave as 'P'
2343 2 upper case letter macros:
2344 "XY" => print 'x' or 'y' if suffix_always is true or no register
2345 operands and no broadcast.
2346 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2347 register operands and no broadcast.
2348 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2349 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2350 or suffix_always is true
2351 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2352 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2353 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2354 "LW" => print 'd', 'q' depending on the VEX.W bit
2355 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2356 an operand size prefix, or suffix_always is true. print
2357 'q' if rex prefix is present.
2359 Many of the above letters print nothing in Intel mode. See "putop"
2362 Braces '{' and '}', and vertical bars '|', indicate alternative
2363 mnemonic strings for AT&T and Intel. */
2365 static const struct dis386 dis386
[] = {
2367 { "addB", { Ebh1
, Gb
}, 0 },
2368 { "addS", { Evh1
, Gv
}, 0 },
2369 { "addB", { Gb
, EbS
}, 0 },
2370 { "addS", { Gv
, EvS
}, 0 },
2371 { "addB", { AL
, Ib
}, 0 },
2372 { "addS", { eAX
, Iv
}, 0 },
2373 { X86_64_TABLE (X86_64_06
) },
2374 { X86_64_TABLE (X86_64_07
) },
2376 { "orB", { Ebh1
, Gb
}, 0 },
2377 { "orS", { Evh1
, Gv
}, 0 },
2378 { "orB", { Gb
, EbS
}, 0 },
2379 { "orS", { Gv
, EvS
}, 0 },
2380 { "orB", { AL
, Ib
}, 0 },
2381 { "orS", { eAX
, Iv
}, 0 },
2382 { X86_64_TABLE (X86_64_0D
) },
2383 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2385 { "adcB", { Ebh1
, Gb
}, 0 },
2386 { "adcS", { Evh1
, Gv
}, 0 },
2387 { "adcB", { Gb
, EbS
}, 0 },
2388 { "adcS", { Gv
, EvS
}, 0 },
2389 { "adcB", { AL
, Ib
}, 0 },
2390 { "adcS", { eAX
, Iv
}, 0 },
2391 { X86_64_TABLE (X86_64_16
) },
2392 { X86_64_TABLE (X86_64_17
) },
2394 { "sbbB", { Ebh1
, Gb
}, 0 },
2395 { "sbbS", { Evh1
, Gv
}, 0 },
2396 { "sbbB", { Gb
, EbS
}, 0 },
2397 { "sbbS", { Gv
, EvS
}, 0 },
2398 { "sbbB", { AL
, Ib
}, 0 },
2399 { "sbbS", { eAX
, Iv
}, 0 },
2400 { X86_64_TABLE (X86_64_1E
) },
2401 { X86_64_TABLE (X86_64_1F
) },
2403 { "andB", { Ebh1
, Gb
}, 0 },
2404 { "andS", { Evh1
, Gv
}, 0 },
2405 { "andB", { Gb
, EbS
}, 0 },
2406 { "andS", { Gv
, EvS
}, 0 },
2407 { "andB", { AL
, Ib
}, 0 },
2408 { "andS", { eAX
, Iv
}, 0 },
2409 { Bad_Opcode
}, /* SEG ES prefix */
2410 { X86_64_TABLE (X86_64_27
) },
2412 { "subB", { Ebh1
, Gb
}, 0 },
2413 { "subS", { Evh1
, Gv
}, 0 },
2414 { "subB", { Gb
, EbS
}, 0 },
2415 { "subS", { Gv
, EvS
}, 0 },
2416 { "subB", { AL
, Ib
}, 0 },
2417 { "subS", { eAX
, Iv
}, 0 },
2418 { Bad_Opcode
}, /* SEG CS prefix */
2419 { X86_64_TABLE (X86_64_2F
) },
2421 { "xorB", { Ebh1
, Gb
}, 0 },
2422 { "xorS", { Evh1
, Gv
}, 0 },
2423 { "xorB", { Gb
, EbS
}, 0 },
2424 { "xorS", { Gv
, EvS
}, 0 },
2425 { "xorB", { AL
, Ib
}, 0 },
2426 { "xorS", { eAX
, Iv
}, 0 },
2427 { Bad_Opcode
}, /* SEG SS prefix */
2428 { X86_64_TABLE (X86_64_37
) },
2430 { "cmpB", { Eb
, Gb
}, 0 },
2431 { "cmpS", { Ev
, Gv
}, 0 },
2432 { "cmpB", { Gb
, EbS
}, 0 },
2433 { "cmpS", { Gv
, EvS
}, 0 },
2434 { "cmpB", { AL
, Ib
}, 0 },
2435 { "cmpS", { eAX
, Iv
}, 0 },
2436 { Bad_Opcode
}, /* SEG DS prefix */
2437 { X86_64_TABLE (X86_64_3F
) },
2439 { "inc{S|}", { RMeAX
}, 0 },
2440 { "inc{S|}", { RMeCX
}, 0 },
2441 { "inc{S|}", { RMeDX
}, 0 },
2442 { "inc{S|}", { RMeBX
}, 0 },
2443 { "inc{S|}", { RMeSP
}, 0 },
2444 { "inc{S|}", { RMeBP
}, 0 },
2445 { "inc{S|}", { RMeSI
}, 0 },
2446 { "inc{S|}", { RMeDI
}, 0 },
2448 { "dec{S|}", { RMeAX
}, 0 },
2449 { "dec{S|}", { RMeCX
}, 0 },
2450 { "dec{S|}", { RMeDX
}, 0 },
2451 { "dec{S|}", { RMeBX
}, 0 },
2452 { "dec{S|}", { RMeSP
}, 0 },
2453 { "dec{S|}", { RMeBP
}, 0 },
2454 { "dec{S|}", { RMeSI
}, 0 },
2455 { "dec{S|}", { RMeDI
}, 0 },
2457 { "pushV", { RMrAX
}, 0 },
2458 { "pushV", { RMrCX
}, 0 },
2459 { "pushV", { RMrDX
}, 0 },
2460 { "pushV", { RMrBX
}, 0 },
2461 { "pushV", { RMrSP
}, 0 },
2462 { "pushV", { RMrBP
}, 0 },
2463 { "pushV", { RMrSI
}, 0 },
2464 { "pushV", { RMrDI
}, 0 },
2466 { "popV", { RMrAX
}, 0 },
2467 { "popV", { RMrCX
}, 0 },
2468 { "popV", { RMrDX
}, 0 },
2469 { "popV", { RMrBX
}, 0 },
2470 { "popV", { RMrSP
}, 0 },
2471 { "popV", { RMrBP
}, 0 },
2472 { "popV", { RMrSI
}, 0 },
2473 { "popV", { RMrDI
}, 0 },
2475 { X86_64_TABLE (X86_64_60
) },
2476 { X86_64_TABLE (X86_64_61
) },
2477 { X86_64_TABLE (X86_64_62
) },
2478 { X86_64_TABLE (X86_64_63
) },
2479 { Bad_Opcode
}, /* seg fs */
2480 { Bad_Opcode
}, /* seg gs */
2481 { Bad_Opcode
}, /* op size prefix */
2482 { Bad_Opcode
}, /* adr size prefix */
2484 { "pushT", { sIv
}, 0 },
2485 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2486 { "pushT", { sIbT
}, 0 },
2487 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2488 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2489 { X86_64_TABLE (X86_64_6D
) },
2490 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2491 { X86_64_TABLE (X86_64_6F
) },
2493 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2494 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2495 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2496 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2497 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2498 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2499 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2500 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2502 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2503 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2504 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2505 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2506 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2507 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2508 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2509 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2511 { REG_TABLE (REG_80
) },
2512 { REG_TABLE (REG_81
) },
2513 { X86_64_TABLE (X86_64_82
) },
2514 { REG_TABLE (REG_83
) },
2515 { "testB", { Eb
, Gb
}, 0 },
2516 { "testS", { Ev
, Gv
}, 0 },
2517 { "xchgB", { Ebh2
, Gb
}, 0 },
2518 { "xchgS", { Evh2
, Gv
}, 0 },
2520 { "movB", { Ebh3
, Gb
}, 0 },
2521 { "movS", { Evh3
, Gv
}, 0 },
2522 { "movB", { Gb
, EbS
}, 0 },
2523 { "movS", { Gv
, EvS
}, 0 },
2524 { "movD", { Sv
, Sw
}, 0 },
2525 { MOD_TABLE (MOD_8D
) },
2526 { "movD", { Sw
, Sv
}, 0 },
2527 { REG_TABLE (REG_8F
) },
2529 { PREFIX_TABLE (PREFIX_90
) },
2530 { "xchgS", { RMeCX
, eAX
}, 0 },
2531 { "xchgS", { RMeDX
, eAX
}, 0 },
2532 { "xchgS", { RMeBX
, eAX
}, 0 },
2533 { "xchgS", { RMeSP
, eAX
}, 0 },
2534 { "xchgS", { RMeBP
, eAX
}, 0 },
2535 { "xchgS", { RMeSI
, eAX
}, 0 },
2536 { "xchgS", { RMeDI
, eAX
}, 0 },
2538 { "cW{t|}R", { XX
}, 0 },
2539 { "cR{t|}O", { XX
}, 0 },
2540 { X86_64_TABLE (X86_64_9A
) },
2541 { Bad_Opcode
}, /* fwait */
2542 { "pushfT", { XX
}, 0 },
2543 { "popfT", { XX
}, 0 },
2544 { "sahf", { XX
}, 0 },
2545 { "lahf", { XX
}, 0 },
2547 { "mov%LB", { AL
, Ob
}, 0 },
2548 { "mov%LS", { eAX
, Ov
}, 0 },
2549 { "mov%LB", { Ob
, AL
}, 0 },
2550 { "mov%LS", { Ov
, eAX
}, 0 },
2551 { "movs{b|}", { Ybr
, Xb
}, 0 },
2552 { "movs{R|}", { Yvr
, Xv
}, 0 },
2553 { "cmps{b|}", { Xb
, Yb
}, 0 },
2554 { "cmps{R|}", { Xv
, Yv
}, 0 },
2556 { "testB", { AL
, Ib
}, 0 },
2557 { "testS", { eAX
, Iv
}, 0 },
2558 { "stosB", { Ybr
, AL
}, 0 },
2559 { "stosS", { Yvr
, eAX
}, 0 },
2560 { "lodsB", { ALr
, Xb
}, 0 },
2561 { "lodsS", { eAXr
, Xv
}, 0 },
2562 { "scasB", { AL
, Yb
}, 0 },
2563 { "scasS", { eAX
, Yv
}, 0 },
2565 { "movB", { RMAL
, Ib
}, 0 },
2566 { "movB", { RMCL
, Ib
}, 0 },
2567 { "movB", { RMDL
, Ib
}, 0 },
2568 { "movB", { RMBL
, Ib
}, 0 },
2569 { "movB", { RMAH
, Ib
}, 0 },
2570 { "movB", { RMCH
, Ib
}, 0 },
2571 { "movB", { RMDH
, Ib
}, 0 },
2572 { "movB", { RMBH
, Ib
}, 0 },
2574 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2575 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2576 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2577 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2578 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2579 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2580 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2581 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2583 { REG_TABLE (REG_C0
) },
2584 { REG_TABLE (REG_C1
) },
2585 { X86_64_TABLE (X86_64_C2
) },
2586 { X86_64_TABLE (X86_64_C3
) },
2587 { X86_64_TABLE (X86_64_C4
) },
2588 { X86_64_TABLE (X86_64_C5
) },
2589 { REG_TABLE (REG_C6
) },
2590 { REG_TABLE (REG_C7
) },
2592 { "enterT", { Iw
, Ib
}, 0 },
2593 { "leaveT", { XX
}, 0 },
2594 { "Jret{|f}P", { Iw
}, 0 },
2595 { "Jret{|f}P", { XX
}, 0 },
2596 { "int3", { XX
}, 0 },
2597 { "int", { Ib
}, 0 },
2598 { X86_64_TABLE (X86_64_CE
) },
2599 { "iret%LP", { XX
}, 0 },
2601 { REG_TABLE (REG_D0
) },
2602 { REG_TABLE (REG_D1
) },
2603 { REG_TABLE (REG_D2
) },
2604 { REG_TABLE (REG_D3
) },
2605 { X86_64_TABLE (X86_64_D4
) },
2606 { X86_64_TABLE (X86_64_D5
) },
2608 { "xlat", { DSBX
}, 0 },
2619 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2620 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2621 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2622 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2623 { "inB", { AL
, Ib
}, 0 },
2624 { "inG", { zAX
, Ib
}, 0 },
2625 { "outB", { Ib
, AL
}, 0 },
2626 { "outG", { Ib
, zAX
}, 0 },
2628 { X86_64_TABLE (X86_64_E8
) },
2629 { X86_64_TABLE (X86_64_E9
) },
2630 { X86_64_TABLE (X86_64_EA
) },
2631 { "jmp", { Jb
, BND
}, 0 },
2632 { "inB", { AL
, indirDX
}, 0 },
2633 { "inG", { zAX
, indirDX
}, 0 },
2634 { "outB", { indirDX
, AL
}, 0 },
2635 { "outG", { indirDX
, zAX
}, 0 },
2637 { Bad_Opcode
}, /* lock prefix */
2638 { "icebp", { XX
}, 0 },
2639 { Bad_Opcode
}, /* repne */
2640 { Bad_Opcode
}, /* repz */
2641 { "hlt", { XX
}, 0 },
2642 { "cmc", { XX
}, 0 },
2643 { REG_TABLE (REG_F6
) },
2644 { REG_TABLE (REG_F7
) },
2646 { "clc", { XX
}, 0 },
2647 { "stc", { XX
}, 0 },
2648 { "cli", { XX
}, 0 },
2649 { "sti", { XX
}, 0 },
2650 { "cld", { XX
}, 0 },
2651 { "std", { XX
}, 0 },
2652 { REG_TABLE (REG_FE
) },
2653 { REG_TABLE (REG_FF
) },
2656 static const struct dis386 dis386_twobyte
[] = {
2658 { REG_TABLE (REG_0F00
) },
2659 { REG_TABLE (REG_0F01
) },
2660 { "larS", { Gv
, Ew
}, 0 },
2661 { "lslS", { Gv
, Ew
}, 0 },
2663 { "syscall", { XX
}, 0 },
2664 { "clts", { XX
}, 0 },
2665 { "sysret%LP", { XX
}, 0 },
2667 { "invd", { XX
}, 0 },
2668 { PREFIX_TABLE (PREFIX_0F09
) },
2670 { "ud2", { XX
}, 0 },
2672 { REG_TABLE (REG_0F0D
) },
2673 { "femms", { XX
}, 0 },
2674 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2676 { PREFIX_TABLE (PREFIX_0F10
) },
2677 { PREFIX_TABLE (PREFIX_0F11
) },
2678 { PREFIX_TABLE (PREFIX_0F12
) },
2679 { MOD_TABLE (MOD_0F13
) },
2680 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2681 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2682 { PREFIX_TABLE (PREFIX_0F16
) },
2683 { MOD_TABLE (MOD_0F17
) },
2685 { REG_TABLE (REG_0F18
) },
2686 { "nopQ", { Ev
}, 0 },
2687 { PREFIX_TABLE (PREFIX_0F1A
) },
2688 { PREFIX_TABLE (PREFIX_0F1B
) },
2689 { PREFIX_TABLE (PREFIX_0F1C
) },
2690 { "nopQ", { Ev
}, 0 },
2691 { PREFIX_TABLE (PREFIX_0F1E
) },
2692 { "nopQ", { Ev
}, 0 },
2694 { "movZ", { Rm
, Cm
}, 0 },
2695 { "movZ", { Rm
, Dm
}, 0 },
2696 { "movZ", { Cm
, Rm
}, 0 },
2697 { "movZ", { Dm
, Rm
}, 0 },
2698 { MOD_TABLE (MOD_0F24
) },
2700 { MOD_TABLE (MOD_0F26
) },
2703 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2704 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2705 { PREFIX_TABLE (PREFIX_0F2A
) },
2706 { PREFIX_TABLE (PREFIX_0F2B
) },
2707 { PREFIX_TABLE (PREFIX_0F2C
) },
2708 { PREFIX_TABLE (PREFIX_0F2D
) },
2709 { PREFIX_TABLE (PREFIX_0F2E
) },
2710 { PREFIX_TABLE (PREFIX_0F2F
) },
2712 { "wrmsr", { XX
}, 0 },
2713 { "rdtsc", { XX
}, 0 },
2714 { "rdmsr", { XX
}, 0 },
2715 { "rdpmc", { XX
}, 0 },
2716 { "sysenter", { SEP
}, 0 },
2717 { "sysexit", { SEP
}, 0 },
2719 { "getsec", { XX
}, 0 },
2721 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2723 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2730 { "cmovoS", { Gv
, Ev
}, 0 },
2731 { "cmovnoS", { Gv
, Ev
}, 0 },
2732 { "cmovbS", { Gv
, Ev
}, 0 },
2733 { "cmovaeS", { Gv
, Ev
}, 0 },
2734 { "cmoveS", { Gv
, Ev
}, 0 },
2735 { "cmovneS", { Gv
, Ev
}, 0 },
2736 { "cmovbeS", { Gv
, Ev
}, 0 },
2737 { "cmovaS", { Gv
, Ev
}, 0 },
2739 { "cmovsS", { Gv
, Ev
}, 0 },
2740 { "cmovnsS", { Gv
, Ev
}, 0 },
2741 { "cmovpS", { Gv
, Ev
}, 0 },
2742 { "cmovnpS", { Gv
, Ev
}, 0 },
2743 { "cmovlS", { Gv
, Ev
}, 0 },
2744 { "cmovgeS", { Gv
, Ev
}, 0 },
2745 { "cmovleS", { Gv
, Ev
}, 0 },
2746 { "cmovgS", { Gv
, Ev
}, 0 },
2748 { MOD_TABLE (MOD_0F51
) },
2749 { PREFIX_TABLE (PREFIX_0F51
) },
2750 { PREFIX_TABLE (PREFIX_0F52
) },
2751 { PREFIX_TABLE (PREFIX_0F53
) },
2752 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2753 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2754 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2755 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2757 { PREFIX_TABLE (PREFIX_0F58
) },
2758 { PREFIX_TABLE (PREFIX_0F59
) },
2759 { PREFIX_TABLE (PREFIX_0F5A
) },
2760 { PREFIX_TABLE (PREFIX_0F5B
) },
2761 { PREFIX_TABLE (PREFIX_0F5C
) },
2762 { PREFIX_TABLE (PREFIX_0F5D
) },
2763 { PREFIX_TABLE (PREFIX_0F5E
) },
2764 { PREFIX_TABLE (PREFIX_0F5F
) },
2766 { PREFIX_TABLE (PREFIX_0F60
) },
2767 { PREFIX_TABLE (PREFIX_0F61
) },
2768 { PREFIX_TABLE (PREFIX_0F62
) },
2769 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2770 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2771 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2772 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2773 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2775 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2776 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2777 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2778 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2779 { PREFIX_TABLE (PREFIX_0F6C
) },
2780 { PREFIX_TABLE (PREFIX_0F6D
) },
2781 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2782 { PREFIX_TABLE (PREFIX_0F6F
) },
2784 { PREFIX_TABLE (PREFIX_0F70
) },
2785 { REG_TABLE (REG_0F71
) },
2786 { REG_TABLE (REG_0F72
) },
2787 { REG_TABLE (REG_0F73
) },
2788 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2789 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2790 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2791 { "emms", { XX
}, PREFIX_OPCODE
},
2793 { PREFIX_TABLE (PREFIX_0F78
) },
2794 { PREFIX_TABLE (PREFIX_0F79
) },
2797 { PREFIX_TABLE (PREFIX_0F7C
) },
2798 { PREFIX_TABLE (PREFIX_0F7D
) },
2799 { PREFIX_TABLE (PREFIX_0F7E
) },
2800 { PREFIX_TABLE (PREFIX_0F7F
) },
2802 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2803 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2804 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2805 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2806 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2807 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2808 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2809 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2811 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2812 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2813 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2814 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2815 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2816 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2817 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2818 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2820 { "seto", { Eb
}, 0 },
2821 { "setno", { Eb
}, 0 },
2822 { "setb", { Eb
}, 0 },
2823 { "setae", { Eb
}, 0 },
2824 { "sete", { Eb
}, 0 },
2825 { "setne", { Eb
}, 0 },
2826 { "setbe", { Eb
}, 0 },
2827 { "seta", { Eb
}, 0 },
2829 { "sets", { Eb
}, 0 },
2830 { "setns", { Eb
}, 0 },
2831 { "setp", { Eb
}, 0 },
2832 { "setnp", { Eb
}, 0 },
2833 { "setl", { Eb
}, 0 },
2834 { "setge", { Eb
}, 0 },
2835 { "setle", { Eb
}, 0 },
2836 { "setg", { Eb
}, 0 },
2838 { "pushT", { fs
}, 0 },
2839 { "popT", { fs
}, 0 },
2840 { "cpuid", { XX
}, 0 },
2841 { "btS", { Ev
, Gv
}, 0 },
2842 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2843 { "shldS", { Ev
, Gv
, CL
}, 0 },
2844 { REG_TABLE (REG_0FA6
) },
2845 { REG_TABLE (REG_0FA7
) },
2847 { "pushT", { gs
}, 0 },
2848 { "popT", { gs
}, 0 },
2849 { "rsm", { XX
}, 0 },
2850 { "btsS", { Evh1
, Gv
}, 0 },
2851 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2852 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2853 { REG_TABLE (REG_0FAE
) },
2854 { "imulS", { Gv
, Ev
}, 0 },
2856 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2857 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2858 { MOD_TABLE (MOD_0FB2
) },
2859 { "btrS", { Evh1
, Gv
}, 0 },
2860 { MOD_TABLE (MOD_0FB4
) },
2861 { MOD_TABLE (MOD_0FB5
) },
2862 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2863 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2865 { PREFIX_TABLE (PREFIX_0FB8
) },
2866 { "ud1S", { Gv
, Ev
}, 0 },
2867 { REG_TABLE (REG_0FBA
) },
2868 { "btcS", { Evh1
, Gv
}, 0 },
2869 { PREFIX_TABLE (PREFIX_0FBC
) },
2870 { PREFIX_TABLE (PREFIX_0FBD
) },
2871 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2872 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2874 { "xaddB", { Ebh1
, Gb
}, 0 },
2875 { "xaddS", { Evh1
, Gv
}, 0 },
2876 { PREFIX_TABLE (PREFIX_0FC2
) },
2877 { MOD_TABLE (MOD_0FC3
) },
2878 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
2879 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
2880 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2881 { REG_TABLE (REG_0FC7
) },
2883 { "bswap", { RMeAX
}, 0 },
2884 { "bswap", { RMeCX
}, 0 },
2885 { "bswap", { RMeDX
}, 0 },
2886 { "bswap", { RMeBX
}, 0 },
2887 { "bswap", { RMeSP
}, 0 },
2888 { "bswap", { RMeBP
}, 0 },
2889 { "bswap", { RMeSI
}, 0 },
2890 { "bswap", { RMeDI
}, 0 },
2892 { PREFIX_TABLE (PREFIX_0FD0
) },
2893 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2894 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2895 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2896 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2897 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2898 { PREFIX_TABLE (PREFIX_0FD6
) },
2899 { MOD_TABLE (MOD_0FD7
) },
2901 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2902 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2903 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2904 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2905 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2906 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2907 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2908 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2910 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2911 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2912 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2913 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2914 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2915 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2916 { PREFIX_TABLE (PREFIX_0FE6
) },
2917 { PREFIX_TABLE (PREFIX_0FE7
) },
2919 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
2920 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
2921 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
2922 { "por", { MX
, EM
}, PREFIX_OPCODE
},
2923 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
2924 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
2925 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
2926 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
2928 { PREFIX_TABLE (PREFIX_0FF0
) },
2929 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
2930 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
2931 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
2932 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
2933 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
2934 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
2935 { PREFIX_TABLE (PREFIX_0FF7
) },
2937 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
2938 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
2939 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
2940 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
2941 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
2942 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
2943 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
2944 { "ud0S", { Gv
, Ev
}, 0 },
2947 static const unsigned char onebyte_has_modrm
[256] = {
2948 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2949 /* ------------------------------- */
2950 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2951 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2952 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2953 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2954 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2955 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2956 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2957 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2958 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2959 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2960 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2961 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2962 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2963 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2964 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2965 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2966 /* ------------------------------- */
2967 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2970 static const unsigned char twobyte_has_modrm
[256] = {
2971 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2972 /* ------------------------------- */
2973 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2974 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2975 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2976 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2977 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2978 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2979 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2980 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2981 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2982 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2983 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2984 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2985 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2986 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2987 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2988 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2989 /* ------------------------------- */
2990 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2993 static char obuf
[100];
2995 static char *mnemonicendp
;
2996 static char scratchbuf
[100];
2997 static unsigned char *start_codep
;
2998 static unsigned char *insn_codep
;
2999 static unsigned char *codep
;
3000 static unsigned char *end_codep
;
3001 static int last_lock_prefix
;
3002 static int last_repz_prefix
;
3003 static int last_repnz_prefix
;
3004 static int last_data_prefix
;
3005 static int last_addr_prefix
;
3006 static int last_rex_prefix
;
3007 static int last_seg_prefix
;
3008 static int fwait_prefix
;
3009 /* The active segment register prefix. */
3010 static int active_seg_prefix
;
3011 #define MAX_CODE_LENGTH 15
3012 /* We can up to 14 prefixes since the maximum instruction length is
3014 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
3015 static disassemble_info
*the_info
;
3023 static unsigned char need_modrm
;
3033 int register_specifier
;
3040 int mask_register_specifier
;
3046 static unsigned char need_vex
;
3047 static unsigned char need_vex_reg
;
3048 static unsigned char vex_w_done
;
3056 /* If we are accessing mod/rm/reg without need_modrm set, then the
3057 values are stale. Hitting this abort likely indicates that you
3058 need to update onebyte_has_modrm or twobyte_has_modrm. */
3059 #define MODRM_CHECK if (!need_modrm) abort ()
3061 static const char **names64
;
3062 static const char **names32
;
3063 static const char **names16
;
3064 static const char **names8
;
3065 static const char **names8rex
;
3066 static const char **names_seg
;
3067 static const char *index64
;
3068 static const char *index32
;
3069 static const char **index16
;
3070 static const char **names_bnd
;
3072 static const char *intel_names64
[] = {
3073 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3074 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3076 static const char *intel_names32
[] = {
3077 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3078 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3080 static const char *intel_names16
[] = {
3081 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3082 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3084 static const char *intel_names8
[] = {
3085 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3087 static const char *intel_names8rex
[] = {
3088 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3089 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3091 static const char *intel_names_seg
[] = {
3092 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3094 static const char *intel_index64
= "riz";
3095 static const char *intel_index32
= "eiz";
3096 static const char *intel_index16
[] = {
3097 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3100 static const char *att_names64
[] = {
3101 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3102 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3104 static const char *att_names32
[] = {
3105 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3106 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3108 static const char *att_names16
[] = {
3109 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3110 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3112 static const char *att_names8
[] = {
3113 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3115 static const char *att_names8rex
[] = {
3116 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3117 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3119 static const char *att_names_seg
[] = {
3120 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3122 static const char *att_index64
= "%riz";
3123 static const char *att_index32
= "%eiz";
3124 static const char *att_index16
[] = {
3125 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3128 static const char **names_mm
;
3129 static const char *intel_names_mm
[] = {
3130 "mm0", "mm1", "mm2", "mm3",
3131 "mm4", "mm5", "mm6", "mm7"
3133 static const char *att_names_mm
[] = {
3134 "%mm0", "%mm1", "%mm2", "%mm3",
3135 "%mm4", "%mm5", "%mm6", "%mm7"
3138 static const char *intel_names_bnd
[] = {
3139 "bnd0", "bnd1", "bnd2", "bnd3"
3142 static const char *att_names_bnd
[] = {
3143 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3146 static const char **names_xmm
;
3147 static const char *intel_names_xmm
[] = {
3148 "xmm0", "xmm1", "xmm2", "xmm3",
3149 "xmm4", "xmm5", "xmm6", "xmm7",
3150 "xmm8", "xmm9", "xmm10", "xmm11",
3151 "xmm12", "xmm13", "xmm14", "xmm15",
3152 "xmm16", "xmm17", "xmm18", "xmm19",
3153 "xmm20", "xmm21", "xmm22", "xmm23",
3154 "xmm24", "xmm25", "xmm26", "xmm27",
3155 "xmm28", "xmm29", "xmm30", "xmm31"
3157 static const char *att_names_xmm
[] = {
3158 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3159 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3160 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3161 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3162 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3163 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3164 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3165 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3168 static const char **names_ymm
;
3169 static const char *intel_names_ymm
[] = {
3170 "ymm0", "ymm1", "ymm2", "ymm3",
3171 "ymm4", "ymm5", "ymm6", "ymm7",
3172 "ymm8", "ymm9", "ymm10", "ymm11",
3173 "ymm12", "ymm13", "ymm14", "ymm15",
3174 "ymm16", "ymm17", "ymm18", "ymm19",
3175 "ymm20", "ymm21", "ymm22", "ymm23",
3176 "ymm24", "ymm25", "ymm26", "ymm27",
3177 "ymm28", "ymm29", "ymm30", "ymm31"
3179 static const char *att_names_ymm
[] = {
3180 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3181 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3182 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3183 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3184 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3185 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3186 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3187 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3190 static const char **names_zmm
;
3191 static const char *intel_names_zmm
[] = {
3192 "zmm0", "zmm1", "zmm2", "zmm3",
3193 "zmm4", "zmm5", "zmm6", "zmm7",
3194 "zmm8", "zmm9", "zmm10", "zmm11",
3195 "zmm12", "zmm13", "zmm14", "zmm15",
3196 "zmm16", "zmm17", "zmm18", "zmm19",
3197 "zmm20", "zmm21", "zmm22", "zmm23",
3198 "zmm24", "zmm25", "zmm26", "zmm27",
3199 "zmm28", "zmm29", "zmm30", "zmm31"
3201 static const char *att_names_zmm
[] = {
3202 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3203 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3204 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3205 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3206 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3207 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3208 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3209 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3212 static const char **names_mask
;
3213 static const char *intel_names_mask
[] = {
3214 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3216 static const char *att_names_mask
[] = {
3217 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3220 static const char *names_rounding
[] =
3228 static const struct dis386 reg_table
[][8] = {
3231 { "addA", { Ebh1
, Ib
}, 0 },
3232 { "orA", { Ebh1
, Ib
}, 0 },
3233 { "adcA", { Ebh1
, Ib
}, 0 },
3234 { "sbbA", { Ebh1
, Ib
}, 0 },
3235 { "andA", { Ebh1
, Ib
}, 0 },
3236 { "subA", { Ebh1
, Ib
}, 0 },
3237 { "xorA", { Ebh1
, Ib
}, 0 },
3238 { "cmpA", { Eb
, Ib
}, 0 },
3242 { "addQ", { Evh1
, Iv
}, 0 },
3243 { "orQ", { Evh1
, Iv
}, 0 },
3244 { "adcQ", { Evh1
, Iv
}, 0 },
3245 { "sbbQ", { Evh1
, Iv
}, 0 },
3246 { "andQ", { Evh1
, Iv
}, 0 },
3247 { "subQ", { Evh1
, Iv
}, 0 },
3248 { "xorQ", { Evh1
, Iv
}, 0 },
3249 { "cmpQ", { Ev
, Iv
}, 0 },
3253 { "addQ", { Evh1
, sIb
}, 0 },
3254 { "orQ", { Evh1
, sIb
}, 0 },
3255 { "adcQ", { Evh1
, sIb
}, 0 },
3256 { "sbbQ", { Evh1
, sIb
}, 0 },
3257 { "andQ", { Evh1
, sIb
}, 0 },
3258 { "subQ", { Evh1
, sIb
}, 0 },
3259 { "xorQ", { Evh1
, sIb
}, 0 },
3260 { "cmpQ", { Ev
, sIb
}, 0 },
3264 { "popU", { stackEv
}, 0 },
3265 { XOP_8F_TABLE (XOP_09
) },
3269 { XOP_8F_TABLE (XOP_09
) },
3273 { "rolA", { Eb
, Ib
}, 0 },
3274 { "rorA", { Eb
, Ib
}, 0 },
3275 { "rclA", { Eb
, Ib
}, 0 },
3276 { "rcrA", { Eb
, Ib
}, 0 },
3277 { "shlA", { Eb
, Ib
}, 0 },
3278 { "shrA", { Eb
, Ib
}, 0 },
3279 { "shlA", { Eb
, Ib
}, 0 },
3280 { "sarA", { Eb
, Ib
}, 0 },
3284 { "rolQ", { Ev
, Ib
}, 0 },
3285 { "rorQ", { Ev
, Ib
}, 0 },
3286 { "rclQ", { Ev
, Ib
}, 0 },
3287 { "rcrQ", { Ev
, Ib
}, 0 },
3288 { "shlQ", { Ev
, Ib
}, 0 },
3289 { "shrQ", { Ev
, Ib
}, 0 },
3290 { "shlQ", { Ev
, Ib
}, 0 },
3291 { "sarQ", { Ev
, Ib
}, 0 },
3295 { "movA", { Ebh3
, Ib
}, 0 },
3302 { MOD_TABLE (MOD_C6_REG_7
) },
3306 { "movQ", { Evh3
, Iv
}, 0 },
3313 { MOD_TABLE (MOD_C7_REG_7
) },
3317 { "rolA", { Eb
, I1
}, 0 },
3318 { "rorA", { Eb
, I1
}, 0 },
3319 { "rclA", { Eb
, I1
}, 0 },
3320 { "rcrA", { Eb
, I1
}, 0 },
3321 { "shlA", { Eb
, I1
}, 0 },
3322 { "shrA", { Eb
, I1
}, 0 },
3323 { "shlA", { Eb
, I1
}, 0 },
3324 { "sarA", { Eb
, I1
}, 0 },
3328 { "rolQ", { Ev
, I1
}, 0 },
3329 { "rorQ", { Ev
, I1
}, 0 },
3330 { "rclQ", { Ev
, I1
}, 0 },
3331 { "rcrQ", { Ev
, I1
}, 0 },
3332 { "shlQ", { Ev
, I1
}, 0 },
3333 { "shrQ", { Ev
, I1
}, 0 },
3334 { "shlQ", { Ev
, I1
}, 0 },
3335 { "sarQ", { Ev
, I1
}, 0 },
3339 { "rolA", { Eb
, CL
}, 0 },
3340 { "rorA", { Eb
, CL
}, 0 },
3341 { "rclA", { Eb
, CL
}, 0 },
3342 { "rcrA", { Eb
, CL
}, 0 },
3343 { "shlA", { Eb
, CL
}, 0 },
3344 { "shrA", { Eb
, CL
}, 0 },
3345 { "shlA", { Eb
, CL
}, 0 },
3346 { "sarA", { Eb
, CL
}, 0 },
3350 { "rolQ", { Ev
, CL
}, 0 },
3351 { "rorQ", { Ev
, CL
}, 0 },
3352 { "rclQ", { Ev
, CL
}, 0 },
3353 { "rcrQ", { Ev
, CL
}, 0 },
3354 { "shlQ", { Ev
, CL
}, 0 },
3355 { "shrQ", { Ev
, CL
}, 0 },
3356 { "shlQ", { Ev
, CL
}, 0 },
3357 { "sarQ", { Ev
, CL
}, 0 },
3361 { "testA", { Eb
, Ib
}, 0 },
3362 { "testA", { Eb
, Ib
}, 0 },
3363 { "notA", { Ebh1
}, 0 },
3364 { "negA", { Ebh1
}, 0 },
3365 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3366 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3367 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3368 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3372 { "testQ", { Ev
, Iv
}, 0 },
3373 { "testQ", { Ev
, Iv
}, 0 },
3374 { "notQ", { Evh1
}, 0 },
3375 { "negQ", { Evh1
}, 0 },
3376 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3377 { "imulQ", { Ev
}, 0 },
3378 { "divQ", { Ev
}, 0 },
3379 { "idivQ", { Ev
}, 0 },
3383 { "incA", { Ebh1
}, 0 },
3384 { "decA", { Ebh1
}, 0 },
3388 { "incQ", { Evh1
}, 0 },
3389 { "decQ", { Evh1
}, 0 },
3390 { "call{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3391 { MOD_TABLE (MOD_FF_REG_3
) },
3392 { "jmp{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3393 { MOD_TABLE (MOD_FF_REG_5
) },
3394 { "pushU", { stackEv
}, 0 },
3399 { "sldtD", { Sv
}, 0 },
3400 { "strD", { Sv
}, 0 },
3401 { "lldt", { Ew
}, 0 },
3402 { "ltr", { Ew
}, 0 },
3403 { "verr", { Ew
}, 0 },
3404 { "verw", { Ew
}, 0 },
3410 { MOD_TABLE (MOD_0F01_REG_0
) },
3411 { MOD_TABLE (MOD_0F01_REG_1
) },
3412 { MOD_TABLE (MOD_0F01_REG_2
) },
3413 { MOD_TABLE (MOD_0F01_REG_3
) },
3414 { "smswD", { Sv
}, 0 },
3415 { MOD_TABLE (MOD_0F01_REG_5
) },
3416 { "lmsw", { Ew
}, 0 },
3417 { MOD_TABLE (MOD_0F01_REG_7
) },
3421 { "prefetch", { Mb
}, 0 },
3422 { "prefetchw", { Mb
}, 0 },
3423 { "prefetchwt1", { Mb
}, 0 },
3424 { "prefetch", { Mb
}, 0 },
3425 { "prefetch", { Mb
}, 0 },
3426 { "prefetch", { Mb
}, 0 },
3427 { "prefetch", { Mb
}, 0 },
3428 { "prefetch", { Mb
}, 0 },
3432 { MOD_TABLE (MOD_0F18_REG_0
) },
3433 { MOD_TABLE (MOD_0F18_REG_1
) },
3434 { MOD_TABLE (MOD_0F18_REG_2
) },
3435 { MOD_TABLE (MOD_0F18_REG_3
) },
3436 { MOD_TABLE (MOD_0F18_REG_4
) },
3437 { MOD_TABLE (MOD_0F18_REG_5
) },
3438 { MOD_TABLE (MOD_0F18_REG_6
) },
3439 { MOD_TABLE (MOD_0F18_REG_7
) },
3441 /* REG_0F1C_P_0_MOD_0 */
3443 { "cldemote", { Mb
}, 0 },
3444 { "nopQ", { Ev
}, 0 },
3445 { "nopQ", { Ev
}, 0 },
3446 { "nopQ", { Ev
}, 0 },
3447 { "nopQ", { Ev
}, 0 },
3448 { "nopQ", { Ev
}, 0 },
3449 { "nopQ", { Ev
}, 0 },
3450 { "nopQ", { Ev
}, 0 },
3452 /* REG_0F1E_P_1_MOD_3 */
3454 { "nopQ", { Ev
}, 0 },
3455 { "rdsspK", { Rdq
}, PREFIX_OPCODE
},
3456 { "nopQ", { Ev
}, 0 },
3457 { "nopQ", { Ev
}, 0 },
3458 { "nopQ", { Ev
}, 0 },
3459 { "nopQ", { Ev
}, 0 },
3460 { "nopQ", { Ev
}, 0 },
3461 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7
) },
3467 { MOD_TABLE (MOD_0F71_REG_2
) },
3469 { MOD_TABLE (MOD_0F71_REG_4
) },
3471 { MOD_TABLE (MOD_0F71_REG_6
) },
3477 { MOD_TABLE (MOD_0F72_REG_2
) },
3479 { MOD_TABLE (MOD_0F72_REG_4
) },
3481 { MOD_TABLE (MOD_0F72_REG_6
) },
3487 { MOD_TABLE (MOD_0F73_REG_2
) },
3488 { MOD_TABLE (MOD_0F73_REG_3
) },
3491 { MOD_TABLE (MOD_0F73_REG_6
) },
3492 { MOD_TABLE (MOD_0F73_REG_7
) },
3496 { "montmul", { { OP_0f07
, 0 } }, 0 },
3497 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3498 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3502 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3503 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3504 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3505 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3506 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3507 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3511 { MOD_TABLE (MOD_0FAE_REG_0
) },
3512 { MOD_TABLE (MOD_0FAE_REG_1
) },
3513 { MOD_TABLE (MOD_0FAE_REG_2
) },
3514 { MOD_TABLE (MOD_0FAE_REG_3
) },
3515 { MOD_TABLE (MOD_0FAE_REG_4
) },
3516 { MOD_TABLE (MOD_0FAE_REG_5
) },
3517 { MOD_TABLE (MOD_0FAE_REG_6
) },
3518 { MOD_TABLE (MOD_0FAE_REG_7
) },
3526 { "btQ", { Ev
, Ib
}, 0 },
3527 { "btsQ", { Evh1
, Ib
}, 0 },
3528 { "btrQ", { Evh1
, Ib
}, 0 },
3529 { "btcQ", { Evh1
, Ib
}, 0 },
3534 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3536 { MOD_TABLE (MOD_0FC7_REG_3
) },
3537 { MOD_TABLE (MOD_0FC7_REG_4
) },
3538 { MOD_TABLE (MOD_0FC7_REG_5
) },
3539 { MOD_TABLE (MOD_0FC7_REG_6
) },
3540 { MOD_TABLE (MOD_0FC7_REG_7
) },
3546 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3548 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3550 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3556 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3558 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3560 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3566 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3567 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3570 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3571 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3577 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3578 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3580 /* REG_VEX_0F38F3 */
3583 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3584 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3585 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3589 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3590 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3594 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Id
}, 0 },
3595 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Id
}, 0 },
3597 /* REG_XOP_TBM_01 */
3600 { "blcfill", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3601 { "blsfill", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3602 { "blcs", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3603 { "tzmsk", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3604 { "blcic", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3605 { "blsic", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3606 { "t1mskc", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3608 /* REG_XOP_TBM_02 */
3611 { "blcmsk", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3616 { "blci", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3619 #include "i386-dis-evex-reg.h"
3622 static const struct dis386 prefix_table
[][4] = {
3625 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3626 { "pause", { XX
}, 0 },
3627 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3628 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3631 /* PREFIX_0F01_REG_3_MOD_1 */
3633 { "vmmcall", { Skip_MODRM
}, 0 },
3634 { "vmgexit", { Skip_MODRM
}, 0 },
3636 { "vmgexit", { Skip_MODRM
}, 0 },
3639 /* PREFIX_0F01_REG_5_MOD_0 */
3642 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3645 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3648 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3651 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3654 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3657 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3659 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
3660 { "mcommit", { Skip_MODRM
}, 0 },
3663 /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3665 { "mwaitx", { { OP_Mwait
, eBX_reg
} }, 0 },
3670 { "wbinvd", { XX
}, 0 },
3671 { "wbnoinvd", { XX
}, 0 },
3676 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3677 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3678 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3679 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3684 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3685 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3686 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3687 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3692 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3693 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3694 { "movlpd", { XM
, EXq
}, PREFIX_OPCODE
},
3695 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3700 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3701 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3702 { "movhpd", { XM
, EXq
}, PREFIX_OPCODE
},
3707 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3708 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3709 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3710 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3715 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3716 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3717 { "bndmov", { EbndS
, Gbnd
}, 0 },
3718 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3723 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3724 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3725 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3726 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3731 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3732 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3733 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3734 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3739 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3740 { "cvtsi2ss%LQ", { XM
, Edq
}, PREFIX_OPCODE
},
3741 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3742 { "cvtsi2sd%LQ", { XM
, Edq
}, 0 },
3747 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3748 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3749 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3750 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3755 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3756 { "cvttss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3757 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3758 { "cvttsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3763 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3764 { "cvtss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3765 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3766 { "cvtsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3771 { "ucomiss",{ XM
, EXd
}, 0 },
3773 { "ucomisd",{ XM
, EXq
}, 0 },
3778 { "comiss", { XM
, EXd
}, 0 },
3780 { "comisd", { XM
, EXq
}, 0 },
3785 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3786 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3787 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3788 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3793 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3794 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3799 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3800 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3805 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3806 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3807 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3808 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3813 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3814 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3815 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3816 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3821 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3822 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3823 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3824 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3829 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3830 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3831 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3836 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3837 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3838 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3839 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3844 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3845 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3846 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3847 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3852 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3853 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3854 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3855 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3860 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3861 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3862 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3863 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3868 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3870 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3875 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3877 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3882 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3884 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3891 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3898 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3903 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3904 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3905 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3910 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3911 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3912 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3913 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3916 /* PREFIX_0F73_REG_3 */
3920 { "psrldq", { XS
, Ib
}, 0 },
3923 /* PREFIX_0F73_REG_7 */
3927 { "pslldq", { XS
, Ib
}, 0 },
3932 {"vmread", { Em
, Gm
}, 0 },
3934 {"extrq", { XS
, Ib
, Ib
}, 0 },
3935 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3940 {"vmwrite", { Gm
, Em
}, 0 },
3942 {"extrq", { XM
, XS
}, 0 },
3943 {"insertq", { XM
, XS
}, 0 },
3950 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3951 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3958 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3959 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3964 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3965 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3966 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3971 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3972 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3973 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3976 /* PREFIX_0FAE_REG_0_MOD_3 */
3979 { "rdfsbase", { Ev
}, 0 },
3982 /* PREFIX_0FAE_REG_1_MOD_3 */
3985 { "rdgsbase", { Ev
}, 0 },
3988 /* PREFIX_0FAE_REG_2_MOD_3 */
3991 { "wrfsbase", { Ev
}, 0 },
3994 /* PREFIX_0FAE_REG_3_MOD_3 */
3997 { "wrgsbase", { Ev
}, 0 },
4000 /* PREFIX_0FAE_REG_4_MOD_0 */
4002 { "xsave", { FXSAVE
}, 0 },
4003 { "ptwrite%LQ", { Edq
}, 0 },
4006 /* PREFIX_0FAE_REG_4_MOD_3 */
4009 { "ptwrite%LQ", { Edq
}, 0 },
4012 /* PREFIX_0FAE_REG_5_MOD_0 */
4014 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
4017 /* PREFIX_0FAE_REG_5_MOD_3 */
4019 { "lfence", { Skip_MODRM
}, 0 },
4020 { "incsspK", { Rdq
}, PREFIX_OPCODE
},
4023 /* PREFIX_0FAE_REG_6_MOD_0 */
4025 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
4026 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
4027 { "clwb", { Mb
}, PREFIX_OPCODE
},
4030 /* PREFIX_0FAE_REG_6_MOD_3 */
4032 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0
) },
4033 { "umonitor", { Eva
}, PREFIX_OPCODE
},
4034 { "tpause", { Edq
}, PREFIX_OPCODE
},
4035 { "umwait", { Edq
}, PREFIX_OPCODE
},
4038 /* PREFIX_0FAE_REG_7_MOD_0 */
4040 { "clflush", { Mb
}, 0 },
4042 { "clflushopt", { Mb
}, 0 },
4048 { "popcntS", { Gv
, Ev
}, 0 },
4053 { "bsfS", { Gv
, Ev
}, 0 },
4054 { "tzcntS", { Gv
, Ev
}, 0 },
4055 { "bsfS", { Gv
, Ev
}, 0 },
4060 { "bsrS", { Gv
, Ev
}, 0 },
4061 { "lzcntS", { Gv
, Ev
}, 0 },
4062 { "bsrS", { Gv
, Ev
}, 0 },
4067 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4068 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4069 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4070 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4073 /* PREFIX_0FC3_MOD_0 */
4075 { "movntiS", { Edq
, Gdq
}, PREFIX_OPCODE
},
4078 /* PREFIX_0FC7_REG_6_MOD_0 */
4080 { "vmptrld",{ Mq
}, 0 },
4081 { "vmxon", { Mq
}, 0 },
4082 { "vmclear",{ Mq
}, 0 },
4085 /* PREFIX_0FC7_REG_6_MOD_3 */
4087 { "rdrand", { Ev
}, 0 },
4089 { "rdrand", { Ev
}, 0 }
4092 /* PREFIX_0FC7_REG_7_MOD_3 */
4094 { "rdseed", { Ev
}, 0 },
4095 { "rdpid", { Em
}, 0 },
4096 { "rdseed", { Ev
}, 0 },
4103 { "addsubpd", { XM
, EXx
}, 0 },
4104 { "addsubps", { XM
, EXx
}, 0 },
4110 { "movq2dq",{ XM
, MS
}, 0 },
4111 { "movq", { EXqS
, XM
}, 0 },
4112 { "movdq2q",{ MX
, XS
}, 0 },
4118 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4119 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4120 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4125 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4127 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4135 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4140 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4142 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4149 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4156 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4163 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4170 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4177 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4184 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4191 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4198 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4205 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4212 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4219 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4226 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4233 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4240 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4247 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4254 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4261 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4268 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4275 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4282 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4289 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4296 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4303 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4310 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4317 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4324 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4331 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4338 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4345 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4352 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4359 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4366 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4373 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4380 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4385 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4390 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4395 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4400 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4405 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4410 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4417 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_OPCODE
},
4424 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4431 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4438 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4445 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4452 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4457 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4459 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4460 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4465 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4467 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4468 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4475 { MOD_TABLE (MOD_0F38F5_PREFIX_2
) },
4480 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
4481 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4482 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4489 { MOD_TABLE (MOD_0F38F8_PREFIX_1
) },
4490 { MOD_TABLE (MOD_0F38F8_PREFIX_2
) },
4491 { MOD_TABLE (MOD_0F38F8_PREFIX_3
) },
4496 { MOD_TABLE (MOD_0F38F9_PREFIX_0
) },
4503 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4510 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4517 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4524 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4531 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4538 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4545 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4552 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4559 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4566 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4573 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4580 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4587 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4594 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4601 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4608 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4615 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4622 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4629 { "pcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4636 { "pcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4643 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4650 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4655 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4662 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4669 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4676 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4679 /* PREFIX_VEX_0F10 */
4681 { "vmovups", { XM
, EXx
}, 0 },
4682 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
}, 0 },
4683 { "vmovupd", { XM
, EXx
}, 0 },
4684 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
}, 0 },
4687 /* PREFIX_VEX_0F11 */
4689 { "vmovups", { EXxS
, XM
}, 0 },
4690 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
4691 { "vmovupd", { EXxS
, XM
}, 0 },
4692 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
4695 /* PREFIX_VEX_0F12 */
4697 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4698 { "vmovsldup", { XM
, EXx
}, 0 },
4699 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4700 { "vmovddup", { XM
, EXymmq
}, 0 },
4703 /* PREFIX_VEX_0F16 */
4705 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4706 { "vmovshdup", { XM
, EXx
}, 0 },
4707 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4710 /* PREFIX_VEX_0F2A */
4713 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4715 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4718 /* PREFIX_VEX_0F2C */
4721 { "vcvttss2si", { Gdq
, EXdScalar
}, 0 },
4723 { "vcvttsd2si", { Gdq
, EXqScalar
}, 0 },
4726 /* PREFIX_VEX_0F2D */
4729 { "vcvtss2si", { Gdq
, EXdScalar
}, 0 },
4731 { "vcvtsd2si", { Gdq
, EXqScalar
}, 0 },
4734 /* PREFIX_VEX_0F2E */
4736 { "vucomiss", { XMScalar
, EXdScalar
}, 0 },
4738 { "vucomisd", { XMScalar
, EXqScalar
}, 0 },
4741 /* PREFIX_VEX_0F2F */
4743 { "vcomiss", { XMScalar
, EXdScalar
}, 0 },
4745 { "vcomisd", { XMScalar
, EXqScalar
}, 0 },
4748 /* PREFIX_VEX_0F41 */
4750 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4752 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4755 /* PREFIX_VEX_0F42 */
4757 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4759 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4762 /* PREFIX_VEX_0F44 */
4764 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4766 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4769 /* PREFIX_VEX_0F45 */
4771 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4773 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4776 /* PREFIX_VEX_0F46 */
4778 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4780 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4783 /* PREFIX_VEX_0F47 */
4785 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4787 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4790 /* PREFIX_VEX_0F4A */
4792 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4794 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4797 /* PREFIX_VEX_0F4B */
4799 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4801 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4804 /* PREFIX_VEX_0F51 */
4806 { "vsqrtps", { XM
, EXx
}, 0 },
4807 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4808 { "vsqrtpd", { XM
, EXx
}, 0 },
4809 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4812 /* PREFIX_VEX_0F52 */
4814 { "vrsqrtps", { XM
, EXx
}, 0 },
4815 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4818 /* PREFIX_VEX_0F53 */
4820 { "vrcpps", { XM
, EXx
}, 0 },
4821 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4824 /* PREFIX_VEX_0F58 */
4826 { "vaddps", { XM
, Vex
, EXx
}, 0 },
4827 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4828 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
4829 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4832 /* PREFIX_VEX_0F59 */
4834 { "vmulps", { XM
, Vex
, EXx
}, 0 },
4835 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4836 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
4837 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4840 /* PREFIX_VEX_0F5A */
4842 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
4843 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4844 { "vcvtpd2ps%XY",{ XMM
, EXx
}, 0 },
4845 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4848 /* PREFIX_VEX_0F5B */
4850 { "vcvtdq2ps", { XM
, EXx
}, 0 },
4851 { "vcvttps2dq", { XM
, EXx
}, 0 },
4852 { "vcvtps2dq", { XM
, EXx
}, 0 },
4855 /* PREFIX_VEX_0F5C */
4857 { "vsubps", { XM
, Vex
, EXx
}, 0 },
4858 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4859 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
4860 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4863 /* PREFIX_VEX_0F5D */
4865 { "vminps", { XM
, Vex
, EXx
}, 0 },
4866 { "vminss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4867 { "vminpd", { XM
, Vex
, EXx
}, 0 },
4868 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4871 /* PREFIX_VEX_0F5E */
4873 { "vdivps", { XM
, Vex
, EXx
}, 0 },
4874 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4875 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
4876 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4879 /* PREFIX_VEX_0F5F */
4881 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
4882 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4883 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
4884 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4887 /* PREFIX_VEX_0F60 */
4891 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
4894 /* PREFIX_VEX_0F61 */
4898 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
4901 /* PREFIX_VEX_0F62 */
4905 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
4908 /* PREFIX_VEX_0F63 */
4912 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
4915 /* PREFIX_VEX_0F64 */
4919 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
4922 /* PREFIX_VEX_0F65 */
4926 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
4929 /* PREFIX_VEX_0F66 */
4933 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
4936 /* PREFIX_VEX_0F67 */
4940 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
4943 /* PREFIX_VEX_0F68 */
4947 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
4950 /* PREFIX_VEX_0F69 */
4954 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
4957 /* PREFIX_VEX_0F6A */
4961 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
4964 /* PREFIX_VEX_0F6B */
4968 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
4971 /* PREFIX_VEX_0F6C */
4975 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
4978 /* PREFIX_VEX_0F6D */
4982 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
4985 /* PREFIX_VEX_0F6E */
4989 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4992 /* PREFIX_VEX_0F6F */
4995 { "vmovdqu", { XM
, EXx
}, 0 },
4996 { "vmovdqa", { XM
, EXx
}, 0 },
4999 /* PREFIX_VEX_0F70 */
5002 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
5003 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
5004 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
5007 /* PREFIX_VEX_0F71_REG_2 */
5011 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
5014 /* PREFIX_VEX_0F71_REG_4 */
5018 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
5021 /* PREFIX_VEX_0F71_REG_6 */
5025 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
5028 /* PREFIX_VEX_0F72_REG_2 */
5032 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
5035 /* PREFIX_VEX_0F72_REG_4 */
5039 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
5042 /* PREFIX_VEX_0F72_REG_6 */
5046 { "vpslld", { Vex
, XS
, Ib
}, 0 },
5049 /* PREFIX_VEX_0F73_REG_2 */
5053 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
5056 /* PREFIX_VEX_0F73_REG_3 */
5060 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
5063 /* PREFIX_VEX_0F73_REG_6 */
5067 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
5070 /* PREFIX_VEX_0F73_REG_7 */
5074 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
5077 /* PREFIX_VEX_0F74 */
5081 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
5084 /* PREFIX_VEX_0F75 */
5088 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
5091 /* PREFIX_VEX_0F76 */
5095 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
5098 /* PREFIX_VEX_0F77 */
5100 { VEX_LEN_TABLE (VEX_LEN_0F77_P_0
) },
5103 /* PREFIX_VEX_0F7C */
5107 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
5108 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
5111 /* PREFIX_VEX_0F7D */
5115 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
5116 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
5119 /* PREFIX_VEX_0F7E */
5122 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5123 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5126 /* PREFIX_VEX_0F7F */
5129 { "vmovdqu", { EXxS
, XM
}, 0 },
5130 { "vmovdqa", { EXxS
, XM
}, 0 },
5133 /* PREFIX_VEX_0F90 */
5135 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5137 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5140 /* PREFIX_VEX_0F91 */
5142 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5144 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5147 /* PREFIX_VEX_0F92 */
5149 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5151 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5152 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5155 /* PREFIX_VEX_0F93 */
5157 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5159 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5160 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5163 /* PREFIX_VEX_0F98 */
5165 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5167 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5170 /* PREFIX_VEX_0F99 */
5172 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5174 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5177 /* PREFIX_VEX_0FC2 */
5179 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
5180 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
}, 0 },
5181 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
5182 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
}, 0 },
5185 /* PREFIX_VEX_0FC4 */
5189 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5192 /* PREFIX_VEX_0FC5 */
5196 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5199 /* PREFIX_VEX_0FD0 */
5203 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
5204 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
5207 /* PREFIX_VEX_0FD1 */
5211 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
5214 /* PREFIX_VEX_0FD2 */
5218 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
5221 /* PREFIX_VEX_0FD3 */
5225 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
5228 /* PREFIX_VEX_0FD4 */
5232 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
5235 /* PREFIX_VEX_0FD5 */
5239 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
5242 /* PREFIX_VEX_0FD6 */
5246 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5249 /* PREFIX_VEX_0FD7 */
5253 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5256 /* PREFIX_VEX_0FD8 */
5260 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
5263 /* PREFIX_VEX_0FD9 */
5267 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
5270 /* PREFIX_VEX_0FDA */
5274 { "vpminub", { XM
, Vex
, EXx
}, 0 },
5277 /* PREFIX_VEX_0FDB */
5281 { "vpand", { XM
, Vex
, EXx
}, 0 },
5284 /* PREFIX_VEX_0FDC */
5288 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
5291 /* PREFIX_VEX_0FDD */
5295 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
5298 /* PREFIX_VEX_0FDE */
5302 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
5305 /* PREFIX_VEX_0FDF */
5309 { "vpandn", { XM
, Vex
, EXx
}, 0 },
5312 /* PREFIX_VEX_0FE0 */
5316 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
5319 /* PREFIX_VEX_0FE1 */
5323 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
5326 /* PREFIX_VEX_0FE2 */
5330 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
5333 /* PREFIX_VEX_0FE3 */
5337 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
5340 /* PREFIX_VEX_0FE4 */
5344 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
5347 /* PREFIX_VEX_0FE5 */
5351 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
5354 /* PREFIX_VEX_0FE6 */
5357 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
5358 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
5359 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
5362 /* PREFIX_VEX_0FE7 */
5366 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5369 /* PREFIX_VEX_0FE8 */
5373 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
5376 /* PREFIX_VEX_0FE9 */
5380 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
5383 /* PREFIX_VEX_0FEA */
5387 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
5390 /* PREFIX_VEX_0FEB */
5394 { "vpor", { XM
, Vex
, EXx
}, 0 },
5397 /* PREFIX_VEX_0FEC */
5401 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
5404 /* PREFIX_VEX_0FED */
5408 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
5411 /* PREFIX_VEX_0FEE */
5415 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
5418 /* PREFIX_VEX_0FEF */
5422 { "vpxor", { XM
, Vex
, EXx
}, 0 },
5425 /* PREFIX_VEX_0FF0 */
5430 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5433 /* PREFIX_VEX_0FF1 */
5437 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
5440 /* PREFIX_VEX_0FF2 */
5444 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
5447 /* PREFIX_VEX_0FF3 */
5451 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
5454 /* PREFIX_VEX_0FF4 */
5458 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
5461 /* PREFIX_VEX_0FF5 */
5465 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
5468 /* PREFIX_VEX_0FF6 */
5472 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
5475 /* PREFIX_VEX_0FF7 */
5479 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5482 /* PREFIX_VEX_0FF8 */
5486 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
5489 /* PREFIX_VEX_0FF9 */
5493 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
5496 /* PREFIX_VEX_0FFA */
5500 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
5503 /* PREFIX_VEX_0FFB */
5507 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
5510 /* PREFIX_VEX_0FFC */
5514 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
5517 /* PREFIX_VEX_0FFD */
5521 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
5524 /* PREFIX_VEX_0FFE */
5528 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
5531 /* PREFIX_VEX_0F3800 */
5535 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
5538 /* PREFIX_VEX_0F3801 */
5542 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
5545 /* PREFIX_VEX_0F3802 */
5549 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
5552 /* PREFIX_VEX_0F3803 */
5556 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
5559 /* PREFIX_VEX_0F3804 */
5563 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
5566 /* PREFIX_VEX_0F3805 */
5570 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
5573 /* PREFIX_VEX_0F3806 */
5577 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
5580 /* PREFIX_VEX_0F3807 */
5584 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
5587 /* PREFIX_VEX_0F3808 */
5591 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
5594 /* PREFIX_VEX_0F3809 */
5598 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
5601 /* PREFIX_VEX_0F380A */
5605 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
5608 /* PREFIX_VEX_0F380B */
5612 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
5615 /* PREFIX_VEX_0F380C */
5619 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5622 /* PREFIX_VEX_0F380D */
5626 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5629 /* PREFIX_VEX_0F380E */
5633 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5636 /* PREFIX_VEX_0F380F */
5640 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5643 /* PREFIX_VEX_0F3813 */
5647 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
5650 /* PREFIX_VEX_0F3816 */
5654 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5657 /* PREFIX_VEX_0F3817 */
5661 { "vptest", { XM
, EXx
}, 0 },
5664 /* PREFIX_VEX_0F3818 */
5668 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5671 /* PREFIX_VEX_0F3819 */
5675 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5678 /* PREFIX_VEX_0F381A */
5682 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5685 /* PREFIX_VEX_0F381C */
5689 { "vpabsb", { XM
, EXx
}, 0 },
5692 /* PREFIX_VEX_0F381D */
5696 { "vpabsw", { XM
, EXx
}, 0 },
5699 /* PREFIX_VEX_0F381E */
5703 { "vpabsd", { XM
, EXx
}, 0 },
5706 /* PREFIX_VEX_0F3820 */
5710 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
5713 /* PREFIX_VEX_0F3821 */
5717 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
5720 /* PREFIX_VEX_0F3822 */
5724 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
5727 /* PREFIX_VEX_0F3823 */
5731 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
5734 /* PREFIX_VEX_0F3824 */
5738 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
5741 /* PREFIX_VEX_0F3825 */
5745 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
5748 /* PREFIX_VEX_0F3828 */
5752 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
5755 /* PREFIX_VEX_0F3829 */
5759 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
5762 /* PREFIX_VEX_0F382A */
5766 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5769 /* PREFIX_VEX_0F382B */
5773 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
5776 /* PREFIX_VEX_0F382C */
5780 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5783 /* PREFIX_VEX_0F382D */
5787 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5790 /* PREFIX_VEX_0F382E */
5794 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5797 /* PREFIX_VEX_0F382F */
5801 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5804 /* PREFIX_VEX_0F3830 */
5808 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
5811 /* PREFIX_VEX_0F3831 */
5815 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
5818 /* PREFIX_VEX_0F3832 */
5822 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
5825 /* PREFIX_VEX_0F3833 */
5829 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
5832 /* PREFIX_VEX_0F3834 */
5836 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
5839 /* PREFIX_VEX_0F3835 */
5843 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
5846 /* PREFIX_VEX_0F3836 */
5850 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5853 /* PREFIX_VEX_0F3837 */
5857 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
5860 /* PREFIX_VEX_0F3838 */
5864 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
5867 /* PREFIX_VEX_0F3839 */
5871 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
5874 /* PREFIX_VEX_0F383A */
5878 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
5881 /* PREFIX_VEX_0F383B */
5885 { "vpminud", { XM
, Vex
, EXx
}, 0 },
5888 /* PREFIX_VEX_0F383C */
5892 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
5895 /* PREFIX_VEX_0F383D */
5899 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
5902 /* PREFIX_VEX_0F383E */
5906 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
5909 /* PREFIX_VEX_0F383F */
5913 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
5916 /* PREFIX_VEX_0F3840 */
5920 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
5923 /* PREFIX_VEX_0F3841 */
5927 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5930 /* PREFIX_VEX_0F3845 */
5934 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
5937 /* PREFIX_VEX_0F3846 */
5941 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5944 /* PREFIX_VEX_0F3847 */
5948 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
5951 /* PREFIX_VEX_0F3858 */
5955 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5958 /* PREFIX_VEX_0F3859 */
5962 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5965 /* PREFIX_VEX_0F385A */
5969 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5972 /* PREFIX_VEX_0F3878 */
5976 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5979 /* PREFIX_VEX_0F3879 */
5983 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5986 /* PREFIX_VEX_0F388C */
5990 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5993 /* PREFIX_VEX_0F388E */
5997 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
6000 /* PREFIX_VEX_0F3890 */
6004 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6007 /* PREFIX_VEX_0F3891 */
6011 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6014 /* PREFIX_VEX_0F3892 */
6018 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6021 /* PREFIX_VEX_0F3893 */
6025 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6028 /* PREFIX_VEX_0F3896 */
6032 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6035 /* PREFIX_VEX_0F3897 */
6039 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6042 /* PREFIX_VEX_0F3898 */
6046 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6049 /* PREFIX_VEX_0F3899 */
6053 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6056 /* PREFIX_VEX_0F389A */
6060 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6063 /* PREFIX_VEX_0F389B */
6067 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6070 /* PREFIX_VEX_0F389C */
6074 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6077 /* PREFIX_VEX_0F389D */
6081 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6084 /* PREFIX_VEX_0F389E */
6088 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6091 /* PREFIX_VEX_0F389F */
6095 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6098 /* PREFIX_VEX_0F38A6 */
6102 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6106 /* PREFIX_VEX_0F38A7 */
6110 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6113 /* PREFIX_VEX_0F38A8 */
6117 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6120 /* PREFIX_VEX_0F38A9 */
6124 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6127 /* PREFIX_VEX_0F38AA */
6131 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6134 /* PREFIX_VEX_0F38AB */
6138 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6141 /* PREFIX_VEX_0F38AC */
6145 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6148 /* PREFIX_VEX_0F38AD */
6152 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6155 /* PREFIX_VEX_0F38AE */
6159 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6162 /* PREFIX_VEX_0F38AF */
6166 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6169 /* PREFIX_VEX_0F38B6 */
6173 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6176 /* PREFIX_VEX_0F38B7 */
6180 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6183 /* PREFIX_VEX_0F38B8 */
6187 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6190 /* PREFIX_VEX_0F38B9 */
6194 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6197 /* PREFIX_VEX_0F38BA */
6201 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6204 /* PREFIX_VEX_0F38BB */
6208 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6211 /* PREFIX_VEX_0F38BC */
6215 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6218 /* PREFIX_VEX_0F38BD */
6222 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6225 /* PREFIX_VEX_0F38BE */
6229 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6232 /* PREFIX_VEX_0F38BF */
6236 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6239 /* PREFIX_VEX_0F38CF */
6243 { VEX_W_TABLE (VEX_W_0F38CF_P_2
) },
6246 /* PREFIX_VEX_0F38DB */
6250 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6253 /* PREFIX_VEX_0F38DC */
6257 { "vaesenc", { XM
, Vex
, EXx
}, 0 },
6260 /* PREFIX_VEX_0F38DD */
6264 { "vaesenclast", { XM
, Vex
, EXx
}, 0 },
6267 /* PREFIX_VEX_0F38DE */
6271 { "vaesdec", { XM
, Vex
, EXx
}, 0 },
6274 /* PREFIX_VEX_0F38DF */
6278 { "vaesdeclast", { XM
, Vex
, EXx
}, 0 },
6281 /* PREFIX_VEX_0F38F2 */
6283 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6286 /* PREFIX_VEX_0F38F3_REG_1 */
6288 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6291 /* PREFIX_VEX_0F38F3_REG_2 */
6293 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6296 /* PREFIX_VEX_0F38F3_REG_3 */
6298 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6301 /* PREFIX_VEX_0F38F5 */
6303 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6304 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6306 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6309 /* PREFIX_VEX_0F38F6 */
6314 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6317 /* PREFIX_VEX_0F38F7 */
6319 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6320 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6321 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6322 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6325 /* PREFIX_VEX_0F3A00 */
6329 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6332 /* PREFIX_VEX_0F3A01 */
6336 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6339 /* PREFIX_VEX_0F3A02 */
6343 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6346 /* PREFIX_VEX_0F3A04 */
6350 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6353 /* PREFIX_VEX_0F3A05 */
6357 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6360 /* PREFIX_VEX_0F3A06 */
6364 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6367 /* PREFIX_VEX_0F3A08 */
6371 { "vroundps", { XM
, EXx
, Ib
}, 0 },
6374 /* PREFIX_VEX_0F3A09 */
6378 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
6381 /* PREFIX_VEX_0F3A0A */
6385 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
}, 0 },
6388 /* PREFIX_VEX_0F3A0B */
6392 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
}, 0 },
6395 /* PREFIX_VEX_0F3A0C */
6399 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
6402 /* PREFIX_VEX_0F3A0D */
6406 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
6409 /* PREFIX_VEX_0F3A0E */
6413 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
6416 /* PREFIX_VEX_0F3A0F */
6420 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
6423 /* PREFIX_VEX_0F3A14 */
6427 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6430 /* PREFIX_VEX_0F3A15 */
6434 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6437 /* PREFIX_VEX_0F3A16 */
6441 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6444 /* PREFIX_VEX_0F3A17 */
6448 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6451 /* PREFIX_VEX_0F3A18 */
6455 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6458 /* PREFIX_VEX_0F3A19 */
6462 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6465 /* PREFIX_VEX_0F3A1D */
6469 { "vcvtps2ph", { EXxmmq
, XM
, Ib
}, 0 },
6472 /* PREFIX_VEX_0F3A20 */
6476 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6479 /* PREFIX_VEX_0F3A21 */
6483 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6486 /* PREFIX_VEX_0F3A22 */
6490 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6493 /* PREFIX_VEX_0F3A30 */
6497 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6500 /* PREFIX_VEX_0F3A31 */
6504 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6507 /* PREFIX_VEX_0F3A32 */
6511 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6514 /* PREFIX_VEX_0F3A33 */
6518 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6521 /* PREFIX_VEX_0F3A38 */
6525 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6528 /* PREFIX_VEX_0F3A39 */
6532 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6535 /* PREFIX_VEX_0F3A40 */
6539 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
6542 /* PREFIX_VEX_0F3A41 */
6546 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6549 /* PREFIX_VEX_0F3A42 */
6553 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
6556 /* PREFIX_VEX_0F3A44 */
6560 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, 0 },
6563 /* PREFIX_VEX_0F3A46 */
6567 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6570 /* PREFIX_VEX_0F3A48 */
6574 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6577 /* PREFIX_VEX_0F3A49 */
6581 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6584 /* PREFIX_VEX_0F3A4A */
6588 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6591 /* PREFIX_VEX_0F3A4B */
6595 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6598 /* PREFIX_VEX_0F3A4C */
6602 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6605 /* PREFIX_VEX_0F3A5C */
6609 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6612 /* PREFIX_VEX_0F3A5D */
6616 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6619 /* PREFIX_VEX_0F3A5E */
6623 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6626 /* PREFIX_VEX_0F3A5F */
6630 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6633 /* PREFIX_VEX_0F3A60 */
6637 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6641 /* PREFIX_VEX_0F3A61 */
6645 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6648 /* PREFIX_VEX_0F3A62 */
6652 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6655 /* PREFIX_VEX_0F3A63 */
6659 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6662 /* PREFIX_VEX_0F3A68 */
6666 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6669 /* PREFIX_VEX_0F3A69 */
6673 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6676 /* PREFIX_VEX_0F3A6A */
6680 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6683 /* PREFIX_VEX_0F3A6B */
6687 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6690 /* PREFIX_VEX_0F3A6C */
6694 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6697 /* PREFIX_VEX_0F3A6D */
6701 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6704 /* PREFIX_VEX_0F3A6E */
6708 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6711 /* PREFIX_VEX_0F3A6F */
6715 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6718 /* PREFIX_VEX_0F3A78 */
6722 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6725 /* PREFIX_VEX_0F3A79 */
6729 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6732 /* PREFIX_VEX_0F3A7A */
6736 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6739 /* PREFIX_VEX_0F3A7B */
6743 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6746 /* PREFIX_VEX_0F3A7C */
6750 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6754 /* PREFIX_VEX_0F3A7D */
6758 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6761 /* PREFIX_VEX_0F3A7E */
6765 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6768 /* PREFIX_VEX_0F3A7F */
6772 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6775 /* PREFIX_VEX_0F3ACE */
6779 { VEX_W_TABLE (VEX_W_0F3ACE_P_2
) },
6782 /* PREFIX_VEX_0F3ACF */
6786 { VEX_W_TABLE (VEX_W_0F3ACF_P_2
) },
6789 /* PREFIX_VEX_0F3ADF */
6793 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6796 /* PREFIX_VEX_0F3AF0 */
6801 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6804 #include "i386-dis-evex-prefix.h"
6807 static const struct dis386 x86_64_table
[][2] = {
6810 { "pushP", { es
}, 0 },
6815 { "popP", { es
}, 0 },
6820 { "pushP", { cs
}, 0 },
6825 { "pushP", { ss
}, 0 },
6830 { "popP", { ss
}, 0 },
6835 { "pushP", { ds
}, 0 },
6840 { "popP", { ds
}, 0 },
6845 { "daa", { XX
}, 0 },
6850 { "das", { XX
}, 0 },
6855 { "aaa", { XX
}, 0 },
6860 { "aas", { XX
}, 0 },
6865 { "pushaP", { XX
}, 0 },
6870 { "popaP", { XX
}, 0 },
6875 { MOD_TABLE (MOD_62_32BIT
) },
6876 { EVEX_TABLE (EVEX_0F
) },
6881 { "arpl", { Ew
, Gw
}, 0 },
6882 { "movs", { { OP_G
, movsxd_mode
}, { MOVSXD_Fixup
, movsxd_mode
} }, 0 },
6887 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6888 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6893 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6894 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6899 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
6900 { REG_TABLE (REG_80
) },
6905 { "Jcall{T|}", { Ap
}, 0 },
6910 { "retP", { Iw
, BND
}, 0 },
6911 { "ret@", { Iw
, BND
}, 0 },
6916 { "retP", { BND
}, 0 },
6917 { "ret@", { BND
}, 0 },
6922 { MOD_TABLE (MOD_C4_32BIT
) },
6923 { VEX_C4_TABLE (VEX_0F
) },
6928 { MOD_TABLE (MOD_C5_32BIT
) },
6929 { VEX_C5_TABLE (VEX_0F
) },
6934 { "into", { XX
}, 0 },
6939 { "aam", { Ib
}, 0 },
6944 { "aad", { Ib
}, 0 },
6949 { "callP", { Jv
, BND
}, 0 },
6950 { "call@", { Jv
, BND
}, 0 }
6955 { "jmpP", { Jv
, BND
}, 0 },
6956 { "jmp@", { Jv
, BND
}, 0 }
6961 { "Jjmp{T|}", { Ap
}, 0 },
6964 /* X86_64_0F01_REG_0 */
6966 { "sgdt{Q|IQ}", { M
}, 0 },
6967 { "sgdt", { M
}, 0 },
6970 /* X86_64_0F01_REG_1 */
6972 { "sidt{Q|IQ}", { M
}, 0 },
6973 { "sidt", { M
}, 0 },
6976 /* X86_64_0F01_REG_2 */
6978 { "lgdt{Q|Q}", { M
}, 0 },
6979 { "lgdt", { M
}, 0 },
6982 /* X86_64_0F01_REG_3 */
6984 { "lidt{Q|Q}", { M
}, 0 },
6985 { "lidt", { M
}, 0 },
6989 static const struct dis386 three_byte_table
[][256] = {
6991 /* THREE_BYTE_0F38 */
6994 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
6995 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
6996 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
6997 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
6998 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
6999 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
7000 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
7001 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
7003 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
7004 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
7005 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
7006 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
7012 { PREFIX_TABLE (PREFIX_0F3810
) },
7016 { PREFIX_TABLE (PREFIX_0F3814
) },
7017 { PREFIX_TABLE (PREFIX_0F3815
) },
7019 { PREFIX_TABLE (PREFIX_0F3817
) },
7025 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
7026 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
7027 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
7030 { PREFIX_TABLE (PREFIX_0F3820
) },
7031 { PREFIX_TABLE (PREFIX_0F3821
) },
7032 { PREFIX_TABLE (PREFIX_0F3822
) },
7033 { PREFIX_TABLE (PREFIX_0F3823
) },
7034 { PREFIX_TABLE (PREFIX_0F3824
) },
7035 { PREFIX_TABLE (PREFIX_0F3825
) },
7039 { PREFIX_TABLE (PREFIX_0F3828
) },
7040 { PREFIX_TABLE (PREFIX_0F3829
) },
7041 { PREFIX_TABLE (PREFIX_0F382A
) },
7042 { PREFIX_TABLE (PREFIX_0F382B
) },
7048 { PREFIX_TABLE (PREFIX_0F3830
) },
7049 { PREFIX_TABLE (PREFIX_0F3831
) },
7050 { PREFIX_TABLE (PREFIX_0F3832
) },
7051 { PREFIX_TABLE (PREFIX_0F3833
) },
7052 { PREFIX_TABLE (PREFIX_0F3834
) },
7053 { PREFIX_TABLE (PREFIX_0F3835
) },
7055 { PREFIX_TABLE (PREFIX_0F3837
) },
7057 { PREFIX_TABLE (PREFIX_0F3838
) },
7058 { PREFIX_TABLE (PREFIX_0F3839
) },
7059 { PREFIX_TABLE (PREFIX_0F383A
) },
7060 { PREFIX_TABLE (PREFIX_0F383B
) },
7061 { PREFIX_TABLE (PREFIX_0F383C
) },
7062 { PREFIX_TABLE (PREFIX_0F383D
) },
7063 { PREFIX_TABLE (PREFIX_0F383E
) },
7064 { PREFIX_TABLE (PREFIX_0F383F
) },
7066 { PREFIX_TABLE (PREFIX_0F3840
) },
7067 { PREFIX_TABLE (PREFIX_0F3841
) },
7138 { PREFIX_TABLE (PREFIX_0F3880
) },
7139 { PREFIX_TABLE (PREFIX_0F3881
) },
7140 { PREFIX_TABLE (PREFIX_0F3882
) },
7219 { PREFIX_TABLE (PREFIX_0F38C8
) },
7220 { PREFIX_TABLE (PREFIX_0F38C9
) },
7221 { PREFIX_TABLE (PREFIX_0F38CA
) },
7222 { PREFIX_TABLE (PREFIX_0F38CB
) },
7223 { PREFIX_TABLE (PREFIX_0F38CC
) },
7224 { PREFIX_TABLE (PREFIX_0F38CD
) },
7226 { PREFIX_TABLE (PREFIX_0F38CF
) },
7240 { PREFIX_TABLE (PREFIX_0F38DB
) },
7241 { PREFIX_TABLE (PREFIX_0F38DC
) },
7242 { PREFIX_TABLE (PREFIX_0F38DD
) },
7243 { PREFIX_TABLE (PREFIX_0F38DE
) },
7244 { PREFIX_TABLE (PREFIX_0F38DF
) },
7264 { PREFIX_TABLE (PREFIX_0F38F0
) },
7265 { PREFIX_TABLE (PREFIX_0F38F1
) },
7269 { PREFIX_TABLE (PREFIX_0F38F5
) },
7270 { PREFIX_TABLE (PREFIX_0F38F6
) },
7273 { PREFIX_TABLE (PREFIX_0F38F8
) },
7274 { PREFIX_TABLE (PREFIX_0F38F9
) },
7282 /* THREE_BYTE_0F3A */
7294 { PREFIX_TABLE (PREFIX_0F3A08
) },
7295 { PREFIX_TABLE (PREFIX_0F3A09
) },
7296 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7297 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7298 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7299 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7300 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7301 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7307 { PREFIX_TABLE (PREFIX_0F3A14
) },
7308 { PREFIX_TABLE (PREFIX_0F3A15
) },
7309 { PREFIX_TABLE (PREFIX_0F3A16
) },
7310 { PREFIX_TABLE (PREFIX_0F3A17
) },
7321 { PREFIX_TABLE (PREFIX_0F3A20
) },
7322 { PREFIX_TABLE (PREFIX_0F3A21
) },
7323 { PREFIX_TABLE (PREFIX_0F3A22
) },
7357 { PREFIX_TABLE (PREFIX_0F3A40
) },
7358 { PREFIX_TABLE (PREFIX_0F3A41
) },
7359 { PREFIX_TABLE (PREFIX_0F3A42
) },
7361 { PREFIX_TABLE (PREFIX_0F3A44
) },
7393 { PREFIX_TABLE (PREFIX_0F3A60
) },
7394 { PREFIX_TABLE (PREFIX_0F3A61
) },
7395 { PREFIX_TABLE (PREFIX_0F3A62
) },
7396 { PREFIX_TABLE (PREFIX_0F3A63
) },
7514 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7516 { PREFIX_TABLE (PREFIX_0F3ACE
) },
7517 { PREFIX_TABLE (PREFIX_0F3ACF
) },
7535 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7575 static const struct dis386 xop_table
[][256] = {
7728 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7729 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7730 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7738 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7739 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7746 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7747 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7748 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7756 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7757 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7761 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7762 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7765 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7783 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7795 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
7796 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
7797 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
7798 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
7808 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7809 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7810 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7811 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7844 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7845 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7846 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7847 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
7871 { REG_TABLE (REG_XOP_TBM_01
) },
7872 { REG_TABLE (REG_XOP_TBM_02
) },
7890 { REG_TABLE (REG_XOP_LWPCB
) },
8014 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
8015 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
8016 { "vfrczss", { XM
, EXd
}, 0 },
8017 { "vfrczsd", { XM
, EXq
}, 0 },
8032 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8033 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8034 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8035 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8036 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8037 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8038 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8039 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8041 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8042 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8043 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8044 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8087 { "vphaddbw", { XM
, EXxmm
}, 0 },
8088 { "vphaddbd", { XM
, EXxmm
}, 0 },
8089 { "vphaddbq", { XM
, EXxmm
}, 0 },
8092 { "vphaddwd", { XM
, EXxmm
}, 0 },
8093 { "vphaddwq", { XM
, EXxmm
}, 0 },
8098 { "vphadddq", { XM
, EXxmm
}, 0 },
8105 { "vphaddubw", { XM
, EXxmm
}, 0 },
8106 { "vphaddubd", { XM
, EXxmm
}, 0 },
8107 { "vphaddubq", { XM
, EXxmm
}, 0 },
8110 { "vphadduwd", { XM
, EXxmm
}, 0 },
8111 { "vphadduwq", { XM
, EXxmm
}, 0 },
8116 { "vphaddudq", { XM
, EXxmm
}, 0 },
8123 { "vphsubbw", { XM
, EXxmm
}, 0 },
8124 { "vphsubwd", { XM
, EXxmm
}, 0 },
8125 { "vphsubdq", { XM
, EXxmm
}, 0 },
8179 { "bextrS", { Gdq
, Edq
, Id
}, 0 },
8181 { REG_TABLE (REG_XOP_LWP
) },
8451 static const struct dis386 vex_table
[][256] = {
8473 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8474 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8475 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8476 { MOD_TABLE (MOD_VEX_0F13
) },
8477 { "vunpcklpX", { XM
, Vex
, EXx
}, 0 },
8478 { "vunpckhpX", { XM
, Vex
, EXx
}, 0 },
8479 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8480 { MOD_TABLE (MOD_VEX_0F17
) },
8500 { "vmovapX", { XM
, EXx
}, 0 },
8501 { "vmovapX", { EXxS
, XM
}, 0 },
8502 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8503 { MOD_TABLE (MOD_VEX_0F2B
) },
8504 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8505 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8506 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8507 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8528 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8529 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8531 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8532 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8533 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8534 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8538 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8539 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8545 { MOD_TABLE (MOD_VEX_0F50
) },
8546 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8547 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8548 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8549 { "vandpX", { XM
, Vex
, EXx
}, 0 },
8550 { "vandnpX", { XM
, Vex
, EXx
}, 0 },
8551 { "vorpX", { XM
, Vex
, EXx
}, 0 },
8552 { "vxorpX", { XM
, Vex
, EXx
}, 0 },
8554 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8555 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8556 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8557 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8558 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8559 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8560 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8561 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8563 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8564 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8565 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8566 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8567 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8568 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8569 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8570 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8572 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8573 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8574 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8575 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8576 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8577 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8578 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8579 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8581 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8582 { REG_TABLE (REG_VEX_0F71
) },
8583 { REG_TABLE (REG_VEX_0F72
) },
8584 { REG_TABLE (REG_VEX_0F73
) },
8585 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8586 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8587 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8588 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8594 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8595 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8596 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8597 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8617 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8618 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8619 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8620 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8626 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8627 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8650 { REG_TABLE (REG_VEX_0FAE
) },
8673 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8675 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8676 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8677 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, 0 },
8689 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8690 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8691 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8692 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8693 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8694 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8695 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8696 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8698 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8699 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8700 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8701 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8702 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8703 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8704 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8705 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8707 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8708 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8709 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8710 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8711 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8712 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8713 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8714 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8716 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8717 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8718 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8719 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8720 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8721 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8722 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8723 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8725 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8726 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8727 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8728 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8729 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8730 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8731 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8732 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8734 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8735 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8736 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8737 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8738 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8739 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8740 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8746 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8747 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8748 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8749 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8750 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8751 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8752 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8753 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8755 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8756 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8758 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8759 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8760 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8762 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8767 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8770 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8771 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8774 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8775 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8777 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8779 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8782 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8783 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8784 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8785 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8786 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8787 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8791 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8792 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8793 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8794 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8795 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8796 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8797 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8798 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8800 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8801 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8802 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8803 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8804 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8805 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8806 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8807 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8809 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8810 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8811 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8812 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8813 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8814 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8815 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8816 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8818 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8819 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8823 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8824 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8825 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8845 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8846 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8847 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
8881 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
8882 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
8903 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
8905 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
8908 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
8909 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
8910 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
8911 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
8914 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
8917 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
8918 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
8919 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
8920 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
8921 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
8922 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
8923 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
8924 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
8932 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
8935 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
8936 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
8939 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
8940 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
8941 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
8942 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
8950 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
8951 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
8953 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
8954 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
8955 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
8956 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
8957 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
8958 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
8959 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
8960 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
8978 { PREFIX_TABLE (PREFIX_VEX_0F38CF
) },
8992 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
8993 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
8994 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
8995 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
8996 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
9018 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
9019 { REG_TABLE (REG_VEX_0F38F3
) },
9021 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
9022 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
9023 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
9037 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
9038 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
9039 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
9041 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
9042 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
9043 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
9046 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
9047 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9048 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9049 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9050 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9051 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9052 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9053 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9059 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9060 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9061 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9062 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9064 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9065 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9069 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9073 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9074 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9075 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9091 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9092 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9093 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9094 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9100 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9101 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9109 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9110 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9111 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9113 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9115 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9118 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9119 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9120 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9121 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9122 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9140 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9141 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9142 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9143 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9145 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9146 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9147 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9148 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9154 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9155 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9156 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9157 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9158 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9159 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9160 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9161 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9172 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9173 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9174 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9175 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9176 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9177 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9178 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9179 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9268 { PREFIX_TABLE(PREFIX_VEX_0F3ACE
) },
9269 { PREFIX_TABLE(PREFIX_VEX_0F3ACF
) },
9287 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9307 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9327 #include "i386-dis-evex.h"
9329 static const struct dis386 vex_len_table
[][2] = {
9330 /* VEX_LEN_0F12_P_0_M_0 */
9332 { "vmovlps", { XM
, Vex128
, EXq
}, 0 },
9335 /* VEX_LEN_0F12_P_0_M_1 */
9337 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
9340 /* VEX_LEN_0F12_P_2 */
9342 { "vmovlpd", { XM
, Vex128
, EXq
}, 0 },
9345 /* VEX_LEN_0F13_M_0 */
9347 { "vmovlpX", { EXq
, XM
}, 0 },
9350 /* VEX_LEN_0F16_P_0_M_0 */
9352 { "vmovhps", { XM
, Vex128
, EXq
}, 0 },
9355 /* VEX_LEN_0F16_P_0_M_1 */
9357 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
9360 /* VEX_LEN_0F16_P_2 */
9362 { "vmovhpd", { XM
, Vex128
, EXq
}, 0 },
9365 /* VEX_LEN_0F17_M_0 */
9367 { "vmovhpX", { EXq
, XM
}, 0 },
9370 /* VEX_LEN_0F41_P_0 */
9373 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9375 /* VEX_LEN_0F41_P_2 */
9378 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9380 /* VEX_LEN_0F42_P_0 */
9383 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9385 /* VEX_LEN_0F42_P_2 */
9388 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9390 /* VEX_LEN_0F44_P_0 */
9392 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9394 /* VEX_LEN_0F44_P_2 */
9396 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9398 /* VEX_LEN_0F45_P_0 */
9401 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9403 /* VEX_LEN_0F45_P_2 */
9406 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9408 /* VEX_LEN_0F46_P_0 */
9411 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9413 /* VEX_LEN_0F46_P_2 */
9416 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9418 /* VEX_LEN_0F47_P_0 */
9421 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9423 /* VEX_LEN_0F47_P_2 */
9426 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9428 /* VEX_LEN_0F4A_P_0 */
9431 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9433 /* VEX_LEN_0F4A_P_2 */
9436 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9438 /* VEX_LEN_0F4B_P_0 */
9441 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9443 /* VEX_LEN_0F4B_P_2 */
9446 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9449 /* VEX_LEN_0F6E_P_2 */
9451 { "vmovK", { XMScalar
, Edq
}, 0 },
9454 /* VEX_LEN_0F77_P_1 */
9456 { "vzeroupper", { XX
}, 0 },
9457 { "vzeroall", { XX
}, 0 },
9460 /* VEX_LEN_0F7E_P_1 */
9462 { "vmovq", { XMScalar
, EXqScalar
}, 0 },
9465 /* VEX_LEN_0F7E_P_2 */
9467 { "vmovK", { Edq
, XMScalar
}, 0 },
9470 /* VEX_LEN_0F90_P_0 */
9472 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9475 /* VEX_LEN_0F90_P_2 */
9477 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9480 /* VEX_LEN_0F91_P_0 */
9482 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9485 /* VEX_LEN_0F91_P_2 */
9487 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9490 /* VEX_LEN_0F92_P_0 */
9492 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9495 /* VEX_LEN_0F92_P_2 */
9497 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9500 /* VEX_LEN_0F92_P_3 */
9502 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0
) },
9505 /* VEX_LEN_0F93_P_0 */
9507 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9510 /* VEX_LEN_0F93_P_2 */
9512 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9515 /* VEX_LEN_0F93_P_3 */
9517 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0
) },
9520 /* VEX_LEN_0F98_P_0 */
9522 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9525 /* VEX_LEN_0F98_P_2 */
9527 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9530 /* VEX_LEN_0F99_P_0 */
9532 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9535 /* VEX_LEN_0F99_P_2 */
9537 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9540 /* VEX_LEN_0FAE_R_2_M_0 */
9542 { "vldmxcsr", { Md
}, 0 },
9545 /* VEX_LEN_0FAE_R_3_M_0 */
9547 { "vstmxcsr", { Md
}, 0 },
9550 /* VEX_LEN_0FC4_P_2 */
9552 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
9555 /* VEX_LEN_0FC5_P_2 */
9557 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
9560 /* VEX_LEN_0FD6_P_2 */
9562 { "vmovq", { EXqScalarS
, XMScalar
}, 0 },
9565 /* VEX_LEN_0FF7_P_2 */
9567 { "vmaskmovdqu", { XM
, XS
}, 0 },
9570 /* VEX_LEN_0F3816_P_2 */
9573 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9576 /* VEX_LEN_0F3819_P_2 */
9579 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9582 /* VEX_LEN_0F381A_P_2_M_0 */
9585 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9588 /* VEX_LEN_0F3836_P_2 */
9591 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9594 /* VEX_LEN_0F3841_P_2 */
9596 { "vphminposuw", { XM
, EXx
}, 0 },
9599 /* VEX_LEN_0F385A_P_2_M_0 */
9602 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9605 /* VEX_LEN_0F38DB_P_2 */
9607 { "vaesimc", { XM
, EXx
}, 0 },
9610 /* VEX_LEN_0F38F2_P_0 */
9612 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
9615 /* VEX_LEN_0F38F3_R_1_P_0 */
9617 { "blsrS", { VexGdq
, Edq
}, 0 },
9620 /* VEX_LEN_0F38F3_R_2_P_0 */
9622 { "blsmskS", { VexGdq
, Edq
}, 0 },
9625 /* VEX_LEN_0F38F3_R_3_P_0 */
9627 { "blsiS", { VexGdq
, Edq
}, 0 },
9630 /* VEX_LEN_0F38F5_P_0 */
9632 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
9635 /* VEX_LEN_0F38F5_P_1 */
9637 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
9640 /* VEX_LEN_0F38F5_P_3 */
9642 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
9645 /* VEX_LEN_0F38F6_P_3 */
9647 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
9650 /* VEX_LEN_0F38F7_P_0 */
9652 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
9655 /* VEX_LEN_0F38F7_P_1 */
9657 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
9660 /* VEX_LEN_0F38F7_P_2 */
9662 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
9665 /* VEX_LEN_0F38F7_P_3 */
9667 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
9670 /* VEX_LEN_0F3A00_P_2 */
9673 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
9676 /* VEX_LEN_0F3A01_P_2 */
9679 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
9682 /* VEX_LEN_0F3A06_P_2 */
9685 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
9688 /* VEX_LEN_0F3A14_P_2 */
9690 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
9693 /* VEX_LEN_0F3A15_P_2 */
9695 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
9698 /* VEX_LEN_0F3A16_P_2 */
9700 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
9703 /* VEX_LEN_0F3A17_P_2 */
9705 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
9708 /* VEX_LEN_0F3A18_P_2 */
9711 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
9714 /* VEX_LEN_0F3A19_P_2 */
9717 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
9720 /* VEX_LEN_0F3A20_P_2 */
9722 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
9725 /* VEX_LEN_0F3A21_P_2 */
9727 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
9730 /* VEX_LEN_0F3A22_P_2 */
9732 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
9735 /* VEX_LEN_0F3A30_P_2 */
9737 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
9740 /* VEX_LEN_0F3A31_P_2 */
9742 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
9745 /* VEX_LEN_0F3A32_P_2 */
9747 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
9750 /* VEX_LEN_0F3A33_P_2 */
9752 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
9755 /* VEX_LEN_0F3A38_P_2 */
9758 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
9761 /* VEX_LEN_0F3A39_P_2 */
9764 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
9767 /* VEX_LEN_0F3A41_P_2 */
9769 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
9772 /* VEX_LEN_0F3A46_P_2 */
9775 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
9778 /* VEX_LEN_0F3A60_P_2 */
9780 { "vpcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9783 /* VEX_LEN_0F3A61_P_2 */
9785 { "vpcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9788 /* VEX_LEN_0F3A62_P_2 */
9790 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
9793 /* VEX_LEN_0F3A63_P_2 */
9795 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
9798 /* VEX_LEN_0F3A6A_P_2 */
9800 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9803 /* VEX_LEN_0F3A6B_P_2 */
9805 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9808 /* VEX_LEN_0F3A6E_P_2 */
9810 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9813 /* VEX_LEN_0F3A6F_P_2 */
9815 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9818 /* VEX_LEN_0F3A7A_P_2 */
9820 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9823 /* VEX_LEN_0F3A7B_P_2 */
9825 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9828 /* VEX_LEN_0F3A7E_P_2 */
9830 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9833 /* VEX_LEN_0F3A7F_P_2 */
9835 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9838 /* VEX_LEN_0F3ADF_P_2 */
9840 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
9843 /* VEX_LEN_0F3AF0_P_3 */
9845 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
9848 /* VEX_LEN_0FXOP_08_CC */
9850 { "vpcomb", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9853 /* VEX_LEN_0FXOP_08_CD */
9855 { "vpcomw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9858 /* VEX_LEN_0FXOP_08_CE */
9860 { "vpcomd", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9863 /* VEX_LEN_0FXOP_08_CF */
9865 { "vpcomq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9868 /* VEX_LEN_0FXOP_08_EC */
9870 { "vpcomub", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9873 /* VEX_LEN_0FXOP_08_ED */
9875 { "vpcomuw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9878 /* VEX_LEN_0FXOP_08_EE */
9880 { "vpcomud", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9883 /* VEX_LEN_0FXOP_08_EF */
9885 { "vpcomuq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9888 /* VEX_LEN_0FXOP_09_80 */
9890 { "vfrczps", { XM
, EXxmm
}, 0 },
9891 { "vfrczps", { XM
, EXymmq
}, 0 },
9894 /* VEX_LEN_0FXOP_09_81 */
9896 { "vfrczpd", { XM
, EXxmm
}, 0 },
9897 { "vfrczpd", { XM
, EXymmq
}, 0 },
9901 #include "i386-dis-evex-len.h"
9903 static const struct dis386 vex_w_table
[][2] = {
9905 /* VEX_W_0F41_P_0_LEN_1 */
9906 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
9907 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
9910 /* VEX_W_0F41_P_2_LEN_1 */
9911 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
9912 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
9915 /* VEX_W_0F42_P_0_LEN_1 */
9916 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
9917 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
9920 /* VEX_W_0F42_P_2_LEN_1 */
9921 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
9922 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
9925 /* VEX_W_0F44_P_0_LEN_0 */
9926 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
9927 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
9930 /* VEX_W_0F44_P_2_LEN_0 */
9931 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
9932 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
9935 /* VEX_W_0F45_P_0_LEN_1 */
9936 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
9937 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
9940 /* VEX_W_0F45_P_2_LEN_1 */
9941 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
9942 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
9945 /* VEX_W_0F46_P_0_LEN_1 */
9946 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
9947 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
9950 /* VEX_W_0F46_P_2_LEN_1 */
9951 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
9952 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
9955 /* VEX_W_0F47_P_0_LEN_1 */
9956 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
9957 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
9960 /* VEX_W_0F47_P_2_LEN_1 */
9961 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
9962 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
9965 /* VEX_W_0F4A_P_0_LEN_1 */
9966 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
9967 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
9970 /* VEX_W_0F4A_P_2_LEN_1 */
9971 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
9972 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
9975 /* VEX_W_0F4B_P_0_LEN_1 */
9976 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
9977 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
9980 /* VEX_W_0F4B_P_2_LEN_1 */
9981 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
9984 /* VEX_W_0F90_P_0_LEN_0 */
9985 { "kmovw", { MaskG
, MaskE
}, 0 },
9986 { "kmovq", { MaskG
, MaskE
}, 0 },
9989 /* VEX_W_0F90_P_2_LEN_0 */
9990 { "kmovb", { MaskG
, MaskBDE
}, 0 },
9991 { "kmovd", { MaskG
, MaskBDE
}, 0 },
9994 /* VEX_W_0F91_P_0_LEN_0 */
9995 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
9996 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
9999 /* VEX_W_0F91_P_2_LEN_0 */
10000 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
10001 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
10004 /* VEX_W_0F92_P_0_LEN_0 */
10005 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
10008 /* VEX_W_0F92_P_2_LEN_0 */
10009 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
10012 /* VEX_W_0F93_P_0_LEN_0 */
10013 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
10016 /* VEX_W_0F93_P_2_LEN_0 */
10017 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
10020 /* VEX_W_0F98_P_0_LEN_0 */
10021 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
10022 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
10025 /* VEX_W_0F98_P_2_LEN_0 */
10026 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
10027 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
10030 /* VEX_W_0F99_P_0_LEN_0 */
10031 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
10032 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
10035 /* VEX_W_0F99_P_2_LEN_0 */
10036 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
10037 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
10040 /* VEX_W_0F380C_P_2 */
10041 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
10044 /* VEX_W_0F380D_P_2 */
10045 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
10048 /* VEX_W_0F380E_P_2 */
10049 { "vtestps", { XM
, EXx
}, 0 },
10052 /* VEX_W_0F380F_P_2 */
10053 { "vtestpd", { XM
, EXx
}, 0 },
10056 /* VEX_W_0F3816_P_2 */
10057 { "vpermps", { XM
, Vex
, EXx
}, 0 },
10060 /* VEX_W_0F3818_P_2 */
10061 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
10064 /* VEX_W_0F3819_P_2 */
10065 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
10068 /* VEX_W_0F381A_P_2_M_0 */
10069 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
10072 /* VEX_W_0F382C_P_2_M_0 */
10073 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
10076 /* VEX_W_0F382D_P_2_M_0 */
10077 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
10080 /* VEX_W_0F382E_P_2_M_0 */
10081 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
10084 /* VEX_W_0F382F_P_2_M_0 */
10085 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
10088 /* VEX_W_0F3836_P_2 */
10089 { "vpermd", { XM
, Vex
, EXx
}, 0 },
10092 /* VEX_W_0F3846_P_2 */
10093 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
10096 /* VEX_W_0F3858_P_2 */
10097 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
10100 /* VEX_W_0F3859_P_2 */
10101 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
10104 /* VEX_W_0F385A_P_2_M_0 */
10105 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
10108 /* VEX_W_0F3878_P_2 */
10109 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
10112 /* VEX_W_0F3879_P_2 */
10113 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
10116 /* VEX_W_0F38CF_P_2 */
10117 { "vgf2p8mulb", { XM
, Vex
, EXx
}, 0 },
10120 /* VEX_W_0F3A00_P_2 */
10122 { "vpermq", { XM
, EXx
, Ib
}, 0 },
10125 /* VEX_W_0F3A01_P_2 */
10127 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
10130 /* VEX_W_0F3A02_P_2 */
10131 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
10134 /* VEX_W_0F3A04_P_2 */
10135 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
10138 /* VEX_W_0F3A05_P_2 */
10139 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
10142 /* VEX_W_0F3A06_P_2 */
10143 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10146 /* VEX_W_0F3A18_P_2 */
10147 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10150 /* VEX_W_0F3A19_P_2 */
10151 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
10154 /* VEX_W_0F3A30_P_2_LEN_0 */
10155 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
10156 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
10159 /* VEX_W_0F3A31_P_2_LEN_0 */
10160 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
10161 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
10164 /* VEX_W_0F3A32_P_2_LEN_0 */
10165 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
10166 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
10169 /* VEX_W_0F3A33_P_2_LEN_0 */
10170 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
10171 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
10174 /* VEX_W_0F3A38_P_2 */
10175 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10178 /* VEX_W_0F3A39_P_2 */
10179 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
10182 /* VEX_W_0F3A46_P_2 */
10183 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10186 /* VEX_W_0F3A48_P_2 */
10187 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10188 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10191 /* VEX_W_0F3A49_P_2 */
10192 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10193 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10196 /* VEX_W_0F3A4A_P_2 */
10197 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10200 /* VEX_W_0F3A4B_P_2 */
10201 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10204 /* VEX_W_0F3A4C_P_2 */
10205 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10208 /* VEX_W_0F3ACE_P_2 */
10210 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10213 /* VEX_W_0F3ACF_P_2 */
10215 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10218 #include "i386-dis-evex-w.h"
10221 static const struct dis386 mod_table
[][2] = {
10224 { "leaS", { Gv
, M
}, 0 },
10229 { RM_TABLE (RM_C6_REG_7
) },
10234 { RM_TABLE (RM_C7_REG_7
) },
10238 { "Jcall^", { indirEp
}, 0 },
10242 { "Jjmp^", { indirEp
}, 0 },
10245 /* MOD_0F01_REG_0 */
10246 { X86_64_TABLE (X86_64_0F01_REG_0
) },
10247 { RM_TABLE (RM_0F01_REG_0
) },
10250 /* MOD_0F01_REG_1 */
10251 { X86_64_TABLE (X86_64_0F01_REG_1
) },
10252 { RM_TABLE (RM_0F01_REG_1
) },
10255 /* MOD_0F01_REG_2 */
10256 { X86_64_TABLE (X86_64_0F01_REG_2
) },
10257 { RM_TABLE (RM_0F01_REG_2
) },
10260 /* MOD_0F01_REG_3 */
10261 { X86_64_TABLE (X86_64_0F01_REG_3
) },
10262 { RM_TABLE (RM_0F01_REG_3
) },
10265 /* MOD_0F01_REG_5 */
10266 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0
) },
10267 { RM_TABLE (RM_0F01_REG_5_MOD_3
) },
10270 /* MOD_0F01_REG_7 */
10271 { "invlpg", { Mb
}, 0 },
10272 { RM_TABLE (RM_0F01_REG_7_MOD_3
) },
10275 /* MOD_0F12_PREFIX_0 */
10276 { "movlps", { XM
, EXq
}, PREFIX_OPCODE
},
10277 { "movhlps", { XM
, EXq
}, PREFIX_OPCODE
},
10281 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
10284 /* MOD_0F16_PREFIX_0 */
10285 { "movhps", { XM
, EXq
}, 0 },
10286 { "movlhps", { XM
, EXq
}, 0 },
10290 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
10293 /* MOD_0F18_REG_0 */
10294 { "prefetchnta", { Mb
}, 0 },
10297 /* MOD_0F18_REG_1 */
10298 { "prefetcht0", { Mb
}, 0 },
10301 /* MOD_0F18_REG_2 */
10302 { "prefetcht1", { Mb
}, 0 },
10305 /* MOD_0F18_REG_3 */
10306 { "prefetcht2", { Mb
}, 0 },
10309 /* MOD_0F18_REG_4 */
10310 { "nop/reserved", { Mb
}, 0 },
10313 /* MOD_0F18_REG_5 */
10314 { "nop/reserved", { Mb
}, 0 },
10317 /* MOD_0F18_REG_6 */
10318 { "nop/reserved", { Mb
}, 0 },
10321 /* MOD_0F18_REG_7 */
10322 { "nop/reserved", { Mb
}, 0 },
10325 /* MOD_0F1A_PREFIX_0 */
10326 { "bndldx", { Gbnd
, Mv_bnd
}, 0 },
10327 { "nopQ", { Ev
}, 0 },
10330 /* MOD_0F1B_PREFIX_0 */
10331 { "bndstx", { Mv_bnd
, Gbnd
}, 0 },
10332 { "nopQ", { Ev
}, 0 },
10335 /* MOD_0F1B_PREFIX_1 */
10336 { "bndmk", { Gbnd
, Mv_bnd
}, 0 },
10337 { "nopQ", { Ev
}, 0 },
10340 /* MOD_0F1C_PREFIX_0 */
10341 { REG_TABLE (REG_0F1C_P_0_MOD_0
) },
10342 { "nopQ", { Ev
}, 0 },
10345 /* MOD_0F1E_PREFIX_1 */
10346 { "nopQ", { Ev
}, 0 },
10347 { REG_TABLE (REG_0F1E_P_1_MOD_3
) },
10352 { "movL", { Rd
, Td
}, 0 },
10357 { "movL", { Td
, Rd
}, 0 },
10360 /* MOD_0F2B_PREFIX_0 */
10361 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
10364 /* MOD_0F2B_PREFIX_1 */
10365 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
10368 /* MOD_0F2B_PREFIX_2 */
10369 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
10372 /* MOD_0F2B_PREFIX_3 */
10373 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
10378 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
10381 /* MOD_0F71_REG_2 */
10383 { "psrlw", { MS
, Ib
}, 0 },
10386 /* MOD_0F71_REG_4 */
10388 { "psraw", { MS
, Ib
}, 0 },
10391 /* MOD_0F71_REG_6 */
10393 { "psllw", { MS
, Ib
}, 0 },
10396 /* MOD_0F72_REG_2 */
10398 { "psrld", { MS
, Ib
}, 0 },
10401 /* MOD_0F72_REG_4 */
10403 { "psrad", { MS
, Ib
}, 0 },
10406 /* MOD_0F72_REG_6 */
10408 { "pslld", { MS
, Ib
}, 0 },
10411 /* MOD_0F73_REG_2 */
10413 { "psrlq", { MS
, Ib
}, 0 },
10416 /* MOD_0F73_REG_3 */
10418 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
10421 /* MOD_0F73_REG_6 */
10423 { "psllq", { MS
, Ib
}, 0 },
10426 /* MOD_0F73_REG_7 */
10428 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
10431 /* MOD_0FAE_REG_0 */
10432 { "fxsave", { FXSAVE
}, 0 },
10433 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3
) },
10436 /* MOD_0FAE_REG_1 */
10437 { "fxrstor", { FXSAVE
}, 0 },
10438 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3
) },
10441 /* MOD_0FAE_REG_2 */
10442 { "ldmxcsr", { Md
}, 0 },
10443 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3
) },
10446 /* MOD_0FAE_REG_3 */
10447 { "stmxcsr", { Md
}, 0 },
10448 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3
) },
10451 /* MOD_0FAE_REG_4 */
10452 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0
) },
10453 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3
) },
10456 /* MOD_0FAE_REG_5 */
10457 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0
) },
10458 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3
) },
10461 /* MOD_0FAE_REG_6 */
10462 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0
) },
10463 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3
) },
10466 /* MOD_0FAE_REG_7 */
10467 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0
) },
10468 { RM_TABLE (RM_0FAE_REG_7_MOD_3
) },
10472 { "lssS", { Gv
, Mp
}, 0 },
10476 { "lfsS", { Gv
, Mp
}, 0 },
10480 { "lgsS", { Gv
, Mp
}, 0 },
10484 { PREFIX_TABLE (PREFIX_0FC3_MOD_0
) },
10487 /* MOD_0FC7_REG_3 */
10488 { "xrstors", { FXSAVE
}, 0 },
10491 /* MOD_0FC7_REG_4 */
10492 { "xsavec", { FXSAVE
}, 0 },
10495 /* MOD_0FC7_REG_5 */
10496 { "xsaves", { FXSAVE
}, 0 },
10499 /* MOD_0FC7_REG_6 */
10500 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0
) },
10501 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3
) }
10504 /* MOD_0FC7_REG_7 */
10505 { "vmptrst", { Mq
}, 0 },
10506 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3
) }
10511 { "pmovmskb", { Gdq
, MS
}, 0 },
10514 /* MOD_0FE7_PREFIX_2 */
10515 { "movntdq", { Mx
, XM
}, 0 },
10518 /* MOD_0FF0_PREFIX_3 */
10519 { "lddqu", { XM
, M
}, 0 },
10522 /* MOD_0F382A_PREFIX_2 */
10523 { "movntdqa", { XM
, Mx
}, 0 },
10526 /* MOD_0F38F5_PREFIX_2 */
10527 { "wrussK", { M
, Gdq
}, PREFIX_OPCODE
},
10530 /* MOD_0F38F6_PREFIX_0 */
10531 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
10534 /* MOD_0F38F8_PREFIX_1 */
10535 { "enqcmds", { Gva
, M
}, PREFIX_OPCODE
},
10538 /* MOD_0F38F8_PREFIX_2 */
10539 { "movdir64b", { Gva
, M
}, PREFIX_OPCODE
},
10542 /* MOD_0F38F8_PREFIX_3 */
10543 { "enqcmd", { Gva
, M
}, PREFIX_OPCODE
},
10546 /* MOD_0F38F9_PREFIX_0 */
10547 { "movdiri", { Ev
, Gv
}, PREFIX_OPCODE
},
10551 { "bound{S|}", { Gv
, Ma
}, 0 },
10552 { EVEX_TABLE (EVEX_0F
) },
10556 { "lesS", { Gv
, Mp
}, 0 },
10557 { VEX_C4_TABLE (VEX_0F
) },
10561 { "ldsS", { Gv
, Mp
}, 0 },
10562 { VEX_C5_TABLE (VEX_0F
) },
10565 /* MOD_VEX_0F12_PREFIX_0 */
10566 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
10567 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
10571 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
10574 /* MOD_VEX_0F16_PREFIX_0 */
10575 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
10576 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
10580 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
10584 { "vmovntpX", { Mx
, XM
}, 0 },
10587 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10589 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
10592 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10594 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
10597 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10599 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
10602 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10604 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
10607 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10609 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
10612 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10614 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
10617 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10619 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
10622 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10624 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
10627 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10629 { "knotw", { MaskG
, MaskR
}, 0 },
10632 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10634 { "knotq", { MaskG
, MaskR
}, 0 },
10637 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10639 { "knotb", { MaskG
, MaskR
}, 0 },
10642 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10644 { "knotd", { MaskG
, MaskR
}, 0 },
10647 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10649 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
10652 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10654 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
10657 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10659 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
10662 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10664 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
10667 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10669 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10672 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10674 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10677 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10679 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10682 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10684 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
10687 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10689 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10692 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10694 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10697 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10699 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10702 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10704 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
10707 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10709 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
10712 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10714 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
10717 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10719 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
10722 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10724 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
10727 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10729 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
10732 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10734 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
10737 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10739 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
10744 { "vmovmskpX", { Gdq
, XS
}, 0 },
10747 /* MOD_VEX_0F71_REG_2 */
10749 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
10752 /* MOD_VEX_0F71_REG_4 */
10754 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
10757 /* MOD_VEX_0F71_REG_6 */
10759 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
10762 /* MOD_VEX_0F72_REG_2 */
10764 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
10767 /* MOD_VEX_0F72_REG_4 */
10769 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
10772 /* MOD_VEX_0F72_REG_6 */
10774 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
10777 /* MOD_VEX_0F73_REG_2 */
10779 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
10782 /* MOD_VEX_0F73_REG_3 */
10784 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
10787 /* MOD_VEX_0F73_REG_6 */
10789 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
10792 /* MOD_VEX_0F73_REG_7 */
10794 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
10797 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10798 { "kmovw", { Ew
, MaskG
}, 0 },
10802 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10803 { "kmovq", { Eq
, MaskG
}, 0 },
10807 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10808 { "kmovb", { Eb
, MaskG
}, 0 },
10812 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10813 { "kmovd", { Ed
, MaskG
}, 0 },
10817 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10819 { "kmovw", { MaskG
, Rdq
}, 0 },
10822 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10824 { "kmovb", { MaskG
, Rdq
}, 0 },
10827 /* MOD_VEX_0F92_P_3_LEN_0 */
10829 { "kmovK", { MaskG
, Rdq
}, 0 },
10832 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10834 { "kmovw", { Gdq
, MaskR
}, 0 },
10837 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10839 { "kmovb", { Gdq
, MaskR
}, 0 },
10842 /* MOD_VEX_0F93_P_3_LEN_0 */
10844 { "kmovK", { Gdq
, MaskR
}, 0 },
10847 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10849 { "kortestw", { MaskG
, MaskR
}, 0 },
10852 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10854 { "kortestq", { MaskG
, MaskR
}, 0 },
10857 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10859 { "kortestb", { MaskG
, MaskR
}, 0 },
10862 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10864 { "kortestd", { MaskG
, MaskR
}, 0 },
10867 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10869 { "ktestw", { MaskG
, MaskR
}, 0 },
10872 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10874 { "ktestq", { MaskG
, MaskR
}, 0 },
10877 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10879 { "ktestb", { MaskG
, MaskR
}, 0 },
10882 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10884 { "ktestd", { MaskG
, MaskR
}, 0 },
10887 /* MOD_VEX_0FAE_REG_2 */
10888 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
10891 /* MOD_VEX_0FAE_REG_3 */
10892 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
10895 /* MOD_VEX_0FD7_PREFIX_2 */
10897 { "vpmovmskb", { Gdq
, XS
}, 0 },
10900 /* MOD_VEX_0FE7_PREFIX_2 */
10901 { "vmovntdq", { Mx
, XM
}, 0 },
10904 /* MOD_VEX_0FF0_PREFIX_3 */
10905 { "vlddqu", { XM
, M
}, 0 },
10908 /* MOD_VEX_0F381A_PREFIX_2 */
10909 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
10912 /* MOD_VEX_0F382A_PREFIX_2 */
10913 { "vmovntdqa", { XM
, Mx
}, 0 },
10916 /* MOD_VEX_0F382C_PREFIX_2 */
10917 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
10920 /* MOD_VEX_0F382D_PREFIX_2 */
10921 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
10924 /* MOD_VEX_0F382E_PREFIX_2 */
10925 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
10928 /* MOD_VEX_0F382F_PREFIX_2 */
10929 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
10932 /* MOD_VEX_0F385A_PREFIX_2 */
10933 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
10936 /* MOD_VEX_0F388C_PREFIX_2 */
10937 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
10940 /* MOD_VEX_0F388E_PREFIX_2 */
10941 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
10944 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10946 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
10949 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10951 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
10954 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10956 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
10959 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10961 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
10964 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10966 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
10969 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10971 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
10974 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10976 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
10979 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10981 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
10984 #include "i386-dis-evex-mod.h"
10987 static const struct dis386 rm_table
[][8] = {
10990 { "xabort", { Skip_MODRM
, Ib
}, 0 },
10994 { "xbeginT", { Skip_MODRM
, Jdqw
}, 0 },
10997 /* RM_0F01_REG_0 */
10998 { "enclv", { Skip_MODRM
}, 0 },
10999 { "vmcall", { Skip_MODRM
}, 0 },
11000 { "vmlaunch", { Skip_MODRM
}, 0 },
11001 { "vmresume", { Skip_MODRM
}, 0 },
11002 { "vmxoff", { Skip_MODRM
}, 0 },
11003 { "pconfig", { Skip_MODRM
}, 0 },
11006 /* RM_0F01_REG_1 */
11007 { "monitor", { { OP_Monitor
, 0 } }, 0 },
11008 { "mwait", { { OP_Mwait
, 0 } }, 0 },
11009 { "clac", { Skip_MODRM
}, 0 },
11010 { "stac", { Skip_MODRM
}, 0 },
11014 { "encls", { Skip_MODRM
}, 0 },
11017 /* RM_0F01_REG_2 */
11018 { "xgetbv", { Skip_MODRM
}, 0 },
11019 { "xsetbv", { Skip_MODRM
}, 0 },
11022 { "vmfunc", { Skip_MODRM
}, 0 },
11023 { "xend", { Skip_MODRM
}, 0 },
11024 { "xtest", { Skip_MODRM
}, 0 },
11025 { "enclu", { Skip_MODRM
}, 0 },
11028 /* RM_0F01_REG_3 */
11029 { "vmrun", { Skip_MODRM
}, 0 },
11030 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1
) },
11031 { "vmload", { Skip_MODRM
}, 0 },
11032 { "vmsave", { Skip_MODRM
}, 0 },
11033 { "stgi", { Skip_MODRM
}, 0 },
11034 { "clgi", { Skip_MODRM
}, 0 },
11035 { "skinit", { Skip_MODRM
}, 0 },
11036 { "invlpga", { Skip_MODRM
}, 0 },
11039 /* RM_0F01_REG_5_MOD_3 */
11040 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0
) },
11042 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2
) },
11046 { "rdpkru", { Skip_MODRM
}, 0 },
11047 { "wrpkru", { Skip_MODRM
}, 0 },
11050 /* RM_0F01_REG_7_MOD_3 */
11051 { "swapgs", { Skip_MODRM
}, 0 },
11052 { "rdtscp", { Skip_MODRM
}, 0 },
11053 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2
) },
11054 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3
) },
11055 { "clzero", { Skip_MODRM
}, 0 },
11056 { "rdpru", { Skip_MODRM
}, 0 },
11059 /* RM_0F1E_P_1_MOD_3_REG_7 */
11060 { "nopQ", { Ev
}, 0 },
11061 { "nopQ", { Ev
}, 0 },
11062 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
11063 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
11064 { "nopQ", { Ev
}, 0 },
11065 { "nopQ", { Ev
}, 0 },
11066 { "nopQ", { Ev
}, 0 },
11067 { "nopQ", { Ev
}, 0 },
11070 /* RM_0FAE_REG_6_MOD_3 */
11071 { "mfence", { Skip_MODRM
}, 0 },
11074 /* RM_0FAE_REG_7_MOD_3 */
11075 { "sfence", { Skip_MODRM
}, 0 },
11080 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11082 /* We use the high bit to indicate different name for the same
11084 #define REP_PREFIX (0xf3 | 0x100)
11085 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11086 #define XRELEASE_PREFIX (0xf3 | 0x400)
11087 #define BND_PREFIX (0xf2 | 0x400)
11088 #define NOTRACK_PREFIX (0x3e | 0x100)
11090 /* Remember if the current op is a jump instruction. */
11091 static bfd_boolean op_is_jump
= FALSE
;
11096 int newrex
, i
, length
;
11102 last_lock_prefix
= -1;
11103 last_repz_prefix
= -1;
11104 last_repnz_prefix
= -1;
11105 last_data_prefix
= -1;
11106 last_addr_prefix
= -1;
11107 last_rex_prefix
= -1;
11108 last_seg_prefix
= -1;
11110 active_seg_prefix
= 0;
11111 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11112 all_prefixes
[i
] = 0;
11115 /* The maximum instruction length is 15bytes. */
11116 while (length
< MAX_CODE_LENGTH
- 1)
11118 FETCH_DATA (the_info
, codep
+ 1);
11122 /* REX prefixes family. */
11139 if (address_mode
== mode_64bit
)
11143 last_rex_prefix
= i
;
11146 prefixes
|= PREFIX_REPZ
;
11147 last_repz_prefix
= i
;
11150 prefixes
|= PREFIX_REPNZ
;
11151 last_repnz_prefix
= i
;
11154 prefixes
|= PREFIX_LOCK
;
11155 last_lock_prefix
= i
;
11158 prefixes
|= PREFIX_CS
;
11159 last_seg_prefix
= i
;
11160 active_seg_prefix
= PREFIX_CS
;
11163 prefixes
|= PREFIX_SS
;
11164 last_seg_prefix
= i
;
11165 active_seg_prefix
= PREFIX_SS
;
11168 prefixes
|= PREFIX_DS
;
11169 last_seg_prefix
= i
;
11170 active_seg_prefix
= PREFIX_DS
;
11173 prefixes
|= PREFIX_ES
;
11174 last_seg_prefix
= i
;
11175 active_seg_prefix
= PREFIX_ES
;
11178 prefixes
|= PREFIX_FS
;
11179 last_seg_prefix
= i
;
11180 active_seg_prefix
= PREFIX_FS
;
11183 prefixes
|= PREFIX_GS
;
11184 last_seg_prefix
= i
;
11185 active_seg_prefix
= PREFIX_GS
;
11188 prefixes
|= PREFIX_DATA
;
11189 last_data_prefix
= i
;
11192 prefixes
|= PREFIX_ADDR
;
11193 last_addr_prefix
= i
;
11196 /* fwait is really an instruction. If there are prefixes
11197 before the fwait, they belong to the fwait, *not* to the
11198 following instruction. */
11200 if (prefixes
|| rex
)
11202 prefixes
|= PREFIX_FWAIT
;
11204 /* This ensures that the previous REX prefixes are noticed
11205 as unused prefixes, as in the return case below. */
11209 prefixes
= PREFIX_FWAIT
;
11214 /* Rex is ignored when followed by another prefix. */
11220 if (*codep
!= FWAIT_OPCODE
)
11221 all_prefixes
[i
++] = *codep
;
11229 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11232 static const char *
11233 prefix_name (int pref
, int sizeflag
)
11235 static const char *rexes
[16] =
11238 "rex.B", /* 0x41 */
11239 "rex.X", /* 0x42 */
11240 "rex.XB", /* 0x43 */
11241 "rex.R", /* 0x44 */
11242 "rex.RB", /* 0x45 */
11243 "rex.RX", /* 0x46 */
11244 "rex.RXB", /* 0x47 */
11245 "rex.W", /* 0x48 */
11246 "rex.WB", /* 0x49 */
11247 "rex.WX", /* 0x4a */
11248 "rex.WXB", /* 0x4b */
11249 "rex.WR", /* 0x4c */
11250 "rex.WRB", /* 0x4d */
11251 "rex.WRX", /* 0x4e */
11252 "rex.WRXB", /* 0x4f */
11257 /* REX prefixes family. */
11274 return rexes
[pref
- 0x40];
11294 return (sizeflag
& DFLAG
) ? "data16" : "data32";
11296 if (address_mode
== mode_64bit
)
11297 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
11299 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
11304 case XACQUIRE_PREFIX
:
11306 case XRELEASE_PREFIX
:
11310 case NOTRACK_PREFIX
:
11317 static char op_out
[MAX_OPERANDS
][100];
11318 static int op_ad
, op_index
[MAX_OPERANDS
];
11319 static int two_source_ops
;
11320 static bfd_vma op_address
[MAX_OPERANDS
];
11321 static bfd_vma op_riprel
[MAX_OPERANDS
];
11322 static bfd_vma start_pc
;
11325 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11326 * (see topic "Redundant prefixes" in the "Differences from 8086"
11327 * section of the "Virtual 8086 Mode" chapter.)
11328 * 'pc' should be the address of this instruction, it will
11329 * be used to print the target address if this is a relative jump or call
11330 * The function returns the length of this instruction in bytes.
11333 static char intel_syntax
;
11334 static char intel_mnemonic
= !SYSV386_COMPAT
;
11335 static char open_char
;
11336 static char close_char
;
11337 static char separator_char
;
11338 static char scale_char
;
11346 static enum x86_64_isa isa64
;
11348 /* Here for backwards compatibility. When gdb stops using
11349 print_insn_i386_att and print_insn_i386_intel these functions can
11350 disappear, and print_insn_i386 be merged into print_insn. */
11352 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
11356 return print_insn (pc
, info
);
11360 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
11364 return print_insn (pc
, info
);
11368 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
11372 return print_insn (pc
, info
);
11376 print_i386_disassembler_options (FILE *stream
)
11378 fprintf (stream
, _("\n\
11379 The following i386/x86-64 specific disassembler options are supported for use\n\
11380 with the -M switch (multiple options should be separated by commas):\n"));
11382 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
11383 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
11384 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
11385 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
11386 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
11387 fprintf (stream
, _(" att-mnemonic\n"
11388 " Display instruction in AT&T mnemonic\n"));
11389 fprintf (stream
, _(" intel-mnemonic\n"
11390 " Display instruction in Intel mnemonic\n"));
11391 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
11392 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
11393 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
11394 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
11395 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
11396 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11397 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
11398 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
11402 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
11404 /* Get a pointer to struct dis386 with a valid name. */
11406 static const struct dis386
*
11407 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
11409 int vindex
, vex_table_index
;
11411 if (dp
->name
!= NULL
)
11414 switch (dp
->op
[0].bytemode
)
11416 case USE_REG_TABLE
:
11417 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
11420 case USE_MOD_TABLE
:
11421 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
11422 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
11426 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
11429 case USE_PREFIX_TABLE
:
11432 /* The prefix in VEX is implicit. */
11433 switch (vex
.prefix
)
11438 case REPE_PREFIX_OPCODE
:
11441 case DATA_PREFIX_OPCODE
:
11444 case REPNE_PREFIX_OPCODE
:
11454 int last_prefix
= -1;
11457 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11458 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11460 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
11462 if (last_repz_prefix
> last_repnz_prefix
)
11465 prefix
= PREFIX_REPZ
;
11466 last_prefix
= last_repz_prefix
;
11471 prefix
= PREFIX_REPNZ
;
11472 last_prefix
= last_repnz_prefix
;
11475 /* Check if prefix should be ignored. */
11476 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
11477 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
11482 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
11485 prefix
= PREFIX_DATA
;
11486 last_prefix
= last_data_prefix
;
11491 used_prefixes
|= prefix
;
11492 all_prefixes
[last_prefix
] = 0;
11495 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
11498 case USE_X86_64_TABLE
:
11499 vindex
= address_mode
== mode_64bit
? 1 : 0;
11500 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
11503 case USE_3BYTE_TABLE
:
11504 FETCH_DATA (info
, codep
+ 2);
11506 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
11508 modrm
.mod
= (*codep
>> 6) & 3;
11509 modrm
.reg
= (*codep
>> 3) & 7;
11510 modrm
.rm
= *codep
& 7;
11513 case USE_VEX_LEN_TABLE
:
11517 switch (vex
.length
)
11530 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
11533 case USE_EVEX_LEN_TABLE
:
11537 switch (vex
.length
)
11553 dp
= &evex_len_table
[dp
->op
[1].bytemode
][vindex
];
11556 case USE_XOP_8F_TABLE
:
11557 FETCH_DATA (info
, codep
+ 3);
11558 /* All bits in the REX prefix are ignored. */
11560 rex
= ~(*codep
>> 5) & 0x7;
11562 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11563 switch ((*codep
& 0x1f))
11569 vex_table_index
= XOP_08
;
11572 vex_table_index
= XOP_09
;
11575 vex_table_index
= XOP_0A
;
11579 vex
.w
= *codep
& 0x80;
11580 if (vex
.w
&& address_mode
== mode_64bit
)
11583 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11584 if (address_mode
!= mode_64bit
)
11586 /* In 16/32-bit mode REX_B is silently ignored. */
11590 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11591 switch ((*codep
& 0x3))
11596 vex
.prefix
= DATA_PREFIX_OPCODE
;
11599 vex
.prefix
= REPE_PREFIX_OPCODE
;
11602 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11609 dp
= &xop_table
[vex_table_index
][vindex
];
11612 FETCH_DATA (info
, codep
+ 1);
11613 modrm
.mod
= (*codep
>> 6) & 3;
11614 modrm
.reg
= (*codep
>> 3) & 7;
11615 modrm
.rm
= *codep
& 7;
11618 case USE_VEX_C4_TABLE
:
11620 FETCH_DATA (info
, codep
+ 3);
11621 /* All bits in the REX prefix are ignored. */
11623 rex
= ~(*codep
>> 5) & 0x7;
11624 switch ((*codep
& 0x1f))
11630 vex_table_index
= VEX_0F
;
11633 vex_table_index
= VEX_0F38
;
11636 vex_table_index
= VEX_0F3A
;
11640 vex
.w
= *codep
& 0x80;
11641 if (address_mode
== mode_64bit
)
11648 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11649 is ignored, other REX bits are 0 and the highest bit in
11650 VEX.vvvv is also ignored (but we mustn't clear it here). */
11653 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11654 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11655 switch ((*codep
& 0x3))
11660 vex
.prefix
= DATA_PREFIX_OPCODE
;
11663 vex
.prefix
= REPE_PREFIX_OPCODE
;
11666 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11673 dp
= &vex_table
[vex_table_index
][vindex
];
11675 /* There is no MODRM byte for VEX0F 77. */
11676 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
11678 FETCH_DATA (info
, codep
+ 1);
11679 modrm
.mod
= (*codep
>> 6) & 3;
11680 modrm
.reg
= (*codep
>> 3) & 7;
11681 modrm
.rm
= *codep
& 7;
11685 case USE_VEX_C5_TABLE
:
11687 FETCH_DATA (info
, codep
+ 2);
11688 /* All bits in the REX prefix are ignored. */
11690 rex
= (*codep
& 0x80) ? 0 : REX_R
;
11692 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11694 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11695 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11696 switch ((*codep
& 0x3))
11701 vex
.prefix
= DATA_PREFIX_OPCODE
;
11704 vex
.prefix
= REPE_PREFIX_OPCODE
;
11707 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11714 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
11716 /* There is no MODRM byte for VEX 77. */
11717 if (vindex
!= 0x77)
11719 FETCH_DATA (info
, codep
+ 1);
11720 modrm
.mod
= (*codep
>> 6) & 3;
11721 modrm
.reg
= (*codep
>> 3) & 7;
11722 modrm
.rm
= *codep
& 7;
11726 case USE_VEX_W_TABLE
:
11730 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
11733 case USE_EVEX_TABLE
:
11734 two_source_ops
= 0;
11737 FETCH_DATA (info
, codep
+ 4);
11738 /* All bits in the REX prefix are ignored. */
11740 /* The first byte after 0x62. */
11741 rex
= ~(*codep
>> 5) & 0x7;
11742 vex
.r
= *codep
& 0x10;
11743 switch ((*codep
& 0xf))
11746 return &bad_opcode
;
11748 vex_table_index
= EVEX_0F
;
11751 vex_table_index
= EVEX_0F38
;
11754 vex_table_index
= EVEX_0F3A
;
11758 /* The second byte after 0x62. */
11760 vex
.w
= *codep
& 0x80;
11761 if (vex
.w
&& address_mode
== mode_64bit
)
11764 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11767 if (!(*codep
& 0x4))
11768 return &bad_opcode
;
11770 switch ((*codep
& 0x3))
11775 vex
.prefix
= DATA_PREFIX_OPCODE
;
11778 vex
.prefix
= REPE_PREFIX_OPCODE
;
11781 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11785 /* The third byte after 0x62. */
11788 /* Remember the static rounding bits. */
11789 vex
.ll
= (*codep
>> 5) & 3;
11790 vex
.b
= (*codep
& 0x10) != 0;
11792 vex
.v
= *codep
& 0x8;
11793 vex
.mask_register_specifier
= *codep
& 0x7;
11794 vex
.zeroing
= *codep
& 0x80;
11796 if (address_mode
!= mode_64bit
)
11798 /* In 16/32-bit mode silently ignore following bits. */
11808 dp
= &evex_table
[vex_table_index
][vindex
];
11810 FETCH_DATA (info
, codep
+ 1);
11811 modrm
.mod
= (*codep
>> 6) & 3;
11812 modrm
.reg
= (*codep
>> 3) & 7;
11813 modrm
.rm
= *codep
& 7;
11815 /* Set vector length. */
11816 if (modrm
.mod
== 3 && vex
.b
)
11832 return &bad_opcode
;
11845 if (dp
->name
!= NULL
)
11848 return get_valid_dis386 (dp
, info
);
11852 get_sib (disassemble_info
*info
, int sizeflag
)
11854 /* If modrm.mod == 3, operand must be register. */
11856 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11860 FETCH_DATA (info
, codep
+ 2);
11861 sib
.index
= (codep
[1] >> 3) & 7;
11862 sib
.scale
= (codep
[1] >> 6) & 3;
11863 sib
.base
= codep
[1] & 7;
11868 print_insn (bfd_vma pc
, disassemble_info
*info
)
11870 const struct dis386
*dp
;
11872 char *op_txt
[MAX_OPERANDS
];
11874 int sizeflag
, orig_sizeflag
;
11876 struct dis_private priv
;
11879 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11880 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
11881 address_mode
= mode_32bit
;
11882 else if (info
->mach
== bfd_mach_i386_i8086
)
11884 address_mode
= mode_16bit
;
11885 priv
.orig_sizeflag
= 0;
11888 address_mode
= mode_64bit
;
11890 if (intel_syntax
== (char) -1)
11891 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
11893 for (p
= info
->disassembler_options
; p
!= NULL
; )
11895 if (CONST_STRNEQ (p
, "amd64"))
11897 else if (CONST_STRNEQ (p
, "intel64"))
11899 else if (CONST_STRNEQ (p
, "x86-64"))
11901 address_mode
= mode_64bit
;
11902 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11904 else if (CONST_STRNEQ (p
, "i386"))
11906 address_mode
= mode_32bit
;
11907 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11909 else if (CONST_STRNEQ (p
, "i8086"))
11911 address_mode
= mode_16bit
;
11912 priv
.orig_sizeflag
= 0;
11914 else if (CONST_STRNEQ (p
, "intel"))
11917 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
11918 intel_mnemonic
= 1;
11920 else if (CONST_STRNEQ (p
, "att"))
11923 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
11924 intel_mnemonic
= 0;
11926 else if (CONST_STRNEQ (p
, "addr"))
11928 if (address_mode
== mode_64bit
)
11930 if (p
[4] == '3' && p
[5] == '2')
11931 priv
.orig_sizeflag
&= ~AFLAG
;
11932 else if (p
[4] == '6' && p
[5] == '4')
11933 priv
.orig_sizeflag
|= AFLAG
;
11937 if (p
[4] == '1' && p
[5] == '6')
11938 priv
.orig_sizeflag
&= ~AFLAG
;
11939 else if (p
[4] == '3' && p
[5] == '2')
11940 priv
.orig_sizeflag
|= AFLAG
;
11943 else if (CONST_STRNEQ (p
, "data"))
11945 if (p
[4] == '1' && p
[5] == '6')
11946 priv
.orig_sizeflag
&= ~DFLAG
;
11947 else if (p
[4] == '3' && p
[5] == '2')
11948 priv
.orig_sizeflag
|= DFLAG
;
11950 else if (CONST_STRNEQ (p
, "suffix"))
11951 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
11953 p
= strchr (p
, ',');
11958 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
11960 (*info
->fprintf_func
) (info
->stream
,
11961 _("64-bit address is disabled"));
11967 names64
= intel_names64
;
11968 names32
= intel_names32
;
11969 names16
= intel_names16
;
11970 names8
= intel_names8
;
11971 names8rex
= intel_names8rex
;
11972 names_seg
= intel_names_seg
;
11973 names_mm
= intel_names_mm
;
11974 names_bnd
= intel_names_bnd
;
11975 names_xmm
= intel_names_xmm
;
11976 names_ymm
= intel_names_ymm
;
11977 names_zmm
= intel_names_zmm
;
11978 index64
= intel_index64
;
11979 index32
= intel_index32
;
11980 names_mask
= intel_names_mask
;
11981 index16
= intel_index16
;
11984 separator_char
= '+';
11989 names64
= att_names64
;
11990 names32
= att_names32
;
11991 names16
= att_names16
;
11992 names8
= att_names8
;
11993 names8rex
= att_names8rex
;
11994 names_seg
= att_names_seg
;
11995 names_mm
= att_names_mm
;
11996 names_bnd
= att_names_bnd
;
11997 names_xmm
= att_names_xmm
;
11998 names_ymm
= att_names_ymm
;
11999 names_zmm
= att_names_zmm
;
12000 index64
= att_index64
;
12001 index32
= att_index32
;
12002 names_mask
= att_names_mask
;
12003 index16
= att_index16
;
12006 separator_char
= ',';
12010 /* The output looks better if we put 7 bytes on a line, since that
12011 puts most long word instructions on a single line. Use 8 bytes
12013 if ((info
->mach
& bfd_mach_l1om
) != 0)
12014 info
->bytes_per_line
= 8;
12016 info
->bytes_per_line
= 7;
12018 info
->private_data
= &priv
;
12019 priv
.max_fetched
= priv
.the_buffer
;
12020 priv
.insn_start
= pc
;
12023 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12031 start_codep
= priv
.the_buffer
;
12032 codep
= priv
.the_buffer
;
12034 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
12038 /* Getting here means we tried for data but didn't get it. That
12039 means we have an incomplete instruction of some sort. Just
12040 print the first byte as a prefix or a .byte pseudo-op. */
12041 if (codep
> priv
.the_buffer
)
12043 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
12045 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
12048 /* Just print the first byte as a .byte instruction. */
12049 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
12050 (unsigned int) priv
.the_buffer
[0]);
12060 sizeflag
= priv
.orig_sizeflag
;
12062 if (!ckprefix () || rex_used
)
12064 /* Too many prefixes or unused REX prefixes. */
12066 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
12068 (*info
->fprintf_func
) (info
->stream
, "%s%s",
12070 prefix_name (all_prefixes
[i
], sizeflag
));
12074 insn_codep
= codep
;
12076 FETCH_DATA (info
, codep
+ 1);
12077 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
12079 if (((prefixes
& PREFIX_FWAIT
)
12080 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
12082 /* Handle prefixes before fwait. */
12083 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
12085 (*info
->fprintf_func
) (info
->stream
, "%s ",
12086 prefix_name (all_prefixes
[i
], sizeflag
));
12087 (*info
->fprintf_func
) (info
->stream
, "fwait");
12091 if (*codep
== 0x0f)
12093 unsigned char threebyte
;
12096 FETCH_DATA (info
, codep
+ 1);
12097 threebyte
= *codep
;
12098 dp
= &dis386_twobyte
[threebyte
];
12099 need_modrm
= twobyte_has_modrm
[*codep
];
12104 dp
= &dis386
[*codep
];
12105 need_modrm
= onebyte_has_modrm
[*codep
];
12109 /* Save sizeflag for printing the extra prefixes later before updating
12110 it for mnemonic and operand processing. The prefix names depend
12111 only on the address mode. */
12112 orig_sizeflag
= sizeflag
;
12113 if (prefixes
& PREFIX_ADDR
)
12115 if ((prefixes
& PREFIX_DATA
))
12121 FETCH_DATA (info
, codep
+ 1);
12122 modrm
.mod
= (*codep
>> 6) & 3;
12123 modrm
.reg
= (*codep
>> 3) & 7;
12124 modrm
.rm
= *codep
& 7;
12130 memset (&vex
, 0, sizeof (vex
));
12132 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
12134 get_sib (info
, sizeflag
);
12135 dofloat (sizeflag
);
12139 dp
= get_valid_dis386 (dp
, info
);
12140 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
12142 get_sib (info
, sizeflag
);
12143 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12146 op_ad
= MAX_OPERANDS
- 1 - i
;
12148 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
12149 /* For EVEX instruction after the last operand masking
12150 should be printed. */
12151 if (i
== 0 && vex
.evex
)
12153 /* Don't print {%k0}. */
12154 if (vex
.mask_register_specifier
)
12157 oappend (names_mask
[vex
.mask_register_specifier
]);
12167 /* Clear instruction information. */
12170 the_info
->insn_info_valid
= 0;
12171 the_info
->branch_delay_insns
= 0;
12172 the_info
->data_size
= 0;
12173 the_info
->insn_type
= dis_noninsn
;
12174 the_info
->target
= 0;
12175 the_info
->target2
= 0;
12178 /* Reset jump operation indicator. */
12179 op_is_jump
= FALSE
;
12182 int jump_detection
= 0;
12184 /* Extract flags. */
12185 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12187 if ((dp
->op
[i
].rtn
== OP_J
)
12188 || (dp
->op
[i
].rtn
== OP_indirE
))
12189 jump_detection
|= 1;
12190 else if ((dp
->op
[i
].rtn
== BND_Fixup
)
12191 || (!dp
->op
[i
].rtn
&& !dp
->op
[i
].bytemode
))
12192 jump_detection
|= 2;
12193 else if ((dp
->op
[i
].bytemode
== cond_jump_mode
)
12194 || (dp
->op
[i
].bytemode
== loop_jcxz_mode
))
12195 jump_detection
|= 4;
12198 /* Determine if this is a jump or branch. */
12199 if ((jump_detection
& 0x3) == 0x3)
12202 if (jump_detection
& 0x4)
12203 the_info
->insn_type
= dis_condbranch
;
12205 the_info
->insn_type
=
12206 (dp
->name
&& !strncmp(dp
->name
, "call", 4))
12207 ? dis_jsr
: dis_branch
;
12211 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12212 are all 0s in inverted form. */
12213 if (need_vex
&& vex
.register_specifier
!= 0)
12215 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12216 return end_codep
- priv
.the_buffer
;
12219 /* Check if the REX prefix is used. */
12220 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
12221 all_prefixes
[last_rex_prefix
] = 0;
12223 /* Check if the SEG prefix is used. */
12224 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
12225 | PREFIX_FS
| PREFIX_GS
)) != 0
12226 && (used_prefixes
& active_seg_prefix
) != 0)
12227 all_prefixes
[last_seg_prefix
] = 0;
12229 /* Check if the ADDR prefix is used. */
12230 if ((prefixes
& PREFIX_ADDR
) != 0
12231 && (used_prefixes
& PREFIX_ADDR
) != 0)
12232 all_prefixes
[last_addr_prefix
] = 0;
12234 /* Check if the DATA prefix is used. */
12235 if ((prefixes
& PREFIX_DATA
) != 0
12236 && (used_prefixes
& PREFIX_DATA
) != 0)
12237 all_prefixes
[last_data_prefix
] = 0;
12239 /* Print the extra prefixes. */
12241 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12242 if (all_prefixes
[i
])
12245 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
12248 prefix_length
+= strlen (name
) + 1;
12249 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
12252 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12253 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
12254 used by putop and MMX/SSE operand and may be overriden by the
12255 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12257 if (dp
->prefix_requirement
== PREFIX_OPCODE
12258 && dp
!= &bad_opcode
12260 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
12262 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
12264 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
12266 && (used_prefixes
& PREFIX_DATA
) == 0))))
12268 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12269 return end_codep
- priv
.the_buffer
;
12272 /* Check maximum code length. */
12273 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
12275 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12276 return MAX_CODE_LENGTH
;
12279 obufp
= mnemonicendp
;
12280 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
12283 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
12285 /* The enter and bound instructions are printed with operands in the same
12286 order as the intel book; everything else is printed in reverse order. */
12287 if (intel_syntax
|| two_source_ops
)
12291 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12292 op_txt
[i
] = op_out
[i
];
12294 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
12295 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
12297 op_txt
[2] = op_out
[3];
12298 op_txt
[3] = op_out
[2];
12301 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
12303 op_ad
= op_index
[i
];
12304 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
12305 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
12306 riprel
= op_riprel
[i
];
12307 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
12308 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
12313 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12314 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
12318 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12322 (*info
->fprintf_func
) (info
->stream
, ",");
12323 if (op_index
[i
] != -1 && !op_riprel
[i
])
12325 bfd_vma target
= (bfd_vma
) op_address
[op_index
[i
]];
12327 if (the_info
&& op_is_jump
)
12329 the_info
->insn_info_valid
= 1;
12330 the_info
->branch_delay_insns
= 0;
12331 the_info
->data_size
= 0;
12332 the_info
->target
= target
;
12333 the_info
->target2
= 0;
12335 (*info
->print_address_func
) (target
, info
);
12338 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
12342 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12343 if (op_index
[i
] != -1 && op_riprel
[i
])
12345 (*info
->fprintf_func
) (info
->stream
, " # ");
12346 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
12347 + op_address
[op_index
[i
]]), info
);
12350 return codep
- priv
.the_buffer
;
12353 static const char *float_mem
[] = {
12428 static const unsigned char float_mem_mode
[] = {
12503 #define ST { OP_ST, 0 }
12504 #define STi { OP_STi, 0 }
12506 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12507 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12508 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12509 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12510 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12511 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12512 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12513 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12514 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12516 static const struct dis386 float_reg
[][8] = {
12519 { "fadd", { ST
, STi
}, 0 },
12520 { "fmul", { ST
, STi
}, 0 },
12521 { "fcom", { STi
}, 0 },
12522 { "fcomp", { STi
}, 0 },
12523 { "fsub", { ST
, STi
}, 0 },
12524 { "fsubr", { ST
, STi
}, 0 },
12525 { "fdiv", { ST
, STi
}, 0 },
12526 { "fdivr", { ST
, STi
}, 0 },
12530 { "fld", { STi
}, 0 },
12531 { "fxch", { STi
}, 0 },
12541 { "fcmovb", { ST
, STi
}, 0 },
12542 { "fcmove", { ST
, STi
}, 0 },
12543 { "fcmovbe",{ ST
, STi
}, 0 },
12544 { "fcmovu", { ST
, STi
}, 0 },
12552 { "fcmovnb",{ ST
, STi
}, 0 },
12553 { "fcmovne",{ ST
, STi
}, 0 },
12554 { "fcmovnbe",{ ST
, STi
}, 0 },
12555 { "fcmovnu",{ ST
, STi
}, 0 },
12557 { "fucomi", { ST
, STi
}, 0 },
12558 { "fcomi", { ST
, STi
}, 0 },
12563 { "fadd", { STi
, ST
}, 0 },
12564 { "fmul", { STi
, ST
}, 0 },
12567 { "fsub{!M|r}", { STi
, ST
}, 0 },
12568 { "fsub{M|}", { STi
, ST
}, 0 },
12569 { "fdiv{!M|r}", { STi
, ST
}, 0 },
12570 { "fdiv{M|}", { STi
, ST
}, 0 },
12574 { "ffree", { STi
}, 0 },
12576 { "fst", { STi
}, 0 },
12577 { "fstp", { STi
}, 0 },
12578 { "fucom", { STi
}, 0 },
12579 { "fucomp", { STi
}, 0 },
12585 { "faddp", { STi
, ST
}, 0 },
12586 { "fmulp", { STi
, ST
}, 0 },
12589 { "fsub{!M|r}p", { STi
, ST
}, 0 },
12590 { "fsub{M|}p", { STi
, ST
}, 0 },
12591 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
12592 { "fdiv{M|}p", { STi
, ST
}, 0 },
12596 { "ffreep", { STi
}, 0 },
12601 { "fucomip", { ST
, STi
}, 0 },
12602 { "fcomip", { ST
, STi
}, 0 },
12607 static char *fgrps
[][8] = {
12610 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12615 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12620 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12625 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12630 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12635 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12640 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12645 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12646 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12651 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12656 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12661 swap_operand (void)
12663 mnemonicendp
[0] = '.';
12664 mnemonicendp
[1] = 's';
12669 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
12670 int sizeflag ATTRIBUTE_UNUSED
)
12672 /* Skip mod/rm byte. */
12678 dofloat (int sizeflag
)
12680 const struct dis386
*dp
;
12681 unsigned char floatop
;
12683 floatop
= codep
[-1];
12685 if (modrm
.mod
!= 3)
12687 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
12689 putop (float_mem
[fp_indx
], sizeflag
);
12692 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
12695 /* Skip mod/rm byte. */
12699 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
12700 if (dp
->name
== NULL
)
12702 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
12704 /* Instruction fnstsw is only one with strange arg. */
12705 if (floatop
== 0xdf && codep
[-1] == 0xe0)
12706 strcpy (op_out
[0], names16
[0]);
12710 putop (dp
->name
, sizeflag
);
12715 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
12720 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
12724 /* Like oappend (below), but S is a string starting with '%'.
12725 In Intel syntax, the '%' is elided. */
12727 oappend_maybe_intel (const char *s
)
12729 oappend (s
+ intel_syntax
);
12733 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12735 oappend_maybe_intel ("%st");
12739 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12741 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
12742 oappend_maybe_intel (scratchbuf
);
12745 /* Capital letters in template are macros. */
12747 putop (const char *in_template
, int sizeflag
)
12752 unsigned int l
= 0, len
= 1;
12755 #define SAVE_LAST(c) \
12756 if (l < len && l < sizeof (last)) \
12761 for (p
= in_template
; *p
; p
++)
12777 while (*++p
!= '|')
12778 if (*p
== '}' || *p
== '\0')
12781 /* Fall through. */
12786 while (*++p
!= '}')
12797 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12801 if (l
== 0 && len
== 1)
12806 if (sizeflag
& SUFFIX_ALWAYS
)
12819 if (address_mode
== mode_64bit
12820 && !(prefixes
& PREFIX_ADDR
))
12831 if (intel_syntax
&& !alt
)
12833 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
12835 if (sizeflag
& DFLAG
)
12836 *obufp
++ = intel_syntax
? 'd' : 'l';
12838 *obufp
++ = intel_syntax
? 'w' : 's';
12839 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12843 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12846 if (modrm
.mod
== 3)
12852 if (sizeflag
& DFLAG
)
12853 *obufp
++ = intel_syntax
? 'd' : 'l';
12856 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12862 case 'E': /* For jcxz/jecxz */
12863 if (address_mode
== mode_64bit
)
12865 if (sizeflag
& AFLAG
)
12871 if (sizeflag
& AFLAG
)
12873 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12878 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
12880 if (sizeflag
& AFLAG
)
12881 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
12883 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
12884 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12888 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
12890 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12894 if (!(rex
& REX_W
))
12895 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12900 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
12901 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
12903 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
12906 if (prefixes
& PREFIX_DS
)
12925 if (l
!= 0 || len
!= 1)
12927 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
12932 if (!need_vex
|| !vex
.evex
)
12935 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
12937 switch (vex
.length
)
12955 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
12960 /* Fall through. */
12963 if (l
!= 0 || len
!= 1)
12971 if (sizeflag
& SUFFIX_ALWAYS
)
12975 if (intel_mnemonic
!= cond
)
12979 if ((prefixes
& PREFIX_FWAIT
) == 0)
12982 used_prefixes
|= PREFIX_FWAIT
;
12988 else if (intel_syntax
&& (sizeflag
& DFLAG
))
12992 if (!(rex
& REX_W
))
12993 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12997 && address_mode
== mode_64bit
12998 && isa64
== intel64
)
13003 /* Fall through. */
13006 && address_mode
== mode_64bit
13007 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13012 /* Fall through. */
13015 if (l
== 0 && len
== 1)
13020 if ((rex
& REX_W
) == 0
13021 && (prefixes
& PREFIX_DATA
))
13023 if ((sizeflag
& DFLAG
) == 0)
13025 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13029 if ((prefixes
& PREFIX_DATA
)
13031 || (sizeflag
& SUFFIX_ALWAYS
))
13038 if (sizeflag
& DFLAG
)
13042 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13048 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13054 if ((prefixes
& PREFIX_DATA
)
13056 || (sizeflag
& SUFFIX_ALWAYS
))
13063 if (sizeflag
& DFLAG
)
13064 *obufp
++ = intel_syntax
? 'd' : 'l';
13067 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13075 if (address_mode
== mode_64bit
13076 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13078 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13082 /* Fall through. */
13085 if (l
== 0 && len
== 1)
13088 if (intel_syntax
&& !alt
)
13091 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13097 if (sizeflag
& DFLAG
)
13098 *obufp
++ = intel_syntax
? 'd' : 'l';
13101 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13107 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13113 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
13128 else if (sizeflag
& DFLAG
)
13137 if (intel_syntax
&& !p
[1]
13138 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
13140 if (!(rex
& REX_W
))
13141 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13144 if (l
== 0 && len
== 1)
13148 if (address_mode
== mode_64bit
13149 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13151 if (sizeflag
& SUFFIX_ALWAYS
)
13173 /* Fall through. */
13176 if (l
== 0 && len
== 1)
13181 if (sizeflag
& SUFFIX_ALWAYS
)
13187 if (sizeflag
& DFLAG
)
13191 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13205 if (address_mode
== mode_64bit
13206 && !(prefixes
& PREFIX_ADDR
))
13217 if (l
!= 0 || len
!= 1)
13222 if (need_vex
&& vex
.prefix
)
13224 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
13231 if (prefixes
& PREFIX_DATA
)
13235 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13239 if (l
== 0 && len
== 1)
13243 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
13251 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
13253 switch (vex
.length
)
13269 if (l
== 0 && len
== 1)
13271 /* operand size flag for cwtl, cbtw */
13280 else if (sizeflag
& DFLAG
)
13284 if (!(rex
& REX_W
))
13285 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13292 && last
[0] != 'L'))
13299 if (last
[0] == 'X')
13300 *obufp
++ = vex
.w
? 'd': 's';
13302 *obufp
++ = vex
.w
? 'q': 'd';
13308 if (isa64
== intel64
&& (rex
& REX_W
))
13314 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13316 if (sizeflag
& DFLAG
)
13320 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13326 if (address_mode
== mode_64bit
13327 && (isa64
== intel64
13328 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
13330 else if ((prefixes
& PREFIX_DATA
))
13332 if (!(sizeflag
& DFLAG
))
13334 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13341 mnemonicendp
= obufp
;
13346 oappend (const char *s
)
13348 obufp
= stpcpy (obufp
, s
);
13354 /* Only print the active segment register. */
13355 if (!active_seg_prefix
)
13358 used_prefixes
|= active_seg_prefix
;
13359 switch (active_seg_prefix
)
13362 oappend_maybe_intel ("%cs:");
13365 oappend_maybe_intel ("%ds:");
13368 oappend_maybe_intel ("%ss:");
13371 oappend_maybe_intel ("%es:");
13374 oappend_maybe_intel ("%fs:");
13377 oappend_maybe_intel ("%gs:");
13385 OP_indirE (int bytemode
, int sizeflag
)
13389 OP_E (bytemode
, sizeflag
);
13393 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
13395 if (address_mode
== mode_64bit
)
13403 sprintf_vma (tmp
, disp
);
13404 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
13405 strcpy (buf
+ 2, tmp
+ i
);
13409 bfd_signed_vma v
= disp
;
13416 /* Check for possible overflow on 0x8000000000000000. */
13419 strcpy (buf
, "9223372036854775808");
13433 tmp
[28 - i
] = (v
% 10) + '0';
13437 strcpy (buf
, tmp
+ 29 - i
);
13443 sprintf (buf
, "0x%x", (unsigned int) disp
);
13445 sprintf (buf
, "%d", (int) disp
);
13449 /* Put DISP in BUF as signed hex number. */
13452 print_displacement (char *buf
, bfd_vma disp
)
13454 bfd_signed_vma val
= disp
;
13463 /* Check for possible overflow. */
13466 switch (address_mode
)
13469 strcpy (buf
+ j
, "0x8000000000000000");
13472 strcpy (buf
+ j
, "0x80000000");
13475 strcpy (buf
+ j
, "0x8000");
13485 sprintf_vma (tmp
, (bfd_vma
) val
);
13486 for (i
= 0; tmp
[i
] == '0'; i
++)
13488 if (tmp
[i
] == '\0')
13490 strcpy (buf
+ j
, tmp
+ i
);
13494 intel_operand_size (int bytemode
, int sizeflag
)
13498 && (bytemode
== x_mode
13499 || bytemode
== evex_half_bcst_xmmq_mode
))
13502 oappend ("QWORD PTR ");
13504 oappend ("DWORD PTR ");
13513 oappend ("BYTE PTR ");
13518 oappend ("WORD PTR ");
13521 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13523 oappend ("QWORD PTR ");
13526 /* Fall through. */
13528 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13530 oappend ("QWORD PTR ");
13533 /* Fall through. */
13539 oappend ("QWORD PTR ");
13542 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
13543 oappend ("DWORD PTR ");
13545 oappend ("WORD PTR ");
13546 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13550 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13552 oappend ("WORD PTR ");
13553 if (!(rex
& REX_W
))
13554 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13557 if (sizeflag
& DFLAG
)
13558 oappend ("QWORD PTR ");
13560 oappend ("DWORD PTR ");
13561 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13564 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
13565 oappend ("WORD PTR ");
13567 oappend ("DWORD PTR ");
13568 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13571 case d_scalar_mode
:
13572 case d_scalar_swap_mode
:
13575 oappend ("DWORD PTR ");
13578 case q_scalar_mode
:
13579 case q_scalar_swap_mode
:
13581 oappend ("QWORD PTR ");
13584 if (address_mode
== mode_64bit
)
13585 oappend ("QWORD PTR ");
13587 oappend ("DWORD PTR ");
13590 if (sizeflag
& DFLAG
)
13591 oappend ("FWORD PTR ");
13593 oappend ("DWORD PTR ");
13594 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13597 oappend ("TBYTE PTR ");
13601 case evex_x_gscat_mode
:
13602 case evex_x_nobcst_mode
:
13603 case b_scalar_mode
:
13604 case w_scalar_mode
:
13607 switch (vex
.length
)
13610 oappend ("XMMWORD PTR ");
13613 oappend ("YMMWORD PTR ");
13616 oappend ("ZMMWORD PTR ");
13623 oappend ("XMMWORD PTR ");
13626 oappend ("XMMWORD PTR ");
13629 oappend ("YMMWORD PTR ");
13632 case evex_half_bcst_xmmq_mode
:
13636 switch (vex
.length
)
13639 oappend ("QWORD PTR ");
13642 oappend ("XMMWORD PTR ");
13645 oappend ("YMMWORD PTR ");
13655 switch (vex
.length
)
13660 oappend ("BYTE PTR ");
13670 switch (vex
.length
)
13675 oappend ("WORD PTR ");
13685 switch (vex
.length
)
13690 oappend ("DWORD PTR ");
13700 switch (vex
.length
)
13705 oappend ("QWORD PTR ");
13715 switch (vex
.length
)
13718 oappend ("WORD PTR ");
13721 oappend ("DWORD PTR ");
13724 oappend ("QWORD PTR ");
13734 switch (vex
.length
)
13737 oappend ("DWORD PTR ");
13740 oappend ("QWORD PTR ");
13743 oappend ("XMMWORD PTR ");
13753 switch (vex
.length
)
13756 oappend ("QWORD PTR ");
13759 oappend ("YMMWORD PTR ");
13762 oappend ("ZMMWORD PTR ");
13772 switch (vex
.length
)
13776 oappend ("XMMWORD PTR ");
13783 oappend ("OWORD PTR ");
13785 case vex_scalar_w_dq_mode
:
13790 oappend ("QWORD PTR ");
13792 oappend ("DWORD PTR ");
13794 case vex_vsib_d_w_dq_mode
:
13795 case vex_vsib_q_w_dq_mode
:
13802 oappend ("QWORD PTR ");
13804 oappend ("DWORD PTR ");
13808 switch (vex
.length
)
13811 oappend ("XMMWORD PTR ");
13814 oappend ("YMMWORD PTR ");
13817 oappend ("ZMMWORD PTR ");
13824 case vex_vsib_q_w_d_mode
:
13825 case vex_vsib_d_w_d_mode
:
13826 if (!need_vex
|| !vex
.evex
)
13829 switch (vex
.length
)
13832 oappend ("QWORD PTR ");
13835 oappend ("XMMWORD PTR ");
13838 oappend ("YMMWORD PTR ");
13846 if (!need_vex
|| vex
.length
!= 128)
13849 oappend ("DWORD PTR ");
13851 oappend ("BYTE PTR ");
13857 oappend ("QWORD PTR ");
13859 oappend ("WORD PTR ");
13869 OP_E_register (int bytemode
, int sizeflag
)
13871 int reg
= modrm
.rm
;
13872 const char **names
;
13878 if ((sizeflag
& SUFFIX_ALWAYS
)
13879 && (bytemode
== b_swap_mode
13880 || bytemode
== bnd_swap_mode
13881 || bytemode
== v_swap_mode
))
13907 names
= address_mode
== mode_64bit
? names64
: names32
;
13910 case bnd_swap_mode
:
13919 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13924 /* Fall through. */
13926 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13932 /* Fall through. */
13944 if ((sizeflag
& DFLAG
)
13945 || (bytemode
!= v_mode
13946 && bytemode
!= v_swap_mode
))
13950 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13954 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
13958 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13961 names
= (address_mode
== mode_64bit
13962 ? names64
: names32
);
13963 if (!(prefixes
& PREFIX_ADDR
))
13964 names
= (address_mode
== mode_16bit
13965 ? names16
: names
);
13968 /* Remove "addr16/addr32". */
13969 all_prefixes
[last_addr_prefix
] = 0;
13970 names
= (address_mode
!= mode_32bit
13971 ? names32
: names16
);
13972 used_prefixes
|= PREFIX_ADDR
;
13982 names
= names_mask
;
13987 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13990 oappend (names
[reg
]);
13994 OP_E_memory (int bytemode
, int sizeflag
)
13997 int add
= (rex
& REX_B
) ? 8 : 0;
14003 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
14005 && bytemode
!= x_mode
14006 && bytemode
!= xmmq_mode
14007 && bytemode
!= evex_half_bcst_xmmq_mode
)
14023 if (address_mode
!= mode_64bit
)
14029 case vex_scalar_w_dq_mode
:
14030 case vex_vsib_d_w_dq_mode
:
14031 case vex_vsib_d_w_d_mode
:
14032 case vex_vsib_q_w_dq_mode
:
14033 case vex_vsib_q_w_d_mode
:
14034 case evex_x_gscat_mode
:
14035 shift
= vex
.w
? 3 : 2;
14038 case evex_half_bcst_xmmq_mode
:
14042 shift
= vex
.w
? 3 : 2;
14045 /* Fall through. */
14049 case evex_x_nobcst_mode
:
14051 switch (vex
.length
)
14074 case q_scalar_mode
:
14076 case q_scalar_swap_mode
:
14082 case d_scalar_mode
:
14084 case d_scalar_swap_mode
:
14087 case w_scalar_mode
:
14091 case b_scalar_mode
:
14098 /* Make necessary corrections to shift for modes that need it.
14099 For these modes we currently have shift 4, 5 or 6 depending on
14100 vex.length (it corresponds to xmmword, ymmword or zmmword
14101 operand). We might want to make it 3, 4 or 5 (e.g. for
14102 xmmq_mode). In case of broadcast enabled the corrections
14103 aren't needed, as element size is always 32 or 64 bits. */
14105 && (bytemode
== xmmq_mode
14106 || bytemode
== evex_half_bcst_xmmq_mode
))
14108 else if (bytemode
== xmmqd_mode
)
14110 else if (bytemode
== xmmdw_mode
)
14112 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
14120 intel_operand_size (bytemode
, sizeflag
);
14123 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14125 /* 32/64 bit address mode */
14135 int addr32flag
= !((sizeflag
& AFLAG
)
14136 || bytemode
== v_bnd_mode
14137 || bytemode
== v_bndmk_mode
14138 || bytemode
== bnd_mode
14139 || bytemode
== bnd_swap_mode
);
14140 const char **indexes64
= names64
;
14141 const char **indexes32
= names32
;
14151 vindex
= sib
.index
;
14157 case vex_vsib_d_w_dq_mode
:
14158 case vex_vsib_d_w_d_mode
:
14159 case vex_vsib_q_w_dq_mode
:
14160 case vex_vsib_q_w_d_mode
:
14170 switch (vex
.length
)
14173 indexes64
= indexes32
= names_xmm
;
14177 || bytemode
== vex_vsib_q_w_dq_mode
14178 || bytemode
== vex_vsib_q_w_d_mode
)
14179 indexes64
= indexes32
= names_ymm
;
14181 indexes64
= indexes32
= names_xmm
;
14185 || bytemode
== vex_vsib_q_w_dq_mode
14186 || bytemode
== vex_vsib_q_w_d_mode
)
14187 indexes64
= indexes32
= names_zmm
;
14189 indexes64
= indexes32
= names_ymm
;
14196 haveindex
= vindex
!= 4;
14203 rbase
= base
+ add
;
14211 if (address_mode
== mode_64bit
&& !havesib
)
14214 if (riprel
&& bytemode
== v_bndmk_mode
)
14222 FETCH_DATA (the_info
, codep
+ 1);
14224 if ((disp
& 0x80) != 0)
14226 if (vex
.evex
&& shift
> 0)
14239 && address_mode
!= mode_16bit
)
14241 if (address_mode
== mode_64bit
)
14243 /* Display eiz instead of addr32. */
14244 needindex
= addr32flag
;
14249 /* In 32-bit mode, we need index register to tell [offset]
14250 from [eiz*1 + offset]. */
14255 havedisp
= (havebase
14257 || (havesib
&& (haveindex
|| scale
!= 0)));
14260 if (modrm
.mod
!= 0 || base
== 5)
14262 if (havedisp
|| riprel
)
14263 print_displacement (scratchbuf
, disp
);
14265 print_operand_value (scratchbuf
, 1, disp
);
14266 oappend (scratchbuf
);
14270 oappend (!addr32flag
? "(%rip)" : "(%eip)");
14274 if ((havebase
|| haveindex
|| needindex
|| needaddr32
|| riprel
)
14275 && (address_mode
!= mode_64bit
14276 || ((bytemode
!= v_bnd_mode
)
14277 && (bytemode
!= v_bndmk_mode
)
14278 && (bytemode
!= bnd_mode
)
14279 && (bytemode
!= bnd_swap_mode
))))
14280 used_prefixes
|= PREFIX_ADDR
;
14282 if (havedisp
|| (intel_syntax
&& riprel
))
14284 *obufp
++ = open_char
;
14285 if (intel_syntax
&& riprel
)
14288 oappend (!addr32flag
? "rip" : "eip");
14292 oappend (address_mode
== mode_64bit
&& !addr32flag
14293 ? names64
[rbase
] : names32
[rbase
]);
14296 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14297 print index to tell base + index from base. */
14301 || (havebase
&& base
!= ESP_REG_NUM
))
14303 if (!intel_syntax
|| havebase
)
14305 *obufp
++ = separator_char
;
14309 oappend (address_mode
== mode_64bit
&& !addr32flag
14310 ? indexes64
[vindex
] : indexes32
[vindex
]);
14312 oappend (address_mode
== mode_64bit
&& !addr32flag
14313 ? index64
: index32
);
14315 *obufp
++ = scale_char
;
14317 sprintf (scratchbuf
, "%d", 1 << scale
);
14318 oappend (scratchbuf
);
14322 && (disp
|| modrm
.mod
!= 0 || base
== 5))
14324 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
14329 else if (modrm
.mod
!= 1 && disp
!= -disp
)
14333 disp
= - (bfd_signed_vma
) disp
;
14337 print_displacement (scratchbuf
, disp
);
14339 print_operand_value (scratchbuf
, 1, disp
);
14340 oappend (scratchbuf
);
14343 *obufp
++ = close_char
;
14346 else if (intel_syntax
)
14348 if (modrm
.mod
!= 0 || base
== 5)
14350 if (!active_seg_prefix
)
14352 oappend (names_seg
[ds_reg
- es_reg
]);
14355 print_operand_value (scratchbuf
, 1, disp
);
14356 oappend (scratchbuf
);
14360 else if (bytemode
== v_bnd_mode
14361 || bytemode
== v_bndmk_mode
14362 || bytemode
== bnd_mode
14363 || bytemode
== bnd_swap_mode
)
14370 /* 16 bit address mode */
14371 used_prefixes
|= prefixes
& PREFIX_ADDR
;
14378 if ((disp
& 0x8000) != 0)
14383 FETCH_DATA (the_info
, codep
+ 1);
14385 if ((disp
& 0x80) != 0)
14387 if (vex
.evex
&& shift
> 0)
14392 if ((disp
& 0x8000) != 0)
14398 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
14400 print_displacement (scratchbuf
, disp
);
14401 oappend (scratchbuf
);
14404 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
14406 *obufp
++ = open_char
;
14408 oappend (index16
[modrm
.rm
]);
14410 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
14412 if ((bfd_signed_vma
) disp
>= 0)
14417 else if (modrm
.mod
!= 1)
14421 disp
= - (bfd_signed_vma
) disp
;
14424 print_displacement (scratchbuf
, disp
);
14425 oappend (scratchbuf
);
14428 *obufp
++ = close_char
;
14431 else if (intel_syntax
)
14433 if (!active_seg_prefix
)
14435 oappend (names_seg
[ds_reg
- es_reg
]);
14438 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
14439 oappend (scratchbuf
);
14442 if (vex
.evex
&& vex
.b
14443 && (bytemode
== x_mode
14444 || bytemode
== xmmq_mode
14445 || bytemode
== evex_half_bcst_xmmq_mode
))
14448 || bytemode
== xmmq_mode
14449 || bytemode
== evex_half_bcst_xmmq_mode
)
14451 switch (vex
.length
)
14454 oappend ("{1to2}");
14457 oappend ("{1to4}");
14460 oappend ("{1to8}");
14468 switch (vex
.length
)
14471 oappend ("{1to4}");
14474 oappend ("{1to8}");
14477 oappend ("{1to16}");
14487 OP_E (int bytemode
, int sizeflag
)
14489 /* Skip mod/rm byte. */
14493 if (modrm
.mod
== 3)
14494 OP_E_register (bytemode
, sizeflag
);
14496 OP_E_memory (bytemode
, sizeflag
);
14500 OP_G (int bytemode
, int sizeflag
)
14503 const char **names
;
14512 oappend (names8rex
[modrm
.reg
+ add
]);
14514 oappend (names8
[modrm
.reg
+ add
]);
14517 oappend (names16
[modrm
.reg
+ add
]);
14522 oappend (names32
[modrm
.reg
+ add
]);
14525 oappend (names64
[modrm
.reg
+ add
]);
14528 if (modrm
.reg
> 0x3)
14533 oappend (names_bnd
[modrm
.reg
]);
14543 oappend (names64
[modrm
.reg
+ add
]);
14546 if ((sizeflag
& DFLAG
)
14547 || (bytemode
!= v_mode
&& bytemode
!= movsxd_mode
))
14548 oappend (names32
[modrm
.reg
+ add
]);
14550 oappend (names16
[modrm
.reg
+ add
]);
14551 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14555 names
= (address_mode
== mode_64bit
14556 ? names64
: names32
);
14557 if (!(prefixes
& PREFIX_ADDR
))
14559 if (address_mode
== mode_16bit
)
14564 /* Remove "addr16/addr32". */
14565 all_prefixes
[last_addr_prefix
] = 0;
14566 names
= (address_mode
!= mode_32bit
14567 ? names32
: names16
);
14568 used_prefixes
|= PREFIX_ADDR
;
14570 oappend (names
[modrm
.reg
+ add
]);
14573 if (address_mode
== mode_64bit
)
14574 oappend (names64
[modrm
.reg
+ add
]);
14576 oappend (names32
[modrm
.reg
+ add
]);
14580 if ((modrm
.reg
+ add
) > 0x7)
14585 oappend (names_mask
[modrm
.reg
+ add
]);
14588 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14601 FETCH_DATA (the_info
, codep
+ 8);
14602 a
= *codep
++ & 0xff;
14603 a
|= (*codep
++ & 0xff) << 8;
14604 a
|= (*codep
++ & 0xff) << 16;
14605 a
|= (*codep
++ & 0xffu
) << 24;
14606 b
= *codep
++ & 0xff;
14607 b
|= (*codep
++ & 0xff) << 8;
14608 b
|= (*codep
++ & 0xff) << 16;
14609 b
|= (*codep
++ & 0xffu
) << 24;
14610 x
= a
+ ((bfd_vma
) b
<< 32);
14618 static bfd_signed_vma
14621 bfd_signed_vma x
= 0;
14623 FETCH_DATA (the_info
, codep
+ 4);
14624 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14625 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14626 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14627 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14631 static bfd_signed_vma
14634 bfd_signed_vma x
= 0;
14636 FETCH_DATA (the_info
, codep
+ 4);
14637 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14638 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14639 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14640 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14642 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
14652 FETCH_DATA (the_info
, codep
+ 2);
14653 x
= *codep
++ & 0xff;
14654 x
|= (*codep
++ & 0xff) << 8;
14659 set_op (bfd_vma op
, int riprel
)
14661 op_index
[op_ad
] = op_ad
;
14662 if (address_mode
== mode_64bit
)
14664 op_address
[op_ad
] = op
;
14665 op_riprel
[op_ad
] = riprel
;
14669 /* Mask to get a 32-bit address. */
14670 op_address
[op_ad
] = op
& 0xffffffff;
14671 op_riprel
[op_ad
] = riprel
& 0xffffffff;
14676 OP_REG (int code
, int sizeflag
)
14683 case es_reg
: case ss_reg
: case cs_reg
:
14684 case ds_reg
: case fs_reg
: case gs_reg
:
14685 oappend (names_seg
[code
- es_reg
]);
14697 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14698 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14699 s
= names16
[code
- ax_reg
+ add
];
14701 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14702 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14705 s
= names8rex
[code
- al_reg
+ add
];
14707 s
= names8
[code
- al_reg
];
14709 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
14710 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
14711 if (address_mode
== mode_64bit
14712 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14714 s
= names64
[code
- rAX_reg
+ add
];
14717 code
+= eAX_reg
- rAX_reg
;
14718 /* Fall through. */
14719 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14720 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14723 s
= names64
[code
- eAX_reg
+ add
];
14726 if (sizeflag
& DFLAG
)
14727 s
= names32
[code
- eAX_reg
+ add
];
14729 s
= names16
[code
- eAX_reg
+ add
];
14730 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14734 s
= INTERNAL_DISASSEMBLER_ERROR
;
14741 OP_IMREG (int code
, int sizeflag
)
14753 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14754 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14755 s
= names16
[code
- ax_reg
];
14757 case es_reg
: case ss_reg
: case cs_reg
:
14758 case ds_reg
: case fs_reg
: case gs_reg
:
14759 s
= names_seg
[code
- es_reg
];
14761 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14762 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14765 s
= names8rex
[code
- al_reg
];
14767 s
= names8
[code
- al_reg
];
14769 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14770 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14773 s
= names64
[code
- eAX_reg
];
14776 if (sizeflag
& DFLAG
)
14777 s
= names32
[code
- eAX_reg
];
14779 s
= names16
[code
- eAX_reg
];
14780 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14783 case z_mode_ax_reg
:
14784 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14788 if (!(rex
& REX_W
))
14789 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14792 s
= INTERNAL_DISASSEMBLER_ERROR
;
14799 OP_I (int bytemode
, int sizeflag
)
14802 bfd_signed_vma mask
= -1;
14807 FETCH_DATA (the_info
, codep
+ 1);
14817 if (sizeflag
& DFLAG
)
14827 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14843 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14848 scratchbuf
[0] = '$';
14849 print_operand_value (scratchbuf
+ 1, 1, op
);
14850 oappend_maybe_intel (scratchbuf
);
14851 scratchbuf
[0] = '\0';
14855 OP_I64 (int bytemode
, int sizeflag
)
14857 if (bytemode
!= v_mode
|| address_mode
!= mode_64bit
|| !(rex
& REX_W
))
14859 OP_I (bytemode
, sizeflag
);
14865 scratchbuf
[0] = '$';
14866 print_operand_value (scratchbuf
+ 1, 1, get64 ());
14867 oappend_maybe_intel (scratchbuf
);
14868 scratchbuf
[0] = '\0';
14872 OP_sI (int bytemode
, int sizeflag
)
14880 FETCH_DATA (the_info
, codep
+ 1);
14882 if ((op
& 0x80) != 0)
14884 if (bytemode
== b_T_mode
)
14886 if (address_mode
!= mode_64bit
14887 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14889 /* The operand-size prefix is overridden by a REX prefix. */
14890 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14898 if (!(rex
& REX_W
))
14900 if (sizeflag
& DFLAG
)
14908 /* The operand-size prefix is overridden by a REX prefix. */
14909 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14915 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14919 scratchbuf
[0] = '$';
14920 print_operand_value (scratchbuf
+ 1, 1, op
);
14921 oappend_maybe_intel (scratchbuf
);
14925 OP_J (int bytemode
, int sizeflag
)
14929 bfd_vma segment
= 0;
14934 FETCH_DATA (the_info
, codep
+ 1);
14936 if ((disp
& 0x80) != 0)
14940 if (isa64
!= intel64
)
14943 if ((sizeflag
& DFLAG
)
14944 || (address_mode
== mode_64bit
14945 && ((isa64
== intel64
&& bytemode
!= dqw_mode
)
14946 || (rex
& REX_W
))))
14951 if ((disp
& 0x8000) != 0)
14953 /* In 16bit mode, address is wrapped around at 64k within
14954 the same segment. Otherwise, a data16 prefix on a jump
14955 instruction means that the pc is masked to 16 bits after
14956 the displacement is added! */
14958 if ((prefixes
& PREFIX_DATA
) == 0)
14959 segment
= ((start_pc
+ (codep
- start_codep
))
14960 & ~((bfd_vma
) 0xffff));
14962 if (address_mode
!= mode_64bit
14963 || (isa64
!= intel64
&& !(rex
& REX_W
)))
14964 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14967 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14970 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
14972 print_operand_value (scratchbuf
, 1, disp
);
14973 oappend (scratchbuf
);
14977 OP_SEG (int bytemode
, int sizeflag
)
14979 if (bytemode
== w_mode
)
14980 oappend (names_seg
[modrm
.reg
]);
14982 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
14986 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
14990 if (sizeflag
& DFLAG
)
15000 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15002 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
15004 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
15005 oappend (scratchbuf
);
15009 OP_OFF (int bytemode
, int sizeflag
)
15013 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
15014 intel_operand_size (bytemode
, sizeflag
);
15017 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15024 if (!active_seg_prefix
)
15026 oappend (names_seg
[ds_reg
- es_reg
]);
15030 print_operand_value (scratchbuf
, 1, off
);
15031 oappend (scratchbuf
);
15035 OP_OFF64 (int bytemode
, int sizeflag
)
15039 if (address_mode
!= mode_64bit
15040 || (prefixes
& PREFIX_ADDR
))
15042 OP_OFF (bytemode
, sizeflag
);
15046 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
15047 intel_operand_size (bytemode
, sizeflag
);
15054 if (!active_seg_prefix
)
15056 oappend (names_seg
[ds_reg
- es_reg
]);
15060 print_operand_value (scratchbuf
, 1, off
);
15061 oappend (scratchbuf
);
15065 ptr_reg (int code
, int sizeflag
)
15069 *obufp
++ = open_char
;
15070 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
15071 if (address_mode
== mode_64bit
)
15073 if (!(sizeflag
& AFLAG
))
15074 s
= names32
[code
- eAX_reg
];
15076 s
= names64
[code
- eAX_reg
];
15078 else if (sizeflag
& AFLAG
)
15079 s
= names32
[code
- eAX_reg
];
15081 s
= names16
[code
- eAX_reg
];
15083 *obufp
++ = close_char
;
15088 OP_ESreg (int code
, int sizeflag
)
15094 case 0x6d: /* insw/insl */
15095 intel_operand_size (z_mode
, sizeflag
);
15097 case 0xa5: /* movsw/movsl/movsq */
15098 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15099 case 0xab: /* stosw/stosl */
15100 case 0xaf: /* scasw/scasl */
15101 intel_operand_size (v_mode
, sizeflag
);
15104 intel_operand_size (b_mode
, sizeflag
);
15107 oappend_maybe_intel ("%es:");
15108 ptr_reg (code
, sizeflag
);
15112 OP_DSreg (int code
, int sizeflag
)
15118 case 0x6f: /* outsw/outsl */
15119 intel_operand_size (z_mode
, sizeflag
);
15121 case 0xa5: /* movsw/movsl/movsq */
15122 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15123 case 0xad: /* lodsw/lodsl/lodsq */
15124 intel_operand_size (v_mode
, sizeflag
);
15127 intel_operand_size (b_mode
, sizeflag
);
15130 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15131 default segment register DS is printed. */
15132 if (!active_seg_prefix
)
15133 active_seg_prefix
= PREFIX_DS
;
15135 ptr_reg (code
, sizeflag
);
15139 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15147 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
15149 all_prefixes
[last_lock_prefix
] = 0;
15150 used_prefixes
|= PREFIX_LOCK
;
15155 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
15156 oappend_maybe_intel (scratchbuf
);
15160 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15169 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
15171 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
15172 oappend (scratchbuf
);
15176 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15178 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
15179 oappend_maybe_intel (scratchbuf
);
15183 OP_R (int bytemode
, int sizeflag
)
15185 /* Skip mod/rm byte. */
15188 OP_E_register (bytemode
, sizeflag
);
15192 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15194 int reg
= modrm
.reg
;
15195 const char **names
;
15197 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15198 if (prefixes
& PREFIX_DATA
)
15207 oappend (names
[reg
]);
15211 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15213 int reg
= modrm
.reg
;
15214 const char **names
;
15226 && bytemode
!= xmm_mode
15227 && bytemode
!= xmmq_mode
15228 && bytemode
!= evex_half_bcst_xmmq_mode
15229 && bytemode
!= ymm_mode
15230 && bytemode
!= scalar_mode
)
15232 switch (vex
.length
)
15239 || (bytemode
!= vex_vsib_q_w_dq_mode
15240 && bytemode
!= vex_vsib_q_w_d_mode
))
15252 else if (bytemode
== xmmq_mode
15253 || bytemode
== evex_half_bcst_xmmq_mode
)
15255 switch (vex
.length
)
15268 else if (bytemode
== ymm_mode
)
15272 oappend (names
[reg
]);
15276 OP_EM (int bytemode
, int sizeflag
)
15279 const char **names
;
15281 if (modrm
.mod
!= 3)
15284 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
15286 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15287 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15289 OP_E (bytemode
, sizeflag
);
15293 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
15296 /* Skip mod/rm byte. */
15299 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15301 if (prefixes
& PREFIX_DATA
)
15310 oappend (names
[reg
]);
15313 /* cvt* are the only instructions in sse2 which have
15314 both SSE and MMX operands and also have 0x66 prefix
15315 in their opcode. 0x66 was originally used to differentiate
15316 between SSE and MMX instruction(operands). So we have to handle the
15317 cvt* separately using OP_EMC and OP_MXC */
15319 OP_EMC (int bytemode
, int sizeflag
)
15321 if (modrm
.mod
!= 3)
15323 if (intel_syntax
&& bytemode
== v_mode
)
15325 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15326 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15328 OP_E (bytemode
, sizeflag
);
15332 /* Skip mod/rm byte. */
15335 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15336 oappend (names_mm
[modrm
.rm
]);
15340 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15342 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15343 oappend (names_mm
[modrm
.reg
]);
15347 OP_EX (int bytemode
, int sizeflag
)
15350 const char **names
;
15352 /* Skip mod/rm byte. */
15356 if (modrm
.mod
!= 3)
15358 OP_E_memory (bytemode
, sizeflag
);
15373 if ((sizeflag
& SUFFIX_ALWAYS
)
15374 && (bytemode
== x_swap_mode
15375 || bytemode
== d_swap_mode
15376 || bytemode
== d_scalar_swap_mode
15377 || bytemode
== q_swap_mode
15378 || bytemode
== q_scalar_swap_mode
))
15382 && bytemode
!= xmm_mode
15383 && bytemode
!= xmmdw_mode
15384 && bytemode
!= xmmqd_mode
15385 && bytemode
!= xmm_mb_mode
15386 && bytemode
!= xmm_mw_mode
15387 && bytemode
!= xmm_md_mode
15388 && bytemode
!= xmm_mq_mode
15389 && bytemode
!= xmmq_mode
15390 && bytemode
!= evex_half_bcst_xmmq_mode
15391 && bytemode
!= ymm_mode
15392 && bytemode
!= d_scalar_mode
15393 && bytemode
!= d_scalar_swap_mode
15394 && bytemode
!= q_scalar_mode
15395 && bytemode
!= q_scalar_swap_mode
15396 && bytemode
!= vex_scalar_w_dq_mode
)
15398 switch (vex
.length
)
15413 else if (bytemode
== xmmq_mode
15414 || bytemode
== evex_half_bcst_xmmq_mode
)
15416 switch (vex
.length
)
15429 else if (bytemode
== ymm_mode
)
15433 oappend (names
[reg
]);
15437 OP_MS (int bytemode
, int sizeflag
)
15439 if (modrm
.mod
== 3)
15440 OP_EM (bytemode
, sizeflag
);
15446 OP_XS (int bytemode
, int sizeflag
)
15448 if (modrm
.mod
== 3)
15449 OP_EX (bytemode
, sizeflag
);
15455 OP_M (int bytemode
, int sizeflag
)
15457 if (modrm
.mod
== 3)
15458 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15461 OP_E (bytemode
, sizeflag
);
15465 OP_0f07 (int bytemode
, int sizeflag
)
15467 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
15470 OP_E (bytemode
, sizeflag
);
15473 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15474 32bit mode and "xchg %rax,%rax" in 64bit mode. */
15477 NOP_Fixup1 (int bytemode
, int sizeflag
)
15479 if ((prefixes
& PREFIX_DATA
) != 0
15482 && address_mode
== mode_64bit
))
15483 OP_REG (bytemode
, sizeflag
);
15485 strcpy (obuf
, "nop");
15489 NOP_Fixup2 (int bytemode
, int sizeflag
)
15491 if ((prefixes
& PREFIX_DATA
) != 0
15494 && address_mode
== mode_64bit
))
15495 OP_IMREG (bytemode
, sizeflag
);
15498 static const char *const Suffix3DNow
[] = {
15499 /* 00 */ NULL
, NULL
, NULL
, NULL
,
15500 /* 04 */ NULL
, NULL
, NULL
, NULL
,
15501 /* 08 */ NULL
, NULL
, NULL
, NULL
,
15502 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
15503 /* 10 */ NULL
, NULL
, NULL
, NULL
,
15504 /* 14 */ NULL
, NULL
, NULL
, NULL
,
15505 /* 18 */ NULL
, NULL
, NULL
, NULL
,
15506 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
15507 /* 20 */ NULL
, NULL
, NULL
, NULL
,
15508 /* 24 */ NULL
, NULL
, NULL
, NULL
,
15509 /* 28 */ NULL
, NULL
, NULL
, NULL
,
15510 /* 2C */ NULL
, NULL
, NULL
, NULL
,
15511 /* 30 */ NULL
, NULL
, NULL
, NULL
,
15512 /* 34 */ NULL
, NULL
, NULL
, NULL
,
15513 /* 38 */ NULL
, NULL
, NULL
, NULL
,
15514 /* 3C */ NULL
, NULL
, NULL
, NULL
,
15515 /* 40 */ NULL
, NULL
, NULL
, NULL
,
15516 /* 44 */ NULL
, NULL
, NULL
, NULL
,
15517 /* 48 */ NULL
, NULL
, NULL
, NULL
,
15518 /* 4C */ NULL
, NULL
, NULL
, NULL
,
15519 /* 50 */ NULL
, NULL
, NULL
, NULL
,
15520 /* 54 */ NULL
, NULL
, NULL
, NULL
,
15521 /* 58 */ NULL
, NULL
, NULL
, NULL
,
15522 /* 5C */ NULL
, NULL
, NULL
, NULL
,
15523 /* 60 */ NULL
, NULL
, NULL
, NULL
,
15524 /* 64 */ NULL
, NULL
, NULL
, NULL
,
15525 /* 68 */ NULL
, NULL
, NULL
, NULL
,
15526 /* 6C */ NULL
, NULL
, NULL
, NULL
,
15527 /* 70 */ NULL
, NULL
, NULL
, NULL
,
15528 /* 74 */ NULL
, NULL
, NULL
, NULL
,
15529 /* 78 */ NULL
, NULL
, NULL
, NULL
,
15530 /* 7C */ NULL
, NULL
, NULL
, NULL
,
15531 /* 80 */ NULL
, NULL
, NULL
, NULL
,
15532 /* 84 */ NULL
, NULL
, NULL
, NULL
,
15533 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
15534 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
15535 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
15536 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
15537 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
15538 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
15539 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
15540 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
15541 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
15542 /* AC */ NULL
, NULL
, "pfacc", NULL
,
15543 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
15544 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
15545 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
15546 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
15547 /* C0 */ NULL
, NULL
, NULL
, NULL
,
15548 /* C4 */ NULL
, NULL
, NULL
, NULL
,
15549 /* C8 */ NULL
, NULL
, NULL
, NULL
,
15550 /* CC */ NULL
, NULL
, NULL
, NULL
,
15551 /* D0 */ NULL
, NULL
, NULL
, NULL
,
15552 /* D4 */ NULL
, NULL
, NULL
, NULL
,
15553 /* D8 */ NULL
, NULL
, NULL
, NULL
,
15554 /* DC */ NULL
, NULL
, NULL
, NULL
,
15555 /* E0 */ NULL
, NULL
, NULL
, NULL
,
15556 /* E4 */ NULL
, NULL
, NULL
, NULL
,
15557 /* E8 */ NULL
, NULL
, NULL
, NULL
,
15558 /* EC */ NULL
, NULL
, NULL
, NULL
,
15559 /* F0 */ NULL
, NULL
, NULL
, NULL
,
15560 /* F4 */ NULL
, NULL
, NULL
, NULL
,
15561 /* F8 */ NULL
, NULL
, NULL
, NULL
,
15562 /* FC */ NULL
, NULL
, NULL
, NULL
,
15566 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15568 const char *mnemonic
;
15570 FETCH_DATA (the_info
, codep
+ 1);
15571 /* AMD 3DNow! instructions are specified by an opcode suffix in the
15572 place where an 8-bit immediate would normally go. ie. the last
15573 byte of the instruction. */
15574 obufp
= mnemonicendp
;
15575 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
15577 oappend (mnemonic
);
15580 /* Since a variable sized modrm/sib chunk is between the start
15581 of the opcode (0x0f0f) and the opcode suffix, we need to do
15582 all the modrm processing first, and don't know until now that
15583 we have a bad opcode. This necessitates some cleaning up. */
15584 op_out
[0][0] = '\0';
15585 op_out
[1][0] = '\0';
15588 mnemonicendp
= obufp
;
15591 static struct op simd_cmp_op
[] =
15593 { STRING_COMMA_LEN ("eq") },
15594 { STRING_COMMA_LEN ("lt") },
15595 { STRING_COMMA_LEN ("le") },
15596 { STRING_COMMA_LEN ("unord") },
15597 { STRING_COMMA_LEN ("neq") },
15598 { STRING_COMMA_LEN ("nlt") },
15599 { STRING_COMMA_LEN ("nle") },
15600 { STRING_COMMA_LEN ("ord") }
15604 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15606 unsigned int cmp_type
;
15608 FETCH_DATA (the_info
, codep
+ 1);
15609 cmp_type
= *codep
++ & 0xff;
15610 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
15613 char *p
= mnemonicendp
- 2;
15617 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
15618 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
15622 /* We have a reserved extension byte. Output it directly. */
15623 scratchbuf
[0] = '$';
15624 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
15625 oappend_maybe_intel (scratchbuf
);
15626 scratchbuf
[0] = '\0';
15631 OP_Mwait (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15633 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
15636 strcpy (op_out
[0], names32
[0]);
15637 strcpy (op_out
[1], names32
[1]);
15638 if (bytemode
== eBX_reg
)
15639 strcpy (op_out
[2], names32
[3]);
15640 two_source_ops
= 1;
15642 /* Skip mod/rm byte. */
15648 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
15649 int sizeflag ATTRIBUTE_UNUSED
)
15651 /* monitor %{e,r,}ax,%ecx,%edx" */
15654 const char **names
= (address_mode
== mode_64bit
15655 ? names64
: names32
);
15657 if (prefixes
& PREFIX_ADDR
)
15659 /* Remove "addr16/addr32". */
15660 all_prefixes
[last_addr_prefix
] = 0;
15661 names
= (address_mode
!= mode_32bit
15662 ? names32
: names16
);
15663 used_prefixes
|= PREFIX_ADDR
;
15665 else if (address_mode
== mode_16bit
)
15667 strcpy (op_out
[0], names
[0]);
15668 strcpy (op_out
[1], names32
[1]);
15669 strcpy (op_out
[2], names32
[2]);
15670 two_source_ops
= 1;
15672 /* Skip mod/rm byte. */
15680 /* Throw away prefixes and 1st. opcode byte. */
15681 codep
= insn_codep
+ 1;
15686 REP_Fixup (int bytemode
, int sizeflag
)
15688 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15690 if (prefixes
& PREFIX_REPZ
)
15691 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
15698 OP_IMREG (bytemode
, sizeflag
);
15701 OP_ESreg (bytemode
, sizeflag
);
15704 OP_DSreg (bytemode
, sizeflag
);
15713 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15715 if ( isa64
!= amd64
)
15720 mnemonicendp
= obufp
;
15724 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15728 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15730 if (prefixes
& PREFIX_REPNZ
)
15731 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
15734 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15738 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
15739 int sizeflag ATTRIBUTE_UNUSED
)
15741 if (active_seg_prefix
== PREFIX_DS
15742 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
15744 /* NOTRACK prefix is only valid on indirect branch instructions.
15745 NB: DATA prefix is unsupported for Intel64. */
15746 active_seg_prefix
= 0;
15747 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
15751 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15752 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15756 HLE_Fixup1 (int bytemode
, int sizeflag
)
15759 && (prefixes
& PREFIX_LOCK
) != 0)
15761 if (prefixes
& PREFIX_REPZ
)
15762 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15763 if (prefixes
& PREFIX_REPNZ
)
15764 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15767 OP_E (bytemode
, sizeflag
);
15770 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15771 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
15775 HLE_Fixup2 (int bytemode
, int sizeflag
)
15777 if (modrm
.mod
!= 3)
15779 if (prefixes
& PREFIX_REPZ
)
15780 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15781 if (prefixes
& PREFIX_REPNZ
)
15782 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15785 OP_E (bytemode
, sizeflag
);
15788 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
15789 "xrelease" for memory operand. No check for LOCK prefix. */
15792 HLE_Fixup3 (int bytemode
, int sizeflag
)
15795 && last_repz_prefix
> last_repnz_prefix
15796 && (prefixes
& PREFIX_REPZ
) != 0)
15797 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15799 OP_E (bytemode
, sizeflag
);
15803 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
15808 /* Change cmpxchg8b to cmpxchg16b. */
15809 char *p
= mnemonicendp
- 2;
15810 mnemonicendp
= stpcpy (p
, "16b");
15813 else if ((prefixes
& PREFIX_LOCK
) != 0)
15815 if (prefixes
& PREFIX_REPZ
)
15816 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15817 if (prefixes
& PREFIX_REPNZ
)
15818 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15821 OP_M (bytemode
, sizeflag
);
15825 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
15827 const char **names
;
15831 switch (vex
.length
)
15845 oappend (names
[reg
]);
15849 CRC32_Fixup (int bytemode
, int sizeflag
)
15851 /* Add proper suffix to "crc32". */
15852 char *p
= mnemonicendp
;
15871 if (sizeflag
& DFLAG
)
15875 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15879 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15886 if (modrm
.mod
== 3)
15890 /* Skip mod/rm byte. */
15895 add
= (rex
& REX_B
) ? 8 : 0;
15896 if (bytemode
== b_mode
)
15900 oappend (names8rex
[modrm
.rm
+ add
]);
15902 oappend (names8
[modrm
.rm
+ add
]);
15908 oappend (names64
[modrm
.rm
+ add
]);
15909 else if ((prefixes
& PREFIX_DATA
))
15910 oappend (names16
[modrm
.rm
+ add
]);
15912 oappend (names32
[modrm
.rm
+ add
]);
15916 OP_E (bytemode
, sizeflag
);
15920 FXSAVE_Fixup (int bytemode
, int sizeflag
)
15922 /* Add proper suffix to "fxsave" and "fxrstor". */
15926 char *p
= mnemonicendp
;
15932 OP_M (bytemode
, sizeflag
);
15936 PCMPESTR_Fixup (int bytemode
, int sizeflag
)
15938 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
15941 char *p
= mnemonicendp
;
15946 else if (sizeflag
& SUFFIX_ALWAYS
)
15953 OP_EX (bytemode
, sizeflag
);
15956 /* Display the destination register operand for instructions with
15960 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15963 const char **names
;
15971 reg
= vex
.register_specifier
;
15972 vex
.register_specifier
= 0;
15973 if (address_mode
!= mode_64bit
)
15975 else if (vex
.evex
&& !vex
.v
)
15978 if (bytemode
== vex_scalar_mode
)
15980 oappend (names_xmm
[reg
]);
15984 switch (vex
.length
)
15991 case vex_vsib_q_w_dq_mode
:
15992 case vex_vsib_q_w_d_mode
:
16008 names
= names_mask
;
16022 case vex_vsib_q_w_dq_mode
:
16023 case vex_vsib_q_w_d_mode
:
16024 names
= vex
.w
? names_ymm
: names_xmm
;
16033 names
= names_mask
;
16036 /* See PR binutils/20893 for a reproducer. */
16048 oappend (names
[reg
]);
16051 /* Get the VEX immediate byte without moving codep. */
16053 static unsigned char
16054 get_vex_imm8 (int sizeflag
, int opnum
)
16056 int bytes_before_imm
= 0;
16058 if (modrm
.mod
!= 3)
16060 /* There are SIB/displacement bytes. */
16061 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
16063 /* 32/64 bit address mode */
16064 int base
= modrm
.rm
;
16066 /* Check SIB byte. */
16069 FETCH_DATA (the_info
, codep
+ 1);
16071 /* When decoding the third source, don't increase
16072 bytes_before_imm as this has already been incremented
16073 by one in OP_E_memory while decoding the second
16076 bytes_before_imm
++;
16079 /* Don't increase bytes_before_imm when decoding the third source,
16080 it has already been incremented by OP_E_memory while decoding
16081 the second source operand. */
16087 /* When modrm.rm == 5 or modrm.rm == 4 and base in
16088 SIB == 5, there is a 4 byte displacement. */
16090 /* No displacement. */
16092 /* Fall through. */
16094 /* 4 byte displacement. */
16095 bytes_before_imm
+= 4;
16098 /* 1 byte displacement. */
16099 bytes_before_imm
++;
16106 /* 16 bit address mode */
16107 /* Don't increase bytes_before_imm when decoding the third source,
16108 it has already been incremented by OP_E_memory while decoding
16109 the second source operand. */
16115 /* When modrm.rm == 6, there is a 2 byte displacement. */
16117 /* No displacement. */
16119 /* Fall through. */
16121 /* 2 byte displacement. */
16122 bytes_before_imm
+= 2;
16125 /* 1 byte displacement: when decoding the third source,
16126 don't increase bytes_before_imm as this has already
16127 been incremented by one in OP_E_memory while decoding
16128 the second source operand. */
16130 bytes_before_imm
++;
16138 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
16139 return codep
[bytes_before_imm
];
16143 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
16145 const char **names
;
16147 if (reg
== -1 && modrm
.mod
!= 3)
16149 OP_E_memory (bytemode
, sizeflag
);
16161 if (address_mode
!= mode_64bit
)
16165 switch (vex
.length
)
16176 oappend (names
[reg
]);
16180 OP_EX_VexImmW (int bytemode
, int sizeflag
)
16183 static unsigned char vex_imm8
;
16185 if (vex_w_done
== 0)
16189 /* Skip mod/rm byte. */
16193 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
16196 reg
= vex_imm8
>> 4;
16198 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16200 else if (vex_w_done
== 1)
16205 reg
= vex_imm8
>> 4;
16207 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16211 /* Output the imm8 directly. */
16212 scratchbuf
[0] = '$';
16213 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
16214 oappend_maybe_intel (scratchbuf
);
16215 scratchbuf
[0] = '\0';
16221 OP_Vex_2src (int bytemode
, int sizeflag
)
16223 if (modrm
.mod
== 3)
16225 int reg
= modrm
.rm
;
16229 oappend (names_xmm
[reg
]);
16234 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16236 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16237 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16239 OP_E (bytemode
, sizeflag
);
16244 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
16246 if (modrm
.mod
== 3)
16248 /* Skip mod/rm byte. */
16255 unsigned int reg
= vex
.register_specifier
;
16256 vex
.register_specifier
= 0;
16258 if (address_mode
!= mode_64bit
)
16260 oappend (names_xmm
[reg
]);
16263 OP_Vex_2src (bytemode
, sizeflag
);
16267 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
16270 OP_Vex_2src (bytemode
, sizeflag
);
16273 unsigned int reg
= vex
.register_specifier
;
16274 vex
.register_specifier
= 0;
16276 if (address_mode
!= mode_64bit
)
16278 oappend (names_xmm
[reg
]);
16283 OP_EX_VexW (int bytemode
, int sizeflag
)
16289 /* Skip mod/rm byte. */
16294 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
16299 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
16302 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16310 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16313 const char **names
;
16315 FETCH_DATA (the_info
, codep
+ 1);
16318 if (bytemode
!= x_mode
)
16322 if (address_mode
!= mode_64bit
)
16325 switch (vex
.length
)
16336 oappend (names
[reg
]);
16340 OP_XMM_VexW (int bytemode
, int sizeflag
)
16342 /* Turn off the REX.W bit since it is used for swapping operands
16345 OP_XMM (bytemode
, sizeflag
);
16349 OP_EX_Vex (int bytemode
, int sizeflag
)
16351 if (modrm
.mod
!= 3)
16353 OP_EX (bytemode
, sizeflag
);
16357 OP_XMM_Vex (int bytemode
, int sizeflag
)
16359 if (modrm
.mod
!= 3)
16361 OP_XMM (bytemode
, sizeflag
);
16364 static struct op vex_cmp_op
[] =
16366 { STRING_COMMA_LEN ("eq") },
16367 { STRING_COMMA_LEN ("lt") },
16368 { STRING_COMMA_LEN ("le") },
16369 { STRING_COMMA_LEN ("unord") },
16370 { STRING_COMMA_LEN ("neq") },
16371 { STRING_COMMA_LEN ("nlt") },
16372 { STRING_COMMA_LEN ("nle") },
16373 { STRING_COMMA_LEN ("ord") },
16374 { STRING_COMMA_LEN ("eq_uq") },
16375 { STRING_COMMA_LEN ("nge") },
16376 { STRING_COMMA_LEN ("ngt") },
16377 { STRING_COMMA_LEN ("false") },
16378 { STRING_COMMA_LEN ("neq_oq") },
16379 { STRING_COMMA_LEN ("ge") },
16380 { STRING_COMMA_LEN ("gt") },
16381 { STRING_COMMA_LEN ("true") },
16382 { STRING_COMMA_LEN ("eq_os") },
16383 { STRING_COMMA_LEN ("lt_oq") },
16384 { STRING_COMMA_LEN ("le_oq") },
16385 { STRING_COMMA_LEN ("unord_s") },
16386 { STRING_COMMA_LEN ("neq_us") },
16387 { STRING_COMMA_LEN ("nlt_uq") },
16388 { STRING_COMMA_LEN ("nle_uq") },
16389 { STRING_COMMA_LEN ("ord_s") },
16390 { STRING_COMMA_LEN ("eq_us") },
16391 { STRING_COMMA_LEN ("nge_uq") },
16392 { STRING_COMMA_LEN ("ngt_uq") },
16393 { STRING_COMMA_LEN ("false_os") },
16394 { STRING_COMMA_LEN ("neq_os") },
16395 { STRING_COMMA_LEN ("ge_oq") },
16396 { STRING_COMMA_LEN ("gt_oq") },
16397 { STRING_COMMA_LEN ("true_us") },
16401 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16403 unsigned int cmp_type
;
16405 FETCH_DATA (the_info
, codep
+ 1);
16406 cmp_type
= *codep
++ & 0xff;
16407 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
16410 char *p
= mnemonicendp
- 2;
16414 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
16415 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
16419 /* We have a reserved extension byte. Output it directly. */
16420 scratchbuf
[0] = '$';
16421 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16422 oappend_maybe_intel (scratchbuf
);
16423 scratchbuf
[0] = '\0';
16428 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16429 int sizeflag ATTRIBUTE_UNUSED
)
16431 unsigned int cmp_type
;
16436 FETCH_DATA (the_info
, codep
+ 1);
16437 cmp_type
= *codep
++ & 0xff;
16438 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16439 If it's the case, print suffix, otherwise - print the immediate. */
16440 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
16445 char *p
= mnemonicendp
- 2;
16447 /* vpcmp* can have both one- and two-lettered suffix. */
16461 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16462 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16466 /* We have a reserved extension byte. Output it directly. */
16467 scratchbuf
[0] = '$';
16468 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16469 oappend_maybe_intel (scratchbuf
);
16470 scratchbuf
[0] = '\0';
16474 static const struct op xop_cmp_op
[] =
16476 { STRING_COMMA_LEN ("lt") },
16477 { STRING_COMMA_LEN ("le") },
16478 { STRING_COMMA_LEN ("gt") },
16479 { STRING_COMMA_LEN ("ge") },
16480 { STRING_COMMA_LEN ("eq") },
16481 { STRING_COMMA_LEN ("neq") },
16482 { STRING_COMMA_LEN ("false") },
16483 { STRING_COMMA_LEN ("true") }
16487 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16488 int sizeflag ATTRIBUTE_UNUSED
)
16490 unsigned int cmp_type
;
16492 FETCH_DATA (the_info
, codep
+ 1);
16493 cmp_type
= *codep
++ & 0xff;
16494 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
16497 char *p
= mnemonicendp
- 2;
16499 /* vpcom* can have both one- and two-lettered suffix. */
16513 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
16514 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
16518 /* We have a reserved extension byte. Output it directly. */
16519 scratchbuf
[0] = '$';
16520 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16521 oappend_maybe_intel (scratchbuf
);
16522 scratchbuf
[0] = '\0';
16526 static const struct op pclmul_op
[] =
16528 { STRING_COMMA_LEN ("lql") },
16529 { STRING_COMMA_LEN ("hql") },
16530 { STRING_COMMA_LEN ("lqh") },
16531 { STRING_COMMA_LEN ("hqh") }
16535 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16536 int sizeflag ATTRIBUTE_UNUSED
)
16538 unsigned int pclmul_type
;
16540 FETCH_DATA (the_info
, codep
+ 1);
16541 pclmul_type
= *codep
++ & 0xff;
16542 switch (pclmul_type
)
16553 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
16556 char *p
= mnemonicendp
- 3;
16561 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
16562 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
16566 /* We have a reserved extension byte. Output it directly. */
16567 scratchbuf
[0] = '$';
16568 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
16569 oappend_maybe_intel (scratchbuf
);
16570 scratchbuf
[0] = '\0';
16575 MOVBE_Fixup (int bytemode
, int sizeflag
)
16577 /* Add proper suffix to "movbe". */
16578 char *p
= mnemonicendp
;
16587 if (sizeflag
& SUFFIX_ALWAYS
)
16593 if (sizeflag
& DFLAG
)
16597 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16602 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16609 OP_M (bytemode
, sizeflag
);
16613 MOVSXD_Fixup (int bytemode
, int sizeflag
)
16615 /* Add proper suffix to "movsxd". */
16616 char *p
= mnemonicendp
;
16641 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16648 OP_E (bytemode
, sizeflag
);
16652 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16655 const char **names
;
16657 /* Skip mod/rm byte. */
16671 oappend (names
[reg
]);
16675 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16677 const char **names
;
16678 unsigned int reg
= vex
.register_specifier
;
16679 vex
.register_specifier
= 0;
16686 if (address_mode
!= mode_64bit
)
16688 oappend (names
[reg
]);
16692 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16695 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
16699 if ((rex
& REX_R
) != 0 || !vex
.r
)
16705 oappend (names_mask
[modrm
.reg
]);
16709 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16712 || (bytemode
!= evex_rounding_mode
16713 && bytemode
!= evex_rounding_64_mode
16714 && bytemode
!= evex_sae_mode
))
16716 if (modrm
.mod
== 3 && vex
.b
)
16719 case evex_rounding_64_mode
:
16720 if (address_mode
!= mode_64bit
)
16725 /* Fall through. */
16726 case evex_rounding_mode
:
16727 oappend (names_rounding
[vex
.ll
]);
16729 case evex_sae_mode
: