1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2019 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VCMP_Fixup (int, int);
99 static void VPCMP_Fixup (int, int);
100 static void VPCOM_Fixup (int, int);
101 static void OP_0f07 (int, int);
102 static void OP_Monitor (int, int);
103 static void OP_Mwait (int, int);
104 static void OP_Mwaitx (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void BND_Fixup (int, int);
112 static void NOTRACK_Fixup (int, int);
113 static void HLE_Fixup1 (int, int);
114 static void HLE_Fixup2 (int, int);
115 static void HLE_Fixup3 (int, int);
116 static void CMPXCHG8B_Fixup (int, int);
117 static void XMM_Fixup (int, int);
118 static void CRC32_Fixup (int, int);
119 static void FXSAVE_Fixup (int, int);
120 static void PCMPESTR_Fixup (int, int);
121 static void OP_LWPCB_E (int, int);
122 static void OP_LWP_E (int, int);
123 static void OP_Vex_2src_1 (int, int);
124 static void OP_Vex_2src_2 (int, int);
126 static void MOVBE_Fixup (int, int);
128 static void OP_Mask (int, int);
131 /* Points to first byte not fetched. */
132 bfd_byte
*max_fetched
;
133 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
136 OPCODES_SIGJMP_BUF bailout
;
146 enum address_mode address_mode
;
148 /* Flags for the prefixes for the current instruction. See below. */
151 /* REX prefix the current instruction. See below. */
153 /* Bits of REX we've already used. */
155 /* REX bits in original REX prefix ignored. */
156 static int rex_ignored
;
157 /* Mark parts used in the REX prefix. When we are testing for
158 empty prefix (for 8bit register REX extension), just mask it
159 out. Otherwise test for REX bit is excuse for existence of REX
160 only in case value is nonzero. */
161 #define USED_REX(value) \
166 rex_used |= (value) | REX_OPCODE; \
169 rex_used |= REX_OPCODE; \
172 /* Flags for prefixes which we somehow handled when printing the
173 current instruction. */
174 static int used_prefixes
;
176 /* Flags stored in PREFIXES. */
177 #define PREFIX_REPZ 1
178 #define PREFIX_REPNZ 2
179 #define PREFIX_LOCK 4
181 #define PREFIX_SS 0x10
182 #define PREFIX_DS 0x20
183 #define PREFIX_ES 0x40
184 #define PREFIX_FS 0x80
185 #define PREFIX_GS 0x100
186 #define PREFIX_DATA 0x200
187 #define PREFIX_ADDR 0x400
188 #define PREFIX_FWAIT 0x800
190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
191 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
193 #define FETCH_DATA(info, addr) \
194 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
195 ? 1 : fetch_data ((info), (addr)))
198 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
201 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
202 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
204 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
205 status
= (*info
->read_memory_func
) (start
,
207 addr
- priv
->max_fetched
,
213 /* If we did manage to read at least one byte, then
214 print_insn_i386 will do something sensible. Otherwise, print
215 an error. We do that here because this is where we know
217 if (priv
->max_fetched
== priv
->the_buffer
)
218 (*info
->memory_error_func
) (status
, start
, info
);
219 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
222 priv
->max_fetched
= addr
;
226 /* Possible values for prefix requirement. */
227 #define PREFIX_IGNORED_SHIFT 16
228 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
229 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
234 /* Opcode prefixes. */
235 #define PREFIX_OPCODE (PREFIX_REPZ \
239 /* Prefixes ignored. */
240 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
241 | PREFIX_IGNORED_REPNZ \
242 | PREFIX_IGNORED_DATA)
244 #define XX { NULL, 0 }
245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
247 #define Eb { OP_E, b_mode }
248 #define Ebnd { OP_E, bnd_mode }
249 #define EbS { OP_E, b_swap_mode }
250 #define EbndS { OP_E, bnd_swap_mode }
251 #define Ev { OP_E, v_mode }
252 #define Eva { OP_E, va_mode }
253 #define Ev_bnd { OP_E, v_bnd_mode }
254 #define EvS { OP_E, v_swap_mode }
255 #define Ed { OP_E, d_mode }
256 #define Edq { OP_E, dq_mode }
257 #define Edqw { OP_E, dqw_mode }
258 #define Edqb { OP_E, dqb_mode }
259 #define Edb { OP_E, db_mode }
260 #define Edw { OP_E, dw_mode }
261 #define Edqd { OP_E, dqd_mode }
262 #define Edqa { OP_E, dqa_mode }
263 #define Eq { OP_E, q_mode }
264 #define indirEv { OP_indirE, indir_v_mode }
265 #define indirEp { OP_indirE, f_mode }
266 #define stackEv { OP_E, stack_v_mode }
267 #define Em { OP_E, m_mode }
268 #define Ew { OP_E, w_mode }
269 #define M { OP_M, 0 } /* lea, lgdt, etc. */
270 #define Ma { OP_M, a_mode }
271 #define Mb { OP_M, b_mode }
272 #define Md { OP_M, d_mode }
273 #define Mo { OP_M, o_mode }
274 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
275 #define Mq { OP_M, q_mode }
276 #define Mv_bnd { OP_M, v_bndmk_mode }
277 #define Mx { OP_M, x_mode }
278 #define Mxmm { OP_M, xmm_mode }
279 #define Gb { OP_G, b_mode }
280 #define Gbnd { OP_G, bnd_mode }
281 #define Gv { OP_G, v_mode }
282 #define Gd { OP_G, d_mode }
283 #define Gdq { OP_G, dq_mode }
284 #define Gm { OP_G, m_mode }
285 #define Gva { OP_G, va_mode }
286 #define Gw { OP_G, w_mode }
287 #define Rd { OP_R, d_mode }
288 #define Rdq { OP_R, dq_mode }
289 #define Rm { OP_R, m_mode }
290 #define Ib { OP_I, b_mode }
291 #define sIb { OP_sI, b_mode } /* sign extened byte */
292 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
293 #define Iv { OP_I, v_mode }
294 #define sIv { OP_sI, v_mode }
295 #define Iq { OP_I, q_mode }
296 #define Iv64 { OP_I64, v_mode }
297 #define Iw { OP_I, w_mode }
298 #define I1 { OP_I, const_1_mode }
299 #define Jb { OP_J, b_mode }
300 #define Jv { OP_J, v_mode }
301 #define Cm { OP_C, m_mode }
302 #define Dm { OP_D, m_mode }
303 #define Td { OP_T, d_mode }
304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
306 #define RMeAX { OP_REG, eAX_reg }
307 #define RMeBX { OP_REG, eBX_reg }
308 #define RMeCX { OP_REG, eCX_reg }
309 #define RMeDX { OP_REG, eDX_reg }
310 #define RMeSP { OP_REG, eSP_reg }
311 #define RMeBP { OP_REG, eBP_reg }
312 #define RMeSI { OP_REG, eSI_reg }
313 #define RMeDI { OP_REG, eDI_reg }
314 #define RMrAX { OP_REG, rAX_reg }
315 #define RMrBX { OP_REG, rBX_reg }
316 #define RMrCX { OP_REG, rCX_reg }
317 #define RMrDX { OP_REG, rDX_reg }
318 #define RMrSP { OP_REG, rSP_reg }
319 #define RMrBP { OP_REG, rBP_reg }
320 #define RMrSI { OP_REG, rSI_reg }
321 #define RMrDI { OP_REG, rDI_reg }
322 #define RMAL { OP_REG, al_reg }
323 #define RMCL { OP_REG, cl_reg }
324 #define RMDL { OP_REG, dl_reg }
325 #define RMBL { OP_REG, bl_reg }
326 #define RMAH { OP_REG, ah_reg }
327 #define RMCH { OP_REG, ch_reg }
328 #define RMDH { OP_REG, dh_reg }
329 #define RMBH { OP_REG, bh_reg }
330 #define RMAX { OP_REG, ax_reg }
331 #define RMDX { OP_REG, dx_reg }
333 #define eAX { OP_IMREG, eAX_reg }
334 #define eBX { OP_IMREG, eBX_reg }
335 #define eCX { OP_IMREG, eCX_reg }
336 #define eDX { OP_IMREG, eDX_reg }
337 #define eSP { OP_IMREG, eSP_reg }
338 #define eBP { OP_IMREG, eBP_reg }
339 #define eSI { OP_IMREG, eSI_reg }
340 #define eDI { OP_IMREG, eDI_reg }
341 #define AL { OP_IMREG, al_reg }
342 #define CL { OP_IMREG, cl_reg }
343 #define DL { OP_IMREG, dl_reg }
344 #define BL { OP_IMREG, bl_reg }
345 #define AH { OP_IMREG, ah_reg }
346 #define CH { OP_IMREG, ch_reg }
347 #define DH { OP_IMREG, dh_reg }
348 #define BH { OP_IMREG, bh_reg }
349 #define AX { OP_IMREG, ax_reg }
350 #define DX { OP_IMREG, dx_reg }
351 #define zAX { OP_IMREG, z_mode_ax_reg }
352 #define indirDX { OP_IMREG, indir_dx_reg }
354 #define Sw { OP_SEG, w_mode }
355 #define Sv { OP_SEG, v_mode }
356 #define Ap { OP_DIR, 0 }
357 #define Ob { OP_OFF64, b_mode }
358 #define Ov { OP_OFF64, v_mode }
359 #define Xb { OP_DSreg, eSI_reg }
360 #define Xv { OP_DSreg, eSI_reg }
361 #define Xz { OP_DSreg, eSI_reg }
362 #define Yb { OP_ESreg, eDI_reg }
363 #define Yv { OP_ESreg, eDI_reg }
364 #define DSBX { OP_DSreg, eBX_reg }
366 #define es { OP_REG, es_reg }
367 #define ss { OP_REG, ss_reg }
368 #define cs { OP_REG, cs_reg }
369 #define ds { OP_REG, ds_reg }
370 #define fs { OP_REG, fs_reg }
371 #define gs { OP_REG, gs_reg }
373 #define MX { OP_MMX, 0 }
374 #define XM { OP_XMM, 0 }
375 #define XMScalar { OP_XMM, scalar_mode }
376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
377 #define XMM { OP_XMM, xmm_mode }
378 #define XMxmmq { OP_XMM, xmmq_mode }
379 #define EM { OP_EM, v_mode }
380 #define EMS { OP_EM, v_swap_mode }
381 #define EMd { OP_EM, d_mode }
382 #define EMx { OP_EM, x_mode }
383 #define EXbScalar { OP_EX, b_scalar_mode }
384 #define EXw { OP_EX, w_mode }
385 #define EXwScalar { OP_EX, w_scalar_mode }
386 #define EXd { OP_EX, d_mode }
387 #define EXdScalar { OP_EX, d_scalar_mode }
388 #define EXdS { OP_EX, d_swap_mode }
389 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
390 #define EXq { OP_EX, q_mode }
391 #define EXqScalar { OP_EX, q_scalar_mode }
392 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
393 #define EXqS { OP_EX, q_swap_mode }
394 #define EXx { OP_EX, x_mode }
395 #define EXxS { OP_EX, x_swap_mode }
396 #define EXxmm { OP_EX, xmm_mode }
397 #define EXymm { OP_EX, ymm_mode }
398 #define EXxmmq { OP_EX, xmmq_mode }
399 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
400 #define EXxmm_mb { OP_EX, xmm_mb_mode }
401 #define EXxmm_mw { OP_EX, xmm_mw_mode }
402 #define EXxmm_md { OP_EX, xmm_md_mode }
403 #define EXxmm_mq { OP_EX, xmm_mq_mode }
404 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
405 #define EXxmmdw { OP_EX, xmmdw_mode }
406 #define EXxmmqd { OP_EX, xmmqd_mode }
407 #define EXymmq { OP_EX, ymmq_mode }
408 #define EXVexWdq { OP_EX, vex_w_dq_mode }
409 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
410 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
411 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
412 #define MS { OP_MS, v_mode }
413 #define XS { OP_XS, v_mode }
414 #define EMCq { OP_EMC, q_mode }
415 #define MXC { OP_MXC, 0 }
416 #define OPSUF { OP_3DNowSuffix, 0 }
417 #define CMP { CMP_Fixup, 0 }
418 #define XMM0 { XMM_Fixup, 0 }
419 #define FXSAVE { FXSAVE_Fixup, 0 }
420 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
421 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
423 #define Vex { OP_VEX, vex_mode }
424 #define VexScalar { OP_VEX, vex_scalar_mode }
425 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
426 #define Vex128 { OP_VEX, vex128_mode }
427 #define Vex256 { OP_VEX, vex256_mode }
428 #define VexGdq { OP_VEX, dq_mode }
429 #define EXdVex { OP_EX_Vex, d_mode }
430 #define EXdVexS { OP_EX_Vex, d_swap_mode }
431 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
432 #define EXqVex { OP_EX_Vex, q_mode }
433 #define EXqVexS { OP_EX_Vex, q_swap_mode }
434 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
435 #define EXVexW { OP_EX_VexW, x_mode }
436 #define EXdVexW { OP_EX_VexW, d_mode }
437 #define EXqVexW { OP_EX_VexW, q_mode }
438 #define EXVexImmW { OP_EX_VexImmW, x_mode }
439 #define XMVex { OP_XMM_Vex, 0 }
440 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
441 #define XMVexW { OP_XMM_VexW, 0 }
442 #define XMVexI4 { OP_REG_VexI4, x_mode }
443 #define PCLMUL { PCLMUL_Fixup, 0 }
444 #define VCMP { VCMP_Fixup, 0 }
445 #define VPCMP { VPCMP_Fixup, 0 }
446 #define VPCOM { VPCOM_Fixup, 0 }
448 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
449 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
450 #define EXxEVexS { OP_Rounding, evex_sae_mode }
452 #define XMask { OP_Mask, mask_mode }
453 #define MaskG { OP_G, mask_mode }
454 #define MaskE { OP_E, mask_mode }
455 #define MaskBDE { OP_E, mask_bd_mode }
456 #define MaskR { OP_R, mask_mode }
457 #define MaskVex { OP_VEX, mask_mode }
459 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
460 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
461 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
462 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
464 /* Used handle "rep" prefix for string instructions. */
465 #define Xbr { REP_Fixup, eSI_reg }
466 #define Xvr { REP_Fixup, eSI_reg }
467 #define Ybr { REP_Fixup, eDI_reg }
468 #define Yvr { REP_Fixup, eDI_reg }
469 #define Yzr { REP_Fixup, eDI_reg }
470 #define indirDXr { REP_Fixup, indir_dx_reg }
471 #define ALr { REP_Fixup, al_reg }
472 #define eAXr { REP_Fixup, eAX_reg }
474 /* Used handle HLE prefix for lockable instructions. */
475 #define Ebh1 { HLE_Fixup1, b_mode }
476 #define Evh1 { HLE_Fixup1, v_mode }
477 #define Ebh2 { HLE_Fixup2, b_mode }
478 #define Evh2 { HLE_Fixup2, v_mode }
479 #define Ebh3 { HLE_Fixup3, b_mode }
480 #define Evh3 { HLE_Fixup3, v_mode }
482 #define BND { BND_Fixup, 0 }
483 #define NOTRACK { NOTRACK_Fixup, 0 }
485 #define cond_jump_flag { NULL, cond_jump_mode }
486 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
488 /* bits in sizeflag */
489 #define SUFFIX_ALWAYS 4
497 /* byte operand with operand swapped */
499 /* byte operand, sign extend like 'T' suffix */
501 /* operand size depends on prefixes */
503 /* operand size depends on prefixes with operand swapped */
505 /* operand size depends on address prefix */
509 /* double word operand */
511 /* double word operand with operand swapped */
513 /* quad word operand */
515 /* quad word operand with operand swapped */
517 /* ten-byte operand */
519 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
520 broadcast enabled. */
522 /* Similar to x_mode, but with different EVEX mem shifts. */
524 /* Similar to x_mode, but with disabled broadcast. */
526 /* Similar to x_mode, but with operands swapped and disabled broadcast
529 /* 16-byte XMM operand */
531 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
532 memory operand (depending on vector length). Broadcast isn't
535 /* Same as xmmq_mode, but broadcast is allowed. */
536 evex_half_bcst_xmmq_mode
,
537 /* XMM register or byte memory operand */
539 /* XMM register or word memory operand */
541 /* XMM register or double word memory operand */
543 /* XMM register or quad word memory operand */
545 /* XMM register or double/quad word memory operand, depending on
548 /* 16-byte XMM, word, double word or quad word operand. */
550 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
552 /* 32-byte YMM operand */
554 /* quad word, ymmword or zmmword memory operand. */
556 /* 32-byte YMM or 16-byte word operand */
558 /* d_mode in 32bit, q_mode in 64bit mode. */
560 /* pair of v_mode operands */
565 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
567 /* operand size depends on REX prefixes. */
569 /* registers like dq_mode, memory like w_mode. */
573 /* bounds operand with operand swapped */
575 /* 4- or 6-byte pointer operand */
578 /* v_mode for indirect branch opcodes. */
580 /* v_mode for stack-related opcodes. */
582 /* non-quad operand size depends on prefixes */
584 /* 16-byte operand */
586 /* registers like dq_mode, memory like b_mode. */
588 /* registers like d_mode, memory like b_mode. */
590 /* registers like d_mode, memory like w_mode. */
592 /* registers like dq_mode, memory like d_mode. */
594 /* operand size depends on the W bit as well as address mode. */
596 /* normal vex mode */
598 /* 128bit vex mode */
600 /* 256bit vex mode */
602 /* operand size depends on the VEX.W bit. */
605 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
606 vex_vsib_d_w_dq_mode
,
607 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
609 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
610 vex_vsib_q_w_dq_mode
,
611 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
614 /* scalar, ignore vector length. */
616 /* like b_mode, ignore vector length. */
618 /* like w_mode, ignore vector length. */
620 /* like d_mode, ignore vector length. */
622 /* like d_swap_mode, ignore vector length. */
624 /* like q_mode, ignore vector length. */
626 /* like q_swap_mode, ignore vector length. */
628 /* like vex_mode, ignore vector length. */
630 /* like vex_w_dq_mode, ignore vector length. */
631 vex_scalar_w_dq_mode
,
633 /* Static rounding. */
635 /* Static rounding, 64-bit mode only. */
636 evex_rounding_64_mode
,
637 /* Supress all exceptions. */
640 /* Mask register operand. */
642 /* Mask register operand. */
710 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
712 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
713 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
714 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
715 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
716 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
717 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
718 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
719 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
720 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
721 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
722 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
723 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
724 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
725 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
726 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
727 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
855 MOD_VEX_0F12_PREFIX_0
,
857 MOD_VEX_0F16_PREFIX_0
,
860 MOD_VEX_W_0_0F41_P_0_LEN_1
,
861 MOD_VEX_W_1_0F41_P_0_LEN_1
,
862 MOD_VEX_W_0_0F41_P_2_LEN_1
,
863 MOD_VEX_W_1_0F41_P_2_LEN_1
,
864 MOD_VEX_W_0_0F42_P_0_LEN_1
,
865 MOD_VEX_W_1_0F42_P_0_LEN_1
,
866 MOD_VEX_W_0_0F42_P_2_LEN_1
,
867 MOD_VEX_W_1_0F42_P_2_LEN_1
,
868 MOD_VEX_W_0_0F44_P_0_LEN_1
,
869 MOD_VEX_W_1_0F44_P_0_LEN_1
,
870 MOD_VEX_W_0_0F44_P_2_LEN_1
,
871 MOD_VEX_W_1_0F44_P_2_LEN_1
,
872 MOD_VEX_W_0_0F45_P_0_LEN_1
,
873 MOD_VEX_W_1_0F45_P_0_LEN_1
,
874 MOD_VEX_W_0_0F45_P_2_LEN_1
,
875 MOD_VEX_W_1_0F45_P_2_LEN_1
,
876 MOD_VEX_W_0_0F46_P_0_LEN_1
,
877 MOD_VEX_W_1_0F46_P_0_LEN_1
,
878 MOD_VEX_W_0_0F46_P_2_LEN_1
,
879 MOD_VEX_W_1_0F46_P_2_LEN_1
,
880 MOD_VEX_W_0_0F47_P_0_LEN_1
,
881 MOD_VEX_W_1_0F47_P_0_LEN_1
,
882 MOD_VEX_W_0_0F47_P_2_LEN_1
,
883 MOD_VEX_W_1_0F47_P_2_LEN_1
,
884 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
885 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
886 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
887 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
888 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
889 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
890 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
902 MOD_VEX_W_0_0F91_P_0_LEN_0
,
903 MOD_VEX_W_1_0F91_P_0_LEN_0
,
904 MOD_VEX_W_0_0F91_P_2_LEN_0
,
905 MOD_VEX_W_1_0F91_P_2_LEN_0
,
906 MOD_VEX_W_0_0F92_P_0_LEN_0
,
907 MOD_VEX_W_0_0F92_P_2_LEN_0
,
908 MOD_VEX_0F92_P_3_LEN_0
,
909 MOD_VEX_W_0_0F93_P_0_LEN_0
,
910 MOD_VEX_W_0_0F93_P_2_LEN_0
,
911 MOD_VEX_0F93_P_3_LEN_0
,
912 MOD_VEX_W_0_0F98_P_0_LEN_0
,
913 MOD_VEX_W_1_0F98_P_0_LEN_0
,
914 MOD_VEX_W_0_0F98_P_2_LEN_0
,
915 MOD_VEX_W_1_0F98_P_2_LEN_0
,
916 MOD_VEX_W_0_0F99_P_0_LEN_0
,
917 MOD_VEX_W_1_0F99_P_0_LEN_0
,
918 MOD_VEX_W_0_0F99_P_2_LEN_0
,
919 MOD_VEX_W_1_0F99_P_2_LEN_0
,
922 MOD_VEX_0FD7_PREFIX_2
,
923 MOD_VEX_0FE7_PREFIX_2
,
924 MOD_VEX_0FF0_PREFIX_3
,
925 MOD_VEX_0F381A_PREFIX_2
,
926 MOD_VEX_0F382A_PREFIX_2
,
927 MOD_VEX_0F382C_PREFIX_2
,
928 MOD_VEX_0F382D_PREFIX_2
,
929 MOD_VEX_0F382E_PREFIX_2
,
930 MOD_VEX_0F382F_PREFIX_2
,
931 MOD_VEX_0F385A_PREFIX_2
,
932 MOD_VEX_0F388C_PREFIX_2
,
933 MOD_VEX_0F388E_PREFIX_2
,
934 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
935 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
936 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
937 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
938 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
939 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
940 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
941 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
943 MOD_EVEX_0F10_PREFIX_1
,
944 MOD_EVEX_0F10_PREFIX_3
,
945 MOD_EVEX_0F11_PREFIX_1
,
946 MOD_EVEX_0F11_PREFIX_3
,
947 MOD_EVEX_0F12_PREFIX_0
,
948 MOD_EVEX_0F16_PREFIX_0
,
949 MOD_EVEX_0F38C6_REG_1
,
950 MOD_EVEX_0F38C6_REG_2
,
951 MOD_EVEX_0F38C6_REG_5
,
952 MOD_EVEX_0F38C6_REG_6
,
953 MOD_EVEX_0F38C7_REG_1
,
954 MOD_EVEX_0F38C7_REG_2
,
955 MOD_EVEX_0F38C7_REG_5
,
956 MOD_EVEX_0F38C7_REG_6
977 PREFIX_MOD_0_0F01_REG_5
,
978 PREFIX_MOD_3_0F01_REG_5_RM_0
,
979 PREFIX_MOD_3_0F01_REG_5_RM_2
,
1025 PREFIX_MOD_0_0FAE_REG_4
,
1026 PREFIX_MOD_3_0FAE_REG_4
,
1027 PREFIX_MOD_0_0FAE_REG_5
,
1028 PREFIX_MOD_3_0FAE_REG_5
,
1029 PREFIX_MOD_0_0FAE_REG_6
,
1030 PREFIX_MOD_1_0FAE_REG_6
,
1037 PREFIX_MOD_0_0FC7_REG_6
,
1038 PREFIX_MOD_3_0FC7_REG_6
,
1039 PREFIX_MOD_3_0FC7_REG_7
,
1169 PREFIX_VEX_0F71_REG_2
,
1170 PREFIX_VEX_0F71_REG_4
,
1171 PREFIX_VEX_0F71_REG_6
,
1172 PREFIX_VEX_0F72_REG_2
,
1173 PREFIX_VEX_0F72_REG_4
,
1174 PREFIX_VEX_0F72_REG_6
,
1175 PREFIX_VEX_0F73_REG_2
,
1176 PREFIX_VEX_0F73_REG_3
,
1177 PREFIX_VEX_0F73_REG_6
,
1178 PREFIX_VEX_0F73_REG_7
,
1351 PREFIX_VEX_0F38F3_REG_1
,
1352 PREFIX_VEX_0F38F3_REG_2
,
1353 PREFIX_VEX_0F38F3_REG_3
,
1472 PREFIX_EVEX_0F71_REG_2
,
1473 PREFIX_EVEX_0F71_REG_4
,
1474 PREFIX_EVEX_0F71_REG_6
,
1475 PREFIX_EVEX_0F72_REG_0
,
1476 PREFIX_EVEX_0F72_REG_1
,
1477 PREFIX_EVEX_0F72_REG_2
,
1478 PREFIX_EVEX_0F72_REG_4
,
1479 PREFIX_EVEX_0F72_REG_6
,
1480 PREFIX_EVEX_0F73_REG_2
,
1481 PREFIX_EVEX_0F73_REG_3
,
1482 PREFIX_EVEX_0F73_REG_6
,
1483 PREFIX_EVEX_0F73_REG_7
,
1680 PREFIX_EVEX_0F38C6_REG_1
,
1681 PREFIX_EVEX_0F38C6_REG_2
,
1682 PREFIX_EVEX_0F38C6_REG_5
,
1683 PREFIX_EVEX_0F38C6_REG_6
,
1684 PREFIX_EVEX_0F38C7_REG_1
,
1685 PREFIX_EVEX_0F38C7_REG_2
,
1686 PREFIX_EVEX_0F38C7_REG_5
,
1687 PREFIX_EVEX_0F38C7_REG_6
,
1789 THREE_BYTE_0F38
= 0,
1816 VEX_LEN_0F12_P_0_M_0
= 0,
1817 VEX_LEN_0F12_P_0_M_1
,
1820 VEX_LEN_0F16_P_0_M_0
,
1821 VEX_LEN_0F16_P_0_M_1
,
1864 VEX_LEN_0FAE_R_2_M_0
,
1865 VEX_LEN_0FAE_R_3_M_0
,
1872 VEX_LEN_0F381A_P_2_M_0
,
1875 VEX_LEN_0F385A_P_2_M_0
,
1878 VEX_LEN_0F38F3_R_1_P_0
,
1879 VEX_LEN_0F38F3_R_2_P_0
,
1880 VEX_LEN_0F38F3_R_3_P_0
,
1923 VEX_LEN_0FXOP_08_CC
,
1924 VEX_LEN_0FXOP_08_CD
,
1925 VEX_LEN_0FXOP_08_CE
,
1926 VEX_LEN_0FXOP_08_CF
,
1927 VEX_LEN_0FXOP_08_EC
,
1928 VEX_LEN_0FXOP_08_ED
,
1929 VEX_LEN_0FXOP_08_EE
,
1930 VEX_LEN_0FXOP_08_EF
,
1931 VEX_LEN_0FXOP_09_80
,
1937 EVEX_LEN_0F6E_P_2
= 0,
1945 VEX_W_0F41_P_0_LEN_1
= 0,
1946 VEX_W_0F41_P_2_LEN_1
,
1947 VEX_W_0F42_P_0_LEN_1
,
1948 VEX_W_0F42_P_2_LEN_1
,
1949 VEX_W_0F44_P_0_LEN_0
,
1950 VEX_W_0F44_P_2_LEN_0
,
1951 VEX_W_0F45_P_0_LEN_1
,
1952 VEX_W_0F45_P_2_LEN_1
,
1953 VEX_W_0F46_P_0_LEN_1
,
1954 VEX_W_0F46_P_2_LEN_1
,
1955 VEX_W_0F47_P_0_LEN_1
,
1956 VEX_W_0F47_P_2_LEN_1
,
1957 VEX_W_0F4A_P_0_LEN_1
,
1958 VEX_W_0F4A_P_2_LEN_1
,
1959 VEX_W_0F4B_P_0_LEN_1
,
1960 VEX_W_0F4B_P_2_LEN_1
,
1961 VEX_W_0F90_P_0_LEN_0
,
1962 VEX_W_0F90_P_2_LEN_0
,
1963 VEX_W_0F91_P_0_LEN_0
,
1964 VEX_W_0F91_P_2_LEN_0
,
1965 VEX_W_0F92_P_0_LEN_0
,
1966 VEX_W_0F92_P_2_LEN_0
,
1967 VEX_W_0F93_P_0_LEN_0
,
1968 VEX_W_0F93_P_2_LEN_0
,
1969 VEX_W_0F98_P_0_LEN_0
,
1970 VEX_W_0F98_P_2_LEN_0
,
1971 VEX_W_0F99_P_0_LEN_0
,
1972 VEX_W_0F99_P_2_LEN_0
,
1980 VEX_W_0F381A_P_2_M_0
,
1981 VEX_W_0F382C_P_2_M_0
,
1982 VEX_W_0F382D_P_2_M_0
,
1983 VEX_W_0F382E_P_2_M_0
,
1984 VEX_W_0F382F_P_2_M_0
,
1989 VEX_W_0F385A_P_2_M_0
,
2001 VEX_W_0F3A30_P_2_LEN_0
,
2002 VEX_W_0F3A31_P_2_LEN_0
,
2003 VEX_W_0F3A32_P_2_LEN_0
,
2004 VEX_W_0F3A33_P_2_LEN_0
,
2017 EVEX_W_0F10_P_1_M_0
,
2018 EVEX_W_0F10_P_1_M_1
,
2020 EVEX_W_0F10_P_3_M_0
,
2021 EVEX_W_0F10_P_3_M_1
,
2023 EVEX_W_0F11_P_1_M_0
,
2024 EVEX_W_0F11_P_1_M_1
,
2026 EVEX_W_0F11_P_3_M_0
,
2027 EVEX_W_0F11_P_3_M_1
,
2028 EVEX_W_0F12_P_0_M_0
,
2029 EVEX_W_0F12_P_0_M_1
,
2039 EVEX_W_0F16_P_0_M_0
,
2040 EVEX_W_0F16_P_0_M_1
,
2110 EVEX_W_0F72_R_2_P_2
,
2111 EVEX_W_0F72_R_6_P_2
,
2112 EVEX_W_0F73_R_2_P_2
,
2113 EVEX_W_0F73_R_6_P_2
,
2224 EVEX_W_0F38C7_R_1_P_2
,
2225 EVEX_W_0F38C7_R_2_P_2
,
2226 EVEX_W_0F38C7_R_5_P_2
,
2227 EVEX_W_0F38C7_R_6_P_2
,
2266 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2275 unsigned int prefix_requirement
;
2278 /* Upper case letters in the instruction names here are macros.
2279 'A' => print 'b' if no register operands or suffix_always is true
2280 'B' => print 'b' if suffix_always is true
2281 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2283 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2284 suffix_always is true
2285 'E' => print 'e' if 32-bit form of jcxz
2286 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2287 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2288 'H' => print ",pt" or ",pn" branch hint
2289 'I' => honor following macro letter even in Intel mode (implemented only
2290 for some of the macro letters)
2292 'K' => print 'd' or 'q' if rex prefix is present.
2293 'L' => print 'l' if suffix_always is true
2294 'M' => print 'r' if intel_mnemonic is false.
2295 'N' => print 'n' if instruction has no wait "prefix"
2296 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2297 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2298 or suffix_always is true. print 'q' if rex prefix is present.
2299 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2301 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2302 'S' => print 'w', 'l' or 'q' if suffix_always is true
2303 'T' => print 'q' in 64bit mode if instruction has no operand size
2304 prefix and behave as 'P' otherwise
2305 'U' => print 'q' in 64bit mode if instruction has no operand size
2306 prefix and behave as 'Q' otherwise
2307 'V' => print 'q' in 64bit mode if instruction has no operand size
2308 prefix and behave as 'S' otherwise
2309 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2310 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2312 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2313 '!' => change condition from true to false or from false to true.
2314 '%' => add 1 upper case letter to the macro.
2315 '^' => print 'w' or 'l' depending on operand size prefix or
2316 suffix_always is true (lcall/ljmp).
2317 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2318 on operand size prefix.
2319 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2320 has no operand size prefix for AMD64 ISA, behave as 'P'
2323 2 upper case letter macros:
2324 "XY" => print 'x' or 'y' if suffix_always is true or no register
2325 operands and no broadcast.
2326 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2327 register operands and no broadcast.
2328 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2329 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2330 or suffix_always is true
2331 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2332 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2333 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2334 "LW" => print 'd', 'q' depending on the VEX.W bit
2335 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2336 an operand size prefix, or suffix_always is true. print
2337 'q' if rex prefix is present.
2339 Many of the above letters print nothing in Intel mode. See "putop"
2342 Braces '{' and '}', and vertical bars '|', indicate alternative
2343 mnemonic strings for AT&T and Intel. */
2345 static const struct dis386 dis386
[] = {
2347 { "addB", { Ebh1
, Gb
}, 0 },
2348 { "addS", { Evh1
, Gv
}, 0 },
2349 { "addB", { Gb
, EbS
}, 0 },
2350 { "addS", { Gv
, EvS
}, 0 },
2351 { "addB", { AL
, Ib
}, 0 },
2352 { "addS", { eAX
, Iv
}, 0 },
2353 { X86_64_TABLE (X86_64_06
) },
2354 { X86_64_TABLE (X86_64_07
) },
2356 { "orB", { Ebh1
, Gb
}, 0 },
2357 { "orS", { Evh1
, Gv
}, 0 },
2358 { "orB", { Gb
, EbS
}, 0 },
2359 { "orS", { Gv
, EvS
}, 0 },
2360 { "orB", { AL
, Ib
}, 0 },
2361 { "orS", { eAX
, Iv
}, 0 },
2362 { X86_64_TABLE (X86_64_0D
) },
2363 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2365 { "adcB", { Ebh1
, Gb
}, 0 },
2366 { "adcS", { Evh1
, Gv
}, 0 },
2367 { "adcB", { Gb
, EbS
}, 0 },
2368 { "adcS", { Gv
, EvS
}, 0 },
2369 { "adcB", { AL
, Ib
}, 0 },
2370 { "adcS", { eAX
, Iv
}, 0 },
2371 { X86_64_TABLE (X86_64_16
) },
2372 { X86_64_TABLE (X86_64_17
) },
2374 { "sbbB", { Ebh1
, Gb
}, 0 },
2375 { "sbbS", { Evh1
, Gv
}, 0 },
2376 { "sbbB", { Gb
, EbS
}, 0 },
2377 { "sbbS", { Gv
, EvS
}, 0 },
2378 { "sbbB", { AL
, Ib
}, 0 },
2379 { "sbbS", { eAX
, Iv
}, 0 },
2380 { X86_64_TABLE (X86_64_1E
) },
2381 { X86_64_TABLE (X86_64_1F
) },
2383 { "andB", { Ebh1
, Gb
}, 0 },
2384 { "andS", { Evh1
, Gv
}, 0 },
2385 { "andB", { Gb
, EbS
}, 0 },
2386 { "andS", { Gv
, EvS
}, 0 },
2387 { "andB", { AL
, Ib
}, 0 },
2388 { "andS", { eAX
, Iv
}, 0 },
2389 { Bad_Opcode
}, /* SEG ES prefix */
2390 { X86_64_TABLE (X86_64_27
) },
2392 { "subB", { Ebh1
, Gb
}, 0 },
2393 { "subS", { Evh1
, Gv
}, 0 },
2394 { "subB", { Gb
, EbS
}, 0 },
2395 { "subS", { Gv
, EvS
}, 0 },
2396 { "subB", { AL
, Ib
}, 0 },
2397 { "subS", { eAX
, Iv
}, 0 },
2398 { Bad_Opcode
}, /* SEG CS prefix */
2399 { X86_64_TABLE (X86_64_2F
) },
2401 { "xorB", { Ebh1
, Gb
}, 0 },
2402 { "xorS", { Evh1
, Gv
}, 0 },
2403 { "xorB", { Gb
, EbS
}, 0 },
2404 { "xorS", { Gv
, EvS
}, 0 },
2405 { "xorB", { AL
, Ib
}, 0 },
2406 { "xorS", { eAX
, Iv
}, 0 },
2407 { Bad_Opcode
}, /* SEG SS prefix */
2408 { X86_64_TABLE (X86_64_37
) },
2410 { "cmpB", { Eb
, Gb
}, 0 },
2411 { "cmpS", { Ev
, Gv
}, 0 },
2412 { "cmpB", { Gb
, EbS
}, 0 },
2413 { "cmpS", { Gv
, EvS
}, 0 },
2414 { "cmpB", { AL
, Ib
}, 0 },
2415 { "cmpS", { eAX
, Iv
}, 0 },
2416 { Bad_Opcode
}, /* SEG DS prefix */
2417 { X86_64_TABLE (X86_64_3F
) },
2419 { "inc{S|}", { RMeAX
}, 0 },
2420 { "inc{S|}", { RMeCX
}, 0 },
2421 { "inc{S|}", { RMeDX
}, 0 },
2422 { "inc{S|}", { RMeBX
}, 0 },
2423 { "inc{S|}", { RMeSP
}, 0 },
2424 { "inc{S|}", { RMeBP
}, 0 },
2425 { "inc{S|}", { RMeSI
}, 0 },
2426 { "inc{S|}", { RMeDI
}, 0 },
2428 { "dec{S|}", { RMeAX
}, 0 },
2429 { "dec{S|}", { RMeCX
}, 0 },
2430 { "dec{S|}", { RMeDX
}, 0 },
2431 { "dec{S|}", { RMeBX
}, 0 },
2432 { "dec{S|}", { RMeSP
}, 0 },
2433 { "dec{S|}", { RMeBP
}, 0 },
2434 { "dec{S|}", { RMeSI
}, 0 },
2435 { "dec{S|}", { RMeDI
}, 0 },
2437 { "pushV", { RMrAX
}, 0 },
2438 { "pushV", { RMrCX
}, 0 },
2439 { "pushV", { RMrDX
}, 0 },
2440 { "pushV", { RMrBX
}, 0 },
2441 { "pushV", { RMrSP
}, 0 },
2442 { "pushV", { RMrBP
}, 0 },
2443 { "pushV", { RMrSI
}, 0 },
2444 { "pushV", { RMrDI
}, 0 },
2446 { "popV", { RMrAX
}, 0 },
2447 { "popV", { RMrCX
}, 0 },
2448 { "popV", { RMrDX
}, 0 },
2449 { "popV", { RMrBX
}, 0 },
2450 { "popV", { RMrSP
}, 0 },
2451 { "popV", { RMrBP
}, 0 },
2452 { "popV", { RMrSI
}, 0 },
2453 { "popV", { RMrDI
}, 0 },
2455 { X86_64_TABLE (X86_64_60
) },
2456 { X86_64_TABLE (X86_64_61
) },
2457 { X86_64_TABLE (X86_64_62
) },
2458 { X86_64_TABLE (X86_64_63
) },
2459 { Bad_Opcode
}, /* seg fs */
2460 { Bad_Opcode
}, /* seg gs */
2461 { Bad_Opcode
}, /* op size prefix */
2462 { Bad_Opcode
}, /* adr size prefix */
2464 { "pushT", { sIv
}, 0 },
2465 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2466 { "pushT", { sIbT
}, 0 },
2467 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2468 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2469 { X86_64_TABLE (X86_64_6D
) },
2470 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2471 { X86_64_TABLE (X86_64_6F
) },
2473 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2474 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2475 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2476 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2477 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2478 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2479 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2480 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2482 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2483 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2484 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2485 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2486 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2487 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2488 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2489 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2491 { REG_TABLE (REG_80
) },
2492 { REG_TABLE (REG_81
) },
2493 { X86_64_TABLE (X86_64_82
) },
2494 { REG_TABLE (REG_83
) },
2495 { "testB", { Eb
, Gb
}, 0 },
2496 { "testS", { Ev
, Gv
}, 0 },
2497 { "xchgB", { Ebh2
, Gb
}, 0 },
2498 { "xchgS", { Evh2
, Gv
}, 0 },
2500 { "movB", { Ebh3
, Gb
}, 0 },
2501 { "movS", { Evh3
, Gv
}, 0 },
2502 { "movB", { Gb
, EbS
}, 0 },
2503 { "movS", { Gv
, EvS
}, 0 },
2504 { "movD", { Sv
, Sw
}, 0 },
2505 { MOD_TABLE (MOD_8D
) },
2506 { "movD", { Sw
, Sv
}, 0 },
2507 { REG_TABLE (REG_8F
) },
2509 { PREFIX_TABLE (PREFIX_90
) },
2510 { "xchgS", { RMeCX
, eAX
}, 0 },
2511 { "xchgS", { RMeDX
, eAX
}, 0 },
2512 { "xchgS", { RMeBX
, eAX
}, 0 },
2513 { "xchgS", { RMeSP
, eAX
}, 0 },
2514 { "xchgS", { RMeBP
, eAX
}, 0 },
2515 { "xchgS", { RMeSI
, eAX
}, 0 },
2516 { "xchgS", { RMeDI
, eAX
}, 0 },
2518 { "cW{t|}R", { XX
}, 0 },
2519 { "cR{t|}O", { XX
}, 0 },
2520 { X86_64_TABLE (X86_64_9A
) },
2521 { Bad_Opcode
}, /* fwait */
2522 { "pushfT", { XX
}, 0 },
2523 { "popfT", { XX
}, 0 },
2524 { "sahf", { XX
}, 0 },
2525 { "lahf", { XX
}, 0 },
2527 { "mov%LB", { AL
, Ob
}, 0 },
2528 { "mov%LS", { eAX
, Ov
}, 0 },
2529 { "mov%LB", { Ob
, AL
}, 0 },
2530 { "mov%LS", { Ov
, eAX
}, 0 },
2531 { "movs{b|}", { Ybr
, Xb
}, 0 },
2532 { "movs{R|}", { Yvr
, Xv
}, 0 },
2533 { "cmps{b|}", { Xb
, Yb
}, 0 },
2534 { "cmps{R|}", { Xv
, Yv
}, 0 },
2536 { "testB", { AL
, Ib
}, 0 },
2537 { "testS", { eAX
, Iv
}, 0 },
2538 { "stosB", { Ybr
, AL
}, 0 },
2539 { "stosS", { Yvr
, eAX
}, 0 },
2540 { "lodsB", { ALr
, Xb
}, 0 },
2541 { "lodsS", { eAXr
, Xv
}, 0 },
2542 { "scasB", { AL
, Yb
}, 0 },
2543 { "scasS", { eAX
, Yv
}, 0 },
2545 { "movB", { RMAL
, Ib
}, 0 },
2546 { "movB", { RMCL
, Ib
}, 0 },
2547 { "movB", { RMDL
, Ib
}, 0 },
2548 { "movB", { RMBL
, Ib
}, 0 },
2549 { "movB", { RMAH
, Ib
}, 0 },
2550 { "movB", { RMCH
, Ib
}, 0 },
2551 { "movB", { RMDH
, Ib
}, 0 },
2552 { "movB", { RMBH
, Ib
}, 0 },
2554 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2555 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2556 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2557 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2558 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2559 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2560 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2561 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2563 { REG_TABLE (REG_C0
) },
2564 { REG_TABLE (REG_C1
) },
2565 { "retT", { Iw
, BND
}, 0 },
2566 { "retT", { BND
}, 0 },
2567 { X86_64_TABLE (X86_64_C4
) },
2568 { X86_64_TABLE (X86_64_C5
) },
2569 { REG_TABLE (REG_C6
) },
2570 { REG_TABLE (REG_C7
) },
2572 { "enterT", { Iw
, Ib
}, 0 },
2573 { "leaveT", { XX
}, 0 },
2574 { "Jret{|f}P", { Iw
}, 0 },
2575 { "Jret{|f}P", { XX
}, 0 },
2576 { "int3", { XX
}, 0 },
2577 { "int", { Ib
}, 0 },
2578 { X86_64_TABLE (X86_64_CE
) },
2579 { "iret%LP", { XX
}, 0 },
2581 { REG_TABLE (REG_D0
) },
2582 { REG_TABLE (REG_D1
) },
2583 { REG_TABLE (REG_D2
) },
2584 { REG_TABLE (REG_D3
) },
2585 { X86_64_TABLE (X86_64_D4
) },
2586 { X86_64_TABLE (X86_64_D5
) },
2588 { "xlat", { DSBX
}, 0 },
2599 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2600 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2601 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2602 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2603 { "inB", { AL
, Ib
}, 0 },
2604 { "inG", { zAX
, Ib
}, 0 },
2605 { "outB", { Ib
, AL
}, 0 },
2606 { "outG", { Ib
, zAX
}, 0 },
2608 { X86_64_TABLE (X86_64_E8
) },
2609 { X86_64_TABLE (X86_64_E9
) },
2610 { X86_64_TABLE (X86_64_EA
) },
2611 { "jmp", { Jb
, BND
}, 0 },
2612 { "inB", { AL
, indirDX
}, 0 },
2613 { "inG", { zAX
, indirDX
}, 0 },
2614 { "outB", { indirDX
, AL
}, 0 },
2615 { "outG", { indirDX
, zAX
}, 0 },
2617 { Bad_Opcode
}, /* lock prefix */
2618 { "icebp", { XX
}, 0 },
2619 { Bad_Opcode
}, /* repne */
2620 { Bad_Opcode
}, /* repz */
2621 { "hlt", { XX
}, 0 },
2622 { "cmc", { XX
}, 0 },
2623 { REG_TABLE (REG_F6
) },
2624 { REG_TABLE (REG_F7
) },
2626 { "clc", { XX
}, 0 },
2627 { "stc", { XX
}, 0 },
2628 { "cli", { XX
}, 0 },
2629 { "sti", { XX
}, 0 },
2630 { "cld", { XX
}, 0 },
2631 { "std", { XX
}, 0 },
2632 { REG_TABLE (REG_FE
) },
2633 { REG_TABLE (REG_FF
) },
2636 static const struct dis386 dis386_twobyte
[] = {
2638 { REG_TABLE (REG_0F00
) },
2639 { REG_TABLE (REG_0F01
) },
2640 { "larS", { Gv
, Ew
}, 0 },
2641 { "lslS", { Gv
, Ew
}, 0 },
2643 { "syscall", { XX
}, 0 },
2644 { "clts", { XX
}, 0 },
2645 { "sysret%LP", { XX
}, 0 },
2647 { "invd", { XX
}, 0 },
2648 { PREFIX_TABLE (PREFIX_0F09
) },
2650 { "ud2", { XX
}, 0 },
2652 { REG_TABLE (REG_0F0D
) },
2653 { "femms", { XX
}, 0 },
2654 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2656 { PREFIX_TABLE (PREFIX_0F10
) },
2657 { PREFIX_TABLE (PREFIX_0F11
) },
2658 { PREFIX_TABLE (PREFIX_0F12
) },
2659 { MOD_TABLE (MOD_0F13
) },
2660 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2661 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2662 { PREFIX_TABLE (PREFIX_0F16
) },
2663 { MOD_TABLE (MOD_0F17
) },
2665 { REG_TABLE (REG_0F18
) },
2666 { "nopQ", { Ev
}, 0 },
2667 { PREFIX_TABLE (PREFIX_0F1A
) },
2668 { PREFIX_TABLE (PREFIX_0F1B
) },
2669 { PREFIX_TABLE (PREFIX_0F1C
) },
2670 { "nopQ", { Ev
}, 0 },
2671 { PREFIX_TABLE (PREFIX_0F1E
) },
2672 { "nopQ", { Ev
}, 0 },
2674 { "movZ", { Rm
, Cm
}, 0 },
2675 { "movZ", { Rm
, Dm
}, 0 },
2676 { "movZ", { Cm
, Rm
}, 0 },
2677 { "movZ", { Dm
, Rm
}, 0 },
2678 { MOD_TABLE (MOD_0F24
) },
2680 { MOD_TABLE (MOD_0F26
) },
2683 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2684 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2685 { PREFIX_TABLE (PREFIX_0F2A
) },
2686 { PREFIX_TABLE (PREFIX_0F2B
) },
2687 { PREFIX_TABLE (PREFIX_0F2C
) },
2688 { PREFIX_TABLE (PREFIX_0F2D
) },
2689 { PREFIX_TABLE (PREFIX_0F2E
) },
2690 { PREFIX_TABLE (PREFIX_0F2F
) },
2692 { "wrmsr", { XX
}, 0 },
2693 { "rdtsc", { XX
}, 0 },
2694 { "rdmsr", { XX
}, 0 },
2695 { "rdpmc", { XX
}, 0 },
2696 { "sysenter", { XX
}, 0 },
2697 { "sysexit", { XX
}, 0 },
2699 { "getsec", { XX
}, 0 },
2701 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2703 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2710 { "cmovoS", { Gv
, Ev
}, 0 },
2711 { "cmovnoS", { Gv
, Ev
}, 0 },
2712 { "cmovbS", { Gv
, Ev
}, 0 },
2713 { "cmovaeS", { Gv
, Ev
}, 0 },
2714 { "cmoveS", { Gv
, Ev
}, 0 },
2715 { "cmovneS", { Gv
, Ev
}, 0 },
2716 { "cmovbeS", { Gv
, Ev
}, 0 },
2717 { "cmovaS", { Gv
, Ev
}, 0 },
2719 { "cmovsS", { Gv
, Ev
}, 0 },
2720 { "cmovnsS", { Gv
, Ev
}, 0 },
2721 { "cmovpS", { Gv
, Ev
}, 0 },
2722 { "cmovnpS", { Gv
, Ev
}, 0 },
2723 { "cmovlS", { Gv
, Ev
}, 0 },
2724 { "cmovgeS", { Gv
, Ev
}, 0 },
2725 { "cmovleS", { Gv
, Ev
}, 0 },
2726 { "cmovgS", { Gv
, Ev
}, 0 },
2728 { MOD_TABLE (MOD_0F51
) },
2729 { PREFIX_TABLE (PREFIX_0F51
) },
2730 { PREFIX_TABLE (PREFIX_0F52
) },
2731 { PREFIX_TABLE (PREFIX_0F53
) },
2732 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2733 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2734 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2735 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2737 { PREFIX_TABLE (PREFIX_0F58
) },
2738 { PREFIX_TABLE (PREFIX_0F59
) },
2739 { PREFIX_TABLE (PREFIX_0F5A
) },
2740 { PREFIX_TABLE (PREFIX_0F5B
) },
2741 { PREFIX_TABLE (PREFIX_0F5C
) },
2742 { PREFIX_TABLE (PREFIX_0F5D
) },
2743 { PREFIX_TABLE (PREFIX_0F5E
) },
2744 { PREFIX_TABLE (PREFIX_0F5F
) },
2746 { PREFIX_TABLE (PREFIX_0F60
) },
2747 { PREFIX_TABLE (PREFIX_0F61
) },
2748 { PREFIX_TABLE (PREFIX_0F62
) },
2749 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2750 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2751 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2752 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2753 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2755 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2756 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2757 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2758 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2759 { PREFIX_TABLE (PREFIX_0F6C
) },
2760 { PREFIX_TABLE (PREFIX_0F6D
) },
2761 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2762 { PREFIX_TABLE (PREFIX_0F6F
) },
2764 { PREFIX_TABLE (PREFIX_0F70
) },
2765 { REG_TABLE (REG_0F71
) },
2766 { REG_TABLE (REG_0F72
) },
2767 { REG_TABLE (REG_0F73
) },
2768 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2769 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2770 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2771 { "emms", { XX
}, PREFIX_OPCODE
},
2773 { PREFIX_TABLE (PREFIX_0F78
) },
2774 { PREFIX_TABLE (PREFIX_0F79
) },
2777 { PREFIX_TABLE (PREFIX_0F7C
) },
2778 { PREFIX_TABLE (PREFIX_0F7D
) },
2779 { PREFIX_TABLE (PREFIX_0F7E
) },
2780 { PREFIX_TABLE (PREFIX_0F7F
) },
2782 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2783 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2784 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2785 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2786 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2787 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2788 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2789 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2791 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2792 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2793 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2794 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2795 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2796 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2797 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2798 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2800 { "seto", { Eb
}, 0 },
2801 { "setno", { Eb
}, 0 },
2802 { "setb", { Eb
}, 0 },
2803 { "setae", { Eb
}, 0 },
2804 { "sete", { Eb
}, 0 },
2805 { "setne", { Eb
}, 0 },
2806 { "setbe", { Eb
}, 0 },
2807 { "seta", { Eb
}, 0 },
2809 { "sets", { Eb
}, 0 },
2810 { "setns", { Eb
}, 0 },
2811 { "setp", { Eb
}, 0 },
2812 { "setnp", { Eb
}, 0 },
2813 { "setl", { Eb
}, 0 },
2814 { "setge", { Eb
}, 0 },
2815 { "setle", { Eb
}, 0 },
2816 { "setg", { Eb
}, 0 },
2818 { "pushT", { fs
}, 0 },
2819 { "popT", { fs
}, 0 },
2820 { "cpuid", { XX
}, 0 },
2821 { "btS", { Ev
, Gv
}, 0 },
2822 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2823 { "shldS", { Ev
, Gv
, CL
}, 0 },
2824 { REG_TABLE (REG_0FA6
) },
2825 { REG_TABLE (REG_0FA7
) },
2827 { "pushT", { gs
}, 0 },
2828 { "popT", { gs
}, 0 },
2829 { "rsm", { XX
}, 0 },
2830 { "btsS", { Evh1
, Gv
}, 0 },
2831 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2832 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2833 { REG_TABLE (REG_0FAE
) },
2834 { "imulS", { Gv
, Ev
}, 0 },
2836 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2837 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2838 { MOD_TABLE (MOD_0FB2
) },
2839 { "btrS", { Evh1
, Gv
}, 0 },
2840 { MOD_TABLE (MOD_0FB4
) },
2841 { MOD_TABLE (MOD_0FB5
) },
2842 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2843 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2845 { PREFIX_TABLE (PREFIX_0FB8
) },
2846 { "ud1S", { Gv
, Ev
}, 0 },
2847 { REG_TABLE (REG_0FBA
) },
2848 { "btcS", { Evh1
, Gv
}, 0 },
2849 { PREFIX_TABLE (PREFIX_0FBC
) },
2850 { PREFIX_TABLE (PREFIX_0FBD
) },
2851 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2852 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2854 { "xaddB", { Ebh1
, Gb
}, 0 },
2855 { "xaddS", { Evh1
, Gv
}, 0 },
2856 { PREFIX_TABLE (PREFIX_0FC2
) },
2857 { MOD_TABLE (MOD_0FC3
) },
2858 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
2859 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
2860 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2861 { REG_TABLE (REG_0FC7
) },
2863 { "bswap", { RMeAX
}, 0 },
2864 { "bswap", { RMeCX
}, 0 },
2865 { "bswap", { RMeDX
}, 0 },
2866 { "bswap", { RMeBX
}, 0 },
2867 { "bswap", { RMeSP
}, 0 },
2868 { "bswap", { RMeBP
}, 0 },
2869 { "bswap", { RMeSI
}, 0 },
2870 { "bswap", { RMeDI
}, 0 },
2872 { PREFIX_TABLE (PREFIX_0FD0
) },
2873 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2874 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2875 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2876 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2877 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2878 { PREFIX_TABLE (PREFIX_0FD6
) },
2879 { MOD_TABLE (MOD_0FD7
) },
2881 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2882 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2883 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2884 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2885 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2886 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2887 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2888 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2890 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2891 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2892 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2893 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2894 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2895 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2896 { PREFIX_TABLE (PREFIX_0FE6
) },
2897 { PREFIX_TABLE (PREFIX_0FE7
) },
2899 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
2900 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
2901 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
2902 { "por", { MX
, EM
}, PREFIX_OPCODE
},
2903 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
2904 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
2905 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
2906 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
2908 { PREFIX_TABLE (PREFIX_0FF0
) },
2909 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
2910 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
2911 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
2912 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
2913 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
2914 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
2915 { PREFIX_TABLE (PREFIX_0FF7
) },
2917 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
2918 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
2919 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
2920 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
2921 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
2922 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
2923 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
2924 { "ud0S", { Gv
, Ev
}, 0 },
2927 static const unsigned char onebyte_has_modrm
[256] = {
2928 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2929 /* ------------------------------- */
2930 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2931 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2932 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2933 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2934 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2935 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2936 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2937 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2938 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2939 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2940 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2941 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2942 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2943 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2944 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2945 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2946 /* ------------------------------- */
2947 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2950 static const unsigned char twobyte_has_modrm
[256] = {
2951 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2952 /* ------------------------------- */
2953 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2954 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2955 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2956 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2957 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2958 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2959 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2960 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2961 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2962 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2963 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2964 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2965 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2966 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2967 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2968 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2969 /* ------------------------------- */
2970 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2973 static char obuf
[100];
2975 static char *mnemonicendp
;
2976 static char scratchbuf
[100];
2977 static unsigned char *start_codep
;
2978 static unsigned char *insn_codep
;
2979 static unsigned char *codep
;
2980 static unsigned char *end_codep
;
2981 static int last_lock_prefix
;
2982 static int last_repz_prefix
;
2983 static int last_repnz_prefix
;
2984 static int last_data_prefix
;
2985 static int last_addr_prefix
;
2986 static int last_rex_prefix
;
2987 static int last_seg_prefix
;
2988 static int fwait_prefix
;
2989 /* The active segment register prefix. */
2990 static int active_seg_prefix
;
2991 #define MAX_CODE_LENGTH 15
2992 /* We can up to 14 prefixes since the maximum instruction length is
2994 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
2995 static disassemble_info
*the_info
;
3003 static unsigned char need_modrm
;
3013 int register_specifier
;
3020 int mask_register_specifier
;
3026 static unsigned char need_vex
;
3027 static unsigned char need_vex_reg
;
3028 static unsigned char vex_w_done
;
3036 /* If we are accessing mod/rm/reg without need_modrm set, then the
3037 values are stale. Hitting this abort likely indicates that you
3038 need to update onebyte_has_modrm or twobyte_has_modrm. */
3039 #define MODRM_CHECK if (!need_modrm) abort ()
3041 static const char **names64
;
3042 static const char **names32
;
3043 static const char **names16
;
3044 static const char **names8
;
3045 static const char **names8rex
;
3046 static const char **names_seg
;
3047 static const char *index64
;
3048 static const char *index32
;
3049 static const char **index16
;
3050 static const char **names_bnd
;
3052 static const char *intel_names64
[] = {
3053 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3054 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3056 static const char *intel_names32
[] = {
3057 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3058 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3060 static const char *intel_names16
[] = {
3061 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3062 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3064 static const char *intel_names8
[] = {
3065 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3067 static const char *intel_names8rex
[] = {
3068 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3069 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3071 static const char *intel_names_seg
[] = {
3072 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3074 static const char *intel_index64
= "riz";
3075 static const char *intel_index32
= "eiz";
3076 static const char *intel_index16
[] = {
3077 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3080 static const char *att_names64
[] = {
3081 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3082 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3084 static const char *att_names32
[] = {
3085 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3086 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3088 static const char *att_names16
[] = {
3089 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3090 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3092 static const char *att_names8
[] = {
3093 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3095 static const char *att_names8rex
[] = {
3096 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3097 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3099 static const char *att_names_seg
[] = {
3100 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3102 static const char *att_index64
= "%riz";
3103 static const char *att_index32
= "%eiz";
3104 static const char *att_index16
[] = {
3105 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3108 static const char **names_mm
;
3109 static const char *intel_names_mm
[] = {
3110 "mm0", "mm1", "mm2", "mm3",
3111 "mm4", "mm5", "mm6", "mm7"
3113 static const char *att_names_mm
[] = {
3114 "%mm0", "%mm1", "%mm2", "%mm3",
3115 "%mm4", "%mm5", "%mm6", "%mm7"
3118 static const char *intel_names_bnd
[] = {
3119 "bnd0", "bnd1", "bnd2", "bnd3"
3122 static const char *att_names_bnd
[] = {
3123 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3126 static const char **names_xmm
;
3127 static const char *intel_names_xmm
[] = {
3128 "xmm0", "xmm1", "xmm2", "xmm3",
3129 "xmm4", "xmm5", "xmm6", "xmm7",
3130 "xmm8", "xmm9", "xmm10", "xmm11",
3131 "xmm12", "xmm13", "xmm14", "xmm15",
3132 "xmm16", "xmm17", "xmm18", "xmm19",
3133 "xmm20", "xmm21", "xmm22", "xmm23",
3134 "xmm24", "xmm25", "xmm26", "xmm27",
3135 "xmm28", "xmm29", "xmm30", "xmm31"
3137 static const char *att_names_xmm
[] = {
3138 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3139 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3140 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3141 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3142 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3143 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3144 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3145 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3148 static const char **names_ymm
;
3149 static const char *intel_names_ymm
[] = {
3150 "ymm0", "ymm1", "ymm2", "ymm3",
3151 "ymm4", "ymm5", "ymm6", "ymm7",
3152 "ymm8", "ymm9", "ymm10", "ymm11",
3153 "ymm12", "ymm13", "ymm14", "ymm15",
3154 "ymm16", "ymm17", "ymm18", "ymm19",
3155 "ymm20", "ymm21", "ymm22", "ymm23",
3156 "ymm24", "ymm25", "ymm26", "ymm27",
3157 "ymm28", "ymm29", "ymm30", "ymm31"
3159 static const char *att_names_ymm
[] = {
3160 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3161 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3162 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3163 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3164 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3165 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3166 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3167 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3170 static const char **names_zmm
;
3171 static const char *intel_names_zmm
[] = {
3172 "zmm0", "zmm1", "zmm2", "zmm3",
3173 "zmm4", "zmm5", "zmm6", "zmm7",
3174 "zmm8", "zmm9", "zmm10", "zmm11",
3175 "zmm12", "zmm13", "zmm14", "zmm15",
3176 "zmm16", "zmm17", "zmm18", "zmm19",
3177 "zmm20", "zmm21", "zmm22", "zmm23",
3178 "zmm24", "zmm25", "zmm26", "zmm27",
3179 "zmm28", "zmm29", "zmm30", "zmm31"
3181 static const char *att_names_zmm
[] = {
3182 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3183 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3184 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3185 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3186 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3187 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3188 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3189 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3192 static const char **names_mask
;
3193 static const char *intel_names_mask
[] = {
3194 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3196 static const char *att_names_mask
[] = {
3197 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3200 static const char *names_rounding
[] =
3208 static const struct dis386 reg_table
[][8] = {
3211 { "addA", { Ebh1
, Ib
}, 0 },
3212 { "orA", { Ebh1
, Ib
}, 0 },
3213 { "adcA", { Ebh1
, Ib
}, 0 },
3214 { "sbbA", { Ebh1
, Ib
}, 0 },
3215 { "andA", { Ebh1
, Ib
}, 0 },
3216 { "subA", { Ebh1
, Ib
}, 0 },
3217 { "xorA", { Ebh1
, Ib
}, 0 },
3218 { "cmpA", { Eb
, Ib
}, 0 },
3222 { "addQ", { Evh1
, Iv
}, 0 },
3223 { "orQ", { Evh1
, Iv
}, 0 },
3224 { "adcQ", { Evh1
, Iv
}, 0 },
3225 { "sbbQ", { Evh1
, Iv
}, 0 },
3226 { "andQ", { Evh1
, Iv
}, 0 },
3227 { "subQ", { Evh1
, Iv
}, 0 },
3228 { "xorQ", { Evh1
, Iv
}, 0 },
3229 { "cmpQ", { Ev
, Iv
}, 0 },
3233 { "addQ", { Evh1
, sIb
}, 0 },
3234 { "orQ", { Evh1
, sIb
}, 0 },
3235 { "adcQ", { Evh1
, sIb
}, 0 },
3236 { "sbbQ", { Evh1
, sIb
}, 0 },
3237 { "andQ", { Evh1
, sIb
}, 0 },
3238 { "subQ", { Evh1
, sIb
}, 0 },
3239 { "xorQ", { Evh1
, sIb
}, 0 },
3240 { "cmpQ", { Ev
, sIb
}, 0 },
3244 { "popU", { stackEv
}, 0 },
3245 { XOP_8F_TABLE (XOP_09
) },
3249 { XOP_8F_TABLE (XOP_09
) },
3253 { "rolA", { Eb
, Ib
}, 0 },
3254 { "rorA", { Eb
, Ib
}, 0 },
3255 { "rclA", { Eb
, Ib
}, 0 },
3256 { "rcrA", { Eb
, Ib
}, 0 },
3257 { "shlA", { Eb
, Ib
}, 0 },
3258 { "shrA", { Eb
, Ib
}, 0 },
3259 { "shlA", { Eb
, Ib
}, 0 },
3260 { "sarA", { Eb
, Ib
}, 0 },
3264 { "rolQ", { Ev
, Ib
}, 0 },
3265 { "rorQ", { Ev
, Ib
}, 0 },
3266 { "rclQ", { Ev
, Ib
}, 0 },
3267 { "rcrQ", { Ev
, Ib
}, 0 },
3268 { "shlQ", { Ev
, Ib
}, 0 },
3269 { "shrQ", { Ev
, Ib
}, 0 },
3270 { "shlQ", { Ev
, Ib
}, 0 },
3271 { "sarQ", { Ev
, Ib
}, 0 },
3275 { "movA", { Ebh3
, Ib
}, 0 },
3282 { MOD_TABLE (MOD_C6_REG_7
) },
3286 { "movQ", { Evh3
, Iv
}, 0 },
3293 { MOD_TABLE (MOD_C7_REG_7
) },
3297 { "rolA", { Eb
, I1
}, 0 },
3298 { "rorA", { Eb
, I1
}, 0 },
3299 { "rclA", { Eb
, I1
}, 0 },
3300 { "rcrA", { Eb
, I1
}, 0 },
3301 { "shlA", { Eb
, I1
}, 0 },
3302 { "shrA", { Eb
, I1
}, 0 },
3303 { "shlA", { Eb
, I1
}, 0 },
3304 { "sarA", { Eb
, I1
}, 0 },
3308 { "rolQ", { Ev
, I1
}, 0 },
3309 { "rorQ", { Ev
, I1
}, 0 },
3310 { "rclQ", { Ev
, I1
}, 0 },
3311 { "rcrQ", { Ev
, I1
}, 0 },
3312 { "shlQ", { Ev
, I1
}, 0 },
3313 { "shrQ", { Ev
, I1
}, 0 },
3314 { "shlQ", { Ev
, I1
}, 0 },
3315 { "sarQ", { Ev
, I1
}, 0 },
3319 { "rolA", { Eb
, CL
}, 0 },
3320 { "rorA", { Eb
, CL
}, 0 },
3321 { "rclA", { Eb
, CL
}, 0 },
3322 { "rcrA", { Eb
, CL
}, 0 },
3323 { "shlA", { Eb
, CL
}, 0 },
3324 { "shrA", { Eb
, CL
}, 0 },
3325 { "shlA", { Eb
, CL
}, 0 },
3326 { "sarA", { Eb
, CL
}, 0 },
3330 { "rolQ", { Ev
, CL
}, 0 },
3331 { "rorQ", { Ev
, CL
}, 0 },
3332 { "rclQ", { Ev
, CL
}, 0 },
3333 { "rcrQ", { Ev
, CL
}, 0 },
3334 { "shlQ", { Ev
, CL
}, 0 },
3335 { "shrQ", { Ev
, CL
}, 0 },
3336 { "shlQ", { Ev
, CL
}, 0 },
3337 { "sarQ", { Ev
, CL
}, 0 },
3341 { "testA", { Eb
, Ib
}, 0 },
3342 { "testA", { Eb
, Ib
}, 0 },
3343 { "notA", { Ebh1
}, 0 },
3344 { "negA", { Ebh1
}, 0 },
3345 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3346 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3347 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3348 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3352 { "testQ", { Ev
, Iv
}, 0 },
3353 { "testQ", { Ev
, Iv
}, 0 },
3354 { "notQ", { Evh1
}, 0 },
3355 { "negQ", { Evh1
}, 0 },
3356 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3357 { "imulQ", { Ev
}, 0 },
3358 { "divQ", { Ev
}, 0 },
3359 { "idivQ", { Ev
}, 0 },
3363 { "incA", { Ebh1
}, 0 },
3364 { "decA", { Ebh1
}, 0 },
3368 { "incQ", { Evh1
}, 0 },
3369 { "decQ", { Evh1
}, 0 },
3370 { "call{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3371 { MOD_TABLE (MOD_FF_REG_3
) },
3372 { "jmp{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3373 { MOD_TABLE (MOD_FF_REG_5
) },
3374 { "pushU", { stackEv
}, 0 },
3379 { "sldtD", { Sv
}, 0 },
3380 { "strD", { Sv
}, 0 },
3381 { "lldt", { Ew
}, 0 },
3382 { "ltr", { Ew
}, 0 },
3383 { "verr", { Ew
}, 0 },
3384 { "verw", { Ew
}, 0 },
3390 { MOD_TABLE (MOD_0F01_REG_0
) },
3391 { MOD_TABLE (MOD_0F01_REG_1
) },
3392 { MOD_TABLE (MOD_0F01_REG_2
) },
3393 { MOD_TABLE (MOD_0F01_REG_3
) },
3394 { "smswD", { Sv
}, 0 },
3395 { MOD_TABLE (MOD_0F01_REG_5
) },
3396 { "lmsw", { Ew
}, 0 },
3397 { MOD_TABLE (MOD_0F01_REG_7
) },
3401 { "prefetch", { Mb
}, 0 },
3402 { "prefetchw", { Mb
}, 0 },
3403 { "prefetchwt1", { Mb
}, 0 },
3404 { "prefetch", { Mb
}, 0 },
3405 { "prefetch", { Mb
}, 0 },
3406 { "prefetch", { Mb
}, 0 },
3407 { "prefetch", { Mb
}, 0 },
3408 { "prefetch", { Mb
}, 0 },
3412 { MOD_TABLE (MOD_0F18_REG_0
) },
3413 { MOD_TABLE (MOD_0F18_REG_1
) },
3414 { MOD_TABLE (MOD_0F18_REG_2
) },
3415 { MOD_TABLE (MOD_0F18_REG_3
) },
3416 { MOD_TABLE (MOD_0F18_REG_4
) },
3417 { MOD_TABLE (MOD_0F18_REG_5
) },
3418 { MOD_TABLE (MOD_0F18_REG_6
) },
3419 { MOD_TABLE (MOD_0F18_REG_7
) },
3421 /* REG_0F1C_MOD_0 */
3423 { "cldemote", { Mb
}, 0 },
3424 { "nopQ", { Ev
}, 0 },
3425 { "nopQ", { Ev
}, 0 },
3426 { "nopQ", { Ev
}, 0 },
3427 { "nopQ", { Ev
}, 0 },
3428 { "nopQ", { Ev
}, 0 },
3429 { "nopQ", { Ev
}, 0 },
3430 { "nopQ", { Ev
}, 0 },
3432 /* REG_0F1E_MOD_3 */
3434 { "nopQ", { Ev
}, 0 },
3435 { "rdsspK", { Rdq
}, PREFIX_OPCODE
},
3436 { "nopQ", { Ev
}, 0 },
3437 { "nopQ", { Ev
}, 0 },
3438 { "nopQ", { Ev
}, 0 },
3439 { "nopQ", { Ev
}, 0 },
3440 { "nopQ", { Ev
}, 0 },
3441 { RM_TABLE (RM_0F1E_MOD_3_REG_7
) },
3447 { MOD_TABLE (MOD_0F71_REG_2
) },
3449 { MOD_TABLE (MOD_0F71_REG_4
) },
3451 { MOD_TABLE (MOD_0F71_REG_6
) },
3457 { MOD_TABLE (MOD_0F72_REG_2
) },
3459 { MOD_TABLE (MOD_0F72_REG_4
) },
3461 { MOD_TABLE (MOD_0F72_REG_6
) },
3467 { MOD_TABLE (MOD_0F73_REG_2
) },
3468 { MOD_TABLE (MOD_0F73_REG_3
) },
3471 { MOD_TABLE (MOD_0F73_REG_6
) },
3472 { MOD_TABLE (MOD_0F73_REG_7
) },
3476 { "montmul", { { OP_0f07
, 0 } }, 0 },
3477 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3478 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3482 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3483 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3484 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3485 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3486 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3487 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3491 { MOD_TABLE (MOD_0FAE_REG_0
) },
3492 { MOD_TABLE (MOD_0FAE_REG_1
) },
3493 { MOD_TABLE (MOD_0FAE_REG_2
) },
3494 { MOD_TABLE (MOD_0FAE_REG_3
) },
3495 { MOD_TABLE (MOD_0FAE_REG_4
) },
3496 { MOD_TABLE (MOD_0FAE_REG_5
) },
3497 { MOD_TABLE (MOD_0FAE_REG_6
) },
3498 { MOD_TABLE (MOD_0FAE_REG_7
) },
3506 { "btQ", { Ev
, Ib
}, 0 },
3507 { "btsQ", { Evh1
, Ib
}, 0 },
3508 { "btrQ", { Evh1
, Ib
}, 0 },
3509 { "btcQ", { Evh1
, Ib
}, 0 },
3514 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3516 { MOD_TABLE (MOD_0FC7_REG_3
) },
3517 { MOD_TABLE (MOD_0FC7_REG_4
) },
3518 { MOD_TABLE (MOD_0FC7_REG_5
) },
3519 { MOD_TABLE (MOD_0FC7_REG_6
) },
3520 { MOD_TABLE (MOD_0FC7_REG_7
) },
3526 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3528 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3530 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3536 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3538 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3540 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3546 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3547 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3550 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3551 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3557 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3558 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3560 /* REG_VEX_0F38F3 */
3563 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3564 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3565 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3569 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3570 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3574 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3575 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3577 /* REG_XOP_TBM_01 */
3580 { "blcfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3581 { "blsfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3582 { "blcs", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3583 { "tzmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3584 { "blcic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3585 { "blsic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3586 { "t1mskc", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3588 /* REG_XOP_TBM_02 */
3591 { "blcmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3596 { "blci", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3598 #define NEED_REG_TABLE
3599 #include "i386-dis-evex.h"
3600 #undef NEED_REG_TABLE
3603 static const struct dis386 prefix_table
[][4] = {
3606 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3607 { "pause", { XX
}, 0 },
3608 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3609 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3612 /* PREFIX_MOD_0_0F01_REG_5 */
3615 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3618 /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3621 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3624 /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3627 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3632 { "wbinvd", { XX
}, 0 },
3633 { "wbnoinvd", { XX
}, 0 },
3638 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3639 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3640 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3641 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3646 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3647 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3648 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3649 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3654 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3655 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3656 { "movlpd", { XM
, EXq
}, PREFIX_OPCODE
},
3657 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3662 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3663 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3664 { "movhpd", { XM
, EXq
}, PREFIX_OPCODE
},
3669 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3670 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3671 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3672 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3677 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3678 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3679 { "bndmov", { EbndS
, Gbnd
}, 0 },
3680 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3685 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3686 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3687 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3688 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3693 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3694 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3695 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3696 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3701 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3702 { "cvtsi2ss%LQ", { XM
, Ev
}, PREFIX_OPCODE
},
3703 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3704 { "cvtsi2sd%LQ", { XM
, Ev
}, 0 },
3709 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3710 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3711 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3712 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3717 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3718 { "cvttss2si", { Gv
, EXd
}, PREFIX_OPCODE
},
3719 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3720 { "cvttsd2si", { Gv
, EXq
}, PREFIX_OPCODE
},
3725 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3726 { "cvtss2si", { Gv
, EXd
}, PREFIX_OPCODE
},
3727 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3728 { "cvtsd2si", { Gv
, EXq
}, PREFIX_OPCODE
},
3733 { "ucomiss",{ XM
, EXd
}, 0 },
3735 { "ucomisd",{ XM
, EXq
}, 0 },
3740 { "comiss", { XM
, EXd
}, 0 },
3742 { "comisd", { XM
, EXq
}, 0 },
3747 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3748 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3749 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3750 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3755 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3756 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3761 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3762 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3767 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3768 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3769 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3770 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3775 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3776 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3777 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3778 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3783 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3784 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3785 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3786 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3791 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3792 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3793 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3798 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3799 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3800 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3801 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3806 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3807 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3808 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3809 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3814 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3815 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3816 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3817 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3822 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3823 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3824 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3825 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3830 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3832 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3837 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3839 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3844 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3846 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3853 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3860 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3865 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3866 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3867 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3872 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3873 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3874 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3875 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3878 /* PREFIX_0F73_REG_3 */
3882 { "psrldq", { XS
, Ib
}, 0 },
3885 /* PREFIX_0F73_REG_7 */
3889 { "pslldq", { XS
, Ib
}, 0 },
3894 {"vmread", { Em
, Gm
}, 0 },
3896 {"extrq", { XS
, Ib
, Ib
}, 0 },
3897 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3902 {"vmwrite", { Gm
, Em
}, 0 },
3904 {"extrq", { XM
, XS
}, 0 },
3905 {"insertq", { XM
, XS
}, 0 },
3912 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3913 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3920 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3921 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3926 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3927 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3928 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3933 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3934 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3935 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3938 /* PREFIX_0FAE_REG_0 */
3941 { "rdfsbase", { Ev
}, 0 },
3944 /* PREFIX_0FAE_REG_1 */
3947 { "rdgsbase", { Ev
}, 0 },
3950 /* PREFIX_0FAE_REG_2 */
3953 { "wrfsbase", { Ev
}, 0 },
3956 /* PREFIX_0FAE_REG_3 */
3959 { "wrgsbase", { Ev
}, 0 },
3962 /* PREFIX_MOD_0_0FAE_REG_4 */
3964 { "xsave", { FXSAVE
}, 0 },
3965 { "ptwrite%LQ", { Edq
}, 0 },
3968 /* PREFIX_MOD_3_0FAE_REG_4 */
3971 { "ptwrite%LQ", { Edq
}, 0 },
3974 /* PREFIX_MOD_0_0FAE_REG_5 */
3976 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
3979 /* PREFIX_MOD_3_0FAE_REG_5 */
3981 { "lfence", { Skip_MODRM
}, 0 },
3982 { "incsspK", { Rdq
}, PREFIX_OPCODE
},
3985 /* PREFIX_MOD_0_0FAE_REG_6 */
3987 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
3988 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
3989 { "clwb", { Mb
}, PREFIX_OPCODE
},
3992 /* PREFIX_MOD_1_0FAE_REG_6 */
3994 { RM_TABLE (RM_0FAE_REG_6
) },
3995 { "umonitor", { Eva
}, PREFIX_OPCODE
},
3996 { "tpause", { Edq
}, PREFIX_OPCODE
},
3997 { "umwait", { Edq
}, PREFIX_OPCODE
},
4000 /* PREFIX_0FAE_REG_7 */
4002 { "clflush", { Mb
}, 0 },
4004 { "clflushopt", { Mb
}, 0 },
4010 { "popcntS", { Gv
, Ev
}, 0 },
4015 { "bsfS", { Gv
, Ev
}, 0 },
4016 { "tzcntS", { Gv
, Ev
}, 0 },
4017 { "bsfS", { Gv
, Ev
}, 0 },
4022 { "bsrS", { Gv
, Ev
}, 0 },
4023 { "lzcntS", { Gv
, Ev
}, 0 },
4024 { "bsrS", { Gv
, Ev
}, 0 },
4029 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4030 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4031 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4032 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4035 /* PREFIX_MOD_0_0FC3 */
4037 { "movntiS", { Ev
, Gv
}, PREFIX_OPCODE
},
4040 /* PREFIX_MOD_0_0FC7_REG_6 */
4042 { "vmptrld",{ Mq
}, 0 },
4043 { "vmxon", { Mq
}, 0 },
4044 { "vmclear",{ Mq
}, 0 },
4047 /* PREFIX_MOD_3_0FC7_REG_6 */
4049 { "rdrand", { Ev
}, 0 },
4051 { "rdrand", { Ev
}, 0 }
4054 /* PREFIX_MOD_3_0FC7_REG_7 */
4056 { "rdseed", { Ev
}, 0 },
4057 { "rdpid", { Em
}, 0 },
4058 { "rdseed", { Ev
}, 0 },
4065 { "addsubpd", { XM
, EXx
}, 0 },
4066 { "addsubps", { XM
, EXx
}, 0 },
4072 { "movq2dq",{ XM
, MS
}, 0 },
4073 { "movq", { EXqS
, XM
}, 0 },
4074 { "movdq2q",{ MX
, XS
}, 0 },
4080 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4081 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4082 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4087 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4089 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4097 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4102 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4104 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4111 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4118 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4125 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4132 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4139 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4146 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4153 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4160 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4167 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4174 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4181 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4188 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4195 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4202 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4209 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4216 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4223 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4230 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4237 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4244 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4251 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4258 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4265 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4272 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4279 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4286 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4293 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4300 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4307 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4314 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4321 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4328 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4335 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4342 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4347 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4352 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4357 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4362 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4367 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4372 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4379 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_OPCODE
},
4386 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4393 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4400 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4407 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4414 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4419 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4421 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4422 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4427 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4429 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4430 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4437 { MOD_TABLE (MOD_0F38F5_PREFIX_2
) },
4442 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
4443 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4444 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4451 { MOD_TABLE (MOD_0F38F8_PREFIX_1
) },
4452 { MOD_TABLE (MOD_0F38F8_PREFIX_2
) },
4453 { MOD_TABLE (MOD_0F38F8_PREFIX_3
) },
4458 { MOD_TABLE (MOD_0F38F9_PREFIX_0
) },
4465 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4472 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4479 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4486 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4493 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4500 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4507 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4514 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4521 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4528 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4535 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4542 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4549 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4556 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4563 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4570 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4577 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4584 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4591 { "pcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4598 { "pcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4605 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4612 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4617 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4624 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4631 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4638 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4641 /* PREFIX_VEX_0F10 */
4643 { "vmovups", { XM
, EXx
}, 0 },
4644 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
}, 0 },
4645 { "vmovupd", { XM
, EXx
}, 0 },
4646 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
}, 0 },
4649 /* PREFIX_VEX_0F11 */
4651 { "vmovups", { EXxS
, XM
}, 0 },
4652 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
4653 { "vmovupd", { EXxS
, XM
}, 0 },
4654 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
4657 /* PREFIX_VEX_0F12 */
4659 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4660 { "vmovsldup", { XM
, EXx
}, 0 },
4661 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4662 { "vmovddup", { XM
, EXymmq
}, 0 },
4665 /* PREFIX_VEX_0F16 */
4667 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4668 { "vmovshdup", { XM
, EXx
}, 0 },
4669 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4672 /* PREFIX_VEX_0F2A */
4675 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1
) },
4677 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3
) },
4680 /* PREFIX_VEX_0F2C */
4683 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1
) },
4685 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3
) },
4688 /* PREFIX_VEX_0F2D */
4691 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1
) },
4693 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3
) },
4696 /* PREFIX_VEX_0F2E */
4698 { "vucomiss", { XMScalar
, EXdScalar
}, 0 },
4700 { "vucomisd", { XMScalar
, EXqScalar
}, 0 },
4703 /* PREFIX_VEX_0F2F */
4705 { "vcomiss", { XMScalar
, EXdScalar
}, 0 },
4707 { "vcomisd", { XMScalar
, EXqScalar
}, 0 },
4710 /* PREFIX_VEX_0F41 */
4712 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4714 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4717 /* PREFIX_VEX_0F42 */
4719 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4721 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4724 /* PREFIX_VEX_0F44 */
4726 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4728 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4731 /* PREFIX_VEX_0F45 */
4733 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4735 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4738 /* PREFIX_VEX_0F46 */
4740 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4742 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4745 /* PREFIX_VEX_0F47 */
4747 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4749 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4752 /* PREFIX_VEX_0F4A */
4754 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4756 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4759 /* PREFIX_VEX_0F4B */
4761 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4763 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4766 /* PREFIX_VEX_0F51 */
4768 { "vsqrtps", { XM
, EXx
}, 0 },
4769 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4770 { "vsqrtpd", { XM
, EXx
}, 0 },
4771 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4774 /* PREFIX_VEX_0F52 */
4776 { "vrsqrtps", { XM
, EXx
}, 0 },
4777 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4780 /* PREFIX_VEX_0F53 */
4782 { "vrcpps", { XM
, EXx
}, 0 },
4783 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4786 /* PREFIX_VEX_0F58 */
4788 { "vaddps", { XM
, Vex
, EXx
}, 0 },
4789 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4790 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
4791 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4794 /* PREFIX_VEX_0F59 */
4796 { "vmulps", { XM
, Vex
, EXx
}, 0 },
4797 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4798 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
4799 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4802 /* PREFIX_VEX_0F5A */
4804 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
4805 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4806 { "vcvtpd2ps%XY",{ XMM
, EXx
}, 0 },
4807 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4810 /* PREFIX_VEX_0F5B */
4812 { "vcvtdq2ps", { XM
, EXx
}, 0 },
4813 { "vcvttps2dq", { XM
, EXx
}, 0 },
4814 { "vcvtps2dq", { XM
, EXx
}, 0 },
4817 /* PREFIX_VEX_0F5C */
4819 { "vsubps", { XM
, Vex
, EXx
}, 0 },
4820 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4821 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
4822 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4825 /* PREFIX_VEX_0F5D */
4827 { "vminps", { XM
, Vex
, EXx
}, 0 },
4828 { "vminss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4829 { "vminpd", { XM
, Vex
, EXx
}, 0 },
4830 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4833 /* PREFIX_VEX_0F5E */
4835 { "vdivps", { XM
, Vex
, EXx
}, 0 },
4836 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4837 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
4838 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4841 /* PREFIX_VEX_0F5F */
4843 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
4844 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4845 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
4846 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4849 /* PREFIX_VEX_0F60 */
4853 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
4856 /* PREFIX_VEX_0F61 */
4860 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
4863 /* PREFIX_VEX_0F62 */
4867 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
4870 /* PREFIX_VEX_0F63 */
4874 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
4877 /* PREFIX_VEX_0F64 */
4881 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
4884 /* PREFIX_VEX_0F65 */
4888 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
4891 /* PREFIX_VEX_0F66 */
4895 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
4898 /* PREFIX_VEX_0F67 */
4902 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
4905 /* PREFIX_VEX_0F68 */
4909 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
4912 /* PREFIX_VEX_0F69 */
4916 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
4919 /* PREFIX_VEX_0F6A */
4923 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
4926 /* PREFIX_VEX_0F6B */
4930 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
4933 /* PREFIX_VEX_0F6C */
4937 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
4940 /* PREFIX_VEX_0F6D */
4944 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
4947 /* PREFIX_VEX_0F6E */
4951 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4954 /* PREFIX_VEX_0F6F */
4957 { "vmovdqu", { XM
, EXx
}, 0 },
4958 { "vmovdqa", { XM
, EXx
}, 0 },
4961 /* PREFIX_VEX_0F70 */
4964 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
4965 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
4966 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
4969 /* PREFIX_VEX_0F71_REG_2 */
4973 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
4976 /* PREFIX_VEX_0F71_REG_4 */
4980 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
4983 /* PREFIX_VEX_0F71_REG_6 */
4987 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
4990 /* PREFIX_VEX_0F72_REG_2 */
4994 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
4997 /* PREFIX_VEX_0F72_REG_4 */
5001 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
5004 /* PREFIX_VEX_0F72_REG_6 */
5008 { "vpslld", { Vex
, XS
, Ib
}, 0 },
5011 /* PREFIX_VEX_0F73_REG_2 */
5015 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
5018 /* PREFIX_VEX_0F73_REG_3 */
5022 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
5025 /* PREFIX_VEX_0F73_REG_6 */
5029 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
5032 /* PREFIX_VEX_0F73_REG_7 */
5036 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
5039 /* PREFIX_VEX_0F74 */
5043 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
5046 /* PREFIX_VEX_0F75 */
5050 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
5053 /* PREFIX_VEX_0F76 */
5057 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
5060 /* PREFIX_VEX_0F77 */
5062 { VEX_LEN_TABLE (VEX_LEN_0F77_P_0
) },
5065 /* PREFIX_VEX_0F7C */
5069 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
5070 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
5073 /* PREFIX_VEX_0F7D */
5077 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
5078 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
5081 /* PREFIX_VEX_0F7E */
5084 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5085 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5088 /* PREFIX_VEX_0F7F */
5091 { "vmovdqu", { EXxS
, XM
}, 0 },
5092 { "vmovdqa", { EXxS
, XM
}, 0 },
5095 /* PREFIX_VEX_0F90 */
5097 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5099 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5102 /* PREFIX_VEX_0F91 */
5104 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5106 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5109 /* PREFIX_VEX_0F92 */
5111 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5113 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5114 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5117 /* PREFIX_VEX_0F93 */
5119 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5121 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5122 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5125 /* PREFIX_VEX_0F98 */
5127 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5129 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5132 /* PREFIX_VEX_0F99 */
5134 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5136 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5139 /* PREFIX_VEX_0FC2 */
5141 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
5142 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
}, 0 },
5143 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
5144 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
}, 0 },
5147 /* PREFIX_VEX_0FC4 */
5151 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5154 /* PREFIX_VEX_0FC5 */
5158 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5161 /* PREFIX_VEX_0FD0 */
5165 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
5166 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
5169 /* PREFIX_VEX_0FD1 */
5173 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
5176 /* PREFIX_VEX_0FD2 */
5180 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
5183 /* PREFIX_VEX_0FD3 */
5187 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
5190 /* PREFIX_VEX_0FD4 */
5194 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
5197 /* PREFIX_VEX_0FD5 */
5201 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
5204 /* PREFIX_VEX_0FD6 */
5208 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5211 /* PREFIX_VEX_0FD7 */
5215 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5218 /* PREFIX_VEX_0FD8 */
5222 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
5225 /* PREFIX_VEX_0FD9 */
5229 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
5232 /* PREFIX_VEX_0FDA */
5236 { "vpminub", { XM
, Vex
, EXx
}, 0 },
5239 /* PREFIX_VEX_0FDB */
5243 { "vpand", { XM
, Vex
, EXx
}, 0 },
5246 /* PREFIX_VEX_0FDC */
5250 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
5253 /* PREFIX_VEX_0FDD */
5257 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
5260 /* PREFIX_VEX_0FDE */
5264 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
5267 /* PREFIX_VEX_0FDF */
5271 { "vpandn", { XM
, Vex
, EXx
}, 0 },
5274 /* PREFIX_VEX_0FE0 */
5278 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
5281 /* PREFIX_VEX_0FE1 */
5285 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
5288 /* PREFIX_VEX_0FE2 */
5292 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
5295 /* PREFIX_VEX_0FE3 */
5299 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
5302 /* PREFIX_VEX_0FE4 */
5306 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
5309 /* PREFIX_VEX_0FE5 */
5313 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
5316 /* PREFIX_VEX_0FE6 */
5319 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
5320 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
5321 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
5324 /* PREFIX_VEX_0FE7 */
5328 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5331 /* PREFIX_VEX_0FE8 */
5335 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
5338 /* PREFIX_VEX_0FE9 */
5342 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
5345 /* PREFIX_VEX_0FEA */
5349 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
5352 /* PREFIX_VEX_0FEB */
5356 { "vpor", { XM
, Vex
, EXx
}, 0 },
5359 /* PREFIX_VEX_0FEC */
5363 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
5366 /* PREFIX_VEX_0FED */
5370 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
5373 /* PREFIX_VEX_0FEE */
5377 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
5380 /* PREFIX_VEX_0FEF */
5384 { "vpxor", { XM
, Vex
, EXx
}, 0 },
5387 /* PREFIX_VEX_0FF0 */
5392 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5395 /* PREFIX_VEX_0FF1 */
5399 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
5402 /* PREFIX_VEX_0FF2 */
5406 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
5409 /* PREFIX_VEX_0FF3 */
5413 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
5416 /* PREFIX_VEX_0FF4 */
5420 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
5423 /* PREFIX_VEX_0FF5 */
5427 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
5430 /* PREFIX_VEX_0FF6 */
5434 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
5437 /* PREFIX_VEX_0FF7 */
5441 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5444 /* PREFIX_VEX_0FF8 */
5448 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
5451 /* PREFIX_VEX_0FF9 */
5455 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
5458 /* PREFIX_VEX_0FFA */
5462 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
5465 /* PREFIX_VEX_0FFB */
5469 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
5472 /* PREFIX_VEX_0FFC */
5476 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
5479 /* PREFIX_VEX_0FFD */
5483 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
5486 /* PREFIX_VEX_0FFE */
5490 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
5493 /* PREFIX_VEX_0F3800 */
5497 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
5500 /* PREFIX_VEX_0F3801 */
5504 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
5507 /* PREFIX_VEX_0F3802 */
5511 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
5514 /* PREFIX_VEX_0F3803 */
5518 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
5521 /* PREFIX_VEX_0F3804 */
5525 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
5528 /* PREFIX_VEX_0F3805 */
5532 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
5535 /* PREFIX_VEX_0F3806 */
5539 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
5542 /* PREFIX_VEX_0F3807 */
5546 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
5549 /* PREFIX_VEX_0F3808 */
5553 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
5556 /* PREFIX_VEX_0F3809 */
5560 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
5563 /* PREFIX_VEX_0F380A */
5567 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
5570 /* PREFIX_VEX_0F380B */
5574 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
5577 /* PREFIX_VEX_0F380C */
5581 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5584 /* PREFIX_VEX_0F380D */
5588 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5591 /* PREFIX_VEX_0F380E */
5595 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5598 /* PREFIX_VEX_0F380F */
5602 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5605 /* PREFIX_VEX_0F3813 */
5609 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
5612 /* PREFIX_VEX_0F3816 */
5616 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5619 /* PREFIX_VEX_0F3817 */
5623 { "vptest", { XM
, EXx
}, 0 },
5626 /* PREFIX_VEX_0F3818 */
5630 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5633 /* PREFIX_VEX_0F3819 */
5637 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5640 /* PREFIX_VEX_0F381A */
5644 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5647 /* PREFIX_VEX_0F381C */
5651 { "vpabsb", { XM
, EXx
}, 0 },
5654 /* PREFIX_VEX_0F381D */
5658 { "vpabsw", { XM
, EXx
}, 0 },
5661 /* PREFIX_VEX_0F381E */
5665 { "vpabsd", { XM
, EXx
}, 0 },
5668 /* PREFIX_VEX_0F3820 */
5672 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
5675 /* PREFIX_VEX_0F3821 */
5679 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
5682 /* PREFIX_VEX_0F3822 */
5686 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
5689 /* PREFIX_VEX_0F3823 */
5693 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
5696 /* PREFIX_VEX_0F3824 */
5700 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
5703 /* PREFIX_VEX_0F3825 */
5707 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
5710 /* PREFIX_VEX_0F3828 */
5714 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
5717 /* PREFIX_VEX_0F3829 */
5721 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
5724 /* PREFIX_VEX_0F382A */
5728 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5731 /* PREFIX_VEX_0F382B */
5735 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
5738 /* PREFIX_VEX_0F382C */
5742 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5745 /* PREFIX_VEX_0F382D */
5749 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5752 /* PREFIX_VEX_0F382E */
5756 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5759 /* PREFIX_VEX_0F382F */
5763 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5766 /* PREFIX_VEX_0F3830 */
5770 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
5773 /* PREFIX_VEX_0F3831 */
5777 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
5780 /* PREFIX_VEX_0F3832 */
5784 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
5787 /* PREFIX_VEX_0F3833 */
5791 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
5794 /* PREFIX_VEX_0F3834 */
5798 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
5801 /* PREFIX_VEX_0F3835 */
5805 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
5808 /* PREFIX_VEX_0F3836 */
5812 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5815 /* PREFIX_VEX_0F3837 */
5819 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
5822 /* PREFIX_VEX_0F3838 */
5826 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
5829 /* PREFIX_VEX_0F3839 */
5833 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
5836 /* PREFIX_VEX_0F383A */
5840 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
5843 /* PREFIX_VEX_0F383B */
5847 { "vpminud", { XM
, Vex
, EXx
}, 0 },
5850 /* PREFIX_VEX_0F383C */
5854 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
5857 /* PREFIX_VEX_0F383D */
5861 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
5864 /* PREFIX_VEX_0F383E */
5868 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
5871 /* PREFIX_VEX_0F383F */
5875 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
5878 /* PREFIX_VEX_0F3840 */
5882 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
5885 /* PREFIX_VEX_0F3841 */
5889 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5892 /* PREFIX_VEX_0F3845 */
5896 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
5899 /* PREFIX_VEX_0F3846 */
5903 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5906 /* PREFIX_VEX_0F3847 */
5910 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
5913 /* PREFIX_VEX_0F3858 */
5917 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5920 /* PREFIX_VEX_0F3859 */
5924 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5927 /* PREFIX_VEX_0F385A */
5931 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5934 /* PREFIX_VEX_0F3878 */
5938 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5941 /* PREFIX_VEX_0F3879 */
5945 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5948 /* PREFIX_VEX_0F388C */
5952 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5955 /* PREFIX_VEX_0F388E */
5959 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
5962 /* PREFIX_VEX_0F3890 */
5966 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5969 /* PREFIX_VEX_0F3891 */
5973 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
5976 /* PREFIX_VEX_0F3892 */
5980 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5983 /* PREFIX_VEX_0F3893 */
5987 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
5990 /* PREFIX_VEX_0F3896 */
5994 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, 0 },
5997 /* PREFIX_VEX_0F3897 */
6001 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6004 /* PREFIX_VEX_0F3898 */
6008 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6011 /* PREFIX_VEX_0F3899 */
6015 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6018 /* PREFIX_VEX_0F389A */
6022 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6025 /* PREFIX_VEX_0F389B */
6029 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6032 /* PREFIX_VEX_0F389C */
6036 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6039 /* PREFIX_VEX_0F389D */
6043 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6046 /* PREFIX_VEX_0F389E */
6050 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6053 /* PREFIX_VEX_0F389F */
6057 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6060 /* PREFIX_VEX_0F38A6 */
6064 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6068 /* PREFIX_VEX_0F38A7 */
6072 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6075 /* PREFIX_VEX_0F38A8 */
6079 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6082 /* PREFIX_VEX_0F38A9 */
6086 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6089 /* PREFIX_VEX_0F38AA */
6093 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6096 /* PREFIX_VEX_0F38AB */
6100 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6103 /* PREFIX_VEX_0F38AC */
6107 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6110 /* PREFIX_VEX_0F38AD */
6114 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6117 /* PREFIX_VEX_0F38AE */
6121 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6124 /* PREFIX_VEX_0F38AF */
6128 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6131 /* PREFIX_VEX_0F38B6 */
6135 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6138 /* PREFIX_VEX_0F38B7 */
6142 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6145 /* PREFIX_VEX_0F38B8 */
6149 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6152 /* PREFIX_VEX_0F38B9 */
6156 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6159 /* PREFIX_VEX_0F38BA */
6163 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6166 /* PREFIX_VEX_0F38BB */
6170 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6173 /* PREFIX_VEX_0F38BC */
6177 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6180 /* PREFIX_VEX_0F38BD */
6184 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6187 /* PREFIX_VEX_0F38BE */
6191 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6194 /* PREFIX_VEX_0F38BF */
6198 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6201 /* PREFIX_VEX_0F38CF */
6205 { VEX_W_TABLE (VEX_W_0F38CF_P_2
) },
6208 /* PREFIX_VEX_0F38DB */
6212 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6215 /* PREFIX_VEX_0F38DC */
6219 { "vaesenc", { XM
, Vex
, EXx
}, 0 },
6222 /* PREFIX_VEX_0F38DD */
6226 { "vaesenclast", { XM
, Vex
, EXx
}, 0 },
6229 /* PREFIX_VEX_0F38DE */
6233 { "vaesdec", { XM
, Vex
, EXx
}, 0 },
6236 /* PREFIX_VEX_0F38DF */
6240 { "vaesdeclast", { XM
, Vex
, EXx
}, 0 },
6243 /* PREFIX_VEX_0F38F2 */
6245 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6248 /* PREFIX_VEX_0F38F3_REG_1 */
6250 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6253 /* PREFIX_VEX_0F38F3_REG_2 */
6255 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6258 /* PREFIX_VEX_0F38F3_REG_3 */
6260 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6263 /* PREFIX_VEX_0F38F5 */
6265 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6266 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6268 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6271 /* PREFIX_VEX_0F38F6 */
6276 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6279 /* PREFIX_VEX_0F38F7 */
6281 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6282 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6283 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6284 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6287 /* PREFIX_VEX_0F3A00 */
6291 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6294 /* PREFIX_VEX_0F3A01 */
6298 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6301 /* PREFIX_VEX_0F3A02 */
6305 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6308 /* PREFIX_VEX_0F3A04 */
6312 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6315 /* PREFIX_VEX_0F3A05 */
6319 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6322 /* PREFIX_VEX_0F3A06 */
6326 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6329 /* PREFIX_VEX_0F3A08 */
6333 { "vroundps", { XM
, EXx
, Ib
}, 0 },
6336 /* PREFIX_VEX_0F3A09 */
6340 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
6343 /* PREFIX_VEX_0F3A0A */
6347 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
}, 0 },
6350 /* PREFIX_VEX_0F3A0B */
6354 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
}, 0 },
6357 /* PREFIX_VEX_0F3A0C */
6361 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
6364 /* PREFIX_VEX_0F3A0D */
6368 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
6371 /* PREFIX_VEX_0F3A0E */
6375 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
6378 /* PREFIX_VEX_0F3A0F */
6382 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
6385 /* PREFIX_VEX_0F3A14 */
6389 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6392 /* PREFIX_VEX_0F3A15 */
6396 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6399 /* PREFIX_VEX_0F3A16 */
6403 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6406 /* PREFIX_VEX_0F3A17 */
6410 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6413 /* PREFIX_VEX_0F3A18 */
6417 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6420 /* PREFIX_VEX_0F3A19 */
6424 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6427 /* PREFIX_VEX_0F3A1D */
6431 { "vcvtps2ph", { EXxmmq
, XM
, Ib
}, 0 },
6434 /* PREFIX_VEX_0F3A20 */
6438 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6441 /* PREFIX_VEX_0F3A21 */
6445 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6448 /* PREFIX_VEX_0F3A22 */
6452 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6455 /* PREFIX_VEX_0F3A30 */
6459 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6462 /* PREFIX_VEX_0F3A31 */
6466 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6469 /* PREFIX_VEX_0F3A32 */
6473 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6476 /* PREFIX_VEX_0F3A33 */
6480 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6483 /* PREFIX_VEX_0F3A38 */
6487 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6490 /* PREFIX_VEX_0F3A39 */
6494 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6497 /* PREFIX_VEX_0F3A40 */
6501 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
6504 /* PREFIX_VEX_0F3A41 */
6508 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6511 /* PREFIX_VEX_0F3A42 */
6515 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
6518 /* PREFIX_VEX_0F3A44 */
6522 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, 0 },
6525 /* PREFIX_VEX_0F3A46 */
6529 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6532 /* PREFIX_VEX_0F3A48 */
6536 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6539 /* PREFIX_VEX_0F3A49 */
6543 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6546 /* PREFIX_VEX_0F3A4A */
6550 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6553 /* PREFIX_VEX_0F3A4B */
6557 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6560 /* PREFIX_VEX_0F3A4C */
6564 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6567 /* PREFIX_VEX_0F3A5C */
6571 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6574 /* PREFIX_VEX_0F3A5D */
6578 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6581 /* PREFIX_VEX_0F3A5E */
6585 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6588 /* PREFIX_VEX_0F3A5F */
6592 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6595 /* PREFIX_VEX_0F3A60 */
6599 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6603 /* PREFIX_VEX_0F3A61 */
6607 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6610 /* PREFIX_VEX_0F3A62 */
6614 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6617 /* PREFIX_VEX_0F3A63 */
6621 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6624 /* PREFIX_VEX_0F3A68 */
6628 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6631 /* PREFIX_VEX_0F3A69 */
6635 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6638 /* PREFIX_VEX_0F3A6A */
6642 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6645 /* PREFIX_VEX_0F3A6B */
6649 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6652 /* PREFIX_VEX_0F3A6C */
6656 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6659 /* PREFIX_VEX_0F3A6D */
6663 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6666 /* PREFIX_VEX_0F3A6E */
6670 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6673 /* PREFIX_VEX_0F3A6F */
6677 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6680 /* PREFIX_VEX_0F3A78 */
6684 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6687 /* PREFIX_VEX_0F3A79 */
6691 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6694 /* PREFIX_VEX_0F3A7A */
6698 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6701 /* PREFIX_VEX_0F3A7B */
6705 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6708 /* PREFIX_VEX_0F3A7C */
6712 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6716 /* PREFIX_VEX_0F3A7D */
6720 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6723 /* PREFIX_VEX_0F3A7E */
6727 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6730 /* PREFIX_VEX_0F3A7F */
6734 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6737 /* PREFIX_VEX_0F3ACE */
6741 { VEX_W_TABLE (VEX_W_0F3ACE_P_2
) },
6744 /* PREFIX_VEX_0F3ACF */
6748 { VEX_W_TABLE (VEX_W_0F3ACF_P_2
) },
6751 /* PREFIX_VEX_0F3ADF */
6755 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6758 /* PREFIX_VEX_0F3AF0 */
6763 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6766 #define NEED_PREFIX_TABLE
6767 #include "i386-dis-evex.h"
6768 #undef NEED_PREFIX_TABLE
6771 static const struct dis386 x86_64_table
[][2] = {
6774 { "pushP", { es
}, 0 },
6779 { "popP", { es
}, 0 },
6784 { "pushP", { cs
}, 0 },
6789 { "pushP", { ss
}, 0 },
6794 { "popP", { ss
}, 0 },
6799 { "pushP", { ds
}, 0 },
6804 { "popP", { ds
}, 0 },
6809 { "daa", { XX
}, 0 },
6814 { "das", { XX
}, 0 },
6819 { "aaa", { XX
}, 0 },
6824 { "aas", { XX
}, 0 },
6829 { "pushaP", { XX
}, 0 },
6834 { "popaP", { XX
}, 0 },
6839 { MOD_TABLE (MOD_62_32BIT
) },
6840 { EVEX_TABLE (EVEX_0F
) },
6845 { "arpl", { Ew
, Gw
}, 0 },
6846 { "movs{lq|xd}", { Gv
, Ed
}, 0 },
6851 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6852 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6857 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6858 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6863 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
6864 { REG_TABLE (REG_80
) },
6869 { "Jcall{T|}", { Ap
}, 0 },
6874 { MOD_TABLE (MOD_C4_32BIT
) },
6875 { VEX_C4_TABLE (VEX_0F
) },
6880 { MOD_TABLE (MOD_C5_32BIT
) },
6881 { VEX_C5_TABLE (VEX_0F
) },
6886 { "into", { XX
}, 0 },
6891 { "aam", { Ib
}, 0 },
6896 { "aad", { Ib
}, 0 },
6901 { "callP", { Jv
, BND
}, 0 },
6902 { "call@", { Jv
, BND
}, 0 }
6907 { "jmpP", { Jv
, BND
}, 0 },
6908 { "jmp@", { Jv
, BND
}, 0 }
6913 { "Jjmp{T|}", { Ap
}, 0 },
6916 /* X86_64_0F01_REG_0 */
6918 { "sgdt{Q|IQ}", { M
}, 0 },
6919 { "sgdt", { M
}, 0 },
6922 /* X86_64_0F01_REG_1 */
6924 { "sidt{Q|IQ}", { M
}, 0 },
6925 { "sidt", { M
}, 0 },
6928 /* X86_64_0F01_REG_2 */
6930 { "lgdt{Q|Q}", { M
}, 0 },
6931 { "lgdt", { M
}, 0 },
6934 /* X86_64_0F01_REG_3 */
6936 { "lidt{Q|Q}", { M
}, 0 },
6937 { "lidt", { M
}, 0 },
6941 static const struct dis386 three_byte_table
[][256] = {
6943 /* THREE_BYTE_0F38 */
6946 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
6947 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
6948 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
6949 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
6950 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
6951 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
6952 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
6953 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
6955 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
6956 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
6957 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
6958 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
6964 { PREFIX_TABLE (PREFIX_0F3810
) },
6968 { PREFIX_TABLE (PREFIX_0F3814
) },
6969 { PREFIX_TABLE (PREFIX_0F3815
) },
6971 { PREFIX_TABLE (PREFIX_0F3817
) },
6977 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
6978 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
6979 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
6982 { PREFIX_TABLE (PREFIX_0F3820
) },
6983 { PREFIX_TABLE (PREFIX_0F3821
) },
6984 { PREFIX_TABLE (PREFIX_0F3822
) },
6985 { PREFIX_TABLE (PREFIX_0F3823
) },
6986 { PREFIX_TABLE (PREFIX_0F3824
) },
6987 { PREFIX_TABLE (PREFIX_0F3825
) },
6991 { PREFIX_TABLE (PREFIX_0F3828
) },
6992 { PREFIX_TABLE (PREFIX_0F3829
) },
6993 { PREFIX_TABLE (PREFIX_0F382A
) },
6994 { PREFIX_TABLE (PREFIX_0F382B
) },
7000 { PREFIX_TABLE (PREFIX_0F3830
) },
7001 { PREFIX_TABLE (PREFIX_0F3831
) },
7002 { PREFIX_TABLE (PREFIX_0F3832
) },
7003 { PREFIX_TABLE (PREFIX_0F3833
) },
7004 { PREFIX_TABLE (PREFIX_0F3834
) },
7005 { PREFIX_TABLE (PREFIX_0F3835
) },
7007 { PREFIX_TABLE (PREFIX_0F3837
) },
7009 { PREFIX_TABLE (PREFIX_0F3838
) },
7010 { PREFIX_TABLE (PREFIX_0F3839
) },
7011 { PREFIX_TABLE (PREFIX_0F383A
) },
7012 { PREFIX_TABLE (PREFIX_0F383B
) },
7013 { PREFIX_TABLE (PREFIX_0F383C
) },
7014 { PREFIX_TABLE (PREFIX_0F383D
) },
7015 { PREFIX_TABLE (PREFIX_0F383E
) },
7016 { PREFIX_TABLE (PREFIX_0F383F
) },
7018 { PREFIX_TABLE (PREFIX_0F3840
) },
7019 { PREFIX_TABLE (PREFIX_0F3841
) },
7090 { PREFIX_TABLE (PREFIX_0F3880
) },
7091 { PREFIX_TABLE (PREFIX_0F3881
) },
7092 { PREFIX_TABLE (PREFIX_0F3882
) },
7171 { PREFIX_TABLE (PREFIX_0F38C8
) },
7172 { PREFIX_TABLE (PREFIX_0F38C9
) },
7173 { PREFIX_TABLE (PREFIX_0F38CA
) },
7174 { PREFIX_TABLE (PREFIX_0F38CB
) },
7175 { PREFIX_TABLE (PREFIX_0F38CC
) },
7176 { PREFIX_TABLE (PREFIX_0F38CD
) },
7178 { PREFIX_TABLE (PREFIX_0F38CF
) },
7192 { PREFIX_TABLE (PREFIX_0F38DB
) },
7193 { PREFIX_TABLE (PREFIX_0F38DC
) },
7194 { PREFIX_TABLE (PREFIX_0F38DD
) },
7195 { PREFIX_TABLE (PREFIX_0F38DE
) },
7196 { PREFIX_TABLE (PREFIX_0F38DF
) },
7216 { PREFIX_TABLE (PREFIX_0F38F0
) },
7217 { PREFIX_TABLE (PREFIX_0F38F1
) },
7221 { PREFIX_TABLE (PREFIX_0F38F5
) },
7222 { PREFIX_TABLE (PREFIX_0F38F6
) },
7225 { PREFIX_TABLE (PREFIX_0F38F8
) },
7226 { PREFIX_TABLE (PREFIX_0F38F9
) },
7234 /* THREE_BYTE_0F3A */
7246 { PREFIX_TABLE (PREFIX_0F3A08
) },
7247 { PREFIX_TABLE (PREFIX_0F3A09
) },
7248 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7249 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7250 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7251 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7252 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7253 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7259 { PREFIX_TABLE (PREFIX_0F3A14
) },
7260 { PREFIX_TABLE (PREFIX_0F3A15
) },
7261 { PREFIX_TABLE (PREFIX_0F3A16
) },
7262 { PREFIX_TABLE (PREFIX_0F3A17
) },
7273 { PREFIX_TABLE (PREFIX_0F3A20
) },
7274 { PREFIX_TABLE (PREFIX_0F3A21
) },
7275 { PREFIX_TABLE (PREFIX_0F3A22
) },
7309 { PREFIX_TABLE (PREFIX_0F3A40
) },
7310 { PREFIX_TABLE (PREFIX_0F3A41
) },
7311 { PREFIX_TABLE (PREFIX_0F3A42
) },
7313 { PREFIX_TABLE (PREFIX_0F3A44
) },
7345 { PREFIX_TABLE (PREFIX_0F3A60
) },
7346 { PREFIX_TABLE (PREFIX_0F3A61
) },
7347 { PREFIX_TABLE (PREFIX_0F3A62
) },
7348 { PREFIX_TABLE (PREFIX_0F3A63
) },
7466 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7468 { PREFIX_TABLE (PREFIX_0F3ACE
) },
7469 { PREFIX_TABLE (PREFIX_0F3ACF
) },
7487 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7527 static const struct dis386 xop_table
[][256] = {
7680 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7681 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7682 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7690 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7691 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7698 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7699 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7700 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7708 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7709 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7713 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7714 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7717 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7735 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7747 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
7748 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
7749 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
7750 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
7760 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7761 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7762 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7763 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7796 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7797 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7798 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7799 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
7823 { REG_TABLE (REG_XOP_TBM_01
) },
7824 { REG_TABLE (REG_XOP_TBM_02
) },
7842 { REG_TABLE (REG_XOP_LWPCB
) },
7966 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
7967 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
7968 { "vfrczss", { XM
, EXd
}, 0 },
7969 { "vfrczsd", { XM
, EXq
}, 0 },
7984 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7985 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7986 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7987 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7988 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7989 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7990 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7991 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7993 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7994 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7995 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7996 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8039 { "vphaddbw", { XM
, EXxmm
}, 0 },
8040 { "vphaddbd", { XM
, EXxmm
}, 0 },
8041 { "vphaddbq", { XM
, EXxmm
}, 0 },
8044 { "vphaddwd", { XM
, EXxmm
}, 0 },
8045 { "vphaddwq", { XM
, EXxmm
}, 0 },
8050 { "vphadddq", { XM
, EXxmm
}, 0 },
8057 { "vphaddubw", { XM
, EXxmm
}, 0 },
8058 { "vphaddubd", { XM
, EXxmm
}, 0 },
8059 { "vphaddubq", { XM
, EXxmm
}, 0 },
8062 { "vphadduwd", { XM
, EXxmm
}, 0 },
8063 { "vphadduwq", { XM
, EXxmm
}, 0 },
8068 { "vphaddudq", { XM
, EXxmm
}, 0 },
8075 { "vphsubbw", { XM
, EXxmm
}, 0 },
8076 { "vphsubwd", { XM
, EXxmm
}, 0 },
8077 { "vphsubdq", { XM
, EXxmm
}, 0 },
8131 { "bextr", { Gv
, Ev
, Iq
}, 0 },
8133 { REG_TABLE (REG_XOP_LWP
) },
8403 static const struct dis386 vex_table
[][256] = {
8425 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8426 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8427 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8428 { MOD_TABLE (MOD_VEX_0F13
) },
8429 { "vunpcklpX", { XM
, Vex
, EXx
}, 0 },
8430 { "vunpckhpX", { XM
, Vex
, EXx
}, 0 },
8431 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8432 { MOD_TABLE (MOD_VEX_0F17
) },
8452 { "vmovapX", { XM
, EXx
}, 0 },
8453 { "vmovapX", { EXxS
, XM
}, 0 },
8454 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8455 { MOD_TABLE (MOD_VEX_0F2B
) },
8456 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8457 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8458 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8459 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8480 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8481 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8483 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8484 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8485 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8486 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8490 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8491 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8497 { MOD_TABLE (MOD_VEX_0F50
) },
8498 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8499 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8500 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8501 { "vandpX", { XM
, Vex
, EXx
}, 0 },
8502 { "vandnpX", { XM
, Vex
, EXx
}, 0 },
8503 { "vorpX", { XM
, Vex
, EXx
}, 0 },
8504 { "vxorpX", { XM
, Vex
, EXx
}, 0 },
8506 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8507 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8508 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8509 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8510 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8511 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8512 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8513 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8515 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8516 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8517 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8518 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8519 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8520 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8521 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8522 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8524 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8525 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8526 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8527 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8528 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8529 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8530 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8531 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8533 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8534 { REG_TABLE (REG_VEX_0F71
) },
8535 { REG_TABLE (REG_VEX_0F72
) },
8536 { REG_TABLE (REG_VEX_0F73
) },
8537 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8538 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8539 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8540 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8546 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8547 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8548 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8549 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8569 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8570 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8571 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8572 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8578 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8579 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8602 { REG_TABLE (REG_VEX_0FAE
) },
8625 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8627 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8628 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8629 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, 0 },
8641 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8642 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8643 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8644 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8645 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8646 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8647 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8648 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8650 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8651 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8652 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8653 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8654 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8655 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8656 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8657 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8659 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8660 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8661 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8662 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8663 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8664 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8665 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8666 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8668 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8669 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8670 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8671 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8672 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8673 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8674 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8675 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8677 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8678 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8679 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8680 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8681 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8682 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8683 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8684 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8686 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8687 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8688 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8689 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8690 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8691 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8692 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8698 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8699 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8700 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8701 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8702 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8703 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8704 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8705 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8707 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8708 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8709 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8710 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8711 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8712 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8713 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8714 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8719 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8722 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8723 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8725 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8726 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8727 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8729 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8730 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8731 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8734 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8735 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8736 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8737 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8738 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8739 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8743 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8744 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8745 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8746 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8747 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8748 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8749 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8750 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8752 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8753 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8754 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8755 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8756 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8758 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8759 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8762 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8763 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8764 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8765 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8766 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8767 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8768 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8770 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8771 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8775 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8776 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8777 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8797 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8798 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8799 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
8833 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
8834 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
8855 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
8857 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
8860 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
8861 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
8862 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
8863 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
8866 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
8867 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
8869 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
8870 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
8871 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
8872 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
8873 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
8874 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
8875 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
8876 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
8884 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
8885 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
8887 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
8888 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
8889 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
8890 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
8891 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
8892 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
8893 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
8894 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
8902 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
8903 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
8905 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
8906 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
8907 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
8908 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
8909 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
8910 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
8911 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
8912 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
8930 { PREFIX_TABLE (PREFIX_VEX_0F38CF
) },
8944 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
8945 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
8946 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
8947 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
8948 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
8970 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
8971 { REG_TABLE (REG_VEX_0F38F3
) },
8973 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
8974 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
8975 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
8989 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
8990 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
8991 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
8993 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
8994 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
8995 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
8998 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
8999 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9000 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9001 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9002 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9003 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9004 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9005 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9011 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9012 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9013 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9014 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9016 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9017 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9021 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9025 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9026 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9027 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9043 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9045 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9046 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9052 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9053 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9061 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9062 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9063 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9065 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9067 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9070 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9071 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9072 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9073 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9074 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9092 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9093 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9094 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9095 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9097 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9098 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9099 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9100 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9106 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9107 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9108 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9109 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9110 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9111 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9112 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9113 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9124 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9125 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9126 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9127 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9128 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9129 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9130 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9131 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9220 { PREFIX_TABLE(PREFIX_VEX_0F3ACE
) },
9221 { PREFIX_TABLE(PREFIX_VEX_0F3ACF
) },
9239 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9259 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9279 #define NEED_OPCODE_TABLE
9280 #include "i386-dis-evex.h"
9281 #undef NEED_OPCODE_TABLE
9282 static const struct dis386 vex_len_table
[][2] = {
9283 /* VEX_LEN_0F12_P_0_M_0 */
9285 { "vmovlps", { XM
, Vex128
, EXq
}, 0 },
9288 /* VEX_LEN_0F12_P_0_M_1 */
9290 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
9293 /* VEX_LEN_0F12_P_2 */
9295 { "vmovlpd", { XM
, Vex128
, EXq
}, 0 },
9298 /* VEX_LEN_0F13_M_0 */
9300 { "vmovlpX", { EXq
, XM
}, 0 },
9303 /* VEX_LEN_0F16_P_0_M_0 */
9305 { "vmovhps", { XM
, Vex128
, EXq
}, 0 },
9308 /* VEX_LEN_0F16_P_0_M_1 */
9310 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
9313 /* VEX_LEN_0F16_P_2 */
9315 { "vmovhpd", { XM
, Vex128
, EXq
}, 0 },
9318 /* VEX_LEN_0F17_M_0 */
9320 { "vmovhpX", { EXq
, XM
}, 0 },
9323 /* VEX_LEN_0F2A_P_1 */
9325 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9326 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9329 /* VEX_LEN_0F2A_P_3 */
9331 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9332 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9335 /* VEX_LEN_0F2C_P_1 */
9337 { "vcvttss2si", { Gv
, EXdScalar
}, 0 },
9338 { "vcvttss2si", { Gv
, EXdScalar
}, 0 },
9341 /* VEX_LEN_0F2C_P_3 */
9343 { "vcvttsd2si", { Gv
, EXqScalar
}, 0 },
9344 { "vcvttsd2si", { Gv
, EXqScalar
}, 0 },
9347 /* VEX_LEN_0F2D_P_1 */
9349 { "vcvtss2si", { Gv
, EXdScalar
}, 0 },
9350 { "vcvtss2si", { Gv
, EXdScalar
}, 0 },
9353 /* VEX_LEN_0F2D_P_3 */
9355 { "vcvtsd2si", { Gv
, EXqScalar
}, 0 },
9356 { "vcvtsd2si", { Gv
, EXqScalar
}, 0 },
9359 /* VEX_LEN_0F41_P_0 */
9362 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9364 /* VEX_LEN_0F41_P_2 */
9367 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9369 /* VEX_LEN_0F42_P_0 */
9372 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9374 /* VEX_LEN_0F42_P_2 */
9377 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9379 /* VEX_LEN_0F44_P_0 */
9381 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9383 /* VEX_LEN_0F44_P_2 */
9385 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9387 /* VEX_LEN_0F45_P_0 */
9390 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9392 /* VEX_LEN_0F45_P_2 */
9395 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9397 /* VEX_LEN_0F46_P_0 */
9400 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9402 /* VEX_LEN_0F46_P_2 */
9405 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9407 /* VEX_LEN_0F47_P_0 */
9410 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9412 /* VEX_LEN_0F47_P_2 */
9415 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9417 /* VEX_LEN_0F4A_P_0 */
9420 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9422 /* VEX_LEN_0F4A_P_2 */
9425 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9427 /* VEX_LEN_0F4B_P_0 */
9430 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9432 /* VEX_LEN_0F4B_P_2 */
9435 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9438 /* VEX_LEN_0F6E_P_2 */
9440 { "vmovK", { XMScalar
, Edq
}, 0 },
9443 /* VEX_LEN_0F77_P_1 */
9445 { "vzeroupper", { XX
}, 0 },
9446 { "vzeroall", { XX
}, 0 },
9449 /* VEX_LEN_0F7E_P_1 */
9451 { "vmovq", { XMScalar
, EXqScalar
}, 0 },
9454 /* VEX_LEN_0F7E_P_2 */
9456 { "vmovK", { Edq
, XMScalar
}, 0 },
9459 /* VEX_LEN_0F90_P_0 */
9461 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9464 /* VEX_LEN_0F90_P_2 */
9466 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9469 /* VEX_LEN_0F91_P_0 */
9471 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9474 /* VEX_LEN_0F91_P_2 */
9476 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9479 /* VEX_LEN_0F92_P_0 */
9481 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9484 /* VEX_LEN_0F92_P_2 */
9486 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9489 /* VEX_LEN_0F92_P_3 */
9491 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0
) },
9494 /* VEX_LEN_0F93_P_0 */
9496 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9499 /* VEX_LEN_0F93_P_2 */
9501 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9504 /* VEX_LEN_0F93_P_3 */
9506 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0
) },
9509 /* VEX_LEN_0F98_P_0 */
9511 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9514 /* VEX_LEN_0F98_P_2 */
9516 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9519 /* VEX_LEN_0F99_P_0 */
9521 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9524 /* VEX_LEN_0F99_P_2 */
9526 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9529 /* VEX_LEN_0FAE_R_2_M_0 */
9531 { "vldmxcsr", { Md
}, 0 },
9534 /* VEX_LEN_0FAE_R_3_M_0 */
9536 { "vstmxcsr", { Md
}, 0 },
9539 /* VEX_LEN_0FC4_P_2 */
9541 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
9544 /* VEX_LEN_0FC5_P_2 */
9546 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
9549 /* VEX_LEN_0FD6_P_2 */
9551 { "vmovq", { EXqScalarS
, XMScalar
}, 0 },
9554 /* VEX_LEN_0FF7_P_2 */
9556 { "vmaskmovdqu", { XM
, XS
}, 0 },
9559 /* VEX_LEN_0F3816_P_2 */
9562 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9565 /* VEX_LEN_0F3819_P_2 */
9568 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9571 /* VEX_LEN_0F381A_P_2_M_0 */
9574 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9577 /* VEX_LEN_0F3836_P_2 */
9580 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9583 /* VEX_LEN_0F3841_P_2 */
9585 { "vphminposuw", { XM
, EXx
}, 0 },
9588 /* VEX_LEN_0F385A_P_2_M_0 */
9591 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9594 /* VEX_LEN_0F38DB_P_2 */
9596 { "vaesimc", { XM
, EXx
}, 0 },
9599 /* VEX_LEN_0F38F2_P_0 */
9601 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
9604 /* VEX_LEN_0F38F3_R_1_P_0 */
9606 { "blsrS", { VexGdq
, Edq
}, 0 },
9609 /* VEX_LEN_0F38F3_R_2_P_0 */
9611 { "blsmskS", { VexGdq
, Edq
}, 0 },
9614 /* VEX_LEN_0F38F3_R_3_P_0 */
9616 { "blsiS", { VexGdq
, Edq
}, 0 },
9619 /* VEX_LEN_0F38F5_P_0 */
9621 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
9624 /* VEX_LEN_0F38F5_P_1 */
9626 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
9629 /* VEX_LEN_0F38F5_P_3 */
9631 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
9634 /* VEX_LEN_0F38F6_P_3 */
9636 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
9639 /* VEX_LEN_0F38F7_P_0 */
9641 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
9644 /* VEX_LEN_0F38F7_P_1 */
9646 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
9649 /* VEX_LEN_0F38F7_P_2 */
9651 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
9654 /* VEX_LEN_0F38F7_P_3 */
9656 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
9659 /* VEX_LEN_0F3A00_P_2 */
9662 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
9665 /* VEX_LEN_0F3A01_P_2 */
9668 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
9671 /* VEX_LEN_0F3A06_P_2 */
9674 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
9677 /* VEX_LEN_0F3A14_P_2 */
9679 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
9682 /* VEX_LEN_0F3A15_P_2 */
9684 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
9687 /* VEX_LEN_0F3A16_P_2 */
9689 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
9692 /* VEX_LEN_0F3A17_P_2 */
9694 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
9697 /* VEX_LEN_0F3A18_P_2 */
9700 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
9703 /* VEX_LEN_0F3A19_P_2 */
9706 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
9709 /* VEX_LEN_0F3A20_P_2 */
9711 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
9714 /* VEX_LEN_0F3A21_P_2 */
9716 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
9719 /* VEX_LEN_0F3A22_P_2 */
9721 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
9724 /* VEX_LEN_0F3A30_P_2 */
9726 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
9729 /* VEX_LEN_0F3A31_P_2 */
9731 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
9734 /* VEX_LEN_0F3A32_P_2 */
9736 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
9739 /* VEX_LEN_0F3A33_P_2 */
9741 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
9744 /* VEX_LEN_0F3A38_P_2 */
9747 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
9750 /* VEX_LEN_0F3A39_P_2 */
9753 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
9756 /* VEX_LEN_0F3A41_P_2 */
9758 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
9761 /* VEX_LEN_0F3A46_P_2 */
9764 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
9767 /* VEX_LEN_0F3A60_P_2 */
9769 { "vpcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9772 /* VEX_LEN_0F3A61_P_2 */
9774 { "vpcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9777 /* VEX_LEN_0F3A62_P_2 */
9779 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
9782 /* VEX_LEN_0F3A63_P_2 */
9784 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
9787 /* VEX_LEN_0F3A6A_P_2 */
9789 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9792 /* VEX_LEN_0F3A6B_P_2 */
9794 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9797 /* VEX_LEN_0F3A6E_P_2 */
9799 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9802 /* VEX_LEN_0F3A6F_P_2 */
9804 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9807 /* VEX_LEN_0F3A7A_P_2 */
9809 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9812 /* VEX_LEN_0F3A7B_P_2 */
9814 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9817 /* VEX_LEN_0F3A7E_P_2 */
9819 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9822 /* VEX_LEN_0F3A7F_P_2 */
9824 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9827 /* VEX_LEN_0F3ADF_P_2 */
9829 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
9832 /* VEX_LEN_0F3AF0_P_3 */
9834 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
9837 /* VEX_LEN_0FXOP_08_CC */
9839 { "vpcomb", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9842 /* VEX_LEN_0FXOP_08_CD */
9844 { "vpcomw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9847 /* VEX_LEN_0FXOP_08_CE */
9849 { "vpcomd", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9852 /* VEX_LEN_0FXOP_08_CF */
9854 { "vpcomq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9857 /* VEX_LEN_0FXOP_08_EC */
9859 { "vpcomub", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9862 /* VEX_LEN_0FXOP_08_ED */
9864 { "vpcomuw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9867 /* VEX_LEN_0FXOP_08_EE */
9869 { "vpcomud", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9872 /* VEX_LEN_0FXOP_08_EF */
9874 { "vpcomuq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9877 /* VEX_LEN_0FXOP_09_80 */
9879 { "vfrczps", { XM
, EXxmm
}, 0 },
9880 { "vfrczps", { XM
, EXymmq
}, 0 },
9883 /* VEX_LEN_0FXOP_09_81 */
9885 { "vfrczpd", { XM
, EXxmm
}, 0 },
9886 { "vfrczpd", { XM
, EXymmq
}, 0 },
9890 static const struct dis386 evex_len_table
[][3] = {
9891 #define NEED_EVEX_LEN_TABLE
9892 #include "i386-dis-evex.h"
9893 #undef NEED_EVEX_LEN_TABLE
9896 static const struct dis386 vex_w_table
[][2] = {
9898 /* VEX_W_0F41_P_0_LEN_1 */
9899 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
9900 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
9903 /* VEX_W_0F41_P_2_LEN_1 */
9904 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
9905 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
9908 /* VEX_W_0F42_P_0_LEN_1 */
9909 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
9910 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
9913 /* VEX_W_0F42_P_2_LEN_1 */
9914 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
9915 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
9918 /* VEX_W_0F44_P_0_LEN_0 */
9919 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
9920 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
9923 /* VEX_W_0F44_P_2_LEN_0 */
9924 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
9925 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
9928 /* VEX_W_0F45_P_0_LEN_1 */
9929 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
9930 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
9933 /* VEX_W_0F45_P_2_LEN_1 */
9934 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
9935 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
9938 /* VEX_W_0F46_P_0_LEN_1 */
9939 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
9940 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
9943 /* VEX_W_0F46_P_2_LEN_1 */
9944 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
9945 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
9948 /* VEX_W_0F47_P_0_LEN_1 */
9949 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
9950 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
9953 /* VEX_W_0F47_P_2_LEN_1 */
9954 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
9955 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
9958 /* VEX_W_0F4A_P_0_LEN_1 */
9959 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
9960 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
9963 /* VEX_W_0F4A_P_2_LEN_1 */
9964 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
9965 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
9968 /* VEX_W_0F4B_P_0_LEN_1 */
9969 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
9970 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
9973 /* VEX_W_0F4B_P_2_LEN_1 */
9974 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
9977 /* VEX_W_0F90_P_0_LEN_0 */
9978 { "kmovw", { MaskG
, MaskE
}, 0 },
9979 { "kmovq", { MaskG
, MaskE
}, 0 },
9982 /* VEX_W_0F90_P_2_LEN_0 */
9983 { "kmovb", { MaskG
, MaskBDE
}, 0 },
9984 { "kmovd", { MaskG
, MaskBDE
}, 0 },
9987 /* VEX_W_0F91_P_0_LEN_0 */
9988 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
9989 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
9992 /* VEX_W_0F91_P_2_LEN_0 */
9993 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
9994 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
9997 /* VEX_W_0F92_P_0_LEN_0 */
9998 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
10001 /* VEX_W_0F92_P_2_LEN_0 */
10002 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
10005 /* VEX_W_0F93_P_0_LEN_0 */
10006 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
10009 /* VEX_W_0F93_P_2_LEN_0 */
10010 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
10013 /* VEX_W_0F98_P_0_LEN_0 */
10014 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
10015 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
10018 /* VEX_W_0F98_P_2_LEN_0 */
10019 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
10020 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
10023 /* VEX_W_0F99_P_0_LEN_0 */
10024 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
10025 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
10028 /* VEX_W_0F99_P_2_LEN_0 */
10029 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
10030 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
10033 /* VEX_W_0F380C_P_2 */
10034 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
10037 /* VEX_W_0F380D_P_2 */
10038 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
10041 /* VEX_W_0F380E_P_2 */
10042 { "vtestps", { XM
, EXx
}, 0 },
10045 /* VEX_W_0F380F_P_2 */
10046 { "vtestpd", { XM
, EXx
}, 0 },
10049 /* VEX_W_0F3816_P_2 */
10050 { "vpermps", { XM
, Vex
, EXx
}, 0 },
10053 /* VEX_W_0F3818_P_2 */
10054 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
10057 /* VEX_W_0F3819_P_2 */
10058 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
10061 /* VEX_W_0F381A_P_2_M_0 */
10062 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
10065 /* VEX_W_0F382C_P_2_M_0 */
10066 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
10069 /* VEX_W_0F382D_P_2_M_0 */
10070 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
10073 /* VEX_W_0F382E_P_2_M_0 */
10074 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
10077 /* VEX_W_0F382F_P_2_M_0 */
10078 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
10081 /* VEX_W_0F3836_P_2 */
10082 { "vpermd", { XM
, Vex
, EXx
}, 0 },
10085 /* VEX_W_0F3846_P_2 */
10086 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
10089 /* VEX_W_0F3858_P_2 */
10090 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
10093 /* VEX_W_0F3859_P_2 */
10094 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
10097 /* VEX_W_0F385A_P_2_M_0 */
10098 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
10101 /* VEX_W_0F3878_P_2 */
10102 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
10105 /* VEX_W_0F3879_P_2 */
10106 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
10109 /* VEX_W_0F38CF_P_2 */
10110 { "vgf2p8mulb", { XM
, Vex
, EXx
}, 0 },
10113 /* VEX_W_0F3A00_P_2 */
10115 { "vpermq", { XM
, EXx
, Ib
}, 0 },
10118 /* VEX_W_0F3A01_P_2 */
10120 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
10123 /* VEX_W_0F3A02_P_2 */
10124 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
10127 /* VEX_W_0F3A04_P_2 */
10128 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
10131 /* VEX_W_0F3A05_P_2 */
10132 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
10135 /* VEX_W_0F3A06_P_2 */
10136 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10139 /* VEX_W_0F3A18_P_2 */
10140 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10143 /* VEX_W_0F3A19_P_2 */
10144 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
10147 /* VEX_W_0F3A30_P_2_LEN_0 */
10148 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
10149 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
10152 /* VEX_W_0F3A31_P_2_LEN_0 */
10153 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
10154 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
10157 /* VEX_W_0F3A32_P_2_LEN_0 */
10158 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
10159 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
10162 /* VEX_W_0F3A33_P_2_LEN_0 */
10163 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
10164 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
10167 /* VEX_W_0F3A38_P_2 */
10168 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10171 /* VEX_W_0F3A39_P_2 */
10172 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
10175 /* VEX_W_0F3A46_P_2 */
10176 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10179 /* VEX_W_0F3A48_P_2 */
10180 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10181 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10184 /* VEX_W_0F3A49_P_2 */
10185 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10186 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10189 /* VEX_W_0F3A4A_P_2 */
10190 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10193 /* VEX_W_0F3A4B_P_2 */
10194 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10197 /* VEX_W_0F3A4C_P_2 */
10198 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10201 /* VEX_W_0F3ACE_P_2 */
10203 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10206 /* VEX_W_0F3ACF_P_2 */
10208 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10210 #define NEED_VEX_W_TABLE
10211 #include "i386-dis-evex.h"
10212 #undef NEED_VEX_W_TABLE
10215 static const struct dis386 mod_table
[][2] = {
10218 { "leaS", { Gv
, M
}, 0 },
10223 { RM_TABLE (RM_C6_REG_7
) },
10228 { RM_TABLE (RM_C7_REG_7
) },
10232 { "Jcall^", { indirEp
}, 0 },
10236 { "Jjmp^", { indirEp
}, 0 },
10239 /* MOD_0F01_REG_0 */
10240 { X86_64_TABLE (X86_64_0F01_REG_0
) },
10241 { RM_TABLE (RM_0F01_REG_0
) },
10244 /* MOD_0F01_REG_1 */
10245 { X86_64_TABLE (X86_64_0F01_REG_1
) },
10246 { RM_TABLE (RM_0F01_REG_1
) },
10249 /* MOD_0F01_REG_2 */
10250 { X86_64_TABLE (X86_64_0F01_REG_2
) },
10251 { RM_TABLE (RM_0F01_REG_2
) },
10254 /* MOD_0F01_REG_3 */
10255 { X86_64_TABLE (X86_64_0F01_REG_3
) },
10256 { RM_TABLE (RM_0F01_REG_3
) },
10259 /* MOD_0F01_REG_5 */
10260 { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5
) },
10261 { RM_TABLE (RM_0F01_REG_5
) },
10264 /* MOD_0F01_REG_7 */
10265 { "invlpg", { Mb
}, 0 },
10266 { RM_TABLE (RM_0F01_REG_7
) },
10269 /* MOD_0F12_PREFIX_0 */
10270 { "movlps", { XM
, EXq
}, PREFIX_OPCODE
},
10271 { "movhlps", { XM
, EXq
}, PREFIX_OPCODE
},
10275 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
10278 /* MOD_0F16_PREFIX_0 */
10279 { "movhps", { XM
, EXq
}, 0 },
10280 { "movlhps", { XM
, EXq
}, 0 },
10284 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
10287 /* MOD_0F18_REG_0 */
10288 { "prefetchnta", { Mb
}, 0 },
10291 /* MOD_0F18_REG_1 */
10292 { "prefetcht0", { Mb
}, 0 },
10295 /* MOD_0F18_REG_2 */
10296 { "prefetcht1", { Mb
}, 0 },
10299 /* MOD_0F18_REG_3 */
10300 { "prefetcht2", { Mb
}, 0 },
10303 /* MOD_0F18_REG_4 */
10304 { "nop/reserved", { Mb
}, 0 },
10307 /* MOD_0F18_REG_5 */
10308 { "nop/reserved", { Mb
}, 0 },
10311 /* MOD_0F18_REG_6 */
10312 { "nop/reserved", { Mb
}, 0 },
10315 /* MOD_0F18_REG_7 */
10316 { "nop/reserved", { Mb
}, 0 },
10319 /* MOD_0F1A_PREFIX_0 */
10320 { "bndldx", { Gbnd
, Mv_bnd
}, 0 },
10321 { "nopQ", { Ev
}, 0 },
10324 /* MOD_0F1B_PREFIX_0 */
10325 { "bndstx", { Mv_bnd
, Gbnd
}, 0 },
10326 { "nopQ", { Ev
}, 0 },
10329 /* MOD_0F1B_PREFIX_1 */
10330 { "bndmk", { Gbnd
, Mv_bnd
}, 0 },
10331 { "nopQ", { Ev
}, 0 },
10334 /* MOD_0F1C_PREFIX_0 */
10335 { REG_TABLE (REG_0F1C_MOD_0
) },
10336 { "nopQ", { Ev
}, 0 },
10339 /* MOD_0F1E_PREFIX_1 */
10340 { "nopQ", { Ev
}, 0 },
10341 { REG_TABLE (REG_0F1E_MOD_3
) },
10346 { "movL", { Rd
, Td
}, 0 },
10351 { "movL", { Td
, Rd
}, 0 },
10354 /* MOD_0F2B_PREFIX_0 */
10355 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
10358 /* MOD_0F2B_PREFIX_1 */
10359 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
10362 /* MOD_0F2B_PREFIX_2 */
10363 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
10366 /* MOD_0F2B_PREFIX_3 */
10367 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
10372 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
10375 /* MOD_0F71_REG_2 */
10377 { "psrlw", { MS
, Ib
}, 0 },
10380 /* MOD_0F71_REG_4 */
10382 { "psraw", { MS
, Ib
}, 0 },
10385 /* MOD_0F71_REG_6 */
10387 { "psllw", { MS
, Ib
}, 0 },
10390 /* MOD_0F72_REG_2 */
10392 { "psrld", { MS
, Ib
}, 0 },
10395 /* MOD_0F72_REG_4 */
10397 { "psrad", { MS
, Ib
}, 0 },
10400 /* MOD_0F72_REG_6 */
10402 { "pslld", { MS
, Ib
}, 0 },
10405 /* MOD_0F73_REG_2 */
10407 { "psrlq", { MS
, Ib
}, 0 },
10410 /* MOD_0F73_REG_3 */
10412 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
10415 /* MOD_0F73_REG_6 */
10417 { "psllq", { MS
, Ib
}, 0 },
10420 /* MOD_0F73_REG_7 */
10422 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
10425 /* MOD_0FAE_REG_0 */
10426 { "fxsave", { FXSAVE
}, 0 },
10427 { PREFIX_TABLE (PREFIX_0FAE_REG_0
) },
10430 /* MOD_0FAE_REG_1 */
10431 { "fxrstor", { FXSAVE
}, 0 },
10432 { PREFIX_TABLE (PREFIX_0FAE_REG_1
) },
10435 /* MOD_0FAE_REG_2 */
10436 { "ldmxcsr", { Md
}, 0 },
10437 { PREFIX_TABLE (PREFIX_0FAE_REG_2
) },
10440 /* MOD_0FAE_REG_3 */
10441 { "stmxcsr", { Md
}, 0 },
10442 { PREFIX_TABLE (PREFIX_0FAE_REG_3
) },
10445 /* MOD_0FAE_REG_4 */
10446 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4
) },
10447 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4
) },
10450 /* MOD_0FAE_REG_5 */
10451 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5
) },
10452 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5
) },
10455 /* MOD_0FAE_REG_6 */
10456 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6
) },
10457 { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6
) },
10460 /* MOD_0FAE_REG_7 */
10461 { PREFIX_TABLE (PREFIX_0FAE_REG_7
) },
10462 { RM_TABLE (RM_0FAE_REG_7
) },
10466 { "lssS", { Gv
, Mp
}, 0 },
10470 { "lfsS", { Gv
, Mp
}, 0 },
10474 { "lgsS", { Gv
, Mp
}, 0 },
10478 { PREFIX_TABLE (PREFIX_MOD_0_0FC3
) },
10481 /* MOD_0FC7_REG_3 */
10482 { "xrstors", { FXSAVE
}, 0 },
10485 /* MOD_0FC7_REG_4 */
10486 { "xsavec", { FXSAVE
}, 0 },
10489 /* MOD_0FC7_REG_5 */
10490 { "xsaves", { FXSAVE
}, 0 },
10493 /* MOD_0FC7_REG_6 */
10494 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6
) },
10495 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6
) }
10498 /* MOD_0FC7_REG_7 */
10499 { "vmptrst", { Mq
}, 0 },
10500 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7
) }
10505 { "pmovmskb", { Gdq
, MS
}, 0 },
10508 /* MOD_0FE7_PREFIX_2 */
10509 { "movntdq", { Mx
, XM
}, 0 },
10512 /* MOD_0FF0_PREFIX_3 */
10513 { "lddqu", { XM
, M
}, 0 },
10516 /* MOD_0F382A_PREFIX_2 */
10517 { "movntdqa", { XM
, Mx
}, 0 },
10520 /* MOD_0F38F5_PREFIX_2 */
10521 { "wrussK", { M
, Gdq
}, PREFIX_OPCODE
},
10524 /* MOD_0F38F6_PREFIX_0 */
10525 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
10528 /* MOD_0F38F8_PREFIX_1 */
10529 { "enqcmds", { Gva
, M
}, PREFIX_OPCODE
},
10532 /* MOD_0F38F8_PREFIX_2 */
10533 { "movdir64b", { Gva
, M
}, PREFIX_OPCODE
},
10536 /* MOD_0F38F8_PREFIX_3 */
10537 { "enqcmd", { Gva
, M
}, PREFIX_OPCODE
},
10540 /* MOD_0F38F9_PREFIX_0 */
10541 { "movdiri", { Em
, Gv
}, PREFIX_OPCODE
},
10545 { "bound{S|}", { Gv
, Ma
}, 0 },
10546 { EVEX_TABLE (EVEX_0F
) },
10550 { "lesS", { Gv
, Mp
}, 0 },
10551 { VEX_C4_TABLE (VEX_0F
) },
10555 { "ldsS", { Gv
, Mp
}, 0 },
10556 { VEX_C5_TABLE (VEX_0F
) },
10559 /* MOD_VEX_0F12_PREFIX_0 */
10560 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
10561 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
10565 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
10568 /* MOD_VEX_0F16_PREFIX_0 */
10569 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
10570 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
10574 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
10578 { "vmovntpX", { Mx
, XM
}, 0 },
10581 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10583 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
10586 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10588 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
10591 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10593 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
10596 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10598 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
10601 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10603 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
10606 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10608 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
10611 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10613 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
10616 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10618 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
10621 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10623 { "knotw", { MaskG
, MaskR
}, 0 },
10626 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10628 { "knotq", { MaskG
, MaskR
}, 0 },
10631 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10633 { "knotb", { MaskG
, MaskR
}, 0 },
10636 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10638 { "knotd", { MaskG
, MaskR
}, 0 },
10641 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10643 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
10646 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10648 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
10651 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10653 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
10656 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10658 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
10661 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10663 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10666 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10668 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10671 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10673 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10676 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10678 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
10681 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10683 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10686 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10688 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10691 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10693 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10696 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10698 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
10701 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10703 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
10706 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10708 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
10711 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10713 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
10716 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10718 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
10721 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10723 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
10726 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10728 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
10731 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10733 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
10738 { "vmovmskpX", { Gdq
, XS
}, 0 },
10741 /* MOD_VEX_0F71_REG_2 */
10743 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
10746 /* MOD_VEX_0F71_REG_4 */
10748 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
10751 /* MOD_VEX_0F71_REG_6 */
10753 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
10756 /* MOD_VEX_0F72_REG_2 */
10758 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
10761 /* MOD_VEX_0F72_REG_4 */
10763 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
10766 /* MOD_VEX_0F72_REG_6 */
10768 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
10771 /* MOD_VEX_0F73_REG_2 */
10773 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
10776 /* MOD_VEX_0F73_REG_3 */
10778 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
10781 /* MOD_VEX_0F73_REG_6 */
10783 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
10786 /* MOD_VEX_0F73_REG_7 */
10788 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
10791 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10792 { "kmovw", { Ew
, MaskG
}, 0 },
10796 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10797 { "kmovq", { Eq
, MaskG
}, 0 },
10801 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10802 { "kmovb", { Eb
, MaskG
}, 0 },
10806 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10807 { "kmovd", { Ed
, MaskG
}, 0 },
10811 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10813 { "kmovw", { MaskG
, Rdq
}, 0 },
10816 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10818 { "kmovb", { MaskG
, Rdq
}, 0 },
10821 /* MOD_VEX_0F92_P_3_LEN_0 */
10823 { "kmovK", { MaskG
, Rdq
}, 0 },
10826 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10828 { "kmovw", { Gdq
, MaskR
}, 0 },
10831 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10833 { "kmovb", { Gdq
, MaskR
}, 0 },
10836 /* MOD_VEX_0F93_P_3_LEN_0 */
10838 { "kmovK", { Gdq
, MaskR
}, 0 },
10841 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10843 { "kortestw", { MaskG
, MaskR
}, 0 },
10846 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10848 { "kortestq", { MaskG
, MaskR
}, 0 },
10851 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10853 { "kortestb", { MaskG
, MaskR
}, 0 },
10856 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10858 { "kortestd", { MaskG
, MaskR
}, 0 },
10861 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10863 { "ktestw", { MaskG
, MaskR
}, 0 },
10866 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10868 { "ktestq", { MaskG
, MaskR
}, 0 },
10871 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10873 { "ktestb", { MaskG
, MaskR
}, 0 },
10876 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10878 { "ktestd", { MaskG
, MaskR
}, 0 },
10881 /* MOD_VEX_0FAE_REG_2 */
10882 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
10885 /* MOD_VEX_0FAE_REG_3 */
10886 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
10889 /* MOD_VEX_0FD7_PREFIX_2 */
10891 { "vpmovmskb", { Gdq
, XS
}, 0 },
10894 /* MOD_VEX_0FE7_PREFIX_2 */
10895 { "vmovntdq", { Mx
, XM
}, 0 },
10898 /* MOD_VEX_0FF0_PREFIX_3 */
10899 { "vlddqu", { XM
, M
}, 0 },
10902 /* MOD_VEX_0F381A_PREFIX_2 */
10903 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
10906 /* MOD_VEX_0F382A_PREFIX_2 */
10907 { "vmovntdqa", { XM
, Mx
}, 0 },
10910 /* MOD_VEX_0F382C_PREFIX_2 */
10911 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
10914 /* MOD_VEX_0F382D_PREFIX_2 */
10915 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
10918 /* MOD_VEX_0F382E_PREFIX_2 */
10919 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
10922 /* MOD_VEX_0F382F_PREFIX_2 */
10923 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
10926 /* MOD_VEX_0F385A_PREFIX_2 */
10927 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
10930 /* MOD_VEX_0F388C_PREFIX_2 */
10931 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
10934 /* MOD_VEX_0F388E_PREFIX_2 */
10935 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
10938 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10940 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
10943 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10945 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
10948 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10950 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
10953 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10955 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
10958 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10960 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
10963 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10965 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
10968 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10970 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
10973 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10975 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
10977 #define NEED_MOD_TABLE
10978 #include "i386-dis-evex.h"
10979 #undef NEED_MOD_TABLE
10982 static const struct dis386 rm_table
[][8] = {
10985 { "xabort", { Skip_MODRM
, Ib
}, 0 },
10989 { "xbeginT", { Skip_MODRM
, Jv
}, 0 },
10992 /* RM_0F01_REG_0 */
10993 { "enclv", { Skip_MODRM
}, 0 },
10994 { "vmcall", { Skip_MODRM
}, 0 },
10995 { "vmlaunch", { Skip_MODRM
}, 0 },
10996 { "vmresume", { Skip_MODRM
}, 0 },
10997 { "vmxoff", { Skip_MODRM
}, 0 },
10998 { "pconfig", { Skip_MODRM
}, 0 },
11001 /* RM_0F01_REG_1 */
11002 { "monitor", { { OP_Monitor
, 0 } }, 0 },
11003 { "mwait", { { OP_Mwait
, 0 } }, 0 },
11004 { "clac", { Skip_MODRM
}, 0 },
11005 { "stac", { Skip_MODRM
}, 0 },
11009 { "encls", { Skip_MODRM
}, 0 },
11012 /* RM_0F01_REG_2 */
11013 { "xgetbv", { Skip_MODRM
}, 0 },
11014 { "xsetbv", { Skip_MODRM
}, 0 },
11017 { "vmfunc", { Skip_MODRM
}, 0 },
11018 { "xend", { Skip_MODRM
}, 0 },
11019 { "xtest", { Skip_MODRM
}, 0 },
11020 { "enclu", { Skip_MODRM
}, 0 },
11023 /* RM_0F01_REG_3 */
11024 { "vmrun", { Skip_MODRM
}, 0 },
11025 { "vmmcall", { Skip_MODRM
}, 0 },
11026 { "vmload", { Skip_MODRM
}, 0 },
11027 { "vmsave", { Skip_MODRM
}, 0 },
11028 { "stgi", { Skip_MODRM
}, 0 },
11029 { "clgi", { Skip_MODRM
}, 0 },
11030 { "skinit", { Skip_MODRM
}, 0 },
11031 { "invlpga", { Skip_MODRM
}, 0 },
11034 /* RM_0F01_REG_5 */
11035 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0
) },
11037 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2
) },
11041 { "rdpkru", { Skip_MODRM
}, 0 },
11042 { "wrpkru", { Skip_MODRM
}, 0 },
11045 /* RM_0F01_REG_7 */
11046 { "swapgs", { Skip_MODRM
}, 0 },
11047 { "rdtscp", { Skip_MODRM
}, 0 },
11048 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
11049 { "mwaitx", { { OP_Mwaitx
, 0 } }, 0 },
11050 { "clzero", { Skip_MODRM
}, 0 },
11053 /* RM_0F1E_MOD_3_REG_7 */
11054 { "nopQ", { Ev
}, 0 },
11055 { "nopQ", { Ev
}, 0 },
11056 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
11057 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
11058 { "nopQ", { Ev
}, 0 },
11059 { "nopQ", { Ev
}, 0 },
11060 { "nopQ", { Ev
}, 0 },
11061 { "nopQ", { Ev
}, 0 },
11064 /* RM_0FAE_REG_6 */
11065 { "mfence", { Skip_MODRM
}, 0 },
11068 /* RM_0FAE_REG_7 */
11069 { "sfence", { Skip_MODRM
}, 0 },
11074 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11076 /* We use the high bit to indicate different name for the same
11078 #define REP_PREFIX (0xf3 | 0x100)
11079 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11080 #define XRELEASE_PREFIX (0xf3 | 0x400)
11081 #define BND_PREFIX (0xf2 | 0x400)
11082 #define NOTRACK_PREFIX (0x3e | 0x100)
11087 int newrex
, i
, length
;
11093 last_lock_prefix
= -1;
11094 last_repz_prefix
= -1;
11095 last_repnz_prefix
= -1;
11096 last_data_prefix
= -1;
11097 last_addr_prefix
= -1;
11098 last_rex_prefix
= -1;
11099 last_seg_prefix
= -1;
11101 active_seg_prefix
= 0;
11102 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11103 all_prefixes
[i
] = 0;
11106 /* The maximum instruction length is 15bytes. */
11107 while (length
< MAX_CODE_LENGTH
- 1)
11109 FETCH_DATA (the_info
, codep
+ 1);
11113 /* REX prefixes family. */
11130 if (address_mode
== mode_64bit
)
11134 last_rex_prefix
= i
;
11137 prefixes
|= PREFIX_REPZ
;
11138 last_repz_prefix
= i
;
11141 prefixes
|= PREFIX_REPNZ
;
11142 last_repnz_prefix
= i
;
11145 prefixes
|= PREFIX_LOCK
;
11146 last_lock_prefix
= i
;
11149 prefixes
|= PREFIX_CS
;
11150 last_seg_prefix
= i
;
11151 active_seg_prefix
= PREFIX_CS
;
11154 prefixes
|= PREFIX_SS
;
11155 last_seg_prefix
= i
;
11156 active_seg_prefix
= PREFIX_SS
;
11159 prefixes
|= PREFIX_DS
;
11160 last_seg_prefix
= i
;
11161 active_seg_prefix
= PREFIX_DS
;
11164 prefixes
|= PREFIX_ES
;
11165 last_seg_prefix
= i
;
11166 active_seg_prefix
= PREFIX_ES
;
11169 prefixes
|= PREFIX_FS
;
11170 last_seg_prefix
= i
;
11171 active_seg_prefix
= PREFIX_FS
;
11174 prefixes
|= PREFIX_GS
;
11175 last_seg_prefix
= i
;
11176 active_seg_prefix
= PREFIX_GS
;
11179 prefixes
|= PREFIX_DATA
;
11180 last_data_prefix
= i
;
11183 prefixes
|= PREFIX_ADDR
;
11184 last_addr_prefix
= i
;
11187 /* fwait is really an instruction. If there are prefixes
11188 before the fwait, they belong to the fwait, *not* to the
11189 following instruction. */
11191 if (prefixes
|| rex
)
11193 prefixes
|= PREFIX_FWAIT
;
11195 /* This ensures that the previous REX prefixes are noticed
11196 as unused prefixes, as in the return case below. */
11200 prefixes
= PREFIX_FWAIT
;
11205 /* Rex is ignored when followed by another prefix. */
11211 if (*codep
!= FWAIT_OPCODE
)
11212 all_prefixes
[i
++] = *codep
;
11220 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11223 static const char *
11224 prefix_name (int pref
, int sizeflag
)
11226 static const char *rexes
[16] =
11229 "rex.B", /* 0x41 */
11230 "rex.X", /* 0x42 */
11231 "rex.XB", /* 0x43 */
11232 "rex.R", /* 0x44 */
11233 "rex.RB", /* 0x45 */
11234 "rex.RX", /* 0x46 */
11235 "rex.RXB", /* 0x47 */
11236 "rex.W", /* 0x48 */
11237 "rex.WB", /* 0x49 */
11238 "rex.WX", /* 0x4a */
11239 "rex.WXB", /* 0x4b */
11240 "rex.WR", /* 0x4c */
11241 "rex.WRB", /* 0x4d */
11242 "rex.WRX", /* 0x4e */
11243 "rex.WRXB", /* 0x4f */
11248 /* REX prefixes family. */
11265 return rexes
[pref
- 0x40];
11285 return (sizeflag
& DFLAG
) ? "data16" : "data32";
11287 if (address_mode
== mode_64bit
)
11288 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
11290 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
11295 case XACQUIRE_PREFIX
:
11297 case XRELEASE_PREFIX
:
11301 case NOTRACK_PREFIX
:
11308 static char op_out
[MAX_OPERANDS
][100];
11309 static int op_ad
, op_index
[MAX_OPERANDS
];
11310 static int two_source_ops
;
11311 static bfd_vma op_address
[MAX_OPERANDS
];
11312 static bfd_vma op_riprel
[MAX_OPERANDS
];
11313 static bfd_vma start_pc
;
11316 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11317 * (see topic "Redundant prefixes" in the "Differences from 8086"
11318 * section of the "Virtual 8086 Mode" chapter.)
11319 * 'pc' should be the address of this instruction, it will
11320 * be used to print the target address if this is a relative jump or call
11321 * The function returns the length of this instruction in bytes.
11324 static char intel_syntax
;
11325 static char intel_mnemonic
= !SYSV386_COMPAT
;
11326 static char open_char
;
11327 static char close_char
;
11328 static char separator_char
;
11329 static char scale_char
;
11337 static enum x86_64_isa isa64
;
11339 /* Here for backwards compatibility. When gdb stops using
11340 print_insn_i386_att and print_insn_i386_intel these functions can
11341 disappear, and print_insn_i386 be merged into print_insn. */
11343 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
11347 return print_insn (pc
, info
);
11351 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
11355 return print_insn (pc
, info
);
11359 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
11363 return print_insn (pc
, info
);
11367 print_i386_disassembler_options (FILE *stream
)
11369 fprintf (stream
, _("\n\
11370 The following i386/x86-64 specific disassembler options are supported for use\n\
11371 with the -M switch (multiple options should be separated by commas):\n"));
11373 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
11374 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
11375 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
11376 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
11377 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
11378 fprintf (stream
, _(" att-mnemonic\n"
11379 " Display instruction in AT&T mnemonic\n"));
11380 fprintf (stream
, _(" intel-mnemonic\n"
11381 " Display instruction in Intel mnemonic\n"));
11382 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
11383 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
11384 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
11385 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
11386 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
11387 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11388 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
11389 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
11393 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
11395 /* Get a pointer to struct dis386 with a valid name. */
11397 static const struct dis386
*
11398 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
11400 int vindex
, vex_table_index
;
11402 if (dp
->name
!= NULL
)
11405 switch (dp
->op
[0].bytemode
)
11407 case USE_REG_TABLE
:
11408 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
11411 case USE_MOD_TABLE
:
11412 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
11413 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
11417 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
11420 case USE_PREFIX_TABLE
:
11423 /* The prefix in VEX is implicit. */
11424 switch (vex
.prefix
)
11429 case REPE_PREFIX_OPCODE
:
11432 case DATA_PREFIX_OPCODE
:
11435 case REPNE_PREFIX_OPCODE
:
11445 int last_prefix
= -1;
11448 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11449 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11451 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
11453 if (last_repz_prefix
> last_repnz_prefix
)
11456 prefix
= PREFIX_REPZ
;
11457 last_prefix
= last_repz_prefix
;
11462 prefix
= PREFIX_REPNZ
;
11463 last_prefix
= last_repnz_prefix
;
11466 /* Check if prefix should be ignored. */
11467 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
11468 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
11473 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
11476 prefix
= PREFIX_DATA
;
11477 last_prefix
= last_data_prefix
;
11482 used_prefixes
|= prefix
;
11483 all_prefixes
[last_prefix
] = 0;
11486 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
11489 case USE_X86_64_TABLE
:
11490 vindex
= address_mode
== mode_64bit
? 1 : 0;
11491 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
11494 case USE_3BYTE_TABLE
:
11495 FETCH_DATA (info
, codep
+ 2);
11497 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
11499 modrm
.mod
= (*codep
>> 6) & 3;
11500 modrm
.reg
= (*codep
>> 3) & 7;
11501 modrm
.rm
= *codep
& 7;
11504 case USE_VEX_LEN_TABLE
:
11508 switch (vex
.length
)
11521 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
11524 case USE_EVEX_LEN_TABLE
:
11528 switch (vex
.length
)
11544 dp
= &evex_len_table
[dp
->op
[1].bytemode
][vindex
];
11547 case USE_XOP_8F_TABLE
:
11548 FETCH_DATA (info
, codep
+ 3);
11549 /* All bits in the REX prefix are ignored. */
11551 rex
= ~(*codep
>> 5) & 0x7;
11553 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11554 switch ((*codep
& 0x1f))
11560 vex_table_index
= XOP_08
;
11563 vex_table_index
= XOP_09
;
11566 vex_table_index
= XOP_0A
;
11570 vex
.w
= *codep
& 0x80;
11571 if (vex
.w
&& address_mode
== mode_64bit
)
11574 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11575 if (address_mode
!= mode_64bit
)
11577 /* In 16/32-bit mode REX_B is silently ignored. */
11581 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11582 switch ((*codep
& 0x3))
11587 vex
.prefix
= DATA_PREFIX_OPCODE
;
11590 vex
.prefix
= REPE_PREFIX_OPCODE
;
11593 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11600 dp
= &xop_table
[vex_table_index
][vindex
];
11603 FETCH_DATA (info
, codep
+ 1);
11604 modrm
.mod
= (*codep
>> 6) & 3;
11605 modrm
.reg
= (*codep
>> 3) & 7;
11606 modrm
.rm
= *codep
& 7;
11609 case USE_VEX_C4_TABLE
:
11611 FETCH_DATA (info
, codep
+ 3);
11612 /* All bits in the REX prefix are ignored. */
11614 rex
= ~(*codep
>> 5) & 0x7;
11615 switch ((*codep
& 0x1f))
11621 vex_table_index
= VEX_0F
;
11624 vex_table_index
= VEX_0F38
;
11627 vex_table_index
= VEX_0F3A
;
11631 vex
.w
= *codep
& 0x80;
11632 if (address_mode
== mode_64bit
)
11639 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11640 is ignored, other REX bits are 0 and the highest bit in
11641 VEX.vvvv is also ignored (but we mustn't clear it here). */
11644 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11645 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11646 switch ((*codep
& 0x3))
11651 vex
.prefix
= DATA_PREFIX_OPCODE
;
11654 vex
.prefix
= REPE_PREFIX_OPCODE
;
11657 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11664 dp
= &vex_table
[vex_table_index
][vindex
];
11666 /* There is no MODRM byte for VEX0F 77. */
11667 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
11669 FETCH_DATA (info
, codep
+ 1);
11670 modrm
.mod
= (*codep
>> 6) & 3;
11671 modrm
.reg
= (*codep
>> 3) & 7;
11672 modrm
.rm
= *codep
& 7;
11676 case USE_VEX_C5_TABLE
:
11678 FETCH_DATA (info
, codep
+ 2);
11679 /* All bits in the REX prefix are ignored. */
11681 rex
= (*codep
& 0x80) ? 0 : REX_R
;
11683 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11685 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11686 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11687 switch ((*codep
& 0x3))
11692 vex
.prefix
= DATA_PREFIX_OPCODE
;
11695 vex
.prefix
= REPE_PREFIX_OPCODE
;
11698 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11705 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
11707 /* There is no MODRM byte for VEX 77. */
11708 if (vindex
!= 0x77)
11710 FETCH_DATA (info
, codep
+ 1);
11711 modrm
.mod
= (*codep
>> 6) & 3;
11712 modrm
.reg
= (*codep
>> 3) & 7;
11713 modrm
.rm
= *codep
& 7;
11717 case USE_VEX_W_TABLE
:
11721 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
11724 case USE_EVEX_TABLE
:
11725 two_source_ops
= 0;
11728 FETCH_DATA (info
, codep
+ 4);
11729 /* All bits in the REX prefix are ignored. */
11731 /* The first byte after 0x62. */
11732 rex
= ~(*codep
>> 5) & 0x7;
11733 vex
.r
= *codep
& 0x10;
11734 switch ((*codep
& 0xf))
11737 return &bad_opcode
;
11739 vex_table_index
= EVEX_0F
;
11742 vex_table_index
= EVEX_0F38
;
11745 vex_table_index
= EVEX_0F3A
;
11749 /* The second byte after 0x62. */
11751 vex
.w
= *codep
& 0x80;
11752 if (vex
.w
&& address_mode
== mode_64bit
)
11755 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11758 if (!(*codep
& 0x4))
11759 return &bad_opcode
;
11761 switch ((*codep
& 0x3))
11766 vex
.prefix
= DATA_PREFIX_OPCODE
;
11769 vex
.prefix
= REPE_PREFIX_OPCODE
;
11772 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11776 /* The third byte after 0x62. */
11779 /* Remember the static rounding bits. */
11780 vex
.ll
= (*codep
>> 5) & 3;
11781 vex
.b
= (*codep
& 0x10) != 0;
11783 vex
.v
= *codep
& 0x8;
11784 vex
.mask_register_specifier
= *codep
& 0x7;
11785 vex
.zeroing
= *codep
& 0x80;
11787 if (address_mode
!= mode_64bit
)
11789 /* In 16/32-bit mode silently ignore following bits. */
11799 dp
= &evex_table
[vex_table_index
][vindex
];
11801 FETCH_DATA (info
, codep
+ 1);
11802 modrm
.mod
= (*codep
>> 6) & 3;
11803 modrm
.reg
= (*codep
>> 3) & 7;
11804 modrm
.rm
= *codep
& 7;
11806 /* Set vector length. */
11807 if (modrm
.mod
== 3 && vex
.b
)
11823 return &bad_opcode
;
11836 if (dp
->name
!= NULL
)
11839 return get_valid_dis386 (dp
, info
);
11843 get_sib (disassemble_info
*info
, int sizeflag
)
11845 /* If modrm.mod == 3, operand must be register. */
11847 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11851 FETCH_DATA (info
, codep
+ 2);
11852 sib
.index
= (codep
[1] >> 3) & 7;
11853 sib
.scale
= (codep
[1] >> 6) & 3;
11854 sib
.base
= codep
[1] & 7;
11859 print_insn (bfd_vma pc
, disassemble_info
*info
)
11861 const struct dis386
*dp
;
11863 char *op_txt
[MAX_OPERANDS
];
11865 int sizeflag
, orig_sizeflag
;
11867 struct dis_private priv
;
11870 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11871 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
11872 address_mode
= mode_32bit
;
11873 else if (info
->mach
== bfd_mach_i386_i8086
)
11875 address_mode
= mode_16bit
;
11876 priv
.orig_sizeflag
= 0;
11879 address_mode
= mode_64bit
;
11881 if (intel_syntax
== (char) -1)
11882 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
11884 for (p
= info
->disassembler_options
; p
!= NULL
; )
11886 if (CONST_STRNEQ (p
, "amd64"))
11888 else if (CONST_STRNEQ (p
, "intel64"))
11890 else if (CONST_STRNEQ (p
, "x86-64"))
11892 address_mode
= mode_64bit
;
11893 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11895 else if (CONST_STRNEQ (p
, "i386"))
11897 address_mode
= mode_32bit
;
11898 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11900 else if (CONST_STRNEQ (p
, "i8086"))
11902 address_mode
= mode_16bit
;
11903 priv
.orig_sizeflag
= 0;
11905 else if (CONST_STRNEQ (p
, "intel"))
11908 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
11909 intel_mnemonic
= 1;
11911 else if (CONST_STRNEQ (p
, "att"))
11914 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
11915 intel_mnemonic
= 0;
11917 else if (CONST_STRNEQ (p
, "addr"))
11919 if (address_mode
== mode_64bit
)
11921 if (p
[4] == '3' && p
[5] == '2')
11922 priv
.orig_sizeflag
&= ~AFLAG
;
11923 else if (p
[4] == '6' && p
[5] == '4')
11924 priv
.orig_sizeflag
|= AFLAG
;
11928 if (p
[4] == '1' && p
[5] == '6')
11929 priv
.orig_sizeflag
&= ~AFLAG
;
11930 else if (p
[4] == '3' && p
[5] == '2')
11931 priv
.orig_sizeflag
|= AFLAG
;
11934 else if (CONST_STRNEQ (p
, "data"))
11936 if (p
[4] == '1' && p
[5] == '6')
11937 priv
.orig_sizeflag
&= ~DFLAG
;
11938 else if (p
[4] == '3' && p
[5] == '2')
11939 priv
.orig_sizeflag
|= DFLAG
;
11941 else if (CONST_STRNEQ (p
, "suffix"))
11942 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
11944 p
= strchr (p
, ',');
11949 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
11951 (*info
->fprintf_func
) (info
->stream
,
11952 _("64-bit address is disabled"));
11958 names64
= intel_names64
;
11959 names32
= intel_names32
;
11960 names16
= intel_names16
;
11961 names8
= intel_names8
;
11962 names8rex
= intel_names8rex
;
11963 names_seg
= intel_names_seg
;
11964 names_mm
= intel_names_mm
;
11965 names_bnd
= intel_names_bnd
;
11966 names_xmm
= intel_names_xmm
;
11967 names_ymm
= intel_names_ymm
;
11968 names_zmm
= intel_names_zmm
;
11969 index64
= intel_index64
;
11970 index32
= intel_index32
;
11971 names_mask
= intel_names_mask
;
11972 index16
= intel_index16
;
11975 separator_char
= '+';
11980 names64
= att_names64
;
11981 names32
= att_names32
;
11982 names16
= att_names16
;
11983 names8
= att_names8
;
11984 names8rex
= att_names8rex
;
11985 names_seg
= att_names_seg
;
11986 names_mm
= att_names_mm
;
11987 names_bnd
= att_names_bnd
;
11988 names_xmm
= att_names_xmm
;
11989 names_ymm
= att_names_ymm
;
11990 names_zmm
= att_names_zmm
;
11991 index64
= att_index64
;
11992 index32
= att_index32
;
11993 names_mask
= att_names_mask
;
11994 index16
= att_index16
;
11997 separator_char
= ',';
12001 /* The output looks better if we put 7 bytes on a line, since that
12002 puts most long word instructions on a single line. Use 8 bytes
12004 if ((info
->mach
& bfd_mach_l1om
) != 0)
12005 info
->bytes_per_line
= 8;
12007 info
->bytes_per_line
= 7;
12009 info
->private_data
= &priv
;
12010 priv
.max_fetched
= priv
.the_buffer
;
12011 priv
.insn_start
= pc
;
12014 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12022 start_codep
= priv
.the_buffer
;
12023 codep
= priv
.the_buffer
;
12025 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
12029 /* Getting here means we tried for data but didn't get it. That
12030 means we have an incomplete instruction of some sort. Just
12031 print the first byte as a prefix or a .byte pseudo-op. */
12032 if (codep
> priv
.the_buffer
)
12034 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
12036 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
12039 /* Just print the first byte as a .byte instruction. */
12040 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
12041 (unsigned int) priv
.the_buffer
[0]);
12051 sizeflag
= priv
.orig_sizeflag
;
12053 if (!ckprefix () || rex_used
)
12055 /* Too many prefixes or unused REX prefixes. */
12057 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
12059 (*info
->fprintf_func
) (info
->stream
, "%s%s",
12061 prefix_name (all_prefixes
[i
], sizeflag
));
12065 insn_codep
= codep
;
12067 FETCH_DATA (info
, codep
+ 1);
12068 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
12070 if (((prefixes
& PREFIX_FWAIT
)
12071 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
12073 /* Handle prefixes before fwait. */
12074 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
12076 (*info
->fprintf_func
) (info
->stream
, "%s ",
12077 prefix_name (all_prefixes
[i
], sizeflag
));
12078 (*info
->fprintf_func
) (info
->stream
, "fwait");
12082 if (*codep
== 0x0f)
12084 unsigned char threebyte
;
12087 FETCH_DATA (info
, codep
+ 1);
12088 threebyte
= *codep
;
12089 dp
= &dis386_twobyte
[threebyte
];
12090 need_modrm
= twobyte_has_modrm
[*codep
];
12095 dp
= &dis386
[*codep
];
12096 need_modrm
= onebyte_has_modrm
[*codep
];
12100 /* Save sizeflag for printing the extra prefixes later before updating
12101 it for mnemonic and operand processing. The prefix names depend
12102 only on the address mode. */
12103 orig_sizeflag
= sizeflag
;
12104 if (prefixes
& PREFIX_ADDR
)
12106 if ((prefixes
& PREFIX_DATA
))
12112 FETCH_DATA (info
, codep
+ 1);
12113 modrm
.mod
= (*codep
>> 6) & 3;
12114 modrm
.reg
= (*codep
>> 3) & 7;
12115 modrm
.rm
= *codep
& 7;
12121 memset (&vex
, 0, sizeof (vex
));
12123 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
12125 get_sib (info
, sizeflag
);
12126 dofloat (sizeflag
);
12130 dp
= get_valid_dis386 (dp
, info
);
12131 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
12133 get_sib (info
, sizeflag
);
12134 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12137 op_ad
= MAX_OPERANDS
- 1 - i
;
12139 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
12140 /* For EVEX instruction after the last operand masking
12141 should be printed. */
12142 if (i
== 0 && vex
.evex
)
12144 /* Don't print {%k0}. */
12145 if (vex
.mask_register_specifier
)
12148 oappend (names_mask
[vex
.mask_register_specifier
]);
12158 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12159 are all 0s in inverted form. */
12160 if (need_vex
&& vex
.register_specifier
!= 0)
12162 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12163 return end_codep
- priv
.the_buffer
;
12166 /* Check if the REX prefix is used. */
12167 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
12168 all_prefixes
[last_rex_prefix
] = 0;
12170 /* Check if the SEG prefix is used. */
12171 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
12172 | PREFIX_FS
| PREFIX_GS
)) != 0
12173 && (used_prefixes
& active_seg_prefix
) != 0)
12174 all_prefixes
[last_seg_prefix
] = 0;
12176 /* Check if the ADDR prefix is used. */
12177 if ((prefixes
& PREFIX_ADDR
) != 0
12178 && (used_prefixes
& PREFIX_ADDR
) != 0)
12179 all_prefixes
[last_addr_prefix
] = 0;
12181 /* Check if the DATA prefix is used. */
12182 if ((prefixes
& PREFIX_DATA
) != 0
12183 && (used_prefixes
& PREFIX_DATA
) != 0)
12184 all_prefixes
[last_data_prefix
] = 0;
12186 /* Print the extra prefixes. */
12188 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12189 if (all_prefixes
[i
])
12192 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
12195 prefix_length
+= strlen (name
) + 1;
12196 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
12199 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12200 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
12201 used by putop and MMX/SSE operand and may be overriden by the
12202 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12204 if (dp
->prefix_requirement
== PREFIX_OPCODE
12205 && dp
!= &bad_opcode
12207 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
12209 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
12211 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
12213 && (used_prefixes
& PREFIX_DATA
) == 0))))
12215 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12216 return end_codep
- priv
.the_buffer
;
12219 /* Check maximum code length. */
12220 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
12222 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12223 return MAX_CODE_LENGTH
;
12226 obufp
= mnemonicendp
;
12227 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
12230 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
12232 /* The enter and bound instructions are printed with operands in the same
12233 order as the intel book; everything else is printed in reverse order. */
12234 if (intel_syntax
|| two_source_ops
)
12238 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12239 op_txt
[i
] = op_out
[i
];
12241 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
12242 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
12244 op_txt
[2] = op_out
[3];
12245 op_txt
[3] = op_out
[2];
12248 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
12250 op_ad
= op_index
[i
];
12251 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
12252 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
12253 riprel
= op_riprel
[i
];
12254 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
12255 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
12260 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12261 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
12265 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12269 (*info
->fprintf_func
) (info
->stream
, ",");
12270 if (op_index
[i
] != -1 && !op_riprel
[i
])
12271 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
12273 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
12277 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12278 if (op_index
[i
] != -1 && op_riprel
[i
])
12280 (*info
->fprintf_func
) (info
->stream
, " # ");
12281 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
12282 + op_address
[op_index
[i
]]), info
);
12285 return codep
- priv
.the_buffer
;
12288 static const char *float_mem
[] = {
12363 static const unsigned char float_mem_mode
[] = {
12438 #define ST { OP_ST, 0 }
12439 #define STi { OP_STi, 0 }
12441 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12442 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12443 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12444 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12445 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12446 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12447 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12448 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12449 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12451 static const struct dis386 float_reg
[][8] = {
12454 { "fadd", { ST
, STi
}, 0 },
12455 { "fmul", { ST
, STi
}, 0 },
12456 { "fcom", { STi
}, 0 },
12457 { "fcomp", { STi
}, 0 },
12458 { "fsub", { ST
, STi
}, 0 },
12459 { "fsubr", { ST
, STi
}, 0 },
12460 { "fdiv", { ST
, STi
}, 0 },
12461 { "fdivr", { ST
, STi
}, 0 },
12465 { "fld", { STi
}, 0 },
12466 { "fxch", { STi
}, 0 },
12476 { "fcmovb", { ST
, STi
}, 0 },
12477 { "fcmove", { ST
, STi
}, 0 },
12478 { "fcmovbe",{ ST
, STi
}, 0 },
12479 { "fcmovu", { ST
, STi
}, 0 },
12487 { "fcmovnb",{ ST
, STi
}, 0 },
12488 { "fcmovne",{ ST
, STi
}, 0 },
12489 { "fcmovnbe",{ ST
, STi
}, 0 },
12490 { "fcmovnu",{ ST
, STi
}, 0 },
12492 { "fucomi", { ST
, STi
}, 0 },
12493 { "fcomi", { ST
, STi
}, 0 },
12498 { "fadd", { STi
, ST
}, 0 },
12499 { "fmul", { STi
, ST
}, 0 },
12502 { "fsub{!M|r}", { STi
, ST
}, 0 },
12503 { "fsub{M|}", { STi
, ST
}, 0 },
12504 { "fdiv{!M|r}", { STi
, ST
}, 0 },
12505 { "fdiv{M|}", { STi
, ST
}, 0 },
12509 { "ffree", { STi
}, 0 },
12511 { "fst", { STi
}, 0 },
12512 { "fstp", { STi
}, 0 },
12513 { "fucom", { STi
}, 0 },
12514 { "fucomp", { STi
}, 0 },
12520 { "faddp", { STi
, ST
}, 0 },
12521 { "fmulp", { STi
, ST
}, 0 },
12524 { "fsub{!M|r}p", { STi
, ST
}, 0 },
12525 { "fsub{M|}p", { STi
, ST
}, 0 },
12526 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
12527 { "fdiv{M|}p", { STi
, ST
}, 0 },
12531 { "ffreep", { STi
}, 0 },
12536 { "fucomip", { ST
, STi
}, 0 },
12537 { "fcomip", { ST
, STi
}, 0 },
12542 static char *fgrps
[][8] = {
12545 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12550 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12555 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12560 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12565 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12570 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12575 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12580 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12581 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12586 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12591 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12596 swap_operand (void)
12598 mnemonicendp
[0] = '.';
12599 mnemonicendp
[1] = 's';
12604 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
12605 int sizeflag ATTRIBUTE_UNUSED
)
12607 /* Skip mod/rm byte. */
12613 dofloat (int sizeflag
)
12615 const struct dis386
*dp
;
12616 unsigned char floatop
;
12618 floatop
= codep
[-1];
12620 if (modrm
.mod
!= 3)
12622 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
12624 putop (float_mem
[fp_indx
], sizeflag
);
12627 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
12630 /* Skip mod/rm byte. */
12634 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
12635 if (dp
->name
== NULL
)
12637 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
12639 /* Instruction fnstsw is only one with strange arg. */
12640 if (floatop
== 0xdf && codep
[-1] == 0xe0)
12641 strcpy (op_out
[0], names16
[0]);
12645 putop (dp
->name
, sizeflag
);
12650 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
12655 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
12659 /* Like oappend (below), but S is a string starting with '%'.
12660 In Intel syntax, the '%' is elided. */
12662 oappend_maybe_intel (const char *s
)
12664 oappend (s
+ intel_syntax
);
12668 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12670 oappend_maybe_intel ("%st");
12674 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12676 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
12677 oappend_maybe_intel (scratchbuf
);
12680 /* Capital letters in template are macros. */
12682 putop (const char *in_template
, int sizeflag
)
12687 unsigned int l
= 0, len
= 1;
12690 #define SAVE_LAST(c) \
12691 if (l < len && l < sizeof (last)) \
12696 for (p
= in_template
; *p
; p
++)
12712 while (*++p
!= '|')
12713 if (*p
== '}' || *p
== '\0')
12716 /* Fall through. */
12721 while (*++p
!= '}')
12732 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12736 if (l
== 0 && len
== 1)
12741 if (sizeflag
& SUFFIX_ALWAYS
)
12754 if (address_mode
== mode_64bit
12755 && !(prefixes
& PREFIX_ADDR
))
12766 if (intel_syntax
&& !alt
)
12768 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
12770 if (sizeflag
& DFLAG
)
12771 *obufp
++ = intel_syntax
? 'd' : 'l';
12773 *obufp
++ = intel_syntax
? 'w' : 's';
12774 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12778 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12781 if (modrm
.mod
== 3)
12787 if (sizeflag
& DFLAG
)
12788 *obufp
++ = intel_syntax
? 'd' : 'l';
12791 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12797 case 'E': /* For jcxz/jecxz */
12798 if (address_mode
== mode_64bit
)
12800 if (sizeflag
& AFLAG
)
12806 if (sizeflag
& AFLAG
)
12808 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12813 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
12815 if (sizeflag
& AFLAG
)
12816 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
12818 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
12819 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12823 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
12825 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12829 if (!(rex
& REX_W
))
12830 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12835 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
12836 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
12838 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
12841 if (prefixes
& PREFIX_DS
)
12860 if (l
!= 0 || len
!= 1)
12862 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
12867 if (!need_vex
|| !vex
.evex
)
12870 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
12872 switch (vex
.length
)
12890 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
12895 /* Fall through. */
12898 if (l
!= 0 || len
!= 1)
12906 if (sizeflag
& SUFFIX_ALWAYS
)
12910 if (intel_mnemonic
!= cond
)
12914 if ((prefixes
& PREFIX_FWAIT
) == 0)
12917 used_prefixes
|= PREFIX_FWAIT
;
12923 else if (intel_syntax
&& (sizeflag
& DFLAG
))
12927 if (!(rex
& REX_W
))
12928 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12932 && address_mode
== mode_64bit
12933 && isa64
== intel64
)
12938 /* Fall through. */
12941 && address_mode
== mode_64bit
12942 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12947 /* Fall through. */
12950 if (l
== 0 && len
== 1)
12955 if ((rex
& REX_W
) == 0
12956 && (prefixes
& PREFIX_DATA
))
12958 if ((sizeflag
& DFLAG
) == 0)
12960 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12964 if ((prefixes
& PREFIX_DATA
)
12966 || (sizeflag
& SUFFIX_ALWAYS
))
12973 if (sizeflag
& DFLAG
)
12977 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12983 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
12989 if ((prefixes
& PREFIX_DATA
)
12991 || (sizeflag
& SUFFIX_ALWAYS
))
12998 if (sizeflag
& DFLAG
)
12999 *obufp
++ = intel_syntax
? 'd' : 'l';
13002 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13010 if (address_mode
== mode_64bit
13011 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13013 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13017 /* Fall through. */
13020 if (l
== 0 && len
== 1)
13023 if (intel_syntax
&& !alt
)
13026 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13032 if (sizeflag
& DFLAG
)
13033 *obufp
++ = intel_syntax
? 'd' : 'l';
13036 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13042 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13048 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
13063 else if (sizeflag
& DFLAG
)
13072 if (intel_syntax
&& !p
[1]
13073 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
13075 if (!(rex
& REX_W
))
13076 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13079 if (l
== 0 && len
== 1)
13083 if (address_mode
== mode_64bit
13084 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13086 if (sizeflag
& SUFFIX_ALWAYS
)
13108 /* Fall through. */
13111 if (l
== 0 && len
== 1)
13116 if (sizeflag
& SUFFIX_ALWAYS
)
13122 if (sizeflag
& DFLAG
)
13126 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13140 if (address_mode
== mode_64bit
13141 && !(prefixes
& PREFIX_ADDR
))
13152 if (l
!= 0 || len
!= 1)
13157 if (need_vex
&& vex
.prefix
)
13159 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
13166 if (prefixes
& PREFIX_DATA
)
13170 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13174 if (l
== 0 && len
== 1)
13178 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
13186 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
13188 switch (vex
.length
)
13204 if (l
== 0 && len
== 1)
13206 /* operand size flag for cwtl, cbtw */
13215 else if (sizeflag
& DFLAG
)
13219 if (!(rex
& REX_W
))
13220 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13227 && last
[0] != 'L'))
13234 if (last
[0] == 'X')
13235 *obufp
++ = vex
.w
? 'd': 's';
13237 *obufp
++ = vex
.w
? 'q': 'd';
13243 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13245 if (sizeflag
& DFLAG
)
13249 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13255 if (address_mode
== mode_64bit
13256 && (isa64
== intel64
13257 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
13259 else if ((prefixes
& PREFIX_DATA
))
13261 if (!(sizeflag
& DFLAG
))
13263 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13270 mnemonicendp
= obufp
;
13275 oappend (const char *s
)
13277 obufp
= stpcpy (obufp
, s
);
13283 /* Only print the active segment register. */
13284 if (!active_seg_prefix
)
13287 used_prefixes
|= active_seg_prefix
;
13288 switch (active_seg_prefix
)
13291 oappend_maybe_intel ("%cs:");
13294 oappend_maybe_intel ("%ds:");
13297 oappend_maybe_intel ("%ss:");
13300 oappend_maybe_intel ("%es:");
13303 oappend_maybe_intel ("%fs:");
13306 oappend_maybe_intel ("%gs:");
13314 OP_indirE (int bytemode
, int sizeflag
)
13318 OP_E (bytemode
, sizeflag
);
13322 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
13324 if (address_mode
== mode_64bit
)
13332 sprintf_vma (tmp
, disp
);
13333 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
13334 strcpy (buf
+ 2, tmp
+ i
);
13338 bfd_signed_vma v
= disp
;
13345 /* Check for possible overflow on 0x8000000000000000. */
13348 strcpy (buf
, "9223372036854775808");
13362 tmp
[28 - i
] = (v
% 10) + '0';
13366 strcpy (buf
, tmp
+ 29 - i
);
13372 sprintf (buf
, "0x%x", (unsigned int) disp
);
13374 sprintf (buf
, "%d", (int) disp
);
13378 /* Put DISP in BUF as signed hex number. */
13381 print_displacement (char *buf
, bfd_vma disp
)
13383 bfd_signed_vma val
= disp
;
13392 /* Check for possible overflow. */
13395 switch (address_mode
)
13398 strcpy (buf
+ j
, "0x8000000000000000");
13401 strcpy (buf
+ j
, "0x80000000");
13404 strcpy (buf
+ j
, "0x8000");
13414 sprintf_vma (tmp
, (bfd_vma
) val
);
13415 for (i
= 0; tmp
[i
] == '0'; i
++)
13417 if (tmp
[i
] == '\0')
13419 strcpy (buf
+ j
, tmp
+ i
);
13423 intel_operand_size (int bytemode
, int sizeflag
)
13427 && (bytemode
== x_mode
13428 || bytemode
== evex_half_bcst_xmmq_mode
))
13431 oappend ("QWORD PTR ");
13433 oappend ("DWORD PTR ");
13442 oappend ("BYTE PTR ");
13447 oappend ("WORD PTR ");
13450 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13452 oappend ("QWORD PTR ");
13455 /* Fall through. */
13457 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13459 oappend ("QWORD PTR ");
13462 /* Fall through. */
13468 oappend ("QWORD PTR ");
13471 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
13472 oappend ("DWORD PTR ");
13474 oappend ("WORD PTR ");
13475 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13479 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13481 oappend ("WORD PTR ");
13482 if (!(rex
& REX_W
))
13483 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13486 if (sizeflag
& DFLAG
)
13487 oappend ("QWORD PTR ");
13489 oappend ("DWORD PTR ");
13490 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13493 case d_scalar_mode
:
13494 case d_scalar_swap_mode
:
13497 oappend ("DWORD PTR ");
13500 case q_scalar_mode
:
13501 case q_scalar_swap_mode
:
13503 oappend ("QWORD PTR ");
13507 if (address_mode
== mode_64bit
)
13508 oappend ("QWORD PTR ");
13510 oappend ("DWORD PTR ");
13513 if (sizeflag
& DFLAG
)
13514 oappend ("FWORD PTR ");
13516 oappend ("DWORD PTR ");
13517 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13520 oappend ("TBYTE PTR ");
13524 case evex_x_gscat_mode
:
13525 case evex_x_nobcst_mode
:
13526 case b_scalar_mode
:
13527 case w_scalar_mode
:
13530 switch (vex
.length
)
13533 oappend ("XMMWORD PTR ");
13536 oappend ("YMMWORD PTR ");
13539 oappend ("ZMMWORD PTR ");
13546 oappend ("XMMWORD PTR ");
13549 oappend ("XMMWORD PTR ");
13552 oappend ("YMMWORD PTR ");
13555 case evex_half_bcst_xmmq_mode
:
13559 switch (vex
.length
)
13562 oappend ("QWORD PTR ");
13565 oappend ("XMMWORD PTR ");
13568 oappend ("YMMWORD PTR ");
13578 switch (vex
.length
)
13583 oappend ("BYTE PTR ");
13593 switch (vex
.length
)
13598 oappend ("WORD PTR ");
13608 switch (vex
.length
)
13613 oappend ("DWORD PTR ");
13623 switch (vex
.length
)
13628 oappend ("QWORD PTR ");
13638 switch (vex
.length
)
13641 oappend ("WORD PTR ");
13644 oappend ("DWORD PTR ");
13647 oappend ("QWORD PTR ");
13657 switch (vex
.length
)
13660 oappend ("DWORD PTR ");
13663 oappend ("QWORD PTR ");
13666 oappend ("XMMWORD PTR ");
13676 switch (vex
.length
)
13679 oappend ("QWORD PTR ");
13682 oappend ("YMMWORD PTR ");
13685 oappend ("ZMMWORD PTR ");
13695 switch (vex
.length
)
13699 oappend ("XMMWORD PTR ");
13706 oappend ("OWORD PTR ");
13709 case vex_w_dq_mode
:
13710 case vex_scalar_w_dq_mode
:
13715 oappend ("QWORD PTR ");
13717 oappend ("DWORD PTR ");
13719 case vex_vsib_d_w_dq_mode
:
13720 case vex_vsib_q_w_dq_mode
:
13727 oappend ("QWORD PTR ");
13729 oappend ("DWORD PTR ");
13733 switch (vex
.length
)
13736 oappend ("XMMWORD PTR ");
13739 oappend ("YMMWORD PTR ");
13742 oappend ("ZMMWORD PTR ");
13749 case vex_vsib_q_w_d_mode
:
13750 case vex_vsib_d_w_d_mode
:
13751 if (!need_vex
|| !vex
.evex
)
13754 switch (vex
.length
)
13757 oappend ("QWORD PTR ");
13760 oappend ("XMMWORD PTR ");
13763 oappend ("YMMWORD PTR ");
13771 if (!need_vex
|| vex
.length
!= 128)
13774 oappend ("DWORD PTR ");
13776 oappend ("BYTE PTR ");
13782 oappend ("QWORD PTR ");
13784 oappend ("WORD PTR ");
13794 OP_E_register (int bytemode
, int sizeflag
)
13796 int reg
= modrm
.rm
;
13797 const char **names
;
13803 if ((sizeflag
& SUFFIX_ALWAYS
)
13804 && (bytemode
== b_swap_mode
13805 || bytemode
== bnd_swap_mode
13806 || bytemode
== v_swap_mode
))
13832 names
= address_mode
== mode_64bit
? names64
: names32
;
13835 case bnd_swap_mode
:
13844 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13849 /* Fall through. */
13851 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13857 /* Fall through. */
13870 if ((sizeflag
& DFLAG
)
13871 || (bytemode
!= v_mode
13872 && bytemode
!= v_swap_mode
))
13876 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13880 names
= (address_mode
== mode_64bit
13881 ? names64
: names32
);
13882 if (!(prefixes
& PREFIX_ADDR
))
13883 names
= (address_mode
== mode_16bit
13884 ? names16
: names
);
13887 /* Remove "addr16/addr32". */
13888 all_prefixes
[last_addr_prefix
] = 0;
13889 names
= (address_mode
!= mode_32bit
13890 ? names32
: names16
);
13891 used_prefixes
|= PREFIX_ADDR
;
13901 names
= names_mask
;
13906 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13909 oappend (names
[reg
]);
13913 OP_E_memory (int bytemode
, int sizeflag
)
13916 int add
= (rex
& REX_B
) ? 8 : 0;
13922 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
13924 && bytemode
!= x_mode
13925 && bytemode
!= xmmq_mode
13926 && bytemode
!= evex_half_bcst_xmmq_mode
)
13942 if (address_mode
!= mode_64bit
)
13948 case vex_vsib_d_w_dq_mode
:
13949 case vex_vsib_d_w_d_mode
:
13950 case vex_vsib_q_w_dq_mode
:
13951 case vex_vsib_q_w_d_mode
:
13952 case evex_x_gscat_mode
:
13954 shift
= vex
.w
? 3 : 2;
13957 case evex_half_bcst_xmmq_mode
:
13961 shift
= vex
.w
? 3 : 2;
13964 /* Fall through. */
13968 case evex_x_nobcst_mode
:
13970 switch (vex
.length
)
13993 case q_scalar_mode
:
13995 case q_scalar_swap_mode
:
14001 case d_scalar_mode
:
14003 case d_scalar_swap_mode
:
14006 case w_scalar_mode
:
14010 case b_scalar_mode
:
14015 shift
= address_mode
== mode_64bit
? 3 : 2;
14020 /* Make necessary corrections to shift for modes that need it.
14021 For these modes we currently have shift 4, 5 or 6 depending on
14022 vex.length (it corresponds to xmmword, ymmword or zmmword
14023 operand). We might want to make it 3, 4 or 5 (e.g. for
14024 xmmq_mode). In case of broadcast enabled the corrections
14025 aren't needed, as element size is always 32 or 64 bits. */
14027 && (bytemode
== xmmq_mode
14028 || bytemode
== evex_half_bcst_xmmq_mode
))
14030 else if (bytemode
== xmmqd_mode
)
14032 else if (bytemode
== xmmdw_mode
)
14034 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
14042 intel_operand_size (bytemode
, sizeflag
);
14045 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14047 /* 32/64 bit address mode */
14057 int addr32flag
= !((sizeflag
& AFLAG
)
14058 || bytemode
== v_bnd_mode
14059 || bytemode
== v_bndmk_mode
14060 || bytemode
== bnd_mode
14061 || bytemode
== bnd_swap_mode
);
14062 const char **indexes64
= names64
;
14063 const char **indexes32
= names32
;
14073 vindex
= sib
.index
;
14079 case vex_vsib_d_w_dq_mode
:
14080 case vex_vsib_d_w_d_mode
:
14081 case vex_vsib_q_w_dq_mode
:
14082 case vex_vsib_q_w_d_mode
:
14092 switch (vex
.length
)
14095 indexes64
= indexes32
= names_xmm
;
14099 || bytemode
== vex_vsib_q_w_dq_mode
14100 || bytemode
== vex_vsib_q_w_d_mode
)
14101 indexes64
= indexes32
= names_ymm
;
14103 indexes64
= indexes32
= names_xmm
;
14107 || bytemode
== vex_vsib_q_w_dq_mode
14108 || bytemode
== vex_vsib_q_w_d_mode
)
14109 indexes64
= indexes32
= names_zmm
;
14111 indexes64
= indexes32
= names_ymm
;
14118 haveindex
= vindex
!= 4;
14125 rbase
= base
+ add
;
14133 if (address_mode
== mode_64bit
&& !havesib
)
14136 if (riprel
&& bytemode
== v_bndmk_mode
)
14144 FETCH_DATA (the_info
, codep
+ 1);
14146 if ((disp
& 0x80) != 0)
14148 if (vex
.evex
&& shift
> 0)
14161 && address_mode
!= mode_16bit
)
14163 if (address_mode
== mode_64bit
)
14165 /* Display eiz instead of addr32. */
14166 needindex
= addr32flag
;
14171 /* In 32-bit mode, we need index register to tell [offset]
14172 from [eiz*1 + offset]. */
14177 havedisp
= (havebase
14179 || (havesib
&& (haveindex
|| scale
!= 0)));
14182 if (modrm
.mod
!= 0 || base
== 5)
14184 if (havedisp
|| riprel
)
14185 print_displacement (scratchbuf
, disp
);
14187 print_operand_value (scratchbuf
, 1, disp
);
14188 oappend (scratchbuf
);
14192 oappend (!addr32flag
? "(%rip)" : "(%eip)");
14196 if ((havebase
|| haveindex
|| needaddr32
|| riprel
)
14197 && (bytemode
!= v_bnd_mode
)
14198 && (bytemode
!= v_bndmk_mode
)
14199 && (bytemode
!= bnd_mode
)
14200 && (bytemode
!= bnd_swap_mode
))
14201 used_prefixes
|= PREFIX_ADDR
;
14203 if (havedisp
|| (intel_syntax
&& riprel
))
14205 *obufp
++ = open_char
;
14206 if (intel_syntax
&& riprel
)
14209 oappend (!addr32flag
? "rip" : "eip");
14213 oappend (address_mode
== mode_64bit
&& !addr32flag
14214 ? names64
[rbase
] : names32
[rbase
]);
14217 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14218 print index to tell base + index from base. */
14222 || (havebase
&& base
!= ESP_REG_NUM
))
14224 if (!intel_syntax
|| havebase
)
14226 *obufp
++ = separator_char
;
14230 oappend (address_mode
== mode_64bit
&& !addr32flag
14231 ? indexes64
[vindex
] : indexes32
[vindex
]);
14233 oappend (address_mode
== mode_64bit
&& !addr32flag
14234 ? index64
: index32
);
14236 *obufp
++ = scale_char
;
14238 sprintf (scratchbuf
, "%d", 1 << scale
);
14239 oappend (scratchbuf
);
14243 && (disp
|| modrm
.mod
!= 0 || base
== 5))
14245 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
14250 else if (modrm
.mod
!= 1 && disp
!= -disp
)
14254 disp
= - (bfd_signed_vma
) disp
;
14258 print_displacement (scratchbuf
, disp
);
14260 print_operand_value (scratchbuf
, 1, disp
);
14261 oappend (scratchbuf
);
14264 *obufp
++ = close_char
;
14267 else if (intel_syntax
)
14269 if (modrm
.mod
!= 0 || base
== 5)
14271 if (!active_seg_prefix
)
14273 oappend (names_seg
[ds_reg
- es_reg
]);
14276 print_operand_value (scratchbuf
, 1, disp
);
14277 oappend (scratchbuf
);
14283 /* 16 bit address mode */
14284 used_prefixes
|= prefixes
& PREFIX_ADDR
;
14291 if ((disp
& 0x8000) != 0)
14296 FETCH_DATA (the_info
, codep
+ 1);
14298 if ((disp
& 0x80) != 0)
14300 if (vex
.evex
&& shift
> 0)
14305 if ((disp
& 0x8000) != 0)
14311 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
14313 print_displacement (scratchbuf
, disp
);
14314 oappend (scratchbuf
);
14317 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
14319 *obufp
++ = open_char
;
14321 oappend (index16
[modrm
.rm
]);
14323 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
14325 if ((bfd_signed_vma
) disp
>= 0)
14330 else if (modrm
.mod
!= 1)
14334 disp
= - (bfd_signed_vma
) disp
;
14337 print_displacement (scratchbuf
, disp
);
14338 oappend (scratchbuf
);
14341 *obufp
++ = close_char
;
14344 else if (intel_syntax
)
14346 if (!active_seg_prefix
)
14348 oappend (names_seg
[ds_reg
- es_reg
]);
14351 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
14352 oappend (scratchbuf
);
14355 if (vex
.evex
&& vex
.b
14356 && (bytemode
== x_mode
14357 || bytemode
== xmmq_mode
14358 || bytemode
== evex_half_bcst_xmmq_mode
))
14361 || bytemode
== xmmq_mode
14362 || bytemode
== evex_half_bcst_xmmq_mode
)
14364 switch (vex
.length
)
14367 oappend ("{1to2}");
14370 oappend ("{1to4}");
14373 oappend ("{1to8}");
14381 switch (vex
.length
)
14384 oappend ("{1to4}");
14387 oappend ("{1to8}");
14390 oappend ("{1to16}");
14400 OP_E (int bytemode
, int sizeflag
)
14402 /* Skip mod/rm byte. */
14406 if (modrm
.mod
== 3)
14407 OP_E_register (bytemode
, sizeflag
);
14409 OP_E_memory (bytemode
, sizeflag
);
14413 OP_G (int bytemode
, int sizeflag
)
14416 const char **names
;
14425 oappend (names8rex
[modrm
.reg
+ add
]);
14427 oappend (names8
[modrm
.reg
+ add
]);
14430 oappend (names16
[modrm
.reg
+ add
]);
14435 oappend (names32
[modrm
.reg
+ add
]);
14438 oappend (names64
[modrm
.reg
+ add
]);
14441 if (modrm
.reg
> 0x3)
14446 oappend (names_bnd
[modrm
.reg
]);
14455 oappend (names64
[modrm
.reg
+ add
]);
14458 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
14459 oappend (names32
[modrm
.reg
+ add
]);
14461 oappend (names16
[modrm
.reg
+ add
]);
14462 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14466 names
= (address_mode
== mode_64bit
14467 ? names64
: names32
);
14468 if (!(prefixes
& PREFIX_ADDR
))
14470 if (address_mode
== mode_16bit
)
14475 /* Remove "addr16/addr32". */
14476 all_prefixes
[last_addr_prefix
] = 0;
14477 names
= (address_mode
!= mode_32bit
14478 ? names32
: names16
);
14479 used_prefixes
|= PREFIX_ADDR
;
14481 oappend (names
[modrm
.reg
+ add
]);
14484 if (address_mode
== mode_64bit
)
14485 oappend (names64
[modrm
.reg
+ add
]);
14487 oappend (names32
[modrm
.reg
+ add
]);
14491 if ((modrm
.reg
+ add
) > 0x7)
14496 oappend (names_mask
[modrm
.reg
+ add
]);
14499 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14512 FETCH_DATA (the_info
, codep
+ 8);
14513 a
= *codep
++ & 0xff;
14514 a
|= (*codep
++ & 0xff) << 8;
14515 a
|= (*codep
++ & 0xff) << 16;
14516 a
|= (*codep
++ & 0xffu
) << 24;
14517 b
= *codep
++ & 0xff;
14518 b
|= (*codep
++ & 0xff) << 8;
14519 b
|= (*codep
++ & 0xff) << 16;
14520 b
|= (*codep
++ & 0xffu
) << 24;
14521 x
= a
+ ((bfd_vma
) b
<< 32);
14529 static bfd_signed_vma
14532 bfd_signed_vma x
= 0;
14534 FETCH_DATA (the_info
, codep
+ 4);
14535 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14536 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14537 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14538 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14542 static bfd_signed_vma
14545 bfd_signed_vma x
= 0;
14547 FETCH_DATA (the_info
, codep
+ 4);
14548 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14549 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14550 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14551 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14553 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
14563 FETCH_DATA (the_info
, codep
+ 2);
14564 x
= *codep
++ & 0xff;
14565 x
|= (*codep
++ & 0xff) << 8;
14570 set_op (bfd_vma op
, int riprel
)
14572 op_index
[op_ad
] = op_ad
;
14573 if (address_mode
== mode_64bit
)
14575 op_address
[op_ad
] = op
;
14576 op_riprel
[op_ad
] = riprel
;
14580 /* Mask to get a 32-bit address. */
14581 op_address
[op_ad
] = op
& 0xffffffff;
14582 op_riprel
[op_ad
] = riprel
& 0xffffffff;
14587 OP_REG (int code
, int sizeflag
)
14594 case es_reg
: case ss_reg
: case cs_reg
:
14595 case ds_reg
: case fs_reg
: case gs_reg
:
14596 oappend (names_seg
[code
- es_reg
]);
14608 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14609 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14610 s
= names16
[code
- ax_reg
+ add
];
14612 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14613 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14616 s
= names8rex
[code
- al_reg
+ add
];
14618 s
= names8
[code
- al_reg
];
14620 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
14621 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
14622 if (address_mode
== mode_64bit
14623 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14625 s
= names64
[code
- rAX_reg
+ add
];
14628 code
+= eAX_reg
- rAX_reg
;
14629 /* Fall through. */
14630 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14631 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14634 s
= names64
[code
- eAX_reg
+ add
];
14637 if (sizeflag
& DFLAG
)
14638 s
= names32
[code
- eAX_reg
+ add
];
14640 s
= names16
[code
- eAX_reg
+ add
];
14641 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14645 s
= INTERNAL_DISASSEMBLER_ERROR
;
14652 OP_IMREG (int code
, int sizeflag
)
14664 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14665 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14666 s
= names16
[code
- ax_reg
];
14668 case es_reg
: case ss_reg
: case cs_reg
:
14669 case ds_reg
: case fs_reg
: case gs_reg
:
14670 s
= names_seg
[code
- es_reg
];
14672 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14673 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14676 s
= names8rex
[code
- al_reg
];
14678 s
= names8
[code
- al_reg
];
14680 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14681 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14684 s
= names64
[code
- eAX_reg
];
14687 if (sizeflag
& DFLAG
)
14688 s
= names32
[code
- eAX_reg
];
14690 s
= names16
[code
- eAX_reg
];
14691 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14694 case z_mode_ax_reg
:
14695 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14699 if (!(rex
& REX_W
))
14700 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14703 s
= INTERNAL_DISASSEMBLER_ERROR
;
14710 OP_I (int bytemode
, int sizeflag
)
14713 bfd_signed_vma mask
= -1;
14718 FETCH_DATA (the_info
, codep
+ 1);
14723 if (address_mode
== mode_64bit
)
14728 /* Fall through. */
14735 if (sizeflag
& DFLAG
)
14745 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14757 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14762 scratchbuf
[0] = '$';
14763 print_operand_value (scratchbuf
+ 1, 1, op
);
14764 oappend_maybe_intel (scratchbuf
);
14765 scratchbuf
[0] = '\0';
14769 OP_I64 (int bytemode
, int sizeflag
)
14772 bfd_signed_vma mask
= -1;
14774 if (address_mode
!= mode_64bit
)
14776 OP_I (bytemode
, sizeflag
);
14783 FETCH_DATA (the_info
, codep
+ 1);
14793 if (sizeflag
& DFLAG
)
14803 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14811 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14816 scratchbuf
[0] = '$';
14817 print_operand_value (scratchbuf
+ 1, 1, op
);
14818 oappend_maybe_intel (scratchbuf
);
14819 scratchbuf
[0] = '\0';
14823 OP_sI (int bytemode
, int sizeflag
)
14831 FETCH_DATA (the_info
, codep
+ 1);
14833 if ((op
& 0x80) != 0)
14835 if (bytemode
== b_T_mode
)
14837 if (address_mode
!= mode_64bit
14838 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14840 /* The operand-size prefix is overridden by a REX prefix. */
14841 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14849 if (!(rex
& REX_W
))
14851 if (sizeflag
& DFLAG
)
14859 /* The operand-size prefix is overridden by a REX prefix. */
14860 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14866 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14870 scratchbuf
[0] = '$';
14871 print_operand_value (scratchbuf
+ 1, 1, op
);
14872 oappend_maybe_intel (scratchbuf
);
14876 OP_J (int bytemode
, int sizeflag
)
14880 bfd_vma segment
= 0;
14885 FETCH_DATA (the_info
, codep
+ 1);
14887 if ((disp
& 0x80) != 0)
14891 if (isa64
== amd64
)
14893 if ((sizeflag
& DFLAG
)
14894 || (address_mode
== mode_64bit
14895 && (isa64
!= amd64
|| (rex
& REX_W
))))
14900 if ((disp
& 0x8000) != 0)
14902 /* In 16bit mode, address is wrapped around at 64k within
14903 the same segment. Otherwise, a data16 prefix on a jump
14904 instruction means that the pc is masked to 16 bits after
14905 the displacement is added! */
14907 if ((prefixes
& PREFIX_DATA
) == 0)
14908 segment
= ((start_pc
+ (codep
- start_codep
))
14909 & ~((bfd_vma
) 0xffff));
14911 if (address_mode
!= mode_64bit
14912 || (isa64
== amd64
&& !(rex
& REX_W
)))
14913 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14916 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14919 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
14921 print_operand_value (scratchbuf
, 1, disp
);
14922 oappend (scratchbuf
);
14926 OP_SEG (int bytemode
, int sizeflag
)
14928 if (bytemode
== w_mode
)
14929 oappend (names_seg
[modrm
.reg
]);
14931 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
14935 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
14939 if (sizeflag
& DFLAG
)
14949 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14951 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
14953 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
14954 oappend (scratchbuf
);
14958 OP_OFF (int bytemode
, int sizeflag
)
14962 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14963 intel_operand_size (bytemode
, sizeflag
);
14966 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14973 if (!active_seg_prefix
)
14975 oappend (names_seg
[ds_reg
- es_reg
]);
14979 print_operand_value (scratchbuf
, 1, off
);
14980 oappend (scratchbuf
);
14984 OP_OFF64 (int bytemode
, int sizeflag
)
14988 if (address_mode
!= mode_64bit
14989 || (prefixes
& PREFIX_ADDR
))
14991 OP_OFF (bytemode
, sizeflag
);
14995 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14996 intel_operand_size (bytemode
, sizeflag
);
15003 if (!active_seg_prefix
)
15005 oappend (names_seg
[ds_reg
- es_reg
]);
15009 print_operand_value (scratchbuf
, 1, off
);
15010 oappend (scratchbuf
);
15014 ptr_reg (int code
, int sizeflag
)
15018 *obufp
++ = open_char
;
15019 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
15020 if (address_mode
== mode_64bit
)
15022 if (!(sizeflag
& AFLAG
))
15023 s
= names32
[code
- eAX_reg
];
15025 s
= names64
[code
- eAX_reg
];
15027 else if (sizeflag
& AFLAG
)
15028 s
= names32
[code
- eAX_reg
];
15030 s
= names16
[code
- eAX_reg
];
15032 *obufp
++ = close_char
;
15037 OP_ESreg (int code
, int sizeflag
)
15043 case 0x6d: /* insw/insl */
15044 intel_operand_size (z_mode
, sizeflag
);
15046 case 0xa5: /* movsw/movsl/movsq */
15047 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15048 case 0xab: /* stosw/stosl */
15049 case 0xaf: /* scasw/scasl */
15050 intel_operand_size (v_mode
, sizeflag
);
15053 intel_operand_size (b_mode
, sizeflag
);
15056 oappend_maybe_intel ("%es:");
15057 ptr_reg (code
, sizeflag
);
15061 OP_DSreg (int code
, int sizeflag
)
15067 case 0x6f: /* outsw/outsl */
15068 intel_operand_size (z_mode
, sizeflag
);
15070 case 0xa5: /* movsw/movsl/movsq */
15071 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15072 case 0xad: /* lodsw/lodsl/lodsq */
15073 intel_operand_size (v_mode
, sizeflag
);
15076 intel_operand_size (b_mode
, sizeflag
);
15079 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15080 default segment register DS is printed. */
15081 if (!active_seg_prefix
)
15082 active_seg_prefix
= PREFIX_DS
;
15084 ptr_reg (code
, sizeflag
);
15088 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15096 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
15098 all_prefixes
[last_lock_prefix
] = 0;
15099 used_prefixes
|= PREFIX_LOCK
;
15104 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
15105 oappend_maybe_intel (scratchbuf
);
15109 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15118 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
15120 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
15121 oappend (scratchbuf
);
15125 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15127 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
15128 oappend_maybe_intel (scratchbuf
);
15132 OP_R (int bytemode
, int sizeflag
)
15134 /* Skip mod/rm byte. */
15137 OP_E_register (bytemode
, sizeflag
);
15141 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15143 int reg
= modrm
.reg
;
15144 const char **names
;
15146 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15147 if (prefixes
& PREFIX_DATA
)
15156 oappend (names
[reg
]);
15160 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15162 int reg
= modrm
.reg
;
15163 const char **names
;
15175 && bytemode
!= xmm_mode
15176 && bytemode
!= xmmq_mode
15177 && bytemode
!= evex_half_bcst_xmmq_mode
15178 && bytemode
!= ymm_mode
15179 && bytemode
!= scalar_mode
)
15181 switch (vex
.length
)
15188 || (bytemode
!= vex_vsib_q_w_dq_mode
15189 && bytemode
!= vex_vsib_q_w_d_mode
))
15201 else if (bytemode
== xmmq_mode
15202 || bytemode
== evex_half_bcst_xmmq_mode
)
15204 switch (vex
.length
)
15217 else if (bytemode
== ymm_mode
)
15221 oappend (names
[reg
]);
15225 OP_EM (int bytemode
, int sizeflag
)
15228 const char **names
;
15230 if (modrm
.mod
!= 3)
15233 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
15235 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15236 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15238 OP_E (bytemode
, sizeflag
);
15242 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
15245 /* Skip mod/rm byte. */
15248 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15250 if (prefixes
& PREFIX_DATA
)
15259 oappend (names
[reg
]);
15262 /* cvt* are the only instructions in sse2 which have
15263 both SSE and MMX operands and also have 0x66 prefix
15264 in their opcode. 0x66 was originally used to differentiate
15265 between SSE and MMX instruction(operands). So we have to handle the
15266 cvt* separately using OP_EMC and OP_MXC */
15268 OP_EMC (int bytemode
, int sizeflag
)
15270 if (modrm
.mod
!= 3)
15272 if (intel_syntax
&& bytemode
== v_mode
)
15274 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15275 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15277 OP_E (bytemode
, sizeflag
);
15281 /* Skip mod/rm byte. */
15284 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15285 oappend (names_mm
[modrm
.rm
]);
15289 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15291 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15292 oappend (names_mm
[modrm
.reg
]);
15296 OP_EX (int bytemode
, int sizeflag
)
15299 const char **names
;
15301 /* Skip mod/rm byte. */
15305 if (modrm
.mod
!= 3)
15307 OP_E_memory (bytemode
, sizeflag
);
15322 if ((sizeflag
& SUFFIX_ALWAYS
)
15323 && (bytemode
== x_swap_mode
15324 || bytemode
== d_swap_mode
15325 || bytemode
== d_scalar_swap_mode
15326 || bytemode
== q_swap_mode
15327 || bytemode
== q_scalar_swap_mode
))
15331 && bytemode
!= xmm_mode
15332 && bytemode
!= xmmdw_mode
15333 && bytemode
!= xmmqd_mode
15334 && bytemode
!= xmm_mb_mode
15335 && bytemode
!= xmm_mw_mode
15336 && bytemode
!= xmm_md_mode
15337 && bytemode
!= xmm_mq_mode
15338 && bytemode
!= xmm_mdq_mode
15339 && bytemode
!= xmmq_mode
15340 && bytemode
!= evex_half_bcst_xmmq_mode
15341 && bytemode
!= ymm_mode
15342 && bytemode
!= d_scalar_mode
15343 && bytemode
!= d_scalar_swap_mode
15344 && bytemode
!= q_scalar_mode
15345 && bytemode
!= q_scalar_swap_mode
15346 && bytemode
!= vex_scalar_w_dq_mode
)
15348 switch (vex
.length
)
15363 else if (bytemode
== xmmq_mode
15364 || bytemode
== evex_half_bcst_xmmq_mode
)
15366 switch (vex
.length
)
15379 else if (bytemode
== ymm_mode
)
15383 oappend (names
[reg
]);
15387 OP_MS (int bytemode
, int sizeflag
)
15389 if (modrm
.mod
== 3)
15390 OP_EM (bytemode
, sizeflag
);
15396 OP_XS (int bytemode
, int sizeflag
)
15398 if (modrm
.mod
== 3)
15399 OP_EX (bytemode
, sizeflag
);
15405 OP_M (int bytemode
, int sizeflag
)
15407 if (modrm
.mod
== 3)
15408 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15411 OP_E (bytemode
, sizeflag
);
15415 OP_0f07 (int bytemode
, int sizeflag
)
15417 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
15420 OP_E (bytemode
, sizeflag
);
15423 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15424 32bit mode and "xchg %rax,%rax" in 64bit mode. */
15427 NOP_Fixup1 (int bytemode
, int sizeflag
)
15429 if ((prefixes
& PREFIX_DATA
) != 0
15432 && address_mode
== mode_64bit
))
15433 OP_REG (bytemode
, sizeflag
);
15435 strcpy (obuf
, "nop");
15439 NOP_Fixup2 (int bytemode
, int sizeflag
)
15441 if ((prefixes
& PREFIX_DATA
) != 0
15444 && address_mode
== mode_64bit
))
15445 OP_IMREG (bytemode
, sizeflag
);
15448 static const char *const Suffix3DNow
[] = {
15449 /* 00 */ NULL
, NULL
, NULL
, NULL
,
15450 /* 04 */ NULL
, NULL
, NULL
, NULL
,
15451 /* 08 */ NULL
, NULL
, NULL
, NULL
,
15452 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
15453 /* 10 */ NULL
, NULL
, NULL
, NULL
,
15454 /* 14 */ NULL
, NULL
, NULL
, NULL
,
15455 /* 18 */ NULL
, NULL
, NULL
, NULL
,
15456 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
15457 /* 20 */ NULL
, NULL
, NULL
, NULL
,
15458 /* 24 */ NULL
, NULL
, NULL
, NULL
,
15459 /* 28 */ NULL
, NULL
, NULL
, NULL
,
15460 /* 2C */ NULL
, NULL
, NULL
, NULL
,
15461 /* 30 */ NULL
, NULL
, NULL
, NULL
,
15462 /* 34 */ NULL
, NULL
, NULL
, NULL
,
15463 /* 38 */ NULL
, NULL
, NULL
, NULL
,
15464 /* 3C */ NULL
, NULL
, NULL
, NULL
,
15465 /* 40 */ NULL
, NULL
, NULL
, NULL
,
15466 /* 44 */ NULL
, NULL
, NULL
, NULL
,
15467 /* 48 */ NULL
, NULL
, NULL
, NULL
,
15468 /* 4C */ NULL
, NULL
, NULL
, NULL
,
15469 /* 50 */ NULL
, NULL
, NULL
, NULL
,
15470 /* 54 */ NULL
, NULL
, NULL
, NULL
,
15471 /* 58 */ NULL
, NULL
, NULL
, NULL
,
15472 /* 5C */ NULL
, NULL
, NULL
, NULL
,
15473 /* 60 */ NULL
, NULL
, NULL
, NULL
,
15474 /* 64 */ NULL
, NULL
, NULL
, NULL
,
15475 /* 68 */ NULL
, NULL
, NULL
, NULL
,
15476 /* 6C */ NULL
, NULL
, NULL
, NULL
,
15477 /* 70 */ NULL
, NULL
, NULL
, NULL
,
15478 /* 74 */ NULL
, NULL
, NULL
, NULL
,
15479 /* 78 */ NULL
, NULL
, NULL
, NULL
,
15480 /* 7C */ NULL
, NULL
, NULL
, NULL
,
15481 /* 80 */ NULL
, NULL
, NULL
, NULL
,
15482 /* 84 */ NULL
, NULL
, NULL
, NULL
,
15483 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
15484 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
15485 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
15486 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
15487 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
15488 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
15489 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
15490 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
15491 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
15492 /* AC */ NULL
, NULL
, "pfacc", NULL
,
15493 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
15494 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
15495 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
15496 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
15497 /* C0 */ NULL
, NULL
, NULL
, NULL
,
15498 /* C4 */ NULL
, NULL
, NULL
, NULL
,
15499 /* C8 */ NULL
, NULL
, NULL
, NULL
,
15500 /* CC */ NULL
, NULL
, NULL
, NULL
,
15501 /* D0 */ NULL
, NULL
, NULL
, NULL
,
15502 /* D4 */ NULL
, NULL
, NULL
, NULL
,
15503 /* D8 */ NULL
, NULL
, NULL
, NULL
,
15504 /* DC */ NULL
, NULL
, NULL
, NULL
,
15505 /* E0 */ NULL
, NULL
, NULL
, NULL
,
15506 /* E4 */ NULL
, NULL
, NULL
, NULL
,
15507 /* E8 */ NULL
, NULL
, NULL
, NULL
,
15508 /* EC */ NULL
, NULL
, NULL
, NULL
,
15509 /* F0 */ NULL
, NULL
, NULL
, NULL
,
15510 /* F4 */ NULL
, NULL
, NULL
, NULL
,
15511 /* F8 */ NULL
, NULL
, NULL
, NULL
,
15512 /* FC */ NULL
, NULL
, NULL
, NULL
,
15516 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15518 const char *mnemonic
;
15520 FETCH_DATA (the_info
, codep
+ 1);
15521 /* AMD 3DNow! instructions are specified by an opcode suffix in the
15522 place where an 8-bit immediate would normally go. ie. the last
15523 byte of the instruction. */
15524 obufp
= mnemonicendp
;
15525 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
15527 oappend (mnemonic
);
15530 /* Since a variable sized modrm/sib chunk is between the start
15531 of the opcode (0x0f0f) and the opcode suffix, we need to do
15532 all the modrm processing first, and don't know until now that
15533 we have a bad opcode. This necessitates some cleaning up. */
15534 op_out
[0][0] = '\0';
15535 op_out
[1][0] = '\0';
15538 mnemonicendp
= obufp
;
15541 static struct op simd_cmp_op
[] =
15543 { STRING_COMMA_LEN ("eq") },
15544 { STRING_COMMA_LEN ("lt") },
15545 { STRING_COMMA_LEN ("le") },
15546 { STRING_COMMA_LEN ("unord") },
15547 { STRING_COMMA_LEN ("neq") },
15548 { STRING_COMMA_LEN ("nlt") },
15549 { STRING_COMMA_LEN ("nle") },
15550 { STRING_COMMA_LEN ("ord") }
15554 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15556 unsigned int cmp_type
;
15558 FETCH_DATA (the_info
, codep
+ 1);
15559 cmp_type
= *codep
++ & 0xff;
15560 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
15563 char *p
= mnemonicendp
- 2;
15567 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
15568 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
15572 /* We have a reserved extension byte. Output it directly. */
15573 scratchbuf
[0] = '$';
15574 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
15575 oappend_maybe_intel (scratchbuf
);
15576 scratchbuf
[0] = '\0';
15581 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED
,
15582 int sizeflag ATTRIBUTE_UNUSED
)
15584 /* mwaitx %eax,%ecx,%ebx */
15587 const char **names
= (address_mode
== mode_64bit
15588 ? names64
: names32
);
15589 strcpy (op_out
[0], names
[0]);
15590 strcpy (op_out
[1], names
[1]);
15591 strcpy (op_out
[2], names
[3]);
15592 two_source_ops
= 1;
15594 /* Skip mod/rm byte. */
15600 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
15601 int sizeflag ATTRIBUTE_UNUSED
)
15603 /* mwait %eax,%ecx */
15606 const char **names
= (address_mode
== mode_64bit
15607 ? names64
: names32
);
15608 strcpy (op_out
[0], names
[0]);
15609 strcpy (op_out
[1], names
[1]);
15610 two_source_ops
= 1;
15612 /* Skip mod/rm byte. */
15618 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
15619 int sizeflag ATTRIBUTE_UNUSED
)
15621 /* monitor %eax,%ecx,%edx" */
15624 const char **op1_names
;
15625 const char **names
= (address_mode
== mode_64bit
15626 ? names64
: names32
);
15628 if (!(prefixes
& PREFIX_ADDR
))
15629 op1_names
= (address_mode
== mode_16bit
15630 ? names16
: names
);
15633 /* Remove "addr16/addr32". */
15634 all_prefixes
[last_addr_prefix
] = 0;
15635 op1_names
= (address_mode
!= mode_32bit
15636 ? names32
: names16
);
15637 used_prefixes
|= PREFIX_ADDR
;
15639 strcpy (op_out
[0], op1_names
[0]);
15640 strcpy (op_out
[1], names
[1]);
15641 strcpy (op_out
[2], names
[2]);
15642 two_source_ops
= 1;
15644 /* Skip mod/rm byte. */
15652 /* Throw away prefixes and 1st. opcode byte. */
15653 codep
= insn_codep
+ 1;
15658 REP_Fixup (int bytemode
, int sizeflag
)
15660 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15662 if (prefixes
& PREFIX_REPZ
)
15663 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
15670 OP_IMREG (bytemode
, sizeflag
);
15673 OP_ESreg (bytemode
, sizeflag
);
15676 OP_DSreg (bytemode
, sizeflag
);
15684 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15688 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15690 if (prefixes
& PREFIX_REPNZ
)
15691 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
15694 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15698 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
15699 int sizeflag ATTRIBUTE_UNUSED
)
15701 if (active_seg_prefix
== PREFIX_DS
15702 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
15704 /* NOTRACK prefix is only valid on indirect branch instructions.
15705 NB: DATA prefix is unsupported for Intel64. */
15706 active_seg_prefix
= 0;
15707 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
15711 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15712 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15716 HLE_Fixup1 (int bytemode
, int sizeflag
)
15719 && (prefixes
& PREFIX_LOCK
) != 0)
15721 if (prefixes
& PREFIX_REPZ
)
15722 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15723 if (prefixes
& PREFIX_REPNZ
)
15724 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15727 OP_E (bytemode
, sizeflag
);
15730 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15731 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
15735 HLE_Fixup2 (int bytemode
, int sizeflag
)
15737 if (modrm
.mod
!= 3)
15739 if (prefixes
& PREFIX_REPZ
)
15740 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15741 if (prefixes
& PREFIX_REPNZ
)
15742 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15745 OP_E (bytemode
, sizeflag
);
15748 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
15749 "xrelease" for memory operand. No check for LOCK prefix. */
15752 HLE_Fixup3 (int bytemode
, int sizeflag
)
15755 && last_repz_prefix
> last_repnz_prefix
15756 && (prefixes
& PREFIX_REPZ
) != 0)
15757 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15759 OP_E (bytemode
, sizeflag
);
15763 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
15768 /* Change cmpxchg8b to cmpxchg16b. */
15769 char *p
= mnemonicendp
- 2;
15770 mnemonicendp
= stpcpy (p
, "16b");
15773 else if ((prefixes
& PREFIX_LOCK
) != 0)
15775 if (prefixes
& PREFIX_REPZ
)
15776 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15777 if (prefixes
& PREFIX_REPNZ
)
15778 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15781 OP_M (bytemode
, sizeflag
);
15785 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
15787 const char **names
;
15791 switch (vex
.length
)
15805 oappend (names
[reg
]);
15809 CRC32_Fixup (int bytemode
, int sizeflag
)
15811 /* Add proper suffix to "crc32". */
15812 char *p
= mnemonicendp
;
15831 if (sizeflag
& DFLAG
)
15835 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15839 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15846 if (modrm
.mod
== 3)
15850 /* Skip mod/rm byte. */
15855 add
= (rex
& REX_B
) ? 8 : 0;
15856 if (bytemode
== b_mode
)
15860 oappend (names8rex
[modrm
.rm
+ add
]);
15862 oappend (names8
[modrm
.rm
+ add
]);
15868 oappend (names64
[modrm
.rm
+ add
]);
15869 else if ((prefixes
& PREFIX_DATA
))
15870 oappend (names16
[modrm
.rm
+ add
]);
15872 oappend (names32
[modrm
.rm
+ add
]);
15876 OP_E (bytemode
, sizeflag
);
15880 FXSAVE_Fixup (int bytemode
, int sizeflag
)
15882 /* Add proper suffix to "fxsave" and "fxrstor". */
15886 char *p
= mnemonicendp
;
15892 OP_M (bytemode
, sizeflag
);
15896 PCMPESTR_Fixup (int bytemode
, int sizeflag
)
15898 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
15901 char *p
= mnemonicendp
;
15906 else if (sizeflag
& SUFFIX_ALWAYS
)
15913 OP_EX (bytemode
, sizeflag
);
15916 /* Display the destination register operand for instructions with
15920 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15923 const char **names
;
15931 reg
= vex
.register_specifier
;
15932 vex
.register_specifier
= 0;
15933 if (address_mode
!= mode_64bit
)
15935 else if (vex
.evex
&& !vex
.v
)
15938 if (bytemode
== vex_scalar_mode
)
15940 oappend (names_xmm
[reg
]);
15944 switch (vex
.length
)
15951 case vex_vsib_q_w_dq_mode
:
15952 case vex_vsib_q_w_d_mode
:
15968 names
= names_mask
;
15982 case vex_vsib_q_w_dq_mode
:
15983 case vex_vsib_q_w_d_mode
:
15984 names
= vex
.w
? names_ymm
: names_xmm
;
15993 names
= names_mask
;
15996 /* See PR binutils/20893 for a reproducer. */
16008 oappend (names
[reg
]);
16011 /* Get the VEX immediate byte without moving codep. */
16013 static unsigned char
16014 get_vex_imm8 (int sizeflag
, int opnum
)
16016 int bytes_before_imm
= 0;
16018 if (modrm
.mod
!= 3)
16020 /* There are SIB/displacement bytes. */
16021 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
16023 /* 32/64 bit address mode */
16024 int base
= modrm
.rm
;
16026 /* Check SIB byte. */
16029 FETCH_DATA (the_info
, codep
+ 1);
16031 /* When decoding the third source, don't increase
16032 bytes_before_imm as this has already been incremented
16033 by one in OP_E_memory while decoding the second
16036 bytes_before_imm
++;
16039 /* Don't increase bytes_before_imm when decoding the third source,
16040 it has already been incremented by OP_E_memory while decoding
16041 the second source operand. */
16047 /* When modrm.rm == 5 or modrm.rm == 4 and base in
16048 SIB == 5, there is a 4 byte displacement. */
16050 /* No displacement. */
16052 /* Fall through. */
16054 /* 4 byte displacement. */
16055 bytes_before_imm
+= 4;
16058 /* 1 byte displacement. */
16059 bytes_before_imm
++;
16066 /* 16 bit address mode */
16067 /* Don't increase bytes_before_imm when decoding the third source,
16068 it has already been incremented by OP_E_memory while decoding
16069 the second source operand. */
16075 /* When modrm.rm == 6, there is a 2 byte displacement. */
16077 /* No displacement. */
16079 /* Fall through. */
16081 /* 2 byte displacement. */
16082 bytes_before_imm
+= 2;
16085 /* 1 byte displacement: when decoding the third source,
16086 don't increase bytes_before_imm as this has already
16087 been incremented by one in OP_E_memory while decoding
16088 the second source operand. */
16090 bytes_before_imm
++;
16098 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
16099 return codep
[bytes_before_imm
];
16103 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
16105 const char **names
;
16107 if (reg
== -1 && modrm
.mod
!= 3)
16109 OP_E_memory (bytemode
, sizeflag
);
16121 if (address_mode
!= mode_64bit
)
16125 switch (vex
.length
)
16136 oappend (names
[reg
]);
16140 OP_EX_VexImmW (int bytemode
, int sizeflag
)
16143 static unsigned char vex_imm8
;
16145 if (vex_w_done
== 0)
16149 /* Skip mod/rm byte. */
16153 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
16156 reg
= vex_imm8
>> 4;
16158 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16160 else if (vex_w_done
== 1)
16165 reg
= vex_imm8
>> 4;
16167 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16171 /* Output the imm8 directly. */
16172 scratchbuf
[0] = '$';
16173 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
16174 oappend_maybe_intel (scratchbuf
);
16175 scratchbuf
[0] = '\0';
16181 OP_Vex_2src (int bytemode
, int sizeflag
)
16183 if (modrm
.mod
== 3)
16185 int reg
= modrm
.rm
;
16189 oappend (names_xmm
[reg
]);
16194 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16196 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16197 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16199 OP_E (bytemode
, sizeflag
);
16204 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
16206 if (modrm
.mod
== 3)
16208 /* Skip mod/rm byte. */
16215 unsigned int reg
= vex
.register_specifier
;
16216 vex
.register_specifier
= 0;
16218 if (address_mode
!= mode_64bit
)
16220 oappend (names_xmm
[reg
]);
16223 OP_Vex_2src (bytemode
, sizeflag
);
16227 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
16230 OP_Vex_2src (bytemode
, sizeflag
);
16233 unsigned int reg
= vex
.register_specifier
;
16234 vex
.register_specifier
= 0;
16236 if (address_mode
!= mode_64bit
)
16238 oappend (names_xmm
[reg
]);
16243 OP_EX_VexW (int bytemode
, int sizeflag
)
16249 /* Skip mod/rm byte. */
16254 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
16259 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
16262 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16270 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16273 const char **names
;
16275 FETCH_DATA (the_info
, codep
+ 1);
16278 if (bytemode
!= x_mode
)
16282 if (address_mode
!= mode_64bit
)
16285 switch (vex
.length
)
16296 oappend (names
[reg
]);
16300 OP_XMM_VexW (int bytemode
, int sizeflag
)
16302 /* Turn off the REX.W bit since it is used for swapping operands
16305 OP_XMM (bytemode
, sizeflag
);
16309 OP_EX_Vex (int bytemode
, int sizeflag
)
16311 if (modrm
.mod
!= 3)
16313 OP_EX (bytemode
, sizeflag
);
16317 OP_XMM_Vex (int bytemode
, int sizeflag
)
16319 if (modrm
.mod
!= 3)
16321 OP_XMM (bytemode
, sizeflag
);
16324 static struct op vex_cmp_op
[] =
16326 { STRING_COMMA_LEN ("eq") },
16327 { STRING_COMMA_LEN ("lt") },
16328 { STRING_COMMA_LEN ("le") },
16329 { STRING_COMMA_LEN ("unord") },
16330 { STRING_COMMA_LEN ("neq") },
16331 { STRING_COMMA_LEN ("nlt") },
16332 { STRING_COMMA_LEN ("nle") },
16333 { STRING_COMMA_LEN ("ord") },
16334 { STRING_COMMA_LEN ("eq_uq") },
16335 { STRING_COMMA_LEN ("nge") },
16336 { STRING_COMMA_LEN ("ngt") },
16337 { STRING_COMMA_LEN ("false") },
16338 { STRING_COMMA_LEN ("neq_oq") },
16339 { STRING_COMMA_LEN ("ge") },
16340 { STRING_COMMA_LEN ("gt") },
16341 { STRING_COMMA_LEN ("true") },
16342 { STRING_COMMA_LEN ("eq_os") },
16343 { STRING_COMMA_LEN ("lt_oq") },
16344 { STRING_COMMA_LEN ("le_oq") },
16345 { STRING_COMMA_LEN ("unord_s") },
16346 { STRING_COMMA_LEN ("neq_us") },
16347 { STRING_COMMA_LEN ("nlt_uq") },
16348 { STRING_COMMA_LEN ("nle_uq") },
16349 { STRING_COMMA_LEN ("ord_s") },
16350 { STRING_COMMA_LEN ("eq_us") },
16351 { STRING_COMMA_LEN ("nge_uq") },
16352 { STRING_COMMA_LEN ("ngt_uq") },
16353 { STRING_COMMA_LEN ("false_os") },
16354 { STRING_COMMA_LEN ("neq_os") },
16355 { STRING_COMMA_LEN ("ge_oq") },
16356 { STRING_COMMA_LEN ("gt_oq") },
16357 { STRING_COMMA_LEN ("true_us") },
16361 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16363 unsigned int cmp_type
;
16365 FETCH_DATA (the_info
, codep
+ 1);
16366 cmp_type
= *codep
++ & 0xff;
16367 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
16370 char *p
= mnemonicendp
- 2;
16374 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
16375 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
16379 /* We have a reserved extension byte. Output it directly. */
16380 scratchbuf
[0] = '$';
16381 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16382 oappend_maybe_intel (scratchbuf
);
16383 scratchbuf
[0] = '\0';
16388 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16389 int sizeflag ATTRIBUTE_UNUSED
)
16391 unsigned int cmp_type
;
16396 FETCH_DATA (the_info
, codep
+ 1);
16397 cmp_type
= *codep
++ & 0xff;
16398 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16399 If it's the case, print suffix, otherwise - print the immediate. */
16400 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
16405 char *p
= mnemonicendp
- 2;
16407 /* vpcmp* can have both one- and two-lettered suffix. */
16421 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16422 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16426 /* We have a reserved extension byte. Output it directly. */
16427 scratchbuf
[0] = '$';
16428 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16429 oappend_maybe_intel (scratchbuf
);
16430 scratchbuf
[0] = '\0';
16434 static const struct op xop_cmp_op
[] =
16436 { STRING_COMMA_LEN ("lt") },
16437 { STRING_COMMA_LEN ("le") },
16438 { STRING_COMMA_LEN ("gt") },
16439 { STRING_COMMA_LEN ("ge") },
16440 { STRING_COMMA_LEN ("eq") },
16441 { STRING_COMMA_LEN ("neq") },
16442 { STRING_COMMA_LEN ("false") },
16443 { STRING_COMMA_LEN ("true") }
16447 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16448 int sizeflag ATTRIBUTE_UNUSED
)
16450 unsigned int cmp_type
;
16452 FETCH_DATA (the_info
, codep
+ 1);
16453 cmp_type
= *codep
++ & 0xff;
16454 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
16457 char *p
= mnemonicendp
- 2;
16459 /* vpcom* can have both one- and two-lettered suffix. */
16473 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
16474 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
16478 /* We have a reserved extension byte. Output it directly. */
16479 scratchbuf
[0] = '$';
16480 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16481 oappend_maybe_intel (scratchbuf
);
16482 scratchbuf
[0] = '\0';
16486 static const struct op pclmul_op
[] =
16488 { STRING_COMMA_LEN ("lql") },
16489 { STRING_COMMA_LEN ("hql") },
16490 { STRING_COMMA_LEN ("lqh") },
16491 { STRING_COMMA_LEN ("hqh") }
16495 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16496 int sizeflag ATTRIBUTE_UNUSED
)
16498 unsigned int pclmul_type
;
16500 FETCH_DATA (the_info
, codep
+ 1);
16501 pclmul_type
= *codep
++ & 0xff;
16502 switch (pclmul_type
)
16513 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
16516 char *p
= mnemonicendp
- 3;
16521 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
16522 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
16526 /* We have a reserved extension byte. Output it directly. */
16527 scratchbuf
[0] = '$';
16528 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
16529 oappend_maybe_intel (scratchbuf
);
16530 scratchbuf
[0] = '\0';
16535 MOVBE_Fixup (int bytemode
, int sizeflag
)
16537 /* Add proper suffix to "movbe". */
16538 char *p
= mnemonicendp
;
16547 if (sizeflag
& SUFFIX_ALWAYS
)
16553 if (sizeflag
& DFLAG
)
16557 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16562 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16569 OP_M (bytemode
, sizeflag
);
16573 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16576 const char **names
;
16578 /* Skip mod/rm byte. */
16592 oappend (names
[reg
]);
16596 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16598 const char **names
;
16599 unsigned int reg
= vex
.register_specifier
;
16600 vex
.register_specifier
= 0;
16607 if (address_mode
!= mode_64bit
)
16609 oappend (names
[reg
]);
16613 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16616 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
16620 if ((rex
& REX_R
) != 0 || !vex
.r
)
16626 oappend (names_mask
[modrm
.reg
]);
16630 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16633 || (bytemode
!= evex_rounding_mode
16634 && bytemode
!= evex_rounding_64_mode
16635 && bytemode
!= evex_sae_mode
))
16637 if (modrm
.mod
== 3 && vex
.b
)
16640 case evex_rounding_64_mode
:
16641 if (address_mode
!= mode_64bit
)
16646 /* Fall through. */
16647 case evex_rounding_mode
:
16648 oappend (names_rounding
[vex
.ll
]);
16650 case evex_sae_mode
: