1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2020 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
44 static int print_insn (bfd_vma
, disassemble_info
*);
45 static void dofloat (int);
46 static void OP_ST (int, int);
47 static void OP_STi (int, int);
48 static int putop (const char *, int);
49 static void oappend (const char *);
50 static void append_seg (void);
51 static void OP_indirE (int, int);
52 static void print_operand_value (char *, int, bfd_vma
);
53 static void OP_E_register (int, int);
54 static void OP_E_memory (int, int);
55 static void print_displacement (char *, bfd_vma
);
56 static void OP_E (int, int);
57 static void OP_G (int, int);
58 static bfd_vma
get64 (void);
59 static bfd_signed_vma
get32 (void);
60 static bfd_signed_vma
get32s (void);
61 static int get16 (void);
62 static void set_op (bfd_vma
, int);
63 static void OP_Skip_MODRM (int, int);
64 static void OP_REG (int, int);
65 static void OP_IMREG (int, int);
66 static void OP_I (int, int);
67 static void OP_I64 (int, int);
68 static void OP_sI (int, int);
69 static void OP_J (int, int);
70 static void OP_SEG (int, int);
71 static void OP_DIR (int, int);
72 static void OP_OFF (int, int);
73 static void OP_OFF64 (int, int);
74 static void ptr_reg (int, int);
75 static void OP_ESreg (int, int);
76 static void OP_DSreg (int, int);
77 static void OP_C (int, int);
78 static void OP_D (int, int);
79 static void OP_T (int, int);
80 static void OP_R (int, int);
81 static void OP_MMX (int, int);
82 static void OP_XMM (int, int);
83 static void OP_EM (int, int);
84 static void OP_EX (int, int);
85 static void OP_EMC (int,int);
86 static void OP_MXC (int,int);
87 static void OP_MS (int, int);
88 static void OP_XS (int, int);
89 static void OP_M (int, int);
90 static void OP_VEX (int, int);
91 static void OP_VexW (int, int);
92 static void OP_EX_Vex (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_Rounding (int, int);
95 static void OP_REG_VexI4 (int, int);
96 static void OP_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VPCMP_Fixup (int, int);
99 static void VPCOM_Fixup (int, int);
100 static void OP_0f07 (int, int);
101 static void OP_Monitor (int, int);
102 static void OP_Mwait (int, int);
103 static void NOP_Fixup1 (int, int);
104 static void NOP_Fixup2 (int, int);
105 static void OP_3DNowSuffix (int, int);
106 static void CMP_Fixup (int, int);
107 static void BadOp (void);
108 static void REP_Fixup (int, int);
109 static void SEP_Fixup (int, int);
110 static void BND_Fixup (int, int);
111 static void NOTRACK_Fixup (int, int);
112 static void HLE_Fixup1 (int, int);
113 static void HLE_Fixup2 (int, int);
114 static void HLE_Fixup3 (int, int);
115 static void CMPXCHG8B_Fixup (int, int);
116 static void XMM_Fixup (int, int);
117 static void FXSAVE_Fixup (int, int);
119 static void MOVSXD_Fixup (int, int);
121 static void OP_Mask (int, int);
124 /* Points to first byte not fetched. */
125 bfd_byte
*max_fetched
;
126 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
129 OPCODES_SIGJMP_BUF bailout
;
139 enum address_mode address_mode
;
141 /* Flags for the prefixes for the current instruction. See below. */
144 /* REX prefix the current instruction. See below. */
146 /* Bits of REX we've already used. */
148 /* Mark parts used in the REX prefix. When we are testing for
149 empty prefix (for 8bit register REX extension), just mask it
150 out. Otherwise test for REX bit is excuse for existence of REX
151 only in case value is nonzero. */
152 #define USED_REX(value) \
157 rex_used |= (value) | REX_OPCODE; \
160 rex_used |= REX_OPCODE; \
163 /* Flags for prefixes which we somehow handled when printing the
164 current instruction. */
165 static int used_prefixes
;
167 /* Flags stored in PREFIXES. */
168 #define PREFIX_REPZ 1
169 #define PREFIX_REPNZ 2
170 #define PREFIX_LOCK 4
172 #define PREFIX_SS 0x10
173 #define PREFIX_DS 0x20
174 #define PREFIX_ES 0x40
175 #define PREFIX_FS 0x80
176 #define PREFIX_GS 0x100
177 #define PREFIX_DATA 0x200
178 #define PREFIX_ADDR 0x400
179 #define PREFIX_FWAIT 0x800
181 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
182 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
184 #define FETCH_DATA(info, addr) \
185 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
186 ? 1 : fetch_data ((info), (addr)))
189 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
192 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
193 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
195 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
196 status
= (*info
->read_memory_func
) (start
,
198 addr
- priv
->max_fetched
,
204 /* If we did manage to read at least one byte, then
205 print_insn_i386 will do something sensible. Otherwise, print
206 an error. We do that here because this is where we know
208 if (priv
->max_fetched
== priv
->the_buffer
)
209 (*info
->memory_error_func
) (status
, start
, info
);
210 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
213 priv
->max_fetched
= addr
;
217 /* Possible values for prefix requirement. */
218 #define PREFIX_IGNORED_SHIFT 16
219 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
220 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
221 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
222 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
223 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
225 /* Opcode prefixes. */
226 #define PREFIX_OPCODE (PREFIX_REPZ \
230 /* Prefixes ignored. */
231 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
232 | PREFIX_IGNORED_REPNZ \
233 | PREFIX_IGNORED_DATA)
235 #define XX { NULL, 0 }
236 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
238 #define Eb { OP_E, b_mode }
239 #define Ebnd { OP_E, bnd_mode }
240 #define EbS { OP_E, b_swap_mode }
241 #define EbndS { OP_E, bnd_swap_mode }
242 #define Ev { OP_E, v_mode }
243 #define Eva { OP_E, va_mode }
244 #define Ev_bnd { OP_E, v_bnd_mode }
245 #define EvS { OP_E, v_swap_mode }
246 #define Ed { OP_E, d_mode }
247 #define Edq { OP_E, dq_mode }
248 #define Edqw { OP_E, dqw_mode }
249 #define Edqb { OP_E, dqb_mode }
250 #define Edb { OP_E, db_mode }
251 #define Edw { OP_E, dw_mode }
252 #define Edqd { OP_E, dqd_mode }
253 #define Eq { OP_E, q_mode }
254 #define indirEv { OP_indirE, indir_v_mode }
255 #define indirEp { OP_indirE, f_mode }
256 #define stackEv { OP_E, stack_v_mode }
257 #define Em { OP_E, m_mode }
258 #define Ew { OP_E, w_mode }
259 #define M { OP_M, 0 } /* lea, lgdt, etc. */
260 #define Ma { OP_M, a_mode }
261 #define Mb { OP_M, b_mode }
262 #define Md { OP_M, d_mode }
263 #define Mo { OP_M, o_mode }
264 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
265 #define Mq { OP_M, q_mode }
266 #define Mv { OP_M, v_mode }
267 #define Mv_bnd { OP_M, v_bndmk_mode }
268 #define Mx { OP_M, x_mode }
269 #define Mxmm { OP_M, xmm_mode }
270 #define Gb { OP_G, b_mode }
271 #define Gbnd { OP_G, bnd_mode }
272 #define Gv { OP_G, v_mode }
273 #define Gd { OP_G, d_mode }
274 #define Gdq { OP_G, dq_mode }
275 #define Gm { OP_G, m_mode }
276 #define Gva { OP_G, va_mode }
277 #define Gw { OP_G, w_mode }
278 #define Rd { OP_R, d_mode }
279 #define Rdq { OP_R, dq_mode }
280 #define Rm { OP_R, m_mode }
281 #define Ib { OP_I, b_mode }
282 #define sIb { OP_sI, b_mode } /* sign extened byte */
283 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
284 #define Iv { OP_I, v_mode }
285 #define sIv { OP_sI, v_mode }
286 #define Iv64 { OP_I64, v_mode }
287 #define Id { OP_I, d_mode }
288 #define Iw { OP_I, w_mode }
289 #define I1 { OP_I, const_1_mode }
290 #define Jb { OP_J, b_mode }
291 #define Jv { OP_J, v_mode }
292 #define Jdqw { OP_J, dqw_mode }
293 #define Cm { OP_C, m_mode }
294 #define Dm { OP_D, m_mode }
295 #define Td { OP_T, d_mode }
296 #define Skip_MODRM { OP_Skip_MODRM, 0 }
298 #define RMeAX { OP_REG, eAX_reg }
299 #define RMeBX { OP_REG, eBX_reg }
300 #define RMeCX { OP_REG, eCX_reg }
301 #define RMeDX { OP_REG, eDX_reg }
302 #define RMeSP { OP_REG, eSP_reg }
303 #define RMeBP { OP_REG, eBP_reg }
304 #define RMeSI { OP_REG, eSI_reg }
305 #define RMeDI { OP_REG, eDI_reg }
306 #define RMrAX { OP_REG, rAX_reg }
307 #define RMrBX { OP_REG, rBX_reg }
308 #define RMrCX { OP_REG, rCX_reg }
309 #define RMrDX { OP_REG, rDX_reg }
310 #define RMrSP { OP_REG, rSP_reg }
311 #define RMrBP { OP_REG, rBP_reg }
312 #define RMrSI { OP_REG, rSI_reg }
313 #define RMrDI { OP_REG, rDI_reg }
314 #define RMAL { OP_REG, al_reg }
315 #define RMCL { OP_REG, cl_reg }
316 #define RMDL { OP_REG, dl_reg }
317 #define RMBL { OP_REG, bl_reg }
318 #define RMAH { OP_REG, ah_reg }
319 #define RMCH { OP_REG, ch_reg }
320 #define RMDH { OP_REG, dh_reg }
321 #define RMBH { OP_REG, bh_reg }
322 #define RMAX { OP_REG, ax_reg }
323 #define RMDX { OP_REG, dx_reg }
325 #define eAX { OP_IMREG, eAX_reg }
326 #define AL { OP_IMREG, al_reg }
327 #define CL { OP_IMREG, cl_reg }
328 #define zAX { OP_IMREG, z_mode_ax_reg }
329 #define indirDX { OP_IMREG, indir_dx_reg }
331 #define Sw { OP_SEG, w_mode }
332 #define Sv { OP_SEG, v_mode }
333 #define Ap { OP_DIR, 0 }
334 #define Ob { OP_OFF64, b_mode }
335 #define Ov { OP_OFF64, v_mode }
336 #define Xb { OP_DSreg, eSI_reg }
337 #define Xv { OP_DSreg, eSI_reg }
338 #define Xz { OP_DSreg, eSI_reg }
339 #define Yb { OP_ESreg, eDI_reg }
340 #define Yv { OP_ESreg, eDI_reg }
341 #define DSBX { OP_DSreg, eBX_reg }
343 #define es { OP_REG, es_reg }
344 #define ss { OP_REG, ss_reg }
345 #define cs { OP_REG, cs_reg }
346 #define ds { OP_REG, ds_reg }
347 #define fs { OP_REG, fs_reg }
348 #define gs { OP_REG, gs_reg }
350 #define MX { OP_MMX, 0 }
351 #define XM { OP_XMM, 0 }
352 #define XMScalar { OP_XMM, scalar_mode }
353 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
354 #define XMM { OP_XMM, xmm_mode }
355 #define TMM { OP_XMM, tmm_mode }
356 #define XMxmmq { OP_XMM, xmmq_mode }
357 #define EM { OP_EM, v_mode }
358 #define EMS { OP_EM, v_swap_mode }
359 #define EMd { OP_EM, d_mode }
360 #define EMx { OP_EM, x_mode }
361 #define EXbwUnit { OP_EX, bw_unit_mode }
362 #define EXw { OP_EX, w_mode }
363 #define EXd { OP_EX, d_mode }
364 #define EXdS { OP_EX, d_swap_mode }
365 #define EXq { OP_EX, q_mode }
366 #define EXqS { OP_EX, q_swap_mode }
367 #define EXx { OP_EX, x_mode }
368 #define EXxS { OP_EX, x_swap_mode }
369 #define EXxmm { OP_EX, xmm_mode }
370 #define EXymm { OP_EX, ymm_mode }
371 #define EXtmm { OP_EX, tmm_mode }
372 #define EXxmmq { OP_EX, xmmq_mode }
373 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
374 #define EXxmm_mb { OP_EX, xmm_mb_mode }
375 #define EXxmm_mw { OP_EX, xmm_mw_mode }
376 #define EXxmm_md { OP_EX, xmm_md_mode }
377 #define EXxmm_mq { OP_EX, xmm_mq_mode }
378 #define EXxmmdw { OP_EX, xmmdw_mode }
379 #define EXxmmqd { OP_EX, xmmqd_mode }
380 #define EXymmq { OP_EX, ymmq_mode }
381 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
382 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
383 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
384 #define MS { OP_MS, v_mode }
385 #define XS { OP_XS, v_mode }
386 #define EMCq { OP_EMC, q_mode }
387 #define MXC { OP_MXC, 0 }
388 #define OPSUF { OP_3DNowSuffix, 0 }
389 #define SEP { SEP_Fixup, 0 }
390 #define CMP { CMP_Fixup, 0 }
391 #define XMM0 { XMM_Fixup, 0 }
392 #define FXSAVE { FXSAVE_Fixup, 0 }
394 #define Vex { OP_VEX, vex_mode }
395 #define VexW { OP_VexW, vex_mode }
396 #define VexScalar { OP_VEX, vex_scalar_mode }
397 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
398 #define Vex128 { OP_VEX, vex128_mode }
399 #define Vex256 { OP_VEX, vex256_mode }
400 #define VexGdq { OP_VEX, dq_mode }
401 #define VexTmm { OP_VEX, tmm_mode }
402 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
403 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
404 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
405 #define XMVexI4 { OP_REG_VexI4, x_mode }
406 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
407 #define VexI4 { OP_VexI4, 0 }
408 #define PCLMUL { PCLMUL_Fixup, 0 }
409 #define VPCMP { VPCMP_Fixup, 0 }
410 #define VPCOM { VPCOM_Fixup, 0 }
412 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
413 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
414 #define EXxEVexS { OP_Rounding, evex_sae_mode }
416 #define XMask { OP_Mask, mask_mode }
417 #define MaskG { OP_G, mask_mode }
418 #define MaskE { OP_E, mask_mode }
419 #define MaskBDE { OP_E, mask_bd_mode }
420 #define MaskR { OP_R, mask_mode }
421 #define MaskVex { OP_VEX, mask_mode }
423 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
424 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
425 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
426 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
428 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
430 /* Used handle "rep" prefix for string instructions. */
431 #define Xbr { REP_Fixup, eSI_reg }
432 #define Xvr { REP_Fixup, eSI_reg }
433 #define Ybr { REP_Fixup, eDI_reg }
434 #define Yvr { REP_Fixup, eDI_reg }
435 #define Yzr { REP_Fixup, eDI_reg }
436 #define indirDXr { REP_Fixup, indir_dx_reg }
437 #define ALr { REP_Fixup, al_reg }
438 #define eAXr { REP_Fixup, eAX_reg }
440 /* Used handle HLE prefix for lockable instructions. */
441 #define Ebh1 { HLE_Fixup1, b_mode }
442 #define Evh1 { HLE_Fixup1, v_mode }
443 #define Ebh2 { HLE_Fixup2, b_mode }
444 #define Evh2 { HLE_Fixup2, v_mode }
445 #define Ebh3 { HLE_Fixup3, b_mode }
446 #define Evh3 { HLE_Fixup3, v_mode }
448 #define BND { BND_Fixup, 0 }
449 #define NOTRACK { NOTRACK_Fixup, 0 }
451 #define cond_jump_flag { NULL, cond_jump_mode }
452 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
454 /* bits in sizeflag */
455 #define SUFFIX_ALWAYS 4
463 /* byte operand with operand swapped */
465 /* byte operand, sign extend like 'T' suffix */
467 /* operand size depends on prefixes */
469 /* operand size depends on prefixes with operand swapped */
471 /* operand size depends on address prefix */
475 /* double word operand */
477 /* double word operand with operand swapped */
479 /* quad word operand */
481 /* quad word operand with operand swapped */
483 /* ten-byte operand */
485 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
486 broadcast enabled. */
488 /* Similar to x_mode, but with different EVEX mem shifts. */
490 /* Similar to x_mode, but with yet different EVEX mem shifts. */
492 /* Similar to x_mode, but with disabled broadcast. */
494 /* Similar to x_mode, but with operands swapped and disabled broadcast
497 /* 16-byte XMM operand */
499 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
500 memory operand (depending on vector length). Broadcast isn't
503 /* Same as xmmq_mode, but broadcast is allowed. */
504 evex_half_bcst_xmmq_mode
,
505 /* XMM register or byte memory operand */
507 /* XMM register or word memory operand */
509 /* XMM register or double word memory operand */
511 /* XMM register or quad word memory operand */
513 /* 16-byte XMM, word, double word or quad word operand. */
515 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
517 /* 32-byte YMM operand */
519 /* quad word, ymmword or zmmword memory operand. */
521 /* 32-byte YMM or 16-byte word operand */
525 /* d_mode in 32bit, q_mode in 64bit mode. */
527 /* pair of v_mode operands */
533 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
535 /* operand size depends on REX prefixes. */
537 /* registers like dq_mode, memory like w_mode, displacements like
538 v_mode without considering Intel64 ISA. */
542 /* bounds operand with operand swapped */
544 /* 4- or 6-byte pointer operand */
547 /* v_mode for indirect branch opcodes. */
549 /* v_mode for stack-related opcodes. */
551 /* non-quad operand size depends on prefixes */
553 /* 16-byte operand */
555 /* registers like dq_mode, memory like b_mode. */
557 /* registers like d_mode, memory like b_mode. */
559 /* registers like d_mode, memory like w_mode. */
561 /* registers like dq_mode, memory like d_mode. */
563 /* normal vex mode */
565 /* 128bit vex mode */
567 /* 256bit vex mode */
570 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
571 vex_vsib_d_w_dq_mode
,
572 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
574 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
575 vex_vsib_q_w_dq_mode
,
576 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
578 /* mandatory non-vector SIB. */
581 /* scalar, ignore vector length. */
583 /* like d_swap_mode, ignore vector length. */
585 /* like q_swap_mode, ignore vector length. */
587 /* like vex_mode, ignore vector length. */
589 /* Operand size depends on the VEX.W bit, ignore vector length. */
590 vex_scalar_w_dq_mode
,
592 /* Static rounding. */
594 /* Static rounding, 64-bit mode only. */
595 evex_rounding_64_mode
,
596 /* Supress all exceptions. */
599 /* Mask register operand. */
601 /* Mask register operand. */
669 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
671 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
672 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
673 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
674 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
675 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
676 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
677 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
678 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
679 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
680 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
681 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
682 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
683 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
684 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
685 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
686 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
724 REG_VEX_0F3849_X86_64_P_0_W_0_M_1
,
729 REG_0FXOP_09_12_M_1_L_0
,
809 MOD_VEX_0F3849_X86_64_P_0_W_0
,
810 MOD_VEX_0F3849_X86_64_P_2_W_0
,
811 MOD_VEX_0F3849_X86_64_P_3_W_0
,
812 MOD_VEX_0F384B_X86_64_P_1_W_0
,
813 MOD_VEX_0F384B_X86_64_P_2_W_0
,
814 MOD_VEX_0F384B_X86_64_P_3_W_0
,
815 MOD_VEX_0F385C_X86_64_P_1_W_0
,
816 MOD_VEX_0F385E_X86_64_P_0_W_0
,
817 MOD_VEX_0F385E_X86_64_P_1_W_0
,
818 MOD_VEX_0F385E_X86_64_P_2_W_0
,
819 MOD_VEX_0F385E_X86_64_P_3_W_0
,
829 MOD_VEX_0F12_PREFIX_0
,
830 MOD_VEX_0F12_PREFIX_2
,
832 MOD_VEX_0F16_PREFIX_0
,
833 MOD_VEX_0F16_PREFIX_2
,
836 MOD_VEX_W_0_0F41_P_0_LEN_1
,
837 MOD_VEX_W_1_0F41_P_0_LEN_1
,
838 MOD_VEX_W_0_0F41_P_2_LEN_1
,
839 MOD_VEX_W_1_0F41_P_2_LEN_1
,
840 MOD_VEX_W_0_0F42_P_0_LEN_1
,
841 MOD_VEX_W_1_0F42_P_0_LEN_1
,
842 MOD_VEX_W_0_0F42_P_2_LEN_1
,
843 MOD_VEX_W_1_0F42_P_2_LEN_1
,
844 MOD_VEX_W_0_0F44_P_0_LEN_1
,
845 MOD_VEX_W_1_0F44_P_0_LEN_1
,
846 MOD_VEX_W_0_0F44_P_2_LEN_1
,
847 MOD_VEX_W_1_0F44_P_2_LEN_1
,
848 MOD_VEX_W_0_0F45_P_0_LEN_1
,
849 MOD_VEX_W_1_0F45_P_0_LEN_1
,
850 MOD_VEX_W_0_0F45_P_2_LEN_1
,
851 MOD_VEX_W_1_0F45_P_2_LEN_1
,
852 MOD_VEX_W_0_0F46_P_0_LEN_1
,
853 MOD_VEX_W_1_0F46_P_0_LEN_1
,
854 MOD_VEX_W_0_0F46_P_2_LEN_1
,
855 MOD_VEX_W_1_0F46_P_2_LEN_1
,
856 MOD_VEX_W_0_0F47_P_0_LEN_1
,
857 MOD_VEX_W_1_0F47_P_0_LEN_1
,
858 MOD_VEX_W_0_0F47_P_2_LEN_1
,
859 MOD_VEX_W_1_0F47_P_2_LEN_1
,
860 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
861 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
862 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
863 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
864 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
865 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
866 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
878 MOD_VEX_W_0_0F91_P_0_LEN_0
,
879 MOD_VEX_W_1_0F91_P_0_LEN_0
,
880 MOD_VEX_W_0_0F91_P_2_LEN_0
,
881 MOD_VEX_W_1_0F91_P_2_LEN_0
,
882 MOD_VEX_W_0_0F92_P_0_LEN_0
,
883 MOD_VEX_W_0_0F92_P_2_LEN_0
,
884 MOD_VEX_0F92_P_3_LEN_0
,
885 MOD_VEX_W_0_0F93_P_0_LEN_0
,
886 MOD_VEX_W_0_0F93_P_2_LEN_0
,
887 MOD_VEX_0F93_P_3_LEN_0
,
888 MOD_VEX_W_0_0F98_P_0_LEN_0
,
889 MOD_VEX_W_1_0F98_P_0_LEN_0
,
890 MOD_VEX_W_0_0F98_P_2_LEN_0
,
891 MOD_VEX_W_1_0F98_P_2_LEN_0
,
892 MOD_VEX_W_0_0F99_P_0_LEN_0
,
893 MOD_VEX_W_1_0F99_P_0_LEN_0
,
894 MOD_VEX_W_0_0F99_P_2_LEN_0
,
895 MOD_VEX_W_1_0F99_P_2_LEN_0
,
898 MOD_VEX_0FD7_PREFIX_2
,
899 MOD_VEX_0FE7_PREFIX_2
,
900 MOD_VEX_0FF0_PREFIX_3
,
901 MOD_VEX_0F381A_PREFIX_2
,
902 MOD_VEX_0F382A_PREFIX_2
,
903 MOD_VEX_0F382C_PREFIX_2
,
904 MOD_VEX_0F382D_PREFIX_2
,
905 MOD_VEX_0F382E_PREFIX_2
,
906 MOD_VEX_0F382F_PREFIX_2
,
907 MOD_VEX_0F385A_PREFIX_2
,
908 MOD_VEX_0F388C_PREFIX_2
,
909 MOD_VEX_0F388E_PREFIX_2
,
910 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
911 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
912 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
913 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
914 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
915 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
916 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
917 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
921 MOD_EVEX_0F12_PREFIX_0
,
922 MOD_EVEX_0F12_PREFIX_2
,
924 MOD_EVEX_0F16_PREFIX_0
,
925 MOD_EVEX_0F16_PREFIX_2
,
928 MOD_EVEX_0F381A_P_2_W_0
,
929 MOD_EVEX_0F381A_P_2_W_1
,
930 MOD_EVEX_0F381B_P_2_W_0
,
931 MOD_EVEX_0F381B_P_2_W_1
,
932 MOD_EVEX_0F385A_P_2_W_0
,
933 MOD_EVEX_0F385A_P_2_W_1
,
934 MOD_EVEX_0F385B_P_2_W_0
,
935 MOD_EVEX_0F385B_P_2_W_1
,
936 MOD_EVEX_0F38C6_REG_1
,
937 MOD_EVEX_0F38C6_REG_2
,
938 MOD_EVEX_0F38C6_REG_5
,
939 MOD_EVEX_0F38C6_REG_6
,
940 MOD_EVEX_0F38C7_REG_1
,
941 MOD_EVEX_0F38C7_REG_2
,
942 MOD_EVEX_0F38C7_REG_5
,
943 MOD_EVEX_0F38C7_REG_6
956 RM_0F1E_P_1_MOD_3_REG_7
,
957 RM_0FAE_REG_6_MOD_3_P_0
,
959 RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
965 PREFIX_0F01_REG_3_RM_1
,
966 PREFIX_0F01_REG_5_MOD_0
,
967 PREFIX_0F01_REG_5_MOD_3_RM_0
,
968 PREFIX_0F01_REG_5_MOD_3_RM_1
,
969 PREFIX_0F01_REG_5_MOD_3_RM_2
,
970 PREFIX_0F01_REG_7_MOD_3_RM_2
,
971 PREFIX_0F01_REG_7_MOD_3_RM_3
,
1013 PREFIX_0FAE_REG_0_MOD_3
,
1014 PREFIX_0FAE_REG_1_MOD_3
,
1015 PREFIX_0FAE_REG_2_MOD_3
,
1016 PREFIX_0FAE_REG_3_MOD_3
,
1017 PREFIX_0FAE_REG_4_MOD_0
,
1018 PREFIX_0FAE_REG_4_MOD_3
,
1019 PREFIX_0FAE_REG_5_MOD_0
,
1020 PREFIX_0FAE_REG_5_MOD_3
,
1021 PREFIX_0FAE_REG_6_MOD_0
,
1022 PREFIX_0FAE_REG_6_MOD_3
,
1023 PREFIX_0FAE_REG_7_MOD_0
,
1029 PREFIX_0FC7_REG_6_MOD_0
,
1030 PREFIX_0FC7_REG_6_MOD_3
,
1031 PREFIX_0FC7_REG_7_MOD_3
,
1161 PREFIX_VEX_0F71_REG_2
,
1162 PREFIX_VEX_0F71_REG_4
,
1163 PREFIX_VEX_0F71_REG_6
,
1164 PREFIX_VEX_0F72_REG_2
,
1165 PREFIX_VEX_0F72_REG_4
,
1166 PREFIX_VEX_0F72_REG_6
,
1167 PREFIX_VEX_0F73_REG_2
,
1168 PREFIX_VEX_0F73_REG_3
,
1169 PREFIX_VEX_0F73_REG_6
,
1170 PREFIX_VEX_0F73_REG_7
,
1295 PREFIX_VEX_0F3849_X86_64
,
1296 PREFIX_VEX_0F384B_X86_64
,
1300 PREFIX_VEX_0F385C_X86_64
,
1301 PREFIX_VEX_0F385E_X86_64
,
1347 PREFIX_VEX_0F38F3_REG_1
,
1348 PREFIX_VEX_0F38F3_REG_2
,
1349 PREFIX_VEX_0F38F3_REG_3
,
1446 PREFIX_EVEX_0F71_REG_2
,
1447 PREFIX_EVEX_0F71_REG_4
,
1448 PREFIX_EVEX_0F71_REG_6
,
1449 PREFIX_EVEX_0F72_REG_0
,
1450 PREFIX_EVEX_0F72_REG_1
,
1451 PREFIX_EVEX_0F72_REG_2
,
1452 PREFIX_EVEX_0F72_REG_4
,
1453 PREFIX_EVEX_0F72_REG_6
,
1454 PREFIX_EVEX_0F73_REG_2
,
1455 PREFIX_EVEX_0F73_REG_3
,
1456 PREFIX_EVEX_0F73_REG_6
,
1457 PREFIX_EVEX_0F73_REG_7
,
1579 PREFIX_EVEX_0F38C6_REG_1
,
1580 PREFIX_EVEX_0F38C6_REG_2
,
1581 PREFIX_EVEX_0F38C6_REG_5
,
1582 PREFIX_EVEX_0F38C6_REG_6
,
1583 PREFIX_EVEX_0F38C7_REG_1
,
1584 PREFIX_EVEX_0F38C7_REG_2
,
1585 PREFIX_EVEX_0F38C7_REG_5
,
1586 PREFIX_EVEX_0F38C7_REG_6
,
1683 THREE_BYTE_0F38
= 0,
1710 VEX_LEN_0F12_P_0_M_0
= 0,
1711 VEX_LEN_0F12_P_0_M_1
,
1712 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1714 VEX_LEN_0F16_P_0_M_0
,
1715 VEX_LEN_0F16_P_0_M_1
,
1716 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1752 VEX_LEN_0FAE_R_2_M_0
,
1753 VEX_LEN_0FAE_R_3_M_0
,
1760 VEX_LEN_0F381A_P_2_M_0
,
1763 VEX_LEN_0F3849_X86_64_P_0_W_0_M_0
,
1764 VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0
,
1765 VEX_LEN_0F3849_X86_64_P_2_W_0_M_0
,
1766 VEX_LEN_0F3849_X86_64_P_3_W_0_M_0
,
1767 VEX_LEN_0F384B_X86_64_P_1_W_0_M_0
,
1768 VEX_LEN_0F384B_X86_64_P_2_W_0_M_0
,
1769 VEX_LEN_0F384B_X86_64_P_3_W_0_M_0
,
1770 VEX_LEN_0F385A_P_2_M_0
,
1771 VEX_LEN_0F385C_X86_64_P_1_W_0_M_0
,
1772 VEX_LEN_0F385E_X86_64_P_0_W_0_M_0
,
1773 VEX_LEN_0F385E_X86_64_P_1_W_0_M_0
,
1774 VEX_LEN_0F385E_X86_64_P_2_W_0_M_0
,
1775 VEX_LEN_0F385E_X86_64_P_3_W_0_M_0
,
1778 VEX_LEN_0F38F3_R_1_P_0
,
1779 VEX_LEN_0F38F3_R_2_P_0
,
1780 VEX_LEN_0F38F3_R_3_P_0
,
1815 VEX_LEN_0FXOP_08_85
,
1816 VEX_LEN_0FXOP_08_86
,
1817 VEX_LEN_0FXOP_08_87
,
1818 VEX_LEN_0FXOP_08_8E
,
1819 VEX_LEN_0FXOP_08_8F
,
1820 VEX_LEN_0FXOP_08_95
,
1821 VEX_LEN_0FXOP_08_96
,
1822 VEX_LEN_0FXOP_08_97
,
1823 VEX_LEN_0FXOP_08_9E
,
1824 VEX_LEN_0FXOP_08_9F
,
1825 VEX_LEN_0FXOP_08_A3
,
1826 VEX_LEN_0FXOP_08_A6
,
1827 VEX_LEN_0FXOP_08_B6
,
1828 VEX_LEN_0FXOP_08_C0
,
1829 VEX_LEN_0FXOP_08_C1
,
1830 VEX_LEN_0FXOP_08_C2
,
1831 VEX_LEN_0FXOP_08_C3
,
1832 VEX_LEN_0FXOP_08_CC
,
1833 VEX_LEN_0FXOP_08_CD
,
1834 VEX_LEN_0FXOP_08_CE
,
1835 VEX_LEN_0FXOP_08_CF
,
1836 VEX_LEN_0FXOP_08_EC
,
1837 VEX_LEN_0FXOP_08_ED
,
1838 VEX_LEN_0FXOP_08_EE
,
1839 VEX_LEN_0FXOP_08_EF
,
1840 VEX_LEN_0FXOP_09_01
,
1841 VEX_LEN_0FXOP_09_02
,
1842 VEX_LEN_0FXOP_09_12_M_1
,
1843 VEX_LEN_0FXOP_09_82_W_0
,
1844 VEX_LEN_0FXOP_09_83_W_0
,
1845 VEX_LEN_0FXOP_09_90
,
1846 VEX_LEN_0FXOP_09_91
,
1847 VEX_LEN_0FXOP_09_92
,
1848 VEX_LEN_0FXOP_09_93
,
1849 VEX_LEN_0FXOP_09_94
,
1850 VEX_LEN_0FXOP_09_95
,
1851 VEX_LEN_0FXOP_09_96
,
1852 VEX_LEN_0FXOP_09_97
,
1853 VEX_LEN_0FXOP_09_98
,
1854 VEX_LEN_0FXOP_09_99
,
1855 VEX_LEN_0FXOP_09_9A
,
1856 VEX_LEN_0FXOP_09_9B
,
1857 VEX_LEN_0FXOP_09_C1
,
1858 VEX_LEN_0FXOP_09_C2
,
1859 VEX_LEN_0FXOP_09_C3
,
1860 VEX_LEN_0FXOP_09_C6
,
1861 VEX_LEN_0FXOP_09_C7
,
1862 VEX_LEN_0FXOP_09_CB
,
1863 VEX_LEN_0FXOP_09_D1
,
1864 VEX_LEN_0FXOP_09_D2
,
1865 VEX_LEN_0FXOP_09_D3
,
1866 VEX_LEN_0FXOP_09_D6
,
1867 VEX_LEN_0FXOP_09_D7
,
1868 VEX_LEN_0FXOP_09_DB
,
1869 VEX_LEN_0FXOP_09_E1
,
1870 VEX_LEN_0FXOP_09_E2
,
1871 VEX_LEN_0FXOP_09_E3
,
1872 VEX_LEN_0FXOP_0A_12
,
1877 EVEX_LEN_0F6E_P_2
= 0,
1883 EVEX_LEN_0F3816_P_2
,
1884 EVEX_LEN_0F3819_P_2_W_0
,
1885 EVEX_LEN_0F3819_P_2_W_1
,
1886 EVEX_LEN_0F381A_P_2_W_0_M_0
,
1887 EVEX_LEN_0F381A_P_2_W_1_M_0
,
1888 EVEX_LEN_0F381B_P_2_W_0_M_0
,
1889 EVEX_LEN_0F381B_P_2_W_1_M_0
,
1890 EVEX_LEN_0F3836_P_2
,
1891 EVEX_LEN_0F385A_P_2_W_0_M_0
,
1892 EVEX_LEN_0F385A_P_2_W_1_M_0
,
1893 EVEX_LEN_0F385B_P_2_W_0_M_0
,
1894 EVEX_LEN_0F385B_P_2_W_1_M_0
,
1895 EVEX_LEN_0F38C6_REG_1_PREFIX_2
,
1896 EVEX_LEN_0F38C6_REG_2_PREFIX_2
,
1897 EVEX_LEN_0F38C6_REG_5_PREFIX_2
,
1898 EVEX_LEN_0F38C6_REG_6_PREFIX_2
,
1899 EVEX_LEN_0F38C7_R_1_P_2_W_0
,
1900 EVEX_LEN_0F38C7_R_1_P_2_W_1
,
1901 EVEX_LEN_0F38C7_R_2_P_2_W_0
,
1902 EVEX_LEN_0F38C7_R_2_P_2_W_1
,
1903 EVEX_LEN_0F38C7_R_5_P_2_W_0
,
1904 EVEX_LEN_0F38C7_R_5_P_2_W_1
,
1905 EVEX_LEN_0F38C7_R_6_P_2_W_0
,
1906 EVEX_LEN_0F38C7_R_6_P_2_W_1
,
1907 EVEX_LEN_0F3A00_P_2_W_1
,
1908 EVEX_LEN_0F3A01_P_2_W_1
,
1909 EVEX_LEN_0F3A14_P_2
,
1910 EVEX_LEN_0F3A15_P_2
,
1911 EVEX_LEN_0F3A16_P_2
,
1912 EVEX_LEN_0F3A17_P_2
,
1913 EVEX_LEN_0F3A18_P_2_W_0
,
1914 EVEX_LEN_0F3A18_P_2_W_1
,
1915 EVEX_LEN_0F3A19_P_2_W_0
,
1916 EVEX_LEN_0F3A19_P_2_W_1
,
1917 EVEX_LEN_0F3A1A_P_2_W_0
,
1918 EVEX_LEN_0F3A1A_P_2_W_1
,
1919 EVEX_LEN_0F3A1B_P_2_W_0
,
1920 EVEX_LEN_0F3A1B_P_2_W_1
,
1921 EVEX_LEN_0F3A20_P_2
,
1922 EVEX_LEN_0F3A21_P_2_W_0
,
1923 EVEX_LEN_0F3A22_P_2
,
1924 EVEX_LEN_0F3A23_P_2_W_0
,
1925 EVEX_LEN_0F3A23_P_2_W_1
,
1926 EVEX_LEN_0F3A38_P_2_W_0
,
1927 EVEX_LEN_0F3A38_P_2_W_1
,
1928 EVEX_LEN_0F3A39_P_2_W_0
,
1929 EVEX_LEN_0F3A39_P_2_W_1
,
1930 EVEX_LEN_0F3A3A_P_2_W_0
,
1931 EVEX_LEN_0F3A3A_P_2_W_1
,
1932 EVEX_LEN_0F3A3B_P_2_W_0
,
1933 EVEX_LEN_0F3A3B_P_2_W_1
,
1934 EVEX_LEN_0F3A43_P_2_W_0
,
1935 EVEX_LEN_0F3A43_P_2_W_1
1940 VEX_W_0F41_P_0_LEN_1
= 0,
1941 VEX_W_0F41_P_2_LEN_1
,
1942 VEX_W_0F42_P_0_LEN_1
,
1943 VEX_W_0F42_P_2_LEN_1
,
1944 VEX_W_0F44_P_0_LEN_0
,
1945 VEX_W_0F44_P_2_LEN_0
,
1946 VEX_W_0F45_P_0_LEN_1
,
1947 VEX_W_0F45_P_2_LEN_1
,
1948 VEX_W_0F46_P_0_LEN_1
,
1949 VEX_W_0F46_P_2_LEN_1
,
1950 VEX_W_0F47_P_0_LEN_1
,
1951 VEX_W_0F47_P_2_LEN_1
,
1952 VEX_W_0F4A_P_0_LEN_1
,
1953 VEX_W_0F4A_P_2_LEN_1
,
1954 VEX_W_0F4B_P_0_LEN_1
,
1955 VEX_W_0F4B_P_2_LEN_1
,
1956 VEX_W_0F90_P_0_LEN_0
,
1957 VEX_W_0F90_P_2_LEN_0
,
1958 VEX_W_0F91_P_0_LEN_0
,
1959 VEX_W_0F91_P_2_LEN_0
,
1960 VEX_W_0F92_P_0_LEN_0
,
1961 VEX_W_0F92_P_2_LEN_0
,
1962 VEX_W_0F93_P_0_LEN_0
,
1963 VEX_W_0F93_P_2_LEN_0
,
1964 VEX_W_0F98_P_0_LEN_0
,
1965 VEX_W_0F98_P_2_LEN_0
,
1966 VEX_W_0F99_P_0_LEN_0
,
1967 VEX_W_0F99_P_2_LEN_0
,
1976 VEX_W_0F381A_P_2_M_0
,
1977 VEX_W_0F382C_P_2_M_0
,
1978 VEX_W_0F382D_P_2_M_0
,
1979 VEX_W_0F382E_P_2_M_0
,
1980 VEX_W_0F382F_P_2_M_0
,
1983 VEX_W_0F3849_X86_64_P_0
,
1984 VEX_W_0F3849_X86_64_P_2
,
1985 VEX_W_0F3849_X86_64_P_3
,
1986 VEX_W_0F384B_X86_64_P_1
,
1987 VEX_W_0F384B_X86_64_P_2
,
1988 VEX_W_0F384B_X86_64_P_3
,
1991 VEX_W_0F385A_P_2_M_0
,
1992 VEX_W_0F385C_X86_64_P_1
,
1993 VEX_W_0F385E_X86_64_P_0
,
1994 VEX_W_0F385E_X86_64_P_1
,
1995 VEX_W_0F385E_X86_64_P_2
,
1996 VEX_W_0F385E_X86_64_P_3
,
2009 VEX_W_0F3A30_P_2_LEN_0
,
2010 VEX_W_0F3A31_P_2_LEN_0
,
2011 VEX_W_0F3A32_P_2_LEN_0
,
2012 VEX_W_0F3A33_P_2_LEN_0
,
2022 VEX_W_0FXOP_08_85_L_0
,
2023 VEX_W_0FXOP_08_86_L_0
,
2024 VEX_W_0FXOP_08_87_L_0
,
2025 VEX_W_0FXOP_08_8E_L_0
,
2026 VEX_W_0FXOP_08_8F_L_0
,
2027 VEX_W_0FXOP_08_95_L_0
,
2028 VEX_W_0FXOP_08_96_L_0
,
2029 VEX_W_0FXOP_08_97_L_0
,
2030 VEX_W_0FXOP_08_9E_L_0
,
2031 VEX_W_0FXOP_08_9F_L_0
,
2032 VEX_W_0FXOP_08_A6_L_0
,
2033 VEX_W_0FXOP_08_B6_L_0
,
2034 VEX_W_0FXOP_08_C0_L_0
,
2035 VEX_W_0FXOP_08_C1_L_0
,
2036 VEX_W_0FXOP_08_C2_L_0
,
2037 VEX_W_0FXOP_08_C3_L_0
,
2038 VEX_W_0FXOP_08_CC_L_0
,
2039 VEX_W_0FXOP_08_CD_L_0
,
2040 VEX_W_0FXOP_08_CE_L_0
,
2041 VEX_W_0FXOP_08_CF_L_0
,
2042 VEX_W_0FXOP_08_EC_L_0
,
2043 VEX_W_0FXOP_08_ED_L_0
,
2044 VEX_W_0FXOP_08_EE_L_0
,
2045 VEX_W_0FXOP_08_EF_L_0
,
2051 VEX_W_0FXOP_09_C1_L_0
,
2052 VEX_W_0FXOP_09_C2_L_0
,
2053 VEX_W_0FXOP_09_C3_L_0
,
2054 VEX_W_0FXOP_09_C6_L_0
,
2055 VEX_W_0FXOP_09_C7_L_0
,
2056 VEX_W_0FXOP_09_CB_L_0
,
2057 VEX_W_0FXOP_09_D1_L_0
,
2058 VEX_W_0FXOP_09_D2_L_0
,
2059 VEX_W_0FXOP_09_D3_L_0
,
2060 VEX_W_0FXOP_09_D6_L_0
,
2061 VEX_W_0FXOP_09_D7_L_0
,
2062 VEX_W_0FXOP_09_DB_L_0
,
2063 VEX_W_0FXOP_09_E1_L_0
,
2064 VEX_W_0FXOP_09_E2_L_0
,
2065 VEX_W_0FXOP_09_E3_L_0
,
2071 EVEX_W_0F12_P_0_M_1
,
2074 EVEX_W_0F16_P_0_M_1
,
2108 EVEX_W_0F72_R_2_P_2
,
2109 EVEX_W_0F72_R_6_P_2
,
2110 EVEX_W_0F73_R_2_P_2
,
2111 EVEX_W_0F73_R_6_P_2
,
2194 EVEX_W_0F38C7_R_1_P_2
,
2195 EVEX_W_0F38C7_R_2_P_2
,
2196 EVEX_W_0F38C7_R_5_P_2
,
2197 EVEX_W_0F38C7_R_6_P_2
,
2222 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2231 unsigned int prefix_requirement
;
2234 /* Upper case letters in the instruction names here are macros.
2235 'A' => print 'b' if no register operands or suffix_always is true
2236 'B' => print 'b' if suffix_always is true
2237 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2239 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2240 suffix_always is true
2241 'E' => print 'e' if 32-bit form of jcxz
2242 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2243 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2244 'H' => print ",pt" or ",pn" branch hint
2247 'K' => print 'd' or 'q' if rex prefix is present.
2248 'L' => print 'l' if suffix_always is true
2249 'M' => print 'r' if intel_mnemonic is false.
2250 'N' => print 'n' if instruction has no wait "prefix"
2251 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2252 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2253 or suffix_always is true. print 'q' if rex prefix is present.
2254 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2256 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2257 'S' => print 'w', 'l' or 'q' if suffix_always is true
2258 'T' => print 'q' in 64bit mode if instruction has no operand size
2259 prefix and behave as 'P' otherwise
2260 'U' => print 'q' in 64bit mode if instruction has no operand size
2261 prefix and behave as 'Q' otherwise
2262 'V' => print 'q' in 64bit mode if instruction has no operand size
2263 prefix and behave as 'S' otherwise
2264 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2265 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2267 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2268 '!' => change condition from true to false or from false to true.
2269 '%' => add 1 upper case letter to the macro.
2270 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
2271 prefix or suffix_always is true (lcall/ljmp).
2272 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2273 on operand size prefix.
2274 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2275 has no operand size prefix for AMD64 ISA, behave as 'P'
2278 2 upper case letter macros:
2279 "XY" => print 'x' or 'y' if suffix_always is true or no register
2280 operands and no broadcast.
2281 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2282 register operands and no broadcast.
2283 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2284 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
2285 being false, or no operand at all in 64bit mode, or if suffix_always
2287 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2288 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2289 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2290 "LW" => print 'd', 'q' depending on the VEX.W bit
2291 "BW" => print 'b' or 'w' depending on the EVEX.W bit
2292 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2293 an operand size prefix, or suffix_always is true. print
2294 'q' if rex prefix is present.
2296 Many of the above letters print nothing in Intel mode. See "putop"
2299 Braces '{' and '}', and vertical bars '|', indicate alternative
2300 mnemonic strings for AT&T and Intel. */
2302 static const struct dis386 dis386
[] = {
2304 { "addB", { Ebh1
, Gb
}, 0 },
2305 { "addS", { Evh1
, Gv
}, 0 },
2306 { "addB", { Gb
, EbS
}, 0 },
2307 { "addS", { Gv
, EvS
}, 0 },
2308 { "addB", { AL
, Ib
}, 0 },
2309 { "addS", { eAX
, Iv
}, 0 },
2310 { X86_64_TABLE (X86_64_06
) },
2311 { X86_64_TABLE (X86_64_07
) },
2313 { "orB", { Ebh1
, Gb
}, 0 },
2314 { "orS", { Evh1
, Gv
}, 0 },
2315 { "orB", { Gb
, EbS
}, 0 },
2316 { "orS", { Gv
, EvS
}, 0 },
2317 { "orB", { AL
, Ib
}, 0 },
2318 { "orS", { eAX
, Iv
}, 0 },
2319 { X86_64_TABLE (X86_64_0E
) },
2320 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2322 { "adcB", { Ebh1
, Gb
}, 0 },
2323 { "adcS", { Evh1
, Gv
}, 0 },
2324 { "adcB", { Gb
, EbS
}, 0 },
2325 { "adcS", { Gv
, EvS
}, 0 },
2326 { "adcB", { AL
, Ib
}, 0 },
2327 { "adcS", { eAX
, Iv
}, 0 },
2328 { X86_64_TABLE (X86_64_16
) },
2329 { X86_64_TABLE (X86_64_17
) },
2331 { "sbbB", { Ebh1
, Gb
}, 0 },
2332 { "sbbS", { Evh1
, Gv
}, 0 },
2333 { "sbbB", { Gb
, EbS
}, 0 },
2334 { "sbbS", { Gv
, EvS
}, 0 },
2335 { "sbbB", { AL
, Ib
}, 0 },
2336 { "sbbS", { eAX
, Iv
}, 0 },
2337 { X86_64_TABLE (X86_64_1E
) },
2338 { X86_64_TABLE (X86_64_1F
) },
2340 { "andB", { Ebh1
, Gb
}, 0 },
2341 { "andS", { Evh1
, Gv
}, 0 },
2342 { "andB", { Gb
, EbS
}, 0 },
2343 { "andS", { Gv
, EvS
}, 0 },
2344 { "andB", { AL
, Ib
}, 0 },
2345 { "andS", { eAX
, Iv
}, 0 },
2346 { Bad_Opcode
}, /* SEG ES prefix */
2347 { X86_64_TABLE (X86_64_27
) },
2349 { "subB", { Ebh1
, Gb
}, 0 },
2350 { "subS", { Evh1
, Gv
}, 0 },
2351 { "subB", { Gb
, EbS
}, 0 },
2352 { "subS", { Gv
, EvS
}, 0 },
2353 { "subB", { AL
, Ib
}, 0 },
2354 { "subS", { eAX
, Iv
}, 0 },
2355 { Bad_Opcode
}, /* SEG CS prefix */
2356 { X86_64_TABLE (X86_64_2F
) },
2358 { "xorB", { Ebh1
, Gb
}, 0 },
2359 { "xorS", { Evh1
, Gv
}, 0 },
2360 { "xorB", { Gb
, EbS
}, 0 },
2361 { "xorS", { Gv
, EvS
}, 0 },
2362 { "xorB", { AL
, Ib
}, 0 },
2363 { "xorS", { eAX
, Iv
}, 0 },
2364 { Bad_Opcode
}, /* SEG SS prefix */
2365 { X86_64_TABLE (X86_64_37
) },
2367 { "cmpB", { Eb
, Gb
}, 0 },
2368 { "cmpS", { Ev
, Gv
}, 0 },
2369 { "cmpB", { Gb
, EbS
}, 0 },
2370 { "cmpS", { Gv
, EvS
}, 0 },
2371 { "cmpB", { AL
, Ib
}, 0 },
2372 { "cmpS", { eAX
, Iv
}, 0 },
2373 { Bad_Opcode
}, /* SEG DS prefix */
2374 { X86_64_TABLE (X86_64_3F
) },
2376 { "inc{S|}", { RMeAX
}, 0 },
2377 { "inc{S|}", { RMeCX
}, 0 },
2378 { "inc{S|}", { RMeDX
}, 0 },
2379 { "inc{S|}", { RMeBX
}, 0 },
2380 { "inc{S|}", { RMeSP
}, 0 },
2381 { "inc{S|}", { RMeBP
}, 0 },
2382 { "inc{S|}", { RMeSI
}, 0 },
2383 { "inc{S|}", { RMeDI
}, 0 },
2385 { "dec{S|}", { RMeAX
}, 0 },
2386 { "dec{S|}", { RMeCX
}, 0 },
2387 { "dec{S|}", { RMeDX
}, 0 },
2388 { "dec{S|}", { RMeBX
}, 0 },
2389 { "dec{S|}", { RMeSP
}, 0 },
2390 { "dec{S|}", { RMeBP
}, 0 },
2391 { "dec{S|}", { RMeSI
}, 0 },
2392 { "dec{S|}", { RMeDI
}, 0 },
2394 { "pushV", { RMrAX
}, 0 },
2395 { "pushV", { RMrCX
}, 0 },
2396 { "pushV", { RMrDX
}, 0 },
2397 { "pushV", { RMrBX
}, 0 },
2398 { "pushV", { RMrSP
}, 0 },
2399 { "pushV", { RMrBP
}, 0 },
2400 { "pushV", { RMrSI
}, 0 },
2401 { "pushV", { RMrDI
}, 0 },
2403 { "popV", { RMrAX
}, 0 },
2404 { "popV", { RMrCX
}, 0 },
2405 { "popV", { RMrDX
}, 0 },
2406 { "popV", { RMrBX
}, 0 },
2407 { "popV", { RMrSP
}, 0 },
2408 { "popV", { RMrBP
}, 0 },
2409 { "popV", { RMrSI
}, 0 },
2410 { "popV", { RMrDI
}, 0 },
2412 { X86_64_TABLE (X86_64_60
) },
2413 { X86_64_TABLE (X86_64_61
) },
2414 { X86_64_TABLE (X86_64_62
) },
2415 { X86_64_TABLE (X86_64_63
) },
2416 { Bad_Opcode
}, /* seg fs */
2417 { Bad_Opcode
}, /* seg gs */
2418 { Bad_Opcode
}, /* op size prefix */
2419 { Bad_Opcode
}, /* adr size prefix */
2421 { "pushT", { sIv
}, 0 },
2422 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2423 { "pushT", { sIbT
}, 0 },
2424 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2425 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2426 { X86_64_TABLE (X86_64_6D
) },
2427 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2428 { X86_64_TABLE (X86_64_6F
) },
2430 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2431 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2432 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2433 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2434 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2435 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2436 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2437 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2439 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2440 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2441 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2442 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2443 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2444 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2445 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2446 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2448 { REG_TABLE (REG_80
) },
2449 { REG_TABLE (REG_81
) },
2450 { X86_64_TABLE (X86_64_82
) },
2451 { REG_TABLE (REG_83
) },
2452 { "testB", { Eb
, Gb
}, 0 },
2453 { "testS", { Ev
, Gv
}, 0 },
2454 { "xchgB", { Ebh2
, Gb
}, 0 },
2455 { "xchgS", { Evh2
, Gv
}, 0 },
2457 { "movB", { Ebh3
, Gb
}, 0 },
2458 { "movS", { Evh3
, Gv
}, 0 },
2459 { "movB", { Gb
, EbS
}, 0 },
2460 { "movS", { Gv
, EvS
}, 0 },
2461 { "movD", { Sv
, Sw
}, 0 },
2462 { MOD_TABLE (MOD_8D
) },
2463 { "movD", { Sw
, Sv
}, 0 },
2464 { REG_TABLE (REG_8F
) },
2466 { PREFIX_TABLE (PREFIX_90
) },
2467 { "xchgS", { RMeCX
, eAX
}, 0 },
2468 { "xchgS", { RMeDX
, eAX
}, 0 },
2469 { "xchgS", { RMeBX
, eAX
}, 0 },
2470 { "xchgS", { RMeSP
, eAX
}, 0 },
2471 { "xchgS", { RMeBP
, eAX
}, 0 },
2472 { "xchgS", { RMeSI
, eAX
}, 0 },
2473 { "xchgS", { RMeDI
, eAX
}, 0 },
2475 { "cW{t|}R", { XX
}, 0 },
2476 { "cR{t|}O", { XX
}, 0 },
2477 { X86_64_TABLE (X86_64_9A
) },
2478 { Bad_Opcode
}, /* fwait */
2479 { "pushfT", { XX
}, 0 },
2480 { "popfT", { XX
}, 0 },
2481 { "sahf", { XX
}, 0 },
2482 { "lahf", { XX
}, 0 },
2484 { "mov%LB", { AL
, Ob
}, 0 },
2485 { "mov%LS", { eAX
, Ov
}, 0 },
2486 { "mov%LB", { Ob
, AL
}, 0 },
2487 { "mov%LS", { Ov
, eAX
}, 0 },
2488 { "movs{b|}", { Ybr
, Xb
}, 0 },
2489 { "movs{R|}", { Yvr
, Xv
}, 0 },
2490 { "cmps{b|}", { Xb
, Yb
}, 0 },
2491 { "cmps{R|}", { Xv
, Yv
}, 0 },
2493 { "testB", { AL
, Ib
}, 0 },
2494 { "testS", { eAX
, Iv
}, 0 },
2495 { "stosB", { Ybr
, AL
}, 0 },
2496 { "stosS", { Yvr
, eAX
}, 0 },
2497 { "lodsB", { ALr
, Xb
}, 0 },
2498 { "lodsS", { eAXr
, Xv
}, 0 },
2499 { "scasB", { AL
, Yb
}, 0 },
2500 { "scasS", { eAX
, Yv
}, 0 },
2502 { "movB", { RMAL
, Ib
}, 0 },
2503 { "movB", { RMCL
, Ib
}, 0 },
2504 { "movB", { RMDL
, Ib
}, 0 },
2505 { "movB", { RMBL
, Ib
}, 0 },
2506 { "movB", { RMAH
, Ib
}, 0 },
2507 { "movB", { RMCH
, Ib
}, 0 },
2508 { "movB", { RMDH
, Ib
}, 0 },
2509 { "movB", { RMBH
, Ib
}, 0 },
2511 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2512 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2513 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2514 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2515 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2516 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2517 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2518 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2520 { REG_TABLE (REG_C0
) },
2521 { REG_TABLE (REG_C1
) },
2522 { X86_64_TABLE (X86_64_C2
) },
2523 { X86_64_TABLE (X86_64_C3
) },
2524 { X86_64_TABLE (X86_64_C4
) },
2525 { X86_64_TABLE (X86_64_C5
) },
2526 { REG_TABLE (REG_C6
) },
2527 { REG_TABLE (REG_C7
) },
2529 { "enterT", { Iw
, Ib
}, 0 },
2530 { "leaveT", { XX
}, 0 },
2531 { "{l|}ret{|f}P", { Iw
}, 0 },
2532 { "{l|}ret{|f}P", { XX
}, 0 },
2533 { "int3", { XX
}, 0 },
2534 { "int", { Ib
}, 0 },
2535 { X86_64_TABLE (X86_64_CE
) },
2536 { "iret%LP", { XX
}, 0 },
2538 { REG_TABLE (REG_D0
) },
2539 { REG_TABLE (REG_D1
) },
2540 { REG_TABLE (REG_D2
) },
2541 { REG_TABLE (REG_D3
) },
2542 { X86_64_TABLE (X86_64_D4
) },
2543 { X86_64_TABLE (X86_64_D5
) },
2545 { "xlat", { DSBX
}, 0 },
2556 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2557 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2558 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2559 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2560 { "inB", { AL
, Ib
}, 0 },
2561 { "inG", { zAX
, Ib
}, 0 },
2562 { "outB", { Ib
, AL
}, 0 },
2563 { "outG", { Ib
, zAX
}, 0 },
2565 { X86_64_TABLE (X86_64_E8
) },
2566 { X86_64_TABLE (X86_64_E9
) },
2567 { X86_64_TABLE (X86_64_EA
) },
2568 { "jmp", { Jb
, BND
}, 0 },
2569 { "inB", { AL
, indirDX
}, 0 },
2570 { "inG", { zAX
, indirDX
}, 0 },
2571 { "outB", { indirDX
, AL
}, 0 },
2572 { "outG", { indirDX
, zAX
}, 0 },
2574 { Bad_Opcode
}, /* lock prefix */
2575 { "icebp", { XX
}, 0 },
2576 { Bad_Opcode
}, /* repne */
2577 { Bad_Opcode
}, /* repz */
2578 { "hlt", { XX
}, 0 },
2579 { "cmc", { XX
}, 0 },
2580 { REG_TABLE (REG_F6
) },
2581 { REG_TABLE (REG_F7
) },
2583 { "clc", { XX
}, 0 },
2584 { "stc", { XX
}, 0 },
2585 { "cli", { XX
}, 0 },
2586 { "sti", { XX
}, 0 },
2587 { "cld", { XX
}, 0 },
2588 { "std", { XX
}, 0 },
2589 { REG_TABLE (REG_FE
) },
2590 { REG_TABLE (REG_FF
) },
2593 static const struct dis386 dis386_twobyte
[] = {
2595 { REG_TABLE (REG_0F00
) },
2596 { REG_TABLE (REG_0F01
) },
2597 { "larS", { Gv
, Ew
}, 0 },
2598 { "lslS", { Gv
, Ew
}, 0 },
2600 { "syscall", { XX
}, 0 },
2601 { "clts", { XX
}, 0 },
2602 { "sysret%LQ", { XX
}, 0 },
2604 { "invd", { XX
}, 0 },
2605 { PREFIX_TABLE (PREFIX_0F09
) },
2607 { "ud2", { XX
}, 0 },
2609 { REG_TABLE (REG_0F0D
) },
2610 { "femms", { XX
}, 0 },
2611 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2613 { PREFIX_TABLE (PREFIX_0F10
) },
2614 { PREFIX_TABLE (PREFIX_0F11
) },
2615 { PREFIX_TABLE (PREFIX_0F12
) },
2616 { MOD_TABLE (MOD_0F13
) },
2617 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2618 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2619 { PREFIX_TABLE (PREFIX_0F16
) },
2620 { MOD_TABLE (MOD_0F17
) },
2622 { REG_TABLE (REG_0F18
) },
2623 { "nopQ", { Ev
}, 0 },
2624 { PREFIX_TABLE (PREFIX_0F1A
) },
2625 { PREFIX_TABLE (PREFIX_0F1B
) },
2626 { PREFIX_TABLE (PREFIX_0F1C
) },
2627 { "nopQ", { Ev
}, 0 },
2628 { PREFIX_TABLE (PREFIX_0F1E
) },
2629 { "nopQ", { Ev
}, 0 },
2631 { "movZ", { Rm
, Cm
}, 0 },
2632 { "movZ", { Rm
, Dm
}, 0 },
2633 { "movZ", { Cm
, Rm
}, 0 },
2634 { "movZ", { Dm
, Rm
}, 0 },
2635 { MOD_TABLE (MOD_0F24
) },
2637 { MOD_TABLE (MOD_0F26
) },
2640 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2641 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2642 { PREFIX_TABLE (PREFIX_0F2A
) },
2643 { PREFIX_TABLE (PREFIX_0F2B
) },
2644 { PREFIX_TABLE (PREFIX_0F2C
) },
2645 { PREFIX_TABLE (PREFIX_0F2D
) },
2646 { PREFIX_TABLE (PREFIX_0F2E
) },
2647 { PREFIX_TABLE (PREFIX_0F2F
) },
2649 { "wrmsr", { XX
}, 0 },
2650 { "rdtsc", { XX
}, 0 },
2651 { "rdmsr", { XX
}, 0 },
2652 { "rdpmc", { XX
}, 0 },
2653 { "sysenter", { SEP
}, 0 },
2654 { "sysexit", { SEP
}, 0 },
2656 { "getsec", { XX
}, 0 },
2658 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2660 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2667 { "cmovoS", { Gv
, Ev
}, 0 },
2668 { "cmovnoS", { Gv
, Ev
}, 0 },
2669 { "cmovbS", { Gv
, Ev
}, 0 },
2670 { "cmovaeS", { Gv
, Ev
}, 0 },
2671 { "cmoveS", { Gv
, Ev
}, 0 },
2672 { "cmovneS", { Gv
, Ev
}, 0 },
2673 { "cmovbeS", { Gv
, Ev
}, 0 },
2674 { "cmovaS", { Gv
, Ev
}, 0 },
2676 { "cmovsS", { Gv
, Ev
}, 0 },
2677 { "cmovnsS", { Gv
, Ev
}, 0 },
2678 { "cmovpS", { Gv
, Ev
}, 0 },
2679 { "cmovnpS", { Gv
, Ev
}, 0 },
2680 { "cmovlS", { Gv
, Ev
}, 0 },
2681 { "cmovgeS", { Gv
, Ev
}, 0 },
2682 { "cmovleS", { Gv
, Ev
}, 0 },
2683 { "cmovgS", { Gv
, Ev
}, 0 },
2685 { MOD_TABLE (MOD_0F50
) },
2686 { PREFIX_TABLE (PREFIX_0F51
) },
2687 { PREFIX_TABLE (PREFIX_0F52
) },
2688 { PREFIX_TABLE (PREFIX_0F53
) },
2689 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2690 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2691 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2692 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2694 { PREFIX_TABLE (PREFIX_0F58
) },
2695 { PREFIX_TABLE (PREFIX_0F59
) },
2696 { PREFIX_TABLE (PREFIX_0F5A
) },
2697 { PREFIX_TABLE (PREFIX_0F5B
) },
2698 { PREFIX_TABLE (PREFIX_0F5C
) },
2699 { PREFIX_TABLE (PREFIX_0F5D
) },
2700 { PREFIX_TABLE (PREFIX_0F5E
) },
2701 { PREFIX_TABLE (PREFIX_0F5F
) },
2703 { PREFIX_TABLE (PREFIX_0F60
) },
2704 { PREFIX_TABLE (PREFIX_0F61
) },
2705 { PREFIX_TABLE (PREFIX_0F62
) },
2706 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2707 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2708 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2709 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2710 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2712 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2713 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2714 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2715 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2716 { PREFIX_TABLE (PREFIX_0F6C
) },
2717 { PREFIX_TABLE (PREFIX_0F6D
) },
2718 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2719 { PREFIX_TABLE (PREFIX_0F6F
) },
2721 { PREFIX_TABLE (PREFIX_0F70
) },
2722 { REG_TABLE (REG_0F71
) },
2723 { REG_TABLE (REG_0F72
) },
2724 { REG_TABLE (REG_0F73
) },
2725 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2726 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2727 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2728 { "emms", { XX
}, PREFIX_OPCODE
},
2730 { PREFIX_TABLE (PREFIX_0F78
) },
2731 { PREFIX_TABLE (PREFIX_0F79
) },
2734 { PREFIX_TABLE (PREFIX_0F7C
) },
2735 { PREFIX_TABLE (PREFIX_0F7D
) },
2736 { PREFIX_TABLE (PREFIX_0F7E
) },
2737 { PREFIX_TABLE (PREFIX_0F7F
) },
2739 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2740 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2741 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2742 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2743 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2744 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2745 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2746 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2748 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2749 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2750 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2751 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2752 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2753 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2754 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2755 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2757 { "seto", { Eb
}, 0 },
2758 { "setno", { Eb
}, 0 },
2759 { "setb", { Eb
}, 0 },
2760 { "setae", { Eb
}, 0 },
2761 { "sete", { Eb
}, 0 },
2762 { "setne", { Eb
}, 0 },
2763 { "setbe", { Eb
}, 0 },
2764 { "seta", { Eb
}, 0 },
2766 { "sets", { Eb
}, 0 },
2767 { "setns", { Eb
}, 0 },
2768 { "setp", { Eb
}, 0 },
2769 { "setnp", { Eb
}, 0 },
2770 { "setl", { Eb
}, 0 },
2771 { "setge", { Eb
}, 0 },
2772 { "setle", { Eb
}, 0 },
2773 { "setg", { Eb
}, 0 },
2775 { "pushT", { fs
}, 0 },
2776 { "popT", { fs
}, 0 },
2777 { "cpuid", { XX
}, 0 },
2778 { "btS", { Ev
, Gv
}, 0 },
2779 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2780 { "shldS", { Ev
, Gv
, CL
}, 0 },
2781 { REG_TABLE (REG_0FA6
) },
2782 { REG_TABLE (REG_0FA7
) },
2784 { "pushT", { gs
}, 0 },
2785 { "popT", { gs
}, 0 },
2786 { "rsm", { XX
}, 0 },
2787 { "btsS", { Evh1
, Gv
}, 0 },
2788 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2789 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2790 { REG_TABLE (REG_0FAE
) },
2791 { "imulS", { Gv
, Ev
}, 0 },
2793 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2794 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2795 { MOD_TABLE (MOD_0FB2
) },
2796 { "btrS", { Evh1
, Gv
}, 0 },
2797 { MOD_TABLE (MOD_0FB4
) },
2798 { MOD_TABLE (MOD_0FB5
) },
2799 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2800 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2802 { PREFIX_TABLE (PREFIX_0FB8
) },
2803 { "ud1S", { Gv
, Ev
}, 0 },
2804 { REG_TABLE (REG_0FBA
) },
2805 { "btcS", { Evh1
, Gv
}, 0 },
2806 { PREFIX_TABLE (PREFIX_0FBC
) },
2807 { PREFIX_TABLE (PREFIX_0FBD
) },
2808 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2809 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2811 { "xaddB", { Ebh1
, Gb
}, 0 },
2812 { "xaddS", { Evh1
, Gv
}, 0 },
2813 { PREFIX_TABLE (PREFIX_0FC2
) },
2814 { MOD_TABLE (MOD_0FC3
) },
2815 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
2816 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
2817 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2818 { REG_TABLE (REG_0FC7
) },
2820 { "bswap", { RMeAX
}, 0 },
2821 { "bswap", { RMeCX
}, 0 },
2822 { "bswap", { RMeDX
}, 0 },
2823 { "bswap", { RMeBX
}, 0 },
2824 { "bswap", { RMeSP
}, 0 },
2825 { "bswap", { RMeBP
}, 0 },
2826 { "bswap", { RMeSI
}, 0 },
2827 { "bswap", { RMeDI
}, 0 },
2829 { PREFIX_TABLE (PREFIX_0FD0
) },
2830 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2831 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2832 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2833 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2834 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2835 { PREFIX_TABLE (PREFIX_0FD6
) },
2836 { MOD_TABLE (MOD_0FD7
) },
2838 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2839 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2840 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2841 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2842 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2843 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2844 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2845 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2847 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2848 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2849 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2850 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2851 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2852 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2853 { PREFIX_TABLE (PREFIX_0FE6
) },
2854 { PREFIX_TABLE (PREFIX_0FE7
) },
2856 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
2857 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
2858 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
2859 { "por", { MX
, EM
}, PREFIX_OPCODE
},
2860 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
2861 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
2862 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
2863 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
2865 { PREFIX_TABLE (PREFIX_0FF0
) },
2866 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
2867 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
2868 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
2869 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
2870 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
2871 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
2872 { PREFIX_TABLE (PREFIX_0FF7
) },
2874 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
2875 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
2876 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
2877 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
2878 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
2879 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
2880 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
2881 { "ud0S", { Gv
, Ev
}, 0 },
2884 static const unsigned char onebyte_has_modrm
[256] = {
2885 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2886 /* ------------------------------- */
2887 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2888 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2889 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2890 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2891 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2892 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2893 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2894 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2895 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2896 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2897 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2898 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2899 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2900 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2901 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2902 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2903 /* ------------------------------- */
2904 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2907 static const unsigned char twobyte_has_modrm
[256] = {
2908 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2909 /* ------------------------------- */
2910 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2911 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2912 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2913 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2914 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2915 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2916 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2917 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2918 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2919 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2920 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2921 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2922 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2923 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2924 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2925 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2926 /* ------------------------------- */
2927 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2930 static char obuf
[100];
2932 static char *mnemonicendp
;
2933 static char scratchbuf
[100];
2934 static unsigned char *start_codep
;
2935 static unsigned char *insn_codep
;
2936 static unsigned char *codep
;
2937 static unsigned char *end_codep
;
2938 static int last_lock_prefix
;
2939 static int last_repz_prefix
;
2940 static int last_repnz_prefix
;
2941 static int last_data_prefix
;
2942 static int last_addr_prefix
;
2943 static int last_rex_prefix
;
2944 static int last_seg_prefix
;
2945 static int fwait_prefix
;
2946 /* The active segment register prefix. */
2947 static int active_seg_prefix
;
2948 #define MAX_CODE_LENGTH 15
2949 /* We can up to 14 prefixes since the maximum instruction length is
2951 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
2952 static disassemble_info
*the_info
;
2960 static unsigned char need_modrm
;
2970 int register_specifier
;
2977 int mask_register_specifier
;
2983 static unsigned char need_vex
;
2984 static unsigned char need_vex_reg
;
2992 /* If we are accessing mod/rm/reg without need_modrm set, then the
2993 values are stale. Hitting this abort likely indicates that you
2994 need to update onebyte_has_modrm or twobyte_has_modrm. */
2995 #define MODRM_CHECK if (!need_modrm) abort ()
2997 static const char **names64
;
2998 static const char **names32
;
2999 static const char **names16
;
3000 static const char **names8
;
3001 static const char **names8rex
;
3002 static const char **names_seg
;
3003 static const char *index64
;
3004 static const char *index32
;
3005 static const char **index16
;
3006 static const char **names_bnd
;
3008 static const char *intel_names64
[] = {
3009 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3010 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3012 static const char *intel_names32
[] = {
3013 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3014 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3016 static const char *intel_names16
[] = {
3017 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3018 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3020 static const char *intel_names8
[] = {
3021 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3023 static const char *intel_names8rex
[] = {
3024 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3025 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3027 static const char *intel_names_seg
[] = {
3028 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3030 static const char *intel_index64
= "riz";
3031 static const char *intel_index32
= "eiz";
3032 static const char *intel_index16
[] = {
3033 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3036 static const char *att_names64
[] = {
3037 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3038 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3040 static const char *att_names32
[] = {
3041 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3042 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3044 static const char *att_names16
[] = {
3045 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3046 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3048 static const char *att_names8
[] = {
3049 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3051 static const char *att_names8rex
[] = {
3052 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3053 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3055 static const char *att_names_seg
[] = {
3056 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3058 static const char *att_index64
= "%riz";
3059 static const char *att_index32
= "%eiz";
3060 static const char *att_index16
[] = {
3061 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3064 static const char **names_mm
;
3065 static const char *intel_names_mm
[] = {
3066 "mm0", "mm1", "mm2", "mm3",
3067 "mm4", "mm5", "mm6", "mm7"
3069 static const char *att_names_mm
[] = {
3070 "%mm0", "%mm1", "%mm2", "%mm3",
3071 "%mm4", "%mm5", "%mm6", "%mm7"
3074 static const char *intel_names_bnd
[] = {
3075 "bnd0", "bnd1", "bnd2", "bnd3"
3078 static const char *att_names_bnd
[] = {
3079 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3082 static const char **names_xmm
;
3083 static const char *intel_names_xmm
[] = {
3084 "xmm0", "xmm1", "xmm2", "xmm3",
3085 "xmm4", "xmm5", "xmm6", "xmm7",
3086 "xmm8", "xmm9", "xmm10", "xmm11",
3087 "xmm12", "xmm13", "xmm14", "xmm15",
3088 "xmm16", "xmm17", "xmm18", "xmm19",
3089 "xmm20", "xmm21", "xmm22", "xmm23",
3090 "xmm24", "xmm25", "xmm26", "xmm27",
3091 "xmm28", "xmm29", "xmm30", "xmm31"
3093 static const char *att_names_xmm
[] = {
3094 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3095 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3096 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3097 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3098 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3099 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3100 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3101 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3104 static const char **names_ymm
;
3105 static const char *intel_names_ymm
[] = {
3106 "ymm0", "ymm1", "ymm2", "ymm3",
3107 "ymm4", "ymm5", "ymm6", "ymm7",
3108 "ymm8", "ymm9", "ymm10", "ymm11",
3109 "ymm12", "ymm13", "ymm14", "ymm15",
3110 "ymm16", "ymm17", "ymm18", "ymm19",
3111 "ymm20", "ymm21", "ymm22", "ymm23",
3112 "ymm24", "ymm25", "ymm26", "ymm27",
3113 "ymm28", "ymm29", "ymm30", "ymm31"
3115 static const char *att_names_ymm
[] = {
3116 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3117 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3118 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3119 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3120 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3121 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3122 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3123 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3126 static const char **names_zmm
;
3127 static const char *intel_names_zmm
[] = {
3128 "zmm0", "zmm1", "zmm2", "zmm3",
3129 "zmm4", "zmm5", "zmm6", "zmm7",
3130 "zmm8", "zmm9", "zmm10", "zmm11",
3131 "zmm12", "zmm13", "zmm14", "zmm15",
3132 "zmm16", "zmm17", "zmm18", "zmm19",
3133 "zmm20", "zmm21", "zmm22", "zmm23",
3134 "zmm24", "zmm25", "zmm26", "zmm27",
3135 "zmm28", "zmm29", "zmm30", "zmm31"
3137 static const char *att_names_zmm
[] = {
3138 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3139 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3140 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3141 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3142 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3143 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3144 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3145 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3148 static const char **names_tmm
;
3149 static const char *intel_names_tmm
[] = {
3150 "tmm0", "tmm1", "tmm2", "tmm3",
3151 "tmm4", "tmm5", "tmm6", "tmm7"
3153 static const char *att_names_tmm
[] = {
3154 "%tmm0", "%tmm1", "%tmm2", "%tmm3",
3155 "%tmm4", "%tmm5", "%tmm6", "%tmm7"
3158 static const char **names_mask
;
3159 static const char *intel_names_mask
[] = {
3160 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3162 static const char *att_names_mask
[] = {
3163 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3166 static const char *names_rounding
[] =
3174 static const struct dis386 reg_table
[][8] = {
3177 { "addA", { Ebh1
, Ib
}, 0 },
3178 { "orA", { Ebh1
, Ib
}, 0 },
3179 { "adcA", { Ebh1
, Ib
}, 0 },
3180 { "sbbA", { Ebh1
, Ib
}, 0 },
3181 { "andA", { Ebh1
, Ib
}, 0 },
3182 { "subA", { Ebh1
, Ib
}, 0 },
3183 { "xorA", { Ebh1
, Ib
}, 0 },
3184 { "cmpA", { Eb
, Ib
}, 0 },
3188 { "addQ", { Evh1
, Iv
}, 0 },
3189 { "orQ", { Evh1
, Iv
}, 0 },
3190 { "adcQ", { Evh1
, Iv
}, 0 },
3191 { "sbbQ", { Evh1
, Iv
}, 0 },
3192 { "andQ", { Evh1
, Iv
}, 0 },
3193 { "subQ", { Evh1
, Iv
}, 0 },
3194 { "xorQ", { Evh1
, Iv
}, 0 },
3195 { "cmpQ", { Ev
, Iv
}, 0 },
3199 { "addQ", { Evh1
, sIb
}, 0 },
3200 { "orQ", { Evh1
, sIb
}, 0 },
3201 { "adcQ", { Evh1
, sIb
}, 0 },
3202 { "sbbQ", { Evh1
, sIb
}, 0 },
3203 { "andQ", { Evh1
, sIb
}, 0 },
3204 { "subQ", { Evh1
, sIb
}, 0 },
3205 { "xorQ", { Evh1
, sIb
}, 0 },
3206 { "cmpQ", { Ev
, sIb
}, 0 },
3210 { "popU", { stackEv
}, 0 },
3211 { XOP_8F_TABLE (XOP_09
) },
3215 { XOP_8F_TABLE (XOP_09
) },
3219 { "rolA", { Eb
, Ib
}, 0 },
3220 { "rorA", { Eb
, Ib
}, 0 },
3221 { "rclA", { Eb
, Ib
}, 0 },
3222 { "rcrA", { Eb
, Ib
}, 0 },
3223 { "shlA", { Eb
, Ib
}, 0 },
3224 { "shrA", { Eb
, Ib
}, 0 },
3225 { "shlA", { Eb
, Ib
}, 0 },
3226 { "sarA", { Eb
, Ib
}, 0 },
3230 { "rolQ", { Ev
, Ib
}, 0 },
3231 { "rorQ", { Ev
, Ib
}, 0 },
3232 { "rclQ", { Ev
, Ib
}, 0 },
3233 { "rcrQ", { Ev
, Ib
}, 0 },
3234 { "shlQ", { Ev
, Ib
}, 0 },
3235 { "shrQ", { Ev
, Ib
}, 0 },
3236 { "shlQ", { Ev
, Ib
}, 0 },
3237 { "sarQ", { Ev
, Ib
}, 0 },
3241 { "movA", { Ebh3
, Ib
}, 0 },
3248 { MOD_TABLE (MOD_C6_REG_7
) },
3252 { "movQ", { Evh3
, Iv
}, 0 },
3259 { MOD_TABLE (MOD_C7_REG_7
) },
3263 { "rolA", { Eb
, I1
}, 0 },
3264 { "rorA", { Eb
, I1
}, 0 },
3265 { "rclA", { Eb
, I1
}, 0 },
3266 { "rcrA", { Eb
, I1
}, 0 },
3267 { "shlA", { Eb
, I1
}, 0 },
3268 { "shrA", { Eb
, I1
}, 0 },
3269 { "shlA", { Eb
, I1
}, 0 },
3270 { "sarA", { Eb
, I1
}, 0 },
3274 { "rolQ", { Ev
, I1
}, 0 },
3275 { "rorQ", { Ev
, I1
}, 0 },
3276 { "rclQ", { Ev
, I1
}, 0 },
3277 { "rcrQ", { Ev
, I1
}, 0 },
3278 { "shlQ", { Ev
, I1
}, 0 },
3279 { "shrQ", { Ev
, I1
}, 0 },
3280 { "shlQ", { Ev
, I1
}, 0 },
3281 { "sarQ", { Ev
, I1
}, 0 },
3285 { "rolA", { Eb
, CL
}, 0 },
3286 { "rorA", { Eb
, CL
}, 0 },
3287 { "rclA", { Eb
, CL
}, 0 },
3288 { "rcrA", { Eb
, CL
}, 0 },
3289 { "shlA", { Eb
, CL
}, 0 },
3290 { "shrA", { Eb
, CL
}, 0 },
3291 { "shlA", { Eb
, CL
}, 0 },
3292 { "sarA", { Eb
, CL
}, 0 },
3296 { "rolQ", { Ev
, CL
}, 0 },
3297 { "rorQ", { Ev
, CL
}, 0 },
3298 { "rclQ", { Ev
, CL
}, 0 },
3299 { "rcrQ", { Ev
, CL
}, 0 },
3300 { "shlQ", { Ev
, CL
}, 0 },
3301 { "shrQ", { Ev
, CL
}, 0 },
3302 { "shlQ", { Ev
, CL
}, 0 },
3303 { "sarQ", { Ev
, CL
}, 0 },
3307 { "testA", { Eb
, Ib
}, 0 },
3308 { "testA", { Eb
, Ib
}, 0 },
3309 { "notA", { Ebh1
}, 0 },
3310 { "negA", { Ebh1
}, 0 },
3311 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3312 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3313 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3314 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3318 { "testQ", { Ev
, Iv
}, 0 },
3319 { "testQ", { Ev
, Iv
}, 0 },
3320 { "notQ", { Evh1
}, 0 },
3321 { "negQ", { Evh1
}, 0 },
3322 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3323 { "imulQ", { Ev
}, 0 },
3324 { "divQ", { Ev
}, 0 },
3325 { "idivQ", { Ev
}, 0 },
3329 { "incA", { Ebh1
}, 0 },
3330 { "decA", { Ebh1
}, 0 },
3334 { "incQ", { Evh1
}, 0 },
3335 { "decQ", { Evh1
}, 0 },
3336 { "call{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3337 { MOD_TABLE (MOD_FF_REG_3
) },
3338 { "jmp{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3339 { MOD_TABLE (MOD_FF_REG_5
) },
3340 { "pushU", { stackEv
}, 0 },
3345 { "sldtD", { Sv
}, 0 },
3346 { "strD", { Sv
}, 0 },
3347 { "lldt", { Ew
}, 0 },
3348 { "ltr", { Ew
}, 0 },
3349 { "verr", { Ew
}, 0 },
3350 { "verw", { Ew
}, 0 },
3356 { MOD_TABLE (MOD_0F01_REG_0
) },
3357 { MOD_TABLE (MOD_0F01_REG_1
) },
3358 { MOD_TABLE (MOD_0F01_REG_2
) },
3359 { MOD_TABLE (MOD_0F01_REG_3
) },
3360 { "smswD", { Sv
}, 0 },
3361 { MOD_TABLE (MOD_0F01_REG_5
) },
3362 { "lmsw", { Ew
}, 0 },
3363 { MOD_TABLE (MOD_0F01_REG_7
) },
3367 { "prefetch", { Mb
}, 0 },
3368 { "prefetchw", { Mb
}, 0 },
3369 { "prefetchwt1", { Mb
}, 0 },
3370 { "prefetch", { Mb
}, 0 },
3371 { "prefetch", { Mb
}, 0 },
3372 { "prefetch", { Mb
}, 0 },
3373 { "prefetch", { Mb
}, 0 },
3374 { "prefetch", { Mb
}, 0 },
3378 { MOD_TABLE (MOD_0F18_REG_0
) },
3379 { MOD_TABLE (MOD_0F18_REG_1
) },
3380 { MOD_TABLE (MOD_0F18_REG_2
) },
3381 { MOD_TABLE (MOD_0F18_REG_3
) },
3382 { MOD_TABLE (MOD_0F18_REG_4
) },
3383 { MOD_TABLE (MOD_0F18_REG_5
) },
3384 { MOD_TABLE (MOD_0F18_REG_6
) },
3385 { MOD_TABLE (MOD_0F18_REG_7
) },
3387 /* REG_0F1C_P_0_MOD_0 */
3389 { "cldemote", { Mb
}, 0 },
3390 { "nopQ", { Ev
}, 0 },
3391 { "nopQ", { Ev
}, 0 },
3392 { "nopQ", { Ev
}, 0 },
3393 { "nopQ", { Ev
}, 0 },
3394 { "nopQ", { Ev
}, 0 },
3395 { "nopQ", { Ev
}, 0 },
3396 { "nopQ", { Ev
}, 0 },
3398 /* REG_0F1E_P_1_MOD_3 */
3400 { "nopQ", { Ev
}, 0 },
3401 { "rdsspK", { Rdq
}, PREFIX_OPCODE
},
3402 { "nopQ", { Ev
}, 0 },
3403 { "nopQ", { Ev
}, 0 },
3404 { "nopQ", { Ev
}, 0 },
3405 { "nopQ", { Ev
}, 0 },
3406 { "nopQ", { Ev
}, 0 },
3407 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7
) },
3413 { MOD_TABLE (MOD_0F71_REG_2
) },
3415 { MOD_TABLE (MOD_0F71_REG_4
) },
3417 { MOD_TABLE (MOD_0F71_REG_6
) },
3423 { MOD_TABLE (MOD_0F72_REG_2
) },
3425 { MOD_TABLE (MOD_0F72_REG_4
) },
3427 { MOD_TABLE (MOD_0F72_REG_6
) },
3433 { MOD_TABLE (MOD_0F73_REG_2
) },
3434 { MOD_TABLE (MOD_0F73_REG_3
) },
3437 { MOD_TABLE (MOD_0F73_REG_6
) },
3438 { MOD_TABLE (MOD_0F73_REG_7
) },
3442 { "montmul", { { OP_0f07
, 0 } }, 0 },
3443 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3444 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3448 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3449 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3450 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3451 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3452 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3453 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3457 { MOD_TABLE (MOD_0FAE_REG_0
) },
3458 { MOD_TABLE (MOD_0FAE_REG_1
) },
3459 { MOD_TABLE (MOD_0FAE_REG_2
) },
3460 { MOD_TABLE (MOD_0FAE_REG_3
) },
3461 { MOD_TABLE (MOD_0FAE_REG_4
) },
3462 { MOD_TABLE (MOD_0FAE_REG_5
) },
3463 { MOD_TABLE (MOD_0FAE_REG_6
) },
3464 { MOD_TABLE (MOD_0FAE_REG_7
) },
3472 { "btQ", { Ev
, Ib
}, 0 },
3473 { "btsQ", { Evh1
, Ib
}, 0 },
3474 { "btrQ", { Evh1
, Ib
}, 0 },
3475 { "btcQ", { Evh1
, Ib
}, 0 },
3480 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3482 { MOD_TABLE (MOD_0FC7_REG_3
) },
3483 { MOD_TABLE (MOD_0FC7_REG_4
) },
3484 { MOD_TABLE (MOD_0FC7_REG_5
) },
3485 { MOD_TABLE (MOD_0FC7_REG_6
) },
3486 { MOD_TABLE (MOD_0FC7_REG_7
) },
3492 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3494 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3496 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3502 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3504 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3506 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3512 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3513 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3516 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3517 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3523 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3524 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3526 /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
3528 { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
) },
3530 /* REG_VEX_0F38F3 */
3533 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3534 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3535 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3537 /* REG_0FXOP_09_01_L_0 */
3540 { "blcfill", { VexGdq
, Edq
}, 0 },
3541 { "blsfill", { VexGdq
, Edq
}, 0 },
3542 { "blcs", { VexGdq
, Edq
}, 0 },
3543 { "tzmsk", { VexGdq
, Edq
}, 0 },
3544 { "blcic", { VexGdq
, Edq
}, 0 },
3545 { "blsic", { VexGdq
, Edq
}, 0 },
3546 { "t1mskc", { VexGdq
, Edq
}, 0 },
3548 /* REG_0FXOP_09_02_L_0 */
3551 { "blcmsk", { VexGdq
, Edq
}, 0 },
3556 { "blci", { VexGdq
, Edq
}, 0 },
3558 /* REG_0FXOP_09_12_M_1_L_0 */
3560 { "llwpcb", { Edq
}, 0 },
3561 { "slwpcb", { Edq
}, 0 },
3563 /* REG_0FXOP_0A_12_L_0 */
3565 { "lwpins", { VexGdq
, Ed
, Id
}, 0 },
3566 { "lwpval", { VexGdq
, Ed
, Id
}, 0 },
3569 #include "i386-dis-evex-reg.h"
3572 static const struct dis386 prefix_table
[][4] = {
3575 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3576 { "pause", { XX
}, 0 },
3577 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3578 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3581 /* PREFIX_0F01_REG_3_RM_1 */
3583 { "vmmcall", { Skip_MODRM
}, 0 },
3584 { "vmgexit", { Skip_MODRM
}, 0 },
3586 { "vmgexit", { Skip_MODRM
}, 0 },
3589 /* PREFIX_0F01_REG_5_MOD_0 */
3592 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3595 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3597 { "serialize", { Skip_MODRM
}, PREFIX_OPCODE
},
3598 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3600 { "xsusldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3603 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3608 { "xresldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3611 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3614 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3617 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3619 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
3620 { "mcommit", { Skip_MODRM
}, 0 },
3623 /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3625 { "mwaitx", { { OP_Mwait
, eBX_reg
} }, 0 },
3630 { "wbinvd", { XX
}, 0 },
3631 { "wbnoinvd", { XX
}, 0 },
3636 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3637 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3638 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3639 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3644 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3645 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3646 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3647 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3652 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3653 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3654 { MOD_TABLE (MOD_0F12_PREFIX_2
) },
3655 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3660 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3661 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3662 { MOD_TABLE (MOD_0F16_PREFIX_2
) },
3667 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3668 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3669 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3670 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3675 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3676 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3677 { "bndmov", { EbndS
, Gbnd
}, 0 },
3678 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3683 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3684 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3685 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3686 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3691 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3692 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3693 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3694 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3699 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3700 { "cvtsi2ss{%LQ|}", { XM
, Edq
}, PREFIX_OPCODE
},
3701 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3702 { "cvtsi2sd{%LQ|}", { XM
, Edq
}, 0 },
3707 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3708 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3709 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3710 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3715 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3716 { "cvttss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3717 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3718 { "cvttsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3723 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3724 { "cvtss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3725 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3726 { "cvtsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3731 { "ucomiss",{ XM
, EXd
}, 0 },
3733 { "ucomisd",{ XM
, EXq
}, 0 },
3738 { "comiss", { XM
, EXd
}, 0 },
3740 { "comisd", { XM
, EXq
}, 0 },
3745 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3746 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3747 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3748 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3753 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3754 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3759 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3760 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3765 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3766 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3767 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3768 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3773 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3774 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3775 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3776 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3781 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3782 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3783 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3784 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3789 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3790 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3791 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3796 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3797 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3798 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3799 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3804 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3805 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3806 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3807 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3812 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3813 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3814 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3815 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3820 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3821 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3822 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3823 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3828 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3830 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3835 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3837 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3842 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3844 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3851 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3858 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3863 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3864 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3865 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3870 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3871 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3872 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3873 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3876 /* PREFIX_0F73_REG_3 */
3880 { "psrldq", { XS
, Ib
}, 0 },
3883 /* PREFIX_0F73_REG_7 */
3887 { "pslldq", { XS
, Ib
}, 0 },
3892 {"vmread", { Em
, Gm
}, 0 },
3894 {"extrq", { XS
, Ib
, Ib
}, 0 },
3895 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3900 {"vmwrite", { Gm
, Em
}, 0 },
3902 {"extrq", { XM
, XS
}, 0 },
3903 {"insertq", { XM
, XS
}, 0 },
3910 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3911 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3918 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3919 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3924 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3925 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3926 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3931 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3932 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3933 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3936 /* PREFIX_0FAE_REG_0_MOD_3 */
3939 { "rdfsbase", { Ev
}, 0 },
3942 /* PREFIX_0FAE_REG_1_MOD_3 */
3945 { "rdgsbase", { Ev
}, 0 },
3948 /* PREFIX_0FAE_REG_2_MOD_3 */
3951 { "wrfsbase", { Ev
}, 0 },
3954 /* PREFIX_0FAE_REG_3_MOD_3 */
3957 { "wrgsbase", { Ev
}, 0 },
3960 /* PREFIX_0FAE_REG_4_MOD_0 */
3962 { "xsave", { FXSAVE
}, 0 },
3963 { "ptwrite{%LQ|}", { Edq
}, 0 },
3966 /* PREFIX_0FAE_REG_4_MOD_3 */
3969 { "ptwrite{%LQ|}", { Edq
}, 0 },
3972 /* PREFIX_0FAE_REG_5_MOD_0 */
3974 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
3977 /* PREFIX_0FAE_REG_5_MOD_3 */
3979 { "lfence", { Skip_MODRM
}, 0 },
3980 { "incsspK", { Rdq
}, PREFIX_OPCODE
},
3983 /* PREFIX_0FAE_REG_6_MOD_0 */
3985 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
3986 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
3987 { "clwb", { Mb
}, PREFIX_OPCODE
},
3990 /* PREFIX_0FAE_REG_6_MOD_3 */
3992 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0
) },
3993 { "umonitor", { Eva
}, PREFIX_OPCODE
},
3994 { "tpause", { Edq
}, PREFIX_OPCODE
},
3995 { "umwait", { Edq
}, PREFIX_OPCODE
},
3998 /* PREFIX_0FAE_REG_7_MOD_0 */
4000 { "clflush", { Mb
}, 0 },
4002 { "clflushopt", { Mb
}, 0 },
4008 { "popcntS", { Gv
, Ev
}, 0 },
4013 { "bsfS", { Gv
, Ev
}, 0 },
4014 { "tzcntS", { Gv
, Ev
}, 0 },
4015 { "bsfS", { Gv
, Ev
}, 0 },
4020 { "bsrS", { Gv
, Ev
}, 0 },
4021 { "lzcntS", { Gv
, Ev
}, 0 },
4022 { "bsrS", { Gv
, Ev
}, 0 },
4027 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4028 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4029 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4030 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4033 /* PREFIX_0FC3_MOD_0 */
4035 { "movntiS", { Edq
, Gdq
}, PREFIX_OPCODE
},
4038 /* PREFIX_0FC7_REG_6_MOD_0 */
4040 { "vmptrld",{ Mq
}, 0 },
4041 { "vmxon", { Mq
}, 0 },
4042 { "vmclear",{ Mq
}, 0 },
4045 /* PREFIX_0FC7_REG_6_MOD_3 */
4047 { "rdrand", { Ev
}, 0 },
4049 { "rdrand", { Ev
}, 0 }
4052 /* PREFIX_0FC7_REG_7_MOD_3 */
4054 { "rdseed", { Ev
}, 0 },
4055 { "rdpid", { Em
}, 0 },
4056 { "rdseed", { Ev
}, 0 },
4063 { "addsubpd", { XM
, EXx
}, 0 },
4064 { "addsubps", { XM
, EXx
}, 0 },
4070 { "movq2dq",{ XM
, MS
}, 0 },
4071 { "movq", { EXqS
, XM
}, 0 },
4072 { "movdq2q",{ MX
, XS
}, 0 },
4078 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4079 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4080 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4085 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4087 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4095 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4100 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4102 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4109 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4116 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4123 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4130 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4137 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4144 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4151 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4158 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4165 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4172 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4179 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4186 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4193 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4200 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4207 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4214 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4221 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4228 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4235 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4242 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4249 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4256 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4263 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4270 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4277 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4284 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4291 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4298 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4305 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4312 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4319 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4326 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4333 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4340 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4345 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4350 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4355 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4360 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4365 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4370 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4377 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_OPCODE
},
4384 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4391 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4398 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4405 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4412 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4417 { "movbeS", { Gv
, Mv
}, PREFIX_OPCODE
},
4419 { "movbeS", { Gv
, Mv
}, PREFIX_OPCODE
},
4420 { "crc32A", { Gdq
, Eb
}, PREFIX_OPCODE
},
4425 { "movbeS", { Mv
, Gv
}, PREFIX_OPCODE
},
4427 { "movbeS", { Mv
, Gv
}, PREFIX_OPCODE
},
4428 { "crc32Q", { Gdq
, Ev
}, PREFIX_OPCODE
},
4435 { MOD_TABLE (MOD_0F38F5_PREFIX_2
) },
4440 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
4441 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4442 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4449 { MOD_TABLE (MOD_0F38F8_PREFIX_1
) },
4450 { MOD_TABLE (MOD_0F38F8_PREFIX_2
) },
4451 { MOD_TABLE (MOD_0F38F8_PREFIX_3
) },
4456 { MOD_TABLE (MOD_0F38F9_PREFIX_0
) },
4463 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4470 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4477 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4484 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4491 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4498 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4505 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4512 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4519 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4526 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4533 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4540 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4547 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4554 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4561 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4568 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4575 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4582 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4589 { "pcmpestrm!%LQ", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4596 { "pcmpestri!%LQ", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4603 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4610 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4615 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4622 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4629 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4636 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4639 /* PREFIX_VEX_0F10 */
4641 { "vmovups", { XM
, EXx
}, 0 },
4642 { "vmovss", { XMVexScalar
, VexScalar
, EXxmm_md
}, 0 },
4643 { "vmovupd", { XM
, EXx
}, 0 },
4644 { "vmovsd", { XMVexScalar
, VexScalar
, EXxmm_mq
}, 0 },
4647 /* PREFIX_VEX_0F11 */
4649 { "vmovups", { EXxS
, XM
}, 0 },
4650 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
4651 { "vmovupd", { EXxS
, XM
}, 0 },
4652 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
4655 /* PREFIX_VEX_0F12 */
4657 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4658 { "vmovsldup", { XM
, EXx
}, 0 },
4659 { MOD_TABLE (MOD_VEX_0F12_PREFIX_2
) },
4660 { "vmovddup", { XM
, EXymmq
}, 0 },
4663 /* PREFIX_VEX_0F16 */
4665 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4666 { "vmovshdup", { XM
, EXx
}, 0 },
4667 { MOD_TABLE (MOD_VEX_0F16_PREFIX_2
) },
4670 /* PREFIX_VEX_0F2A */
4673 { "vcvtsi2ss{%LQ|}", { XMScalar
, VexScalar
, Edq
}, 0 },
4675 { "vcvtsi2sd{%LQ|}", { XMScalar
, VexScalar
, Edq
}, 0 },
4678 /* PREFIX_VEX_0F2C */
4681 { "vcvttss2si", { Gdq
, EXxmm_md
}, 0 },
4683 { "vcvttsd2si", { Gdq
, EXxmm_mq
}, 0 },
4686 /* PREFIX_VEX_0F2D */
4689 { "vcvtss2si", { Gdq
, EXxmm_md
}, 0 },
4691 { "vcvtsd2si", { Gdq
, EXxmm_mq
}, 0 },
4694 /* PREFIX_VEX_0F2E */
4696 { "vucomiss", { XMScalar
, EXxmm_md
}, 0 },
4698 { "vucomisd", { XMScalar
, EXxmm_mq
}, 0 },
4701 /* PREFIX_VEX_0F2F */
4703 { "vcomiss", { XMScalar
, EXxmm_md
}, 0 },
4705 { "vcomisd", { XMScalar
, EXxmm_mq
}, 0 },
4708 /* PREFIX_VEX_0F41 */
4710 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4712 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4715 /* PREFIX_VEX_0F42 */
4717 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4719 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4722 /* PREFIX_VEX_0F44 */
4724 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4726 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4729 /* PREFIX_VEX_0F45 */
4731 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4733 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4736 /* PREFIX_VEX_0F46 */
4738 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4740 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4743 /* PREFIX_VEX_0F47 */
4745 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4747 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4750 /* PREFIX_VEX_0F4A */
4752 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4754 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4757 /* PREFIX_VEX_0F4B */
4759 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4761 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4764 /* PREFIX_VEX_0F51 */
4766 { "vsqrtps", { XM
, EXx
}, 0 },
4767 { "vsqrtss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4768 { "vsqrtpd", { XM
, EXx
}, 0 },
4769 { "vsqrtsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4772 /* PREFIX_VEX_0F52 */
4774 { "vrsqrtps", { XM
, EXx
}, 0 },
4775 { "vrsqrtss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4778 /* PREFIX_VEX_0F53 */
4780 { "vrcpps", { XM
, EXx
}, 0 },
4781 { "vrcpss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4784 /* PREFIX_VEX_0F58 */
4786 { "vaddps", { XM
, Vex
, EXx
}, 0 },
4787 { "vaddss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4788 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
4789 { "vaddsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4792 /* PREFIX_VEX_0F59 */
4794 { "vmulps", { XM
, Vex
, EXx
}, 0 },
4795 { "vmulss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4796 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
4797 { "vmulsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4800 /* PREFIX_VEX_0F5A */
4802 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
4803 { "vcvtss2sd", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4804 { "vcvtpd2ps%XY",{ XMM
, EXx
}, 0 },
4805 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4808 /* PREFIX_VEX_0F5B */
4810 { "vcvtdq2ps", { XM
, EXx
}, 0 },
4811 { "vcvttps2dq", { XM
, EXx
}, 0 },
4812 { "vcvtps2dq", { XM
, EXx
}, 0 },
4815 /* PREFIX_VEX_0F5C */
4817 { "vsubps", { XM
, Vex
, EXx
}, 0 },
4818 { "vsubss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4819 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
4820 { "vsubsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4823 /* PREFIX_VEX_0F5D */
4825 { "vminps", { XM
, Vex
, EXx
}, 0 },
4826 { "vminss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4827 { "vminpd", { XM
, Vex
, EXx
}, 0 },
4828 { "vminsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4831 /* PREFIX_VEX_0F5E */
4833 { "vdivps", { XM
, Vex
, EXx
}, 0 },
4834 { "vdivss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4835 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
4836 { "vdivsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4839 /* PREFIX_VEX_0F5F */
4841 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
4842 { "vmaxss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4843 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
4844 { "vmaxsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4847 /* PREFIX_VEX_0F60 */
4851 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
4854 /* PREFIX_VEX_0F61 */
4858 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
4861 /* PREFIX_VEX_0F62 */
4865 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
4868 /* PREFIX_VEX_0F63 */
4872 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
4875 /* PREFIX_VEX_0F64 */
4879 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
4882 /* PREFIX_VEX_0F65 */
4886 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
4889 /* PREFIX_VEX_0F66 */
4893 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
4896 /* PREFIX_VEX_0F67 */
4900 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
4903 /* PREFIX_VEX_0F68 */
4907 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
4910 /* PREFIX_VEX_0F69 */
4914 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
4917 /* PREFIX_VEX_0F6A */
4921 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
4924 /* PREFIX_VEX_0F6B */
4928 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
4931 /* PREFIX_VEX_0F6C */
4935 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
4938 /* PREFIX_VEX_0F6D */
4942 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
4945 /* PREFIX_VEX_0F6E */
4949 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4952 /* PREFIX_VEX_0F6F */
4955 { "vmovdqu", { XM
, EXx
}, 0 },
4956 { "vmovdqa", { XM
, EXx
}, 0 },
4959 /* PREFIX_VEX_0F70 */
4962 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
4963 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
4964 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
4967 /* PREFIX_VEX_0F71_REG_2 */
4971 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
4974 /* PREFIX_VEX_0F71_REG_4 */
4978 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
4981 /* PREFIX_VEX_0F71_REG_6 */
4985 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
4988 /* PREFIX_VEX_0F72_REG_2 */
4992 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
4995 /* PREFIX_VEX_0F72_REG_4 */
4999 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
5002 /* PREFIX_VEX_0F72_REG_6 */
5006 { "vpslld", { Vex
, XS
, Ib
}, 0 },
5009 /* PREFIX_VEX_0F73_REG_2 */
5013 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
5016 /* PREFIX_VEX_0F73_REG_3 */
5020 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
5023 /* PREFIX_VEX_0F73_REG_6 */
5027 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
5030 /* PREFIX_VEX_0F73_REG_7 */
5034 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
5037 /* PREFIX_VEX_0F74 */
5041 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
5044 /* PREFIX_VEX_0F75 */
5048 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
5051 /* PREFIX_VEX_0F76 */
5055 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
5058 /* PREFIX_VEX_0F77 */
5060 { VEX_LEN_TABLE (VEX_LEN_0F77_P_0
) },
5063 /* PREFIX_VEX_0F7C */
5067 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
5068 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
5071 /* PREFIX_VEX_0F7D */
5075 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
5076 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
5079 /* PREFIX_VEX_0F7E */
5082 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5083 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5086 /* PREFIX_VEX_0F7F */
5089 { "vmovdqu", { EXxS
, XM
}, 0 },
5090 { "vmovdqa", { EXxS
, XM
}, 0 },
5093 /* PREFIX_VEX_0F90 */
5095 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5097 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5100 /* PREFIX_VEX_0F91 */
5102 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5104 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5107 /* PREFIX_VEX_0F92 */
5109 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5111 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5112 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5115 /* PREFIX_VEX_0F93 */
5117 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5119 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5120 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5123 /* PREFIX_VEX_0F98 */
5125 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5127 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5130 /* PREFIX_VEX_0F99 */
5132 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5134 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5137 /* PREFIX_VEX_0FC2 */
5139 { "vcmpps", { XM
, Vex
, EXx
, CMP
}, 0 },
5140 { "vcmpss", { XMScalar
, VexScalar
, EXxmm_md
, CMP
}, 0 },
5141 { "vcmppd", { XM
, Vex
, EXx
, CMP
}, 0 },
5142 { "vcmpsd", { XMScalar
, VexScalar
, EXxmm_mq
, CMP
}, 0 },
5145 /* PREFIX_VEX_0FC4 */
5149 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5152 /* PREFIX_VEX_0FC5 */
5156 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5159 /* PREFIX_VEX_0FD0 */
5163 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
5164 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
5167 /* PREFIX_VEX_0FD1 */
5171 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
5174 /* PREFIX_VEX_0FD2 */
5178 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
5181 /* PREFIX_VEX_0FD3 */
5185 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
5188 /* PREFIX_VEX_0FD4 */
5192 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
5195 /* PREFIX_VEX_0FD5 */
5199 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
5202 /* PREFIX_VEX_0FD6 */
5206 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5209 /* PREFIX_VEX_0FD7 */
5213 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5216 /* PREFIX_VEX_0FD8 */
5220 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
5223 /* PREFIX_VEX_0FD9 */
5227 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
5230 /* PREFIX_VEX_0FDA */
5234 { "vpminub", { XM
, Vex
, EXx
}, 0 },
5237 /* PREFIX_VEX_0FDB */
5241 { "vpand", { XM
, Vex
, EXx
}, 0 },
5244 /* PREFIX_VEX_0FDC */
5248 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
5251 /* PREFIX_VEX_0FDD */
5255 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
5258 /* PREFIX_VEX_0FDE */
5262 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
5265 /* PREFIX_VEX_0FDF */
5269 { "vpandn", { XM
, Vex
, EXx
}, 0 },
5272 /* PREFIX_VEX_0FE0 */
5276 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
5279 /* PREFIX_VEX_0FE1 */
5283 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
5286 /* PREFIX_VEX_0FE2 */
5290 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
5293 /* PREFIX_VEX_0FE3 */
5297 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
5300 /* PREFIX_VEX_0FE4 */
5304 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
5307 /* PREFIX_VEX_0FE5 */
5311 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
5314 /* PREFIX_VEX_0FE6 */
5317 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
5318 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
5319 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
5322 /* PREFIX_VEX_0FE7 */
5326 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5329 /* PREFIX_VEX_0FE8 */
5333 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
5336 /* PREFIX_VEX_0FE9 */
5340 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
5343 /* PREFIX_VEX_0FEA */
5347 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
5350 /* PREFIX_VEX_0FEB */
5354 { "vpor", { XM
, Vex
, EXx
}, 0 },
5357 /* PREFIX_VEX_0FEC */
5361 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
5364 /* PREFIX_VEX_0FED */
5368 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
5371 /* PREFIX_VEX_0FEE */
5375 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
5378 /* PREFIX_VEX_0FEF */
5382 { "vpxor", { XM
, Vex
, EXx
}, 0 },
5385 /* PREFIX_VEX_0FF0 */
5390 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5393 /* PREFIX_VEX_0FF1 */
5397 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
5400 /* PREFIX_VEX_0FF2 */
5404 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
5407 /* PREFIX_VEX_0FF3 */
5411 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
5414 /* PREFIX_VEX_0FF4 */
5418 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
5421 /* PREFIX_VEX_0FF5 */
5425 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
5428 /* PREFIX_VEX_0FF6 */
5432 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
5435 /* PREFIX_VEX_0FF7 */
5439 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5442 /* PREFIX_VEX_0FF8 */
5446 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
5449 /* PREFIX_VEX_0FF9 */
5453 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
5456 /* PREFIX_VEX_0FFA */
5460 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
5463 /* PREFIX_VEX_0FFB */
5467 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
5470 /* PREFIX_VEX_0FFC */
5474 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
5477 /* PREFIX_VEX_0FFD */
5481 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
5484 /* PREFIX_VEX_0FFE */
5488 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
5491 /* PREFIX_VEX_0F3800 */
5495 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
5498 /* PREFIX_VEX_0F3801 */
5502 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
5505 /* PREFIX_VEX_0F3802 */
5509 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
5512 /* PREFIX_VEX_0F3803 */
5516 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
5519 /* PREFIX_VEX_0F3804 */
5523 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
5526 /* PREFIX_VEX_0F3805 */
5530 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
5533 /* PREFIX_VEX_0F3806 */
5537 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
5540 /* PREFIX_VEX_0F3807 */
5544 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
5547 /* PREFIX_VEX_0F3808 */
5551 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
5554 /* PREFIX_VEX_0F3809 */
5558 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
5561 /* PREFIX_VEX_0F380A */
5565 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
5568 /* PREFIX_VEX_0F380B */
5572 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
5575 /* PREFIX_VEX_0F380C */
5579 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5582 /* PREFIX_VEX_0F380D */
5586 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5589 /* PREFIX_VEX_0F380E */
5593 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5596 /* PREFIX_VEX_0F380F */
5600 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5603 /* PREFIX_VEX_0F3813 */
5607 { VEX_W_TABLE (VEX_W_0F3813_P_2
) },
5610 /* PREFIX_VEX_0F3816 */
5614 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5617 /* PREFIX_VEX_0F3817 */
5621 { "vptest", { XM
, EXx
}, 0 },
5624 /* PREFIX_VEX_0F3818 */
5628 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5631 /* PREFIX_VEX_0F3819 */
5635 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5638 /* PREFIX_VEX_0F381A */
5642 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5645 /* PREFIX_VEX_0F381C */
5649 { "vpabsb", { XM
, EXx
}, 0 },
5652 /* PREFIX_VEX_0F381D */
5656 { "vpabsw", { XM
, EXx
}, 0 },
5659 /* PREFIX_VEX_0F381E */
5663 { "vpabsd", { XM
, EXx
}, 0 },
5666 /* PREFIX_VEX_0F3820 */
5670 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
5673 /* PREFIX_VEX_0F3821 */
5677 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
5680 /* PREFIX_VEX_0F3822 */
5684 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
5687 /* PREFIX_VEX_0F3823 */
5691 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
5694 /* PREFIX_VEX_0F3824 */
5698 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
5701 /* PREFIX_VEX_0F3825 */
5705 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
5708 /* PREFIX_VEX_0F3828 */
5712 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
5715 /* PREFIX_VEX_0F3829 */
5719 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
5722 /* PREFIX_VEX_0F382A */
5726 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5729 /* PREFIX_VEX_0F382B */
5733 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
5736 /* PREFIX_VEX_0F382C */
5740 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5743 /* PREFIX_VEX_0F382D */
5747 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5750 /* PREFIX_VEX_0F382E */
5754 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5757 /* PREFIX_VEX_0F382F */
5761 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5764 /* PREFIX_VEX_0F3830 */
5768 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
5771 /* PREFIX_VEX_0F3831 */
5775 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
5778 /* PREFIX_VEX_0F3832 */
5782 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
5785 /* PREFIX_VEX_0F3833 */
5789 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
5792 /* PREFIX_VEX_0F3834 */
5796 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
5799 /* PREFIX_VEX_0F3835 */
5803 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
5806 /* PREFIX_VEX_0F3836 */
5810 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5813 /* PREFIX_VEX_0F3837 */
5817 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
5820 /* PREFIX_VEX_0F3838 */
5824 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
5827 /* PREFIX_VEX_0F3839 */
5831 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
5834 /* PREFIX_VEX_0F383A */
5838 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
5841 /* PREFIX_VEX_0F383B */
5845 { "vpminud", { XM
, Vex
, EXx
}, 0 },
5848 /* PREFIX_VEX_0F383C */
5852 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
5855 /* PREFIX_VEX_0F383D */
5859 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
5862 /* PREFIX_VEX_0F383E */
5866 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
5869 /* PREFIX_VEX_0F383F */
5873 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
5876 /* PREFIX_VEX_0F3840 */
5880 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
5883 /* PREFIX_VEX_0F3841 */
5887 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5890 /* PREFIX_VEX_0F3845 */
5894 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
5897 /* PREFIX_VEX_0F3846 */
5901 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5904 /* PREFIX_VEX_0F3847 */
5908 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
5911 /* PREFIX_VEX_0F3849_X86_64 */
5913 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0
) },
5915 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2
) },
5916 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3
) },
5919 /* PREFIX_VEX_0F384B_X86_64 */
5922 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1
) },
5923 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2
) },
5924 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3
) },
5927 /* PREFIX_VEX_0F3858 */
5931 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5934 /* PREFIX_VEX_0F3859 */
5938 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5941 /* PREFIX_VEX_0F385A */
5945 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5948 /* PREFIX_VEX_0F385C_X86_64 */
5951 { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1
) },
5955 /* PREFIX_VEX_0F385E_X86_64 */
5957 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0
) },
5958 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1
) },
5959 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2
) },
5960 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3
) },
5963 /* PREFIX_VEX_0F3878 */
5967 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5970 /* PREFIX_VEX_0F3879 */
5974 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5977 /* PREFIX_VEX_0F388C */
5981 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5984 /* PREFIX_VEX_0F388E */
5988 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
5991 /* PREFIX_VEX_0F3890 */
5995 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5998 /* PREFIX_VEX_0F3891 */
6002 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6005 /* PREFIX_VEX_0F3892 */
6009 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6012 /* PREFIX_VEX_0F3893 */
6016 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6019 /* PREFIX_VEX_0F3896 */
6023 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6026 /* PREFIX_VEX_0F3897 */
6030 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6033 /* PREFIX_VEX_0F3898 */
6037 { "vfmadd132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6040 /* PREFIX_VEX_0F3899 */
6044 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6047 /* PREFIX_VEX_0F389A */
6051 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6054 /* PREFIX_VEX_0F389B */
6058 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6061 /* PREFIX_VEX_0F389C */
6065 { "vfnmadd132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6068 /* PREFIX_VEX_0F389D */
6072 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6075 /* PREFIX_VEX_0F389E */
6079 { "vfnmsub132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6082 /* PREFIX_VEX_0F389F */
6086 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6089 /* PREFIX_VEX_0F38A6 */
6093 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6097 /* PREFIX_VEX_0F38A7 */
6101 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6104 /* PREFIX_VEX_0F38A8 */
6108 { "vfmadd213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6111 /* PREFIX_VEX_0F38A9 */
6115 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6118 /* PREFIX_VEX_0F38AA */
6122 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6125 /* PREFIX_VEX_0F38AB */
6129 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6132 /* PREFIX_VEX_0F38AC */
6136 { "vfnmadd213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6139 /* PREFIX_VEX_0F38AD */
6143 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6146 /* PREFIX_VEX_0F38AE */
6150 { "vfnmsub213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6153 /* PREFIX_VEX_0F38AF */
6157 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6160 /* PREFIX_VEX_0F38B6 */
6164 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6167 /* PREFIX_VEX_0F38B7 */
6171 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6174 /* PREFIX_VEX_0F38B8 */
6178 { "vfmadd231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6181 /* PREFIX_VEX_0F38B9 */
6185 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6188 /* PREFIX_VEX_0F38BA */
6192 { "vfmsub231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6195 /* PREFIX_VEX_0F38BB */
6199 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6202 /* PREFIX_VEX_0F38BC */
6206 { "vfnmadd231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6209 /* PREFIX_VEX_0F38BD */
6213 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6216 /* PREFIX_VEX_0F38BE */
6220 { "vfnmsub231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6223 /* PREFIX_VEX_0F38BF */
6227 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6230 /* PREFIX_VEX_0F38CF */
6234 { VEX_W_TABLE (VEX_W_0F38CF_P_2
) },
6237 /* PREFIX_VEX_0F38DB */
6241 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6244 /* PREFIX_VEX_0F38DC */
6248 { "vaesenc", { XM
, Vex
, EXx
}, 0 },
6251 /* PREFIX_VEX_0F38DD */
6255 { "vaesenclast", { XM
, Vex
, EXx
}, 0 },
6258 /* PREFIX_VEX_0F38DE */
6262 { "vaesdec", { XM
, Vex
, EXx
}, 0 },
6265 /* PREFIX_VEX_0F38DF */
6269 { "vaesdeclast", { XM
, Vex
, EXx
}, 0 },
6272 /* PREFIX_VEX_0F38F2 */
6274 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6277 /* PREFIX_VEX_0F38F3_REG_1 */
6279 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6282 /* PREFIX_VEX_0F38F3_REG_2 */
6284 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6287 /* PREFIX_VEX_0F38F3_REG_3 */
6289 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6292 /* PREFIX_VEX_0F38F5 */
6294 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6295 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6297 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6300 /* PREFIX_VEX_0F38F6 */
6305 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6308 /* PREFIX_VEX_0F38F7 */
6310 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6311 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6312 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6313 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6316 /* PREFIX_VEX_0F3A00 */
6320 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6323 /* PREFIX_VEX_0F3A01 */
6327 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6330 /* PREFIX_VEX_0F3A02 */
6334 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6337 /* PREFIX_VEX_0F3A04 */
6341 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6344 /* PREFIX_VEX_0F3A05 */
6348 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6351 /* PREFIX_VEX_0F3A06 */
6355 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6358 /* PREFIX_VEX_0F3A08 */
6362 { "vroundps", { XM
, EXx
, Ib
}, 0 },
6365 /* PREFIX_VEX_0F3A09 */
6369 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
6372 /* PREFIX_VEX_0F3A0A */
6376 { "vroundss", { XMScalar
, VexScalar
, EXxmm_md
, Ib
}, 0 },
6379 /* PREFIX_VEX_0F3A0B */
6383 { "vroundsd", { XMScalar
, VexScalar
, EXxmm_mq
, Ib
}, 0 },
6386 /* PREFIX_VEX_0F3A0C */
6390 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
6393 /* PREFIX_VEX_0F3A0D */
6397 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
6400 /* PREFIX_VEX_0F3A0E */
6404 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
6407 /* PREFIX_VEX_0F3A0F */
6411 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
6414 /* PREFIX_VEX_0F3A14 */
6418 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6421 /* PREFIX_VEX_0F3A15 */
6425 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6428 /* PREFIX_VEX_0F3A16 */
6432 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6435 /* PREFIX_VEX_0F3A17 */
6439 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6442 /* PREFIX_VEX_0F3A18 */
6446 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6449 /* PREFIX_VEX_0F3A19 */
6453 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6456 /* PREFIX_VEX_0F3A1D */
6460 { VEX_W_TABLE (VEX_W_0F3A1D_P_2
) },
6463 /* PREFIX_VEX_0F3A20 */
6467 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6470 /* PREFIX_VEX_0F3A21 */
6474 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6477 /* PREFIX_VEX_0F3A22 */
6481 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6484 /* PREFIX_VEX_0F3A30 */
6488 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6491 /* PREFIX_VEX_0F3A31 */
6495 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6498 /* PREFIX_VEX_0F3A32 */
6502 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6505 /* PREFIX_VEX_0F3A33 */
6509 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6512 /* PREFIX_VEX_0F3A38 */
6516 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6519 /* PREFIX_VEX_0F3A39 */
6523 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6526 /* PREFIX_VEX_0F3A40 */
6530 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
6533 /* PREFIX_VEX_0F3A41 */
6537 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6540 /* PREFIX_VEX_0F3A42 */
6544 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
6547 /* PREFIX_VEX_0F3A44 */
6551 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, 0 },
6554 /* PREFIX_VEX_0F3A46 */
6558 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6561 /* PREFIX_VEX_0F3A48 */
6565 { "vpermil2ps", { XM
, Vex
, EXx
, XMVexI4
, VexI4
}, 0 },
6568 /* PREFIX_VEX_0F3A49 */
6572 { "vpermil2pd", { XM
, Vex
, EXx
, XMVexI4
, VexI4
}, 0 },
6575 /* PREFIX_VEX_0F3A4A */
6579 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6582 /* PREFIX_VEX_0F3A4B */
6586 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6589 /* PREFIX_VEX_0F3A4C */
6593 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6596 /* PREFIX_VEX_0F3A5C */
6600 { "vfmaddsubps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6603 /* PREFIX_VEX_0F3A5D */
6607 { "vfmaddsubpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6610 /* PREFIX_VEX_0F3A5E */
6614 { "vfmsubaddps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6617 /* PREFIX_VEX_0F3A5F */
6621 { "vfmsubaddpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6624 /* PREFIX_VEX_0F3A60 */
6628 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6632 /* PREFIX_VEX_0F3A61 */
6636 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6639 /* PREFIX_VEX_0F3A62 */
6643 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6646 /* PREFIX_VEX_0F3A63 */
6650 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6653 /* PREFIX_VEX_0F3A68 */
6657 { "vfmaddps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6660 /* PREFIX_VEX_0F3A69 */
6664 { "vfmaddpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6667 /* PREFIX_VEX_0F3A6A */
6671 { "vfmaddss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, 0 },
6674 /* PREFIX_VEX_0F3A6B */
6678 { "vfmaddsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, 0 },
6681 /* PREFIX_VEX_0F3A6C */
6685 { "vfmsubps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6688 /* PREFIX_VEX_0F3A6D */
6692 { "vfmsubpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6695 /* PREFIX_VEX_0F3A6E */
6699 { "vfmsubss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, 0 },
6702 /* PREFIX_VEX_0F3A6F */
6706 { "vfmsubsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, 0 },
6709 /* PREFIX_VEX_0F3A78 */
6713 { "vfnmaddps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6716 /* PREFIX_VEX_0F3A79 */
6720 { "vfnmaddpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6723 /* PREFIX_VEX_0F3A7A */
6727 { "vfnmaddss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, 0 },
6730 /* PREFIX_VEX_0F3A7B */
6734 { "vfnmaddsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, 0 },
6737 /* PREFIX_VEX_0F3A7C */
6741 { "vfnmsubps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6745 /* PREFIX_VEX_0F3A7D */
6749 { "vfnmsubpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6752 /* PREFIX_VEX_0F3A7E */
6756 { "vfnmsubss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, 0 },
6759 /* PREFIX_VEX_0F3A7F */
6763 { "vfnmsubsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, 0 },
6766 /* PREFIX_VEX_0F3ACE */
6770 { VEX_W_TABLE (VEX_W_0F3ACE_P_2
) },
6773 /* PREFIX_VEX_0F3ACF */
6777 { VEX_W_TABLE (VEX_W_0F3ACF_P_2
) },
6780 /* PREFIX_VEX_0F3ADF */
6784 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6787 /* PREFIX_VEX_0F3AF0 */
6792 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6795 #include "i386-dis-evex-prefix.h"
6798 static const struct dis386 x86_64_table
[][2] = {
6801 { "pushP", { es
}, 0 },
6806 { "popP", { es
}, 0 },
6811 { "pushP", { cs
}, 0 },
6816 { "pushP", { ss
}, 0 },
6821 { "popP", { ss
}, 0 },
6826 { "pushP", { ds
}, 0 },
6831 { "popP", { ds
}, 0 },
6836 { "daa", { XX
}, 0 },
6841 { "das", { XX
}, 0 },
6846 { "aaa", { XX
}, 0 },
6851 { "aas", { XX
}, 0 },
6856 { "pushaP", { XX
}, 0 },
6861 { "popaP", { XX
}, 0 },
6866 { MOD_TABLE (MOD_62_32BIT
) },
6867 { EVEX_TABLE (EVEX_0F
) },
6872 { "arpl", { Ew
, Gw
}, 0 },
6873 { "movs", { { OP_G
, movsxd_mode
}, { MOVSXD_Fixup
, movsxd_mode
} }, 0 },
6878 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6879 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6884 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6885 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6890 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
6891 { REG_TABLE (REG_80
) },
6896 { "{l|}call{T|}", { Ap
}, 0 },
6901 { "retP", { Iw
, BND
}, 0 },
6902 { "ret@", { Iw
, BND
}, 0 },
6907 { "retP", { BND
}, 0 },
6908 { "ret@", { BND
}, 0 },
6913 { MOD_TABLE (MOD_C4_32BIT
) },
6914 { VEX_C4_TABLE (VEX_0F
) },
6919 { MOD_TABLE (MOD_C5_32BIT
) },
6920 { VEX_C5_TABLE (VEX_0F
) },
6925 { "into", { XX
}, 0 },
6930 { "aam", { Ib
}, 0 },
6935 { "aad", { Ib
}, 0 },
6940 { "callP", { Jv
, BND
}, 0 },
6941 { "call@", { Jv
, BND
}, 0 }
6946 { "jmpP", { Jv
, BND
}, 0 },
6947 { "jmp@", { Jv
, BND
}, 0 }
6952 { "{l|}jmp{T|}", { Ap
}, 0 },
6955 /* X86_64_0F01_REG_0 */
6957 { "sgdt{Q|Q}", { M
}, 0 },
6958 { "sgdt", { M
}, 0 },
6961 /* X86_64_0F01_REG_1 */
6963 { "sidt{Q|Q}", { M
}, 0 },
6964 { "sidt", { M
}, 0 },
6967 /* X86_64_0F01_REG_2 */
6969 { "lgdt{Q|Q}", { M
}, 0 },
6970 { "lgdt", { M
}, 0 },
6973 /* X86_64_0F01_REG_3 */
6975 { "lidt{Q|Q}", { M
}, 0 },
6976 { "lidt", { M
}, 0 },
6979 /* X86_64_VEX_0F3849 */
6982 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64
) },
6985 /* X86_64_VEX_0F384B */
6988 { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64
) },
6991 /* X86_64_VEX_0F385C */
6994 { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64
) },
6997 /* X86_64_VEX_0F385E */
7000 { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64
) },
7004 static const struct dis386 three_byte_table
[][256] = {
7006 /* THREE_BYTE_0F38 */
7009 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
7010 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
7011 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
7012 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
7013 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
7014 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
7015 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
7016 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
7018 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
7019 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
7020 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
7021 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
7027 { PREFIX_TABLE (PREFIX_0F3810
) },
7031 { PREFIX_TABLE (PREFIX_0F3814
) },
7032 { PREFIX_TABLE (PREFIX_0F3815
) },
7034 { PREFIX_TABLE (PREFIX_0F3817
) },
7040 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
7041 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
7042 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
7045 { PREFIX_TABLE (PREFIX_0F3820
) },
7046 { PREFIX_TABLE (PREFIX_0F3821
) },
7047 { PREFIX_TABLE (PREFIX_0F3822
) },
7048 { PREFIX_TABLE (PREFIX_0F3823
) },
7049 { PREFIX_TABLE (PREFIX_0F3824
) },
7050 { PREFIX_TABLE (PREFIX_0F3825
) },
7054 { PREFIX_TABLE (PREFIX_0F3828
) },
7055 { PREFIX_TABLE (PREFIX_0F3829
) },
7056 { PREFIX_TABLE (PREFIX_0F382A
) },
7057 { PREFIX_TABLE (PREFIX_0F382B
) },
7063 { PREFIX_TABLE (PREFIX_0F3830
) },
7064 { PREFIX_TABLE (PREFIX_0F3831
) },
7065 { PREFIX_TABLE (PREFIX_0F3832
) },
7066 { PREFIX_TABLE (PREFIX_0F3833
) },
7067 { PREFIX_TABLE (PREFIX_0F3834
) },
7068 { PREFIX_TABLE (PREFIX_0F3835
) },
7070 { PREFIX_TABLE (PREFIX_0F3837
) },
7072 { PREFIX_TABLE (PREFIX_0F3838
) },
7073 { PREFIX_TABLE (PREFIX_0F3839
) },
7074 { PREFIX_TABLE (PREFIX_0F383A
) },
7075 { PREFIX_TABLE (PREFIX_0F383B
) },
7076 { PREFIX_TABLE (PREFIX_0F383C
) },
7077 { PREFIX_TABLE (PREFIX_0F383D
) },
7078 { PREFIX_TABLE (PREFIX_0F383E
) },
7079 { PREFIX_TABLE (PREFIX_0F383F
) },
7081 { PREFIX_TABLE (PREFIX_0F3840
) },
7082 { PREFIX_TABLE (PREFIX_0F3841
) },
7153 { PREFIX_TABLE (PREFIX_0F3880
) },
7154 { PREFIX_TABLE (PREFIX_0F3881
) },
7155 { PREFIX_TABLE (PREFIX_0F3882
) },
7234 { PREFIX_TABLE (PREFIX_0F38C8
) },
7235 { PREFIX_TABLE (PREFIX_0F38C9
) },
7236 { PREFIX_TABLE (PREFIX_0F38CA
) },
7237 { PREFIX_TABLE (PREFIX_0F38CB
) },
7238 { PREFIX_TABLE (PREFIX_0F38CC
) },
7239 { PREFIX_TABLE (PREFIX_0F38CD
) },
7241 { PREFIX_TABLE (PREFIX_0F38CF
) },
7255 { PREFIX_TABLE (PREFIX_0F38DB
) },
7256 { PREFIX_TABLE (PREFIX_0F38DC
) },
7257 { PREFIX_TABLE (PREFIX_0F38DD
) },
7258 { PREFIX_TABLE (PREFIX_0F38DE
) },
7259 { PREFIX_TABLE (PREFIX_0F38DF
) },
7279 { PREFIX_TABLE (PREFIX_0F38F0
) },
7280 { PREFIX_TABLE (PREFIX_0F38F1
) },
7284 { PREFIX_TABLE (PREFIX_0F38F5
) },
7285 { PREFIX_TABLE (PREFIX_0F38F6
) },
7288 { PREFIX_TABLE (PREFIX_0F38F8
) },
7289 { PREFIX_TABLE (PREFIX_0F38F9
) },
7297 /* THREE_BYTE_0F3A */
7309 { PREFIX_TABLE (PREFIX_0F3A08
) },
7310 { PREFIX_TABLE (PREFIX_0F3A09
) },
7311 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7312 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7313 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7314 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7315 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7316 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7322 { PREFIX_TABLE (PREFIX_0F3A14
) },
7323 { PREFIX_TABLE (PREFIX_0F3A15
) },
7324 { PREFIX_TABLE (PREFIX_0F3A16
) },
7325 { PREFIX_TABLE (PREFIX_0F3A17
) },
7336 { PREFIX_TABLE (PREFIX_0F3A20
) },
7337 { PREFIX_TABLE (PREFIX_0F3A21
) },
7338 { PREFIX_TABLE (PREFIX_0F3A22
) },
7372 { PREFIX_TABLE (PREFIX_0F3A40
) },
7373 { PREFIX_TABLE (PREFIX_0F3A41
) },
7374 { PREFIX_TABLE (PREFIX_0F3A42
) },
7376 { PREFIX_TABLE (PREFIX_0F3A44
) },
7408 { PREFIX_TABLE (PREFIX_0F3A60
) },
7409 { PREFIX_TABLE (PREFIX_0F3A61
) },
7410 { PREFIX_TABLE (PREFIX_0F3A62
) },
7411 { PREFIX_TABLE (PREFIX_0F3A63
) },
7529 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7531 { PREFIX_TABLE (PREFIX_0F3ACE
) },
7532 { PREFIX_TABLE (PREFIX_0F3ACF
) },
7550 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7590 static const struct dis386 xop_table
[][256] = {
7743 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85
) },
7744 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86
) },
7745 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87
) },
7753 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E
) },
7754 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F
) },
7761 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95
) },
7762 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96
) },
7763 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97
) },
7771 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E
) },
7772 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F
) },
7776 { "vpcmov", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7777 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3
) },
7780 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6
) },
7798 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6
) },
7810 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0
) },
7811 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1
) },
7812 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2
) },
7813 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3
) },
7823 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7824 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7825 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7826 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7859 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7860 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7861 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7862 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
7886 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01
) },
7887 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02
) },
7905 { MOD_TABLE (MOD_VEX_0FXOP_09_12
) },
8029 { VEX_W_TABLE (VEX_W_0FXOP_09_80
) },
8030 { VEX_W_TABLE (VEX_W_0FXOP_09_81
) },
8031 { VEX_W_TABLE (VEX_W_0FXOP_09_82
) },
8032 { VEX_W_TABLE (VEX_W_0FXOP_09_83
) },
8047 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90
) },
8048 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91
) },
8049 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92
) },
8050 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93
) },
8051 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94
) },
8052 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95
) },
8053 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96
) },
8054 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97
) },
8056 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98
) },
8057 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99
) },
8058 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A
) },
8059 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B
) },
8102 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1
) },
8103 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2
) },
8104 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3
) },
8107 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6
) },
8108 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7
) },
8113 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB
) },
8120 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1
) },
8121 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2
) },
8122 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3
) },
8125 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6
) },
8126 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7
) },
8131 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB
) },
8138 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1
) },
8139 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2
) },
8140 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3
) },
8194 { "bextrS", { Gdq
, Edq
, Id
}, 0 },
8196 { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12
) },
8466 static const struct dis386 vex_table
[][256] = {
8488 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8489 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8490 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8491 { MOD_TABLE (MOD_VEX_0F13
) },
8492 { "vunpcklpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8493 { "vunpckhpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8494 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8495 { MOD_TABLE (MOD_VEX_0F17
) },
8515 { "vmovapX", { XM
, EXx
}, PREFIX_OPCODE
},
8516 { "vmovapX", { EXxS
, XM
}, PREFIX_OPCODE
},
8517 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8518 { MOD_TABLE (MOD_VEX_0F2B
) },
8519 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8520 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8521 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8522 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8543 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8544 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8546 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8547 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8548 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8549 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8553 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8554 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8560 { MOD_TABLE (MOD_VEX_0F50
) },
8561 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8562 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8563 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8564 { "vandpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8565 { "vandnpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8566 { "vorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8567 { "vxorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8569 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8570 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8571 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8572 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8573 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8574 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8575 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8576 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8578 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8579 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8580 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8581 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8582 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8583 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8584 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8585 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8587 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8588 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8589 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8590 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8591 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8592 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8593 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8594 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8596 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8597 { REG_TABLE (REG_VEX_0F71
) },
8598 { REG_TABLE (REG_VEX_0F72
) },
8599 { REG_TABLE (REG_VEX_0F73
) },
8600 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8601 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8602 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8603 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8609 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8610 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8611 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8612 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8632 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8633 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8634 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8635 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8641 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8642 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8665 { REG_TABLE (REG_VEX_0FAE
) },
8688 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8690 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8691 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8692 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, PREFIX_OPCODE
},
8704 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8705 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8706 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8707 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8708 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8709 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8710 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8711 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8713 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8714 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8715 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8716 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8717 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8718 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8719 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8720 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8722 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8723 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8724 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8725 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8726 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8727 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8728 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8729 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8731 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8732 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8733 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8734 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8735 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8736 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8737 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8738 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8740 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8741 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8742 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8743 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8744 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8745 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8746 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8747 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8749 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8750 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8751 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8752 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8753 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8754 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8755 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8762 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8763 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8764 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8765 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8766 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8767 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8768 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8770 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8771 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8774 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8775 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8776 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8777 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8782 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8785 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8786 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8788 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8789 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8790 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8792 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8793 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8794 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8797 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8798 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8799 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8800 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8801 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8802 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8806 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8807 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8808 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8809 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8810 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8811 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8812 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8813 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8815 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8816 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8817 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8818 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8819 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8820 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8821 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8822 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8824 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8825 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8826 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8827 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8828 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8829 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8830 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8831 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8833 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8834 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8838 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8839 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8840 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8843 { X86_64_TABLE (X86_64_VEX_0F3849
) },
8845 { X86_64_TABLE (X86_64_VEX_0F384B
) },
8860 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8861 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8862 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
8864 { X86_64_TABLE (X86_64_VEX_0F385C
) },
8866 { X86_64_TABLE (X86_64_VEX_0F385E
) },
8896 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
8897 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
8918 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
8920 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
8923 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
8924 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
8925 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
8926 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
8929 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
8930 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
8932 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
8934 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
8935 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
8936 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
8939 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
8947 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
8948 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
8950 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
8951 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
8952 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
8953 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
8954 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
8955 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
8956 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
8957 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
8965 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
8966 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
8968 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
8969 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
8970 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
8971 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
8972 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
8973 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
8974 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
8975 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
8993 { PREFIX_TABLE (PREFIX_VEX_0F38CF
) },
9007 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
9008 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
9009 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
9010 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
9011 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
9033 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
9034 { REG_TABLE (REG_VEX_0F38F3
) },
9036 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
9037 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
9038 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
9052 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
9053 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
9054 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
9056 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
9057 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
9058 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
9061 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
9062 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9063 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9064 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9065 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9066 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9067 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9068 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9074 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9075 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9076 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9077 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9079 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9080 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9084 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9088 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9089 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9090 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9106 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9107 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9108 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9109 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9115 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9116 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9124 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9125 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9126 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9128 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9130 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9133 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9134 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9135 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9136 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9137 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9155 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9156 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9157 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9158 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9160 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9161 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9162 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9163 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9169 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9170 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9171 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9172 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9173 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9174 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9175 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9176 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9187 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9188 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9189 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9190 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9191 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9192 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9193 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9194 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9283 { PREFIX_TABLE(PREFIX_VEX_0F3ACE
) },
9284 { PREFIX_TABLE(PREFIX_VEX_0F3ACF
) },
9302 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9322 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9342 #include "i386-dis-evex.h"
9344 static const struct dis386 vex_len_table
[][2] = {
9345 /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
9347 { "vmovlpX", { XM
, Vex128
, EXq
}, 0 },
9350 /* VEX_LEN_0F12_P_0_M_1 */
9352 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
9355 /* VEX_LEN_0F13_M_0 */
9357 { "vmovlpX", { EXq
, XM
}, PREFIX_OPCODE
},
9360 /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
9362 { "vmovhpX", { XM
, Vex128
, EXq
}, 0 },
9365 /* VEX_LEN_0F16_P_0_M_1 */
9367 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
9370 /* VEX_LEN_0F17_M_0 */
9372 { "vmovhpX", { EXq
, XM
}, PREFIX_OPCODE
},
9375 /* VEX_LEN_0F41_P_0 */
9378 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9380 /* VEX_LEN_0F41_P_2 */
9383 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9385 /* VEX_LEN_0F42_P_0 */
9388 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9390 /* VEX_LEN_0F42_P_2 */
9393 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9395 /* VEX_LEN_0F44_P_0 */
9397 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9399 /* VEX_LEN_0F44_P_2 */
9401 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9403 /* VEX_LEN_0F45_P_0 */
9406 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9408 /* VEX_LEN_0F45_P_2 */
9411 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9413 /* VEX_LEN_0F46_P_0 */
9416 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9418 /* VEX_LEN_0F46_P_2 */
9421 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9423 /* VEX_LEN_0F47_P_0 */
9426 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9428 /* VEX_LEN_0F47_P_2 */
9431 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9433 /* VEX_LEN_0F4A_P_0 */
9436 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9438 /* VEX_LEN_0F4A_P_2 */
9441 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9443 /* VEX_LEN_0F4B_P_0 */
9446 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9448 /* VEX_LEN_0F4B_P_2 */
9451 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9454 /* VEX_LEN_0F6E_P_2 */
9456 { "vmovK", { XMScalar
, Edq
}, 0 },
9459 /* VEX_LEN_0F77_P_1 */
9461 { "vzeroupper", { XX
}, 0 },
9462 { "vzeroall", { XX
}, 0 },
9465 /* VEX_LEN_0F7E_P_1 */
9467 { "vmovq", { XMScalar
, EXxmm_mq
}, 0 },
9470 /* VEX_LEN_0F7E_P_2 */
9472 { "vmovK", { Edq
, XMScalar
}, 0 },
9475 /* VEX_LEN_0F90_P_0 */
9477 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9480 /* VEX_LEN_0F90_P_2 */
9482 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9485 /* VEX_LEN_0F91_P_0 */
9487 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9490 /* VEX_LEN_0F91_P_2 */
9492 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9495 /* VEX_LEN_0F92_P_0 */
9497 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9500 /* VEX_LEN_0F92_P_2 */
9502 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9505 /* VEX_LEN_0F92_P_3 */
9507 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0
) },
9510 /* VEX_LEN_0F93_P_0 */
9512 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9515 /* VEX_LEN_0F93_P_2 */
9517 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9520 /* VEX_LEN_0F93_P_3 */
9522 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0
) },
9525 /* VEX_LEN_0F98_P_0 */
9527 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9530 /* VEX_LEN_0F98_P_2 */
9532 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9535 /* VEX_LEN_0F99_P_0 */
9537 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9540 /* VEX_LEN_0F99_P_2 */
9542 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9545 /* VEX_LEN_0FAE_R_2_M_0 */
9547 { "vldmxcsr", { Md
}, 0 },
9550 /* VEX_LEN_0FAE_R_3_M_0 */
9552 { "vstmxcsr", { Md
}, 0 },
9555 /* VEX_LEN_0FC4_P_2 */
9557 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
9560 /* VEX_LEN_0FC5_P_2 */
9562 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
9565 /* VEX_LEN_0FD6_P_2 */
9567 { "vmovq", { EXqVexScalarS
, XMScalar
}, 0 },
9570 /* VEX_LEN_0FF7_P_2 */
9572 { "vmaskmovdqu", { XM
, XS
}, 0 },
9575 /* VEX_LEN_0F3816_P_2 */
9578 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9581 /* VEX_LEN_0F3819_P_2 */
9584 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9587 /* VEX_LEN_0F381A_P_2_M_0 */
9590 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9593 /* VEX_LEN_0F3836_P_2 */
9596 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9599 /* VEX_LEN_0F3841_P_2 */
9601 { "vphminposuw", { XM
, EXx
}, 0 },
9604 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
9606 { "ldtilecfg", { M
}, 0 },
9609 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
9611 { "tilerelease", { Skip_MODRM
}, 0 },
9614 /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
9616 { "sttilecfg", { M
}, 0 },
9619 /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
9621 { "tilezero", { TMM
, Skip_MODRM
}, 0 },
9624 /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
9626 { "tilestored", { MVexSIBMEM
, TMM
}, 0 },
9628 /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
9630 { "tileloaddt1", { TMM
, MVexSIBMEM
}, 0 },
9633 /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
9635 { "tileloadd", { TMM
, MVexSIBMEM
}, 0 },
9638 /* VEX_LEN_0F385A_P_2_M_0 */
9641 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9644 /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
9646 { "tdpbf16ps", { TMM
, EXtmm
, VexTmm
}, 0 },
9649 /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
9651 { "tdpbuud", {TMM
, EXtmm
, VexTmm
}, 0 },
9654 /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
9656 { "tdpbsud", {TMM
, EXtmm
, VexTmm
}, 0 },
9659 /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
9661 { "tdpbusd", {TMM
, EXtmm
, VexTmm
}, 0 },
9664 /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
9666 { "tdpbssd", {TMM
, EXtmm
, VexTmm
}, 0 },
9669 /* VEX_LEN_0F38DB_P_2 */
9671 { "vaesimc", { XM
, EXx
}, 0 },
9674 /* VEX_LEN_0F38F2_P_0 */
9676 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
9679 /* VEX_LEN_0F38F3_R_1_P_0 */
9681 { "blsrS", { VexGdq
, Edq
}, 0 },
9684 /* VEX_LEN_0F38F3_R_2_P_0 */
9686 { "blsmskS", { VexGdq
, Edq
}, 0 },
9689 /* VEX_LEN_0F38F3_R_3_P_0 */
9691 { "blsiS", { VexGdq
, Edq
}, 0 },
9694 /* VEX_LEN_0F38F5_P_0 */
9696 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
9699 /* VEX_LEN_0F38F5_P_1 */
9701 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
9704 /* VEX_LEN_0F38F5_P_3 */
9706 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
9709 /* VEX_LEN_0F38F6_P_3 */
9711 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
9714 /* VEX_LEN_0F38F7_P_0 */
9716 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
9719 /* VEX_LEN_0F38F7_P_1 */
9721 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
9724 /* VEX_LEN_0F38F7_P_2 */
9726 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
9729 /* VEX_LEN_0F38F7_P_3 */
9731 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
9734 /* VEX_LEN_0F3A00_P_2 */
9737 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
9740 /* VEX_LEN_0F3A01_P_2 */
9743 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
9746 /* VEX_LEN_0F3A06_P_2 */
9749 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
9752 /* VEX_LEN_0F3A14_P_2 */
9754 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
9757 /* VEX_LEN_0F3A15_P_2 */
9759 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
9762 /* VEX_LEN_0F3A16_P_2 */
9764 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
9767 /* VEX_LEN_0F3A17_P_2 */
9769 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
9772 /* VEX_LEN_0F3A18_P_2 */
9775 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
9778 /* VEX_LEN_0F3A19_P_2 */
9781 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
9784 /* VEX_LEN_0F3A20_P_2 */
9786 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
9789 /* VEX_LEN_0F3A21_P_2 */
9791 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
9794 /* VEX_LEN_0F3A22_P_2 */
9796 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
9799 /* VEX_LEN_0F3A30_P_2 */
9801 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
9804 /* VEX_LEN_0F3A31_P_2 */
9806 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
9809 /* VEX_LEN_0F3A32_P_2 */
9811 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
9814 /* VEX_LEN_0F3A33_P_2 */
9816 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
9819 /* VEX_LEN_0F3A38_P_2 */
9822 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
9825 /* VEX_LEN_0F3A39_P_2 */
9828 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
9831 /* VEX_LEN_0F3A41_P_2 */
9833 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
9836 /* VEX_LEN_0F3A46_P_2 */
9839 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
9842 /* VEX_LEN_0F3A60_P_2 */
9844 { "vpcmpestrm!%LQ", { XM
, EXx
, Ib
}, 0 },
9847 /* VEX_LEN_0F3A61_P_2 */
9849 { "vpcmpestri!%LQ", { XM
, EXx
, Ib
}, 0 },
9852 /* VEX_LEN_0F3A62_P_2 */
9854 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
9857 /* VEX_LEN_0F3A63_P_2 */
9859 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
9862 /* VEX_LEN_0F3ADF_P_2 */
9864 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
9867 /* VEX_LEN_0F3AF0_P_3 */
9869 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
9872 /* VEX_LEN_0FXOP_08_85 */
9874 { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0
) },
9877 /* VEX_LEN_0FXOP_08_86 */
9879 { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0
) },
9882 /* VEX_LEN_0FXOP_08_87 */
9884 { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0
) },
9887 /* VEX_LEN_0FXOP_08_8E */
9889 { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0
) },
9892 /* VEX_LEN_0FXOP_08_8F */
9894 { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0
) },
9897 /* VEX_LEN_0FXOP_08_95 */
9899 { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0
) },
9902 /* VEX_LEN_0FXOP_08_96 */
9904 { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0
) },
9907 /* VEX_LEN_0FXOP_08_97 */
9909 { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0
) },
9912 /* VEX_LEN_0FXOP_08_9E */
9914 { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0
) },
9917 /* VEX_LEN_0FXOP_08_9F */
9919 { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0
) },
9922 /* VEX_LEN_0FXOP_08_A3 */
9924 { "vpperm", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
9927 /* VEX_LEN_0FXOP_08_A6 */
9929 { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0
) },
9932 /* VEX_LEN_0FXOP_08_B6 */
9934 { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0
) },
9937 /* VEX_LEN_0FXOP_08_C0 */
9939 { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0
) },
9942 /* VEX_LEN_0FXOP_08_C1 */
9944 { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0
) },
9947 /* VEX_LEN_0FXOP_08_C2 */
9949 { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0
) },
9952 /* VEX_LEN_0FXOP_08_C3 */
9954 { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0
) },
9957 /* VEX_LEN_0FXOP_08_CC */
9959 { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0
) },
9962 /* VEX_LEN_0FXOP_08_CD */
9964 { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0
) },
9967 /* VEX_LEN_0FXOP_08_CE */
9969 { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0
) },
9972 /* VEX_LEN_0FXOP_08_CF */
9974 { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0
) },
9977 /* VEX_LEN_0FXOP_08_EC */
9979 { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0
) },
9982 /* VEX_LEN_0FXOP_08_ED */
9984 { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0
) },
9987 /* VEX_LEN_0FXOP_08_EE */
9989 { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0
) },
9992 /* VEX_LEN_0FXOP_08_EF */
9994 { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0
) },
9997 /* VEX_LEN_0FXOP_09_01 */
9999 { REG_TABLE (REG_0FXOP_09_01_L_0
) },
10002 /* VEX_LEN_0FXOP_09_02 */
10004 { REG_TABLE (REG_0FXOP_09_02_L_0
) },
10007 /* VEX_LEN_0FXOP_09_12_M_1 */
10009 { REG_TABLE (REG_0FXOP_09_12_M_1_L_0
) },
10012 /* VEX_LEN_0FXOP_09_82_W_0 */
10014 { "vfrczss", { XM
, EXd
}, 0 },
10017 /* VEX_LEN_0FXOP_09_83_W_0 */
10019 { "vfrczsd", { XM
, EXq
}, 0 },
10022 /* VEX_LEN_0FXOP_09_90 */
10024 { "vprotb", { XM
, EXx
, VexW
}, 0 },
10027 /* VEX_LEN_0FXOP_09_91 */
10029 { "vprotw", { XM
, EXx
, VexW
}, 0 },
10032 /* VEX_LEN_0FXOP_09_92 */
10034 { "vprotd", { XM
, EXx
, VexW
}, 0 },
10037 /* VEX_LEN_0FXOP_09_93 */
10039 { "vprotq", { XM
, EXx
, VexW
}, 0 },
10042 /* VEX_LEN_0FXOP_09_94 */
10044 { "vpshlb", { XM
, EXx
, VexW
}, 0 },
10047 /* VEX_LEN_0FXOP_09_95 */
10049 { "vpshlw", { XM
, EXx
, VexW
}, 0 },
10052 /* VEX_LEN_0FXOP_09_96 */
10054 { "vpshld", { XM
, EXx
, VexW
}, 0 },
10057 /* VEX_LEN_0FXOP_09_97 */
10059 { "vpshlq", { XM
, EXx
, VexW
}, 0 },
10062 /* VEX_LEN_0FXOP_09_98 */
10064 { "vpshab", { XM
, EXx
, VexW
}, 0 },
10067 /* VEX_LEN_0FXOP_09_99 */
10069 { "vpshaw", { XM
, EXx
, VexW
}, 0 },
10072 /* VEX_LEN_0FXOP_09_9A */
10074 { "vpshad", { XM
, EXx
, VexW
}, 0 },
10077 /* VEX_LEN_0FXOP_09_9B */
10079 { "vpshaq", { XM
, EXx
, VexW
}, 0 },
10082 /* VEX_LEN_0FXOP_09_C1 */
10084 { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0
) },
10087 /* VEX_LEN_0FXOP_09_C2 */
10089 { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0
) },
10092 /* VEX_LEN_0FXOP_09_C3 */
10094 { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0
) },
10097 /* VEX_LEN_0FXOP_09_C6 */
10099 { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0
) },
10102 /* VEX_LEN_0FXOP_09_C7 */
10104 { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0
) },
10107 /* VEX_LEN_0FXOP_09_CB */
10109 { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0
) },
10112 /* VEX_LEN_0FXOP_09_D1 */
10114 { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0
) },
10117 /* VEX_LEN_0FXOP_09_D2 */
10119 { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0
) },
10122 /* VEX_LEN_0FXOP_09_D3 */
10124 { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0
) },
10127 /* VEX_LEN_0FXOP_09_D6 */
10129 { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0
) },
10132 /* VEX_LEN_0FXOP_09_D7 */
10134 { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0
) },
10137 /* VEX_LEN_0FXOP_09_DB */
10139 { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0
) },
10142 /* VEX_LEN_0FXOP_09_E1 */
10144 { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0
) },
10147 /* VEX_LEN_0FXOP_09_E2 */
10149 { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0
) },
10152 /* VEX_LEN_0FXOP_09_E3 */
10154 { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0
) },
10157 /* VEX_LEN_0FXOP_0A_12 */
10159 { REG_TABLE (REG_0FXOP_0A_12_L_0
) },
10163 #include "i386-dis-evex-len.h"
10165 static const struct dis386 vex_w_table
[][2] = {
10167 /* VEX_W_0F41_P_0_LEN_1 */
10168 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
10169 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
10172 /* VEX_W_0F41_P_2_LEN_1 */
10173 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
10174 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
10177 /* VEX_W_0F42_P_0_LEN_1 */
10178 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
10179 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
10182 /* VEX_W_0F42_P_2_LEN_1 */
10183 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
10184 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
10187 /* VEX_W_0F44_P_0_LEN_0 */
10188 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
10189 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
10192 /* VEX_W_0F44_P_2_LEN_0 */
10193 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
10194 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
10197 /* VEX_W_0F45_P_0_LEN_1 */
10198 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
10199 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
10202 /* VEX_W_0F45_P_2_LEN_1 */
10203 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
10204 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
10207 /* VEX_W_0F46_P_0_LEN_1 */
10208 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
10209 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
10212 /* VEX_W_0F46_P_2_LEN_1 */
10213 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
10214 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
10217 /* VEX_W_0F47_P_0_LEN_1 */
10218 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
10219 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
10222 /* VEX_W_0F47_P_2_LEN_1 */
10223 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
10224 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
10227 /* VEX_W_0F4A_P_0_LEN_1 */
10228 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
10229 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
10232 /* VEX_W_0F4A_P_2_LEN_1 */
10233 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
10234 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
10237 /* VEX_W_0F4B_P_0_LEN_1 */
10238 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
10239 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
10242 /* VEX_W_0F4B_P_2_LEN_1 */
10243 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
10246 /* VEX_W_0F90_P_0_LEN_0 */
10247 { "kmovw", { MaskG
, MaskE
}, 0 },
10248 { "kmovq", { MaskG
, MaskE
}, 0 },
10251 /* VEX_W_0F90_P_2_LEN_0 */
10252 { "kmovb", { MaskG
, MaskBDE
}, 0 },
10253 { "kmovd", { MaskG
, MaskBDE
}, 0 },
10256 /* VEX_W_0F91_P_0_LEN_0 */
10257 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
10258 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
10261 /* VEX_W_0F91_P_2_LEN_0 */
10262 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
10263 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
10266 /* VEX_W_0F92_P_0_LEN_0 */
10267 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
10270 /* VEX_W_0F92_P_2_LEN_0 */
10271 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
10274 /* VEX_W_0F93_P_0_LEN_0 */
10275 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
10278 /* VEX_W_0F93_P_2_LEN_0 */
10279 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
10282 /* VEX_W_0F98_P_0_LEN_0 */
10283 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
10284 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
10287 /* VEX_W_0F98_P_2_LEN_0 */
10288 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
10289 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
10292 /* VEX_W_0F99_P_0_LEN_0 */
10293 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
10294 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
10297 /* VEX_W_0F99_P_2_LEN_0 */
10298 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
10299 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
10302 /* VEX_W_0F380C_P_2 */
10303 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
10306 /* VEX_W_0F380D_P_2 */
10307 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
10310 /* VEX_W_0F380E_P_2 */
10311 { "vtestps", { XM
, EXx
}, 0 },
10314 /* VEX_W_0F380F_P_2 */
10315 { "vtestpd", { XM
, EXx
}, 0 },
10318 /* VEX_W_0F3813_P_2 */
10319 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
10322 /* VEX_W_0F3816_P_2 */
10323 { "vpermps", { XM
, Vex
, EXx
}, 0 },
10326 /* VEX_W_0F3818_P_2 */
10327 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
10330 /* VEX_W_0F3819_P_2 */
10331 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
10334 /* VEX_W_0F381A_P_2_M_0 */
10335 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
10338 /* VEX_W_0F382C_P_2_M_0 */
10339 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
10342 /* VEX_W_0F382D_P_2_M_0 */
10343 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
10346 /* VEX_W_0F382E_P_2_M_0 */
10347 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
10350 /* VEX_W_0F382F_P_2_M_0 */
10351 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
10354 /* VEX_W_0F3836_P_2 */
10355 { "vpermd", { XM
, Vex
, EXx
}, 0 },
10358 /* VEX_W_0F3846_P_2 */
10359 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
10362 /* VEX_W_0F3849_X86_64_P_0 */
10363 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0
) },
10366 /* VEX_W_0F3849_X86_64_P_2 */
10367 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0
) },
10370 /* VEX_W_0F3849_X86_64_P_3 */
10371 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0
) },
10374 /* VEX_W_0F384B_X86_64_P_1 */
10375 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0
) },
10378 /* VEX_W_0F384B_X86_64_P_2 */
10379 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0
) },
10382 /* VEX_W_0F384B_X86_64_P_3 */
10383 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0
) },
10386 /* VEX_W_0F3858_P_2 */
10387 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
10390 /* VEX_W_0F3859_P_2 */
10391 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
10394 /* VEX_W_0F385A_P_2_M_0 */
10395 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
10398 /* VEX_W_0F385C_X86_64_P_1 */
10399 { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0
) },
10402 /* VEX_W_0F385E_X86_64_P_0 */
10403 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0
) },
10406 /* VEX_W_0F385E_X86_64_P_1 */
10407 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0
) },
10410 /* VEX_W_0F385E_X86_64_P_2 */
10411 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0
) },
10414 /* VEX_W_0F385E_X86_64_P_3 */
10415 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0
) },
10418 /* VEX_W_0F3878_P_2 */
10419 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
10422 /* VEX_W_0F3879_P_2 */
10423 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
10426 /* VEX_W_0F38CF_P_2 */
10427 { "vgf2p8mulb", { XM
, Vex
, EXx
}, 0 },
10430 /* VEX_W_0F3A00_P_2 */
10432 { "vpermq", { XM
, EXx
, Ib
}, 0 },
10435 /* VEX_W_0F3A01_P_2 */
10437 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
10440 /* VEX_W_0F3A02_P_2 */
10441 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
10444 /* VEX_W_0F3A04_P_2 */
10445 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
10448 /* VEX_W_0F3A05_P_2 */
10449 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
10452 /* VEX_W_0F3A06_P_2 */
10453 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10456 /* VEX_W_0F3A18_P_2 */
10457 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10460 /* VEX_W_0F3A19_P_2 */
10461 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
10464 /* VEX_W_0F3A1D_P_2 */
10465 { "vcvtps2ph", { EXxmmq
, XM
, EXxEVexS
, Ib
}, 0 },
10468 /* VEX_W_0F3A30_P_2_LEN_0 */
10469 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
10470 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
10473 /* VEX_W_0F3A31_P_2_LEN_0 */
10474 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
10475 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
10478 /* VEX_W_0F3A32_P_2_LEN_0 */
10479 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
10480 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
10483 /* VEX_W_0F3A33_P_2_LEN_0 */
10484 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
10485 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
10488 /* VEX_W_0F3A38_P_2 */
10489 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10492 /* VEX_W_0F3A39_P_2 */
10493 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
10496 /* VEX_W_0F3A46_P_2 */
10497 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10500 /* VEX_W_0F3A4A_P_2 */
10501 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10504 /* VEX_W_0F3A4B_P_2 */
10505 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10508 /* VEX_W_0F3A4C_P_2 */
10509 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10512 /* VEX_W_0F3ACE_P_2 */
10514 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10517 /* VEX_W_0F3ACF_P_2 */
10519 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10521 /* VEX_W_0FXOP_08_85_L_0 */
10523 { "vpmacssww", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10525 /* VEX_W_0FXOP_08_86_L_0 */
10527 { "vpmacsswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10529 /* VEX_W_0FXOP_08_87_L_0 */
10531 { "vpmacssdql", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10533 /* VEX_W_0FXOP_08_8E_L_0 */
10535 { "vpmacssdd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10537 /* VEX_W_0FXOP_08_8F_L_0 */
10539 { "vpmacssdqh", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10541 /* VEX_W_0FXOP_08_95_L_0 */
10543 { "vpmacsww", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10545 /* VEX_W_0FXOP_08_96_L_0 */
10547 { "vpmacswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10549 /* VEX_W_0FXOP_08_97_L_0 */
10551 { "vpmacsdql", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10553 /* VEX_W_0FXOP_08_9E_L_0 */
10555 { "vpmacsdd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10557 /* VEX_W_0FXOP_08_9F_L_0 */
10559 { "vpmacsdqh", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10561 /* VEX_W_0FXOP_08_A6_L_0 */
10563 { "vpmadcsswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10565 /* VEX_W_0FXOP_08_B6_L_0 */
10567 { "vpmadcswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10569 /* VEX_W_0FXOP_08_C0_L_0 */
10571 { "vprotb", { XM
, EXx
, Ib
}, 0 },
10573 /* VEX_W_0FXOP_08_C1_L_0 */
10575 { "vprotw", { XM
, EXx
, Ib
}, 0 },
10577 /* VEX_W_0FXOP_08_C2_L_0 */
10579 { "vprotd", { XM
, EXx
, Ib
}, 0 },
10581 /* VEX_W_0FXOP_08_C3_L_0 */
10583 { "vprotq", { XM
, EXx
, Ib
}, 0 },
10585 /* VEX_W_0FXOP_08_CC_L_0 */
10587 { "vpcomb", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10589 /* VEX_W_0FXOP_08_CD_L_0 */
10591 { "vpcomw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10593 /* VEX_W_0FXOP_08_CE_L_0 */
10595 { "vpcomd", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10597 /* VEX_W_0FXOP_08_CF_L_0 */
10599 { "vpcomq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10601 /* VEX_W_0FXOP_08_EC_L_0 */
10603 { "vpcomub", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10605 /* VEX_W_0FXOP_08_ED_L_0 */
10607 { "vpcomuw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10609 /* VEX_W_0FXOP_08_EE_L_0 */
10611 { "vpcomud", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10613 /* VEX_W_0FXOP_08_EF_L_0 */
10615 { "vpcomuq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10617 /* VEX_W_0FXOP_09_80 */
10619 { "vfrczps", { XM
, EXx
}, 0 },
10621 /* VEX_W_0FXOP_09_81 */
10623 { "vfrczpd", { XM
, EXx
}, 0 },
10625 /* VEX_W_0FXOP_09_82 */
10627 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0
) },
10629 /* VEX_W_0FXOP_09_83 */
10631 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0
) },
10633 /* VEX_W_0FXOP_09_C1_L_0 */
10635 { "vphaddbw", { XM
, EXxmm
}, 0 },
10637 /* VEX_W_0FXOP_09_C2_L_0 */
10639 { "vphaddbd", { XM
, EXxmm
}, 0 },
10641 /* VEX_W_0FXOP_09_C3_L_0 */
10643 { "vphaddbq", { XM
, EXxmm
}, 0 },
10645 /* VEX_W_0FXOP_09_C6_L_0 */
10647 { "vphaddwd", { XM
, EXxmm
}, 0 },
10649 /* VEX_W_0FXOP_09_C7_L_0 */
10651 { "vphaddwq", { XM
, EXxmm
}, 0 },
10653 /* VEX_W_0FXOP_09_CB_L_0 */
10655 { "vphadddq", { XM
, EXxmm
}, 0 },
10657 /* VEX_W_0FXOP_09_D1_L_0 */
10659 { "vphaddubw", { XM
, EXxmm
}, 0 },
10661 /* VEX_W_0FXOP_09_D2_L_0 */
10663 { "vphaddubd", { XM
, EXxmm
}, 0 },
10665 /* VEX_W_0FXOP_09_D3_L_0 */
10667 { "vphaddubq", { XM
, EXxmm
}, 0 },
10669 /* VEX_W_0FXOP_09_D6_L_0 */
10671 { "vphadduwd", { XM
, EXxmm
}, 0 },
10673 /* VEX_W_0FXOP_09_D7_L_0 */
10675 { "vphadduwq", { XM
, EXxmm
}, 0 },
10677 /* VEX_W_0FXOP_09_DB_L_0 */
10679 { "vphaddudq", { XM
, EXxmm
}, 0 },
10681 /* VEX_W_0FXOP_09_E1_L_0 */
10683 { "vphsubbw", { XM
, EXxmm
}, 0 },
10685 /* VEX_W_0FXOP_09_E2_L_0 */
10687 { "vphsubwd", { XM
, EXxmm
}, 0 },
10689 /* VEX_W_0FXOP_09_E3_L_0 */
10691 { "vphsubdq", { XM
, EXxmm
}, 0 },
10694 #include "i386-dis-evex-w.h"
10697 static const struct dis386 mod_table
[][2] = {
10700 { "leaS", { Gv
, M
}, 0 },
10705 { RM_TABLE (RM_C6_REG_7
) },
10710 { RM_TABLE (RM_C7_REG_7
) },
10714 { "{l|}call^", { indirEp
}, 0 },
10718 { "{l|}jmp^", { indirEp
}, 0 },
10721 /* MOD_0F01_REG_0 */
10722 { X86_64_TABLE (X86_64_0F01_REG_0
) },
10723 { RM_TABLE (RM_0F01_REG_0
) },
10726 /* MOD_0F01_REG_1 */
10727 { X86_64_TABLE (X86_64_0F01_REG_1
) },
10728 { RM_TABLE (RM_0F01_REG_1
) },
10731 /* MOD_0F01_REG_2 */
10732 { X86_64_TABLE (X86_64_0F01_REG_2
) },
10733 { RM_TABLE (RM_0F01_REG_2
) },
10736 /* MOD_0F01_REG_3 */
10737 { X86_64_TABLE (X86_64_0F01_REG_3
) },
10738 { RM_TABLE (RM_0F01_REG_3
) },
10741 /* MOD_0F01_REG_5 */
10742 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0
) },
10743 { RM_TABLE (RM_0F01_REG_5_MOD_3
) },
10746 /* MOD_0F01_REG_7 */
10747 { "invlpg", { Mb
}, 0 },
10748 { RM_TABLE (RM_0F01_REG_7_MOD_3
) },
10751 /* MOD_0F12_PREFIX_0 */
10752 { "movlpX", { XM
, EXq
}, 0 },
10753 { "movhlps", { XM
, EXq
}, 0 },
10756 /* MOD_0F12_PREFIX_2 */
10757 { "movlpX", { XM
, EXq
}, 0 },
10761 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
10764 /* MOD_0F16_PREFIX_0 */
10765 { "movhpX", { XM
, EXq
}, 0 },
10766 { "movlhps", { XM
, EXq
}, 0 },
10769 /* MOD_0F16_PREFIX_2 */
10770 { "movhpX", { XM
, EXq
}, 0 },
10774 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
10777 /* MOD_0F18_REG_0 */
10778 { "prefetchnta", { Mb
}, 0 },
10781 /* MOD_0F18_REG_1 */
10782 { "prefetcht0", { Mb
}, 0 },
10785 /* MOD_0F18_REG_2 */
10786 { "prefetcht1", { Mb
}, 0 },
10789 /* MOD_0F18_REG_3 */
10790 { "prefetcht2", { Mb
}, 0 },
10793 /* MOD_0F18_REG_4 */
10794 { "nop/reserved", { Mb
}, 0 },
10797 /* MOD_0F18_REG_5 */
10798 { "nop/reserved", { Mb
}, 0 },
10801 /* MOD_0F18_REG_6 */
10802 { "nop/reserved", { Mb
}, 0 },
10805 /* MOD_0F18_REG_7 */
10806 { "nop/reserved", { Mb
}, 0 },
10809 /* MOD_0F1A_PREFIX_0 */
10810 { "bndldx", { Gbnd
, Mv_bnd
}, 0 },
10811 { "nopQ", { Ev
}, 0 },
10814 /* MOD_0F1B_PREFIX_0 */
10815 { "bndstx", { Mv_bnd
, Gbnd
}, 0 },
10816 { "nopQ", { Ev
}, 0 },
10819 /* MOD_0F1B_PREFIX_1 */
10820 { "bndmk", { Gbnd
, Mv_bnd
}, 0 },
10821 { "nopQ", { Ev
}, 0 },
10824 /* MOD_0F1C_PREFIX_0 */
10825 { REG_TABLE (REG_0F1C_P_0_MOD_0
) },
10826 { "nopQ", { Ev
}, 0 },
10829 /* MOD_0F1E_PREFIX_1 */
10830 { "nopQ", { Ev
}, 0 },
10831 { REG_TABLE (REG_0F1E_P_1_MOD_3
) },
10836 { "movL", { Rd
, Td
}, 0 },
10841 { "movL", { Td
, Rd
}, 0 },
10844 /* MOD_0F2B_PREFIX_0 */
10845 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
10848 /* MOD_0F2B_PREFIX_1 */
10849 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
10852 /* MOD_0F2B_PREFIX_2 */
10853 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
10856 /* MOD_0F2B_PREFIX_3 */
10857 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
10862 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
10865 /* MOD_0F71_REG_2 */
10867 { "psrlw", { MS
, Ib
}, 0 },
10870 /* MOD_0F71_REG_4 */
10872 { "psraw", { MS
, Ib
}, 0 },
10875 /* MOD_0F71_REG_6 */
10877 { "psllw", { MS
, Ib
}, 0 },
10880 /* MOD_0F72_REG_2 */
10882 { "psrld", { MS
, Ib
}, 0 },
10885 /* MOD_0F72_REG_4 */
10887 { "psrad", { MS
, Ib
}, 0 },
10890 /* MOD_0F72_REG_6 */
10892 { "pslld", { MS
, Ib
}, 0 },
10895 /* MOD_0F73_REG_2 */
10897 { "psrlq", { MS
, Ib
}, 0 },
10900 /* MOD_0F73_REG_3 */
10902 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
10905 /* MOD_0F73_REG_6 */
10907 { "psllq", { MS
, Ib
}, 0 },
10910 /* MOD_0F73_REG_7 */
10912 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
10915 /* MOD_0FAE_REG_0 */
10916 { "fxsave", { FXSAVE
}, 0 },
10917 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3
) },
10920 /* MOD_0FAE_REG_1 */
10921 { "fxrstor", { FXSAVE
}, 0 },
10922 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3
) },
10925 /* MOD_0FAE_REG_2 */
10926 { "ldmxcsr", { Md
}, 0 },
10927 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3
) },
10930 /* MOD_0FAE_REG_3 */
10931 { "stmxcsr", { Md
}, 0 },
10932 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3
) },
10935 /* MOD_0FAE_REG_4 */
10936 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0
) },
10937 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3
) },
10940 /* MOD_0FAE_REG_5 */
10941 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0
) },
10942 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3
) },
10945 /* MOD_0FAE_REG_6 */
10946 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0
) },
10947 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3
) },
10950 /* MOD_0FAE_REG_7 */
10951 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0
) },
10952 { RM_TABLE (RM_0FAE_REG_7_MOD_3
) },
10956 { "lssS", { Gv
, Mp
}, 0 },
10960 { "lfsS", { Gv
, Mp
}, 0 },
10964 { "lgsS", { Gv
, Mp
}, 0 },
10968 { PREFIX_TABLE (PREFIX_0FC3_MOD_0
) },
10971 /* MOD_0FC7_REG_3 */
10972 { "xrstors", { FXSAVE
}, 0 },
10975 /* MOD_0FC7_REG_4 */
10976 { "xsavec", { FXSAVE
}, 0 },
10979 /* MOD_0FC7_REG_5 */
10980 { "xsaves", { FXSAVE
}, 0 },
10983 /* MOD_0FC7_REG_6 */
10984 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0
) },
10985 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3
) }
10988 /* MOD_0FC7_REG_7 */
10989 { "vmptrst", { Mq
}, 0 },
10990 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3
) }
10995 { "pmovmskb", { Gdq
, MS
}, 0 },
10998 /* MOD_0FE7_PREFIX_2 */
10999 { "movntdq", { Mx
, XM
}, 0 },
11002 /* MOD_0FF0_PREFIX_3 */
11003 { "lddqu", { XM
, M
}, 0 },
11006 /* MOD_0F382A_PREFIX_2 */
11007 { "movntdqa", { XM
, Mx
}, 0 },
11010 /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
11011 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0
) },
11012 { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1
) },
11015 /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
11016 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0
) },
11019 /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
11021 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0
) },
11024 /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
11025 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0
) },
11028 /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
11029 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0
) },
11032 /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
11033 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0
) },
11036 /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
11038 { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0
) },
11041 /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
11043 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0
) },
11046 /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
11048 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0
) },
11051 /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
11053 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0
) },
11056 /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
11058 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0
) },
11061 /* MOD_0F38F5_PREFIX_2 */
11062 { "wrussK", { M
, Gdq
}, PREFIX_OPCODE
},
11065 /* MOD_0F38F6_PREFIX_0 */
11066 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
11069 /* MOD_0F38F8_PREFIX_1 */
11070 { "enqcmds", { Gva
, M
}, PREFIX_OPCODE
},
11073 /* MOD_0F38F8_PREFIX_2 */
11074 { "movdir64b", { Gva
, M
}, PREFIX_OPCODE
},
11077 /* MOD_0F38F8_PREFIX_3 */
11078 { "enqcmd", { Gva
, M
}, PREFIX_OPCODE
},
11081 /* MOD_0F38F9_PREFIX_0 */
11082 { "movdiri", { Ev
, Gv
}, PREFIX_OPCODE
},
11086 { "bound{S|}", { Gv
, Ma
}, 0 },
11087 { EVEX_TABLE (EVEX_0F
) },
11091 { "lesS", { Gv
, Mp
}, 0 },
11092 { VEX_C4_TABLE (VEX_0F
) },
11096 { "ldsS", { Gv
, Mp
}, 0 },
11097 { VEX_C5_TABLE (VEX_0F
) },
11100 /* MOD_VEX_0F12_PREFIX_0 */
11101 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
11102 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
11105 /* MOD_VEX_0F12_PREFIX_2 */
11106 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0
) },
11110 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
11113 /* MOD_VEX_0F16_PREFIX_0 */
11114 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
11115 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
11118 /* MOD_VEX_0F16_PREFIX_2 */
11119 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0
) },
11123 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
11127 { "vmovntpX", { Mx
, XM
}, PREFIX_OPCODE
},
11130 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11132 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
11135 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11137 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
11140 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11142 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
11145 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11147 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
11150 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11152 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
11155 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11157 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
11160 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11162 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
11165 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11167 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
11170 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11172 { "knotw", { MaskG
, MaskR
}, 0 },
11175 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11177 { "knotq", { MaskG
, MaskR
}, 0 },
11180 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11182 { "knotb", { MaskG
, MaskR
}, 0 },
11185 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11187 { "knotd", { MaskG
, MaskR
}, 0 },
11190 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11192 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
11195 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11197 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
11200 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11202 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
11205 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11207 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
11210 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11212 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
11215 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11217 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
11220 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11222 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
11225 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11227 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
11230 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11232 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
11235 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11237 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
11240 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11242 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
11245 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11247 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
11250 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11252 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
11255 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11257 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
11260 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11262 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
11265 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11267 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
11270 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11272 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
11275 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11277 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
11280 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11282 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
11287 { "vmovmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
11290 /* MOD_VEX_0F71_REG_2 */
11292 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
11295 /* MOD_VEX_0F71_REG_4 */
11297 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
11300 /* MOD_VEX_0F71_REG_6 */
11302 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
11305 /* MOD_VEX_0F72_REG_2 */
11307 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
11310 /* MOD_VEX_0F72_REG_4 */
11312 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
11315 /* MOD_VEX_0F72_REG_6 */
11317 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
11320 /* MOD_VEX_0F73_REG_2 */
11322 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
11325 /* MOD_VEX_0F73_REG_3 */
11327 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
11330 /* MOD_VEX_0F73_REG_6 */
11332 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
11335 /* MOD_VEX_0F73_REG_7 */
11337 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
11340 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11341 { "kmovw", { Ew
, MaskG
}, 0 },
11345 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11346 { "kmovq", { Eq
, MaskG
}, 0 },
11350 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11351 { "kmovb", { Eb
, MaskG
}, 0 },
11355 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11356 { "kmovd", { Ed
, MaskG
}, 0 },
11360 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
11362 { "kmovw", { MaskG
, Rdq
}, 0 },
11365 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
11367 { "kmovb", { MaskG
, Rdq
}, 0 },
11370 /* MOD_VEX_0F92_P_3_LEN_0 */
11372 { "kmovK", { MaskG
, Rdq
}, 0 },
11375 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
11377 { "kmovw", { Gdq
, MaskR
}, 0 },
11380 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
11382 { "kmovb", { Gdq
, MaskR
}, 0 },
11385 /* MOD_VEX_0F93_P_3_LEN_0 */
11387 { "kmovK", { Gdq
, MaskR
}, 0 },
11390 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
11392 { "kortestw", { MaskG
, MaskR
}, 0 },
11395 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
11397 { "kortestq", { MaskG
, MaskR
}, 0 },
11400 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
11402 { "kortestb", { MaskG
, MaskR
}, 0 },
11405 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
11407 { "kortestd", { MaskG
, MaskR
}, 0 },
11410 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
11412 { "ktestw", { MaskG
, MaskR
}, 0 },
11415 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
11417 { "ktestq", { MaskG
, MaskR
}, 0 },
11420 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
11422 { "ktestb", { MaskG
, MaskR
}, 0 },
11425 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
11427 { "ktestd", { MaskG
, MaskR
}, 0 },
11430 /* MOD_VEX_0FAE_REG_2 */
11431 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
11434 /* MOD_VEX_0FAE_REG_3 */
11435 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
11438 /* MOD_VEX_0FD7_PREFIX_2 */
11440 { "vpmovmskb", { Gdq
, XS
}, 0 },
11443 /* MOD_VEX_0FE7_PREFIX_2 */
11444 { "vmovntdq", { Mx
, XM
}, 0 },
11447 /* MOD_VEX_0FF0_PREFIX_3 */
11448 { "vlddqu", { XM
, M
}, 0 },
11451 /* MOD_VEX_0F381A_PREFIX_2 */
11452 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
11455 /* MOD_VEX_0F382A_PREFIX_2 */
11456 { "vmovntdqa", { XM
, Mx
}, 0 },
11459 /* MOD_VEX_0F382C_PREFIX_2 */
11460 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
11463 /* MOD_VEX_0F382D_PREFIX_2 */
11464 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
11467 /* MOD_VEX_0F382E_PREFIX_2 */
11468 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
11471 /* MOD_VEX_0F382F_PREFIX_2 */
11472 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
11475 /* MOD_VEX_0F385A_PREFIX_2 */
11476 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
11479 /* MOD_VEX_0F388C_PREFIX_2 */
11480 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
11483 /* MOD_VEX_0F388E_PREFIX_2 */
11484 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
11487 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
11489 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
11492 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
11494 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
11497 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
11499 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
11502 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
11504 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
11507 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
11509 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
11512 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
11514 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
11517 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
11519 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
11522 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
11524 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
11527 /* MOD_VEX_0FXOP_09_12 */
11529 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1
) },
11532 #include "i386-dis-evex-mod.h"
11535 static const struct dis386 rm_table
[][8] = {
11538 { "xabort", { Skip_MODRM
, Ib
}, 0 },
11542 { "xbeginT", { Skip_MODRM
, Jdqw
}, 0 },
11545 /* RM_0F01_REG_0 */
11546 { "enclv", { Skip_MODRM
}, 0 },
11547 { "vmcall", { Skip_MODRM
}, 0 },
11548 { "vmlaunch", { Skip_MODRM
}, 0 },
11549 { "vmresume", { Skip_MODRM
}, 0 },
11550 { "vmxoff", { Skip_MODRM
}, 0 },
11551 { "pconfig", { Skip_MODRM
}, 0 },
11554 /* RM_0F01_REG_1 */
11555 { "monitor", { { OP_Monitor
, 0 } }, 0 },
11556 { "mwait", { { OP_Mwait
, 0 } }, 0 },
11557 { "clac", { Skip_MODRM
}, 0 },
11558 { "stac", { Skip_MODRM
}, 0 },
11562 { "encls", { Skip_MODRM
}, 0 },
11565 /* RM_0F01_REG_2 */
11566 { "xgetbv", { Skip_MODRM
}, 0 },
11567 { "xsetbv", { Skip_MODRM
}, 0 },
11570 { "vmfunc", { Skip_MODRM
}, 0 },
11571 { "xend", { Skip_MODRM
}, 0 },
11572 { "xtest", { Skip_MODRM
}, 0 },
11573 { "enclu", { Skip_MODRM
}, 0 },
11576 /* RM_0F01_REG_3 */
11577 { "vmrun", { Skip_MODRM
}, 0 },
11578 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1
) },
11579 { "vmload", { Skip_MODRM
}, 0 },
11580 { "vmsave", { Skip_MODRM
}, 0 },
11581 { "stgi", { Skip_MODRM
}, 0 },
11582 { "clgi", { Skip_MODRM
}, 0 },
11583 { "skinit", { Skip_MODRM
}, 0 },
11584 { "invlpga", { Skip_MODRM
}, 0 },
11587 /* RM_0F01_REG_5_MOD_3 */
11588 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0
) },
11589 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1
) },
11590 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2
) },
11594 { "rdpkru", { Skip_MODRM
}, 0 },
11595 { "wrpkru", { Skip_MODRM
}, 0 },
11598 /* RM_0F01_REG_7_MOD_3 */
11599 { "swapgs", { Skip_MODRM
}, 0 },
11600 { "rdtscp", { Skip_MODRM
}, 0 },
11601 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2
) },
11602 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3
) },
11603 { "clzero", { Skip_MODRM
}, 0 },
11604 { "rdpru", { Skip_MODRM
}, 0 },
11607 /* RM_0F1E_P_1_MOD_3_REG_7 */
11608 { "nopQ", { Ev
}, 0 },
11609 { "nopQ", { Ev
}, 0 },
11610 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
11611 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
11612 { "nopQ", { Ev
}, 0 },
11613 { "nopQ", { Ev
}, 0 },
11614 { "nopQ", { Ev
}, 0 },
11615 { "nopQ", { Ev
}, 0 },
11618 /* RM_0FAE_REG_6_MOD_3 */
11619 { "mfence", { Skip_MODRM
}, 0 },
11622 /* RM_0FAE_REG_7_MOD_3 */
11623 { "sfence", { Skip_MODRM
}, 0 },
11627 /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
11628 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0
) },
11632 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11634 /* We use the high bit to indicate different name for the same
11636 #define REP_PREFIX (0xf3 | 0x100)
11637 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11638 #define XRELEASE_PREFIX (0xf3 | 0x400)
11639 #define BND_PREFIX (0xf2 | 0x400)
11640 #define NOTRACK_PREFIX (0x3e | 0x100)
11642 /* Remember if the current op is a jump instruction. */
11643 static bfd_boolean op_is_jump
= FALSE
;
11648 int newrex
, i
, length
;
11653 last_lock_prefix
= -1;
11654 last_repz_prefix
= -1;
11655 last_repnz_prefix
= -1;
11656 last_data_prefix
= -1;
11657 last_addr_prefix
= -1;
11658 last_rex_prefix
= -1;
11659 last_seg_prefix
= -1;
11661 active_seg_prefix
= 0;
11662 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11663 all_prefixes
[i
] = 0;
11666 /* The maximum instruction length is 15bytes. */
11667 while (length
< MAX_CODE_LENGTH
- 1)
11669 FETCH_DATA (the_info
, codep
+ 1);
11673 /* REX prefixes family. */
11690 if (address_mode
== mode_64bit
)
11694 last_rex_prefix
= i
;
11697 prefixes
|= PREFIX_REPZ
;
11698 last_repz_prefix
= i
;
11701 prefixes
|= PREFIX_REPNZ
;
11702 last_repnz_prefix
= i
;
11705 prefixes
|= PREFIX_LOCK
;
11706 last_lock_prefix
= i
;
11709 prefixes
|= PREFIX_CS
;
11710 last_seg_prefix
= i
;
11711 active_seg_prefix
= PREFIX_CS
;
11714 prefixes
|= PREFIX_SS
;
11715 last_seg_prefix
= i
;
11716 active_seg_prefix
= PREFIX_SS
;
11719 prefixes
|= PREFIX_DS
;
11720 last_seg_prefix
= i
;
11721 active_seg_prefix
= PREFIX_DS
;
11724 prefixes
|= PREFIX_ES
;
11725 last_seg_prefix
= i
;
11726 active_seg_prefix
= PREFIX_ES
;
11729 prefixes
|= PREFIX_FS
;
11730 last_seg_prefix
= i
;
11731 active_seg_prefix
= PREFIX_FS
;
11734 prefixes
|= PREFIX_GS
;
11735 last_seg_prefix
= i
;
11736 active_seg_prefix
= PREFIX_GS
;
11739 prefixes
|= PREFIX_DATA
;
11740 last_data_prefix
= i
;
11743 prefixes
|= PREFIX_ADDR
;
11744 last_addr_prefix
= i
;
11747 /* fwait is really an instruction. If there are prefixes
11748 before the fwait, they belong to the fwait, *not* to the
11749 following instruction. */
11751 if (prefixes
|| rex
)
11753 prefixes
|= PREFIX_FWAIT
;
11755 /* This ensures that the previous REX prefixes are noticed
11756 as unused prefixes, as in the return case below. */
11760 prefixes
= PREFIX_FWAIT
;
11765 /* Rex is ignored when followed by another prefix. */
11771 if (*codep
!= FWAIT_OPCODE
)
11772 all_prefixes
[i
++] = *codep
;
11780 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11783 static const char *
11784 prefix_name (int pref
, int sizeflag
)
11786 static const char *rexes
[16] =
11789 "rex.B", /* 0x41 */
11790 "rex.X", /* 0x42 */
11791 "rex.XB", /* 0x43 */
11792 "rex.R", /* 0x44 */
11793 "rex.RB", /* 0x45 */
11794 "rex.RX", /* 0x46 */
11795 "rex.RXB", /* 0x47 */
11796 "rex.W", /* 0x48 */
11797 "rex.WB", /* 0x49 */
11798 "rex.WX", /* 0x4a */
11799 "rex.WXB", /* 0x4b */
11800 "rex.WR", /* 0x4c */
11801 "rex.WRB", /* 0x4d */
11802 "rex.WRX", /* 0x4e */
11803 "rex.WRXB", /* 0x4f */
11808 /* REX prefixes family. */
11825 return rexes
[pref
- 0x40];
11845 return (sizeflag
& DFLAG
) ? "data16" : "data32";
11847 if (address_mode
== mode_64bit
)
11848 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
11850 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
11855 case XACQUIRE_PREFIX
:
11857 case XRELEASE_PREFIX
:
11861 case NOTRACK_PREFIX
:
11868 static char op_out
[MAX_OPERANDS
][100];
11869 static int op_ad
, op_index
[MAX_OPERANDS
];
11870 static int two_source_ops
;
11871 static bfd_vma op_address
[MAX_OPERANDS
];
11872 static bfd_vma op_riprel
[MAX_OPERANDS
];
11873 static bfd_vma start_pc
;
11876 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11877 * (see topic "Redundant prefixes" in the "Differences from 8086"
11878 * section of the "Virtual 8086 Mode" chapter.)
11879 * 'pc' should be the address of this instruction, it will
11880 * be used to print the target address if this is a relative jump or call
11881 * The function returns the length of this instruction in bytes.
11884 static char intel_syntax
;
11885 static char intel_mnemonic
= !SYSV386_COMPAT
;
11886 static char open_char
;
11887 static char close_char
;
11888 static char separator_char
;
11889 static char scale_char
;
11897 static enum x86_64_isa isa64
;
11899 /* Here for backwards compatibility. When gdb stops using
11900 print_insn_i386_att and print_insn_i386_intel these functions can
11901 disappear, and print_insn_i386 be merged into print_insn. */
11903 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
11907 return print_insn (pc
, info
);
11911 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
11915 return print_insn (pc
, info
);
11919 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
11923 return print_insn (pc
, info
);
11927 print_i386_disassembler_options (FILE *stream
)
11929 fprintf (stream
, _("\n\
11930 The following i386/x86-64 specific disassembler options are supported for use\n\
11931 with the -M switch (multiple options should be separated by commas):\n"));
11933 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
11934 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
11935 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
11936 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
11937 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
11938 fprintf (stream
, _(" att-mnemonic\n"
11939 " Display instruction in AT&T mnemonic\n"));
11940 fprintf (stream
, _(" intel-mnemonic\n"
11941 " Display instruction in Intel mnemonic\n"));
11942 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
11943 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
11944 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
11945 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
11946 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
11947 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11948 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
11949 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
11953 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
11955 /* Get a pointer to struct dis386 with a valid name. */
11957 static const struct dis386
*
11958 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
11960 int vindex
, vex_table_index
;
11962 if (dp
->name
!= NULL
)
11965 switch (dp
->op
[0].bytemode
)
11967 case USE_REG_TABLE
:
11968 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
11971 case USE_MOD_TABLE
:
11972 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
11973 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
11977 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
11980 case USE_PREFIX_TABLE
:
11983 /* The prefix in VEX is implicit. */
11984 switch (vex
.prefix
)
11989 case REPE_PREFIX_OPCODE
:
11992 case DATA_PREFIX_OPCODE
:
11995 case REPNE_PREFIX_OPCODE
:
12005 int last_prefix
= -1;
12008 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12009 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12011 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
12013 if (last_repz_prefix
> last_repnz_prefix
)
12016 prefix
= PREFIX_REPZ
;
12017 last_prefix
= last_repz_prefix
;
12022 prefix
= PREFIX_REPNZ
;
12023 last_prefix
= last_repnz_prefix
;
12026 /* Check if prefix should be ignored. */
12027 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
12028 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
12033 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
12036 prefix
= PREFIX_DATA
;
12037 last_prefix
= last_data_prefix
;
12042 used_prefixes
|= prefix
;
12043 all_prefixes
[last_prefix
] = 0;
12046 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
12049 case USE_X86_64_TABLE
:
12050 vindex
= address_mode
== mode_64bit
? 1 : 0;
12051 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
12054 case USE_3BYTE_TABLE
:
12055 FETCH_DATA (info
, codep
+ 2);
12057 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
12059 modrm
.mod
= (*codep
>> 6) & 3;
12060 modrm
.reg
= (*codep
>> 3) & 7;
12061 modrm
.rm
= *codep
& 7;
12064 case USE_VEX_LEN_TABLE
:
12068 switch (vex
.length
)
12081 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
12084 case USE_EVEX_LEN_TABLE
:
12088 switch (vex
.length
)
12104 dp
= &evex_len_table
[dp
->op
[1].bytemode
][vindex
];
12107 case USE_XOP_8F_TABLE
:
12108 FETCH_DATA (info
, codep
+ 3);
12109 rex
= ~(*codep
>> 5) & 0x7;
12111 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12112 switch ((*codep
& 0x1f))
12118 vex_table_index
= XOP_08
;
12121 vex_table_index
= XOP_09
;
12124 vex_table_index
= XOP_0A
;
12128 vex
.w
= *codep
& 0x80;
12129 if (vex
.w
&& address_mode
== mode_64bit
)
12132 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12133 if (address_mode
!= mode_64bit
)
12135 /* In 16/32-bit mode REX_B is silently ignored. */
12139 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12140 switch ((*codep
& 0x3))
12145 vex
.prefix
= DATA_PREFIX_OPCODE
;
12148 vex
.prefix
= REPE_PREFIX_OPCODE
;
12151 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12158 dp
= &xop_table
[vex_table_index
][vindex
];
12161 FETCH_DATA (info
, codep
+ 1);
12162 modrm
.mod
= (*codep
>> 6) & 3;
12163 modrm
.reg
= (*codep
>> 3) & 7;
12164 modrm
.rm
= *codep
& 7;
12166 /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
12167 having to decode the bits for every otherwise valid encoding. */
12169 return &bad_opcode
;
12172 case USE_VEX_C4_TABLE
:
12174 FETCH_DATA (info
, codep
+ 3);
12175 rex
= ~(*codep
>> 5) & 0x7;
12176 switch ((*codep
& 0x1f))
12182 vex_table_index
= VEX_0F
;
12185 vex_table_index
= VEX_0F38
;
12188 vex_table_index
= VEX_0F3A
;
12192 vex
.w
= *codep
& 0x80;
12193 if (address_mode
== mode_64bit
)
12200 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12201 is ignored, other REX bits are 0 and the highest bit in
12202 VEX.vvvv is also ignored (but we mustn't clear it here). */
12205 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12206 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12207 switch ((*codep
& 0x3))
12212 vex
.prefix
= DATA_PREFIX_OPCODE
;
12215 vex
.prefix
= REPE_PREFIX_OPCODE
;
12218 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12225 dp
= &vex_table
[vex_table_index
][vindex
];
12227 /* There is no MODRM byte for VEX0F 77. */
12228 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
12230 FETCH_DATA (info
, codep
+ 1);
12231 modrm
.mod
= (*codep
>> 6) & 3;
12232 modrm
.reg
= (*codep
>> 3) & 7;
12233 modrm
.rm
= *codep
& 7;
12237 case USE_VEX_C5_TABLE
:
12239 FETCH_DATA (info
, codep
+ 2);
12240 rex
= (*codep
& 0x80) ? 0 : REX_R
;
12242 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12244 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12245 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12246 switch ((*codep
& 0x3))
12251 vex
.prefix
= DATA_PREFIX_OPCODE
;
12254 vex
.prefix
= REPE_PREFIX_OPCODE
;
12257 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12264 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
12266 /* There is no MODRM byte for VEX 77. */
12267 if (vindex
!= 0x77)
12269 FETCH_DATA (info
, codep
+ 1);
12270 modrm
.mod
= (*codep
>> 6) & 3;
12271 modrm
.reg
= (*codep
>> 3) & 7;
12272 modrm
.rm
= *codep
& 7;
12276 case USE_VEX_W_TABLE
:
12280 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
12283 case USE_EVEX_TABLE
:
12284 two_source_ops
= 0;
12287 FETCH_DATA (info
, codep
+ 4);
12288 /* The first byte after 0x62. */
12289 rex
= ~(*codep
>> 5) & 0x7;
12290 vex
.r
= *codep
& 0x10;
12291 switch ((*codep
& 0xf))
12294 return &bad_opcode
;
12296 vex_table_index
= EVEX_0F
;
12299 vex_table_index
= EVEX_0F38
;
12302 vex_table_index
= EVEX_0F3A
;
12306 /* The second byte after 0x62. */
12308 vex
.w
= *codep
& 0x80;
12309 if (vex
.w
&& address_mode
== mode_64bit
)
12312 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12315 if (!(*codep
& 0x4))
12316 return &bad_opcode
;
12318 switch ((*codep
& 0x3))
12323 vex
.prefix
= DATA_PREFIX_OPCODE
;
12326 vex
.prefix
= REPE_PREFIX_OPCODE
;
12329 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12333 /* The third byte after 0x62. */
12336 /* Remember the static rounding bits. */
12337 vex
.ll
= (*codep
>> 5) & 3;
12338 vex
.b
= (*codep
& 0x10) != 0;
12340 vex
.v
= *codep
& 0x8;
12341 vex
.mask_register_specifier
= *codep
& 0x7;
12342 vex
.zeroing
= *codep
& 0x80;
12344 if (address_mode
!= mode_64bit
)
12346 /* In 16/32-bit mode silently ignore following bits. */
12356 dp
= &evex_table
[vex_table_index
][vindex
];
12358 FETCH_DATA (info
, codep
+ 1);
12359 modrm
.mod
= (*codep
>> 6) & 3;
12360 modrm
.reg
= (*codep
>> 3) & 7;
12361 modrm
.rm
= *codep
& 7;
12363 /* Set vector length. */
12364 if (modrm
.mod
== 3 && vex
.b
)
12380 return &bad_opcode
;
12393 if (dp
->name
!= NULL
)
12396 return get_valid_dis386 (dp
, info
);
12400 get_sib (disassemble_info
*info
, int sizeflag
)
12402 /* If modrm.mod == 3, operand must be register. */
12404 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
12408 FETCH_DATA (info
, codep
+ 2);
12409 sib
.index
= (codep
[1] >> 3) & 7;
12410 sib
.scale
= (codep
[1] >> 6) & 3;
12411 sib
.base
= codep
[1] & 7;
12416 print_insn (bfd_vma pc
, disassemble_info
*info
)
12418 const struct dis386
*dp
;
12420 char *op_txt
[MAX_OPERANDS
];
12422 int sizeflag
, orig_sizeflag
;
12424 struct dis_private priv
;
12427 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
12428 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
12429 address_mode
= mode_32bit
;
12430 else if (info
->mach
== bfd_mach_i386_i8086
)
12432 address_mode
= mode_16bit
;
12433 priv
.orig_sizeflag
= 0;
12436 address_mode
= mode_64bit
;
12438 if (intel_syntax
== (char) -1)
12439 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
12441 for (p
= info
->disassembler_options
; p
!= NULL
; )
12443 if (CONST_STRNEQ (p
, "amd64"))
12445 else if (CONST_STRNEQ (p
, "intel64"))
12447 else if (CONST_STRNEQ (p
, "x86-64"))
12449 address_mode
= mode_64bit
;
12450 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
12452 else if (CONST_STRNEQ (p
, "i386"))
12454 address_mode
= mode_32bit
;
12455 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
12457 else if (CONST_STRNEQ (p
, "i8086"))
12459 address_mode
= mode_16bit
;
12460 priv
.orig_sizeflag
&= ~(AFLAG
| DFLAG
);
12462 else if (CONST_STRNEQ (p
, "intel"))
12465 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
12466 intel_mnemonic
= 1;
12468 else if (CONST_STRNEQ (p
, "att"))
12471 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
12472 intel_mnemonic
= 0;
12474 else if (CONST_STRNEQ (p
, "addr"))
12476 if (address_mode
== mode_64bit
)
12478 if (p
[4] == '3' && p
[5] == '2')
12479 priv
.orig_sizeflag
&= ~AFLAG
;
12480 else if (p
[4] == '6' && p
[5] == '4')
12481 priv
.orig_sizeflag
|= AFLAG
;
12485 if (p
[4] == '1' && p
[5] == '6')
12486 priv
.orig_sizeflag
&= ~AFLAG
;
12487 else if (p
[4] == '3' && p
[5] == '2')
12488 priv
.orig_sizeflag
|= AFLAG
;
12491 else if (CONST_STRNEQ (p
, "data"))
12493 if (p
[4] == '1' && p
[5] == '6')
12494 priv
.orig_sizeflag
&= ~DFLAG
;
12495 else if (p
[4] == '3' && p
[5] == '2')
12496 priv
.orig_sizeflag
|= DFLAG
;
12498 else if (CONST_STRNEQ (p
, "suffix"))
12499 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
12501 p
= strchr (p
, ',');
12506 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
12508 (*info
->fprintf_func
) (info
->stream
,
12509 _("64-bit address is disabled"));
12515 names64
= intel_names64
;
12516 names32
= intel_names32
;
12517 names16
= intel_names16
;
12518 names8
= intel_names8
;
12519 names8rex
= intel_names8rex
;
12520 names_seg
= intel_names_seg
;
12521 names_mm
= intel_names_mm
;
12522 names_bnd
= intel_names_bnd
;
12523 names_xmm
= intel_names_xmm
;
12524 names_ymm
= intel_names_ymm
;
12525 names_zmm
= intel_names_zmm
;
12526 names_tmm
= intel_names_tmm
;
12527 index64
= intel_index64
;
12528 index32
= intel_index32
;
12529 names_mask
= intel_names_mask
;
12530 index16
= intel_index16
;
12533 separator_char
= '+';
12538 names64
= att_names64
;
12539 names32
= att_names32
;
12540 names16
= att_names16
;
12541 names8
= att_names8
;
12542 names8rex
= att_names8rex
;
12543 names_seg
= att_names_seg
;
12544 names_mm
= att_names_mm
;
12545 names_bnd
= att_names_bnd
;
12546 names_xmm
= att_names_xmm
;
12547 names_ymm
= att_names_ymm
;
12548 names_zmm
= att_names_zmm
;
12549 names_tmm
= att_names_tmm
;
12550 index64
= att_index64
;
12551 index32
= att_index32
;
12552 names_mask
= att_names_mask
;
12553 index16
= att_index16
;
12556 separator_char
= ',';
12560 /* The output looks better if we put 7 bytes on a line, since that
12561 puts most long word instructions on a single line. Use 8 bytes
12563 if ((info
->mach
& bfd_mach_l1om
) != 0)
12564 info
->bytes_per_line
= 8;
12566 info
->bytes_per_line
= 7;
12568 info
->private_data
= &priv
;
12569 priv
.max_fetched
= priv
.the_buffer
;
12570 priv
.insn_start
= pc
;
12573 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12581 start_codep
= priv
.the_buffer
;
12582 codep
= priv
.the_buffer
;
12584 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
12588 /* Getting here means we tried for data but didn't get it. That
12589 means we have an incomplete instruction of some sort. Just
12590 print the first byte as a prefix or a .byte pseudo-op. */
12591 if (codep
> priv
.the_buffer
)
12593 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
12595 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
12598 /* Just print the first byte as a .byte instruction. */
12599 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
12600 (unsigned int) priv
.the_buffer
[0]);
12610 sizeflag
= priv
.orig_sizeflag
;
12612 if (!ckprefix () || rex_used
)
12614 /* Too many prefixes or unused REX prefixes. */
12616 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
12618 (*info
->fprintf_func
) (info
->stream
, "%s%s",
12620 prefix_name (all_prefixes
[i
], sizeflag
));
12624 insn_codep
= codep
;
12626 FETCH_DATA (info
, codep
+ 1);
12627 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
12629 if (((prefixes
& PREFIX_FWAIT
)
12630 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
12632 /* Handle prefixes before fwait. */
12633 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
12635 (*info
->fprintf_func
) (info
->stream
, "%s ",
12636 prefix_name (all_prefixes
[i
], sizeflag
));
12637 (*info
->fprintf_func
) (info
->stream
, "fwait");
12641 if (*codep
== 0x0f)
12643 unsigned char threebyte
;
12646 FETCH_DATA (info
, codep
+ 1);
12647 threebyte
= *codep
;
12648 dp
= &dis386_twobyte
[threebyte
];
12649 need_modrm
= twobyte_has_modrm
[*codep
];
12654 dp
= &dis386
[*codep
];
12655 need_modrm
= onebyte_has_modrm
[*codep
];
12659 /* Save sizeflag for printing the extra prefixes later before updating
12660 it for mnemonic and operand processing. The prefix names depend
12661 only on the address mode. */
12662 orig_sizeflag
= sizeflag
;
12663 if (prefixes
& PREFIX_ADDR
)
12665 if ((prefixes
& PREFIX_DATA
))
12671 FETCH_DATA (info
, codep
+ 1);
12672 modrm
.mod
= (*codep
>> 6) & 3;
12673 modrm
.reg
= (*codep
>> 3) & 7;
12674 modrm
.rm
= *codep
& 7;
12679 memset (&vex
, 0, sizeof (vex
));
12681 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
12683 get_sib (info
, sizeflag
);
12684 dofloat (sizeflag
);
12688 dp
= get_valid_dis386 (dp
, info
);
12689 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
12691 get_sib (info
, sizeflag
);
12692 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12695 op_ad
= MAX_OPERANDS
- 1 - i
;
12697 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
12698 /* For EVEX instruction after the last operand masking
12699 should be printed. */
12700 if (i
== 0 && vex
.evex
)
12702 /* Don't print {%k0}. */
12703 if (vex
.mask_register_specifier
)
12706 oappend (names_mask
[vex
.mask_register_specifier
]);
12716 /* Clear instruction information. */
12719 the_info
->insn_info_valid
= 0;
12720 the_info
->branch_delay_insns
= 0;
12721 the_info
->data_size
= 0;
12722 the_info
->insn_type
= dis_noninsn
;
12723 the_info
->target
= 0;
12724 the_info
->target2
= 0;
12727 /* Reset jump operation indicator. */
12728 op_is_jump
= FALSE
;
12731 int jump_detection
= 0;
12733 /* Extract flags. */
12734 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12736 if ((dp
->op
[i
].rtn
== OP_J
)
12737 || (dp
->op
[i
].rtn
== OP_indirE
))
12738 jump_detection
|= 1;
12739 else if ((dp
->op
[i
].rtn
== BND_Fixup
)
12740 || (!dp
->op
[i
].rtn
&& !dp
->op
[i
].bytemode
))
12741 jump_detection
|= 2;
12742 else if ((dp
->op
[i
].bytemode
== cond_jump_mode
)
12743 || (dp
->op
[i
].bytemode
== loop_jcxz_mode
))
12744 jump_detection
|= 4;
12747 /* Determine if this is a jump or branch. */
12748 if ((jump_detection
& 0x3) == 0x3)
12751 if (jump_detection
& 0x4)
12752 the_info
->insn_type
= dis_condbranch
;
12754 the_info
->insn_type
=
12755 (dp
->name
&& !strncmp(dp
->name
, "call", 4))
12756 ? dis_jsr
: dis_branch
;
12760 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12761 are all 0s in inverted form. */
12762 if (need_vex
&& vex
.register_specifier
!= 0)
12764 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12765 return end_codep
- priv
.the_buffer
;
12768 /* Check if the REX prefix is used. */
12769 if ((rex
^ rex_used
) == 0 && !need_vex
&& last_rex_prefix
>= 0)
12770 all_prefixes
[last_rex_prefix
] = 0;
12772 /* Check if the SEG prefix is used. */
12773 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
12774 | PREFIX_FS
| PREFIX_GS
)) != 0
12775 && (used_prefixes
& active_seg_prefix
) != 0)
12776 all_prefixes
[last_seg_prefix
] = 0;
12778 /* Check if the ADDR prefix is used. */
12779 if ((prefixes
& PREFIX_ADDR
) != 0
12780 && (used_prefixes
& PREFIX_ADDR
) != 0)
12781 all_prefixes
[last_addr_prefix
] = 0;
12783 /* Check if the DATA prefix is used. */
12784 if ((prefixes
& PREFIX_DATA
) != 0
12785 && (used_prefixes
& PREFIX_DATA
) != 0
12787 all_prefixes
[last_data_prefix
] = 0;
12789 /* Print the extra prefixes. */
12791 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12792 if (all_prefixes
[i
])
12795 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
12798 prefix_length
+= strlen (name
) + 1;
12799 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
12802 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12803 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
12804 used by putop and MMX/SSE operand and may be overriden by the
12805 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12807 if (dp
->prefix_requirement
== PREFIX_OPCODE
12809 ? vex
.prefix
== REPE_PREFIX_OPCODE
12810 || vex
.prefix
== REPNE_PREFIX_OPCODE
12812 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
12814 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
12816 ? vex
.prefix
== DATA_PREFIX_OPCODE
12818 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
12820 && (used_prefixes
& PREFIX_DATA
) == 0))
12821 || (vex
.evex
&& !vex
.w
!= !(used_prefixes
& PREFIX_DATA
))))
12823 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12824 return end_codep
- priv
.the_buffer
;
12827 /* Check maximum code length. */
12828 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
12830 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12831 return MAX_CODE_LENGTH
;
12834 obufp
= mnemonicendp
;
12835 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
12838 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
12840 /* The enter and bound instructions are printed with operands in the same
12841 order as the intel book; everything else is printed in reverse order. */
12842 if (intel_syntax
|| two_source_ops
)
12846 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12847 op_txt
[i
] = op_out
[i
];
12849 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
12850 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
12852 op_txt
[2] = op_out
[3];
12853 op_txt
[3] = op_out
[2];
12856 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
12858 op_ad
= op_index
[i
];
12859 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
12860 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
12861 riprel
= op_riprel
[i
];
12862 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
12863 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
12868 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12869 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
12873 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12877 (*info
->fprintf_func
) (info
->stream
, ",");
12878 if (op_index
[i
] != -1 && !op_riprel
[i
])
12880 bfd_vma target
= (bfd_vma
) op_address
[op_index
[i
]];
12882 if (the_info
&& op_is_jump
)
12884 the_info
->insn_info_valid
= 1;
12885 the_info
->branch_delay_insns
= 0;
12886 the_info
->data_size
= 0;
12887 the_info
->target
= target
;
12888 the_info
->target2
= 0;
12890 (*info
->print_address_func
) (target
, info
);
12893 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
12897 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12898 if (op_index
[i
] != -1 && op_riprel
[i
])
12900 (*info
->fprintf_func
) (info
->stream
, " # ");
12901 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
12902 + op_address
[op_index
[i
]]), info
);
12905 return codep
- priv
.the_buffer
;
12908 static const char *float_mem
[] = {
12983 static const unsigned char float_mem_mode
[] = {
13058 #define ST { OP_ST, 0 }
13059 #define STi { OP_STi, 0 }
13061 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13062 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13063 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13064 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13065 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13066 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13067 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13068 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13069 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13071 static const struct dis386 float_reg
[][8] = {
13074 { "fadd", { ST
, STi
}, 0 },
13075 { "fmul", { ST
, STi
}, 0 },
13076 { "fcom", { STi
}, 0 },
13077 { "fcomp", { STi
}, 0 },
13078 { "fsub", { ST
, STi
}, 0 },
13079 { "fsubr", { ST
, STi
}, 0 },
13080 { "fdiv", { ST
, STi
}, 0 },
13081 { "fdivr", { ST
, STi
}, 0 },
13085 { "fld", { STi
}, 0 },
13086 { "fxch", { STi
}, 0 },
13096 { "fcmovb", { ST
, STi
}, 0 },
13097 { "fcmove", { ST
, STi
}, 0 },
13098 { "fcmovbe",{ ST
, STi
}, 0 },
13099 { "fcmovu", { ST
, STi
}, 0 },
13107 { "fcmovnb",{ ST
, STi
}, 0 },
13108 { "fcmovne",{ ST
, STi
}, 0 },
13109 { "fcmovnbe",{ ST
, STi
}, 0 },
13110 { "fcmovnu",{ ST
, STi
}, 0 },
13112 { "fucomi", { ST
, STi
}, 0 },
13113 { "fcomi", { ST
, STi
}, 0 },
13118 { "fadd", { STi
, ST
}, 0 },
13119 { "fmul", { STi
, ST
}, 0 },
13122 { "fsub{!M|r}", { STi
, ST
}, 0 },
13123 { "fsub{M|}", { STi
, ST
}, 0 },
13124 { "fdiv{!M|r}", { STi
, ST
}, 0 },
13125 { "fdiv{M|}", { STi
, ST
}, 0 },
13129 { "ffree", { STi
}, 0 },
13131 { "fst", { STi
}, 0 },
13132 { "fstp", { STi
}, 0 },
13133 { "fucom", { STi
}, 0 },
13134 { "fucomp", { STi
}, 0 },
13140 { "faddp", { STi
, ST
}, 0 },
13141 { "fmulp", { STi
, ST
}, 0 },
13144 { "fsub{!M|r}p", { STi
, ST
}, 0 },
13145 { "fsub{M|}p", { STi
, ST
}, 0 },
13146 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
13147 { "fdiv{M|}p", { STi
, ST
}, 0 },
13151 { "ffreep", { STi
}, 0 },
13156 { "fucomip", { ST
, STi
}, 0 },
13157 { "fcomip", { ST
, STi
}, 0 },
13162 static char *fgrps
[][8] = {
13165 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13170 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13175 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13180 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13185 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13190 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13195 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13200 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13201 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13206 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13211 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13216 swap_operand (void)
13218 mnemonicendp
[0] = '.';
13219 mnemonicendp
[1] = 's';
13224 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
13225 int sizeflag ATTRIBUTE_UNUSED
)
13227 /* Skip mod/rm byte. */
13233 dofloat (int sizeflag
)
13235 const struct dis386
*dp
;
13236 unsigned char floatop
;
13238 floatop
= codep
[-1];
13240 if (modrm
.mod
!= 3)
13242 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
13244 putop (float_mem
[fp_indx
], sizeflag
);
13247 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
13250 /* Skip mod/rm byte. */
13254 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
13255 if (dp
->name
== NULL
)
13257 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
13259 /* Instruction fnstsw is only one with strange arg. */
13260 if (floatop
== 0xdf && codep
[-1] == 0xe0)
13261 strcpy (op_out
[0], names16
[0]);
13265 putop (dp
->name
, sizeflag
);
13270 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
13275 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
13279 /* Like oappend (below), but S is a string starting with '%'.
13280 In Intel syntax, the '%' is elided. */
13282 oappend_maybe_intel (const char *s
)
13284 oappend (s
+ intel_syntax
);
13288 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13290 oappend_maybe_intel ("%st");
13294 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13296 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
13297 oappend_maybe_intel (scratchbuf
);
13300 /* Capital letters in template are macros. */
13302 putop (const char *in_template
, int sizeflag
)
13307 unsigned int l
= 0, len
= 0;
13310 for (p
= in_template
; *p
; p
++)
13314 if (l
>= sizeof (last
) || !ISUPPER (*p
))
13333 while (*++p
!= '|')
13334 if (*p
== '}' || *p
== '\0')
13340 while (*++p
!= '}')
13352 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13361 if (sizeflag
& SUFFIX_ALWAYS
)
13364 else if (l
== 1 && last
[0] == 'L')
13366 if (address_mode
== mode_64bit
13367 && !(prefixes
& PREFIX_ADDR
))
13380 if (intel_syntax
&& !alt
)
13382 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13384 if (sizeflag
& DFLAG
)
13385 *obufp
++ = intel_syntax
? 'd' : 'l';
13387 *obufp
++ = intel_syntax
? 'w' : 's';
13388 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13392 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
13395 if (modrm
.mod
== 3)
13401 if (sizeflag
& DFLAG
)
13402 *obufp
++ = intel_syntax
? 'd' : 'l';
13405 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13411 case 'E': /* For jcxz/jecxz */
13412 if (address_mode
== mode_64bit
)
13414 if (sizeflag
& AFLAG
)
13420 if (sizeflag
& AFLAG
)
13422 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
13427 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
13429 if (sizeflag
& AFLAG
)
13430 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
13432 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
13433 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
13437 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
13439 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13443 if (!(rex
& REX_W
))
13444 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13449 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
13450 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
13452 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
13455 if (prefixes
& PREFIX_DS
)
13471 if (l
!= 1 || last
[0] != 'X')
13473 if (!need_vex
|| !vex
.evex
)
13476 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
13478 switch (vex
.length
)
13496 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
13501 /* Fall through. */
13509 if (sizeflag
& SUFFIX_ALWAYS
)
13513 if (intel_mnemonic
!= cond
)
13517 if ((prefixes
& PREFIX_FWAIT
) == 0)
13520 used_prefixes
|= PREFIX_FWAIT
;
13526 else if (intel_syntax
&& (sizeflag
& DFLAG
))
13530 if (!(rex
& REX_W
))
13531 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13535 && address_mode
== mode_64bit
13536 && isa64
== intel64
)
13541 /* Fall through. */
13544 && address_mode
== mode_64bit
13545 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13550 /* Fall through. */
13558 if ((rex
& REX_W
) == 0
13559 && (prefixes
& PREFIX_DATA
))
13561 if ((sizeflag
& DFLAG
) == 0)
13563 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13567 if ((prefixes
& PREFIX_DATA
)
13569 || (sizeflag
& SUFFIX_ALWAYS
))
13576 if (sizeflag
& DFLAG
)
13580 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13584 else if (l
== 1 && last
[0] == 'L')
13586 if ((prefixes
& PREFIX_DATA
)
13588 || (sizeflag
& SUFFIX_ALWAYS
))
13595 if (sizeflag
& DFLAG
)
13596 *obufp
++ = intel_syntax
? 'd' : 'l';
13599 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13609 if (address_mode
== mode_64bit
13610 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13612 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13616 /* Fall through. */
13622 if (intel_syntax
&& !alt
)
13625 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13631 if (sizeflag
& DFLAG
)
13632 *obufp
++ = intel_syntax
? 'd' : 'l';
13635 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13639 else if (l
== 1 && last
[0] == 'L')
13641 if (cond
? modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)
13642 : address_mode
!= mode_64bit
)
13649 else if((address_mode
== mode_64bit
&& need_modrm
&& cond
)
13650 || (sizeflag
& SUFFIX_ALWAYS
))
13651 *obufp
++ = intel_syntax
? 'd' : 'l';
13660 else if (sizeflag
& DFLAG
)
13669 if (intel_syntax
&& !p
[1]
13670 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
13672 if (!(rex
& REX_W
))
13673 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13680 if (address_mode
== mode_64bit
13681 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13683 if (sizeflag
& SUFFIX_ALWAYS
)
13688 else if (l
== 1 && last
[0] == 'L')
13699 /* Fall through. */
13707 if (sizeflag
& SUFFIX_ALWAYS
)
13713 if (sizeflag
& DFLAG
)
13717 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13721 else if (l
== 1 && last
[0] == 'L')
13723 if (address_mode
== mode_64bit
13724 && !(prefixes
& PREFIX_ADDR
))
13740 ? vex
.prefix
== DATA_PREFIX_OPCODE
13741 : prefixes
& PREFIX_DATA
)
13744 used_prefixes
|= PREFIX_DATA
;
13750 if (l
== 1 && last
[0] == 'X')
13755 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
13757 switch (vex
.length
)
13777 /* operand size flag for cwtl, cbtw */
13786 else if (sizeflag
& DFLAG
)
13790 if (!(rex
& REX_W
))
13791 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13797 if (last
[0] == 'X')
13798 *obufp
++ = vex
.w
? 'd': 's';
13799 else if (last
[0] == 'L')
13800 *obufp
++ = vex
.w
? 'q': 'd';
13801 else if (last
[0] == 'B')
13802 *obufp
++ = vex
.w
? 'w': 'b';
13812 if (isa64
== intel64
&& (rex
& REX_W
))
13818 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13820 if (sizeflag
& DFLAG
)
13824 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13830 if (address_mode
== mode_64bit
13831 && (isa64
== intel64
13832 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
13834 else if ((prefixes
& PREFIX_DATA
))
13836 if (!(sizeflag
& DFLAG
))
13838 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13847 mnemonicendp
= obufp
;
13852 oappend (const char *s
)
13854 obufp
= stpcpy (obufp
, s
);
13860 /* Only print the active segment register. */
13861 if (!active_seg_prefix
)
13864 used_prefixes
|= active_seg_prefix
;
13865 switch (active_seg_prefix
)
13868 oappend_maybe_intel ("%cs:");
13871 oappend_maybe_intel ("%ds:");
13874 oappend_maybe_intel ("%ss:");
13877 oappend_maybe_intel ("%es:");
13880 oappend_maybe_intel ("%fs:");
13883 oappend_maybe_intel ("%gs:");
13891 OP_indirE (int bytemode
, int sizeflag
)
13895 OP_E (bytemode
, sizeflag
);
13899 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
13901 if (address_mode
== mode_64bit
)
13909 sprintf_vma (tmp
, disp
);
13910 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
13911 strcpy (buf
+ 2, tmp
+ i
);
13915 bfd_signed_vma v
= disp
;
13922 /* Check for possible overflow on 0x8000000000000000. */
13925 strcpy (buf
, "9223372036854775808");
13939 tmp
[28 - i
] = (v
% 10) + '0';
13943 strcpy (buf
, tmp
+ 29 - i
);
13949 sprintf (buf
, "0x%x", (unsigned int) disp
);
13951 sprintf (buf
, "%d", (int) disp
);
13955 /* Put DISP in BUF as signed hex number. */
13958 print_displacement (char *buf
, bfd_vma disp
)
13960 bfd_signed_vma val
= disp
;
13969 /* Check for possible overflow. */
13972 switch (address_mode
)
13975 strcpy (buf
+ j
, "0x8000000000000000");
13978 strcpy (buf
+ j
, "0x80000000");
13981 strcpy (buf
+ j
, "0x8000");
13991 sprintf_vma (tmp
, (bfd_vma
) val
);
13992 for (i
= 0; tmp
[i
] == '0'; i
++)
13994 if (tmp
[i
] == '\0')
13996 strcpy (buf
+ j
, tmp
+ i
);
14000 intel_operand_size (int bytemode
, int sizeflag
)
14004 && (bytemode
== x_mode
14005 || bytemode
== evex_half_bcst_xmmq_mode
))
14008 oappend ("QWORD PTR ");
14010 oappend ("DWORD PTR ");
14019 oappend ("BYTE PTR ");
14024 oappend ("WORD PTR ");
14027 if (address_mode
== mode_64bit
&& isa64
== intel64
)
14029 oappend ("QWORD PTR ");
14032 /* Fall through. */
14034 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14036 oappend ("QWORD PTR ");
14039 /* Fall through. */
14045 oappend ("QWORD PTR ");
14048 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
14049 oappend ("DWORD PTR ");
14051 oappend ("WORD PTR ");
14052 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14056 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14058 oappend ("WORD PTR ");
14059 if (!(rex
& REX_W
))
14060 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14063 if (sizeflag
& DFLAG
)
14064 oappend ("QWORD PTR ");
14066 oappend ("DWORD PTR ");
14067 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14070 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
14071 oappend ("WORD PTR ");
14073 oappend ("DWORD PTR ");
14074 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14077 case d_scalar_swap_mode
:
14080 oappend ("DWORD PTR ");
14083 case q_scalar_swap_mode
:
14085 oappend ("QWORD PTR ");
14088 if (address_mode
== mode_64bit
)
14089 oappend ("QWORD PTR ");
14091 oappend ("DWORD PTR ");
14094 if (sizeflag
& DFLAG
)
14095 oappend ("FWORD PTR ");
14097 oappend ("DWORD PTR ");
14098 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14101 oappend ("TBYTE PTR ");
14105 case evex_x_gscat_mode
:
14106 case evex_x_nobcst_mode
:
14110 switch (vex
.length
)
14113 oappend ("XMMWORD PTR ");
14116 oappend ("YMMWORD PTR ");
14119 oappend ("ZMMWORD PTR ");
14126 oappend ("XMMWORD PTR ");
14129 oappend ("XMMWORD PTR ");
14132 oappend ("YMMWORD PTR ");
14135 case evex_half_bcst_xmmq_mode
:
14139 switch (vex
.length
)
14142 oappend ("QWORD PTR ");
14145 oappend ("XMMWORD PTR ");
14148 oappend ("YMMWORD PTR ");
14158 switch (vex
.length
)
14163 oappend ("BYTE PTR ");
14173 switch (vex
.length
)
14178 oappend ("WORD PTR ");
14188 switch (vex
.length
)
14193 oappend ("DWORD PTR ");
14203 switch (vex
.length
)
14208 oappend ("QWORD PTR ");
14218 switch (vex
.length
)
14221 oappend ("WORD PTR ");
14224 oappend ("DWORD PTR ");
14227 oappend ("QWORD PTR ");
14237 switch (vex
.length
)
14240 oappend ("DWORD PTR ");
14243 oappend ("QWORD PTR ");
14246 oappend ("XMMWORD PTR ");
14256 switch (vex
.length
)
14259 oappend ("QWORD PTR ");
14262 oappend ("YMMWORD PTR ");
14265 oappend ("ZMMWORD PTR ");
14275 switch (vex
.length
)
14279 oappend ("XMMWORD PTR ");
14286 oappend ("OWORD PTR ");
14288 case vex_scalar_w_dq_mode
:
14293 oappend ("QWORD PTR ");
14295 oappend ("DWORD PTR ");
14297 case vex_vsib_d_w_dq_mode
:
14298 case vex_vsib_q_w_dq_mode
:
14305 oappend ("QWORD PTR ");
14307 oappend ("DWORD PTR ");
14311 switch (vex
.length
)
14314 oappend ("XMMWORD PTR ");
14317 oappend ("YMMWORD PTR ");
14320 oappend ("ZMMWORD PTR ");
14327 case vex_vsib_q_w_d_mode
:
14328 case vex_vsib_d_w_d_mode
:
14329 if (!need_vex
|| !vex
.evex
)
14332 switch (vex
.length
)
14335 oappend ("QWORD PTR ");
14338 oappend ("XMMWORD PTR ");
14341 oappend ("YMMWORD PTR ");
14349 if (!need_vex
|| vex
.length
!= 128)
14352 oappend ("DWORD PTR ");
14354 oappend ("BYTE PTR ");
14360 oappend ("QWORD PTR ");
14362 oappend ("WORD PTR ");
14372 OP_E_register (int bytemode
, int sizeflag
)
14374 int reg
= modrm
.rm
;
14375 const char **names
;
14381 if ((sizeflag
& SUFFIX_ALWAYS
)
14382 && (bytemode
== b_swap_mode
14383 || bytemode
== bnd_swap_mode
14384 || bytemode
== v_swap_mode
))
14411 names
= address_mode
== mode_64bit
? names64
: names32
;
14414 case bnd_swap_mode
:
14423 if (address_mode
== mode_64bit
&& isa64
== intel64
)
14428 /* Fall through. */
14430 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14436 /* Fall through. */
14448 if ((sizeflag
& DFLAG
)
14449 || (bytemode
!= v_mode
14450 && bytemode
!= v_swap_mode
))
14454 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14458 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
14462 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14465 names
= (address_mode
== mode_64bit
14466 ? names64
: names32
);
14467 if (!(prefixes
& PREFIX_ADDR
))
14468 names
= (address_mode
== mode_16bit
14469 ? names16
: names
);
14472 /* Remove "addr16/addr32". */
14473 all_prefixes
[last_addr_prefix
] = 0;
14474 names
= (address_mode
!= mode_32bit
14475 ? names32
: names16
);
14476 used_prefixes
|= PREFIX_ADDR
;
14486 names
= names_mask
;
14491 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14494 oappend (names
[reg
]);
14498 OP_E_memory (int bytemode
, int sizeflag
)
14501 int add
= (rex
& REX_B
) ? 8 : 0;
14507 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
14509 && bytemode
!= x_mode
14510 && bytemode
!= xmmq_mode
14511 && bytemode
!= evex_half_bcst_xmmq_mode
)
14529 if (address_mode
!= mode_64bit
)
14535 case d_scalar_swap_mode
:
14540 case vex_scalar_w_dq_mode
:
14541 case vex_vsib_d_w_dq_mode
:
14542 case vex_vsib_d_w_d_mode
:
14543 case vex_vsib_q_w_dq_mode
:
14544 case vex_vsib_q_w_d_mode
:
14545 case evex_x_gscat_mode
:
14546 shift
= vex
.w
? 3 : 2;
14549 case evex_half_bcst_xmmq_mode
:
14553 shift
= vex
.w
? 3 : 2;
14556 /* Fall through. */
14560 case evex_x_nobcst_mode
:
14562 switch (vex
.length
)
14576 /* Make necessary corrections to shift for modes that need it. */
14577 if (bytemode
== xmmq_mode
14578 || bytemode
== evex_half_bcst_xmmq_mode
14579 || (bytemode
== ymmq_mode
&& vex
.length
== 128))
14581 else if (bytemode
== xmmqd_mode
)
14583 else if (bytemode
== xmmdw_mode
)
14595 case q_scalar_swap_mode
:
14599 shift
= vex
.w
? 1 : 0;
14610 intel_operand_size (bytemode
, sizeflag
);
14613 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14615 /* 32/64 bit address mode */
14625 int addr32flag
= !((sizeflag
& AFLAG
)
14626 || bytemode
== v_bnd_mode
14627 || bytemode
== v_bndmk_mode
14628 || bytemode
== bnd_mode
14629 || bytemode
== bnd_swap_mode
);
14630 const char **indexes64
= names64
;
14631 const char **indexes32
= names32
;
14641 vindex
= sib
.index
;
14647 case vex_vsib_d_w_dq_mode
:
14648 case vex_vsib_d_w_d_mode
:
14649 case vex_vsib_q_w_dq_mode
:
14650 case vex_vsib_q_w_d_mode
:
14660 switch (vex
.length
)
14663 indexes64
= indexes32
= names_xmm
;
14667 || bytemode
== vex_vsib_q_w_dq_mode
14668 || bytemode
== vex_vsib_q_w_d_mode
)
14669 indexes64
= indexes32
= names_ymm
;
14671 indexes64
= indexes32
= names_xmm
;
14675 || bytemode
== vex_vsib_q_w_dq_mode
14676 || bytemode
== vex_vsib_q_w_d_mode
)
14677 indexes64
= indexes32
= names_zmm
;
14679 indexes64
= indexes32
= names_ymm
;
14686 haveindex
= vindex
!= 4;
14695 /* mandatory non-vector SIB must have sib */
14696 if (bytemode
== vex_sibmem_mode
)
14702 rbase
= base
+ add
;
14710 if (address_mode
== mode_64bit
&& !havesib
)
14713 if (riprel
&& bytemode
== v_bndmk_mode
)
14721 FETCH_DATA (the_info
, codep
+ 1);
14723 if ((disp
& 0x80) != 0)
14725 if (vex
.evex
&& shift
> 0)
14738 && address_mode
!= mode_16bit
)
14740 if (address_mode
== mode_64bit
)
14742 /* Display eiz instead of addr32. */
14743 needindex
= addr32flag
;
14748 /* In 32-bit mode, we need index register to tell [offset]
14749 from [eiz*1 + offset]. */
14754 havedisp
= (havebase
14756 || (havesib
&& (haveindex
|| scale
!= 0)));
14759 if (modrm
.mod
!= 0 || base
== 5)
14761 if (havedisp
|| riprel
)
14762 print_displacement (scratchbuf
, disp
);
14764 print_operand_value (scratchbuf
, 1, disp
);
14765 oappend (scratchbuf
);
14769 oappend (!addr32flag
? "(%rip)" : "(%eip)");
14773 if ((havebase
|| haveindex
|| needindex
|| needaddr32
|| riprel
)
14774 && (address_mode
!= mode_64bit
14775 || ((bytemode
!= v_bnd_mode
)
14776 && (bytemode
!= v_bndmk_mode
)
14777 && (bytemode
!= bnd_mode
)
14778 && (bytemode
!= bnd_swap_mode
))))
14779 used_prefixes
|= PREFIX_ADDR
;
14781 if (havedisp
|| (intel_syntax
&& riprel
))
14783 *obufp
++ = open_char
;
14784 if (intel_syntax
&& riprel
)
14787 oappend (!addr32flag
? "rip" : "eip");
14791 oappend (address_mode
== mode_64bit
&& !addr32flag
14792 ? names64
[rbase
] : names32
[rbase
]);
14795 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14796 print index to tell base + index from base. */
14800 || (havebase
&& base
!= ESP_REG_NUM
))
14802 if (!intel_syntax
|| havebase
)
14804 *obufp
++ = separator_char
;
14808 oappend (address_mode
== mode_64bit
&& !addr32flag
14809 ? indexes64
[vindex
] : indexes32
[vindex
]);
14811 oappend (address_mode
== mode_64bit
&& !addr32flag
14812 ? index64
: index32
);
14814 *obufp
++ = scale_char
;
14816 sprintf (scratchbuf
, "%d", 1 << scale
);
14817 oappend (scratchbuf
);
14821 && (disp
|| modrm
.mod
!= 0 || base
== 5))
14823 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
14828 else if (modrm
.mod
!= 1 && disp
!= -disp
)
14832 disp
= - (bfd_signed_vma
) disp
;
14836 print_displacement (scratchbuf
, disp
);
14838 print_operand_value (scratchbuf
, 1, disp
);
14839 oappend (scratchbuf
);
14842 *obufp
++ = close_char
;
14845 else if (intel_syntax
)
14847 if (modrm
.mod
!= 0 || base
== 5)
14849 if (!active_seg_prefix
)
14851 oappend (names_seg
[ds_reg
- es_reg
]);
14854 print_operand_value (scratchbuf
, 1, disp
);
14855 oappend (scratchbuf
);
14859 else if (bytemode
== v_bnd_mode
14860 || bytemode
== v_bndmk_mode
14861 || bytemode
== bnd_mode
14862 || bytemode
== bnd_swap_mode
)
14869 /* 16 bit address mode */
14870 used_prefixes
|= prefixes
& PREFIX_ADDR
;
14877 if ((disp
& 0x8000) != 0)
14882 FETCH_DATA (the_info
, codep
+ 1);
14884 if ((disp
& 0x80) != 0)
14886 if (vex
.evex
&& shift
> 0)
14891 if ((disp
& 0x8000) != 0)
14897 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
14899 print_displacement (scratchbuf
, disp
);
14900 oappend (scratchbuf
);
14903 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
14905 *obufp
++ = open_char
;
14907 oappend (index16
[modrm
.rm
]);
14909 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
14911 if ((bfd_signed_vma
) disp
>= 0)
14916 else if (modrm
.mod
!= 1)
14920 disp
= - (bfd_signed_vma
) disp
;
14923 print_displacement (scratchbuf
, disp
);
14924 oappend (scratchbuf
);
14927 *obufp
++ = close_char
;
14930 else if (intel_syntax
)
14932 if (!active_seg_prefix
)
14934 oappend (names_seg
[ds_reg
- es_reg
]);
14937 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
14938 oappend (scratchbuf
);
14941 if (vex
.evex
&& vex
.b
14942 && (bytemode
== x_mode
14943 || bytemode
== xmmq_mode
14944 || bytemode
== evex_half_bcst_xmmq_mode
))
14947 || bytemode
== xmmq_mode
14948 || bytemode
== evex_half_bcst_xmmq_mode
)
14950 switch (vex
.length
)
14953 oappend ("{1to2}");
14956 oappend ("{1to4}");
14959 oappend ("{1to8}");
14967 switch (vex
.length
)
14970 oappend ("{1to4}");
14973 oappend ("{1to8}");
14976 oappend ("{1to16}");
14986 OP_E (int bytemode
, int sizeflag
)
14988 /* Skip mod/rm byte. */
14992 if (modrm
.mod
== 3)
14993 OP_E_register (bytemode
, sizeflag
);
14995 OP_E_memory (bytemode
, sizeflag
);
14999 OP_G (int bytemode
, int sizeflag
)
15002 const char **names
;
15012 oappend (names8rex
[modrm
.reg
+ add
]);
15014 oappend (names8
[modrm
.reg
+ add
]);
15017 oappend (names16
[modrm
.reg
+ add
]);
15022 oappend (names32
[modrm
.reg
+ add
]);
15025 oappend (names64
[modrm
.reg
+ add
]);
15028 if (modrm
.reg
> 0x3)
15033 oappend (names_bnd
[modrm
.reg
]);
15043 oappend (names64
[modrm
.reg
+ add
]);
15046 if ((sizeflag
& DFLAG
)
15047 || (bytemode
!= v_mode
&& bytemode
!= movsxd_mode
))
15048 oappend (names32
[modrm
.reg
+ add
]);
15050 oappend (names16
[modrm
.reg
+ add
]);
15051 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15055 names
= (address_mode
== mode_64bit
15056 ? names64
: names32
);
15057 if (!(prefixes
& PREFIX_ADDR
))
15059 if (address_mode
== mode_16bit
)
15064 /* Remove "addr16/addr32". */
15065 all_prefixes
[last_addr_prefix
] = 0;
15066 names
= (address_mode
!= mode_32bit
15067 ? names32
: names16
);
15068 used_prefixes
|= PREFIX_ADDR
;
15070 oappend (names
[modrm
.reg
+ add
]);
15073 if (address_mode
== mode_64bit
)
15074 oappend (names64
[modrm
.reg
+ add
]);
15076 oappend (names32
[modrm
.reg
+ add
]);
15080 if ((modrm
.reg
+ add
) > 0x7)
15085 oappend (names_mask
[modrm
.reg
+ add
]);
15088 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15101 FETCH_DATA (the_info
, codep
+ 8);
15102 a
= *codep
++ & 0xff;
15103 a
|= (*codep
++ & 0xff) << 8;
15104 a
|= (*codep
++ & 0xff) << 16;
15105 a
|= (*codep
++ & 0xffu
) << 24;
15106 b
= *codep
++ & 0xff;
15107 b
|= (*codep
++ & 0xff) << 8;
15108 b
|= (*codep
++ & 0xff) << 16;
15109 b
|= (*codep
++ & 0xffu
) << 24;
15110 x
= a
+ ((bfd_vma
) b
<< 32);
15118 static bfd_signed_vma
15121 bfd_signed_vma x
= 0;
15123 FETCH_DATA (the_info
, codep
+ 4);
15124 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15125 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15126 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15127 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15131 static bfd_signed_vma
15134 bfd_signed_vma x
= 0;
15136 FETCH_DATA (the_info
, codep
+ 4);
15137 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15138 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15139 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15140 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15142 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
15152 FETCH_DATA (the_info
, codep
+ 2);
15153 x
= *codep
++ & 0xff;
15154 x
|= (*codep
++ & 0xff) << 8;
15159 set_op (bfd_vma op
, int riprel
)
15161 op_index
[op_ad
] = op_ad
;
15162 if (address_mode
== mode_64bit
)
15164 op_address
[op_ad
] = op
;
15165 op_riprel
[op_ad
] = riprel
;
15169 /* Mask to get a 32-bit address. */
15170 op_address
[op_ad
] = op
& 0xffffffff;
15171 op_riprel
[op_ad
] = riprel
& 0xffffffff;
15176 OP_REG (int code
, int sizeflag
)
15183 case es_reg
: case ss_reg
: case cs_reg
:
15184 case ds_reg
: case fs_reg
: case gs_reg
:
15185 oappend (names_seg
[code
- es_reg
]);
15197 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15198 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15199 s
= names16
[code
- ax_reg
+ add
];
15201 case ah_reg
: case ch_reg
: case dh_reg
: case bh_reg
:
15203 /* Fall through. */
15204 case al_reg
: case cl_reg
: case dl_reg
: case bl_reg
:
15206 s
= names8rex
[code
- al_reg
+ add
];
15208 s
= names8
[code
- al_reg
];
15210 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
15211 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
15212 if (address_mode
== mode_64bit
15213 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15215 s
= names64
[code
- rAX_reg
+ add
];
15218 code
+= eAX_reg
- rAX_reg
;
15219 /* Fall through. */
15220 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15221 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15224 s
= names64
[code
- eAX_reg
+ add
];
15227 if (sizeflag
& DFLAG
)
15228 s
= names32
[code
- eAX_reg
+ add
];
15230 s
= names16
[code
- eAX_reg
+ add
];
15231 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15235 s
= INTERNAL_DISASSEMBLER_ERROR
;
15242 OP_IMREG (int code
, int sizeflag
)
15254 case al_reg
: case cl_reg
:
15255 s
= names8
[code
- al_reg
];
15264 /* Fall through. */
15265 case z_mode_ax_reg
:
15266 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
15270 if (!(rex
& REX_W
))
15271 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15274 s
= INTERNAL_DISASSEMBLER_ERROR
;
15281 OP_I (int bytemode
, int sizeflag
)
15284 bfd_signed_vma mask
= -1;
15289 FETCH_DATA (the_info
, codep
+ 1);
15299 if (sizeflag
& DFLAG
)
15309 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15325 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15330 scratchbuf
[0] = '$';
15331 print_operand_value (scratchbuf
+ 1, 1, op
);
15332 oappend_maybe_intel (scratchbuf
);
15333 scratchbuf
[0] = '\0';
15337 OP_I64 (int bytemode
, int sizeflag
)
15339 if (bytemode
!= v_mode
|| address_mode
!= mode_64bit
|| !(rex
& REX_W
))
15341 OP_I (bytemode
, sizeflag
);
15347 scratchbuf
[0] = '$';
15348 print_operand_value (scratchbuf
+ 1, 1, get64 ());
15349 oappend_maybe_intel (scratchbuf
);
15350 scratchbuf
[0] = '\0';
15354 OP_sI (int bytemode
, int sizeflag
)
15362 FETCH_DATA (the_info
, codep
+ 1);
15364 if ((op
& 0x80) != 0)
15366 if (bytemode
== b_T_mode
)
15368 if (address_mode
!= mode_64bit
15369 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15371 /* The operand-size prefix is overridden by a REX prefix. */
15372 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15380 if (!(rex
& REX_W
))
15382 if (sizeflag
& DFLAG
)
15390 /* The operand-size prefix is overridden by a REX prefix. */
15391 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15397 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15401 scratchbuf
[0] = '$';
15402 print_operand_value (scratchbuf
+ 1, 1, op
);
15403 oappend_maybe_intel (scratchbuf
);
15407 OP_J (int bytemode
, int sizeflag
)
15411 bfd_vma segment
= 0;
15416 FETCH_DATA (the_info
, codep
+ 1);
15418 if ((disp
& 0x80) != 0)
15422 if (isa64
!= intel64
)
15425 if ((sizeflag
& DFLAG
)
15426 || (address_mode
== mode_64bit
15427 && ((isa64
== intel64
&& bytemode
!= dqw_mode
)
15428 || (rex
& REX_W
))))
15433 if ((disp
& 0x8000) != 0)
15435 /* In 16bit mode, address is wrapped around at 64k within
15436 the same segment. Otherwise, a data16 prefix on a jump
15437 instruction means that the pc is masked to 16 bits after
15438 the displacement is added! */
15440 if ((prefixes
& PREFIX_DATA
) == 0)
15441 segment
= ((start_pc
+ (codep
- start_codep
))
15442 & ~((bfd_vma
) 0xffff));
15444 if (address_mode
!= mode_64bit
15445 || (isa64
!= intel64
&& !(rex
& REX_W
)))
15446 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15449 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15452 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
15454 print_operand_value (scratchbuf
, 1, disp
);
15455 oappend (scratchbuf
);
15459 OP_SEG (int bytemode
, int sizeflag
)
15461 if (bytemode
== w_mode
)
15462 oappend (names_seg
[modrm
.reg
]);
15464 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
15468 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
15472 if (sizeflag
& DFLAG
)
15482 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15484 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
15486 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
15487 oappend (scratchbuf
);
15491 OP_OFF (int bytemode
, int sizeflag
)
15495 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
15496 intel_operand_size (bytemode
, sizeflag
);
15499 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15506 if (!active_seg_prefix
)
15508 oappend (names_seg
[ds_reg
- es_reg
]);
15512 print_operand_value (scratchbuf
, 1, off
);
15513 oappend (scratchbuf
);
15517 OP_OFF64 (int bytemode
, int sizeflag
)
15521 if (address_mode
!= mode_64bit
15522 || (prefixes
& PREFIX_ADDR
))
15524 OP_OFF (bytemode
, sizeflag
);
15528 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
15529 intel_operand_size (bytemode
, sizeflag
);
15536 if (!active_seg_prefix
)
15538 oappend (names_seg
[ds_reg
- es_reg
]);
15542 print_operand_value (scratchbuf
, 1, off
);
15543 oappend (scratchbuf
);
15547 ptr_reg (int code
, int sizeflag
)
15551 *obufp
++ = open_char
;
15552 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
15553 if (address_mode
== mode_64bit
)
15555 if (!(sizeflag
& AFLAG
))
15556 s
= names32
[code
- eAX_reg
];
15558 s
= names64
[code
- eAX_reg
];
15560 else if (sizeflag
& AFLAG
)
15561 s
= names32
[code
- eAX_reg
];
15563 s
= names16
[code
- eAX_reg
];
15565 *obufp
++ = close_char
;
15570 OP_ESreg (int code
, int sizeflag
)
15576 case 0x6d: /* insw/insl */
15577 intel_operand_size (z_mode
, sizeflag
);
15579 case 0xa5: /* movsw/movsl/movsq */
15580 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15581 case 0xab: /* stosw/stosl */
15582 case 0xaf: /* scasw/scasl */
15583 intel_operand_size (v_mode
, sizeflag
);
15586 intel_operand_size (b_mode
, sizeflag
);
15589 oappend_maybe_intel ("%es:");
15590 ptr_reg (code
, sizeflag
);
15594 OP_DSreg (int code
, int sizeflag
)
15600 case 0x6f: /* outsw/outsl */
15601 intel_operand_size (z_mode
, sizeflag
);
15603 case 0xa5: /* movsw/movsl/movsq */
15604 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15605 case 0xad: /* lodsw/lodsl/lodsq */
15606 intel_operand_size (v_mode
, sizeflag
);
15609 intel_operand_size (b_mode
, sizeflag
);
15612 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15613 default segment register DS is printed. */
15614 if (!active_seg_prefix
)
15615 active_seg_prefix
= PREFIX_DS
;
15617 ptr_reg (code
, sizeflag
);
15621 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15629 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
15631 all_prefixes
[last_lock_prefix
] = 0;
15632 used_prefixes
|= PREFIX_LOCK
;
15637 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
15638 oappend_maybe_intel (scratchbuf
);
15642 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15651 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
15653 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
15654 oappend (scratchbuf
);
15658 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15660 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
15661 oappend_maybe_intel (scratchbuf
);
15665 OP_R (int bytemode
, int sizeflag
)
15667 /* Skip mod/rm byte. */
15670 OP_E_register (bytemode
, sizeflag
);
15674 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15676 int reg
= modrm
.reg
;
15677 const char **names
;
15679 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15680 if (prefixes
& PREFIX_DATA
)
15689 oappend (names
[reg
]);
15693 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15695 int reg
= modrm
.reg
;
15696 const char **names
;
15708 && bytemode
!= xmm_mode
15709 && bytemode
!= xmmq_mode
15710 && bytemode
!= evex_half_bcst_xmmq_mode
15711 && bytemode
!= ymm_mode
15712 && bytemode
!= tmm_mode
15713 && bytemode
!= scalar_mode
)
15715 switch (vex
.length
)
15722 || (bytemode
!= vex_vsib_q_w_dq_mode
15723 && bytemode
!= vex_vsib_q_w_d_mode
))
15735 else if (bytemode
== xmmq_mode
15736 || bytemode
== evex_half_bcst_xmmq_mode
)
15738 switch (vex
.length
)
15751 else if (bytemode
== tmm_mode
)
15761 else if (bytemode
== ymm_mode
)
15765 oappend (names
[reg
]);
15769 OP_EM (int bytemode
, int sizeflag
)
15772 const char **names
;
15774 if (modrm
.mod
!= 3)
15777 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
15779 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15780 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15782 OP_E (bytemode
, sizeflag
);
15786 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
15789 /* Skip mod/rm byte. */
15792 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15794 if (prefixes
& PREFIX_DATA
)
15803 oappend (names
[reg
]);
15806 /* cvt* are the only instructions in sse2 which have
15807 both SSE and MMX operands and also have 0x66 prefix
15808 in their opcode. 0x66 was originally used to differentiate
15809 between SSE and MMX instruction(operands). So we have to handle the
15810 cvt* separately using OP_EMC and OP_MXC */
15812 OP_EMC (int bytemode
, int sizeflag
)
15814 if (modrm
.mod
!= 3)
15816 if (intel_syntax
&& bytemode
== v_mode
)
15818 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15819 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15821 OP_E (bytemode
, sizeflag
);
15825 /* Skip mod/rm byte. */
15828 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15829 oappend (names_mm
[modrm
.rm
]);
15833 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15835 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15836 oappend (names_mm
[modrm
.reg
]);
15840 OP_EX (int bytemode
, int sizeflag
)
15843 const char **names
;
15845 /* Skip mod/rm byte. */
15849 if (modrm
.mod
!= 3)
15851 OP_E_memory (bytemode
, sizeflag
);
15866 if ((sizeflag
& SUFFIX_ALWAYS
)
15867 && (bytemode
== x_swap_mode
15868 || bytemode
== d_swap_mode
15869 || bytemode
== d_scalar_swap_mode
15870 || bytemode
== q_swap_mode
15871 || bytemode
== q_scalar_swap_mode
))
15875 && bytemode
!= xmm_mode
15876 && bytemode
!= xmmdw_mode
15877 && bytemode
!= xmmqd_mode
15878 && bytemode
!= xmm_mb_mode
15879 && bytemode
!= xmm_mw_mode
15880 && bytemode
!= xmm_md_mode
15881 && bytemode
!= xmm_mq_mode
15882 && bytemode
!= xmmq_mode
15883 && bytemode
!= evex_half_bcst_xmmq_mode
15884 && bytemode
!= ymm_mode
15885 && bytemode
!= tmm_mode
15886 && bytemode
!= d_scalar_swap_mode
15887 && bytemode
!= q_scalar_swap_mode
15888 && bytemode
!= vex_scalar_w_dq_mode
)
15890 switch (vex
.length
)
15905 else if (bytemode
== xmmq_mode
15906 || bytemode
== evex_half_bcst_xmmq_mode
)
15908 switch (vex
.length
)
15921 else if (bytemode
== tmm_mode
)
15931 else if (bytemode
== ymm_mode
)
15935 oappend (names
[reg
]);
15939 OP_MS (int bytemode
, int sizeflag
)
15941 if (modrm
.mod
== 3)
15942 OP_EM (bytemode
, sizeflag
);
15948 OP_XS (int bytemode
, int sizeflag
)
15950 if (modrm
.mod
== 3)
15951 OP_EX (bytemode
, sizeflag
);
15957 OP_M (int bytemode
, int sizeflag
)
15959 if (modrm
.mod
== 3)
15960 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15963 OP_E (bytemode
, sizeflag
);
15967 OP_0f07 (int bytemode
, int sizeflag
)
15969 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
15972 OP_E (bytemode
, sizeflag
);
15975 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15976 32bit mode and "xchg %rax,%rax" in 64bit mode. */
15979 NOP_Fixup1 (int bytemode
, int sizeflag
)
15981 if ((prefixes
& PREFIX_DATA
) != 0
15984 && address_mode
== mode_64bit
))
15985 OP_REG (bytemode
, sizeflag
);
15987 strcpy (obuf
, "nop");
15991 NOP_Fixup2 (int bytemode
, int sizeflag
)
15993 if ((prefixes
& PREFIX_DATA
) != 0
15996 && address_mode
== mode_64bit
))
15997 OP_IMREG (bytemode
, sizeflag
);
16000 static const char *const Suffix3DNow
[] = {
16001 /* 00 */ NULL
, NULL
, NULL
, NULL
,
16002 /* 04 */ NULL
, NULL
, NULL
, NULL
,
16003 /* 08 */ NULL
, NULL
, NULL
, NULL
,
16004 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
16005 /* 10 */ NULL
, NULL
, NULL
, NULL
,
16006 /* 14 */ NULL
, NULL
, NULL
, NULL
,
16007 /* 18 */ NULL
, NULL
, NULL
, NULL
,
16008 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
16009 /* 20 */ NULL
, NULL
, NULL
, NULL
,
16010 /* 24 */ NULL
, NULL
, NULL
, NULL
,
16011 /* 28 */ NULL
, NULL
, NULL
, NULL
,
16012 /* 2C */ NULL
, NULL
, NULL
, NULL
,
16013 /* 30 */ NULL
, NULL
, NULL
, NULL
,
16014 /* 34 */ NULL
, NULL
, NULL
, NULL
,
16015 /* 38 */ NULL
, NULL
, NULL
, NULL
,
16016 /* 3C */ NULL
, NULL
, NULL
, NULL
,
16017 /* 40 */ NULL
, NULL
, NULL
, NULL
,
16018 /* 44 */ NULL
, NULL
, NULL
, NULL
,
16019 /* 48 */ NULL
, NULL
, NULL
, NULL
,
16020 /* 4C */ NULL
, NULL
, NULL
, NULL
,
16021 /* 50 */ NULL
, NULL
, NULL
, NULL
,
16022 /* 54 */ NULL
, NULL
, NULL
, NULL
,
16023 /* 58 */ NULL
, NULL
, NULL
, NULL
,
16024 /* 5C */ NULL
, NULL
, NULL
, NULL
,
16025 /* 60 */ NULL
, NULL
, NULL
, NULL
,
16026 /* 64 */ NULL
, NULL
, NULL
, NULL
,
16027 /* 68 */ NULL
, NULL
, NULL
, NULL
,
16028 /* 6C */ NULL
, NULL
, NULL
, NULL
,
16029 /* 70 */ NULL
, NULL
, NULL
, NULL
,
16030 /* 74 */ NULL
, NULL
, NULL
, NULL
,
16031 /* 78 */ NULL
, NULL
, NULL
, NULL
,
16032 /* 7C */ NULL
, NULL
, NULL
, NULL
,
16033 /* 80 */ NULL
, NULL
, NULL
, NULL
,
16034 /* 84 */ NULL
, NULL
, NULL
, NULL
,
16035 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
16036 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
16037 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
16038 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
16039 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
16040 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
16041 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
16042 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
16043 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
16044 /* AC */ NULL
, NULL
, "pfacc", NULL
,
16045 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
16046 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
16047 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
16048 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
16049 /* C0 */ NULL
, NULL
, NULL
, NULL
,
16050 /* C4 */ NULL
, NULL
, NULL
, NULL
,
16051 /* C8 */ NULL
, NULL
, NULL
, NULL
,
16052 /* CC */ NULL
, NULL
, NULL
, NULL
,
16053 /* D0 */ NULL
, NULL
, NULL
, NULL
,
16054 /* D4 */ NULL
, NULL
, NULL
, NULL
,
16055 /* D8 */ NULL
, NULL
, NULL
, NULL
,
16056 /* DC */ NULL
, NULL
, NULL
, NULL
,
16057 /* E0 */ NULL
, NULL
, NULL
, NULL
,
16058 /* E4 */ NULL
, NULL
, NULL
, NULL
,
16059 /* E8 */ NULL
, NULL
, NULL
, NULL
,
16060 /* EC */ NULL
, NULL
, NULL
, NULL
,
16061 /* F0 */ NULL
, NULL
, NULL
, NULL
,
16062 /* F4 */ NULL
, NULL
, NULL
, NULL
,
16063 /* F8 */ NULL
, NULL
, NULL
, NULL
,
16064 /* FC */ NULL
, NULL
, NULL
, NULL
,
16068 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16070 const char *mnemonic
;
16072 FETCH_DATA (the_info
, codep
+ 1);
16073 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16074 place where an 8-bit immediate would normally go. ie. the last
16075 byte of the instruction. */
16076 obufp
= mnemonicendp
;
16077 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
16079 oappend (mnemonic
);
16082 /* Since a variable sized modrm/sib chunk is between the start
16083 of the opcode (0x0f0f) and the opcode suffix, we need to do
16084 all the modrm processing first, and don't know until now that
16085 we have a bad opcode. This necessitates some cleaning up. */
16086 op_out
[0][0] = '\0';
16087 op_out
[1][0] = '\0';
16090 mnemonicendp
= obufp
;
16093 static const struct op simd_cmp_op
[] =
16095 { STRING_COMMA_LEN ("eq") },
16096 { STRING_COMMA_LEN ("lt") },
16097 { STRING_COMMA_LEN ("le") },
16098 { STRING_COMMA_LEN ("unord") },
16099 { STRING_COMMA_LEN ("neq") },
16100 { STRING_COMMA_LEN ("nlt") },
16101 { STRING_COMMA_LEN ("nle") },
16102 { STRING_COMMA_LEN ("ord") }
16105 static const struct op vex_cmp_op
[] =
16107 { STRING_COMMA_LEN ("eq_uq") },
16108 { STRING_COMMA_LEN ("nge") },
16109 { STRING_COMMA_LEN ("ngt") },
16110 { STRING_COMMA_LEN ("false") },
16111 { STRING_COMMA_LEN ("neq_oq") },
16112 { STRING_COMMA_LEN ("ge") },
16113 { STRING_COMMA_LEN ("gt") },
16114 { STRING_COMMA_LEN ("true") },
16115 { STRING_COMMA_LEN ("eq_os") },
16116 { STRING_COMMA_LEN ("lt_oq") },
16117 { STRING_COMMA_LEN ("le_oq") },
16118 { STRING_COMMA_LEN ("unord_s") },
16119 { STRING_COMMA_LEN ("neq_us") },
16120 { STRING_COMMA_LEN ("nlt_uq") },
16121 { STRING_COMMA_LEN ("nle_uq") },
16122 { STRING_COMMA_LEN ("ord_s") },
16123 { STRING_COMMA_LEN ("eq_us") },
16124 { STRING_COMMA_LEN ("nge_uq") },
16125 { STRING_COMMA_LEN ("ngt_uq") },
16126 { STRING_COMMA_LEN ("false_os") },
16127 { STRING_COMMA_LEN ("neq_os") },
16128 { STRING_COMMA_LEN ("ge_oq") },
16129 { STRING_COMMA_LEN ("gt_oq") },
16130 { STRING_COMMA_LEN ("true_us") },
16134 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16136 unsigned int cmp_type
;
16138 FETCH_DATA (the_info
, codep
+ 1);
16139 cmp_type
= *codep
++ & 0xff;
16140 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
16143 char *p
= mnemonicendp
- 2;
16147 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16148 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16151 && cmp_type
< ARRAY_SIZE (simd_cmp_op
) + ARRAY_SIZE (vex_cmp_op
))
16154 char *p
= mnemonicendp
- 2;
16158 cmp_type
-= ARRAY_SIZE (simd_cmp_op
);
16159 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
16160 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
16164 /* We have a reserved extension byte. Output it directly. */
16165 scratchbuf
[0] = '$';
16166 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16167 oappend_maybe_intel (scratchbuf
);
16168 scratchbuf
[0] = '\0';
16173 OP_Mwait (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16175 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
16178 strcpy (op_out
[0], names32
[0]);
16179 strcpy (op_out
[1], names32
[1]);
16180 if (bytemode
== eBX_reg
)
16181 strcpy (op_out
[2], names32
[3]);
16182 two_source_ops
= 1;
16184 /* Skip mod/rm byte. */
16190 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
16191 int sizeflag ATTRIBUTE_UNUSED
)
16193 /* monitor %{e,r,}ax,%ecx,%edx" */
16196 const char **names
= (address_mode
== mode_64bit
16197 ? names64
: names32
);
16199 if (prefixes
& PREFIX_ADDR
)
16201 /* Remove "addr16/addr32". */
16202 all_prefixes
[last_addr_prefix
] = 0;
16203 names
= (address_mode
!= mode_32bit
16204 ? names32
: names16
);
16205 used_prefixes
|= PREFIX_ADDR
;
16207 else if (address_mode
== mode_16bit
)
16209 strcpy (op_out
[0], names
[0]);
16210 strcpy (op_out
[1], names32
[1]);
16211 strcpy (op_out
[2], names32
[2]);
16212 two_source_ops
= 1;
16214 /* Skip mod/rm byte. */
16222 /* Throw away prefixes and 1st. opcode byte. */
16223 codep
= insn_codep
+ 1;
16228 REP_Fixup (int bytemode
, int sizeflag
)
16230 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16232 if (prefixes
& PREFIX_REPZ
)
16233 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
16240 OP_IMREG (bytemode
, sizeflag
);
16243 OP_ESreg (bytemode
, sizeflag
);
16246 OP_DSreg (bytemode
, sizeflag
);
16255 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16257 if ( isa64
!= amd64
)
16262 mnemonicendp
= obufp
;
16266 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16270 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16272 if (prefixes
& PREFIX_REPNZ
)
16273 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
16276 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16280 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16281 int sizeflag ATTRIBUTE_UNUSED
)
16283 if (active_seg_prefix
== PREFIX_DS
16284 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
16286 /* NOTRACK prefix is only valid on indirect branch instructions.
16287 NB: DATA prefix is unsupported for Intel64. */
16288 active_seg_prefix
= 0;
16289 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
16293 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16294 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16298 HLE_Fixup1 (int bytemode
, int sizeflag
)
16301 && (prefixes
& PREFIX_LOCK
) != 0)
16303 if (prefixes
& PREFIX_REPZ
)
16304 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16305 if (prefixes
& PREFIX_REPNZ
)
16306 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16309 OP_E (bytemode
, sizeflag
);
16312 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16313 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
16317 HLE_Fixup2 (int bytemode
, int sizeflag
)
16319 if (modrm
.mod
!= 3)
16321 if (prefixes
& PREFIX_REPZ
)
16322 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16323 if (prefixes
& PREFIX_REPNZ
)
16324 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16327 OP_E (bytemode
, sizeflag
);
16330 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
16331 "xrelease" for memory operand. No check for LOCK prefix. */
16334 HLE_Fixup3 (int bytemode
, int sizeflag
)
16337 && last_repz_prefix
> last_repnz_prefix
16338 && (prefixes
& PREFIX_REPZ
) != 0)
16339 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16341 OP_E (bytemode
, sizeflag
);
16345 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
16350 /* Change cmpxchg8b to cmpxchg16b. */
16351 char *p
= mnemonicendp
- 2;
16352 mnemonicendp
= stpcpy (p
, "16b");
16355 else if ((prefixes
& PREFIX_LOCK
) != 0)
16357 if (prefixes
& PREFIX_REPZ
)
16358 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16359 if (prefixes
& PREFIX_REPNZ
)
16360 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16363 OP_M (bytemode
, sizeflag
);
16367 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
16369 const char **names
;
16373 switch (vex
.length
)
16387 oappend (names
[reg
]);
16391 FXSAVE_Fixup (int bytemode
, int sizeflag
)
16393 /* Add proper suffix to "fxsave" and "fxrstor". */
16397 char *p
= mnemonicendp
;
16403 OP_M (bytemode
, sizeflag
);
16406 /* Display the destination register operand for instructions with
16410 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16413 const char **names
;
16421 reg
= vex
.register_specifier
;
16422 vex
.register_specifier
= 0;
16423 if (address_mode
!= mode_64bit
)
16425 else if (vex
.evex
&& !vex
.v
)
16428 if (bytemode
== vex_scalar_mode
)
16430 oappend (names_xmm
[reg
]);
16434 if (bytemode
== tmm_mode
)
16436 /* All 3 TMM registers must be distinct. */
16441 /* This must be the 3rd operand. */
16442 if (obufp
!= op_out
[2])
16444 oappend (names_tmm
[reg
]);
16445 if (reg
== modrm
.reg
|| reg
== modrm
.rm
)
16446 strcpy (obufp
, "/(bad)");
16449 if (modrm
.reg
== modrm
.rm
|| modrm
.reg
== reg
|| modrm
.rm
== reg
)
16452 && (modrm
.reg
== modrm
.rm
|| modrm
.reg
== reg
))
16453 strcat (op_out
[0], "/(bad)");
16455 && (modrm
.rm
== modrm
.reg
|| modrm
.rm
== reg
))
16456 strcat (op_out
[1], "/(bad)");
16462 switch (vex
.length
)
16469 case vex_vsib_q_w_dq_mode
:
16470 case vex_vsib_q_w_d_mode
:
16486 names
= names_mask
;
16500 case vex_vsib_q_w_dq_mode
:
16501 case vex_vsib_q_w_d_mode
:
16502 names
= vex
.w
? names_ymm
: names_xmm
;
16511 names
= names_mask
;
16514 /* See PR binutils/20893 for a reproducer. */
16526 oappend (names
[reg
]);
16530 OP_VexW (int bytemode
, int sizeflag
)
16532 OP_VEX (bytemode
, sizeflag
);
16536 /* Swap 2nd and 3rd operands. */
16537 strcpy (scratchbuf
, op_out
[2]);
16538 strcpy (op_out
[2], op_out
[1]);
16539 strcpy (op_out
[1], scratchbuf
);
16544 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16547 const char **names
= names_xmm
;
16549 FETCH_DATA (the_info
, codep
+ 1);
16552 if (bytemode
!= x_mode
&& bytemode
!= scalar_mode
)
16556 if (address_mode
!= mode_64bit
)
16559 if (bytemode
== x_mode
&& vex
.length
== 256)
16562 oappend (names
[reg
]);
16566 /* Swap 3rd and 4th operands. */
16567 strcpy (scratchbuf
, op_out
[3]);
16568 strcpy (op_out
[3], op_out
[2]);
16569 strcpy (op_out
[2], scratchbuf
);
16574 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED
,
16575 int sizeflag ATTRIBUTE_UNUSED
)
16577 scratchbuf
[0] = '$';
16578 print_operand_value (scratchbuf
+ 1, 1, codep
[-1] & 0xf);
16579 oappend_maybe_intel (scratchbuf
);
16583 OP_EX_Vex (int bytemode
, int sizeflag
)
16585 if (modrm
.mod
!= 3)
16587 OP_EX (bytemode
, sizeflag
);
16591 OP_XMM_Vex (int bytemode
, int sizeflag
)
16593 if (modrm
.mod
!= 3)
16595 OP_XMM (bytemode
, sizeflag
);
16599 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16600 int sizeflag ATTRIBUTE_UNUSED
)
16602 unsigned int cmp_type
;
16607 FETCH_DATA (the_info
, codep
+ 1);
16608 cmp_type
= *codep
++ & 0xff;
16609 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16610 If it's the case, print suffix, otherwise - print the immediate. */
16611 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
16616 char *p
= mnemonicendp
- 2;
16618 /* vpcmp* can have both one- and two-lettered suffix. */
16632 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16633 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16637 /* We have a reserved extension byte. Output it directly. */
16638 scratchbuf
[0] = '$';
16639 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16640 oappend_maybe_intel (scratchbuf
);
16641 scratchbuf
[0] = '\0';
16645 static const struct op xop_cmp_op
[] =
16647 { STRING_COMMA_LEN ("lt") },
16648 { STRING_COMMA_LEN ("le") },
16649 { STRING_COMMA_LEN ("gt") },
16650 { STRING_COMMA_LEN ("ge") },
16651 { STRING_COMMA_LEN ("eq") },
16652 { STRING_COMMA_LEN ("neq") },
16653 { STRING_COMMA_LEN ("false") },
16654 { STRING_COMMA_LEN ("true") }
16658 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16659 int sizeflag ATTRIBUTE_UNUSED
)
16661 unsigned int cmp_type
;
16663 FETCH_DATA (the_info
, codep
+ 1);
16664 cmp_type
= *codep
++ & 0xff;
16665 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
16668 char *p
= mnemonicendp
- 2;
16670 /* vpcom* can have both one- and two-lettered suffix. */
16684 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
16685 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
16689 /* We have a reserved extension byte. Output it directly. */
16690 scratchbuf
[0] = '$';
16691 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16692 oappend_maybe_intel (scratchbuf
);
16693 scratchbuf
[0] = '\0';
16697 static const struct op pclmul_op
[] =
16699 { STRING_COMMA_LEN ("lql") },
16700 { STRING_COMMA_LEN ("hql") },
16701 { STRING_COMMA_LEN ("lqh") },
16702 { STRING_COMMA_LEN ("hqh") }
16706 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16707 int sizeflag ATTRIBUTE_UNUSED
)
16709 unsigned int pclmul_type
;
16711 FETCH_DATA (the_info
, codep
+ 1);
16712 pclmul_type
= *codep
++ & 0xff;
16713 switch (pclmul_type
)
16724 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
16727 char *p
= mnemonicendp
- 3;
16732 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
16733 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
16737 /* We have a reserved extension byte. Output it directly. */
16738 scratchbuf
[0] = '$';
16739 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
16740 oappend_maybe_intel (scratchbuf
);
16741 scratchbuf
[0] = '\0';
16746 MOVSXD_Fixup (int bytemode
, int sizeflag
)
16748 /* Add proper suffix to "movsxd". */
16749 char *p
= mnemonicendp
;
16774 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16781 OP_E (bytemode
, sizeflag
);
16785 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16788 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
16792 if ((rex
& REX_R
) != 0 || !vex
.r
)
16798 oappend (names_mask
[modrm
.reg
]);
16802 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16804 if (modrm
.mod
== 3 && vex
.b
)
16807 case evex_rounding_64_mode
:
16808 if (address_mode
!= mode_64bit
)
16813 /* Fall through. */
16814 case evex_rounding_mode
:
16815 oappend (names_rounding
[vex
.ll
]);
16817 case evex_sae_mode
: