1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2020 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
44 static int print_insn (bfd_vma
, disassemble_info
*);
45 static void dofloat (int);
46 static void OP_ST (int, int);
47 static void OP_STi (int, int);
48 static int putop (const char *, int);
49 static void oappend (const char *);
50 static void append_seg (void);
51 static void OP_indirE (int, int);
52 static void print_operand_value (char *, int, bfd_vma
);
53 static void OP_E_register (int, int);
54 static void OP_E_memory (int, int);
55 static void print_displacement (char *, bfd_vma
);
56 static void OP_E (int, int);
57 static void OP_G (int, int);
58 static bfd_vma
get64 (void);
59 static bfd_signed_vma
get32 (void);
60 static bfd_signed_vma
get32s (void);
61 static int get16 (void);
62 static void set_op (bfd_vma
, int);
63 static void OP_Skip_MODRM (int, int);
64 static void OP_REG (int, int);
65 static void OP_IMREG (int, int);
66 static void OP_I (int, int);
67 static void OP_I64 (int, int);
68 static void OP_sI (int, int);
69 static void OP_J (int, int);
70 static void OP_SEG (int, int);
71 static void OP_DIR (int, int);
72 static void OP_OFF (int, int);
73 static void OP_OFF64 (int, int);
74 static void ptr_reg (int, int);
75 static void OP_ESreg (int, int);
76 static void OP_DSreg (int, int);
77 static void OP_C (int, int);
78 static void OP_D (int, int);
79 static void OP_T (int, int);
80 static void OP_R (int, int);
81 static void OP_MMX (int, int);
82 static void OP_XMM (int, int);
83 static void OP_EM (int, int);
84 static void OP_EX (int, int);
85 static void OP_EMC (int,int);
86 static void OP_MXC (int,int);
87 static void OP_MS (int, int);
88 static void OP_XS (int, int);
89 static void OP_M (int, int);
90 static void OP_VEX (int, int);
91 static void OP_VexW (int, int);
92 static void OP_EX_Vex (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_Rounding (int, int);
95 static void OP_REG_VexI4 (int, int);
96 static void OP_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VCMP_Fixup (int, int);
99 static void VPCMP_Fixup (int, int);
100 static void VPCOM_Fixup (int, int);
101 static void OP_0f07 (int, int);
102 static void OP_Monitor (int, int);
103 static void OP_Mwait (int, int);
104 static void NOP_Fixup1 (int, int);
105 static void NOP_Fixup2 (int, int);
106 static void OP_3DNowSuffix (int, int);
107 static void CMP_Fixup (int, int);
108 static void BadOp (void);
109 static void REP_Fixup (int, int);
110 static void SEP_Fixup (int, int);
111 static void BND_Fixup (int, int);
112 static void NOTRACK_Fixup (int, int);
113 static void HLE_Fixup1 (int, int);
114 static void HLE_Fixup2 (int, int);
115 static void HLE_Fixup3 (int, int);
116 static void CMPXCHG8B_Fixup (int, int);
117 static void XMM_Fixup (int, int);
118 static void FXSAVE_Fixup (int, int);
119 static void PCMPESTR_Fixup (int, int);
121 static void MOVBE_Fixup (int, int);
122 static void MOVSXD_Fixup (int, int);
124 static void OP_Mask (int, int);
127 /* Points to first byte not fetched. */
128 bfd_byte
*max_fetched
;
129 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
132 OPCODES_SIGJMP_BUF bailout
;
142 enum address_mode address_mode
;
144 /* Flags for the prefixes for the current instruction. See below. */
147 /* REX prefix the current instruction. See below. */
149 /* Bits of REX we've already used. */
151 /* Mark parts used in the REX prefix. When we are testing for
152 empty prefix (for 8bit register REX extension), just mask it
153 out. Otherwise test for REX bit is excuse for existence of REX
154 only in case value is nonzero. */
155 #define USED_REX(value) \
160 rex_used |= (value) | REX_OPCODE; \
163 rex_used |= REX_OPCODE; \
166 /* Flags for prefixes which we somehow handled when printing the
167 current instruction. */
168 static int used_prefixes
;
170 /* Flags stored in PREFIXES. */
171 #define PREFIX_REPZ 1
172 #define PREFIX_REPNZ 2
173 #define PREFIX_LOCK 4
175 #define PREFIX_SS 0x10
176 #define PREFIX_DS 0x20
177 #define PREFIX_ES 0x40
178 #define PREFIX_FS 0x80
179 #define PREFIX_GS 0x100
180 #define PREFIX_DATA 0x200
181 #define PREFIX_ADDR 0x400
182 #define PREFIX_FWAIT 0x800
184 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
185 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
187 #define FETCH_DATA(info, addr) \
188 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
189 ? 1 : fetch_data ((info), (addr)))
192 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
195 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
196 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
198 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
199 status
= (*info
->read_memory_func
) (start
,
201 addr
- priv
->max_fetched
,
207 /* If we did manage to read at least one byte, then
208 print_insn_i386 will do something sensible. Otherwise, print
209 an error. We do that here because this is where we know
211 if (priv
->max_fetched
== priv
->the_buffer
)
212 (*info
->memory_error_func
) (status
, start
, info
);
213 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
216 priv
->max_fetched
= addr
;
220 /* Possible values for prefix requirement. */
221 #define PREFIX_IGNORED_SHIFT 16
222 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
223 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
224 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
225 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
226 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
228 /* Opcode prefixes. */
229 #define PREFIX_OPCODE (PREFIX_REPZ \
233 /* Prefixes ignored. */
234 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
235 | PREFIX_IGNORED_REPNZ \
236 | PREFIX_IGNORED_DATA)
238 #define XX { NULL, 0 }
239 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
241 #define Eb { OP_E, b_mode }
242 #define Ebnd { OP_E, bnd_mode }
243 #define EbS { OP_E, b_swap_mode }
244 #define EbndS { OP_E, bnd_swap_mode }
245 #define Ev { OP_E, v_mode }
246 #define Eva { OP_E, va_mode }
247 #define Ev_bnd { OP_E, v_bnd_mode }
248 #define EvS { OP_E, v_swap_mode }
249 #define Ed { OP_E, d_mode }
250 #define Edq { OP_E, dq_mode }
251 #define Edqw { OP_E, dqw_mode }
252 #define Edqb { OP_E, dqb_mode }
253 #define Edb { OP_E, db_mode }
254 #define Edw { OP_E, dw_mode }
255 #define Edqd { OP_E, dqd_mode }
256 #define Eq { OP_E, q_mode }
257 #define indirEv { OP_indirE, indir_v_mode }
258 #define indirEp { OP_indirE, f_mode }
259 #define stackEv { OP_E, stack_v_mode }
260 #define Em { OP_E, m_mode }
261 #define Ew { OP_E, w_mode }
262 #define M { OP_M, 0 } /* lea, lgdt, etc. */
263 #define Ma { OP_M, a_mode }
264 #define Mb { OP_M, b_mode }
265 #define Md { OP_M, d_mode }
266 #define Mo { OP_M, o_mode }
267 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
268 #define Mq { OP_M, q_mode }
269 #define Mv_bnd { OP_M, v_bndmk_mode }
270 #define Mx { OP_M, x_mode }
271 #define Mxmm { OP_M, xmm_mode }
272 #define Gb { OP_G, b_mode }
273 #define Gbnd { OP_G, bnd_mode }
274 #define Gv { OP_G, v_mode }
275 #define Gd { OP_G, d_mode }
276 #define Gdq { OP_G, dq_mode }
277 #define Gm { OP_G, m_mode }
278 #define Gva { OP_G, va_mode }
279 #define Gw { OP_G, w_mode }
280 #define Rd { OP_R, d_mode }
281 #define Rdq { OP_R, dq_mode }
282 #define Rm { OP_R, m_mode }
283 #define Ib { OP_I, b_mode }
284 #define sIb { OP_sI, b_mode } /* sign extened byte */
285 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
286 #define Iv { OP_I, v_mode }
287 #define sIv { OP_sI, v_mode }
288 #define Iv64 { OP_I64, v_mode }
289 #define Id { OP_I, d_mode }
290 #define Iw { OP_I, w_mode }
291 #define I1 { OP_I, const_1_mode }
292 #define Jb { OP_J, b_mode }
293 #define Jv { OP_J, v_mode }
294 #define Jdqw { OP_J, dqw_mode }
295 #define Cm { OP_C, m_mode }
296 #define Dm { OP_D, m_mode }
297 #define Td { OP_T, d_mode }
298 #define Skip_MODRM { OP_Skip_MODRM, 0 }
300 #define RMeAX { OP_REG, eAX_reg }
301 #define RMeBX { OP_REG, eBX_reg }
302 #define RMeCX { OP_REG, eCX_reg }
303 #define RMeDX { OP_REG, eDX_reg }
304 #define RMeSP { OP_REG, eSP_reg }
305 #define RMeBP { OP_REG, eBP_reg }
306 #define RMeSI { OP_REG, eSI_reg }
307 #define RMeDI { OP_REG, eDI_reg }
308 #define RMrAX { OP_REG, rAX_reg }
309 #define RMrBX { OP_REG, rBX_reg }
310 #define RMrCX { OP_REG, rCX_reg }
311 #define RMrDX { OP_REG, rDX_reg }
312 #define RMrSP { OP_REG, rSP_reg }
313 #define RMrBP { OP_REG, rBP_reg }
314 #define RMrSI { OP_REG, rSI_reg }
315 #define RMrDI { OP_REG, rDI_reg }
316 #define RMAL { OP_REG, al_reg }
317 #define RMCL { OP_REG, cl_reg }
318 #define RMDL { OP_REG, dl_reg }
319 #define RMBL { OP_REG, bl_reg }
320 #define RMAH { OP_REG, ah_reg }
321 #define RMCH { OP_REG, ch_reg }
322 #define RMDH { OP_REG, dh_reg }
323 #define RMBH { OP_REG, bh_reg }
324 #define RMAX { OP_REG, ax_reg }
325 #define RMDX { OP_REG, dx_reg }
327 #define eAX { OP_IMREG, eAX_reg }
328 #define AL { OP_IMREG, al_reg }
329 #define CL { OP_IMREG, cl_reg }
330 #define zAX { OP_IMREG, z_mode_ax_reg }
331 #define indirDX { OP_IMREG, indir_dx_reg }
333 #define Sw { OP_SEG, w_mode }
334 #define Sv { OP_SEG, v_mode }
335 #define Ap { OP_DIR, 0 }
336 #define Ob { OP_OFF64, b_mode }
337 #define Ov { OP_OFF64, v_mode }
338 #define Xb { OP_DSreg, eSI_reg }
339 #define Xv { OP_DSreg, eSI_reg }
340 #define Xz { OP_DSreg, eSI_reg }
341 #define Yb { OP_ESreg, eDI_reg }
342 #define Yv { OP_ESreg, eDI_reg }
343 #define DSBX { OP_DSreg, eBX_reg }
345 #define es { OP_REG, es_reg }
346 #define ss { OP_REG, ss_reg }
347 #define cs { OP_REG, cs_reg }
348 #define ds { OP_REG, ds_reg }
349 #define fs { OP_REG, fs_reg }
350 #define gs { OP_REG, gs_reg }
352 #define MX { OP_MMX, 0 }
353 #define XM { OP_XMM, 0 }
354 #define XMScalar { OP_XMM, scalar_mode }
355 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
356 #define XMM { OP_XMM, xmm_mode }
357 #define TMM { OP_XMM, tmm_mode }
358 #define XMxmmq { OP_XMM, xmmq_mode }
359 #define EM { OP_EM, v_mode }
360 #define EMS { OP_EM, v_swap_mode }
361 #define EMd { OP_EM, d_mode }
362 #define EMx { OP_EM, x_mode }
363 #define EXbScalar { OP_EX, b_scalar_mode }
364 #define EXw { OP_EX, w_mode }
365 #define EXwScalar { OP_EX, w_scalar_mode }
366 #define EXd { OP_EX, d_mode }
367 #define EXdS { OP_EX, d_swap_mode }
368 #define EXq { OP_EX, q_mode }
369 #define EXqS { OP_EX, q_swap_mode }
370 #define EXx { OP_EX, x_mode }
371 #define EXxS { OP_EX, x_swap_mode }
372 #define EXxmm { OP_EX, xmm_mode }
373 #define EXymm { OP_EX, ymm_mode }
374 #define EXtmm { OP_EX, tmm_mode }
375 #define EXxmmq { OP_EX, xmmq_mode }
376 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
377 #define EXxmm_mb { OP_EX, xmm_mb_mode }
378 #define EXxmm_mw { OP_EX, xmm_mw_mode }
379 #define EXxmm_md { OP_EX, xmm_md_mode }
380 #define EXxmm_mq { OP_EX, xmm_mq_mode }
381 #define EXxmmdw { OP_EX, xmmdw_mode }
382 #define EXxmmqd { OP_EX, xmmqd_mode }
383 #define EXymmq { OP_EX, ymmq_mode }
384 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
385 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
386 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
387 #define MS { OP_MS, v_mode }
388 #define XS { OP_XS, v_mode }
389 #define EMCq { OP_EMC, q_mode }
390 #define MXC { OP_MXC, 0 }
391 #define OPSUF { OP_3DNowSuffix, 0 }
392 #define SEP { SEP_Fixup, 0 }
393 #define CMP { CMP_Fixup, 0 }
394 #define XMM0 { XMM_Fixup, 0 }
395 #define FXSAVE { FXSAVE_Fixup, 0 }
397 #define Vex { OP_VEX, vex_mode }
398 #define VexW { OP_VexW, vex_mode }
399 #define VexScalar { OP_VEX, vex_scalar_mode }
400 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
401 #define Vex128 { OP_VEX, vex128_mode }
402 #define Vex256 { OP_VEX, vex256_mode }
403 #define VexGdq { OP_VEX, dq_mode }
404 #define VexTmm { OP_VEX, tmm_mode }
405 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
406 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
407 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
408 #define XMVexI4 { OP_REG_VexI4, x_mode }
409 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
410 #define VexI4 { OP_VexI4, 0 }
411 #define PCLMUL { PCLMUL_Fixup, 0 }
412 #define VCMP { VCMP_Fixup, 0 }
413 #define VPCMP { VPCMP_Fixup, 0 }
414 #define VPCOM { VPCOM_Fixup, 0 }
416 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
417 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
418 #define EXxEVexS { OP_Rounding, evex_sae_mode }
420 #define XMask { OP_Mask, mask_mode }
421 #define MaskG { OP_G, mask_mode }
422 #define MaskE { OP_E, mask_mode }
423 #define MaskBDE { OP_E, mask_bd_mode }
424 #define MaskR { OP_R, mask_mode }
425 #define MaskVex { OP_VEX, mask_mode }
427 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
428 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
429 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
430 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
432 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
434 /* Used handle "rep" prefix for string instructions. */
435 #define Xbr { REP_Fixup, eSI_reg }
436 #define Xvr { REP_Fixup, eSI_reg }
437 #define Ybr { REP_Fixup, eDI_reg }
438 #define Yvr { REP_Fixup, eDI_reg }
439 #define Yzr { REP_Fixup, eDI_reg }
440 #define indirDXr { REP_Fixup, indir_dx_reg }
441 #define ALr { REP_Fixup, al_reg }
442 #define eAXr { REP_Fixup, eAX_reg }
444 /* Used handle HLE prefix for lockable instructions. */
445 #define Ebh1 { HLE_Fixup1, b_mode }
446 #define Evh1 { HLE_Fixup1, v_mode }
447 #define Ebh2 { HLE_Fixup2, b_mode }
448 #define Evh2 { HLE_Fixup2, v_mode }
449 #define Ebh3 { HLE_Fixup3, b_mode }
450 #define Evh3 { HLE_Fixup3, v_mode }
452 #define BND { BND_Fixup, 0 }
453 #define NOTRACK { NOTRACK_Fixup, 0 }
455 #define cond_jump_flag { NULL, cond_jump_mode }
456 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
458 /* bits in sizeflag */
459 #define SUFFIX_ALWAYS 4
467 /* byte operand with operand swapped */
469 /* byte operand, sign extend like 'T' suffix */
471 /* operand size depends on prefixes */
473 /* operand size depends on prefixes with operand swapped */
475 /* operand size depends on address prefix */
479 /* double word operand */
481 /* double word operand with operand swapped */
483 /* quad word operand */
485 /* quad word operand with operand swapped */
487 /* ten-byte operand */
489 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
490 broadcast enabled. */
492 /* Similar to x_mode, but with different EVEX mem shifts. */
494 /* Similar to x_mode, but with disabled broadcast. */
496 /* Similar to x_mode, but with operands swapped and disabled broadcast
499 /* 16-byte XMM operand */
501 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
502 memory operand (depending on vector length). Broadcast isn't
505 /* Same as xmmq_mode, but broadcast is allowed. */
506 evex_half_bcst_xmmq_mode
,
507 /* XMM register or byte memory operand */
509 /* XMM register or word memory operand */
511 /* XMM register or double word memory operand */
513 /* XMM register or quad word memory operand */
515 /* 16-byte XMM, word, double word or quad word operand. */
517 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
519 /* 32-byte YMM operand */
521 /* quad word, ymmword or zmmword memory operand. */
523 /* 32-byte YMM or 16-byte word operand */
527 /* d_mode in 32bit, q_mode in 64bit mode. */
529 /* pair of v_mode operands */
535 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
537 /* operand size depends on REX prefixes. */
539 /* registers like dq_mode, memory like w_mode, displacements like
540 v_mode without considering Intel64 ISA. */
544 /* bounds operand with operand swapped */
546 /* 4- or 6-byte pointer operand */
549 /* v_mode for indirect branch opcodes. */
551 /* v_mode for stack-related opcodes. */
553 /* non-quad operand size depends on prefixes */
555 /* 16-byte operand */
557 /* registers like dq_mode, memory like b_mode. */
559 /* registers like d_mode, memory like b_mode. */
561 /* registers like d_mode, memory like w_mode. */
563 /* registers like dq_mode, memory like d_mode. */
565 /* normal vex mode */
567 /* 128bit vex mode */
569 /* 256bit vex mode */
572 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
573 vex_vsib_d_w_dq_mode
,
574 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
576 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
577 vex_vsib_q_w_dq_mode
,
578 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
580 /* mandatory non-vector SIB. */
583 /* scalar, ignore vector length. */
585 /* like b_mode, ignore vector length. */
587 /* like w_mode, ignore vector length. */
589 /* like d_swap_mode, ignore vector length. */
591 /* like q_swap_mode, ignore vector length. */
593 /* like vex_mode, ignore vector length. */
595 /* Operand size depends on the VEX.W bit, ignore vector length. */
596 vex_scalar_w_dq_mode
,
598 /* Static rounding. */
600 /* Static rounding, 64-bit mode only. */
601 evex_rounding_64_mode
,
602 /* Supress all exceptions. */
605 /* Mask register operand. */
607 /* Mask register operand. */
675 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
677 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
678 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
679 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
680 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
681 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
682 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
683 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
684 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
685 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
686 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
687 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
688 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
689 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
690 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
691 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
692 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
730 REG_VEX_0F3849_X86_64_P_0_W_0_M_1
,
735 REG_0FXOP_09_12_M_1_L_0
,
815 MOD_VEX_0F3849_X86_64_P_0_W_0
,
816 MOD_VEX_0F3849_X86_64_P_2_W_0
,
817 MOD_VEX_0F3849_X86_64_P_3_W_0
,
818 MOD_VEX_0F384B_X86_64_P_1_W_0
,
819 MOD_VEX_0F384B_X86_64_P_2_W_0
,
820 MOD_VEX_0F384B_X86_64_P_3_W_0
,
821 MOD_VEX_0F385C_X86_64_P_1_W_0
,
822 MOD_VEX_0F385E_X86_64_P_0_W_0
,
823 MOD_VEX_0F385E_X86_64_P_1_W_0
,
824 MOD_VEX_0F385E_X86_64_P_2_W_0
,
825 MOD_VEX_0F385E_X86_64_P_3_W_0
,
835 MOD_VEX_0F12_PREFIX_0
,
836 MOD_VEX_0F12_PREFIX_2
,
838 MOD_VEX_0F16_PREFIX_0
,
839 MOD_VEX_0F16_PREFIX_2
,
842 MOD_VEX_W_0_0F41_P_0_LEN_1
,
843 MOD_VEX_W_1_0F41_P_0_LEN_1
,
844 MOD_VEX_W_0_0F41_P_2_LEN_1
,
845 MOD_VEX_W_1_0F41_P_2_LEN_1
,
846 MOD_VEX_W_0_0F42_P_0_LEN_1
,
847 MOD_VEX_W_1_0F42_P_0_LEN_1
,
848 MOD_VEX_W_0_0F42_P_2_LEN_1
,
849 MOD_VEX_W_1_0F42_P_2_LEN_1
,
850 MOD_VEX_W_0_0F44_P_0_LEN_1
,
851 MOD_VEX_W_1_0F44_P_0_LEN_1
,
852 MOD_VEX_W_0_0F44_P_2_LEN_1
,
853 MOD_VEX_W_1_0F44_P_2_LEN_1
,
854 MOD_VEX_W_0_0F45_P_0_LEN_1
,
855 MOD_VEX_W_1_0F45_P_0_LEN_1
,
856 MOD_VEX_W_0_0F45_P_2_LEN_1
,
857 MOD_VEX_W_1_0F45_P_2_LEN_1
,
858 MOD_VEX_W_0_0F46_P_0_LEN_1
,
859 MOD_VEX_W_1_0F46_P_0_LEN_1
,
860 MOD_VEX_W_0_0F46_P_2_LEN_1
,
861 MOD_VEX_W_1_0F46_P_2_LEN_1
,
862 MOD_VEX_W_0_0F47_P_0_LEN_1
,
863 MOD_VEX_W_1_0F47_P_0_LEN_1
,
864 MOD_VEX_W_0_0F47_P_2_LEN_1
,
865 MOD_VEX_W_1_0F47_P_2_LEN_1
,
866 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
867 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
868 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
869 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
870 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
871 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
872 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
884 MOD_VEX_W_0_0F91_P_0_LEN_0
,
885 MOD_VEX_W_1_0F91_P_0_LEN_0
,
886 MOD_VEX_W_0_0F91_P_2_LEN_0
,
887 MOD_VEX_W_1_0F91_P_2_LEN_0
,
888 MOD_VEX_W_0_0F92_P_0_LEN_0
,
889 MOD_VEX_W_0_0F92_P_2_LEN_0
,
890 MOD_VEX_0F92_P_3_LEN_0
,
891 MOD_VEX_W_0_0F93_P_0_LEN_0
,
892 MOD_VEX_W_0_0F93_P_2_LEN_0
,
893 MOD_VEX_0F93_P_3_LEN_0
,
894 MOD_VEX_W_0_0F98_P_0_LEN_0
,
895 MOD_VEX_W_1_0F98_P_0_LEN_0
,
896 MOD_VEX_W_0_0F98_P_2_LEN_0
,
897 MOD_VEX_W_1_0F98_P_2_LEN_0
,
898 MOD_VEX_W_0_0F99_P_0_LEN_0
,
899 MOD_VEX_W_1_0F99_P_0_LEN_0
,
900 MOD_VEX_W_0_0F99_P_2_LEN_0
,
901 MOD_VEX_W_1_0F99_P_2_LEN_0
,
904 MOD_VEX_0FD7_PREFIX_2
,
905 MOD_VEX_0FE7_PREFIX_2
,
906 MOD_VEX_0FF0_PREFIX_3
,
907 MOD_VEX_0F381A_PREFIX_2
,
908 MOD_VEX_0F382A_PREFIX_2
,
909 MOD_VEX_0F382C_PREFIX_2
,
910 MOD_VEX_0F382D_PREFIX_2
,
911 MOD_VEX_0F382E_PREFIX_2
,
912 MOD_VEX_0F382F_PREFIX_2
,
913 MOD_VEX_0F385A_PREFIX_2
,
914 MOD_VEX_0F388C_PREFIX_2
,
915 MOD_VEX_0F388E_PREFIX_2
,
916 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
917 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
918 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
919 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
920 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
921 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
922 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
923 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
927 MOD_EVEX_0F12_PREFIX_0
,
928 MOD_EVEX_0F12_PREFIX_2
,
930 MOD_EVEX_0F16_PREFIX_0
,
931 MOD_EVEX_0F16_PREFIX_2
,
934 MOD_EVEX_0F381A_P_2_W_0
,
935 MOD_EVEX_0F381A_P_2_W_1
,
936 MOD_EVEX_0F381B_P_2_W_0
,
937 MOD_EVEX_0F381B_P_2_W_1
,
938 MOD_EVEX_0F385A_P_2_W_0
,
939 MOD_EVEX_0F385A_P_2_W_1
,
940 MOD_EVEX_0F385B_P_2_W_0
,
941 MOD_EVEX_0F385B_P_2_W_1
,
942 MOD_EVEX_0F38C6_REG_1
,
943 MOD_EVEX_0F38C6_REG_2
,
944 MOD_EVEX_0F38C6_REG_5
,
945 MOD_EVEX_0F38C6_REG_6
,
946 MOD_EVEX_0F38C7_REG_1
,
947 MOD_EVEX_0F38C7_REG_2
,
948 MOD_EVEX_0F38C7_REG_5
,
949 MOD_EVEX_0F38C7_REG_6
962 RM_0F1E_P_1_MOD_3_REG_7
,
963 RM_0FAE_REG_6_MOD_3_P_0
,
965 RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
971 PREFIX_0F01_REG_3_RM_1
,
972 PREFIX_0F01_REG_5_MOD_0
,
973 PREFIX_0F01_REG_5_MOD_3_RM_0
,
974 PREFIX_0F01_REG_5_MOD_3_RM_1
,
975 PREFIX_0F01_REG_5_MOD_3_RM_2
,
976 PREFIX_0F01_REG_7_MOD_3_RM_2
,
977 PREFIX_0F01_REG_7_MOD_3_RM_3
,
1019 PREFIX_0FAE_REG_0_MOD_3
,
1020 PREFIX_0FAE_REG_1_MOD_3
,
1021 PREFIX_0FAE_REG_2_MOD_3
,
1022 PREFIX_0FAE_REG_3_MOD_3
,
1023 PREFIX_0FAE_REG_4_MOD_0
,
1024 PREFIX_0FAE_REG_4_MOD_3
,
1025 PREFIX_0FAE_REG_5_MOD_0
,
1026 PREFIX_0FAE_REG_5_MOD_3
,
1027 PREFIX_0FAE_REG_6_MOD_0
,
1028 PREFIX_0FAE_REG_6_MOD_3
,
1029 PREFIX_0FAE_REG_7_MOD_0
,
1035 PREFIX_0FC7_REG_6_MOD_0
,
1036 PREFIX_0FC7_REG_6_MOD_3
,
1037 PREFIX_0FC7_REG_7_MOD_3
,
1167 PREFIX_VEX_0F71_REG_2
,
1168 PREFIX_VEX_0F71_REG_4
,
1169 PREFIX_VEX_0F71_REG_6
,
1170 PREFIX_VEX_0F72_REG_2
,
1171 PREFIX_VEX_0F72_REG_4
,
1172 PREFIX_VEX_0F72_REG_6
,
1173 PREFIX_VEX_0F73_REG_2
,
1174 PREFIX_VEX_0F73_REG_3
,
1175 PREFIX_VEX_0F73_REG_6
,
1176 PREFIX_VEX_0F73_REG_7
,
1301 PREFIX_VEX_0F3849_X86_64
,
1302 PREFIX_VEX_0F384B_X86_64
,
1306 PREFIX_VEX_0F385C_X86_64
,
1307 PREFIX_VEX_0F385E_X86_64
,
1353 PREFIX_VEX_0F38F3_REG_1
,
1354 PREFIX_VEX_0F38F3_REG_2
,
1355 PREFIX_VEX_0F38F3_REG_3
,
1452 PREFIX_EVEX_0F71_REG_2
,
1453 PREFIX_EVEX_0F71_REG_4
,
1454 PREFIX_EVEX_0F71_REG_6
,
1455 PREFIX_EVEX_0F72_REG_0
,
1456 PREFIX_EVEX_0F72_REG_1
,
1457 PREFIX_EVEX_0F72_REG_2
,
1458 PREFIX_EVEX_0F72_REG_4
,
1459 PREFIX_EVEX_0F72_REG_6
,
1460 PREFIX_EVEX_0F73_REG_2
,
1461 PREFIX_EVEX_0F73_REG_3
,
1462 PREFIX_EVEX_0F73_REG_6
,
1463 PREFIX_EVEX_0F73_REG_7
,
1585 PREFIX_EVEX_0F38C6_REG_1
,
1586 PREFIX_EVEX_0F38C6_REG_2
,
1587 PREFIX_EVEX_0F38C6_REG_5
,
1588 PREFIX_EVEX_0F38C6_REG_6
,
1589 PREFIX_EVEX_0F38C7_REG_1
,
1590 PREFIX_EVEX_0F38C7_REG_2
,
1591 PREFIX_EVEX_0F38C7_REG_5
,
1592 PREFIX_EVEX_0F38C7_REG_6
,
1689 THREE_BYTE_0F38
= 0,
1716 VEX_LEN_0F12_P_0_M_0
= 0,
1717 VEX_LEN_0F12_P_0_M_1
,
1718 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1720 VEX_LEN_0F16_P_0_M_0
,
1721 VEX_LEN_0F16_P_0_M_1
,
1722 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1758 VEX_LEN_0FAE_R_2_M_0
,
1759 VEX_LEN_0FAE_R_3_M_0
,
1766 VEX_LEN_0F381A_P_2_M_0
,
1769 VEX_LEN_0F3849_X86_64_P_0_W_0_M_0
,
1770 VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0
,
1771 VEX_LEN_0F3849_X86_64_P_2_W_0_M_0
,
1772 VEX_LEN_0F3849_X86_64_P_3_W_0_M_0
,
1773 VEX_LEN_0F384B_X86_64_P_1_W_0_M_0
,
1774 VEX_LEN_0F384B_X86_64_P_2_W_0_M_0
,
1775 VEX_LEN_0F384B_X86_64_P_3_W_0_M_0
,
1776 VEX_LEN_0F385A_P_2_M_0
,
1777 VEX_LEN_0F385C_X86_64_P_1_W_0_M_0
,
1778 VEX_LEN_0F385E_X86_64_P_0_W_0_M_0
,
1779 VEX_LEN_0F385E_X86_64_P_1_W_0_M_0
,
1780 VEX_LEN_0F385E_X86_64_P_2_W_0_M_0
,
1781 VEX_LEN_0F385E_X86_64_P_3_W_0_M_0
,
1784 VEX_LEN_0F38F3_R_1_P_0
,
1785 VEX_LEN_0F38F3_R_2_P_0
,
1786 VEX_LEN_0F38F3_R_3_P_0
,
1821 VEX_LEN_0FXOP_08_85
,
1822 VEX_LEN_0FXOP_08_86
,
1823 VEX_LEN_0FXOP_08_87
,
1824 VEX_LEN_0FXOP_08_8E
,
1825 VEX_LEN_0FXOP_08_8F
,
1826 VEX_LEN_0FXOP_08_95
,
1827 VEX_LEN_0FXOP_08_96
,
1828 VEX_LEN_0FXOP_08_97
,
1829 VEX_LEN_0FXOP_08_9E
,
1830 VEX_LEN_0FXOP_08_9F
,
1831 VEX_LEN_0FXOP_08_A3
,
1832 VEX_LEN_0FXOP_08_A6
,
1833 VEX_LEN_0FXOP_08_B6
,
1834 VEX_LEN_0FXOP_08_C0
,
1835 VEX_LEN_0FXOP_08_C1
,
1836 VEX_LEN_0FXOP_08_C2
,
1837 VEX_LEN_0FXOP_08_C3
,
1838 VEX_LEN_0FXOP_08_CC
,
1839 VEX_LEN_0FXOP_08_CD
,
1840 VEX_LEN_0FXOP_08_CE
,
1841 VEX_LEN_0FXOP_08_CF
,
1842 VEX_LEN_0FXOP_08_EC
,
1843 VEX_LEN_0FXOP_08_ED
,
1844 VEX_LEN_0FXOP_08_EE
,
1845 VEX_LEN_0FXOP_08_EF
,
1846 VEX_LEN_0FXOP_09_01
,
1847 VEX_LEN_0FXOP_09_02
,
1848 VEX_LEN_0FXOP_09_12_M_1
,
1849 VEX_LEN_0FXOP_09_82_W_0
,
1850 VEX_LEN_0FXOP_09_83_W_0
,
1851 VEX_LEN_0FXOP_09_90
,
1852 VEX_LEN_0FXOP_09_91
,
1853 VEX_LEN_0FXOP_09_92
,
1854 VEX_LEN_0FXOP_09_93
,
1855 VEX_LEN_0FXOP_09_94
,
1856 VEX_LEN_0FXOP_09_95
,
1857 VEX_LEN_0FXOP_09_96
,
1858 VEX_LEN_0FXOP_09_97
,
1859 VEX_LEN_0FXOP_09_98
,
1860 VEX_LEN_0FXOP_09_99
,
1861 VEX_LEN_0FXOP_09_9A
,
1862 VEX_LEN_0FXOP_09_9B
,
1863 VEX_LEN_0FXOP_09_C1
,
1864 VEX_LEN_0FXOP_09_C2
,
1865 VEX_LEN_0FXOP_09_C3
,
1866 VEX_LEN_0FXOP_09_C6
,
1867 VEX_LEN_0FXOP_09_C7
,
1868 VEX_LEN_0FXOP_09_CB
,
1869 VEX_LEN_0FXOP_09_D1
,
1870 VEX_LEN_0FXOP_09_D2
,
1871 VEX_LEN_0FXOP_09_D3
,
1872 VEX_LEN_0FXOP_09_D6
,
1873 VEX_LEN_0FXOP_09_D7
,
1874 VEX_LEN_0FXOP_09_DB
,
1875 VEX_LEN_0FXOP_09_E1
,
1876 VEX_LEN_0FXOP_09_E2
,
1877 VEX_LEN_0FXOP_09_E3
,
1878 VEX_LEN_0FXOP_0A_12
,
1883 EVEX_LEN_0F6E_P_2
= 0,
1889 EVEX_LEN_0F3816_P_2
,
1890 EVEX_LEN_0F3819_P_2_W_0
,
1891 EVEX_LEN_0F3819_P_2_W_1
,
1892 EVEX_LEN_0F381A_P_2_W_0_M_0
,
1893 EVEX_LEN_0F381A_P_2_W_1_M_0
,
1894 EVEX_LEN_0F381B_P_2_W_0_M_0
,
1895 EVEX_LEN_0F381B_P_2_W_1_M_0
,
1896 EVEX_LEN_0F3836_P_2
,
1897 EVEX_LEN_0F385A_P_2_W_0_M_0
,
1898 EVEX_LEN_0F385A_P_2_W_1_M_0
,
1899 EVEX_LEN_0F385B_P_2_W_0_M_0
,
1900 EVEX_LEN_0F385B_P_2_W_1_M_0
,
1901 EVEX_LEN_0F38C6_REG_1_PREFIX_2
,
1902 EVEX_LEN_0F38C6_REG_2_PREFIX_2
,
1903 EVEX_LEN_0F38C6_REG_5_PREFIX_2
,
1904 EVEX_LEN_0F38C6_REG_6_PREFIX_2
,
1905 EVEX_LEN_0F38C7_R_1_P_2_W_0
,
1906 EVEX_LEN_0F38C7_R_1_P_2_W_1
,
1907 EVEX_LEN_0F38C7_R_2_P_2_W_0
,
1908 EVEX_LEN_0F38C7_R_2_P_2_W_1
,
1909 EVEX_LEN_0F38C7_R_5_P_2_W_0
,
1910 EVEX_LEN_0F38C7_R_5_P_2_W_1
,
1911 EVEX_LEN_0F38C7_R_6_P_2_W_0
,
1912 EVEX_LEN_0F38C7_R_6_P_2_W_1
,
1913 EVEX_LEN_0F3A00_P_2_W_1
,
1914 EVEX_LEN_0F3A01_P_2_W_1
,
1915 EVEX_LEN_0F3A14_P_2
,
1916 EVEX_LEN_0F3A15_P_2
,
1917 EVEX_LEN_0F3A16_P_2
,
1918 EVEX_LEN_0F3A17_P_2
,
1919 EVEX_LEN_0F3A18_P_2_W_0
,
1920 EVEX_LEN_0F3A18_P_2_W_1
,
1921 EVEX_LEN_0F3A19_P_2_W_0
,
1922 EVEX_LEN_0F3A19_P_2_W_1
,
1923 EVEX_LEN_0F3A1A_P_2_W_0
,
1924 EVEX_LEN_0F3A1A_P_2_W_1
,
1925 EVEX_LEN_0F3A1B_P_2_W_0
,
1926 EVEX_LEN_0F3A1B_P_2_W_1
,
1927 EVEX_LEN_0F3A20_P_2
,
1928 EVEX_LEN_0F3A21_P_2_W_0
,
1929 EVEX_LEN_0F3A22_P_2
,
1930 EVEX_LEN_0F3A23_P_2_W_0
,
1931 EVEX_LEN_0F3A23_P_2_W_1
,
1932 EVEX_LEN_0F3A38_P_2_W_0
,
1933 EVEX_LEN_0F3A38_P_2_W_1
,
1934 EVEX_LEN_0F3A39_P_2_W_0
,
1935 EVEX_LEN_0F3A39_P_2_W_1
,
1936 EVEX_LEN_0F3A3A_P_2_W_0
,
1937 EVEX_LEN_0F3A3A_P_2_W_1
,
1938 EVEX_LEN_0F3A3B_P_2_W_0
,
1939 EVEX_LEN_0F3A3B_P_2_W_1
,
1940 EVEX_LEN_0F3A43_P_2_W_0
,
1941 EVEX_LEN_0F3A43_P_2_W_1
1946 VEX_W_0F41_P_0_LEN_1
= 0,
1947 VEX_W_0F41_P_2_LEN_1
,
1948 VEX_W_0F42_P_0_LEN_1
,
1949 VEX_W_0F42_P_2_LEN_1
,
1950 VEX_W_0F44_P_0_LEN_0
,
1951 VEX_W_0F44_P_2_LEN_0
,
1952 VEX_W_0F45_P_0_LEN_1
,
1953 VEX_W_0F45_P_2_LEN_1
,
1954 VEX_W_0F46_P_0_LEN_1
,
1955 VEX_W_0F46_P_2_LEN_1
,
1956 VEX_W_0F47_P_0_LEN_1
,
1957 VEX_W_0F47_P_2_LEN_1
,
1958 VEX_W_0F4A_P_0_LEN_1
,
1959 VEX_W_0F4A_P_2_LEN_1
,
1960 VEX_W_0F4B_P_0_LEN_1
,
1961 VEX_W_0F4B_P_2_LEN_1
,
1962 VEX_W_0F90_P_0_LEN_0
,
1963 VEX_W_0F90_P_2_LEN_0
,
1964 VEX_W_0F91_P_0_LEN_0
,
1965 VEX_W_0F91_P_2_LEN_0
,
1966 VEX_W_0F92_P_0_LEN_0
,
1967 VEX_W_0F92_P_2_LEN_0
,
1968 VEX_W_0F93_P_0_LEN_0
,
1969 VEX_W_0F93_P_2_LEN_0
,
1970 VEX_W_0F98_P_0_LEN_0
,
1971 VEX_W_0F98_P_2_LEN_0
,
1972 VEX_W_0F99_P_0_LEN_0
,
1973 VEX_W_0F99_P_2_LEN_0
,
1982 VEX_W_0F381A_P_2_M_0
,
1983 VEX_W_0F382C_P_2_M_0
,
1984 VEX_W_0F382D_P_2_M_0
,
1985 VEX_W_0F382E_P_2_M_0
,
1986 VEX_W_0F382F_P_2_M_0
,
1989 VEX_W_0F3849_X86_64_P_0
,
1990 VEX_W_0F3849_X86_64_P_2
,
1991 VEX_W_0F3849_X86_64_P_3
,
1992 VEX_W_0F384B_X86_64_P_1
,
1993 VEX_W_0F384B_X86_64_P_2
,
1994 VEX_W_0F384B_X86_64_P_3
,
1997 VEX_W_0F385A_P_2_M_0
,
1998 VEX_W_0F385C_X86_64_P_1
,
1999 VEX_W_0F385E_X86_64_P_0
,
2000 VEX_W_0F385E_X86_64_P_1
,
2001 VEX_W_0F385E_X86_64_P_2
,
2002 VEX_W_0F385E_X86_64_P_3
,
2015 VEX_W_0F3A30_P_2_LEN_0
,
2016 VEX_W_0F3A31_P_2_LEN_0
,
2017 VEX_W_0F3A32_P_2_LEN_0
,
2018 VEX_W_0F3A33_P_2_LEN_0
,
2028 VEX_W_0FXOP_08_85_L_0
,
2029 VEX_W_0FXOP_08_86_L_0
,
2030 VEX_W_0FXOP_08_87_L_0
,
2031 VEX_W_0FXOP_08_8E_L_0
,
2032 VEX_W_0FXOP_08_8F_L_0
,
2033 VEX_W_0FXOP_08_95_L_0
,
2034 VEX_W_0FXOP_08_96_L_0
,
2035 VEX_W_0FXOP_08_97_L_0
,
2036 VEX_W_0FXOP_08_9E_L_0
,
2037 VEX_W_0FXOP_08_9F_L_0
,
2038 VEX_W_0FXOP_08_A6_L_0
,
2039 VEX_W_0FXOP_08_B6_L_0
,
2040 VEX_W_0FXOP_08_C0_L_0
,
2041 VEX_W_0FXOP_08_C1_L_0
,
2042 VEX_W_0FXOP_08_C2_L_0
,
2043 VEX_W_0FXOP_08_C3_L_0
,
2044 VEX_W_0FXOP_08_CC_L_0
,
2045 VEX_W_0FXOP_08_CD_L_0
,
2046 VEX_W_0FXOP_08_CE_L_0
,
2047 VEX_W_0FXOP_08_CF_L_0
,
2048 VEX_W_0FXOP_08_EC_L_0
,
2049 VEX_W_0FXOP_08_ED_L_0
,
2050 VEX_W_0FXOP_08_EE_L_0
,
2051 VEX_W_0FXOP_08_EF_L_0
,
2057 VEX_W_0FXOP_09_C1_L_0
,
2058 VEX_W_0FXOP_09_C2_L_0
,
2059 VEX_W_0FXOP_09_C3_L_0
,
2060 VEX_W_0FXOP_09_C6_L_0
,
2061 VEX_W_0FXOP_09_C7_L_0
,
2062 VEX_W_0FXOP_09_CB_L_0
,
2063 VEX_W_0FXOP_09_D1_L_0
,
2064 VEX_W_0FXOP_09_D2_L_0
,
2065 VEX_W_0FXOP_09_D3_L_0
,
2066 VEX_W_0FXOP_09_D6_L_0
,
2067 VEX_W_0FXOP_09_D7_L_0
,
2068 VEX_W_0FXOP_09_DB_L_0
,
2069 VEX_W_0FXOP_09_E1_L_0
,
2070 VEX_W_0FXOP_09_E2_L_0
,
2071 VEX_W_0FXOP_09_E3_L_0
,
2077 EVEX_W_0F12_P_0_M_1
,
2080 EVEX_W_0F16_P_0_M_1
,
2114 EVEX_W_0F72_R_2_P_2
,
2115 EVEX_W_0F72_R_6_P_2
,
2116 EVEX_W_0F73_R_2_P_2
,
2117 EVEX_W_0F73_R_6_P_2
,
2202 EVEX_W_0F38C7_R_1_P_2
,
2203 EVEX_W_0F38C7_R_2_P_2
,
2204 EVEX_W_0F38C7_R_5_P_2
,
2205 EVEX_W_0F38C7_R_6_P_2
,
2230 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2239 unsigned int prefix_requirement
;
2242 /* Upper case letters in the instruction names here are macros.
2243 'A' => print 'b' if no register operands or suffix_always is true
2244 'B' => print 'b' if suffix_always is true
2245 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2247 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2248 suffix_always is true
2249 'E' => print 'e' if 32-bit form of jcxz
2250 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2251 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2252 'H' => print ",pt" or ",pn" branch hint
2255 'K' => print 'd' or 'q' if rex prefix is present.
2256 'L' => print 'l' if suffix_always is true
2257 'M' => print 'r' if intel_mnemonic is false.
2258 'N' => print 'n' if instruction has no wait "prefix"
2259 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2260 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2261 or suffix_always is true. print 'q' if rex prefix is present.
2262 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2264 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2265 'S' => print 'w', 'l' or 'q' if suffix_always is true
2266 'T' => print 'q' in 64bit mode if instruction has no operand size
2267 prefix and behave as 'P' otherwise
2268 'U' => print 'q' in 64bit mode if instruction has no operand size
2269 prefix and behave as 'Q' otherwise
2270 'V' => print 'q' in 64bit mode if instruction has no operand size
2271 prefix and behave as 'S' otherwise
2272 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2273 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2275 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2276 '!' => change condition from true to false or from false to true.
2277 '%' => add 1 upper case letter to the macro.
2278 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
2279 prefix or suffix_always is true (lcall/ljmp).
2280 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2281 on operand size prefix.
2282 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2283 has no operand size prefix for AMD64 ISA, behave as 'P'
2286 2 upper case letter macros:
2287 "XY" => print 'x' or 'y' if suffix_always is true or no register
2288 operands and no broadcast.
2289 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2290 register operands and no broadcast.
2291 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2292 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory
2293 operand or no operand at all in 64bit mode, or if suffix_always
2295 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2296 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2297 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2298 "LW" => print 'd', 'q' depending on the VEX.W bit
2299 "BW" => print 'b' or 'w' depending on the EVEX.W bit
2300 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2301 an operand size prefix, or suffix_always is true. print
2302 'q' if rex prefix is present.
2304 Many of the above letters print nothing in Intel mode. See "putop"
2307 Braces '{' and '}', and vertical bars '|', indicate alternative
2308 mnemonic strings for AT&T and Intel. */
2310 static const struct dis386 dis386
[] = {
2312 { "addB", { Ebh1
, Gb
}, 0 },
2313 { "addS", { Evh1
, Gv
}, 0 },
2314 { "addB", { Gb
, EbS
}, 0 },
2315 { "addS", { Gv
, EvS
}, 0 },
2316 { "addB", { AL
, Ib
}, 0 },
2317 { "addS", { eAX
, Iv
}, 0 },
2318 { X86_64_TABLE (X86_64_06
) },
2319 { X86_64_TABLE (X86_64_07
) },
2321 { "orB", { Ebh1
, Gb
}, 0 },
2322 { "orS", { Evh1
, Gv
}, 0 },
2323 { "orB", { Gb
, EbS
}, 0 },
2324 { "orS", { Gv
, EvS
}, 0 },
2325 { "orB", { AL
, Ib
}, 0 },
2326 { "orS", { eAX
, Iv
}, 0 },
2327 { X86_64_TABLE (X86_64_0E
) },
2328 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2330 { "adcB", { Ebh1
, Gb
}, 0 },
2331 { "adcS", { Evh1
, Gv
}, 0 },
2332 { "adcB", { Gb
, EbS
}, 0 },
2333 { "adcS", { Gv
, EvS
}, 0 },
2334 { "adcB", { AL
, Ib
}, 0 },
2335 { "adcS", { eAX
, Iv
}, 0 },
2336 { X86_64_TABLE (X86_64_16
) },
2337 { X86_64_TABLE (X86_64_17
) },
2339 { "sbbB", { Ebh1
, Gb
}, 0 },
2340 { "sbbS", { Evh1
, Gv
}, 0 },
2341 { "sbbB", { Gb
, EbS
}, 0 },
2342 { "sbbS", { Gv
, EvS
}, 0 },
2343 { "sbbB", { AL
, Ib
}, 0 },
2344 { "sbbS", { eAX
, Iv
}, 0 },
2345 { X86_64_TABLE (X86_64_1E
) },
2346 { X86_64_TABLE (X86_64_1F
) },
2348 { "andB", { Ebh1
, Gb
}, 0 },
2349 { "andS", { Evh1
, Gv
}, 0 },
2350 { "andB", { Gb
, EbS
}, 0 },
2351 { "andS", { Gv
, EvS
}, 0 },
2352 { "andB", { AL
, Ib
}, 0 },
2353 { "andS", { eAX
, Iv
}, 0 },
2354 { Bad_Opcode
}, /* SEG ES prefix */
2355 { X86_64_TABLE (X86_64_27
) },
2357 { "subB", { Ebh1
, Gb
}, 0 },
2358 { "subS", { Evh1
, Gv
}, 0 },
2359 { "subB", { Gb
, EbS
}, 0 },
2360 { "subS", { Gv
, EvS
}, 0 },
2361 { "subB", { AL
, Ib
}, 0 },
2362 { "subS", { eAX
, Iv
}, 0 },
2363 { Bad_Opcode
}, /* SEG CS prefix */
2364 { X86_64_TABLE (X86_64_2F
) },
2366 { "xorB", { Ebh1
, Gb
}, 0 },
2367 { "xorS", { Evh1
, Gv
}, 0 },
2368 { "xorB", { Gb
, EbS
}, 0 },
2369 { "xorS", { Gv
, EvS
}, 0 },
2370 { "xorB", { AL
, Ib
}, 0 },
2371 { "xorS", { eAX
, Iv
}, 0 },
2372 { Bad_Opcode
}, /* SEG SS prefix */
2373 { X86_64_TABLE (X86_64_37
) },
2375 { "cmpB", { Eb
, Gb
}, 0 },
2376 { "cmpS", { Ev
, Gv
}, 0 },
2377 { "cmpB", { Gb
, EbS
}, 0 },
2378 { "cmpS", { Gv
, EvS
}, 0 },
2379 { "cmpB", { AL
, Ib
}, 0 },
2380 { "cmpS", { eAX
, Iv
}, 0 },
2381 { Bad_Opcode
}, /* SEG DS prefix */
2382 { X86_64_TABLE (X86_64_3F
) },
2384 { "inc{S|}", { RMeAX
}, 0 },
2385 { "inc{S|}", { RMeCX
}, 0 },
2386 { "inc{S|}", { RMeDX
}, 0 },
2387 { "inc{S|}", { RMeBX
}, 0 },
2388 { "inc{S|}", { RMeSP
}, 0 },
2389 { "inc{S|}", { RMeBP
}, 0 },
2390 { "inc{S|}", { RMeSI
}, 0 },
2391 { "inc{S|}", { RMeDI
}, 0 },
2393 { "dec{S|}", { RMeAX
}, 0 },
2394 { "dec{S|}", { RMeCX
}, 0 },
2395 { "dec{S|}", { RMeDX
}, 0 },
2396 { "dec{S|}", { RMeBX
}, 0 },
2397 { "dec{S|}", { RMeSP
}, 0 },
2398 { "dec{S|}", { RMeBP
}, 0 },
2399 { "dec{S|}", { RMeSI
}, 0 },
2400 { "dec{S|}", { RMeDI
}, 0 },
2402 { "pushV", { RMrAX
}, 0 },
2403 { "pushV", { RMrCX
}, 0 },
2404 { "pushV", { RMrDX
}, 0 },
2405 { "pushV", { RMrBX
}, 0 },
2406 { "pushV", { RMrSP
}, 0 },
2407 { "pushV", { RMrBP
}, 0 },
2408 { "pushV", { RMrSI
}, 0 },
2409 { "pushV", { RMrDI
}, 0 },
2411 { "popV", { RMrAX
}, 0 },
2412 { "popV", { RMrCX
}, 0 },
2413 { "popV", { RMrDX
}, 0 },
2414 { "popV", { RMrBX
}, 0 },
2415 { "popV", { RMrSP
}, 0 },
2416 { "popV", { RMrBP
}, 0 },
2417 { "popV", { RMrSI
}, 0 },
2418 { "popV", { RMrDI
}, 0 },
2420 { X86_64_TABLE (X86_64_60
) },
2421 { X86_64_TABLE (X86_64_61
) },
2422 { X86_64_TABLE (X86_64_62
) },
2423 { X86_64_TABLE (X86_64_63
) },
2424 { Bad_Opcode
}, /* seg fs */
2425 { Bad_Opcode
}, /* seg gs */
2426 { Bad_Opcode
}, /* op size prefix */
2427 { Bad_Opcode
}, /* adr size prefix */
2429 { "pushT", { sIv
}, 0 },
2430 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2431 { "pushT", { sIbT
}, 0 },
2432 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2433 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2434 { X86_64_TABLE (X86_64_6D
) },
2435 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2436 { X86_64_TABLE (X86_64_6F
) },
2438 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2439 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2440 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2441 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2442 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2443 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2444 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2445 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2447 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2448 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2449 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2450 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2451 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2452 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2453 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2454 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2456 { REG_TABLE (REG_80
) },
2457 { REG_TABLE (REG_81
) },
2458 { X86_64_TABLE (X86_64_82
) },
2459 { REG_TABLE (REG_83
) },
2460 { "testB", { Eb
, Gb
}, 0 },
2461 { "testS", { Ev
, Gv
}, 0 },
2462 { "xchgB", { Ebh2
, Gb
}, 0 },
2463 { "xchgS", { Evh2
, Gv
}, 0 },
2465 { "movB", { Ebh3
, Gb
}, 0 },
2466 { "movS", { Evh3
, Gv
}, 0 },
2467 { "movB", { Gb
, EbS
}, 0 },
2468 { "movS", { Gv
, EvS
}, 0 },
2469 { "movD", { Sv
, Sw
}, 0 },
2470 { MOD_TABLE (MOD_8D
) },
2471 { "movD", { Sw
, Sv
}, 0 },
2472 { REG_TABLE (REG_8F
) },
2474 { PREFIX_TABLE (PREFIX_90
) },
2475 { "xchgS", { RMeCX
, eAX
}, 0 },
2476 { "xchgS", { RMeDX
, eAX
}, 0 },
2477 { "xchgS", { RMeBX
, eAX
}, 0 },
2478 { "xchgS", { RMeSP
, eAX
}, 0 },
2479 { "xchgS", { RMeBP
, eAX
}, 0 },
2480 { "xchgS", { RMeSI
, eAX
}, 0 },
2481 { "xchgS", { RMeDI
, eAX
}, 0 },
2483 { "cW{t|}R", { XX
}, 0 },
2484 { "cR{t|}O", { XX
}, 0 },
2485 { X86_64_TABLE (X86_64_9A
) },
2486 { Bad_Opcode
}, /* fwait */
2487 { "pushfT", { XX
}, 0 },
2488 { "popfT", { XX
}, 0 },
2489 { "sahf", { XX
}, 0 },
2490 { "lahf", { XX
}, 0 },
2492 { "mov%LB", { AL
, Ob
}, 0 },
2493 { "mov%LS", { eAX
, Ov
}, 0 },
2494 { "mov%LB", { Ob
, AL
}, 0 },
2495 { "mov%LS", { Ov
, eAX
}, 0 },
2496 { "movs{b|}", { Ybr
, Xb
}, 0 },
2497 { "movs{R|}", { Yvr
, Xv
}, 0 },
2498 { "cmps{b|}", { Xb
, Yb
}, 0 },
2499 { "cmps{R|}", { Xv
, Yv
}, 0 },
2501 { "testB", { AL
, Ib
}, 0 },
2502 { "testS", { eAX
, Iv
}, 0 },
2503 { "stosB", { Ybr
, AL
}, 0 },
2504 { "stosS", { Yvr
, eAX
}, 0 },
2505 { "lodsB", { ALr
, Xb
}, 0 },
2506 { "lodsS", { eAXr
, Xv
}, 0 },
2507 { "scasB", { AL
, Yb
}, 0 },
2508 { "scasS", { eAX
, Yv
}, 0 },
2510 { "movB", { RMAL
, Ib
}, 0 },
2511 { "movB", { RMCL
, Ib
}, 0 },
2512 { "movB", { RMDL
, Ib
}, 0 },
2513 { "movB", { RMBL
, Ib
}, 0 },
2514 { "movB", { RMAH
, Ib
}, 0 },
2515 { "movB", { RMCH
, Ib
}, 0 },
2516 { "movB", { RMDH
, Ib
}, 0 },
2517 { "movB", { RMBH
, Ib
}, 0 },
2519 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2520 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2521 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2522 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2523 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2524 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2525 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2526 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2528 { REG_TABLE (REG_C0
) },
2529 { REG_TABLE (REG_C1
) },
2530 { X86_64_TABLE (X86_64_C2
) },
2531 { X86_64_TABLE (X86_64_C3
) },
2532 { X86_64_TABLE (X86_64_C4
) },
2533 { X86_64_TABLE (X86_64_C5
) },
2534 { REG_TABLE (REG_C6
) },
2535 { REG_TABLE (REG_C7
) },
2537 { "enterT", { Iw
, Ib
}, 0 },
2538 { "leaveT", { XX
}, 0 },
2539 { "{l|}ret{|f}P", { Iw
}, 0 },
2540 { "{l|}ret{|f}P", { XX
}, 0 },
2541 { "int3", { XX
}, 0 },
2542 { "int", { Ib
}, 0 },
2543 { X86_64_TABLE (X86_64_CE
) },
2544 { "iret%LP", { XX
}, 0 },
2546 { REG_TABLE (REG_D0
) },
2547 { REG_TABLE (REG_D1
) },
2548 { REG_TABLE (REG_D2
) },
2549 { REG_TABLE (REG_D3
) },
2550 { X86_64_TABLE (X86_64_D4
) },
2551 { X86_64_TABLE (X86_64_D5
) },
2553 { "xlat", { DSBX
}, 0 },
2564 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2565 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2566 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2567 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2568 { "inB", { AL
, Ib
}, 0 },
2569 { "inG", { zAX
, Ib
}, 0 },
2570 { "outB", { Ib
, AL
}, 0 },
2571 { "outG", { Ib
, zAX
}, 0 },
2573 { X86_64_TABLE (X86_64_E8
) },
2574 { X86_64_TABLE (X86_64_E9
) },
2575 { X86_64_TABLE (X86_64_EA
) },
2576 { "jmp", { Jb
, BND
}, 0 },
2577 { "inB", { AL
, indirDX
}, 0 },
2578 { "inG", { zAX
, indirDX
}, 0 },
2579 { "outB", { indirDX
, AL
}, 0 },
2580 { "outG", { indirDX
, zAX
}, 0 },
2582 { Bad_Opcode
}, /* lock prefix */
2583 { "icebp", { XX
}, 0 },
2584 { Bad_Opcode
}, /* repne */
2585 { Bad_Opcode
}, /* repz */
2586 { "hlt", { XX
}, 0 },
2587 { "cmc", { XX
}, 0 },
2588 { REG_TABLE (REG_F6
) },
2589 { REG_TABLE (REG_F7
) },
2591 { "clc", { XX
}, 0 },
2592 { "stc", { XX
}, 0 },
2593 { "cli", { XX
}, 0 },
2594 { "sti", { XX
}, 0 },
2595 { "cld", { XX
}, 0 },
2596 { "std", { XX
}, 0 },
2597 { REG_TABLE (REG_FE
) },
2598 { REG_TABLE (REG_FF
) },
2601 static const struct dis386 dis386_twobyte
[] = {
2603 { REG_TABLE (REG_0F00
) },
2604 { REG_TABLE (REG_0F01
) },
2605 { "larS", { Gv
, Ew
}, 0 },
2606 { "lslS", { Gv
, Ew
}, 0 },
2608 { "syscall", { XX
}, 0 },
2609 { "clts", { XX
}, 0 },
2610 { "sysret%LQ", { XX
}, 0 },
2612 { "invd", { XX
}, 0 },
2613 { PREFIX_TABLE (PREFIX_0F09
) },
2615 { "ud2", { XX
}, 0 },
2617 { REG_TABLE (REG_0F0D
) },
2618 { "femms", { XX
}, 0 },
2619 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2621 { PREFIX_TABLE (PREFIX_0F10
) },
2622 { PREFIX_TABLE (PREFIX_0F11
) },
2623 { PREFIX_TABLE (PREFIX_0F12
) },
2624 { MOD_TABLE (MOD_0F13
) },
2625 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2626 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2627 { PREFIX_TABLE (PREFIX_0F16
) },
2628 { MOD_TABLE (MOD_0F17
) },
2630 { REG_TABLE (REG_0F18
) },
2631 { "nopQ", { Ev
}, 0 },
2632 { PREFIX_TABLE (PREFIX_0F1A
) },
2633 { PREFIX_TABLE (PREFIX_0F1B
) },
2634 { PREFIX_TABLE (PREFIX_0F1C
) },
2635 { "nopQ", { Ev
}, 0 },
2636 { PREFIX_TABLE (PREFIX_0F1E
) },
2637 { "nopQ", { Ev
}, 0 },
2639 { "movZ", { Rm
, Cm
}, 0 },
2640 { "movZ", { Rm
, Dm
}, 0 },
2641 { "movZ", { Cm
, Rm
}, 0 },
2642 { "movZ", { Dm
, Rm
}, 0 },
2643 { MOD_TABLE (MOD_0F24
) },
2645 { MOD_TABLE (MOD_0F26
) },
2648 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2649 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2650 { PREFIX_TABLE (PREFIX_0F2A
) },
2651 { PREFIX_TABLE (PREFIX_0F2B
) },
2652 { PREFIX_TABLE (PREFIX_0F2C
) },
2653 { PREFIX_TABLE (PREFIX_0F2D
) },
2654 { PREFIX_TABLE (PREFIX_0F2E
) },
2655 { PREFIX_TABLE (PREFIX_0F2F
) },
2657 { "wrmsr", { XX
}, 0 },
2658 { "rdtsc", { XX
}, 0 },
2659 { "rdmsr", { XX
}, 0 },
2660 { "rdpmc", { XX
}, 0 },
2661 { "sysenter", { SEP
}, 0 },
2662 { "sysexit", { SEP
}, 0 },
2664 { "getsec", { XX
}, 0 },
2666 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2668 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2675 { "cmovoS", { Gv
, Ev
}, 0 },
2676 { "cmovnoS", { Gv
, Ev
}, 0 },
2677 { "cmovbS", { Gv
, Ev
}, 0 },
2678 { "cmovaeS", { Gv
, Ev
}, 0 },
2679 { "cmoveS", { Gv
, Ev
}, 0 },
2680 { "cmovneS", { Gv
, Ev
}, 0 },
2681 { "cmovbeS", { Gv
, Ev
}, 0 },
2682 { "cmovaS", { Gv
, Ev
}, 0 },
2684 { "cmovsS", { Gv
, Ev
}, 0 },
2685 { "cmovnsS", { Gv
, Ev
}, 0 },
2686 { "cmovpS", { Gv
, Ev
}, 0 },
2687 { "cmovnpS", { Gv
, Ev
}, 0 },
2688 { "cmovlS", { Gv
, Ev
}, 0 },
2689 { "cmovgeS", { Gv
, Ev
}, 0 },
2690 { "cmovleS", { Gv
, Ev
}, 0 },
2691 { "cmovgS", { Gv
, Ev
}, 0 },
2693 { MOD_TABLE (MOD_0F50
) },
2694 { PREFIX_TABLE (PREFIX_0F51
) },
2695 { PREFIX_TABLE (PREFIX_0F52
) },
2696 { PREFIX_TABLE (PREFIX_0F53
) },
2697 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2698 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2699 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2700 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2702 { PREFIX_TABLE (PREFIX_0F58
) },
2703 { PREFIX_TABLE (PREFIX_0F59
) },
2704 { PREFIX_TABLE (PREFIX_0F5A
) },
2705 { PREFIX_TABLE (PREFIX_0F5B
) },
2706 { PREFIX_TABLE (PREFIX_0F5C
) },
2707 { PREFIX_TABLE (PREFIX_0F5D
) },
2708 { PREFIX_TABLE (PREFIX_0F5E
) },
2709 { PREFIX_TABLE (PREFIX_0F5F
) },
2711 { PREFIX_TABLE (PREFIX_0F60
) },
2712 { PREFIX_TABLE (PREFIX_0F61
) },
2713 { PREFIX_TABLE (PREFIX_0F62
) },
2714 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2715 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2716 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2717 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2718 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2720 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2721 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2722 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2723 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2724 { PREFIX_TABLE (PREFIX_0F6C
) },
2725 { PREFIX_TABLE (PREFIX_0F6D
) },
2726 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2727 { PREFIX_TABLE (PREFIX_0F6F
) },
2729 { PREFIX_TABLE (PREFIX_0F70
) },
2730 { REG_TABLE (REG_0F71
) },
2731 { REG_TABLE (REG_0F72
) },
2732 { REG_TABLE (REG_0F73
) },
2733 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2734 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2735 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2736 { "emms", { XX
}, PREFIX_OPCODE
},
2738 { PREFIX_TABLE (PREFIX_0F78
) },
2739 { PREFIX_TABLE (PREFIX_0F79
) },
2742 { PREFIX_TABLE (PREFIX_0F7C
) },
2743 { PREFIX_TABLE (PREFIX_0F7D
) },
2744 { PREFIX_TABLE (PREFIX_0F7E
) },
2745 { PREFIX_TABLE (PREFIX_0F7F
) },
2747 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2748 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2749 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2750 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2751 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2752 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2753 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2754 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2756 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2757 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2758 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2759 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2760 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2761 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2762 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2763 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2765 { "seto", { Eb
}, 0 },
2766 { "setno", { Eb
}, 0 },
2767 { "setb", { Eb
}, 0 },
2768 { "setae", { Eb
}, 0 },
2769 { "sete", { Eb
}, 0 },
2770 { "setne", { Eb
}, 0 },
2771 { "setbe", { Eb
}, 0 },
2772 { "seta", { Eb
}, 0 },
2774 { "sets", { Eb
}, 0 },
2775 { "setns", { Eb
}, 0 },
2776 { "setp", { Eb
}, 0 },
2777 { "setnp", { Eb
}, 0 },
2778 { "setl", { Eb
}, 0 },
2779 { "setge", { Eb
}, 0 },
2780 { "setle", { Eb
}, 0 },
2781 { "setg", { Eb
}, 0 },
2783 { "pushT", { fs
}, 0 },
2784 { "popT", { fs
}, 0 },
2785 { "cpuid", { XX
}, 0 },
2786 { "btS", { Ev
, Gv
}, 0 },
2787 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2788 { "shldS", { Ev
, Gv
, CL
}, 0 },
2789 { REG_TABLE (REG_0FA6
) },
2790 { REG_TABLE (REG_0FA7
) },
2792 { "pushT", { gs
}, 0 },
2793 { "popT", { gs
}, 0 },
2794 { "rsm", { XX
}, 0 },
2795 { "btsS", { Evh1
, Gv
}, 0 },
2796 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2797 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2798 { REG_TABLE (REG_0FAE
) },
2799 { "imulS", { Gv
, Ev
}, 0 },
2801 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2802 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2803 { MOD_TABLE (MOD_0FB2
) },
2804 { "btrS", { Evh1
, Gv
}, 0 },
2805 { MOD_TABLE (MOD_0FB4
) },
2806 { MOD_TABLE (MOD_0FB5
) },
2807 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2808 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2810 { PREFIX_TABLE (PREFIX_0FB8
) },
2811 { "ud1S", { Gv
, Ev
}, 0 },
2812 { REG_TABLE (REG_0FBA
) },
2813 { "btcS", { Evh1
, Gv
}, 0 },
2814 { PREFIX_TABLE (PREFIX_0FBC
) },
2815 { PREFIX_TABLE (PREFIX_0FBD
) },
2816 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2817 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2819 { "xaddB", { Ebh1
, Gb
}, 0 },
2820 { "xaddS", { Evh1
, Gv
}, 0 },
2821 { PREFIX_TABLE (PREFIX_0FC2
) },
2822 { MOD_TABLE (MOD_0FC3
) },
2823 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
2824 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
2825 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2826 { REG_TABLE (REG_0FC7
) },
2828 { "bswap", { RMeAX
}, 0 },
2829 { "bswap", { RMeCX
}, 0 },
2830 { "bswap", { RMeDX
}, 0 },
2831 { "bswap", { RMeBX
}, 0 },
2832 { "bswap", { RMeSP
}, 0 },
2833 { "bswap", { RMeBP
}, 0 },
2834 { "bswap", { RMeSI
}, 0 },
2835 { "bswap", { RMeDI
}, 0 },
2837 { PREFIX_TABLE (PREFIX_0FD0
) },
2838 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2839 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2840 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2841 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2842 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2843 { PREFIX_TABLE (PREFIX_0FD6
) },
2844 { MOD_TABLE (MOD_0FD7
) },
2846 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2847 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2848 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2849 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2850 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2851 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2852 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2853 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2855 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2856 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2857 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2858 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2859 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2860 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2861 { PREFIX_TABLE (PREFIX_0FE6
) },
2862 { PREFIX_TABLE (PREFIX_0FE7
) },
2864 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
2865 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
2866 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
2867 { "por", { MX
, EM
}, PREFIX_OPCODE
},
2868 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
2869 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
2870 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
2871 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
2873 { PREFIX_TABLE (PREFIX_0FF0
) },
2874 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
2875 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
2876 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
2877 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
2878 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
2879 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
2880 { PREFIX_TABLE (PREFIX_0FF7
) },
2882 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
2883 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
2884 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
2885 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
2886 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
2887 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
2888 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
2889 { "ud0S", { Gv
, Ev
}, 0 },
2892 static const unsigned char onebyte_has_modrm
[256] = {
2893 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2894 /* ------------------------------- */
2895 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2896 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2897 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2898 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2899 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2900 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2901 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2902 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2903 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2904 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2905 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2906 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2907 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2908 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2909 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2910 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2911 /* ------------------------------- */
2912 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2915 static const unsigned char twobyte_has_modrm
[256] = {
2916 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2917 /* ------------------------------- */
2918 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2919 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2920 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2921 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2922 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2923 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2924 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2925 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2926 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2927 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2928 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2929 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2930 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2931 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2932 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2933 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2934 /* ------------------------------- */
2935 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2938 static char obuf
[100];
2940 static char *mnemonicendp
;
2941 static char scratchbuf
[100];
2942 static unsigned char *start_codep
;
2943 static unsigned char *insn_codep
;
2944 static unsigned char *codep
;
2945 static unsigned char *end_codep
;
2946 static int last_lock_prefix
;
2947 static int last_repz_prefix
;
2948 static int last_repnz_prefix
;
2949 static int last_data_prefix
;
2950 static int last_addr_prefix
;
2951 static int last_rex_prefix
;
2952 static int last_seg_prefix
;
2953 static int fwait_prefix
;
2954 /* The active segment register prefix. */
2955 static int active_seg_prefix
;
2956 #define MAX_CODE_LENGTH 15
2957 /* We can up to 14 prefixes since the maximum instruction length is
2959 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
2960 static disassemble_info
*the_info
;
2968 static unsigned char need_modrm
;
2978 int register_specifier
;
2985 int mask_register_specifier
;
2991 static unsigned char need_vex
;
2992 static unsigned char need_vex_reg
;
3000 /* If we are accessing mod/rm/reg without need_modrm set, then the
3001 values are stale. Hitting this abort likely indicates that you
3002 need to update onebyte_has_modrm or twobyte_has_modrm. */
3003 #define MODRM_CHECK if (!need_modrm) abort ()
3005 static const char **names64
;
3006 static const char **names32
;
3007 static const char **names16
;
3008 static const char **names8
;
3009 static const char **names8rex
;
3010 static const char **names_seg
;
3011 static const char *index64
;
3012 static const char *index32
;
3013 static const char **index16
;
3014 static const char **names_bnd
;
3016 static const char *intel_names64
[] = {
3017 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3018 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3020 static const char *intel_names32
[] = {
3021 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3022 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3024 static const char *intel_names16
[] = {
3025 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3026 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3028 static const char *intel_names8
[] = {
3029 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3031 static const char *intel_names8rex
[] = {
3032 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3033 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3035 static const char *intel_names_seg
[] = {
3036 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3038 static const char *intel_index64
= "riz";
3039 static const char *intel_index32
= "eiz";
3040 static const char *intel_index16
[] = {
3041 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3044 static const char *att_names64
[] = {
3045 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3046 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3048 static const char *att_names32
[] = {
3049 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3050 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3052 static const char *att_names16
[] = {
3053 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3054 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3056 static const char *att_names8
[] = {
3057 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3059 static const char *att_names8rex
[] = {
3060 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3061 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3063 static const char *att_names_seg
[] = {
3064 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3066 static const char *att_index64
= "%riz";
3067 static const char *att_index32
= "%eiz";
3068 static const char *att_index16
[] = {
3069 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3072 static const char **names_mm
;
3073 static const char *intel_names_mm
[] = {
3074 "mm0", "mm1", "mm2", "mm3",
3075 "mm4", "mm5", "mm6", "mm7"
3077 static const char *att_names_mm
[] = {
3078 "%mm0", "%mm1", "%mm2", "%mm3",
3079 "%mm4", "%mm5", "%mm6", "%mm7"
3082 static const char *intel_names_bnd
[] = {
3083 "bnd0", "bnd1", "bnd2", "bnd3"
3086 static const char *att_names_bnd
[] = {
3087 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3090 static const char **names_xmm
;
3091 static const char *intel_names_xmm
[] = {
3092 "xmm0", "xmm1", "xmm2", "xmm3",
3093 "xmm4", "xmm5", "xmm6", "xmm7",
3094 "xmm8", "xmm9", "xmm10", "xmm11",
3095 "xmm12", "xmm13", "xmm14", "xmm15",
3096 "xmm16", "xmm17", "xmm18", "xmm19",
3097 "xmm20", "xmm21", "xmm22", "xmm23",
3098 "xmm24", "xmm25", "xmm26", "xmm27",
3099 "xmm28", "xmm29", "xmm30", "xmm31"
3101 static const char *att_names_xmm
[] = {
3102 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3103 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3104 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3105 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3106 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3107 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3108 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3109 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3112 static const char **names_ymm
;
3113 static const char *intel_names_ymm
[] = {
3114 "ymm0", "ymm1", "ymm2", "ymm3",
3115 "ymm4", "ymm5", "ymm6", "ymm7",
3116 "ymm8", "ymm9", "ymm10", "ymm11",
3117 "ymm12", "ymm13", "ymm14", "ymm15",
3118 "ymm16", "ymm17", "ymm18", "ymm19",
3119 "ymm20", "ymm21", "ymm22", "ymm23",
3120 "ymm24", "ymm25", "ymm26", "ymm27",
3121 "ymm28", "ymm29", "ymm30", "ymm31"
3123 static const char *att_names_ymm
[] = {
3124 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3125 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3126 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3127 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3128 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3129 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3130 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3131 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3134 static const char **names_zmm
;
3135 static const char *intel_names_zmm
[] = {
3136 "zmm0", "zmm1", "zmm2", "zmm3",
3137 "zmm4", "zmm5", "zmm6", "zmm7",
3138 "zmm8", "zmm9", "zmm10", "zmm11",
3139 "zmm12", "zmm13", "zmm14", "zmm15",
3140 "zmm16", "zmm17", "zmm18", "zmm19",
3141 "zmm20", "zmm21", "zmm22", "zmm23",
3142 "zmm24", "zmm25", "zmm26", "zmm27",
3143 "zmm28", "zmm29", "zmm30", "zmm31"
3145 static const char *att_names_zmm
[] = {
3146 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3147 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3148 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3149 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3150 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3151 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3152 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3153 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3156 static const char **names_tmm
;
3157 static const char *intel_names_tmm
[] = {
3158 "tmm0", "tmm1", "tmm2", "tmm3",
3159 "tmm4", "tmm5", "tmm6", "tmm7"
3161 static const char *att_names_tmm
[] = {
3162 "%tmm0", "%tmm1", "%tmm2", "%tmm3",
3163 "%tmm4", "%tmm5", "%tmm6", "%tmm7"
3166 static const char **names_mask
;
3167 static const char *intel_names_mask
[] = {
3168 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3170 static const char *att_names_mask
[] = {
3171 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3174 static const char *names_rounding
[] =
3182 static const struct dis386 reg_table
[][8] = {
3185 { "addA", { Ebh1
, Ib
}, 0 },
3186 { "orA", { Ebh1
, Ib
}, 0 },
3187 { "adcA", { Ebh1
, Ib
}, 0 },
3188 { "sbbA", { Ebh1
, Ib
}, 0 },
3189 { "andA", { Ebh1
, Ib
}, 0 },
3190 { "subA", { Ebh1
, Ib
}, 0 },
3191 { "xorA", { Ebh1
, Ib
}, 0 },
3192 { "cmpA", { Eb
, Ib
}, 0 },
3196 { "addQ", { Evh1
, Iv
}, 0 },
3197 { "orQ", { Evh1
, Iv
}, 0 },
3198 { "adcQ", { Evh1
, Iv
}, 0 },
3199 { "sbbQ", { Evh1
, Iv
}, 0 },
3200 { "andQ", { Evh1
, Iv
}, 0 },
3201 { "subQ", { Evh1
, Iv
}, 0 },
3202 { "xorQ", { Evh1
, Iv
}, 0 },
3203 { "cmpQ", { Ev
, Iv
}, 0 },
3207 { "addQ", { Evh1
, sIb
}, 0 },
3208 { "orQ", { Evh1
, sIb
}, 0 },
3209 { "adcQ", { Evh1
, sIb
}, 0 },
3210 { "sbbQ", { Evh1
, sIb
}, 0 },
3211 { "andQ", { Evh1
, sIb
}, 0 },
3212 { "subQ", { Evh1
, sIb
}, 0 },
3213 { "xorQ", { Evh1
, sIb
}, 0 },
3214 { "cmpQ", { Ev
, sIb
}, 0 },
3218 { "popU", { stackEv
}, 0 },
3219 { XOP_8F_TABLE (XOP_09
) },
3223 { XOP_8F_TABLE (XOP_09
) },
3227 { "rolA", { Eb
, Ib
}, 0 },
3228 { "rorA", { Eb
, Ib
}, 0 },
3229 { "rclA", { Eb
, Ib
}, 0 },
3230 { "rcrA", { Eb
, Ib
}, 0 },
3231 { "shlA", { Eb
, Ib
}, 0 },
3232 { "shrA", { Eb
, Ib
}, 0 },
3233 { "shlA", { Eb
, Ib
}, 0 },
3234 { "sarA", { Eb
, Ib
}, 0 },
3238 { "rolQ", { Ev
, Ib
}, 0 },
3239 { "rorQ", { Ev
, Ib
}, 0 },
3240 { "rclQ", { Ev
, Ib
}, 0 },
3241 { "rcrQ", { Ev
, Ib
}, 0 },
3242 { "shlQ", { Ev
, Ib
}, 0 },
3243 { "shrQ", { Ev
, Ib
}, 0 },
3244 { "shlQ", { Ev
, Ib
}, 0 },
3245 { "sarQ", { Ev
, Ib
}, 0 },
3249 { "movA", { Ebh3
, Ib
}, 0 },
3256 { MOD_TABLE (MOD_C6_REG_7
) },
3260 { "movQ", { Evh3
, Iv
}, 0 },
3267 { MOD_TABLE (MOD_C7_REG_7
) },
3271 { "rolA", { Eb
, I1
}, 0 },
3272 { "rorA", { Eb
, I1
}, 0 },
3273 { "rclA", { Eb
, I1
}, 0 },
3274 { "rcrA", { Eb
, I1
}, 0 },
3275 { "shlA", { Eb
, I1
}, 0 },
3276 { "shrA", { Eb
, I1
}, 0 },
3277 { "shlA", { Eb
, I1
}, 0 },
3278 { "sarA", { Eb
, I1
}, 0 },
3282 { "rolQ", { Ev
, I1
}, 0 },
3283 { "rorQ", { Ev
, I1
}, 0 },
3284 { "rclQ", { Ev
, I1
}, 0 },
3285 { "rcrQ", { Ev
, I1
}, 0 },
3286 { "shlQ", { Ev
, I1
}, 0 },
3287 { "shrQ", { Ev
, I1
}, 0 },
3288 { "shlQ", { Ev
, I1
}, 0 },
3289 { "sarQ", { Ev
, I1
}, 0 },
3293 { "rolA", { Eb
, CL
}, 0 },
3294 { "rorA", { Eb
, CL
}, 0 },
3295 { "rclA", { Eb
, CL
}, 0 },
3296 { "rcrA", { Eb
, CL
}, 0 },
3297 { "shlA", { Eb
, CL
}, 0 },
3298 { "shrA", { Eb
, CL
}, 0 },
3299 { "shlA", { Eb
, CL
}, 0 },
3300 { "sarA", { Eb
, CL
}, 0 },
3304 { "rolQ", { Ev
, CL
}, 0 },
3305 { "rorQ", { Ev
, CL
}, 0 },
3306 { "rclQ", { Ev
, CL
}, 0 },
3307 { "rcrQ", { Ev
, CL
}, 0 },
3308 { "shlQ", { Ev
, CL
}, 0 },
3309 { "shrQ", { Ev
, CL
}, 0 },
3310 { "shlQ", { Ev
, CL
}, 0 },
3311 { "sarQ", { Ev
, CL
}, 0 },
3315 { "testA", { Eb
, Ib
}, 0 },
3316 { "testA", { Eb
, Ib
}, 0 },
3317 { "notA", { Ebh1
}, 0 },
3318 { "negA", { Ebh1
}, 0 },
3319 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3320 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3321 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3322 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3326 { "testQ", { Ev
, Iv
}, 0 },
3327 { "testQ", { Ev
, Iv
}, 0 },
3328 { "notQ", { Evh1
}, 0 },
3329 { "negQ", { Evh1
}, 0 },
3330 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3331 { "imulQ", { Ev
}, 0 },
3332 { "divQ", { Ev
}, 0 },
3333 { "idivQ", { Ev
}, 0 },
3337 { "incA", { Ebh1
}, 0 },
3338 { "decA", { Ebh1
}, 0 },
3342 { "incQ", { Evh1
}, 0 },
3343 { "decQ", { Evh1
}, 0 },
3344 { "call{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3345 { MOD_TABLE (MOD_FF_REG_3
) },
3346 { "jmp{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3347 { MOD_TABLE (MOD_FF_REG_5
) },
3348 { "pushU", { stackEv
}, 0 },
3353 { "sldtD", { Sv
}, 0 },
3354 { "strD", { Sv
}, 0 },
3355 { "lldt", { Ew
}, 0 },
3356 { "ltr", { Ew
}, 0 },
3357 { "verr", { Ew
}, 0 },
3358 { "verw", { Ew
}, 0 },
3364 { MOD_TABLE (MOD_0F01_REG_0
) },
3365 { MOD_TABLE (MOD_0F01_REG_1
) },
3366 { MOD_TABLE (MOD_0F01_REG_2
) },
3367 { MOD_TABLE (MOD_0F01_REG_3
) },
3368 { "smswD", { Sv
}, 0 },
3369 { MOD_TABLE (MOD_0F01_REG_5
) },
3370 { "lmsw", { Ew
}, 0 },
3371 { MOD_TABLE (MOD_0F01_REG_7
) },
3375 { "prefetch", { Mb
}, 0 },
3376 { "prefetchw", { Mb
}, 0 },
3377 { "prefetchwt1", { Mb
}, 0 },
3378 { "prefetch", { Mb
}, 0 },
3379 { "prefetch", { Mb
}, 0 },
3380 { "prefetch", { Mb
}, 0 },
3381 { "prefetch", { Mb
}, 0 },
3382 { "prefetch", { Mb
}, 0 },
3386 { MOD_TABLE (MOD_0F18_REG_0
) },
3387 { MOD_TABLE (MOD_0F18_REG_1
) },
3388 { MOD_TABLE (MOD_0F18_REG_2
) },
3389 { MOD_TABLE (MOD_0F18_REG_3
) },
3390 { MOD_TABLE (MOD_0F18_REG_4
) },
3391 { MOD_TABLE (MOD_0F18_REG_5
) },
3392 { MOD_TABLE (MOD_0F18_REG_6
) },
3393 { MOD_TABLE (MOD_0F18_REG_7
) },
3395 /* REG_0F1C_P_0_MOD_0 */
3397 { "cldemote", { Mb
}, 0 },
3398 { "nopQ", { Ev
}, 0 },
3399 { "nopQ", { Ev
}, 0 },
3400 { "nopQ", { Ev
}, 0 },
3401 { "nopQ", { Ev
}, 0 },
3402 { "nopQ", { Ev
}, 0 },
3403 { "nopQ", { Ev
}, 0 },
3404 { "nopQ", { Ev
}, 0 },
3406 /* REG_0F1E_P_1_MOD_3 */
3408 { "nopQ", { Ev
}, 0 },
3409 { "rdsspK", { Rdq
}, PREFIX_OPCODE
},
3410 { "nopQ", { Ev
}, 0 },
3411 { "nopQ", { Ev
}, 0 },
3412 { "nopQ", { Ev
}, 0 },
3413 { "nopQ", { Ev
}, 0 },
3414 { "nopQ", { Ev
}, 0 },
3415 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7
) },
3421 { MOD_TABLE (MOD_0F71_REG_2
) },
3423 { MOD_TABLE (MOD_0F71_REG_4
) },
3425 { MOD_TABLE (MOD_0F71_REG_6
) },
3431 { MOD_TABLE (MOD_0F72_REG_2
) },
3433 { MOD_TABLE (MOD_0F72_REG_4
) },
3435 { MOD_TABLE (MOD_0F72_REG_6
) },
3441 { MOD_TABLE (MOD_0F73_REG_2
) },
3442 { MOD_TABLE (MOD_0F73_REG_3
) },
3445 { MOD_TABLE (MOD_0F73_REG_6
) },
3446 { MOD_TABLE (MOD_0F73_REG_7
) },
3450 { "montmul", { { OP_0f07
, 0 } }, 0 },
3451 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3452 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3456 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3457 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3458 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3459 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3460 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3461 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3465 { MOD_TABLE (MOD_0FAE_REG_0
) },
3466 { MOD_TABLE (MOD_0FAE_REG_1
) },
3467 { MOD_TABLE (MOD_0FAE_REG_2
) },
3468 { MOD_TABLE (MOD_0FAE_REG_3
) },
3469 { MOD_TABLE (MOD_0FAE_REG_4
) },
3470 { MOD_TABLE (MOD_0FAE_REG_5
) },
3471 { MOD_TABLE (MOD_0FAE_REG_6
) },
3472 { MOD_TABLE (MOD_0FAE_REG_7
) },
3480 { "btQ", { Ev
, Ib
}, 0 },
3481 { "btsQ", { Evh1
, Ib
}, 0 },
3482 { "btrQ", { Evh1
, Ib
}, 0 },
3483 { "btcQ", { Evh1
, Ib
}, 0 },
3488 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3490 { MOD_TABLE (MOD_0FC7_REG_3
) },
3491 { MOD_TABLE (MOD_0FC7_REG_4
) },
3492 { MOD_TABLE (MOD_0FC7_REG_5
) },
3493 { MOD_TABLE (MOD_0FC7_REG_6
) },
3494 { MOD_TABLE (MOD_0FC7_REG_7
) },
3500 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3502 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3504 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3510 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3512 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3514 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3520 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3521 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3524 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3525 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3531 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3532 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3534 /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
3536 { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
) },
3538 /* REG_VEX_0F38F3 */
3541 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3542 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3543 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3545 /* REG_0FXOP_09_01_L_0 */
3548 { "blcfill", { VexGdq
, Edq
}, 0 },
3549 { "blsfill", { VexGdq
, Edq
}, 0 },
3550 { "blcs", { VexGdq
, Edq
}, 0 },
3551 { "tzmsk", { VexGdq
, Edq
}, 0 },
3552 { "blcic", { VexGdq
, Edq
}, 0 },
3553 { "blsic", { VexGdq
, Edq
}, 0 },
3554 { "t1mskc", { VexGdq
, Edq
}, 0 },
3556 /* REG_0FXOP_09_02_L_0 */
3559 { "blcmsk", { VexGdq
, Edq
}, 0 },
3564 { "blci", { VexGdq
, Edq
}, 0 },
3566 /* REG_0FXOP_09_12_M_1_L_0 */
3568 { "llwpcb", { Edq
}, 0 },
3569 { "slwpcb", { Edq
}, 0 },
3571 /* REG_0FXOP_0A_12_L_0 */
3573 { "lwpins", { VexGdq
, Ed
, Id
}, 0 },
3574 { "lwpval", { VexGdq
, Ed
, Id
}, 0 },
3577 #include "i386-dis-evex-reg.h"
3580 static const struct dis386 prefix_table
[][4] = {
3583 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3584 { "pause", { XX
}, 0 },
3585 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3586 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3589 /* PREFIX_0F01_REG_3_RM_1 */
3591 { "vmmcall", { Skip_MODRM
}, 0 },
3592 { "vmgexit", { Skip_MODRM
}, 0 },
3594 { "vmgexit", { Skip_MODRM
}, 0 },
3597 /* PREFIX_0F01_REG_5_MOD_0 */
3600 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3603 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3605 { "serialize", { Skip_MODRM
}, PREFIX_OPCODE
},
3606 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3608 { "xsusldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3611 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3616 { "xresldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3619 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3622 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3625 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3627 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
3628 { "mcommit", { Skip_MODRM
}, 0 },
3631 /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3633 { "mwaitx", { { OP_Mwait
, eBX_reg
} }, 0 },
3638 { "wbinvd", { XX
}, 0 },
3639 { "wbnoinvd", { XX
}, 0 },
3644 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3645 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3646 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3647 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3652 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3653 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3654 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3655 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3660 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3661 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3662 { MOD_TABLE (MOD_0F12_PREFIX_2
) },
3663 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3668 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3669 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3670 { MOD_TABLE (MOD_0F16_PREFIX_2
) },
3675 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3676 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3677 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3678 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3683 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3684 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3685 { "bndmov", { EbndS
, Gbnd
}, 0 },
3686 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3691 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3692 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3693 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3694 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3699 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3700 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3701 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3702 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3707 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3708 { "cvtsi2ss%LQ", { XM
, Edq
}, PREFIX_OPCODE
},
3709 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3710 { "cvtsi2sd%LQ", { XM
, Edq
}, 0 },
3715 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3716 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3717 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3718 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3723 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3724 { "cvttss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3725 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3726 { "cvttsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3731 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3732 { "cvtss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3733 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3734 { "cvtsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3739 { "ucomiss",{ XM
, EXd
}, 0 },
3741 { "ucomisd",{ XM
, EXq
}, 0 },
3746 { "comiss", { XM
, EXd
}, 0 },
3748 { "comisd", { XM
, EXq
}, 0 },
3753 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3754 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3755 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3756 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3761 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3762 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3767 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3768 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3773 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3774 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3775 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3776 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3781 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3782 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3783 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3784 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3789 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3790 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3791 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3792 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3797 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3798 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3799 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3804 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3805 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3806 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3807 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3812 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3813 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3814 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3815 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3820 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3821 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3822 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3823 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3828 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3829 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3830 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3831 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3836 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3838 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3843 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3845 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3850 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3852 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3859 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3866 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3871 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3872 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3873 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3878 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3879 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3880 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3881 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3884 /* PREFIX_0F73_REG_3 */
3888 { "psrldq", { XS
, Ib
}, 0 },
3891 /* PREFIX_0F73_REG_7 */
3895 { "pslldq", { XS
, Ib
}, 0 },
3900 {"vmread", { Em
, Gm
}, 0 },
3902 {"extrq", { XS
, Ib
, Ib
}, 0 },
3903 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3908 {"vmwrite", { Gm
, Em
}, 0 },
3910 {"extrq", { XM
, XS
}, 0 },
3911 {"insertq", { XM
, XS
}, 0 },
3918 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3919 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3926 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3927 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3932 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3933 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3934 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3939 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3940 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3941 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3944 /* PREFIX_0FAE_REG_0_MOD_3 */
3947 { "rdfsbase", { Ev
}, 0 },
3950 /* PREFIX_0FAE_REG_1_MOD_3 */
3953 { "rdgsbase", { Ev
}, 0 },
3956 /* PREFIX_0FAE_REG_2_MOD_3 */
3959 { "wrfsbase", { Ev
}, 0 },
3962 /* PREFIX_0FAE_REG_3_MOD_3 */
3965 { "wrgsbase", { Ev
}, 0 },
3968 /* PREFIX_0FAE_REG_4_MOD_0 */
3970 { "xsave", { FXSAVE
}, 0 },
3971 { "ptwrite%LQ", { Edq
}, 0 },
3974 /* PREFIX_0FAE_REG_4_MOD_3 */
3977 { "ptwrite%LQ", { Edq
}, 0 },
3980 /* PREFIX_0FAE_REG_5_MOD_0 */
3982 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
3985 /* PREFIX_0FAE_REG_5_MOD_3 */
3987 { "lfence", { Skip_MODRM
}, 0 },
3988 { "incsspK", { Rdq
}, PREFIX_OPCODE
},
3991 /* PREFIX_0FAE_REG_6_MOD_0 */
3993 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
3994 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
3995 { "clwb", { Mb
}, PREFIX_OPCODE
},
3998 /* PREFIX_0FAE_REG_6_MOD_3 */
4000 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0
) },
4001 { "umonitor", { Eva
}, PREFIX_OPCODE
},
4002 { "tpause", { Edq
}, PREFIX_OPCODE
},
4003 { "umwait", { Edq
}, PREFIX_OPCODE
},
4006 /* PREFIX_0FAE_REG_7_MOD_0 */
4008 { "clflush", { Mb
}, 0 },
4010 { "clflushopt", { Mb
}, 0 },
4016 { "popcntS", { Gv
, Ev
}, 0 },
4021 { "bsfS", { Gv
, Ev
}, 0 },
4022 { "tzcntS", { Gv
, Ev
}, 0 },
4023 { "bsfS", { Gv
, Ev
}, 0 },
4028 { "bsrS", { Gv
, Ev
}, 0 },
4029 { "lzcntS", { Gv
, Ev
}, 0 },
4030 { "bsrS", { Gv
, Ev
}, 0 },
4035 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4036 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4037 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4038 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4041 /* PREFIX_0FC3_MOD_0 */
4043 { "movntiS", { Edq
, Gdq
}, PREFIX_OPCODE
},
4046 /* PREFIX_0FC7_REG_6_MOD_0 */
4048 { "vmptrld",{ Mq
}, 0 },
4049 { "vmxon", { Mq
}, 0 },
4050 { "vmclear",{ Mq
}, 0 },
4053 /* PREFIX_0FC7_REG_6_MOD_3 */
4055 { "rdrand", { Ev
}, 0 },
4057 { "rdrand", { Ev
}, 0 }
4060 /* PREFIX_0FC7_REG_7_MOD_3 */
4062 { "rdseed", { Ev
}, 0 },
4063 { "rdpid", { Em
}, 0 },
4064 { "rdseed", { Ev
}, 0 },
4071 { "addsubpd", { XM
, EXx
}, 0 },
4072 { "addsubps", { XM
, EXx
}, 0 },
4078 { "movq2dq",{ XM
, MS
}, 0 },
4079 { "movq", { EXqS
, XM
}, 0 },
4080 { "movdq2q",{ MX
, XS
}, 0 },
4086 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4087 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4088 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4093 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4095 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4103 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4108 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4110 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4117 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4124 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4131 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4138 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4145 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4152 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4159 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4166 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4173 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4180 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4187 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4194 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4201 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4208 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4215 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4222 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4229 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4236 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4243 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4250 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4257 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4264 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4271 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4278 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4285 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4292 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4299 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4306 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4313 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4320 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4327 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4334 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4341 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4348 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4353 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4358 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4363 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4368 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4373 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4378 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4385 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_OPCODE
},
4392 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4399 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4406 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4413 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4420 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4425 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4427 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4428 { "crc32A", { Gdq
, Eb
}, PREFIX_OPCODE
},
4433 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4435 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4436 { "crc32Q", { Gdq
, Ev
}, PREFIX_OPCODE
},
4443 { MOD_TABLE (MOD_0F38F5_PREFIX_2
) },
4448 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
4449 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4450 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4457 { MOD_TABLE (MOD_0F38F8_PREFIX_1
) },
4458 { MOD_TABLE (MOD_0F38F8_PREFIX_2
) },
4459 { MOD_TABLE (MOD_0F38F8_PREFIX_3
) },
4464 { MOD_TABLE (MOD_0F38F9_PREFIX_0
) },
4471 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4478 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4485 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4492 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4499 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4506 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4513 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4520 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4527 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4534 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4541 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4548 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4555 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4562 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4569 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4576 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4583 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4590 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4597 { "pcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4604 { "pcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4611 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4618 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4623 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4630 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4637 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4644 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4647 /* PREFIX_VEX_0F10 */
4649 { "vmovups", { XM
, EXx
}, 0 },
4650 { "vmovss", { XMVexScalar
, VexScalar
, EXxmm_md
}, 0 },
4651 { "vmovupd", { XM
, EXx
}, 0 },
4652 { "vmovsd", { XMVexScalar
, VexScalar
, EXxmm_mq
}, 0 },
4655 /* PREFIX_VEX_0F11 */
4657 { "vmovups", { EXxS
, XM
}, 0 },
4658 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
4659 { "vmovupd", { EXxS
, XM
}, 0 },
4660 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
4663 /* PREFIX_VEX_0F12 */
4665 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4666 { "vmovsldup", { XM
, EXx
}, 0 },
4667 { MOD_TABLE (MOD_VEX_0F12_PREFIX_2
) },
4668 { "vmovddup", { XM
, EXymmq
}, 0 },
4671 /* PREFIX_VEX_0F16 */
4673 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4674 { "vmovshdup", { XM
, EXx
}, 0 },
4675 { MOD_TABLE (MOD_VEX_0F16_PREFIX_2
) },
4678 /* PREFIX_VEX_0F2A */
4681 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4683 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4686 /* PREFIX_VEX_0F2C */
4689 { "vcvttss2si", { Gdq
, EXxmm_md
}, 0 },
4691 { "vcvttsd2si", { Gdq
, EXxmm_mq
}, 0 },
4694 /* PREFIX_VEX_0F2D */
4697 { "vcvtss2si", { Gdq
, EXxmm_md
}, 0 },
4699 { "vcvtsd2si", { Gdq
, EXxmm_mq
}, 0 },
4702 /* PREFIX_VEX_0F2E */
4704 { "vucomiss", { XMScalar
, EXxmm_md
}, 0 },
4706 { "vucomisd", { XMScalar
, EXxmm_mq
}, 0 },
4709 /* PREFIX_VEX_0F2F */
4711 { "vcomiss", { XMScalar
, EXxmm_md
}, 0 },
4713 { "vcomisd", { XMScalar
, EXxmm_mq
}, 0 },
4716 /* PREFIX_VEX_0F41 */
4718 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4720 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4723 /* PREFIX_VEX_0F42 */
4725 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4727 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4730 /* PREFIX_VEX_0F44 */
4732 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4734 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4737 /* PREFIX_VEX_0F45 */
4739 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4741 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4744 /* PREFIX_VEX_0F46 */
4746 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4748 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4751 /* PREFIX_VEX_0F47 */
4753 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4755 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4758 /* PREFIX_VEX_0F4A */
4760 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4762 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4765 /* PREFIX_VEX_0F4B */
4767 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4769 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4772 /* PREFIX_VEX_0F51 */
4774 { "vsqrtps", { XM
, EXx
}, 0 },
4775 { "vsqrtss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4776 { "vsqrtpd", { XM
, EXx
}, 0 },
4777 { "vsqrtsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4780 /* PREFIX_VEX_0F52 */
4782 { "vrsqrtps", { XM
, EXx
}, 0 },
4783 { "vrsqrtss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4786 /* PREFIX_VEX_0F53 */
4788 { "vrcpps", { XM
, EXx
}, 0 },
4789 { "vrcpss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4792 /* PREFIX_VEX_0F58 */
4794 { "vaddps", { XM
, Vex
, EXx
}, 0 },
4795 { "vaddss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4796 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
4797 { "vaddsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4800 /* PREFIX_VEX_0F59 */
4802 { "vmulps", { XM
, Vex
, EXx
}, 0 },
4803 { "vmulss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4804 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
4805 { "vmulsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4808 /* PREFIX_VEX_0F5A */
4810 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
4811 { "vcvtss2sd", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4812 { "vcvtpd2ps%XY",{ XMM
, EXx
}, 0 },
4813 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4816 /* PREFIX_VEX_0F5B */
4818 { "vcvtdq2ps", { XM
, EXx
}, 0 },
4819 { "vcvttps2dq", { XM
, EXx
}, 0 },
4820 { "vcvtps2dq", { XM
, EXx
}, 0 },
4823 /* PREFIX_VEX_0F5C */
4825 { "vsubps", { XM
, Vex
, EXx
}, 0 },
4826 { "vsubss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4827 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
4828 { "vsubsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4831 /* PREFIX_VEX_0F5D */
4833 { "vminps", { XM
, Vex
, EXx
}, 0 },
4834 { "vminss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4835 { "vminpd", { XM
, Vex
, EXx
}, 0 },
4836 { "vminsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4839 /* PREFIX_VEX_0F5E */
4841 { "vdivps", { XM
, Vex
, EXx
}, 0 },
4842 { "vdivss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4843 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
4844 { "vdivsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4847 /* PREFIX_VEX_0F5F */
4849 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
4850 { "vmaxss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4851 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
4852 { "vmaxsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4855 /* PREFIX_VEX_0F60 */
4859 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
4862 /* PREFIX_VEX_0F61 */
4866 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
4869 /* PREFIX_VEX_0F62 */
4873 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
4876 /* PREFIX_VEX_0F63 */
4880 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
4883 /* PREFIX_VEX_0F64 */
4887 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
4890 /* PREFIX_VEX_0F65 */
4894 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
4897 /* PREFIX_VEX_0F66 */
4901 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
4904 /* PREFIX_VEX_0F67 */
4908 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
4911 /* PREFIX_VEX_0F68 */
4915 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
4918 /* PREFIX_VEX_0F69 */
4922 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
4925 /* PREFIX_VEX_0F6A */
4929 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
4932 /* PREFIX_VEX_0F6B */
4936 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
4939 /* PREFIX_VEX_0F6C */
4943 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
4946 /* PREFIX_VEX_0F6D */
4950 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
4953 /* PREFIX_VEX_0F6E */
4957 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4960 /* PREFIX_VEX_0F6F */
4963 { "vmovdqu", { XM
, EXx
}, 0 },
4964 { "vmovdqa", { XM
, EXx
}, 0 },
4967 /* PREFIX_VEX_0F70 */
4970 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
4971 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
4972 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
4975 /* PREFIX_VEX_0F71_REG_2 */
4979 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
4982 /* PREFIX_VEX_0F71_REG_4 */
4986 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
4989 /* PREFIX_VEX_0F71_REG_6 */
4993 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
4996 /* PREFIX_VEX_0F72_REG_2 */
5000 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
5003 /* PREFIX_VEX_0F72_REG_4 */
5007 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
5010 /* PREFIX_VEX_0F72_REG_6 */
5014 { "vpslld", { Vex
, XS
, Ib
}, 0 },
5017 /* PREFIX_VEX_0F73_REG_2 */
5021 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
5024 /* PREFIX_VEX_0F73_REG_3 */
5028 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
5031 /* PREFIX_VEX_0F73_REG_6 */
5035 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
5038 /* PREFIX_VEX_0F73_REG_7 */
5042 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
5045 /* PREFIX_VEX_0F74 */
5049 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
5052 /* PREFIX_VEX_0F75 */
5056 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
5059 /* PREFIX_VEX_0F76 */
5063 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
5066 /* PREFIX_VEX_0F77 */
5068 { VEX_LEN_TABLE (VEX_LEN_0F77_P_0
) },
5071 /* PREFIX_VEX_0F7C */
5075 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
5076 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
5079 /* PREFIX_VEX_0F7D */
5083 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
5084 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
5087 /* PREFIX_VEX_0F7E */
5090 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5091 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5094 /* PREFIX_VEX_0F7F */
5097 { "vmovdqu", { EXxS
, XM
}, 0 },
5098 { "vmovdqa", { EXxS
, XM
}, 0 },
5101 /* PREFIX_VEX_0F90 */
5103 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5105 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5108 /* PREFIX_VEX_0F91 */
5110 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5112 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5115 /* PREFIX_VEX_0F92 */
5117 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5119 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5120 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5123 /* PREFIX_VEX_0F93 */
5125 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5127 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5128 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5131 /* PREFIX_VEX_0F98 */
5133 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5135 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5138 /* PREFIX_VEX_0F99 */
5140 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5142 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5145 /* PREFIX_VEX_0FC2 */
5147 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
5148 { "vcmpss", { XMScalar
, VexScalar
, EXxmm_md
, VCMP
}, 0 },
5149 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
5150 { "vcmpsd", { XMScalar
, VexScalar
, EXxmm_mq
, VCMP
}, 0 },
5153 /* PREFIX_VEX_0FC4 */
5157 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5160 /* PREFIX_VEX_0FC5 */
5164 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5167 /* PREFIX_VEX_0FD0 */
5171 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
5172 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
5175 /* PREFIX_VEX_0FD1 */
5179 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
5182 /* PREFIX_VEX_0FD2 */
5186 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
5189 /* PREFIX_VEX_0FD3 */
5193 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
5196 /* PREFIX_VEX_0FD4 */
5200 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
5203 /* PREFIX_VEX_0FD5 */
5207 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
5210 /* PREFIX_VEX_0FD6 */
5214 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5217 /* PREFIX_VEX_0FD7 */
5221 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5224 /* PREFIX_VEX_0FD8 */
5228 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
5231 /* PREFIX_VEX_0FD9 */
5235 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
5238 /* PREFIX_VEX_0FDA */
5242 { "vpminub", { XM
, Vex
, EXx
}, 0 },
5245 /* PREFIX_VEX_0FDB */
5249 { "vpand", { XM
, Vex
, EXx
}, 0 },
5252 /* PREFIX_VEX_0FDC */
5256 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
5259 /* PREFIX_VEX_0FDD */
5263 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
5266 /* PREFIX_VEX_0FDE */
5270 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
5273 /* PREFIX_VEX_0FDF */
5277 { "vpandn", { XM
, Vex
, EXx
}, 0 },
5280 /* PREFIX_VEX_0FE0 */
5284 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
5287 /* PREFIX_VEX_0FE1 */
5291 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
5294 /* PREFIX_VEX_0FE2 */
5298 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
5301 /* PREFIX_VEX_0FE3 */
5305 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
5308 /* PREFIX_VEX_0FE4 */
5312 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
5315 /* PREFIX_VEX_0FE5 */
5319 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
5322 /* PREFIX_VEX_0FE6 */
5325 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
5326 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
5327 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
5330 /* PREFIX_VEX_0FE7 */
5334 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5337 /* PREFIX_VEX_0FE8 */
5341 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
5344 /* PREFIX_VEX_0FE9 */
5348 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
5351 /* PREFIX_VEX_0FEA */
5355 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
5358 /* PREFIX_VEX_0FEB */
5362 { "vpor", { XM
, Vex
, EXx
}, 0 },
5365 /* PREFIX_VEX_0FEC */
5369 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
5372 /* PREFIX_VEX_0FED */
5376 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
5379 /* PREFIX_VEX_0FEE */
5383 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
5386 /* PREFIX_VEX_0FEF */
5390 { "vpxor", { XM
, Vex
, EXx
}, 0 },
5393 /* PREFIX_VEX_0FF0 */
5398 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5401 /* PREFIX_VEX_0FF1 */
5405 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
5408 /* PREFIX_VEX_0FF2 */
5412 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
5415 /* PREFIX_VEX_0FF3 */
5419 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
5422 /* PREFIX_VEX_0FF4 */
5426 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
5429 /* PREFIX_VEX_0FF5 */
5433 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
5436 /* PREFIX_VEX_0FF6 */
5440 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
5443 /* PREFIX_VEX_0FF7 */
5447 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5450 /* PREFIX_VEX_0FF8 */
5454 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
5457 /* PREFIX_VEX_0FF9 */
5461 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
5464 /* PREFIX_VEX_0FFA */
5468 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
5471 /* PREFIX_VEX_0FFB */
5475 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
5478 /* PREFIX_VEX_0FFC */
5482 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
5485 /* PREFIX_VEX_0FFD */
5489 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
5492 /* PREFIX_VEX_0FFE */
5496 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
5499 /* PREFIX_VEX_0F3800 */
5503 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
5506 /* PREFIX_VEX_0F3801 */
5510 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
5513 /* PREFIX_VEX_0F3802 */
5517 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
5520 /* PREFIX_VEX_0F3803 */
5524 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
5527 /* PREFIX_VEX_0F3804 */
5531 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
5534 /* PREFIX_VEX_0F3805 */
5538 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
5541 /* PREFIX_VEX_0F3806 */
5545 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
5548 /* PREFIX_VEX_0F3807 */
5552 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
5555 /* PREFIX_VEX_0F3808 */
5559 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
5562 /* PREFIX_VEX_0F3809 */
5566 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
5569 /* PREFIX_VEX_0F380A */
5573 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
5576 /* PREFIX_VEX_0F380B */
5580 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
5583 /* PREFIX_VEX_0F380C */
5587 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5590 /* PREFIX_VEX_0F380D */
5594 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5597 /* PREFIX_VEX_0F380E */
5601 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5604 /* PREFIX_VEX_0F380F */
5608 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5611 /* PREFIX_VEX_0F3813 */
5615 { VEX_W_TABLE (VEX_W_0F3813_P_2
) },
5618 /* PREFIX_VEX_0F3816 */
5622 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5625 /* PREFIX_VEX_0F3817 */
5629 { "vptest", { XM
, EXx
}, 0 },
5632 /* PREFIX_VEX_0F3818 */
5636 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5639 /* PREFIX_VEX_0F3819 */
5643 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5646 /* PREFIX_VEX_0F381A */
5650 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5653 /* PREFIX_VEX_0F381C */
5657 { "vpabsb", { XM
, EXx
}, 0 },
5660 /* PREFIX_VEX_0F381D */
5664 { "vpabsw", { XM
, EXx
}, 0 },
5667 /* PREFIX_VEX_0F381E */
5671 { "vpabsd", { XM
, EXx
}, 0 },
5674 /* PREFIX_VEX_0F3820 */
5678 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
5681 /* PREFIX_VEX_0F3821 */
5685 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
5688 /* PREFIX_VEX_0F3822 */
5692 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
5695 /* PREFIX_VEX_0F3823 */
5699 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
5702 /* PREFIX_VEX_0F3824 */
5706 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
5709 /* PREFIX_VEX_0F3825 */
5713 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
5716 /* PREFIX_VEX_0F3828 */
5720 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
5723 /* PREFIX_VEX_0F3829 */
5727 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
5730 /* PREFIX_VEX_0F382A */
5734 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5737 /* PREFIX_VEX_0F382B */
5741 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
5744 /* PREFIX_VEX_0F382C */
5748 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5751 /* PREFIX_VEX_0F382D */
5755 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5758 /* PREFIX_VEX_0F382E */
5762 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5765 /* PREFIX_VEX_0F382F */
5769 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5772 /* PREFIX_VEX_0F3830 */
5776 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
5779 /* PREFIX_VEX_0F3831 */
5783 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
5786 /* PREFIX_VEX_0F3832 */
5790 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
5793 /* PREFIX_VEX_0F3833 */
5797 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
5800 /* PREFIX_VEX_0F3834 */
5804 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
5807 /* PREFIX_VEX_0F3835 */
5811 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
5814 /* PREFIX_VEX_0F3836 */
5818 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5821 /* PREFIX_VEX_0F3837 */
5825 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
5828 /* PREFIX_VEX_0F3838 */
5832 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
5835 /* PREFIX_VEX_0F3839 */
5839 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
5842 /* PREFIX_VEX_0F383A */
5846 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
5849 /* PREFIX_VEX_0F383B */
5853 { "vpminud", { XM
, Vex
, EXx
}, 0 },
5856 /* PREFIX_VEX_0F383C */
5860 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
5863 /* PREFIX_VEX_0F383D */
5867 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
5870 /* PREFIX_VEX_0F383E */
5874 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
5877 /* PREFIX_VEX_0F383F */
5881 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
5884 /* PREFIX_VEX_0F3840 */
5888 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
5891 /* PREFIX_VEX_0F3841 */
5895 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5898 /* PREFIX_VEX_0F3845 */
5902 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
5905 /* PREFIX_VEX_0F3846 */
5909 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5912 /* PREFIX_VEX_0F3847 */
5916 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
5919 /* PREFIX_VEX_0F3849_X86_64 */
5921 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0
) },
5923 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2
) },
5924 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3
) },
5927 /* PREFIX_VEX_0F384B_X86_64 */
5930 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1
) },
5931 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2
) },
5932 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3
) },
5935 /* PREFIX_VEX_0F3858 */
5939 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5942 /* PREFIX_VEX_0F3859 */
5946 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5949 /* PREFIX_VEX_0F385A */
5953 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5956 /* PREFIX_VEX_0F385C_X86_64 */
5959 { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1
) },
5963 /* PREFIX_VEX_0F385E_X86_64 */
5965 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0
) },
5966 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1
) },
5967 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2
) },
5968 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3
) },
5971 /* PREFIX_VEX_0F3878 */
5975 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5978 /* PREFIX_VEX_0F3879 */
5982 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5985 /* PREFIX_VEX_0F388C */
5989 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5992 /* PREFIX_VEX_0F388E */
5996 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
5999 /* PREFIX_VEX_0F3890 */
6003 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6006 /* PREFIX_VEX_0F3891 */
6010 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6013 /* PREFIX_VEX_0F3892 */
6017 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6020 /* PREFIX_VEX_0F3893 */
6024 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6027 /* PREFIX_VEX_0F3896 */
6031 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6034 /* PREFIX_VEX_0F3897 */
6038 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6041 /* PREFIX_VEX_0F3898 */
6045 { "vfmadd132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6048 /* PREFIX_VEX_0F3899 */
6052 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6055 /* PREFIX_VEX_0F389A */
6059 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6062 /* PREFIX_VEX_0F389B */
6066 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6069 /* PREFIX_VEX_0F389C */
6073 { "vfnmadd132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6076 /* PREFIX_VEX_0F389D */
6080 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6083 /* PREFIX_VEX_0F389E */
6087 { "vfnmsub132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6090 /* PREFIX_VEX_0F389F */
6094 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6097 /* PREFIX_VEX_0F38A6 */
6101 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6105 /* PREFIX_VEX_0F38A7 */
6109 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6112 /* PREFIX_VEX_0F38A8 */
6116 { "vfmadd213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6119 /* PREFIX_VEX_0F38A9 */
6123 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6126 /* PREFIX_VEX_0F38AA */
6130 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6133 /* PREFIX_VEX_0F38AB */
6137 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6140 /* PREFIX_VEX_0F38AC */
6144 { "vfnmadd213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6147 /* PREFIX_VEX_0F38AD */
6151 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6154 /* PREFIX_VEX_0F38AE */
6158 { "vfnmsub213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6161 /* PREFIX_VEX_0F38AF */
6165 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6168 /* PREFIX_VEX_0F38B6 */
6172 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6175 /* PREFIX_VEX_0F38B7 */
6179 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6182 /* PREFIX_VEX_0F38B8 */
6186 { "vfmadd231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6189 /* PREFIX_VEX_0F38B9 */
6193 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6196 /* PREFIX_VEX_0F38BA */
6200 { "vfmsub231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6203 /* PREFIX_VEX_0F38BB */
6207 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6210 /* PREFIX_VEX_0F38BC */
6214 { "vfnmadd231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6217 /* PREFIX_VEX_0F38BD */
6221 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6224 /* PREFIX_VEX_0F38BE */
6228 { "vfnmsub231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6231 /* PREFIX_VEX_0F38BF */
6235 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6238 /* PREFIX_VEX_0F38CF */
6242 { VEX_W_TABLE (VEX_W_0F38CF_P_2
) },
6245 /* PREFIX_VEX_0F38DB */
6249 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6252 /* PREFIX_VEX_0F38DC */
6256 { "vaesenc", { XM
, Vex
, EXx
}, 0 },
6259 /* PREFIX_VEX_0F38DD */
6263 { "vaesenclast", { XM
, Vex
, EXx
}, 0 },
6266 /* PREFIX_VEX_0F38DE */
6270 { "vaesdec", { XM
, Vex
, EXx
}, 0 },
6273 /* PREFIX_VEX_0F38DF */
6277 { "vaesdeclast", { XM
, Vex
, EXx
}, 0 },
6280 /* PREFIX_VEX_0F38F2 */
6282 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6285 /* PREFIX_VEX_0F38F3_REG_1 */
6287 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6290 /* PREFIX_VEX_0F38F3_REG_2 */
6292 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6295 /* PREFIX_VEX_0F38F3_REG_3 */
6297 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6300 /* PREFIX_VEX_0F38F5 */
6302 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6303 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6305 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6308 /* PREFIX_VEX_0F38F6 */
6313 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6316 /* PREFIX_VEX_0F38F7 */
6318 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6319 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6320 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6321 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6324 /* PREFIX_VEX_0F3A00 */
6328 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6331 /* PREFIX_VEX_0F3A01 */
6335 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6338 /* PREFIX_VEX_0F3A02 */
6342 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6345 /* PREFIX_VEX_0F3A04 */
6349 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6352 /* PREFIX_VEX_0F3A05 */
6356 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6359 /* PREFIX_VEX_0F3A06 */
6363 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6366 /* PREFIX_VEX_0F3A08 */
6370 { "vroundps", { XM
, EXx
, Ib
}, 0 },
6373 /* PREFIX_VEX_0F3A09 */
6377 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
6380 /* PREFIX_VEX_0F3A0A */
6384 { "vroundss", { XMScalar
, VexScalar
, EXxmm_md
, Ib
}, 0 },
6387 /* PREFIX_VEX_0F3A0B */
6391 { "vroundsd", { XMScalar
, VexScalar
, EXxmm_mq
, Ib
}, 0 },
6394 /* PREFIX_VEX_0F3A0C */
6398 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
6401 /* PREFIX_VEX_0F3A0D */
6405 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
6408 /* PREFIX_VEX_0F3A0E */
6412 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
6415 /* PREFIX_VEX_0F3A0F */
6419 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
6422 /* PREFIX_VEX_0F3A14 */
6426 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6429 /* PREFIX_VEX_0F3A15 */
6433 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6436 /* PREFIX_VEX_0F3A16 */
6440 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6443 /* PREFIX_VEX_0F3A17 */
6447 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6450 /* PREFIX_VEX_0F3A18 */
6454 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6457 /* PREFIX_VEX_0F3A19 */
6461 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6464 /* PREFIX_VEX_0F3A1D */
6468 { VEX_W_TABLE (VEX_W_0F3A1D_P_2
) },
6471 /* PREFIX_VEX_0F3A20 */
6475 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6478 /* PREFIX_VEX_0F3A21 */
6482 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6485 /* PREFIX_VEX_0F3A22 */
6489 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6492 /* PREFIX_VEX_0F3A30 */
6496 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6499 /* PREFIX_VEX_0F3A31 */
6503 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6506 /* PREFIX_VEX_0F3A32 */
6510 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6513 /* PREFIX_VEX_0F3A33 */
6517 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6520 /* PREFIX_VEX_0F3A38 */
6524 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6527 /* PREFIX_VEX_0F3A39 */
6531 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6534 /* PREFIX_VEX_0F3A40 */
6538 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
6541 /* PREFIX_VEX_0F3A41 */
6545 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6548 /* PREFIX_VEX_0F3A42 */
6552 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
6555 /* PREFIX_VEX_0F3A44 */
6559 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, 0 },
6562 /* PREFIX_VEX_0F3A46 */
6566 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6569 /* PREFIX_VEX_0F3A48 */
6573 { "vpermil2ps", { XM
, Vex
, EXx
, XMVexI4
, VexI4
}, 0 },
6576 /* PREFIX_VEX_0F3A49 */
6580 { "vpermil2pd", { XM
, Vex
, EXx
, XMVexI4
, VexI4
}, 0 },
6583 /* PREFIX_VEX_0F3A4A */
6587 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6590 /* PREFIX_VEX_0F3A4B */
6594 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6597 /* PREFIX_VEX_0F3A4C */
6601 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6604 /* PREFIX_VEX_0F3A5C */
6608 { "vfmaddsubps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6611 /* PREFIX_VEX_0F3A5D */
6615 { "vfmaddsubpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6618 /* PREFIX_VEX_0F3A5E */
6622 { "vfmsubaddps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6625 /* PREFIX_VEX_0F3A5F */
6629 { "vfmsubaddpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6632 /* PREFIX_VEX_0F3A60 */
6636 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6640 /* PREFIX_VEX_0F3A61 */
6644 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6647 /* PREFIX_VEX_0F3A62 */
6651 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6654 /* PREFIX_VEX_0F3A63 */
6658 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6661 /* PREFIX_VEX_0F3A68 */
6665 { "vfmaddps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6668 /* PREFIX_VEX_0F3A69 */
6672 { "vfmaddpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6675 /* PREFIX_VEX_0F3A6A */
6679 { "vfmaddss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, 0 },
6682 /* PREFIX_VEX_0F3A6B */
6686 { "vfmaddsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, 0 },
6689 /* PREFIX_VEX_0F3A6C */
6693 { "vfmsubps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6696 /* PREFIX_VEX_0F3A6D */
6700 { "vfmsubpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6703 /* PREFIX_VEX_0F3A6E */
6707 { "vfmsubss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, 0 },
6710 /* PREFIX_VEX_0F3A6F */
6714 { "vfmsubsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, 0 },
6717 /* PREFIX_VEX_0F3A78 */
6721 { "vfnmaddps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6724 /* PREFIX_VEX_0F3A79 */
6728 { "vfnmaddpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6731 /* PREFIX_VEX_0F3A7A */
6735 { "vfnmaddss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, 0 },
6738 /* PREFIX_VEX_0F3A7B */
6742 { "vfnmaddsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, 0 },
6745 /* PREFIX_VEX_0F3A7C */
6749 { "vfnmsubps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6753 /* PREFIX_VEX_0F3A7D */
6757 { "vfnmsubpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6760 /* PREFIX_VEX_0F3A7E */
6764 { "vfnmsubss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, 0 },
6767 /* PREFIX_VEX_0F3A7F */
6771 { "vfnmsubsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, 0 },
6774 /* PREFIX_VEX_0F3ACE */
6778 { VEX_W_TABLE (VEX_W_0F3ACE_P_2
) },
6781 /* PREFIX_VEX_0F3ACF */
6785 { VEX_W_TABLE (VEX_W_0F3ACF_P_2
) },
6788 /* PREFIX_VEX_0F3ADF */
6792 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6795 /* PREFIX_VEX_0F3AF0 */
6800 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6803 #include "i386-dis-evex-prefix.h"
6806 static const struct dis386 x86_64_table
[][2] = {
6809 { "pushP", { es
}, 0 },
6814 { "popP", { es
}, 0 },
6819 { "pushP", { cs
}, 0 },
6824 { "pushP", { ss
}, 0 },
6829 { "popP", { ss
}, 0 },
6834 { "pushP", { ds
}, 0 },
6839 { "popP", { ds
}, 0 },
6844 { "daa", { XX
}, 0 },
6849 { "das", { XX
}, 0 },
6854 { "aaa", { XX
}, 0 },
6859 { "aas", { XX
}, 0 },
6864 { "pushaP", { XX
}, 0 },
6869 { "popaP", { XX
}, 0 },
6874 { MOD_TABLE (MOD_62_32BIT
) },
6875 { EVEX_TABLE (EVEX_0F
) },
6880 { "arpl", { Ew
, Gw
}, 0 },
6881 { "movs", { { OP_G
, movsxd_mode
}, { MOVSXD_Fixup
, movsxd_mode
} }, 0 },
6886 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6887 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6892 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6893 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6898 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
6899 { REG_TABLE (REG_80
) },
6904 { "{l|}call{T|}", { Ap
}, 0 },
6909 { "retP", { Iw
, BND
}, 0 },
6910 { "ret@", { Iw
, BND
}, 0 },
6915 { "retP", { BND
}, 0 },
6916 { "ret@", { BND
}, 0 },
6921 { MOD_TABLE (MOD_C4_32BIT
) },
6922 { VEX_C4_TABLE (VEX_0F
) },
6927 { MOD_TABLE (MOD_C5_32BIT
) },
6928 { VEX_C5_TABLE (VEX_0F
) },
6933 { "into", { XX
}, 0 },
6938 { "aam", { Ib
}, 0 },
6943 { "aad", { Ib
}, 0 },
6948 { "callP", { Jv
, BND
}, 0 },
6949 { "call@", { Jv
, BND
}, 0 }
6954 { "jmpP", { Jv
, BND
}, 0 },
6955 { "jmp@", { Jv
, BND
}, 0 }
6960 { "{l|}jmp{T|}", { Ap
}, 0 },
6963 /* X86_64_0F01_REG_0 */
6965 { "sgdt{Q|Q}", { M
}, 0 },
6966 { "sgdt", { M
}, 0 },
6969 /* X86_64_0F01_REG_1 */
6971 { "sidt{Q|Q}", { M
}, 0 },
6972 { "sidt", { M
}, 0 },
6975 /* X86_64_0F01_REG_2 */
6977 { "lgdt{Q|Q}", { M
}, 0 },
6978 { "lgdt", { M
}, 0 },
6981 /* X86_64_0F01_REG_3 */
6983 { "lidt{Q|Q}", { M
}, 0 },
6984 { "lidt", { M
}, 0 },
6987 /* X86_64_VEX_0F3849 */
6990 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64
) },
6993 /* X86_64_VEX_0F384B */
6996 { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64
) },
6999 /* X86_64_VEX_0F385C */
7002 { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64
) },
7005 /* X86_64_VEX_0F385E */
7008 { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64
) },
7012 static const struct dis386 three_byte_table
[][256] = {
7014 /* THREE_BYTE_0F38 */
7017 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
7018 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
7019 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
7020 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
7021 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
7022 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
7023 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
7024 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
7026 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
7027 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
7028 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
7029 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
7035 { PREFIX_TABLE (PREFIX_0F3810
) },
7039 { PREFIX_TABLE (PREFIX_0F3814
) },
7040 { PREFIX_TABLE (PREFIX_0F3815
) },
7042 { PREFIX_TABLE (PREFIX_0F3817
) },
7048 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
7049 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
7050 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
7053 { PREFIX_TABLE (PREFIX_0F3820
) },
7054 { PREFIX_TABLE (PREFIX_0F3821
) },
7055 { PREFIX_TABLE (PREFIX_0F3822
) },
7056 { PREFIX_TABLE (PREFIX_0F3823
) },
7057 { PREFIX_TABLE (PREFIX_0F3824
) },
7058 { PREFIX_TABLE (PREFIX_0F3825
) },
7062 { PREFIX_TABLE (PREFIX_0F3828
) },
7063 { PREFIX_TABLE (PREFIX_0F3829
) },
7064 { PREFIX_TABLE (PREFIX_0F382A
) },
7065 { PREFIX_TABLE (PREFIX_0F382B
) },
7071 { PREFIX_TABLE (PREFIX_0F3830
) },
7072 { PREFIX_TABLE (PREFIX_0F3831
) },
7073 { PREFIX_TABLE (PREFIX_0F3832
) },
7074 { PREFIX_TABLE (PREFIX_0F3833
) },
7075 { PREFIX_TABLE (PREFIX_0F3834
) },
7076 { PREFIX_TABLE (PREFIX_0F3835
) },
7078 { PREFIX_TABLE (PREFIX_0F3837
) },
7080 { PREFIX_TABLE (PREFIX_0F3838
) },
7081 { PREFIX_TABLE (PREFIX_0F3839
) },
7082 { PREFIX_TABLE (PREFIX_0F383A
) },
7083 { PREFIX_TABLE (PREFIX_0F383B
) },
7084 { PREFIX_TABLE (PREFIX_0F383C
) },
7085 { PREFIX_TABLE (PREFIX_0F383D
) },
7086 { PREFIX_TABLE (PREFIX_0F383E
) },
7087 { PREFIX_TABLE (PREFIX_0F383F
) },
7089 { PREFIX_TABLE (PREFIX_0F3840
) },
7090 { PREFIX_TABLE (PREFIX_0F3841
) },
7161 { PREFIX_TABLE (PREFIX_0F3880
) },
7162 { PREFIX_TABLE (PREFIX_0F3881
) },
7163 { PREFIX_TABLE (PREFIX_0F3882
) },
7242 { PREFIX_TABLE (PREFIX_0F38C8
) },
7243 { PREFIX_TABLE (PREFIX_0F38C9
) },
7244 { PREFIX_TABLE (PREFIX_0F38CA
) },
7245 { PREFIX_TABLE (PREFIX_0F38CB
) },
7246 { PREFIX_TABLE (PREFIX_0F38CC
) },
7247 { PREFIX_TABLE (PREFIX_0F38CD
) },
7249 { PREFIX_TABLE (PREFIX_0F38CF
) },
7263 { PREFIX_TABLE (PREFIX_0F38DB
) },
7264 { PREFIX_TABLE (PREFIX_0F38DC
) },
7265 { PREFIX_TABLE (PREFIX_0F38DD
) },
7266 { PREFIX_TABLE (PREFIX_0F38DE
) },
7267 { PREFIX_TABLE (PREFIX_0F38DF
) },
7287 { PREFIX_TABLE (PREFIX_0F38F0
) },
7288 { PREFIX_TABLE (PREFIX_0F38F1
) },
7292 { PREFIX_TABLE (PREFIX_0F38F5
) },
7293 { PREFIX_TABLE (PREFIX_0F38F6
) },
7296 { PREFIX_TABLE (PREFIX_0F38F8
) },
7297 { PREFIX_TABLE (PREFIX_0F38F9
) },
7305 /* THREE_BYTE_0F3A */
7317 { PREFIX_TABLE (PREFIX_0F3A08
) },
7318 { PREFIX_TABLE (PREFIX_0F3A09
) },
7319 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7320 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7321 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7322 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7323 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7324 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7330 { PREFIX_TABLE (PREFIX_0F3A14
) },
7331 { PREFIX_TABLE (PREFIX_0F3A15
) },
7332 { PREFIX_TABLE (PREFIX_0F3A16
) },
7333 { PREFIX_TABLE (PREFIX_0F3A17
) },
7344 { PREFIX_TABLE (PREFIX_0F3A20
) },
7345 { PREFIX_TABLE (PREFIX_0F3A21
) },
7346 { PREFIX_TABLE (PREFIX_0F3A22
) },
7380 { PREFIX_TABLE (PREFIX_0F3A40
) },
7381 { PREFIX_TABLE (PREFIX_0F3A41
) },
7382 { PREFIX_TABLE (PREFIX_0F3A42
) },
7384 { PREFIX_TABLE (PREFIX_0F3A44
) },
7416 { PREFIX_TABLE (PREFIX_0F3A60
) },
7417 { PREFIX_TABLE (PREFIX_0F3A61
) },
7418 { PREFIX_TABLE (PREFIX_0F3A62
) },
7419 { PREFIX_TABLE (PREFIX_0F3A63
) },
7537 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7539 { PREFIX_TABLE (PREFIX_0F3ACE
) },
7540 { PREFIX_TABLE (PREFIX_0F3ACF
) },
7558 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7598 static const struct dis386 xop_table
[][256] = {
7751 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85
) },
7752 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86
) },
7753 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87
) },
7761 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E
) },
7762 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F
) },
7769 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95
) },
7770 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96
) },
7771 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97
) },
7779 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E
) },
7780 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F
) },
7784 { "vpcmov", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7785 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3
) },
7788 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6
) },
7806 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6
) },
7818 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0
) },
7819 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1
) },
7820 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2
) },
7821 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3
) },
7831 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7832 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7833 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7834 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7867 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7868 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7869 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7870 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
7894 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01
) },
7895 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02
) },
7913 { MOD_TABLE (MOD_VEX_0FXOP_09_12
) },
8037 { VEX_W_TABLE (VEX_W_0FXOP_09_80
) },
8038 { VEX_W_TABLE (VEX_W_0FXOP_09_81
) },
8039 { VEX_W_TABLE (VEX_W_0FXOP_09_82
) },
8040 { VEX_W_TABLE (VEX_W_0FXOP_09_83
) },
8055 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90
) },
8056 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91
) },
8057 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92
) },
8058 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93
) },
8059 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94
) },
8060 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95
) },
8061 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96
) },
8062 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97
) },
8064 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98
) },
8065 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99
) },
8066 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A
) },
8067 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B
) },
8110 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1
) },
8111 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2
) },
8112 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3
) },
8115 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6
) },
8116 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7
) },
8121 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB
) },
8128 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1
) },
8129 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2
) },
8130 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3
) },
8133 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6
) },
8134 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7
) },
8139 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB
) },
8146 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1
) },
8147 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2
) },
8148 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3
) },
8202 { "bextrS", { Gdq
, Edq
, Id
}, 0 },
8204 { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12
) },
8474 static const struct dis386 vex_table
[][256] = {
8496 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8497 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8498 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8499 { MOD_TABLE (MOD_VEX_0F13
) },
8500 { "vunpcklpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8501 { "vunpckhpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8502 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8503 { MOD_TABLE (MOD_VEX_0F17
) },
8523 { "vmovapX", { XM
, EXx
}, PREFIX_OPCODE
},
8524 { "vmovapX", { EXxS
, XM
}, PREFIX_OPCODE
},
8525 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8526 { MOD_TABLE (MOD_VEX_0F2B
) },
8527 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8528 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8529 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8530 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8551 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8552 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8554 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8555 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8556 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8557 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8561 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8562 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8568 { MOD_TABLE (MOD_VEX_0F50
) },
8569 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8570 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8571 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8572 { "vandpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8573 { "vandnpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8574 { "vorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8575 { "vxorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8577 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8578 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8579 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8580 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8581 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8582 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8583 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8584 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8586 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8587 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8588 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8589 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8590 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8591 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8592 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8593 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8595 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8596 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8597 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8598 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8599 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8600 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8601 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8602 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8604 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8605 { REG_TABLE (REG_VEX_0F71
) },
8606 { REG_TABLE (REG_VEX_0F72
) },
8607 { REG_TABLE (REG_VEX_0F73
) },
8608 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8609 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8610 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8611 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8617 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8618 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8619 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8620 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8640 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8641 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8642 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8643 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8649 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8650 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8673 { REG_TABLE (REG_VEX_0FAE
) },
8696 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8698 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8699 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8700 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, PREFIX_OPCODE
},
8712 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8713 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8714 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8715 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8716 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8717 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8718 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8719 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8721 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8722 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8723 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8724 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8725 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8726 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8727 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8728 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8730 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8731 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8732 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8733 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8734 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8735 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8736 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8737 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8739 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8740 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8741 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8742 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8743 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8744 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8745 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8746 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8748 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8749 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8750 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8751 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8752 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8753 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8754 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8755 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8757 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8758 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8759 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8760 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8761 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8762 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8763 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8769 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8770 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8771 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8774 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8775 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8776 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8779 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8780 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8781 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8782 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8783 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8784 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8785 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8790 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8793 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8794 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8796 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8797 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8798 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8800 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8801 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8802 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8805 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8806 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8807 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8808 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8809 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8810 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8814 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8815 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8816 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8817 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8818 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8819 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8820 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8821 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8823 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8824 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8825 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8826 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8827 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8828 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8829 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8830 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8832 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8833 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8834 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8835 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8836 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8837 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8838 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8839 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8841 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8842 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8846 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8847 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8848 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8851 { X86_64_TABLE (X86_64_VEX_0F3849
) },
8853 { X86_64_TABLE (X86_64_VEX_0F384B
) },
8868 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8869 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8870 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
8872 { X86_64_TABLE (X86_64_VEX_0F385C
) },
8874 { X86_64_TABLE (X86_64_VEX_0F385E
) },
8904 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
8905 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
8926 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
8928 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
8931 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
8932 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
8934 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
8940 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
8941 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
8942 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
8943 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
8944 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
8945 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
8946 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
8947 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
8955 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
8956 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
8958 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
8959 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
8960 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
8961 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
8962 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
8963 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
8964 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
8965 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
8973 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
8974 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
8976 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
8977 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
8978 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
8979 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
8980 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
8981 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
8982 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
8983 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
9001 { PREFIX_TABLE (PREFIX_VEX_0F38CF
) },
9015 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
9016 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
9017 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
9018 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
9019 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
9041 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
9042 { REG_TABLE (REG_VEX_0F38F3
) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
9045 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
9046 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
9060 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
9061 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
9062 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
9064 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
9065 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
9066 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
9069 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
9070 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9071 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9072 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9073 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9074 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9075 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9076 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9082 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9083 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9084 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9085 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9087 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9088 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9092 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9096 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9097 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9098 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9114 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9115 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9116 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9117 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9123 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9124 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9132 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9133 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9134 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9136 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9138 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9141 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9142 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9143 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9144 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9145 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9163 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9164 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9165 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9166 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9168 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9169 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9170 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9171 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9177 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9178 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9179 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9180 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9181 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9182 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9183 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9184 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9195 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9196 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9197 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9198 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9199 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9200 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9201 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9202 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9291 { PREFIX_TABLE(PREFIX_VEX_0F3ACE
) },
9292 { PREFIX_TABLE(PREFIX_VEX_0F3ACF
) },
9310 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9330 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9350 #include "i386-dis-evex.h"
9352 static const struct dis386 vex_len_table
[][2] = {
9353 /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
9355 { "vmovlpX", { XM
, Vex128
, EXq
}, 0 },
9358 /* VEX_LEN_0F12_P_0_M_1 */
9360 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
9363 /* VEX_LEN_0F13_M_0 */
9365 { "vmovlpX", { EXq
, XM
}, PREFIX_OPCODE
},
9368 /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
9370 { "vmovhpX", { XM
, Vex128
, EXq
}, 0 },
9373 /* VEX_LEN_0F16_P_0_M_1 */
9375 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
9378 /* VEX_LEN_0F17_M_0 */
9380 { "vmovhpX", { EXq
, XM
}, PREFIX_OPCODE
},
9383 /* VEX_LEN_0F41_P_0 */
9386 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9388 /* VEX_LEN_0F41_P_2 */
9391 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9393 /* VEX_LEN_0F42_P_0 */
9396 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9398 /* VEX_LEN_0F42_P_2 */
9401 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9403 /* VEX_LEN_0F44_P_0 */
9405 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9407 /* VEX_LEN_0F44_P_2 */
9409 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9411 /* VEX_LEN_0F45_P_0 */
9414 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9416 /* VEX_LEN_0F45_P_2 */
9419 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9421 /* VEX_LEN_0F46_P_0 */
9424 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9426 /* VEX_LEN_0F46_P_2 */
9429 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9431 /* VEX_LEN_0F47_P_0 */
9434 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9436 /* VEX_LEN_0F47_P_2 */
9439 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9441 /* VEX_LEN_0F4A_P_0 */
9444 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9446 /* VEX_LEN_0F4A_P_2 */
9449 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9451 /* VEX_LEN_0F4B_P_0 */
9454 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9456 /* VEX_LEN_0F4B_P_2 */
9459 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9462 /* VEX_LEN_0F6E_P_2 */
9464 { "vmovK", { XMScalar
, Edq
}, 0 },
9467 /* VEX_LEN_0F77_P_1 */
9469 { "vzeroupper", { XX
}, 0 },
9470 { "vzeroall", { XX
}, 0 },
9473 /* VEX_LEN_0F7E_P_1 */
9475 { "vmovq", { XMScalar
, EXxmm_mq
}, 0 },
9478 /* VEX_LEN_0F7E_P_2 */
9480 { "vmovK", { Edq
, XMScalar
}, 0 },
9483 /* VEX_LEN_0F90_P_0 */
9485 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9488 /* VEX_LEN_0F90_P_2 */
9490 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9493 /* VEX_LEN_0F91_P_0 */
9495 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9498 /* VEX_LEN_0F91_P_2 */
9500 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9503 /* VEX_LEN_0F92_P_0 */
9505 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9508 /* VEX_LEN_0F92_P_2 */
9510 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9513 /* VEX_LEN_0F92_P_3 */
9515 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0
) },
9518 /* VEX_LEN_0F93_P_0 */
9520 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9523 /* VEX_LEN_0F93_P_2 */
9525 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9528 /* VEX_LEN_0F93_P_3 */
9530 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0
) },
9533 /* VEX_LEN_0F98_P_0 */
9535 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9538 /* VEX_LEN_0F98_P_2 */
9540 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9543 /* VEX_LEN_0F99_P_0 */
9545 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9548 /* VEX_LEN_0F99_P_2 */
9550 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9553 /* VEX_LEN_0FAE_R_2_M_0 */
9555 { "vldmxcsr", { Md
}, 0 },
9558 /* VEX_LEN_0FAE_R_3_M_0 */
9560 { "vstmxcsr", { Md
}, 0 },
9563 /* VEX_LEN_0FC4_P_2 */
9565 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
9568 /* VEX_LEN_0FC5_P_2 */
9570 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
9573 /* VEX_LEN_0FD6_P_2 */
9575 { "vmovq", { EXqVexScalarS
, XMScalar
}, 0 },
9578 /* VEX_LEN_0FF7_P_2 */
9580 { "vmaskmovdqu", { XM
, XS
}, 0 },
9583 /* VEX_LEN_0F3816_P_2 */
9586 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9589 /* VEX_LEN_0F3819_P_2 */
9592 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9595 /* VEX_LEN_0F381A_P_2_M_0 */
9598 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9601 /* VEX_LEN_0F3836_P_2 */
9604 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9607 /* VEX_LEN_0F3841_P_2 */
9609 { "vphminposuw", { XM
, EXx
}, 0 },
9612 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
9614 { "ldtilecfg", { M
}, 0 },
9617 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
9619 { "tilerelease", { Skip_MODRM
}, 0 },
9622 /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
9624 { "sttilecfg", { M
}, 0 },
9627 /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
9629 { "tilezero", { TMM
, Skip_MODRM
}, 0 },
9632 /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
9634 { "tilestored", { MVexSIBMEM
, TMM
}, 0 },
9636 /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
9638 { "tileloaddt1", { TMM
, MVexSIBMEM
}, 0 },
9641 /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
9643 { "tileloadd", { TMM
, MVexSIBMEM
}, 0 },
9646 /* VEX_LEN_0F385A_P_2_M_0 */
9649 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9652 /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
9654 { "tdpbf16ps", { TMM
, EXtmm
, VexTmm
}, 0 },
9657 /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
9659 { "tdpbuud", {TMM
, EXtmm
, VexTmm
}, 0 },
9662 /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
9664 { "tdpbsud", {TMM
, EXtmm
, VexTmm
}, 0 },
9667 /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
9669 { "tdpbusd", {TMM
, EXtmm
, VexTmm
}, 0 },
9672 /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
9674 { "tdpbssd", {TMM
, EXtmm
, VexTmm
}, 0 },
9677 /* VEX_LEN_0F38DB_P_2 */
9679 { "vaesimc", { XM
, EXx
}, 0 },
9682 /* VEX_LEN_0F38F2_P_0 */
9684 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
9687 /* VEX_LEN_0F38F3_R_1_P_0 */
9689 { "blsrS", { VexGdq
, Edq
}, 0 },
9692 /* VEX_LEN_0F38F3_R_2_P_0 */
9694 { "blsmskS", { VexGdq
, Edq
}, 0 },
9697 /* VEX_LEN_0F38F3_R_3_P_0 */
9699 { "blsiS", { VexGdq
, Edq
}, 0 },
9702 /* VEX_LEN_0F38F5_P_0 */
9704 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
9707 /* VEX_LEN_0F38F5_P_1 */
9709 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
9712 /* VEX_LEN_0F38F5_P_3 */
9714 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
9717 /* VEX_LEN_0F38F6_P_3 */
9719 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
9722 /* VEX_LEN_0F38F7_P_0 */
9724 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
9727 /* VEX_LEN_0F38F7_P_1 */
9729 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
9732 /* VEX_LEN_0F38F7_P_2 */
9734 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
9737 /* VEX_LEN_0F38F7_P_3 */
9739 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
9742 /* VEX_LEN_0F3A00_P_2 */
9745 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
9748 /* VEX_LEN_0F3A01_P_2 */
9751 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
9754 /* VEX_LEN_0F3A06_P_2 */
9757 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
9760 /* VEX_LEN_0F3A14_P_2 */
9762 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
9765 /* VEX_LEN_0F3A15_P_2 */
9767 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
9770 /* VEX_LEN_0F3A16_P_2 */
9772 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
9775 /* VEX_LEN_0F3A17_P_2 */
9777 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
9780 /* VEX_LEN_0F3A18_P_2 */
9783 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
9786 /* VEX_LEN_0F3A19_P_2 */
9789 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
9792 /* VEX_LEN_0F3A20_P_2 */
9794 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
9797 /* VEX_LEN_0F3A21_P_2 */
9799 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
9802 /* VEX_LEN_0F3A22_P_2 */
9804 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
9807 /* VEX_LEN_0F3A30_P_2 */
9809 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
9812 /* VEX_LEN_0F3A31_P_2 */
9814 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
9817 /* VEX_LEN_0F3A32_P_2 */
9819 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
9822 /* VEX_LEN_0F3A33_P_2 */
9824 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
9827 /* VEX_LEN_0F3A38_P_2 */
9830 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
9833 /* VEX_LEN_0F3A39_P_2 */
9836 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
9839 /* VEX_LEN_0F3A41_P_2 */
9841 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
9844 /* VEX_LEN_0F3A46_P_2 */
9847 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
9850 /* VEX_LEN_0F3A60_P_2 */
9852 { "vpcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9855 /* VEX_LEN_0F3A61_P_2 */
9857 { "vpcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9860 /* VEX_LEN_0F3A62_P_2 */
9862 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
9865 /* VEX_LEN_0F3A63_P_2 */
9867 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
9870 /* VEX_LEN_0F3ADF_P_2 */
9872 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
9875 /* VEX_LEN_0F3AF0_P_3 */
9877 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
9880 /* VEX_LEN_0FXOP_08_85 */
9882 { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0
) },
9885 /* VEX_LEN_0FXOP_08_86 */
9887 { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0
) },
9890 /* VEX_LEN_0FXOP_08_87 */
9892 { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0
) },
9895 /* VEX_LEN_0FXOP_08_8E */
9897 { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0
) },
9900 /* VEX_LEN_0FXOP_08_8F */
9902 { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0
) },
9905 /* VEX_LEN_0FXOP_08_95 */
9907 { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0
) },
9910 /* VEX_LEN_0FXOP_08_96 */
9912 { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0
) },
9915 /* VEX_LEN_0FXOP_08_97 */
9917 { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0
) },
9920 /* VEX_LEN_0FXOP_08_9E */
9922 { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0
) },
9925 /* VEX_LEN_0FXOP_08_9F */
9927 { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0
) },
9930 /* VEX_LEN_0FXOP_08_A3 */
9932 { "vpperm", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
9935 /* VEX_LEN_0FXOP_08_A6 */
9937 { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0
) },
9940 /* VEX_LEN_0FXOP_08_B6 */
9942 { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0
) },
9945 /* VEX_LEN_0FXOP_08_C0 */
9947 { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0
) },
9950 /* VEX_LEN_0FXOP_08_C1 */
9952 { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0
) },
9955 /* VEX_LEN_0FXOP_08_C2 */
9957 { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0
) },
9960 /* VEX_LEN_0FXOP_08_C3 */
9962 { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0
) },
9965 /* VEX_LEN_0FXOP_08_CC */
9967 { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0
) },
9970 /* VEX_LEN_0FXOP_08_CD */
9972 { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0
) },
9975 /* VEX_LEN_0FXOP_08_CE */
9977 { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0
) },
9980 /* VEX_LEN_0FXOP_08_CF */
9982 { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0
) },
9985 /* VEX_LEN_0FXOP_08_EC */
9987 { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0
) },
9990 /* VEX_LEN_0FXOP_08_ED */
9992 { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0
) },
9995 /* VEX_LEN_0FXOP_08_EE */
9997 { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0
) },
10000 /* VEX_LEN_0FXOP_08_EF */
10002 { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0
) },
10005 /* VEX_LEN_0FXOP_09_01 */
10007 { REG_TABLE (REG_0FXOP_09_01_L_0
) },
10010 /* VEX_LEN_0FXOP_09_02 */
10012 { REG_TABLE (REG_0FXOP_09_02_L_0
) },
10015 /* VEX_LEN_0FXOP_09_12_M_1 */
10017 { REG_TABLE (REG_0FXOP_09_12_M_1_L_0
) },
10020 /* VEX_LEN_0FXOP_09_82_W_0 */
10022 { "vfrczss", { XM
, EXd
}, 0 },
10025 /* VEX_LEN_0FXOP_09_83_W_0 */
10027 { "vfrczsd", { XM
, EXq
}, 0 },
10030 /* VEX_LEN_0FXOP_09_90 */
10032 { "vprotb", { XM
, EXx
, VexW
}, 0 },
10035 /* VEX_LEN_0FXOP_09_91 */
10037 { "vprotw", { XM
, EXx
, VexW
}, 0 },
10040 /* VEX_LEN_0FXOP_09_92 */
10042 { "vprotd", { XM
, EXx
, VexW
}, 0 },
10045 /* VEX_LEN_0FXOP_09_93 */
10047 { "vprotq", { XM
, EXx
, VexW
}, 0 },
10050 /* VEX_LEN_0FXOP_09_94 */
10052 { "vpshlb", { XM
, EXx
, VexW
}, 0 },
10055 /* VEX_LEN_0FXOP_09_95 */
10057 { "vpshlw", { XM
, EXx
, VexW
}, 0 },
10060 /* VEX_LEN_0FXOP_09_96 */
10062 { "vpshld", { XM
, EXx
, VexW
}, 0 },
10065 /* VEX_LEN_0FXOP_09_97 */
10067 { "vpshlq", { XM
, EXx
, VexW
}, 0 },
10070 /* VEX_LEN_0FXOP_09_98 */
10072 { "vpshab", { XM
, EXx
, VexW
}, 0 },
10075 /* VEX_LEN_0FXOP_09_99 */
10077 { "vpshaw", { XM
, EXx
, VexW
}, 0 },
10080 /* VEX_LEN_0FXOP_09_9A */
10082 { "vpshad", { XM
, EXx
, VexW
}, 0 },
10085 /* VEX_LEN_0FXOP_09_9B */
10087 { "vpshaq", { XM
, EXx
, VexW
}, 0 },
10090 /* VEX_LEN_0FXOP_09_C1 */
10092 { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0
) },
10095 /* VEX_LEN_0FXOP_09_C2 */
10097 { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0
) },
10100 /* VEX_LEN_0FXOP_09_C3 */
10102 { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0
) },
10105 /* VEX_LEN_0FXOP_09_C6 */
10107 { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0
) },
10110 /* VEX_LEN_0FXOP_09_C7 */
10112 { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0
) },
10115 /* VEX_LEN_0FXOP_09_CB */
10117 { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0
) },
10120 /* VEX_LEN_0FXOP_09_D1 */
10122 { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0
) },
10125 /* VEX_LEN_0FXOP_09_D2 */
10127 { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0
) },
10130 /* VEX_LEN_0FXOP_09_D3 */
10132 { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0
) },
10135 /* VEX_LEN_0FXOP_09_D6 */
10137 { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0
) },
10140 /* VEX_LEN_0FXOP_09_D7 */
10142 { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0
) },
10145 /* VEX_LEN_0FXOP_09_DB */
10147 { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0
) },
10150 /* VEX_LEN_0FXOP_09_E1 */
10152 { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0
) },
10155 /* VEX_LEN_0FXOP_09_E2 */
10157 { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0
) },
10160 /* VEX_LEN_0FXOP_09_E3 */
10162 { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0
) },
10165 /* VEX_LEN_0FXOP_0A_12 */
10167 { REG_TABLE (REG_0FXOP_0A_12_L_0
) },
10171 #include "i386-dis-evex-len.h"
10173 static const struct dis386 vex_w_table
[][2] = {
10175 /* VEX_W_0F41_P_0_LEN_1 */
10176 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
10177 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
10180 /* VEX_W_0F41_P_2_LEN_1 */
10181 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
10182 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
10185 /* VEX_W_0F42_P_0_LEN_1 */
10186 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
10187 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
10190 /* VEX_W_0F42_P_2_LEN_1 */
10191 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
10192 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
10195 /* VEX_W_0F44_P_0_LEN_0 */
10196 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
10197 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
10200 /* VEX_W_0F44_P_2_LEN_0 */
10201 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
10202 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
10205 /* VEX_W_0F45_P_0_LEN_1 */
10206 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
10207 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
10210 /* VEX_W_0F45_P_2_LEN_1 */
10211 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
10212 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
10215 /* VEX_W_0F46_P_0_LEN_1 */
10216 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
10217 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
10220 /* VEX_W_0F46_P_2_LEN_1 */
10221 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
10222 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
10225 /* VEX_W_0F47_P_0_LEN_1 */
10226 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
10227 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
10230 /* VEX_W_0F47_P_2_LEN_1 */
10231 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
10232 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
10235 /* VEX_W_0F4A_P_0_LEN_1 */
10236 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
10237 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
10240 /* VEX_W_0F4A_P_2_LEN_1 */
10241 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
10242 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
10245 /* VEX_W_0F4B_P_0_LEN_1 */
10246 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
10247 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
10250 /* VEX_W_0F4B_P_2_LEN_1 */
10251 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
10254 /* VEX_W_0F90_P_0_LEN_0 */
10255 { "kmovw", { MaskG
, MaskE
}, 0 },
10256 { "kmovq", { MaskG
, MaskE
}, 0 },
10259 /* VEX_W_0F90_P_2_LEN_0 */
10260 { "kmovb", { MaskG
, MaskBDE
}, 0 },
10261 { "kmovd", { MaskG
, MaskBDE
}, 0 },
10264 /* VEX_W_0F91_P_0_LEN_0 */
10265 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
10266 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
10269 /* VEX_W_0F91_P_2_LEN_0 */
10270 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
10271 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
10274 /* VEX_W_0F92_P_0_LEN_0 */
10275 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
10278 /* VEX_W_0F92_P_2_LEN_0 */
10279 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
10282 /* VEX_W_0F93_P_0_LEN_0 */
10283 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
10286 /* VEX_W_0F93_P_2_LEN_0 */
10287 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
10290 /* VEX_W_0F98_P_0_LEN_0 */
10291 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
10292 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
10295 /* VEX_W_0F98_P_2_LEN_0 */
10296 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
10297 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
10300 /* VEX_W_0F99_P_0_LEN_0 */
10301 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
10302 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
10305 /* VEX_W_0F99_P_2_LEN_0 */
10306 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
10307 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
10310 /* VEX_W_0F380C_P_2 */
10311 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
10314 /* VEX_W_0F380D_P_2 */
10315 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
10318 /* VEX_W_0F380E_P_2 */
10319 { "vtestps", { XM
, EXx
}, 0 },
10322 /* VEX_W_0F380F_P_2 */
10323 { "vtestpd", { XM
, EXx
}, 0 },
10326 /* VEX_W_0F3813_P_2 */
10327 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
10330 /* VEX_W_0F3816_P_2 */
10331 { "vpermps", { XM
, Vex
, EXx
}, 0 },
10334 /* VEX_W_0F3818_P_2 */
10335 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
10338 /* VEX_W_0F3819_P_2 */
10339 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
10342 /* VEX_W_0F381A_P_2_M_0 */
10343 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
10346 /* VEX_W_0F382C_P_2_M_0 */
10347 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
10350 /* VEX_W_0F382D_P_2_M_0 */
10351 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
10354 /* VEX_W_0F382E_P_2_M_0 */
10355 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
10358 /* VEX_W_0F382F_P_2_M_0 */
10359 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
10362 /* VEX_W_0F3836_P_2 */
10363 { "vpermd", { XM
, Vex
, EXx
}, 0 },
10366 /* VEX_W_0F3846_P_2 */
10367 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
10370 /* VEX_W_0F3849_X86_64_P_0 */
10371 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0
) },
10374 /* VEX_W_0F3849_X86_64_P_2 */
10375 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0
) },
10378 /* VEX_W_0F3849_X86_64_P_3 */
10379 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0
) },
10382 /* VEX_W_0F384B_X86_64_P_1 */
10383 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0
) },
10386 /* VEX_W_0F384B_X86_64_P_2 */
10387 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0
) },
10390 /* VEX_W_0F384B_X86_64_P_3 */
10391 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0
) },
10394 /* VEX_W_0F3858_P_2 */
10395 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
10398 /* VEX_W_0F3859_P_2 */
10399 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
10402 /* VEX_W_0F385A_P_2_M_0 */
10403 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
10406 /* VEX_W_0F385C_X86_64_P_1 */
10407 { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0
) },
10410 /* VEX_W_0F385E_X86_64_P_0 */
10411 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0
) },
10414 /* VEX_W_0F385E_X86_64_P_1 */
10415 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0
) },
10418 /* VEX_W_0F385E_X86_64_P_2 */
10419 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0
) },
10422 /* VEX_W_0F385E_X86_64_P_3 */
10423 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0
) },
10426 /* VEX_W_0F3878_P_2 */
10427 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
10430 /* VEX_W_0F3879_P_2 */
10431 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
10434 /* VEX_W_0F38CF_P_2 */
10435 { "vgf2p8mulb", { XM
, Vex
, EXx
}, 0 },
10438 /* VEX_W_0F3A00_P_2 */
10440 { "vpermq", { XM
, EXx
, Ib
}, 0 },
10443 /* VEX_W_0F3A01_P_2 */
10445 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
10448 /* VEX_W_0F3A02_P_2 */
10449 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
10452 /* VEX_W_0F3A04_P_2 */
10453 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
10456 /* VEX_W_0F3A05_P_2 */
10457 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
10460 /* VEX_W_0F3A06_P_2 */
10461 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10464 /* VEX_W_0F3A18_P_2 */
10465 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10468 /* VEX_W_0F3A19_P_2 */
10469 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
10472 /* VEX_W_0F3A1D_P_2 */
10473 { "vcvtps2ph", { EXxmmq
, XM
, EXxEVexS
, Ib
}, 0 },
10476 /* VEX_W_0F3A30_P_2_LEN_0 */
10477 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
10478 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
10481 /* VEX_W_0F3A31_P_2_LEN_0 */
10482 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
10483 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
10486 /* VEX_W_0F3A32_P_2_LEN_0 */
10487 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
10488 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
10491 /* VEX_W_0F3A33_P_2_LEN_0 */
10492 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
10493 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
10496 /* VEX_W_0F3A38_P_2 */
10497 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10500 /* VEX_W_0F3A39_P_2 */
10501 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
10504 /* VEX_W_0F3A46_P_2 */
10505 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10508 /* VEX_W_0F3A4A_P_2 */
10509 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10512 /* VEX_W_0F3A4B_P_2 */
10513 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10516 /* VEX_W_0F3A4C_P_2 */
10517 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10520 /* VEX_W_0F3ACE_P_2 */
10522 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10525 /* VEX_W_0F3ACF_P_2 */
10527 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10529 /* VEX_W_0FXOP_08_85_L_0 */
10531 { "vpmacssww", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10533 /* VEX_W_0FXOP_08_86_L_0 */
10535 { "vpmacsswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10537 /* VEX_W_0FXOP_08_87_L_0 */
10539 { "vpmacssdql", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10541 /* VEX_W_0FXOP_08_8E_L_0 */
10543 { "vpmacssdd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10545 /* VEX_W_0FXOP_08_8F_L_0 */
10547 { "vpmacssdqh", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10549 /* VEX_W_0FXOP_08_95_L_0 */
10551 { "vpmacsww", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10553 /* VEX_W_0FXOP_08_96_L_0 */
10555 { "vpmacswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10557 /* VEX_W_0FXOP_08_97_L_0 */
10559 { "vpmacsdql", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10561 /* VEX_W_0FXOP_08_9E_L_0 */
10563 { "vpmacsdd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10565 /* VEX_W_0FXOP_08_9F_L_0 */
10567 { "vpmacsdqh", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10569 /* VEX_W_0FXOP_08_A6_L_0 */
10571 { "vpmadcsswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10573 /* VEX_W_0FXOP_08_B6_L_0 */
10575 { "vpmadcswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10577 /* VEX_W_0FXOP_08_C0_L_0 */
10579 { "vprotb", { XM
, EXx
, Ib
}, 0 },
10581 /* VEX_W_0FXOP_08_C1_L_0 */
10583 { "vprotw", { XM
, EXx
, Ib
}, 0 },
10585 /* VEX_W_0FXOP_08_C2_L_0 */
10587 { "vprotd", { XM
, EXx
, Ib
}, 0 },
10589 /* VEX_W_0FXOP_08_C3_L_0 */
10591 { "vprotq", { XM
, EXx
, Ib
}, 0 },
10593 /* VEX_W_0FXOP_08_CC_L_0 */
10595 { "vpcomb", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10597 /* VEX_W_0FXOP_08_CD_L_0 */
10599 { "vpcomw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10601 /* VEX_W_0FXOP_08_CE_L_0 */
10603 { "vpcomd", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10605 /* VEX_W_0FXOP_08_CF_L_0 */
10607 { "vpcomq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10609 /* VEX_W_0FXOP_08_EC_L_0 */
10611 { "vpcomub", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10613 /* VEX_W_0FXOP_08_ED_L_0 */
10615 { "vpcomuw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10617 /* VEX_W_0FXOP_08_EE_L_0 */
10619 { "vpcomud", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10621 /* VEX_W_0FXOP_08_EF_L_0 */
10623 { "vpcomuq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10625 /* VEX_W_0FXOP_09_80 */
10627 { "vfrczps", { XM
, EXx
}, 0 },
10629 /* VEX_W_0FXOP_09_81 */
10631 { "vfrczpd", { XM
, EXx
}, 0 },
10633 /* VEX_W_0FXOP_09_82 */
10635 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0
) },
10637 /* VEX_W_0FXOP_09_83 */
10639 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0
) },
10641 /* VEX_W_0FXOP_09_C1_L_0 */
10643 { "vphaddbw", { XM
, EXxmm
}, 0 },
10645 /* VEX_W_0FXOP_09_C2_L_0 */
10647 { "vphaddbd", { XM
, EXxmm
}, 0 },
10649 /* VEX_W_0FXOP_09_C3_L_0 */
10651 { "vphaddbq", { XM
, EXxmm
}, 0 },
10653 /* VEX_W_0FXOP_09_C6_L_0 */
10655 { "vphaddwd", { XM
, EXxmm
}, 0 },
10657 /* VEX_W_0FXOP_09_C7_L_0 */
10659 { "vphaddwq", { XM
, EXxmm
}, 0 },
10661 /* VEX_W_0FXOP_09_CB_L_0 */
10663 { "vphadddq", { XM
, EXxmm
}, 0 },
10665 /* VEX_W_0FXOP_09_D1_L_0 */
10667 { "vphaddubw", { XM
, EXxmm
}, 0 },
10669 /* VEX_W_0FXOP_09_D2_L_0 */
10671 { "vphaddubd", { XM
, EXxmm
}, 0 },
10673 /* VEX_W_0FXOP_09_D3_L_0 */
10675 { "vphaddubq", { XM
, EXxmm
}, 0 },
10677 /* VEX_W_0FXOP_09_D6_L_0 */
10679 { "vphadduwd", { XM
, EXxmm
}, 0 },
10681 /* VEX_W_0FXOP_09_D7_L_0 */
10683 { "vphadduwq", { XM
, EXxmm
}, 0 },
10685 /* VEX_W_0FXOP_09_DB_L_0 */
10687 { "vphaddudq", { XM
, EXxmm
}, 0 },
10689 /* VEX_W_0FXOP_09_E1_L_0 */
10691 { "vphsubbw", { XM
, EXxmm
}, 0 },
10693 /* VEX_W_0FXOP_09_E2_L_0 */
10695 { "vphsubwd", { XM
, EXxmm
}, 0 },
10697 /* VEX_W_0FXOP_09_E3_L_0 */
10699 { "vphsubdq", { XM
, EXxmm
}, 0 },
10702 #include "i386-dis-evex-w.h"
10705 static const struct dis386 mod_table
[][2] = {
10708 { "leaS", { Gv
, M
}, 0 },
10713 { RM_TABLE (RM_C6_REG_7
) },
10718 { RM_TABLE (RM_C7_REG_7
) },
10722 { "{l|}call^", { indirEp
}, 0 },
10726 { "{l|}jmp^", { indirEp
}, 0 },
10729 /* MOD_0F01_REG_0 */
10730 { X86_64_TABLE (X86_64_0F01_REG_0
) },
10731 { RM_TABLE (RM_0F01_REG_0
) },
10734 /* MOD_0F01_REG_1 */
10735 { X86_64_TABLE (X86_64_0F01_REG_1
) },
10736 { RM_TABLE (RM_0F01_REG_1
) },
10739 /* MOD_0F01_REG_2 */
10740 { X86_64_TABLE (X86_64_0F01_REG_2
) },
10741 { RM_TABLE (RM_0F01_REG_2
) },
10744 /* MOD_0F01_REG_3 */
10745 { X86_64_TABLE (X86_64_0F01_REG_3
) },
10746 { RM_TABLE (RM_0F01_REG_3
) },
10749 /* MOD_0F01_REG_5 */
10750 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0
) },
10751 { RM_TABLE (RM_0F01_REG_5_MOD_3
) },
10754 /* MOD_0F01_REG_7 */
10755 { "invlpg", { Mb
}, 0 },
10756 { RM_TABLE (RM_0F01_REG_7_MOD_3
) },
10759 /* MOD_0F12_PREFIX_0 */
10760 { "movlpX", { XM
, EXq
}, 0 },
10761 { "movhlps", { XM
, EXq
}, 0 },
10764 /* MOD_0F12_PREFIX_2 */
10765 { "movlpX", { XM
, EXq
}, 0 },
10769 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
10772 /* MOD_0F16_PREFIX_0 */
10773 { "movhpX", { XM
, EXq
}, 0 },
10774 { "movlhps", { XM
, EXq
}, 0 },
10777 /* MOD_0F16_PREFIX_2 */
10778 { "movhpX", { XM
, EXq
}, 0 },
10782 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
10785 /* MOD_0F18_REG_0 */
10786 { "prefetchnta", { Mb
}, 0 },
10789 /* MOD_0F18_REG_1 */
10790 { "prefetcht0", { Mb
}, 0 },
10793 /* MOD_0F18_REG_2 */
10794 { "prefetcht1", { Mb
}, 0 },
10797 /* MOD_0F18_REG_3 */
10798 { "prefetcht2", { Mb
}, 0 },
10801 /* MOD_0F18_REG_4 */
10802 { "nop/reserved", { Mb
}, 0 },
10805 /* MOD_0F18_REG_5 */
10806 { "nop/reserved", { Mb
}, 0 },
10809 /* MOD_0F18_REG_6 */
10810 { "nop/reserved", { Mb
}, 0 },
10813 /* MOD_0F18_REG_7 */
10814 { "nop/reserved", { Mb
}, 0 },
10817 /* MOD_0F1A_PREFIX_0 */
10818 { "bndldx", { Gbnd
, Mv_bnd
}, 0 },
10819 { "nopQ", { Ev
}, 0 },
10822 /* MOD_0F1B_PREFIX_0 */
10823 { "bndstx", { Mv_bnd
, Gbnd
}, 0 },
10824 { "nopQ", { Ev
}, 0 },
10827 /* MOD_0F1B_PREFIX_1 */
10828 { "bndmk", { Gbnd
, Mv_bnd
}, 0 },
10829 { "nopQ", { Ev
}, 0 },
10832 /* MOD_0F1C_PREFIX_0 */
10833 { REG_TABLE (REG_0F1C_P_0_MOD_0
) },
10834 { "nopQ", { Ev
}, 0 },
10837 /* MOD_0F1E_PREFIX_1 */
10838 { "nopQ", { Ev
}, 0 },
10839 { REG_TABLE (REG_0F1E_P_1_MOD_3
) },
10844 { "movL", { Rd
, Td
}, 0 },
10849 { "movL", { Td
, Rd
}, 0 },
10852 /* MOD_0F2B_PREFIX_0 */
10853 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
10856 /* MOD_0F2B_PREFIX_1 */
10857 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
10860 /* MOD_0F2B_PREFIX_2 */
10861 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
10864 /* MOD_0F2B_PREFIX_3 */
10865 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
10870 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
10873 /* MOD_0F71_REG_2 */
10875 { "psrlw", { MS
, Ib
}, 0 },
10878 /* MOD_0F71_REG_4 */
10880 { "psraw", { MS
, Ib
}, 0 },
10883 /* MOD_0F71_REG_6 */
10885 { "psllw", { MS
, Ib
}, 0 },
10888 /* MOD_0F72_REG_2 */
10890 { "psrld", { MS
, Ib
}, 0 },
10893 /* MOD_0F72_REG_4 */
10895 { "psrad", { MS
, Ib
}, 0 },
10898 /* MOD_0F72_REG_6 */
10900 { "pslld", { MS
, Ib
}, 0 },
10903 /* MOD_0F73_REG_2 */
10905 { "psrlq", { MS
, Ib
}, 0 },
10908 /* MOD_0F73_REG_3 */
10910 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
10913 /* MOD_0F73_REG_6 */
10915 { "psllq", { MS
, Ib
}, 0 },
10918 /* MOD_0F73_REG_7 */
10920 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
10923 /* MOD_0FAE_REG_0 */
10924 { "fxsave", { FXSAVE
}, 0 },
10925 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3
) },
10928 /* MOD_0FAE_REG_1 */
10929 { "fxrstor", { FXSAVE
}, 0 },
10930 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3
) },
10933 /* MOD_0FAE_REG_2 */
10934 { "ldmxcsr", { Md
}, 0 },
10935 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3
) },
10938 /* MOD_0FAE_REG_3 */
10939 { "stmxcsr", { Md
}, 0 },
10940 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3
) },
10943 /* MOD_0FAE_REG_4 */
10944 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0
) },
10945 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3
) },
10948 /* MOD_0FAE_REG_5 */
10949 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0
) },
10950 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3
) },
10953 /* MOD_0FAE_REG_6 */
10954 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0
) },
10955 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3
) },
10958 /* MOD_0FAE_REG_7 */
10959 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0
) },
10960 { RM_TABLE (RM_0FAE_REG_7_MOD_3
) },
10964 { "lssS", { Gv
, Mp
}, 0 },
10968 { "lfsS", { Gv
, Mp
}, 0 },
10972 { "lgsS", { Gv
, Mp
}, 0 },
10976 { PREFIX_TABLE (PREFIX_0FC3_MOD_0
) },
10979 /* MOD_0FC7_REG_3 */
10980 { "xrstors", { FXSAVE
}, 0 },
10983 /* MOD_0FC7_REG_4 */
10984 { "xsavec", { FXSAVE
}, 0 },
10987 /* MOD_0FC7_REG_5 */
10988 { "xsaves", { FXSAVE
}, 0 },
10991 /* MOD_0FC7_REG_6 */
10992 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0
) },
10993 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3
) }
10996 /* MOD_0FC7_REG_7 */
10997 { "vmptrst", { Mq
}, 0 },
10998 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3
) }
11003 { "pmovmskb", { Gdq
, MS
}, 0 },
11006 /* MOD_0FE7_PREFIX_2 */
11007 { "movntdq", { Mx
, XM
}, 0 },
11010 /* MOD_0FF0_PREFIX_3 */
11011 { "lddqu", { XM
, M
}, 0 },
11014 /* MOD_0F382A_PREFIX_2 */
11015 { "movntdqa", { XM
, Mx
}, 0 },
11018 /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
11019 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0
) },
11020 { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1
) },
11023 /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
11024 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0
) },
11027 /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
11029 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0
) },
11032 /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
11033 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0
) },
11036 /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
11037 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0
) },
11040 /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
11041 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0
) },
11044 /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
11046 { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0
) },
11049 /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
11051 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0
) },
11054 /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
11056 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0
) },
11059 /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
11061 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0
) },
11064 /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
11066 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0
) },
11069 /* MOD_0F38F5_PREFIX_2 */
11070 { "wrussK", { M
, Gdq
}, PREFIX_OPCODE
},
11073 /* MOD_0F38F6_PREFIX_0 */
11074 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
11077 /* MOD_0F38F8_PREFIX_1 */
11078 { "enqcmds", { Gva
, M
}, PREFIX_OPCODE
},
11081 /* MOD_0F38F8_PREFIX_2 */
11082 { "movdir64b", { Gva
, M
}, PREFIX_OPCODE
},
11085 /* MOD_0F38F8_PREFIX_3 */
11086 { "enqcmd", { Gva
, M
}, PREFIX_OPCODE
},
11089 /* MOD_0F38F9_PREFIX_0 */
11090 { "movdiri", { Ev
, Gv
}, PREFIX_OPCODE
},
11094 { "bound{S|}", { Gv
, Ma
}, 0 },
11095 { EVEX_TABLE (EVEX_0F
) },
11099 { "lesS", { Gv
, Mp
}, 0 },
11100 { VEX_C4_TABLE (VEX_0F
) },
11104 { "ldsS", { Gv
, Mp
}, 0 },
11105 { VEX_C5_TABLE (VEX_0F
) },
11108 /* MOD_VEX_0F12_PREFIX_0 */
11109 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
11110 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
11113 /* MOD_VEX_0F12_PREFIX_2 */
11114 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0
) },
11118 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
11121 /* MOD_VEX_0F16_PREFIX_0 */
11122 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
11123 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
11126 /* MOD_VEX_0F16_PREFIX_2 */
11127 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0
) },
11131 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
11135 { "vmovntpX", { Mx
, XM
}, PREFIX_OPCODE
},
11138 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11140 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
11143 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11145 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
11148 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11150 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
11153 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11155 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
11158 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11160 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
11163 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11165 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
11168 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11170 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
11173 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11175 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
11178 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11180 { "knotw", { MaskG
, MaskR
}, 0 },
11183 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11185 { "knotq", { MaskG
, MaskR
}, 0 },
11188 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11190 { "knotb", { MaskG
, MaskR
}, 0 },
11193 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11195 { "knotd", { MaskG
, MaskR
}, 0 },
11198 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11200 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
11203 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11205 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
11208 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11210 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
11213 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11215 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
11218 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11220 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
11223 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11225 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
11228 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11230 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
11233 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11235 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
11238 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11240 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
11243 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11245 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
11248 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11250 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
11253 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11255 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
11258 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11260 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
11263 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11265 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
11268 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11270 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
11273 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11275 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
11278 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11280 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
11283 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11285 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
11288 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11290 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
11295 { "vmovmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
11298 /* MOD_VEX_0F71_REG_2 */
11300 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
11303 /* MOD_VEX_0F71_REG_4 */
11305 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
11308 /* MOD_VEX_0F71_REG_6 */
11310 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
11313 /* MOD_VEX_0F72_REG_2 */
11315 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
11318 /* MOD_VEX_0F72_REG_4 */
11320 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
11323 /* MOD_VEX_0F72_REG_6 */
11325 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
11328 /* MOD_VEX_0F73_REG_2 */
11330 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
11333 /* MOD_VEX_0F73_REG_3 */
11335 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
11338 /* MOD_VEX_0F73_REG_6 */
11340 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
11343 /* MOD_VEX_0F73_REG_7 */
11345 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
11348 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11349 { "kmovw", { Ew
, MaskG
}, 0 },
11353 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11354 { "kmovq", { Eq
, MaskG
}, 0 },
11358 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11359 { "kmovb", { Eb
, MaskG
}, 0 },
11363 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11364 { "kmovd", { Ed
, MaskG
}, 0 },
11368 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
11370 { "kmovw", { MaskG
, Rdq
}, 0 },
11373 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
11375 { "kmovb", { MaskG
, Rdq
}, 0 },
11378 /* MOD_VEX_0F92_P_3_LEN_0 */
11380 { "kmovK", { MaskG
, Rdq
}, 0 },
11383 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
11385 { "kmovw", { Gdq
, MaskR
}, 0 },
11388 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
11390 { "kmovb", { Gdq
, MaskR
}, 0 },
11393 /* MOD_VEX_0F93_P_3_LEN_0 */
11395 { "kmovK", { Gdq
, MaskR
}, 0 },
11398 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
11400 { "kortestw", { MaskG
, MaskR
}, 0 },
11403 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
11405 { "kortestq", { MaskG
, MaskR
}, 0 },
11408 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
11410 { "kortestb", { MaskG
, MaskR
}, 0 },
11413 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
11415 { "kortestd", { MaskG
, MaskR
}, 0 },
11418 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
11420 { "ktestw", { MaskG
, MaskR
}, 0 },
11423 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
11425 { "ktestq", { MaskG
, MaskR
}, 0 },
11428 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
11430 { "ktestb", { MaskG
, MaskR
}, 0 },
11433 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
11435 { "ktestd", { MaskG
, MaskR
}, 0 },
11438 /* MOD_VEX_0FAE_REG_2 */
11439 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
11442 /* MOD_VEX_0FAE_REG_3 */
11443 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
11446 /* MOD_VEX_0FD7_PREFIX_2 */
11448 { "vpmovmskb", { Gdq
, XS
}, 0 },
11451 /* MOD_VEX_0FE7_PREFIX_2 */
11452 { "vmovntdq", { Mx
, XM
}, 0 },
11455 /* MOD_VEX_0FF0_PREFIX_3 */
11456 { "vlddqu", { XM
, M
}, 0 },
11459 /* MOD_VEX_0F381A_PREFIX_2 */
11460 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
11463 /* MOD_VEX_0F382A_PREFIX_2 */
11464 { "vmovntdqa", { XM
, Mx
}, 0 },
11467 /* MOD_VEX_0F382C_PREFIX_2 */
11468 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
11471 /* MOD_VEX_0F382D_PREFIX_2 */
11472 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
11475 /* MOD_VEX_0F382E_PREFIX_2 */
11476 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
11479 /* MOD_VEX_0F382F_PREFIX_2 */
11480 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
11483 /* MOD_VEX_0F385A_PREFIX_2 */
11484 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
11487 /* MOD_VEX_0F388C_PREFIX_2 */
11488 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
11491 /* MOD_VEX_0F388E_PREFIX_2 */
11492 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
11495 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
11497 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
11500 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
11502 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
11505 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
11507 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
11510 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
11512 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
11515 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
11517 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
11520 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
11522 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
11525 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
11527 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
11530 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
11532 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
11535 /* MOD_VEX_0FXOP_09_12 */
11537 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1
) },
11540 #include "i386-dis-evex-mod.h"
11543 static const struct dis386 rm_table
[][8] = {
11546 { "xabort", { Skip_MODRM
, Ib
}, 0 },
11550 { "xbeginT", { Skip_MODRM
, Jdqw
}, 0 },
11553 /* RM_0F01_REG_0 */
11554 { "enclv", { Skip_MODRM
}, 0 },
11555 { "vmcall", { Skip_MODRM
}, 0 },
11556 { "vmlaunch", { Skip_MODRM
}, 0 },
11557 { "vmresume", { Skip_MODRM
}, 0 },
11558 { "vmxoff", { Skip_MODRM
}, 0 },
11559 { "pconfig", { Skip_MODRM
}, 0 },
11562 /* RM_0F01_REG_1 */
11563 { "monitor", { { OP_Monitor
, 0 } }, 0 },
11564 { "mwait", { { OP_Mwait
, 0 } }, 0 },
11565 { "clac", { Skip_MODRM
}, 0 },
11566 { "stac", { Skip_MODRM
}, 0 },
11570 { "encls", { Skip_MODRM
}, 0 },
11573 /* RM_0F01_REG_2 */
11574 { "xgetbv", { Skip_MODRM
}, 0 },
11575 { "xsetbv", { Skip_MODRM
}, 0 },
11578 { "vmfunc", { Skip_MODRM
}, 0 },
11579 { "xend", { Skip_MODRM
}, 0 },
11580 { "xtest", { Skip_MODRM
}, 0 },
11581 { "enclu", { Skip_MODRM
}, 0 },
11584 /* RM_0F01_REG_3 */
11585 { "vmrun", { Skip_MODRM
}, 0 },
11586 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1
) },
11587 { "vmload", { Skip_MODRM
}, 0 },
11588 { "vmsave", { Skip_MODRM
}, 0 },
11589 { "stgi", { Skip_MODRM
}, 0 },
11590 { "clgi", { Skip_MODRM
}, 0 },
11591 { "skinit", { Skip_MODRM
}, 0 },
11592 { "invlpga", { Skip_MODRM
}, 0 },
11595 /* RM_0F01_REG_5_MOD_3 */
11596 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0
) },
11597 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1
) },
11598 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2
) },
11602 { "rdpkru", { Skip_MODRM
}, 0 },
11603 { "wrpkru", { Skip_MODRM
}, 0 },
11606 /* RM_0F01_REG_7_MOD_3 */
11607 { "swapgs", { Skip_MODRM
}, 0 },
11608 { "rdtscp", { Skip_MODRM
}, 0 },
11609 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2
) },
11610 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3
) },
11611 { "clzero", { Skip_MODRM
}, 0 },
11612 { "rdpru", { Skip_MODRM
}, 0 },
11615 /* RM_0F1E_P_1_MOD_3_REG_7 */
11616 { "nopQ", { Ev
}, 0 },
11617 { "nopQ", { Ev
}, 0 },
11618 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
11619 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
11620 { "nopQ", { Ev
}, 0 },
11621 { "nopQ", { Ev
}, 0 },
11622 { "nopQ", { Ev
}, 0 },
11623 { "nopQ", { Ev
}, 0 },
11626 /* RM_0FAE_REG_6_MOD_3 */
11627 { "mfence", { Skip_MODRM
}, 0 },
11630 /* RM_0FAE_REG_7_MOD_3 */
11631 { "sfence", { Skip_MODRM
}, 0 },
11635 /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
11636 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0
) },
11640 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11642 /* We use the high bit to indicate different name for the same
11644 #define REP_PREFIX (0xf3 | 0x100)
11645 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11646 #define XRELEASE_PREFIX (0xf3 | 0x400)
11647 #define BND_PREFIX (0xf2 | 0x400)
11648 #define NOTRACK_PREFIX (0x3e | 0x100)
11650 /* Remember if the current op is a jump instruction. */
11651 static bfd_boolean op_is_jump
= FALSE
;
11656 int newrex
, i
, length
;
11661 last_lock_prefix
= -1;
11662 last_repz_prefix
= -1;
11663 last_repnz_prefix
= -1;
11664 last_data_prefix
= -1;
11665 last_addr_prefix
= -1;
11666 last_rex_prefix
= -1;
11667 last_seg_prefix
= -1;
11669 active_seg_prefix
= 0;
11670 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11671 all_prefixes
[i
] = 0;
11674 /* The maximum instruction length is 15bytes. */
11675 while (length
< MAX_CODE_LENGTH
- 1)
11677 FETCH_DATA (the_info
, codep
+ 1);
11681 /* REX prefixes family. */
11698 if (address_mode
== mode_64bit
)
11702 last_rex_prefix
= i
;
11705 prefixes
|= PREFIX_REPZ
;
11706 last_repz_prefix
= i
;
11709 prefixes
|= PREFIX_REPNZ
;
11710 last_repnz_prefix
= i
;
11713 prefixes
|= PREFIX_LOCK
;
11714 last_lock_prefix
= i
;
11717 prefixes
|= PREFIX_CS
;
11718 last_seg_prefix
= i
;
11719 active_seg_prefix
= PREFIX_CS
;
11722 prefixes
|= PREFIX_SS
;
11723 last_seg_prefix
= i
;
11724 active_seg_prefix
= PREFIX_SS
;
11727 prefixes
|= PREFIX_DS
;
11728 last_seg_prefix
= i
;
11729 active_seg_prefix
= PREFIX_DS
;
11732 prefixes
|= PREFIX_ES
;
11733 last_seg_prefix
= i
;
11734 active_seg_prefix
= PREFIX_ES
;
11737 prefixes
|= PREFIX_FS
;
11738 last_seg_prefix
= i
;
11739 active_seg_prefix
= PREFIX_FS
;
11742 prefixes
|= PREFIX_GS
;
11743 last_seg_prefix
= i
;
11744 active_seg_prefix
= PREFIX_GS
;
11747 prefixes
|= PREFIX_DATA
;
11748 last_data_prefix
= i
;
11751 prefixes
|= PREFIX_ADDR
;
11752 last_addr_prefix
= i
;
11755 /* fwait is really an instruction. If there are prefixes
11756 before the fwait, they belong to the fwait, *not* to the
11757 following instruction. */
11759 if (prefixes
|| rex
)
11761 prefixes
|= PREFIX_FWAIT
;
11763 /* This ensures that the previous REX prefixes are noticed
11764 as unused prefixes, as in the return case below. */
11768 prefixes
= PREFIX_FWAIT
;
11773 /* Rex is ignored when followed by another prefix. */
11779 if (*codep
!= FWAIT_OPCODE
)
11780 all_prefixes
[i
++] = *codep
;
11788 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11791 static const char *
11792 prefix_name (int pref
, int sizeflag
)
11794 static const char *rexes
[16] =
11797 "rex.B", /* 0x41 */
11798 "rex.X", /* 0x42 */
11799 "rex.XB", /* 0x43 */
11800 "rex.R", /* 0x44 */
11801 "rex.RB", /* 0x45 */
11802 "rex.RX", /* 0x46 */
11803 "rex.RXB", /* 0x47 */
11804 "rex.W", /* 0x48 */
11805 "rex.WB", /* 0x49 */
11806 "rex.WX", /* 0x4a */
11807 "rex.WXB", /* 0x4b */
11808 "rex.WR", /* 0x4c */
11809 "rex.WRB", /* 0x4d */
11810 "rex.WRX", /* 0x4e */
11811 "rex.WRXB", /* 0x4f */
11816 /* REX prefixes family. */
11833 return rexes
[pref
- 0x40];
11853 return (sizeflag
& DFLAG
) ? "data16" : "data32";
11855 if (address_mode
== mode_64bit
)
11856 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
11858 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
11863 case XACQUIRE_PREFIX
:
11865 case XRELEASE_PREFIX
:
11869 case NOTRACK_PREFIX
:
11876 static char op_out
[MAX_OPERANDS
][100];
11877 static int op_ad
, op_index
[MAX_OPERANDS
];
11878 static int two_source_ops
;
11879 static bfd_vma op_address
[MAX_OPERANDS
];
11880 static bfd_vma op_riprel
[MAX_OPERANDS
];
11881 static bfd_vma start_pc
;
11884 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11885 * (see topic "Redundant prefixes" in the "Differences from 8086"
11886 * section of the "Virtual 8086 Mode" chapter.)
11887 * 'pc' should be the address of this instruction, it will
11888 * be used to print the target address if this is a relative jump or call
11889 * The function returns the length of this instruction in bytes.
11892 static char intel_syntax
;
11893 static char intel_mnemonic
= !SYSV386_COMPAT
;
11894 static char open_char
;
11895 static char close_char
;
11896 static char separator_char
;
11897 static char scale_char
;
11905 static enum x86_64_isa isa64
;
11907 /* Here for backwards compatibility. When gdb stops using
11908 print_insn_i386_att and print_insn_i386_intel these functions can
11909 disappear, and print_insn_i386 be merged into print_insn. */
11911 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
11915 return print_insn (pc
, info
);
11919 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
11923 return print_insn (pc
, info
);
11927 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
11931 return print_insn (pc
, info
);
11935 print_i386_disassembler_options (FILE *stream
)
11937 fprintf (stream
, _("\n\
11938 The following i386/x86-64 specific disassembler options are supported for use\n\
11939 with the -M switch (multiple options should be separated by commas):\n"));
11941 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
11942 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
11943 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
11944 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
11945 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
11946 fprintf (stream
, _(" att-mnemonic\n"
11947 " Display instruction in AT&T mnemonic\n"));
11948 fprintf (stream
, _(" intel-mnemonic\n"
11949 " Display instruction in Intel mnemonic\n"));
11950 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
11951 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
11952 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
11953 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
11954 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
11955 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11956 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
11957 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
11961 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
11963 /* Get a pointer to struct dis386 with a valid name. */
11965 static const struct dis386
*
11966 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
11968 int vindex
, vex_table_index
;
11970 if (dp
->name
!= NULL
)
11973 switch (dp
->op
[0].bytemode
)
11975 case USE_REG_TABLE
:
11976 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
11979 case USE_MOD_TABLE
:
11980 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
11981 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
11985 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
11988 case USE_PREFIX_TABLE
:
11991 /* The prefix in VEX is implicit. */
11992 switch (vex
.prefix
)
11997 case REPE_PREFIX_OPCODE
:
12000 case DATA_PREFIX_OPCODE
:
12003 case REPNE_PREFIX_OPCODE
:
12013 int last_prefix
= -1;
12016 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12017 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12019 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
12021 if (last_repz_prefix
> last_repnz_prefix
)
12024 prefix
= PREFIX_REPZ
;
12025 last_prefix
= last_repz_prefix
;
12030 prefix
= PREFIX_REPNZ
;
12031 last_prefix
= last_repnz_prefix
;
12034 /* Check if prefix should be ignored. */
12035 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
12036 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
12041 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
12044 prefix
= PREFIX_DATA
;
12045 last_prefix
= last_data_prefix
;
12050 used_prefixes
|= prefix
;
12051 all_prefixes
[last_prefix
] = 0;
12054 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
12057 case USE_X86_64_TABLE
:
12058 vindex
= address_mode
== mode_64bit
? 1 : 0;
12059 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
12062 case USE_3BYTE_TABLE
:
12063 FETCH_DATA (info
, codep
+ 2);
12065 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
12067 modrm
.mod
= (*codep
>> 6) & 3;
12068 modrm
.reg
= (*codep
>> 3) & 7;
12069 modrm
.rm
= *codep
& 7;
12072 case USE_VEX_LEN_TABLE
:
12076 switch (vex
.length
)
12089 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
12092 case USE_EVEX_LEN_TABLE
:
12096 switch (vex
.length
)
12112 dp
= &evex_len_table
[dp
->op
[1].bytemode
][vindex
];
12115 case USE_XOP_8F_TABLE
:
12116 FETCH_DATA (info
, codep
+ 3);
12117 rex
= ~(*codep
>> 5) & 0x7;
12119 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12120 switch ((*codep
& 0x1f))
12126 vex_table_index
= XOP_08
;
12129 vex_table_index
= XOP_09
;
12132 vex_table_index
= XOP_0A
;
12136 vex
.w
= *codep
& 0x80;
12137 if (vex
.w
&& address_mode
== mode_64bit
)
12140 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12141 if (address_mode
!= mode_64bit
)
12143 /* In 16/32-bit mode REX_B is silently ignored. */
12147 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12148 switch ((*codep
& 0x3))
12153 vex
.prefix
= DATA_PREFIX_OPCODE
;
12156 vex
.prefix
= REPE_PREFIX_OPCODE
;
12159 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12166 dp
= &xop_table
[vex_table_index
][vindex
];
12169 FETCH_DATA (info
, codep
+ 1);
12170 modrm
.mod
= (*codep
>> 6) & 3;
12171 modrm
.reg
= (*codep
>> 3) & 7;
12172 modrm
.rm
= *codep
& 7;
12174 /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
12175 having to decode the bits for every otherwise valid encoding. */
12177 return &bad_opcode
;
12180 case USE_VEX_C4_TABLE
:
12182 FETCH_DATA (info
, codep
+ 3);
12183 rex
= ~(*codep
>> 5) & 0x7;
12184 switch ((*codep
& 0x1f))
12190 vex_table_index
= VEX_0F
;
12193 vex_table_index
= VEX_0F38
;
12196 vex_table_index
= VEX_0F3A
;
12200 vex
.w
= *codep
& 0x80;
12201 if (address_mode
== mode_64bit
)
12208 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12209 is ignored, other REX bits are 0 and the highest bit in
12210 VEX.vvvv is also ignored (but we mustn't clear it here). */
12213 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12214 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12215 switch ((*codep
& 0x3))
12220 vex
.prefix
= DATA_PREFIX_OPCODE
;
12223 vex
.prefix
= REPE_PREFIX_OPCODE
;
12226 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12233 dp
= &vex_table
[vex_table_index
][vindex
];
12235 /* There is no MODRM byte for VEX0F 77. */
12236 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
12238 FETCH_DATA (info
, codep
+ 1);
12239 modrm
.mod
= (*codep
>> 6) & 3;
12240 modrm
.reg
= (*codep
>> 3) & 7;
12241 modrm
.rm
= *codep
& 7;
12245 case USE_VEX_C5_TABLE
:
12247 FETCH_DATA (info
, codep
+ 2);
12248 rex
= (*codep
& 0x80) ? 0 : REX_R
;
12250 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12252 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12253 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12254 switch ((*codep
& 0x3))
12259 vex
.prefix
= DATA_PREFIX_OPCODE
;
12262 vex
.prefix
= REPE_PREFIX_OPCODE
;
12265 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12272 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
12274 /* There is no MODRM byte for VEX 77. */
12275 if (vindex
!= 0x77)
12277 FETCH_DATA (info
, codep
+ 1);
12278 modrm
.mod
= (*codep
>> 6) & 3;
12279 modrm
.reg
= (*codep
>> 3) & 7;
12280 modrm
.rm
= *codep
& 7;
12284 case USE_VEX_W_TABLE
:
12288 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
12291 case USE_EVEX_TABLE
:
12292 two_source_ops
= 0;
12295 FETCH_DATA (info
, codep
+ 4);
12296 /* The first byte after 0x62. */
12297 rex
= ~(*codep
>> 5) & 0x7;
12298 vex
.r
= *codep
& 0x10;
12299 switch ((*codep
& 0xf))
12302 return &bad_opcode
;
12304 vex_table_index
= EVEX_0F
;
12307 vex_table_index
= EVEX_0F38
;
12310 vex_table_index
= EVEX_0F3A
;
12314 /* The second byte after 0x62. */
12316 vex
.w
= *codep
& 0x80;
12317 if (vex
.w
&& address_mode
== mode_64bit
)
12320 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12323 if (!(*codep
& 0x4))
12324 return &bad_opcode
;
12326 switch ((*codep
& 0x3))
12331 vex
.prefix
= DATA_PREFIX_OPCODE
;
12334 vex
.prefix
= REPE_PREFIX_OPCODE
;
12337 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12341 /* The third byte after 0x62. */
12344 /* Remember the static rounding bits. */
12345 vex
.ll
= (*codep
>> 5) & 3;
12346 vex
.b
= (*codep
& 0x10) != 0;
12348 vex
.v
= *codep
& 0x8;
12349 vex
.mask_register_specifier
= *codep
& 0x7;
12350 vex
.zeroing
= *codep
& 0x80;
12352 if (address_mode
!= mode_64bit
)
12354 /* In 16/32-bit mode silently ignore following bits. */
12364 dp
= &evex_table
[vex_table_index
][vindex
];
12366 FETCH_DATA (info
, codep
+ 1);
12367 modrm
.mod
= (*codep
>> 6) & 3;
12368 modrm
.reg
= (*codep
>> 3) & 7;
12369 modrm
.rm
= *codep
& 7;
12371 /* Set vector length. */
12372 if (modrm
.mod
== 3 && vex
.b
)
12388 return &bad_opcode
;
12401 if (dp
->name
!= NULL
)
12404 return get_valid_dis386 (dp
, info
);
12408 get_sib (disassemble_info
*info
, int sizeflag
)
12410 /* If modrm.mod == 3, operand must be register. */
12412 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
12416 FETCH_DATA (info
, codep
+ 2);
12417 sib
.index
= (codep
[1] >> 3) & 7;
12418 sib
.scale
= (codep
[1] >> 6) & 3;
12419 sib
.base
= codep
[1] & 7;
12424 print_insn (bfd_vma pc
, disassemble_info
*info
)
12426 const struct dis386
*dp
;
12428 char *op_txt
[MAX_OPERANDS
];
12430 int sizeflag
, orig_sizeflag
;
12432 struct dis_private priv
;
12435 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
12436 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
12437 address_mode
= mode_32bit
;
12438 else if (info
->mach
== bfd_mach_i386_i8086
)
12440 address_mode
= mode_16bit
;
12441 priv
.orig_sizeflag
= 0;
12444 address_mode
= mode_64bit
;
12446 if (intel_syntax
== (char) -1)
12447 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
12449 for (p
= info
->disassembler_options
; p
!= NULL
; )
12451 if (CONST_STRNEQ (p
, "amd64"))
12453 else if (CONST_STRNEQ (p
, "intel64"))
12455 else if (CONST_STRNEQ (p
, "x86-64"))
12457 address_mode
= mode_64bit
;
12458 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
12460 else if (CONST_STRNEQ (p
, "i386"))
12462 address_mode
= mode_32bit
;
12463 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
12465 else if (CONST_STRNEQ (p
, "i8086"))
12467 address_mode
= mode_16bit
;
12468 priv
.orig_sizeflag
&= ~(AFLAG
| DFLAG
);
12470 else if (CONST_STRNEQ (p
, "intel"))
12473 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
12474 intel_mnemonic
= 1;
12476 else if (CONST_STRNEQ (p
, "att"))
12479 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
12480 intel_mnemonic
= 0;
12482 else if (CONST_STRNEQ (p
, "addr"))
12484 if (address_mode
== mode_64bit
)
12486 if (p
[4] == '3' && p
[5] == '2')
12487 priv
.orig_sizeflag
&= ~AFLAG
;
12488 else if (p
[4] == '6' && p
[5] == '4')
12489 priv
.orig_sizeflag
|= AFLAG
;
12493 if (p
[4] == '1' && p
[5] == '6')
12494 priv
.orig_sizeflag
&= ~AFLAG
;
12495 else if (p
[4] == '3' && p
[5] == '2')
12496 priv
.orig_sizeflag
|= AFLAG
;
12499 else if (CONST_STRNEQ (p
, "data"))
12501 if (p
[4] == '1' && p
[5] == '6')
12502 priv
.orig_sizeflag
&= ~DFLAG
;
12503 else if (p
[4] == '3' && p
[5] == '2')
12504 priv
.orig_sizeflag
|= DFLAG
;
12506 else if (CONST_STRNEQ (p
, "suffix"))
12507 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
12509 p
= strchr (p
, ',');
12514 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
12516 (*info
->fprintf_func
) (info
->stream
,
12517 _("64-bit address is disabled"));
12523 names64
= intel_names64
;
12524 names32
= intel_names32
;
12525 names16
= intel_names16
;
12526 names8
= intel_names8
;
12527 names8rex
= intel_names8rex
;
12528 names_seg
= intel_names_seg
;
12529 names_mm
= intel_names_mm
;
12530 names_bnd
= intel_names_bnd
;
12531 names_xmm
= intel_names_xmm
;
12532 names_ymm
= intel_names_ymm
;
12533 names_zmm
= intel_names_zmm
;
12534 names_tmm
= intel_names_tmm
;
12535 index64
= intel_index64
;
12536 index32
= intel_index32
;
12537 names_mask
= intel_names_mask
;
12538 index16
= intel_index16
;
12541 separator_char
= '+';
12546 names64
= att_names64
;
12547 names32
= att_names32
;
12548 names16
= att_names16
;
12549 names8
= att_names8
;
12550 names8rex
= att_names8rex
;
12551 names_seg
= att_names_seg
;
12552 names_mm
= att_names_mm
;
12553 names_bnd
= att_names_bnd
;
12554 names_xmm
= att_names_xmm
;
12555 names_ymm
= att_names_ymm
;
12556 names_zmm
= att_names_zmm
;
12557 names_tmm
= att_names_tmm
;
12558 index64
= att_index64
;
12559 index32
= att_index32
;
12560 names_mask
= att_names_mask
;
12561 index16
= att_index16
;
12564 separator_char
= ',';
12568 /* The output looks better if we put 7 bytes on a line, since that
12569 puts most long word instructions on a single line. Use 8 bytes
12571 if ((info
->mach
& bfd_mach_l1om
) != 0)
12572 info
->bytes_per_line
= 8;
12574 info
->bytes_per_line
= 7;
12576 info
->private_data
= &priv
;
12577 priv
.max_fetched
= priv
.the_buffer
;
12578 priv
.insn_start
= pc
;
12581 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12589 start_codep
= priv
.the_buffer
;
12590 codep
= priv
.the_buffer
;
12592 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
12596 /* Getting here means we tried for data but didn't get it. That
12597 means we have an incomplete instruction of some sort. Just
12598 print the first byte as a prefix or a .byte pseudo-op. */
12599 if (codep
> priv
.the_buffer
)
12601 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
12603 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
12606 /* Just print the first byte as a .byte instruction. */
12607 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
12608 (unsigned int) priv
.the_buffer
[0]);
12618 sizeflag
= priv
.orig_sizeflag
;
12620 if (!ckprefix () || rex_used
)
12622 /* Too many prefixes or unused REX prefixes. */
12624 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
12626 (*info
->fprintf_func
) (info
->stream
, "%s%s",
12628 prefix_name (all_prefixes
[i
], sizeflag
));
12632 insn_codep
= codep
;
12634 FETCH_DATA (info
, codep
+ 1);
12635 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
12637 if (((prefixes
& PREFIX_FWAIT
)
12638 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
12640 /* Handle prefixes before fwait. */
12641 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
12643 (*info
->fprintf_func
) (info
->stream
, "%s ",
12644 prefix_name (all_prefixes
[i
], sizeflag
));
12645 (*info
->fprintf_func
) (info
->stream
, "fwait");
12649 if (*codep
== 0x0f)
12651 unsigned char threebyte
;
12654 FETCH_DATA (info
, codep
+ 1);
12655 threebyte
= *codep
;
12656 dp
= &dis386_twobyte
[threebyte
];
12657 need_modrm
= twobyte_has_modrm
[*codep
];
12662 dp
= &dis386
[*codep
];
12663 need_modrm
= onebyte_has_modrm
[*codep
];
12667 /* Save sizeflag for printing the extra prefixes later before updating
12668 it for mnemonic and operand processing. The prefix names depend
12669 only on the address mode. */
12670 orig_sizeflag
= sizeflag
;
12671 if (prefixes
& PREFIX_ADDR
)
12673 if ((prefixes
& PREFIX_DATA
))
12679 FETCH_DATA (info
, codep
+ 1);
12680 modrm
.mod
= (*codep
>> 6) & 3;
12681 modrm
.reg
= (*codep
>> 3) & 7;
12682 modrm
.rm
= *codep
& 7;
12687 memset (&vex
, 0, sizeof (vex
));
12689 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
12691 get_sib (info
, sizeflag
);
12692 dofloat (sizeflag
);
12696 dp
= get_valid_dis386 (dp
, info
);
12697 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
12699 get_sib (info
, sizeflag
);
12700 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12703 op_ad
= MAX_OPERANDS
- 1 - i
;
12705 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
12706 /* For EVEX instruction after the last operand masking
12707 should be printed. */
12708 if (i
== 0 && vex
.evex
)
12710 /* Don't print {%k0}. */
12711 if (vex
.mask_register_specifier
)
12714 oappend (names_mask
[vex
.mask_register_specifier
]);
12724 /* Clear instruction information. */
12727 the_info
->insn_info_valid
= 0;
12728 the_info
->branch_delay_insns
= 0;
12729 the_info
->data_size
= 0;
12730 the_info
->insn_type
= dis_noninsn
;
12731 the_info
->target
= 0;
12732 the_info
->target2
= 0;
12735 /* Reset jump operation indicator. */
12736 op_is_jump
= FALSE
;
12739 int jump_detection
= 0;
12741 /* Extract flags. */
12742 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12744 if ((dp
->op
[i
].rtn
== OP_J
)
12745 || (dp
->op
[i
].rtn
== OP_indirE
))
12746 jump_detection
|= 1;
12747 else if ((dp
->op
[i
].rtn
== BND_Fixup
)
12748 || (!dp
->op
[i
].rtn
&& !dp
->op
[i
].bytemode
))
12749 jump_detection
|= 2;
12750 else if ((dp
->op
[i
].bytemode
== cond_jump_mode
)
12751 || (dp
->op
[i
].bytemode
== loop_jcxz_mode
))
12752 jump_detection
|= 4;
12755 /* Determine if this is a jump or branch. */
12756 if ((jump_detection
& 0x3) == 0x3)
12759 if (jump_detection
& 0x4)
12760 the_info
->insn_type
= dis_condbranch
;
12762 the_info
->insn_type
=
12763 (dp
->name
&& !strncmp(dp
->name
, "call", 4))
12764 ? dis_jsr
: dis_branch
;
12768 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12769 are all 0s in inverted form. */
12770 if (need_vex
&& vex
.register_specifier
!= 0)
12772 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12773 return end_codep
- priv
.the_buffer
;
12776 /* Check if the REX prefix is used. */
12777 if ((rex
^ rex_used
) == 0 && !need_vex
&& last_rex_prefix
>= 0)
12778 all_prefixes
[last_rex_prefix
] = 0;
12780 /* Check if the SEG prefix is used. */
12781 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
12782 | PREFIX_FS
| PREFIX_GS
)) != 0
12783 && (used_prefixes
& active_seg_prefix
) != 0)
12784 all_prefixes
[last_seg_prefix
] = 0;
12786 /* Check if the ADDR prefix is used. */
12787 if ((prefixes
& PREFIX_ADDR
) != 0
12788 && (used_prefixes
& PREFIX_ADDR
) != 0)
12789 all_prefixes
[last_addr_prefix
] = 0;
12791 /* Check if the DATA prefix is used. */
12792 if ((prefixes
& PREFIX_DATA
) != 0
12793 && (used_prefixes
& PREFIX_DATA
) != 0
12795 all_prefixes
[last_data_prefix
] = 0;
12797 /* Print the extra prefixes. */
12799 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12800 if (all_prefixes
[i
])
12803 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
12806 prefix_length
+= strlen (name
) + 1;
12807 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
12810 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12811 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
12812 used by putop and MMX/SSE operand and may be overriden by the
12813 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12815 if (dp
->prefix_requirement
== PREFIX_OPCODE
12817 ? vex
.prefix
== REPE_PREFIX_OPCODE
12818 || vex
.prefix
== REPNE_PREFIX_OPCODE
12820 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
12822 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
12824 ? vex
.prefix
== DATA_PREFIX_OPCODE
12826 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
12828 && (used_prefixes
& PREFIX_DATA
) == 0))
12829 || (vex
.evex
&& !vex
.w
!= !(used_prefixes
& PREFIX_DATA
))))
12831 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12832 return end_codep
- priv
.the_buffer
;
12835 /* Check maximum code length. */
12836 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
12838 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12839 return MAX_CODE_LENGTH
;
12842 obufp
= mnemonicendp
;
12843 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
12846 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
12848 /* The enter and bound instructions are printed with operands in the same
12849 order as the intel book; everything else is printed in reverse order. */
12850 if (intel_syntax
|| two_source_ops
)
12854 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12855 op_txt
[i
] = op_out
[i
];
12857 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
12858 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
12860 op_txt
[2] = op_out
[3];
12861 op_txt
[3] = op_out
[2];
12864 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
12866 op_ad
= op_index
[i
];
12867 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
12868 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
12869 riprel
= op_riprel
[i
];
12870 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
12871 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
12876 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12877 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
12881 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12885 (*info
->fprintf_func
) (info
->stream
, ",");
12886 if (op_index
[i
] != -1 && !op_riprel
[i
])
12888 bfd_vma target
= (bfd_vma
) op_address
[op_index
[i
]];
12890 if (the_info
&& op_is_jump
)
12892 the_info
->insn_info_valid
= 1;
12893 the_info
->branch_delay_insns
= 0;
12894 the_info
->data_size
= 0;
12895 the_info
->target
= target
;
12896 the_info
->target2
= 0;
12898 (*info
->print_address_func
) (target
, info
);
12901 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
12905 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12906 if (op_index
[i
] != -1 && op_riprel
[i
])
12908 (*info
->fprintf_func
) (info
->stream
, " # ");
12909 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
12910 + op_address
[op_index
[i
]]), info
);
12913 return codep
- priv
.the_buffer
;
12916 static const char *float_mem
[] = {
12991 static const unsigned char float_mem_mode
[] = {
13066 #define ST { OP_ST, 0 }
13067 #define STi { OP_STi, 0 }
13069 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13070 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13071 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13072 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13073 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13074 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13075 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13076 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13077 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13079 static const struct dis386 float_reg
[][8] = {
13082 { "fadd", { ST
, STi
}, 0 },
13083 { "fmul", { ST
, STi
}, 0 },
13084 { "fcom", { STi
}, 0 },
13085 { "fcomp", { STi
}, 0 },
13086 { "fsub", { ST
, STi
}, 0 },
13087 { "fsubr", { ST
, STi
}, 0 },
13088 { "fdiv", { ST
, STi
}, 0 },
13089 { "fdivr", { ST
, STi
}, 0 },
13093 { "fld", { STi
}, 0 },
13094 { "fxch", { STi
}, 0 },
13104 { "fcmovb", { ST
, STi
}, 0 },
13105 { "fcmove", { ST
, STi
}, 0 },
13106 { "fcmovbe",{ ST
, STi
}, 0 },
13107 { "fcmovu", { ST
, STi
}, 0 },
13115 { "fcmovnb",{ ST
, STi
}, 0 },
13116 { "fcmovne",{ ST
, STi
}, 0 },
13117 { "fcmovnbe",{ ST
, STi
}, 0 },
13118 { "fcmovnu",{ ST
, STi
}, 0 },
13120 { "fucomi", { ST
, STi
}, 0 },
13121 { "fcomi", { ST
, STi
}, 0 },
13126 { "fadd", { STi
, ST
}, 0 },
13127 { "fmul", { STi
, ST
}, 0 },
13130 { "fsub{!M|r}", { STi
, ST
}, 0 },
13131 { "fsub{M|}", { STi
, ST
}, 0 },
13132 { "fdiv{!M|r}", { STi
, ST
}, 0 },
13133 { "fdiv{M|}", { STi
, ST
}, 0 },
13137 { "ffree", { STi
}, 0 },
13139 { "fst", { STi
}, 0 },
13140 { "fstp", { STi
}, 0 },
13141 { "fucom", { STi
}, 0 },
13142 { "fucomp", { STi
}, 0 },
13148 { "faddp", { STi
, ST
}, 0 },
13149 { "fmulp", { STi
, ST
}, 0 },
13152 { "fsub{!M|r}p", { STi
, ST
}, 0 },
13153 { "fsub{M|}p", { STi
, ST
}, 0 },
13154 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
13155 { "fdiv{M|}p", { STi
, ST
}, 0 },
13159 { "ffreep", { STi
}, 0 },
13164 { "fucomip", { ST
, STi
}, 0 },
13165 { "fcomip", { ST
, STi
}, 0 },
13170 static char *fgrps
[][8] = {
13173 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13178 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13183 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13188 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13193 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13198 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13203 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13208 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13209 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13214 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13219 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13224 swap_operand (void)
13226 mnemonicendp
[0] = '.';
13227 mnemonicendp
[1] = 's';
13232 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
13233 int sizeflag ATTRIBUTE_UNUSED
)
13235 /* Skip mod/rm byte. */
13241 dofloat (int sizeflag
)
13243 const struct dis386
*dp
;
13244 unsigned char floatop
;
13246 floatop
= codep
[-1];
13248 if (modrm
.mod
!= 3)
13250 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
13252 putop (float_mem
[fp_indx
], sizeflag
);
13255 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
13258 /* Skip mod/rm byte. */
13262 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
13263 if (dp
->name
== NULL
)
13265 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
13267 /* Instruction fnstsw is only one with strange arg. */
13268 if (floatop
== 0xdf && codep
[-1] == 0xe0)
13269 strcpy (op_out
[0], names16
[0]);
13273 putop (dp
->name
, sizeflag
);
13278 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
13283 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
13287 /* Like oappend (below), but S is a string starting with '%'.
13288 In Intel syntax, the '%' is elided. */
13290 oappend_maybe_intel (const char *s
)
13292 oappend (s
+ intel_syntax
);
13296 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13298 oappend_maybe_intel ("%st");
13302 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13304 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
13305 oappend_maybe_intel (scratchbuf
);
13308 /* Capital letters in template are macros. */
13310 putop (const char *in_template
, int sizeflag
)
13315 unsigned int l
= 0, len
= 0;
13318 for (p
= in_template
; *p
; p
++)
13322 if (l
>= sizeof (last
) || !ISUPPER (*p
))
13341 while (*++p
!= '|')
13342 if (*p
== '}' || *p
== '\0')
13348 while (*++p
!= '}')
13360 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13369 if (sizeflag
& SUFFIX_ALWAYS
)
13372 else if (l
== 1 && last
[0] == 'L')
13374 if (address_mode
== mode_64bit
13375 && !(prefixes
& PREFIX_ADDR
))
13388 if (intel_syntax
&& !alt
)
13390 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13392 if (sizeflag
& DFLAG
)
13393 *obufp
++ = intel_syntax
? 'd' : 'l';
13395 *obufp
++ = intel_syntax
? 'w' : 's';
13396 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13400 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
13403 if (modrm
.mod
== 3)
13409 if (sizeflag
& DFLAG
)
13410 *obufp
++ = intel_syntax
? 'd' : 'l';
13413 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13419 case 'E': /* For jcxz/jecxz */
13420 if (address_mode
== mode_64bit
)
13422 if (sizeflag
& AFLAG
)
13428 if (sizeflag
& AFLAG
)
13430 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
13435 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
13437 if (sizeflag
& AFLAG
)
13438 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
13440 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
13441 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
13445 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
13447 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13451 if (!(rex
& REX_W
))
13452 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13457 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
13458 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
13460 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
13463 if (prefixes
& PREFIX_DS
)
13479 if (l
!= 1 || last
[0] != 'X')
13481 if (!need_vex
|| !vex
.evex
)
13484 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
13486 switch (vex
.length
)
13504 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
13509 /* Fall through. */
13517 if (sizeflag
& SUFFIX_ALWAYS
)
13521 if (intel_mnemonic
!= cond
)
13525 if ((prefixes
& PREFIX_FWAIT
) == 0)
13528 used_prefixes
|= PREFIX_FWAIT
;
13534 else if (intel_syntax
&& (sizeflag
& DFLAG
))
13538 if (!(rex
& REX_W
))
13539 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13543 && address_mode
== mode_64bit
13544 && isa64
== intel64
)
13549 /* Fall through. */
13552 && address_mode
== mode_64bit
13553 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13558 /* Fall through. */
13566 if ((rex
& REX_W
) == 0
13567 && (prefixes
& PREFIX_DATA
))
13569 if ((sizeflag
& DFLAG
) == 0)
13571 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13575 if ((prefixes
& PREFIX_DATA
)
13577 || (sizeflag
& SUFFIX_ALWAYS
))
13584 if (sizeflag
& DFLAG
)
13588 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13592 else if (l
== 1 && last
[0] == 'L')
13594 if ((prefixes
& PREFIX_DATA
)
13596 || (sizeflag
& SUFFIX_ALWAYS
))
13603 if (sizeflag
& DFLAG
)
13604 *obufp
++ = intel_syntax
? 'd' : 'l';
13607 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13617 if (address_mode
== mode_64bit
13618 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13620 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13624 /* Fall through. */
13630 if (intel_syntax
&& !alt
)
13633 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13639 if (sizeflag
& DFLAG
)
13640 *obufp
++ = intel_syntax
? 'd' : 'l';
13643 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13647 else if (l
== 1 && last
[0] == 'L')
13649 if ((intel_syntax
&& need_modrm
)
13650 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
13657 else if((address_mode
== mode_64bit
&& need_modrm
)
13658 || (sizeflag
& SUFFIX_ALWAYS
))
13659 *obufp
++ = intel_syntax
? 'd' : 'l';
13668 else if (sizeflag
& DFLAG
)
13677 if (intel_syntax
&& !p
[1]
13678 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
13680 if (!(rex
& REX_W
))
13681 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13688 if (address_mode
== mode_64bit
13689 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13691 if (sizeflag
& SUFFIX_ALWAYS
)
13696 else if (l
== 1 && last
[0] == 'L')
13707 /* Fall through. */
13715 if (sizeflag
& SUFFIX_ALWAYS
)
13721 if (sizeflag
& DFLAG
)
13725 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13729 else if (l
== 1 && last
[0] == 'L')
13731 if (address_mode
== mode_64bit
13732 && !(prefixes
& PREFIX_ADDR
))
13748 ? vex
.prefix
== DATA_PREFIX_OPCODE
13749 : prefixes
& PREFIX_DATA
)
13752 used_prefixes
|= PREFIX_DATA
;
13758 if (l
== 1 && last
[0] == 'X')
13763 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
13765 switch (vex
.length
)
13785 /* operand size flag for cwtl, cbtw */
13794 else if (sizeflag
& DFLAG
)
13798 if (!(rex
& REX_W
))
13799 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13805 if (last
[0] == 'X')
13806 *obufp
++ = vex
.w
? 'd': 's';
13807 else if (last
[0] == 'L')
13808 *obufp
++ = vex
.w
? 'q': 'd';
13809 else if (last
[0] == 'B')
13810 *obufp
++ = vex
.w
? 'w': 'b';
13820 if (isa64
== intel64
&& (rex
& REX_W
))
13826 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13828 if (sizeflag
& DFLAG
)
13832 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13838 if (address_mode
== mode_64bit
13839 && (isa64
== intel64
13840 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
13842 else if ((prefixes
& PREFIX_DATA
))
13844 if (!(sizeflag
& DFLAG
))
13846 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13855 mnemonicendp
= obufp
;
13860 oappend (const char *s
)
13862 obufp
= stpcpy (obufp
, s
);
13868 /* Only print the active segment register. */
13869 if (!active_seg_prefix
)
13872 used_prefixes
|= active_seg_prefix
;
13873 switch (active_seg_prefix
)
13876 oappend_maybe_intel ("%cs:");
13879 oappend_maybe_intel ("%ds:");
13882 oappend_maybe_intel ("%ss:");
13885 oappend_maybe_intel ("%es:");
13888 oappend_maybe_intel ("%fs:");
13891 oappend_maybe_intel ("%gs:");
13899 OP_indirE (int bytemode
, int sizeflag
)
13903 OP_E (bytemode
, sizeflag
);
13907 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
13909 if (address_mode
== mode_64bit
)
13917 sprintf_vma (tmp
, disp
);
13918 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
13919 strcpy (buf
+ 2, tmp
+ i
);
13923 bfd_signed_vma v
= disp
;
13930 /* Check for possible overflow on 0x8000000000000000. */
13933 strcpy (buf
, "9223372036854775808");
13947 tmp
[28 - i
] = (v
% 10) + '0';
13951 strcpy (buf
, tmp
+ 29 - i
);
13957 sprintf (buf
, "0x%x", (unsigned int) disp
);
13959 sprintf (buf
, "%d", (int) disp
);
13963 /* Put DISP in BUF as signed hex number. */
13966 print_displacement (char *buf
, bfd_vma disp
)
13968 bfd_signed_vma val
= disp
;
13977 /* Check for possible overflow. */
13980 switch (address_mode
)
13983 strcpy (buf
+ j
, "0x8000000000000000");
13986 strcpy (buf
+ j
, "0x80000000");
13989 strcpy (buf
+ j
, "0x8000");
13999 sprintf_vma (tmp
, (bfd_vma
) val
);
14000 for (i
= 0; tmp
[i
] == '0'; i
++)
14002 if (tmp
[i
] == '\0')
14004 strcpy (buf
+ j
, tmp
+ i
);
14008 intel_operand_size (int bytemode
, int sizeflag
)
14012 && (bytemode
== x_mode
14013 || bytemode
== evex_half_bcst_xmmq_mode
))
14016 oappend ("QWORD PTR ");
14018 oappend ("DWORD PTR ");
14027 oappend ("BYTE PTR ");
14032 oappend ("WORD PTR ");
14035 if (address_mode
== mode_64bit
&& isa64
== intel64
)
14037 oappend ("QWORD PTR ");
14040 /* Fall through. */
14042 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14044 oappend ("QWORD PTR ");
14047 /* Fall through. */
14053 oappend ("QWORD PTR ");
14056 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
14057 oappend ("DWORD PTR ");
14059 oappend ("WORD PTR ");
14060 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14064 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14066 oappend ("WORD PTR ");
14067 if (!(rex
& REX_W
))
14068 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14071 if (sizeflag
& DFLAG
)
14072 oappend ("QWORD PTR ");
14074 oappend ("DWORD PTR ");
14075 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14078 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
14079 oappend ("WORD PTR ");
14081 oappend ("DWORD PTR ");
14082 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14085 case d_scalar_swap_mode
:
14088 oappend ("DWORD PTR ");
14091 case q_scalar_swap_mode
:
14093 oappend ("QWORD PTR ");
14096 if (address_mode
== mode_64bit
)
14097 oappend ("QWORD PTR ");
14099 oappend ("DWORD PTR ");
14102 if (sizeflag
& DFLAG
)
14103 oappend ("FWORD PTR ");
14105 oappend ("DWORD PTR ");
14106 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14109 oappend ("TBYTE PTR ");
14113 case evex_x_gscat_mode
:
14114 case evex_x_nobcst_mode
:
14115 case b_scalar_mode
:
14116 case w_scalar_mode
:
14119 switch (vex
.length
)
14122 oappend ("XMMWORD PTR ");
14125 oappend ("YMMWORD PTR ");
14128 oappend ("ZMMWORD PTR ");
14135 oappend ("XMMWORD PTR ");
14138 oappend ("XMMWORD PTR ");
14141 oappend ("YMMWORD PTR ");
14144 case evex_half_bcst_xmmq_mode
:
14148 switch (vex
.length
)
14151 oappend ("QWORD PTR ");
14154 oappend ("XMMWORD PTR ");
14157 oappend ("YMMWORD PTR ");
14167 switch (vex
.length
)
14172 oappend ("BYTE PTR ");
14182 switch (vex
.length
)
14187 oappend ("WORD PTR ");
14197 switch (vex
.length
)
14202 oappend ("DWORD PTR ");
14212 switch (vex
.length
)
14217 oappend ("QWORD PTR ");
14227 switch (vex
.length
)
14230 oappend ("WORD PTR ");
14233 oappend ("DWORD PTR ");
14236 oappend ("QWORD PTR ");
14246 switch (vex
.length
)
14249 oappend ("DWORD PTR ");
14252 oappend ("QWORD PTR ");
14255 oappend ("XMMWORD PTR ");
14265 switch (vex
.length
)
14268 oappend ("QWORD PTR ");
14271 oappend ("YMMWORD PTR ");
14274 oappend ("ZMMWORD PTR ");
14284 switch (vex
.length
)
14288 oappend ("XMMWORD PTR ");
14295 oappend ("OWORD PTR ");
14297 case vex_scalar_w_dq_mode
:
14302 oappend ("QWORD PTR ");
14304 oappend ("DWORD PTR ");
14306 case vex_vsib_d_w_dq_mode
:
14307 case vex_vsib_q_w_dq_mode
:
14314 oappend ("QWORD PTR ");
14316 oappend ("DWORD PTR ");
14320 switch (vex
.length
)
14323 oappend ("XMMWORD PTR ");
14326 oappend ("YMMWORD PTR ");
14329 oappend ("ZMMWORD PTR ");
14336 case vex_vsib_q_w_d_mode
:
14337 case vex_vsib_d_w_d_mode
:
14338 if (!need_vex
|| !vex
.evex
)
14341 switch (vex
.length
)
14344 oappend ("QWORD PTR ");
14347 oappend ("XMMWORD PTR ");
14350 oappend ("YMMWORD PTR ");
14358 if (!need_vex
|| vex
.length
!= 128)
14361 oappend ("DWORD PTR ");
14363 oappend ("BYTE PTR ");
14369 oappend ("QWORD PTR ");
14371 oappend ("WORD PTR ");
14381 OP_E_register (int bytemode
, int sizeflag
)
14383 int reg
= modrm
.rm
;
14384 const char **names
;
14390 if ((sizeflag
& SUFFIX_ALWAYS
)
14391 && (bytemode
== b_swap_mode
14392 || bytemode
== bnd_swap_mode
14393 || bytemode
== v_swap_mode
))
14420 names
= address_mode
== mode_64bit
? names64
: names32
;
14423 case bnd_swap_mode
:
14432 if (address_mode
== mode_64bit
&& isa64
== intel64
)
14437 /* Fall through. */
14439 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14445 /* Fall through. */
14457 if ((sizeflag
& DFLAG
)
14458 || (bytemode
!= v_mode
14459 && bytemode
!= v_swap_mode
))
14463 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14467 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
14471 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14474 names
= (address_mode
== mode_64bit
14475 ? names64
: names32
);
14476 if (!(prefixes
& PREFIX_ADDR
))
14477 names
= (address_mode
== mode_16bit
14478 ? names16
: names
);
14481 /* Remove "addr16/addr32". */
14482 all_prefixes
[last_addr_prefix
] = 0;
14483 names
= (address_mode
!= mode_32bit
14484 ? names32
: names16
);
14485 used_prefixes
|= PREFIX_ADDR
;
14495 names
= names_mask
;
14500 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14503 oappend (names
[reg
]);
14507 OP_E_memory (int bytemode
, int sizeflag
)
14510 int add
= (rex
& REX_B
) ? 8 : 0;
14516 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
14518 && bytemode
!= x_mode
14519 && bytemode
!= xmmq_mode
14520 && bytemode
!= evex_half_bcst_xmmq_mode
)
14536 if (address_mode
!= mode_64bit
)
14542 case vex_scalar_w_dq_mode
:
14543 case vex_vsib_d_w_dq_mode
:
14544 case vex_vsib_d_w_d_mode
:
14545 case vex_vsib_q_w_dq_mode
:
14546 case vex_vsib_q_w_d_mode
:
14547 case evex_x_gscat_mode
:
14548 shift
= vex
.w
? 3 : 2;
14551 case evex_half_bcst_xmmq_mode
:
14555 shift
= vex
.w
? 3 : 2;
14558 /* Fall through. */
14562 case evex_x_nobcst_mode
:
14564 switch (vex
.length
)
14588 case q_scalar_swap_mode
:
14595 case d_scalar_swap_mode
:
14598 case w_scalar_mode
:
14602 case b_scalar_mode
:
14609 /* Make necessary corrections to shift for modes that need it.
14610 For these modes we currently have shift 4, 5 or 6 depending on
14611 vex.length (it corresponds to xmmword, ymmword or zmmword
14612 operand). We might want to make it 3, 4 or 5 (e.g. for
14613 xmmq_mode). In case of broadcast enabled the corrections
14614 aren't needed, as element size is always 32 or 64 bits. */
14616 && (bytemode
== xmmq_mode
14617 || bytemode
== evex_half_bcst_xmmq_mode
))
14619 else if (bytemode
== xmmqd_mode
)
14621 else if (bytemode
== xmmdw_mode
)
14623 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
14631 intel_operand_size (bytemode
, sizeflag
);
14634 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14636 /* 32/64 bit address mode */
14646 int addr32flag
= !((sizeflag
& AFLAG
)
14647 || bytemode
== v_bnd_mode
14648 || bytemode
== v_bndmk_mode
14649 || bytemode
== bnd_mode
14650 || bytemode
== bnd_swap_mode
);
14651 const char **indexes64
= names64
;
14652 const char **indexes32
= names32
;
14662 vindex
= sib
.index
;
14668 case vex_vsib_d_w_dq_mode
:
14669 case vex_vsib_d_w_d_mode
:
14670 case vex_vsib_q_w_dq_mode
:
14671 case vex_vsib_q_w_d_mode
:
14681 switch (vex
.length
)
14684 indexes64
= indexes32
= names_xmm
;
14688 || bytemode
== vex_vsib_q_w_dq_mode
14689 || bytemode
== vex_vsib_q_w_d_mode
)
14690 indexes64
= indexes32
= names_ymm
;
14692 indexes64
= indexes32
= names_xmm
;
14696 || bytemode
== vex_vsib_q_w_dq_mode
14697 || bytemode
== vex_vsib_q_w_d_mode
)
14698 indexes64
= indexes32
= names_zmm
;
14700 indexes64
= indexes32
= names_ymm
;
14707 haveindex
= vindex
!= 4;
14716 /* mandatory non-vector SIB must have sib */
14717 if (bytemode
== vex_sibmem_mode
)
14723 rbase
= base
+ add
;
14731 if (address_mode
== mode_64bit
&& !havesib
)
14734 if (riprel
&& bytemode
== v_bndmk_mode
)
14742 FETCH_DATA (the_info
, codep
+ 1);
14744 if ((disp
& 0x80) != 0)
14746 if (vex
.evex
&& shift
> 0)
14759 && address_mode
!= mode_16bit
)
14761 if (address_mode
== mode_64bit
)
14763 /* Display eiz instead of addr32. */
14764 needindex
= addr32flag
;
14769 /* In 32-bit mode, we need index register to tell [offset]
14770 from [eiz*1 + offset]. */
14775 havedisp
= (havebase
14777 || (havesib
&& (haveindex
|| scale
!= 0)));
14780 if (modrm
.mod
!= 0 || base
== 5)
14782 if (havedisp
|| riprel
)
14783 print_displacement (scratchbuf
, disp
);
14785 print_operand_value (scratchbuf
, 1, disp
);
14786 oappend (scratchbuf
);
14790 oappend (!addr32flag
? "(%rip)" : "(%eip)");
14794 if ((havebase
|| haveindex
|| needindex
|| needaddr32
|| riprel
)
14795 && (address_mode
!= mode_64bit
14796 || ((bytemode
!= v_bnd_mode
)
14797 && (bytemode
!= v_bndmk_mode
)
14798 && (bytemode
!= bnd_mode
)
14799 && (bytemode
!= bnd_swap_mode
))))
14800 used_prefixes
|= PREFIX_ADDR
;
14802 if (havedisp
|| (intel_syntax
&& riprel
))
14804 *obufp
++ = open_char
;
14805 if (intel_syntax
&& riprel
)
14808 oappend (!addr32flag
? "rip" : "eip");
14812 oappend (address_mode
== mode_64bit
&& !addr32flag
14813 ? names64
[rbase
] : names32
[rbase
]);
14816 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14817 print index to tell base + index from base. */
14821 || (havebase
&& base
!= ESP_REG_NUM
))
14823 if (!intel_syntax
|| havebase
)
14825 *obufp
++ = separator_char
;
14829 oappend (address_mode
== mode_64bit
&& !addr32flag
14830 ? indexes64
[vindex
] : indexes32
[vindex
]);
14832 oappend (address_mode
== mode_64bit
&& !addr32flag
14833 ? index64
: index32
);
14835 *obufp
++ = scale_char
;
14837 sprintf (scratchbuf
, "%d", 1 << scale
);
14838 oappend (scratchbuf
);
14842 && (disp
|| modrm
.mod
!= 0 || base
== 5))
14844 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
14849 else if (modrm
.mod
!= 1 && disp
!= -disp
)
14853 disp
= - (bfd_signed_vma
) disp
;
14857 print_displacement (scratchbuf
, disp
);
14859 print_operand_value (scratchbuf
, 1, disp
);
14860 oappend (scratchbuf
);
14863 *obufp
++ = close_char
;
14866 else if (intel_syntax
)
14868 if (modrm
.mod
!= 0 || base
== 5)
14870 if (!active_seg_prefix
)
14872 oappend (names_seg
[ds_reg
- es_reg
]);
14875 print_operand_value (scratchbuf
, 1, disp
);
14876 oappend (scratchbuf
);
14880 else if (bytemode
== v_bnd_mode
14881 || bytemode
== v_bndmk_mode
14882 || bytemode
== bnd_mode
14883 || bytemode
== bnd_swap_mode
)
14890 /* 16 bit address mode */
14891 used_prefixes
|= prefixes
& PREFIX_ADDR
;
14898 if ((disp
& 0x8000) != 0)
14903 FETCH_DATA (the_info
, codep
+ 1);
14905 if ((disp
& 0x80) != 0)
14907 if (vex
.evex
&& shift
> 0)
14912 if ((disp
& 0x8000) != 0)
14918 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
14920 print_displacement (scratchbuf
, disp
);
14921 oappend (scratchbuf
);
14924 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
14926 *obufp
++ = open_char
;
14928 oappend (index16
[modrm
.rm
]);
14930 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
14932 if ((bfd_signed_vma
) disp
>= 0)
14937 else if (modrm
.mod
!= 1)
14941 disp
= - (bfd_signed_vma
) disp
;
14944 print_displacement (scratchbuf
, disp
);
14945 oappend (scratchbuf
);
14948 *obufp
++ = close_char
;
14951 else if (intel_syntax
)
14953 if (!active_seg_prefix
)
14955 oappend (names_seg
[ds_reg
- es_reg
]);
14958 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
14959 oappend (scratchbuf
);
14962 if (vex
.evex
&& vex
.b
14963 && (bytemode
== x_mode
14964 || bytemode
== xmmq_mode
14965 || bytemode
== evex_half_bcst_xmmq_mode
))
14968 || bytemode
== xmmq_mode
14969 || bytemode
== evex_half_bcst_xmmq_mode
)
14971 switch (vex
.length
)
14974 oappend ("{1to2}");
14977 oappend ("{1to4}");
14980 oappend ("{1to8}");
14988 switch (vex
.length
)
14991 oappend ("{1to4}");
14994 oappend ("{1to8}");
14997 oappend ("{1to16}");
15007 OP_E (int bytemode
, int sizeflag
)
15009 /* Skip mod/rm byte. */
15013 if (modrm
.mod
== 3)
15014 OP_E_register (bytemode
, sizeflag
);
15016 OP_E_memory (bytemode
, sizeflag
);
15020 OP_G (int bytemode
, int sizeflag
)
15023 const char **names
;
15033 oappend (names8rex
[modrm
.reg
+ add
]);
15035 oappend (names8
[modrm
.reg
+ add
]);
15038 oappend (names16
[modrm
.reg
+ add
]);
15043 oappend (names32
[modrm
.reg
+ add
]);
15046 oappend (names64
[modrm
.reg
+ add
]);
15049 if (modrm
.reg
> 0x3)
15054 oappend (names_bnd
[modrm
.reg
]);
15064 oappend (names64
[modrm
.reg
+ add
]);
15067 if ((sizeflag
& DFLAG
)
15068 || (bytemode
!= v_mode
&& bytemode
!= movsxd_mode
))
15069 oappend (names32
[modrm
.reg
+ add
]);
15071 oappend (names16
[modrm
.reg
+ add
]);
15072 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15076 names
= (address_mode
== mode_64bit
15077 ? names64
: names32
);
15078 if (!(prefixes
& PREFIX_ADDR
))
15080 if (address_mode
== mode_16bit
)
15085 /* Remove "addr16/addr32". */
15086 all_prefixes
[last_addr_prefix
] = 0;
15087 names
= (address_mode
!= mode_32bit
15088 ? names32
: names16
);
15089 used_prefixes
|= PREFIX_ADDR
;
15091 oappend (names
[modrm
.reg
+ add
]);
15094 if (address_mode
== mode_64bit
)
15095 oappend (names64
[modrm
.reg
+ add
]);
15097 oappend (names32
[modrm
.reg
+ add
]);
15101 if ((modrm
.reg
+ add
) > 0x7)
15106 oappend (names_mask
[modrm
.reg
+ add
]);
15109 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15122 FETCH_DATA (the_info
, codep
+ 8);
15123 a
= *codep
++ & 0xff;
15124 a
|= (*codep
++ & 0xff) << 8;
15125 a
|= (*codep
++ & 0xff) << 16;
15126 a
|= (*codep
++ & 0xffu
) << 24;
15127 b
= *codep
++ & 0xff;
15128 b
|= (*codep
++ & 0xff) << 8;
15129 b
|= (*codep
++ & 0xff) << 16;
15130 b
|= (*codep
++ & 0xffu
) << 24;
15131 x
= a
+ ((bfd_vma
) b
<< 32);
15139 static bfd_signed_vma
15142 bfd_signed_vma x
= 0;
15144 FETCH_DATA (the_info
, codep
+ 4);
15145 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15146 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15147 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15148 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15152 static bfd_signed_vma
15155 bfd_signed_vma x
= 0;
15157 FETCH_DATA (the_info
, codep
+ 4);
15158 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15159 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15160 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15161 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15163 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
15173 FETCH_DATA (the_info
, codep
+ 2);
15174 x
= *codep
++ & 0xff;
15175 x
|= (*codep
++ & 0xff) << 8;
15180 set_op (bfd_vma op
, int riprel
)
15182 op_index
[op_ad
] = op_ad
;
15183 if (address_mode
== mode_64bit
)
15185 op_address
[op_ad
] = op
;
15186 op_riprel
[op_ad
] = riprel
;
15190 /* Mask to get a 32-bit address. */
15191 op_address
[op_ad
] = op
& 0xffffffff;
15192 op_riprel
[op_ad
] = riprel
& 0xffffffff;
15197 OP_REG (int code
, int sizeflag
)
15204 case es_reg
: case ss_reg
: case cs_reg
:
15205 case ds_reg
: case fs_reg
: case gs_reg
:
15206 oappend (names_seg
[code
- es_reg
]);
15218 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15219 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15220 s
= names16
[code
- ax_reg
+ add
];
15222 case ah_reg
: case ch_reg
: case dh_reg
: case bh_reg
:
15224 /* Fall through. */
15225 case al_reg
: case cl_reg
: case dl_reg
: case bl_reg
:
15227 s
= names8rex
[code
- al_reg
+ add
];
15229 s
= names8
[code
- al_reg
];
15231 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
15232 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
15233 if (address_mode
== mode_64bit
15234 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15236 s
= names64
[code
- rAX_reg
+ add
];
15239 code
+= eAX_reg
- rAX_reg
;
15240 /* Fall through. */
15241 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15242 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15245 s
= names64
[code
- eAX_reg
+ add
];
15248 if (sizeflag
& DFLAG
)
15249 s
= names32
[code
- eAX_reg
+ add
];
15251 s
= names16
[code
- eAX_reg
+ add
];
15252 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15256 s
= INTERNAL_DISASSEMBLER_ERROR
;
15263 OP_IMREG (int code
, int sizeflag
)
15275 case al_reg
: case cl_reg
:
15276 s
= names8
[code
- al_reg
];
15285 /* Fall through. */
15286 case z_mode_ax_reg
:
15287 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
15291 if (!(rex
& REX_W
))
15292 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15295 s
= INTERNAL_DISASSEMBLER_ERROR
;
15302 OP_I (int bytemode
, int sizeflag
)
15305 bfd_signed_vma mask
= -1;
15310 FETCH_DATA (the_info
, codep
+ 1);
15320 if (sizeflag
& DFLAG
)
15330 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15346 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15351 scratchbuf
[0] = '$';
15352 print_operand_value (scratchbuf
+ 1, 1, op
);
15353 oappend_maybe_intel (scratchbuf
);
15354 scratchbuf
[0] = '\0';
15358 OP_I64 (int bytemode
, int sizeflag
)
15360 if (bytemode
!= v_mode
|| address_mode
!= mode_64bit
|| !(rex
& REX_W
))
15362 OP_I (bytemode
, sizeflag
);
15368 scratchbuf
[0] = '$';
15369 print_operand_value (scratchbuf
+ 1, 1, get64 ());
15370 oappend_maybe_intel (scratchbuf
);
15371 scratchbuf
[0] = '\0';
15375 OP_sI (int bytemode
, int sizeflag
)
15383 FETCH_DATA (the_info
, codep
+ 1);
15385 if ((op
& 0x80) != 0)
15387 if (bytemode
== b_T_mode
)
15389 if (address_mode
!= mode_64bit
15390 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15392 /* The operand-size prefix is overridden by a REX prefix. */
15393 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15401 if (!(rex
& REX_W
))
15403 if (sizeflag
& DFLAG
)
15411 /* The operand-size prefix is overridden by a REX prefix. */
15412 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15418 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15422 scratchbuf
[0] = '$';
15423 print_operand_value (scratchbuf
+ 1, 1, op
);
15424 oappend_maybe_intel (scratchbuf
);
15428 OP_J (int bytemode
, int sizeflag
)
15432 bfd_vma segment
= 0;
15437 FETCH_DATA (the_info
, codep
+ 1);
15439 if ((disp
& 0x80) != 0)
15443 if (isa64
!= intel64
)
15446 if ((sizeflag
& DFLAG
)
15447 || (address_mode
== mode_64bit
15448 && ((isa64
== intel64
&& bytemode
!= dqw_mode
)
15449 || (rex
& REX_W
))))
15454 if ((disp
& 0x8000) != 0)
15456 /* In 16bit mode, address is wrapped around at 64k within
15457 the same segment. Otherwise, a data16 prefix on a jump
15458 instruction means that the pc is masked to 16 bits after
15459 the displacement is added! */
15461 if ((prefixes
& PREFIX_DATA
) == 0)
15462 segment
= ((start_pc
+ (codep
- start_codep
))
15463 & ~((bfd_vma
) 0xffff));
15465 if (address_mode
!= mode_64bit
15466 || (isa64
!= intel64
&& !(rex
& REX_W
)))
15467 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15470 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15473 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
15475 print_operand_value (scratchbuf
, 1, disp
);
15476 oappend (scratchbuf
);
15480 OP_SEG (int bytemode
, int sizeflag
)
15482 if (bytemode
== w_mode
)
15483 oappend (names_seg
[modrm
.reg
]);
15485 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
15489 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
15493 if (sizeflag
& DFLAG
)
15503 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15505 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
15507 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
15508 oappend (scratchbuf
);
15512 OP_OFF (int bytemode
, int sizeflag
)
15516 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
15517 intel_operand_size (bytemode
, sizeflag
);
15520 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15527 if (!active_seg_prefix
)
15529 oappend (names_seg
[ds_reg
- es_reg
]);
15533 print_operand_value (scratchbuf
, 1, off
);
15534 oappend (scratchbuf
);
15538 OP_OFF64 (int bytemode
, int sizeflag
)
15542 if (address_mode
!= mode_64bit
15543 || (prefixes
& PREFIX_ADDR
))
15545 OP_OFF (bytemode
, sizeflag
);
15549 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
15550 intel_operand_size (bytemode
, sizeflag
);
15557 if (!active_seg_prefix
)
15559 oappend (names_seg
[ds_reg
- es_reg
]);
15563 print_operand_value (scratchbuf
, 1, off
);
15564 oappend (scratchbuf
);
15568 ptr_reg (int code
, int sizeflag
)
15572 *obufp
++ = open_char
;
15573 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
15574 if (address_mode
== mode_64bit
)
15576 if (!(sizeflag
& AFLAG
))
15577 s
= names32
[code
- eAX_reg
];
15579 s
= names64
[code
- eAX_reg
];
15581 else if (sizeflag
& AFLAG
)
15582 s
= names32
[code
- eAX_reg
];
15584 s
= names16
[code
- eAX_reg
];
15586 *obufp
++ = close_char
;
15591 OP_ESreg (int code
, int sizeflag
)
15597 case 0x6d: /* insw/insl */
15598 intel_operand_size (z_mode
, sizeflag
);
15600 case 0xa5: /* movsw/movsl/movsq */
15601 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15602 case 0xab: /* stosw/stosl */
15603 case 0xaf: /* scasw/scasl */
15604 intel_operand_size (v_mode
, sizeflag
);
15607 intel_operand_size (b_mode
, sizeflag
);
15610 oappend_maybe_intel ("%es:");
15611 ptr_reg (code
, sizeflag
);
15615 OP_DSreg (int code
, int sizeflag
)
15621 case 0x6f: /* outsw/outsl */
15622 intel_operand_size (z_mode
, sizeflag
);
15624 case 0xa5: /* movsw/movsl/movsq */
15625 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15626 case 0xad: /* lodsw/lodsl/lodsq */
15627 intel_operand_size (v_mode
, sizeflag
);
15630 intel_operand_size (b_mode
, sizeflag
);
15633 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15634 default segment register DS is printed. */
15635 if (!active_seg_prefix
)
15636 active_seg_prefix
= PREFIX_DS
;
15638 ptr_reg (code
, sizeflag
);
15642 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15650 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
15652 all_prefixes
[last_lock_prefix
] = 0;
15653 used_prefixes
|= PREFIX_LOCK
;
15658 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
15659 oappend_maybe_intel (scratchbuf
);
15663 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15672 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
15674 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
15675 oappend (scratchbuf
);
15679 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15681 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
15682 oappend_maybe_intel (scratchbuf
);
15686 OP_R (int bytemode
, int sizeflag
)
15688 /* Skip mod/rm byte. */
15691 OP_E_register (bytemode
, sizeflag
);
15695 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15697 int reg
= modrm
.reg
;
15698 const char **names
;
15700 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15701 if (prefixes
& PREFIX_DATA
)
15710 oappend (names
[reg
]);
15714 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15716 int reg
= modrm
.reg
;
15717 const char **names
;
15729 && bytemode
!= xmm_mode
15730 && bytemode
!= xmmq_mode
15731 && bytemode
!= evex_half_bcst_xmmq_mode
15732 && bytemode
!= ymm_mode
15733 && bytemode
!= tmm_mode
15734 && bytemode
!= scalar_mode
)
15736 switch (vex
.length
)
15743 || (bytemode
!= vex_vsib_q_w_dq_mode
15744 && bytemode
!= vex_vsib_q_w_d_mode
))
15756 else if (bytemode
== xmmq_mode
15757 || bytemode
== evex_half_bcst_xmmq_mode
)
15759 switch (vex
.length
)
15772 else if (bytemode
== tmm_mode
)
15782 else if (bytemode
== ymm_mode
)
15786 oappend (names
[reg
]);
15790 OP_EM (int bytemode
, int sizeflag
)
15793 const char **names
;
15795 if (modrm
.mod
!= 3)
15798 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
15800 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15801 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15803 OP_E (bytemode
, sizeflag
);
15807 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
15810 /* Skip mod/rm byte. */
15813 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15815 if (prefixes
& PREFIX_DATA
)
15824 oappend (names
[reg
]);
15827 /* cvt* are the only instructions in sse2 which have
15828 both SSE and MMX operands and also have 0x66 prefix
15829 in their opcode. 0x66 was originally used to differentiate
15830 between SSE and MMX instruction(operands). So we have to handle the
15831 cvt* separately using OP_EMC and OP_MXC */
15833 OP_EMC (int bytemode
, int sizeflag
)
15835 if (modrm
.mod
!= 3)
15837 if (intel_syntax
&& bytemode
== v_mode
)
15839 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15840 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15842 OP_E (bytemode
, sizeflag
);
15846 /* Skip mod/rm byte. */
15849 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15850 oappend (names_mm
[modrm
.rm
]);
15854 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15856 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15857 oappend (names_mm
[modrm
.reg
]);
15861 OP_EX (int bytemode
, int sizeflag
)
15864 const char **names
;
15866 /* Skip mod/rm byte. */
15870 if (modrm
.mod
!= 3)
15872 OP_E_memory (bytemode
, sizeflag
);
15887 if ((sizeflag
& SUFFIX_ALWAYS
)
15888 && (bytemode
== x_swap_mode
15889 || bytemode
== d_swap_mode
15890 || bytemode
== d_scalar_swap_mode
15891 || bytemode
== q_swap_mode
15892 || bytemode
== q_scalar_swap_mode
))
15896 && bytemode
!= xmm_mode
15897 && bytemode
!= xmmdw_mode
15898 && bytemode
!= xmmqd_mode
15899 && bytemode
!= xmm_mb_mode
15900 && bytemode
!= xmm_mw_mode
15901 && bytemode
!= xmm_md_mode
15902 && bytemode
!= xmm_mq_mode
15903 && bytemode
!= xmmq_mode
15904 && bytemode
!= evex_half_bcst_xmmq_mode
15905 && bytemode
!= ymm_mode
15906 && bytemode
!= tmm_mode
15907 && bytemode
!= d_scalar_swap_mode
15908 && bytemode
!= q_scalar_swap_mode
15909 && bytemode
!= vex_scalar_w_dq_mode
)
15911 switch (vex
.length
)
15926 else if (bytemode
== xmmq_mode
15927 || bytemode
== evex_half_bcst_xmmq_mode
)
15929 switch (vex
.length
)
15942 else if (bytemode
== tmm_mode
)
15952 else if (bytemode
== ymm_mode
)
15956 oappend (names
[reg
]);
15960 OP_MS (int bytemode
, int sizeflag
)
15962 if (modrm
.mod
== 3)
15963 OP_EM (bytemode
, sizeflag
);
15969 OP_XS (int bytemode
, int sizeflag
)
15971 if (modrm
.mod
== 3)
15972 OP_EX (bytemode
, sizeflag
);
15978 OP_M (int bytemode
, int sizeflag
)
15980 if (modrm
.mod
== 3)
15981 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15984 OP_E (bytemode
, sizeflag
);
15988 OP_0f07 (int bytemode
, int sizeflag
)
15990 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
15993 OP_E (bytemode
, sizeflag
);
15996 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15997 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16000 NOP_Fixup1 (int bytemode
, int sizeflag
)
16002 if ((prefixes
& PREFIX_DATA
) != 0
16005 && address_mode
== mode_64bit
))
16006 OP_REG (bytemode
, sizeflag
);
16008 strcpy (obuf
, "nop");
16012 NOP_Fixup2 (int bytemode
, int sizeflag
)
16014 if ((prefixes
& PREFIX_DATA
) != 0
16017 && address_mode
== mode_64bit
))
16018 OP_IMREG (bytemode
, sizeflag
);
16021 static const char *const Suffix3DNow
[] = {
16022 /* 00 */ NULL
, NULL
, NULL
, NULL
,
16023 /* 04 */ NULL
, NULL
, NULL
, NULL
,
16024 /* 08 */ NULL
, NULL
, NULL
, NULL
,
16025 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
16026 /* 10 */ NULL
, NULL
, NULL
, NULL
,
16027 /* 14 */ NULL
, NULL
, NULL
, NULL
,
16028 /* 18 */ NULL
, NULL
, NULL
, NULL
,
16029 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
16030 /* 20 */ NULL
, NULL
, NULL
, NULL
,
16031 /* 24 */ NULL
, NULL
, NULL
, NULL
,
16032 /* 28 */ NULL
, NULL
, NULL
, NULL
,
16033 /* 2C */ NULL
, NULL
, NULL
, NULL
,
16034 /* 30 */ NULL
, NULL
, NULL
, NULL
,
16035 /* 34 */ NULL
, NULL
, NULL
, NULL
,
16036 /* 38 */ NULL
, NULL
, NULL
, NULL
,
16037 /* 3C */ NULL
, NULL
, NULL
, NULL
,
16038 /* 40 */ NULL
, NULL
, NULL
, NULL
,
16039 /* 44 */ NULL
, NULL
, NULL
, NULL
,
16040 /* 48 */ NULL
, NULL
, NULL
, NULL
,
16041 /* 4C */ NULL
, NULL
, NULL
, NULL
,
16042 /* 50 */ NULL
, NULL
, NULL
, NULL
,
16043 /* 54 */ NULL
, NULL
, NULL
, NULL
,
16044 /* 58 */ NULL
, NULL
, NULL
, NULL
,
16045 /* 5C */ NULL
, NULL
, NULL
, NULL
,
16046 /* 60 */ NULL
, NULL
, NULL
, NULL
,
16047 /* 64 */ NULL
, NULL
, NULL
, NULL
,
16048 /* 68 */ NULL
, NULL
, NULL
, NULL
,
16049 /* 6C */ NULL
, NULL
, NULL
, NULL
,
16050 /* 70 */ NULL
, NULL
, NULL
, NULL
,
16051 /* 74 */ NULL
, NULL
, NULL
, NULL
,
16052 /* 78 */ NULL
, NULL
, NULL
, NULL
,
16053 /* 7C */ NULL
, NULL
, NULL
, NULL
,
16054 /* 80 */ NULL
, NULL
, NULL
, NULL
,
16055 /* 84 */ NULL
, NULL
, NULL
, NULL
,
16056 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
16057 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
16058 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
16059 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
16060 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
16061 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
16062 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
16063 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
16064 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
16065 /* AC */ NULL
, NULL
, "pfacc", NULL
,
16066 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
16067 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
16068 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
16069 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
16070 /* C0 */ NULL
, NULL
, NULL
, NULL
,
16071 /* C4 */ NULL
, NULL
, NULL
, NULL
,
16072 /* C8 */ NULL
, NULL
, NULL
, NULL
,
16073 /* CC */ NULL
, NULL
, NULL
, NULL
,
16074 /* D0 */ NULL
, NULL
, NULL
, NULL
,
16075 /* D4 */ NULL
, NULL
, NULL
, NULL
,
16076 /* D8 */ NULL
, NULL
, NULL
, NULL
,
16077 /* DC */ NULL
, NULL
, NULL
, NULL
,
16078 /* E0 */ NULL
, NULL
, NULL
, NULL
,
16079 /* E4 */ NULL
, NULL
, NULL
, NULL
,
16080 /* E8 */ NULL
, NULL
, NULL
, NULL
,
16081 /* EC */ NULL
, NULL
, NULL
, NULL
,
16082 /* F0 */ NULL
, NULL
, NULL
, NULL
,
16083 /* F4 */ NULL
, NULL
, NULL
, NULL
,
16084 /* F8 */ NULL
, NULL
, NULL
, NULL
,
16085 /* FC */ NULL
, NULL
, NULL
, NULL
,
16089 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16091 const char *mnemonic
;
16093 FETCH_DATA (the_info
, codep
+ 1);
16094 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16095 place where an 8-bit immediate would normally go. ie. the last
16096 byte of the instruction. */
16097 obufp
= mnemonicendp
;
16098 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
16100 oappend (mnemonic
);
16103 /* Since a variable sized modrm/sib chunk is between the start
16104 of the opcode (0x0f0f) and the opcode suffix, we need to do
16105 all the modrm processing first, and don't know until now that
16106 we have a bad opcode. This necessitates some cleaning up. */
16107 op_out
[0][0] = '\0';
16108 op_out
[1][0] = '\0';
16111 mnemonicendp
= obufp
;
16114 static struct op simd_cmp_op
[] =
16116 { STRING_COMMA_LEN ("eq") },
16117 { STRING_COMMA_LEN ("lt") },
16118 { STRING_COMMA_LEN ("le") },
16119 { STRING_COMMA_LEN ("unord") },
16120 { STRING_COMMA_LEN ("neq") },
16121 { STRING_COMMA_LEN ("nlt") },
16122 { STRING_COMMA_LEN ("nle") },
16123 { STRING_COMMA_LEN ("ord") }
16127 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16129 unsigned int cmp_type
;
16131 FETCH_DATA (the_info
, codep
+ 1);
16132 cmp_type
= *codep
++ & 0xff;
16133 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
16136 char *p
= mnemonicendp
- 2;
16140 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16141 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16145 /* We have a reserved extension byte. Output it directly. */
16146 scratchbuf
[0] = '$';
16147 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16148 oappend_maybe_intel (scratchbuf
);
16149 scratchbuf
[0] = '\0';
16154 OP_Mwait (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16156 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
16159 strcpy (op_out
[0], names32
[0]);
16160 strcpy (op_out
[1], names32
[1]);
16161 if (bytemode
== eBX_reg
)
16162 strcpy (op_out
[2], names32
[3]);
16163 two_source_ops
= 1;
16165 /* Skip mod/rm byte. */
16171 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
16172 int sizeflag ATTRIBUTE_UNUSED
)
16174 /* monitor %{e,r,}ax,%ecx,%edx" */
16177 const char **names
= (address_mode
== mode_64bit
16178 ? names64
: names32
);
16180 if (prefixes
& PREFIX_ADDR
)
16182 /* Remove "addr16/addr32". */
16183 all_prefixes
[last_addr_prefix
] = 0;
16184 names
= (address_mode
!= mode_32bit
16185 ? names32
: names16
);
16186 used_prefixes
|= PREFIX_ADDR
;
16188 else if (address_mode
== mode_16bit
)
16190 strcpy (op_out
[0], names
[0]);
16191 strcpy (op_out
[1], names32
[1]);
16192 strcpy (op_out
[2], names32
[2]);
16193 two_source_ops
= 1;
16195 /* Skip mod/rm byte. */
16203 /* Throw away prefixes and 1st. opcode byte. */
16204 codep
= insn_codep
+ 1;
16209 REP_Fixup (int bytemode
, int sizeflag
)
16211 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16213 if (prefixes
& PREFIX_REPZ
)
16214 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
16221 OP_IMREG (bytemode
, sizeflag
);
16224 OP_ESreg (bytemode
, sizeflag
);
16227 OP_DSreg (bytemode
, sizeflag
);
16236 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16238 if ( isa64
!= amd64
)
16243 mnemonicendp
= obufp
;
16247 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16251 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16253 if (prefixes
& PREFIX_REPNZ
)
16254 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
16257 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16261 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16262 int sizeflag ATTRIBUTE_UNUSED
)
16264 if (active_seg_prefix
== PREFIX_DS
16265 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
16267 /* NOTRACK prefix is only valid on indirect branch instructions.
16268 NB: DATA prefix is unsupported for Intel64. */
16269 active_seg_prefix
= 0;
16270 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
16274 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16275 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16279 HLE_Fixup1 (int bytemode
, int sizeflag
)
16282 && (prefixes
& PREFIX_LOCK
) != 0)
16284 if (prefixes
& PREFIX_REPZ
)
16285 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16286 if (prefixes
& PREFIX_REPNZ
)
16287 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16290 OP_E (bytemode
, sizeflag
);
16293 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16294 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
16298 HLE_Fixup2 (int bytemode
, int sizeflag
)
16300 if (modrm
.mod
!= 3)
16302 if (prefixes
& PREFIX_REPZ
)
16303 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16304 if (prefixes
& PREFIX_REPNZ
)
16305 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16308 OP_E (bytemode
, sizeflag
);
16311 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
16312 "xrelease" for memory operand. No check for LOCK prefix. */
16315 HLE_Fixup3 (int bytemode
, int sizeflag
)
16318 && last_repz_prefix
> last_repnz_prefix
16319 && (prefixes
& PREFIX_REPZ
) != 0)
16320 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16322 OP_E (bytemode
, sizeflag
);
16326 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
16331 /* Change cmpxchg8b to cmpxchg16b. */
16332 char *p
= mnemonicendp
- 2;
16333 mnemonicendp
= stpcpy (p
, "16b");
16336 else if ((prefixes
& PREFIX_LOCK
) != 0)
16338 if (prefixes
& PREFIX_REPZ
)
16339 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16340 if (prefixes
& PREFIX_REPNZ
)
16341 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16344 OP_M (bytemode
, sizeflag
);
16348 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
16350 const char **names
;
16354 switch (vex
.length
)
16368 oappend (names
[reg
]);
16372 FXSAVE_Fixup (int bytemode
, int sizeflag
)
16374 /* Add proper suffix to "fxsave" and "fxrstor". */
16378 char *p
= mnemonicendp
;
16384 OP_M (bytemode
, sizeflag
);
16388 PCMPESTR_Fixup (int bytemode
, int sizeflag
)
16390 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
16393 char *p
= mnemonicendp
;
16398 else if (sizeflag
& SUFFIX_ALWAYS
)
16405 OP_EX (bytemode
, sizeflag
);
16408 /* Display the destination register operand for instructions with
16412 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16415 const char **names
;
16423 reg
= vex
.register_specifier
;
16424 vex
.register_specifier
= 0;
16425 if (address_mode
!= mode_64bit
)
16427 else if (vex
.evex
&& !vex
.v
)
16430 if (bytemode
== vex_scalar_mode
)
16432 oappend (names_xmm
[reg
]);
16436 if (bytemode
== tmm_mode
)
16438 /* All 3 TMM registers must be distinct. */
16443 /* This must be the 3rd operand. */
16444 if (obufp
!= op_out
[2])
16446 oappend (names_tmm
[reg
]);
16447 if (reg
== modrm
.reg
|| reg
== modrm
.rm
)
16448 strcpy (obufp
, "/(bad)");
16451 if (modrm
.reg
== modrm
.rm
|| modrm
.reg
== reg
|| modrm
.rm
== reg
)
16454 && (modrm
.reg
== modrm
.rm
|| modrm
.reg
== reg
))
16455 strcat (op_out
[0], "/(bad)");
16457 && (modrm
.rm
== modrm
.reg
|| modrm
.rm
== reg
))
16458 strcat (op_out
[1], "/(bad)");
16464 switch (vex
.length
)
16471 case vex_vsib_q_w_dq_mode
:
16472 case vex_vsib_q_w_d_mode
:
16488 names
= names_mask
;
16502 case vex_vsib_q_w_dq_mode
:
16503 case vex_vsib_q_w_d_mode
:
16504 names
= vex
.w
? names_ymm
: names_xmm
;
16513 names
= names_mask
;
16516 /* See PR binutils/20893 for a reproducer. */
16528 oappend (names
[reg
]);
16532 OP_VexW (int bytemode
, int sizeflag
)
16534 OP_VEX (bytemode
, sizeflag
);
16538 /* Swap 2nd and 3rd operands. */
16539 strcpy (scratchbuf
, op_out
[2]);
16540 strcpy (op_out
[2], op_out
[1]);
16541 strcpy (op_out
[1], scratchbuf
);
16546 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16549 const char **names
= names_xmm
;
16551 FETCH_DATA (the_info
, codep
+ 1);
16554 if (bytemode
!= x_mode
&& bytemode
!= scalar_mode
)
16558 if (address_mode
!= mode_64bit
)
16561 if (bytemode
== x_mode
&& vex
.length
== 256)
16564 oappend (names
[reg
]);
16568 /* Swap 3rd and 4th operands. */
16569 strcpy (scratchbuf
, op_out
[3]);
16570 strcpy (op_out
[3], op_out
[2]);
16571 strcpy (op_out
[2], scratchbuf
);
16576 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED
,
16577 int sizeflag ATTRIBUTE_UNUSED
)
16579 scratchbuf
[0] = '$';
16580 print_operand_value (scratchbuf
+ 1, 1, codep
[-1] & 0xf);
16581 oappend_maybe_intel (scratchbuf
);
16585 OP_EX_Vex (int bytemode
, int sizeflag
)
16587 if (modrm
.mod
!= 3)
16589 OP_EX (bytemode
, sizeflag
);
16593 OP_XMM_Vex (int bytemode
, int sizeflag
)
16595 if (modrm
.mod
!= 3)
16597 OP_XMM (bytemode
, sizeflag
);
16600 static struct op vex_cmp_op
[] =
16602 { STRING_COMMA_LEN ("eq") },
16603 { STRING_COMMA_LEN ("lt") },
16604 { STRING_COMMA_LEN ("le") },
16605 { STRING_COMMA_LEN ("unord") },
16606 { STRING_COMMA_LEN ("neq") },
16607 { STRING_COMMA_LEN ("nlt") },
16608 { STRING_COMMA_LEN ("nle") },
16609 { STRING_COMMA_LEN ("ord") },
16610 { STRING_COMMA_LEN ("eq_uq") },
16611 { STRING_COMMA_LEN ("nge") },
16612 { STRING_COMMA_LEN ("ngt") },
16613 { STRING_COMMA_LEN ("false") },
16614 { STRING_COMMA_LEN ("neq_oq") },
16615 { STRING_COMMA_LEN ("ge") },
16616 { STRING_COMMA_LEN ("gt") },
16617 { STRING_COMMA_LEN ("true") },
16618 { STRING_COMMA_LEN ("eq_os") },
16619 { STRING_COMMA_LEN ("lt_oq") },
16620 { STRING_COMMA_LEN ("le_oq") },
16621 { STRING_COMMA_LEN ("unord_s") },
16622 { STRING_COMMA_LEN ("neq_us") },
16623 { STRING_COMMA_LEN ("nlt_uq") },
16624 { STRING_COMMA_LEN ("nle_uq") },
16625 { STRING_COMMA_LEN ("ord_s") },
16626 { STRING_COMMA_LEN ("eq_us") },
16627 { STRING_COMMA_LEN ("nge_uq") },
16628 { STRING_COMMA_LEN ("ngt_uq") },
16629 { STRING_COMMA_LEN ("false_os") },
16630 { STRING_COMMA_LEN ("neq_os") },
16631 { STRING_COMMA_LEN ("ge_oq") },
16632 { STRING_COMMA_LEN ("gt_oq") },
16633 { STRING_COMMA_LEN ("true_us") },
16637 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16639 unsigned int cmp_type
;
16641 FETCH_DATA (the_info
, codep
+ 1);
16642 cmp_type
= *codep
++ & 0xff;
16643 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
16646 char *p
= mnemonicendp
- 2;
16650 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
16651 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
16655 /* We have a reserved extension byte. Output it directly. */
16656 scratchbuf
[0] = '$';
16657 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16658 oappend_maybe_intel (scratchbuf
);
16659 scratchbuf
[0] = '\0';
16664 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16665 int sizeflag ATTRIBUTE_UNUSED
)
16667 unsigned int cmp_type
;
16672 FETCH_DATA (the_info
, codep
+ 1);
16673 cmp_type
= *codep
++ & 0xff;
16674 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16675 If it's the case, print suffix, otherwise - print the immediate. */
16676 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
16681 char *p
= mnemonicendp
- 2;
16683 /* vpcmp* can have both one- and two-lettered suffix. */
16697 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16698 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16702 /* We have a reserved extension byte. Output it directly. */
16703 scratchbuf
[0] = '$';
16704 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16705 oappend_maybe_intel (scratchbuf
);
16706 scratchbuf
[0] = '\0';
16710 static const struct op xop_cmp_op
[] =
16712 { STRING_COMMA_LEN ("lt") },
16713 { STRING_COMMA_LEN ("le") },
16714 { STRING_COMMA_LEN ("gt") },
16715 { STRING_COMMA_LEN ("ge") },
16716 { STRING_COMMA_LEN ("eq") },
16717 { STRING_COMMA_LEN ("neq") },
16718 { STRING_COMMA_LEN ("false") },
16719 { STRING_COMMA_LEN ("true") }
16723 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16724 int sizeflag ATTRIBUTE_UNUSED
)
16726 unsigned int cmp_type
;
16728 FETCH_DATA (the_info
, codep
+ 1);
16729 cmp_type
= *codep
++ & 0xff;
16730 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
16733 char *p
= mnemonicendp
- 2;
16735 /* vpcom* can have both one- and two-lettered suffix. */
16749 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
16750 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
16754 /* We have a reserved extension byte. Output it directly. */
16755 scratchbuf
[0] = '$';
16756 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16757 oappend_maybe_intel (scratchbuf
);
16758 scratchbuf
[0] = '\0';
16762 static const struct op pclmul_op
[] =
16764 { STRING_COMMA_LEN ("lql") },
16765 { STRING_COMMA_LEN ("hql") },
16766 { STRING_COMMA_LEN ("lqh") },
16767 { STRING_COMMA_LEN ("hqh") }
16771 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16772 int sizeflag ATTRIBUTE_UNUSED
)
16774 unsigned int pclmul_type
;
16776 FETCH_DATA (the_info
, codep
+ 1);
16777 pclmul_type
= *codep
++ & 0xff;
16778 switch (pclmul_type
)
16789 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
16792 char *p
= mnemonicendp
- 3;
16797 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
16798 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
16802 /* We have a reserved extension byte. Output it directly. */
16803 scratchbuf
[0] = '$';
16804 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
16805 oappend_maybe_intel (scratchbuf
);
16806 scratchbuf
[0] = '\0';
16811 MOVBE_Fixup (int bytemode
, int sizeflag
)
16813 /* Add proper suffix to "movbe". */
16814 char *p
= mnemonicendp
;
16823 if (sizeflag
& SUFFIX_ALWAYS
)
16829 if (sizeflag
& DFLAG
)
16833 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16838 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16845 OP_M (bytemode
, sizeflag
);
16849 MOVSXD_Fixup (int bytemode
, int sizeflag
)
16851 /* Add proper suffix to "movsxd". */
16852 char *p
= mnemonicendp
;
16877 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16884 OP_E (bytemode
, sizeflag
);
16888 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16891 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
16895 if ((rex
& REX_R
) != 0 || !vex
.r
)
16901 oappend (names_mask
[modrm
.reg
]);
16905 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16907 if (modrm
.mod
== 3 && vex
.b
)
16910 case evex_rounding_64_mode
:
16911 if (address_mode
!= mode_64bit
)
16916 /* Fall through. */
16917 case evex_rounding_mode
:
16918 oappend (names_rounding
[vex
.ll
]);
16920 case evex_sae_mode
: