]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blob - opcodes/i386-dis.c
projects / thirdparty / binutils-gdb.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
x86: fold legacy/VEX {,V}MOV{H,L}* entries
[thirdparty/binutils-gdb.git] / opcodes / i386-dis.c
1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2023 Free Software Foundation, Inc.
3
4 This file is part of the GNU opcodes library.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
23 July 1988
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
27
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
34
35 #include "sysdep.h"
36 #include "disassemble.h"
37 #include "opintl.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
41
42 typedef struct instr_info instr_info;
43
44 static bool dofloat (instr_info *, int);
45 static int putop (instr_info *, const char *, int);
46 static void oappend_with_style (instr_info *, const char *,
47 enum disassembler_style);
48
49 static bool OP_E (instr_info *, int, int);
50 static bool OP_E_memory (instr_info *, int, int);
51 static bool OP_indirE (instr_info *, int, int);
52 static bool OP_G (instr_info *, int, int);
53 static bool OP_ST (instr_info *, int, int);
54 static bool OP_STi (instr_info *, int, int);
55 static bool OP_Skip_MODRM (instr_info *, int, int);
56 static bool OP_REG (instr_info *, int, int);
57 static bool OP_IMREG (instr_info *, int, int);
58 static bool OP_I (instr_info *, int, int);
59 static bool OP_I64 (instr_info *, int, int);
60 static bool OP_sI (instr_info *, int, int);
61 static bool OP_J (instr_info *, int, int);
62 static bool OP_SEG (instr_info *, int, int);
63 static bool OP_DIR (instr_info *, int, int);
64 static bool OP_OFF (instr_info *, int, int);
65 static bool OP_OFF64 (instr_info *, int, int);
66 static bool OP_ESreg (instr_info *, int, int);
67 static bool OP_DSreg (instr_info *, int, int);
68 static bool OP_C (instr_info *, int, int);
69 static bool OP_D (instr_info *, int, int);
70 static bool OP_T (instr_info *, int, int);
71 static bool OP_MMX (instr_info *, int, int);
72 static bool OP_XMM (instr_info *, int, int);
73 static bool OP_EM (instr_info *, int, int);
74 static bool OP_EX (instr_info *, int, int);
75 static bool OP_EMC (instr_info *, int,int);
76 static bool OP_MXC (instr_info *, int,int);
77 static bool OP_MS (instr_info *, int, int);
78 static bool OP_XS (instr_info *, int, int);
79 static bool OP_M (instr_info *, int, int);
80 static bool OP_VEX (instr_info *, int, int);
81 static bool OP_VexR (instr_info *, int, int);
82 static bool OP_VexW (instr_info *, int, int);
83 static bool OP_Rounding (instr_info *, int, int);
84 static bool OP_REG_VexI4 (instr_info *, int, int);
85 static bool OP_VexI4 (instr_info *, int, int);
86 static bool OP_0f07 (instr_info *, int, int);
87 static bool OP_Monitor (instr_info *, int, int);
88 static bool OP_Mwait (instr_info *, int, int);
89
90 static bool PCLMUL_Fixup (instr_info *, int, int);
91 static bool VPCMP_Fixup (instr_info *, int, int);
92 static bool VPCOM_Fixup (instr_info *, int, int);
93 static bool NOP_Fixup (instr_info *, int, int);
94 static bool OP_3DNowSuffix (instr_info *, int, int);
95 static bool CMP_Fixup (instr_info *, int, int);
96 static bool REP_Fixup (instr_info *, int, int);
97 static bool SEP_Fixup (instr_info *, int, int);
98 static bool BND_Fixup (instr_info *, int, int);
99 static bool NOTRACK_Fixup (instr_info *, int, int);
100 static bool HLE_Fixup1 (instr_info *, int, int);
101 static bool HLE_Fixup2 (instr_info *, int, int);
102 static bool HLE_Fixup3 (instr_info *, int, int);
103 static bool CMPXCHG8B_Fixup (instr_info *, int, int);
104 static bool XMM_Fixup (instr_info *, int, int);
105 static bool FXSAVE_Fixup (instr_info *, int, int);
106 static bool MOVSXD_Fixup (instr_info *, int, int);
107 static bool DistinctDest_Fixup (instr_info *, int, int);
108 static bool PREFETCHI_Fixup (instr_info *, int, int);
109
110 static void ATTRIBUTE_PRINTF_3 i386_dis_printf (const disassemble_info *,
111 enum disassembler_style,
112 const char *, ...);
113
114 /* This character is used to encode style information within the output
115 buffers. See oappend_insert_style for more details. */
116 #define STYLE_MARKER_CHAR '\002'
117
118 /* The maximum operand buffer size. */
119 #define MAX_OPERAND_BUFFER_SIZE 128
120
121 enum address_mode
122 {
123 mode_16bit,
124 mode_32bit,
125 mode_64bit
126 };
127
128 static const char *prefix_name (enum address_mode, uint8_t, int);
129
130 enum x86_64_isa
131 {
132 amd64 = 1,
133 intel64
134 };
135
136 struct instr_info
137 {
138 enum address_mode address_mode;
139
140 /* Flags for the prefixes for the current instruction. See below. */
141 int prefixes;
142
143 /* REX prefix the current instruction. See below. */
144 uint8_t rex;
145 /* Bits of REX we've already used. */
146 uint8_t rex_used;
147
148 bool need_modrm;
149 bool need_vex;
150 bool has_sib;
151
152 /* Flags for ins->prefixes which we somehow handled when printing the
153 current instruction. */
154 int used_prefixes;
155
156 /* Flags for EVEX bits which we somehow handled when printing the
157 current instruction. */
158 int evex_used;
159
160 char obuf[MAX_OPERAND_BUFFER_SIZE];
161 char *obufp;
162 char *mnemonicendp;
163 const uint8_t *start_codep;
164 uint8_t *codep;
165 const uint8_t *end_codep;
166 unsigned char nr_prefixes;
167 signed char last_lock_prefix;
168 signed char last_repz_prefix;
169 signed char last_repnz_prefix;
170 signed char last_data_prefix;
171 signed char last_addr_prefix;
172 signed char last_rex_prefix;
173 signed char last_seg_prefix;
174 signed char fwait_prefix;
175 /* The active segment register prefix. */
176 unsigned char active_seg_prefix;
177
178 #define MAX_CODE_LENGTH 15
179 /* We can up to 14 ins->prefixes since the maximum instruction length is
180 15bytes. */
181 uint8_t all_prefixes[MAX_CODE_LENGTH - 1];
182 disassemble_info *info;
183
184 struct
185 {
186 int mod;
187 int reg;
188 int rm;
189 }
190 modrm;
191
192 struct
193 {
194 int scale;
195 int index;
196 int base;
197 }
198 sib;
199
200 struct
201 {
202 int register_specifier;
203 int length;
204 int prefix;
205 int mask_register_specifier;
206 int ll;
207 bool w;
208 bool evex;
209 bool r;
210 bool v;
211 bool zeroing;
212 bool b;
213 bool no_broadcast;
214 }
215 vex;
216
217 /* Remember if the current op is a jump instruction. */
218 bool op_is_jump;
219
220 bool two_source_ops;
221
222 /* Record whether EVEX masking is used incorrectly. */
223 bool illegal_masking;
224
225 unsigned char op_ad;
226 signed char op_index[MAX_OPERANDS];
227 bool op_riprel[MAX_OPERANDS];
228 char *op_out[MAX_OPERANDS];
229 bfd_vma op_address[MAX_OPERANDS];
230 bfd_vma start_pc;
231
232 /* On the 386's of 1988, the maximum length of an instruction is 15 bytes.
233 * (see topic "Redundant ins->prefixes" in the "Differences from 8086"
234 * section of the "Virtual 8086 Mode" chapter.)
235 * 'pc' should be the address of this instruction, it will
236 * be used to print the target address if this is a relative jump or call
237 * The function returns the length of this instruction in bytes.
238 */
239 char intel_syntax;
240 bool intel_mnemonic;
241 char open_char;
242 char close_char;
243 char separator_char;
244 char scale_char;
245
246 enum x86_64_isa isa64;
247 };
248
249 struct dis_private {
250 bfd_vma insn_start;
251 int orig_sizeflag;
252
253 /* Indexes first byte not fetched. */
254 unsigned int fetched;
255 uint8_t the_buffer[2 * MAX_CODE_LENGTH - 1];
256 };
257
258 /* Mark parts used in the REX prefix. When we are testing for
259 empty prefix (for 8bit register REX extension), just mask it
260 out. Otherwise test for REX bit is excuse for existence of REX
261 only in case value is nonzero. */
262 #define USED_REX(value) \
263 { \
264 if (value) \
265 { \
266 if ((ins->rex & value)) \
267 ins->rex_used |= (value) | REX_OPCODE; \
268 } \
269 else \
270 ins->rex_used |= REX_OPCODE; \
271 }
272
273
274 #define EVEX_b_used 1
275 #define EVEX_len_used 2
276
277 /* Flags stored in PREFIXES. */
278 #define PREFIX_REPZ 1
279 #define PREFIX_REPNZ 2
280 #define PREFIX_CS 4
281 #define PREFIX_SS 8
282 #define PREFIX_DS 0x10
283 #define PREFIX_ES 0x20
284 #define PREFIX_FS 0x40
285 #define PREFIX_GS 0x80
286 #define PREFIX_LOCK 0x100
287 #define PREFIX_DATA 0x200
288 #define PREFIX_ADDR 0x400
289 #define PREFIX_FWAIT 0x800
290
291 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
292 to ADDR (exclusive) are valid. Returns true for success, false
293 on error. */
294 static bool
295 fetch_code (struct disassemble_info *info, const uint8_t *until)
296 {
297 int status = -1;
298 struct dis_private *priv = info->private_data;
299 bfd_vma start = priv->insn_start + priv->fetched;
300 uint8_t *fetch_end = priv->the_buffer + priv->fetched;
301 ptrdiff_t needed = until - fetch_end;
302
303 if (needed <= 0)
304 return true;
305
306 if (priv->fetched + (size_t) needed <= ARRAY_SIZE (priv->the_buffer))
307 status = (*info->read_memory_func) (start, fetch_end, needed, info);
308 if (status != 0)
309 {
310 /* If we did manage to read at least one byte, then
311 print_insn_i386 will do something sensible. Otherwise, print
312 an error. We do that here because this is where we know
313 STATUS. */
314 if (!priv->fetched)
315 (*info->memory_error_func) (status, start, info);
316 return false;
317 }
318
319 priv->fetched += needed;
320 return true;
321 }
322
323 static bool
324 fetch_modrm (instr_info *ins)
325 {
326 if (!fetch_code (ins->info, ins->codep + 1))
327 return false;
328
329 ins->modrm.mod = (*ins->codep >> 6) & 3;
330 ins->modrm.reg = (*ins->codep >> 3) & 7;
331 ins->modrm.rm = *ins->codep & 7;
332
333 return true;
334 }
335
336 static int
337 fetch_error (const instr_info *ins)
338 {
339 /* Getting here means we tried for data but didn't get it. That
340 means we have an incomplete instruction of some sort. Just
341 print the first byte as a prefix or a .byte pseudo-op. */
342 const struct dis_private *priv = ins->info->private_data;
343 const char *name = NULL;
344
345 if (ins->codep <= priv->the_buffer)
346 return -1;
347
348 if (ins->prefixes || ins->fwait_prefix >= 0 || (ins->rex & REX_OPCODE))
349 name = prefix_name (ins->address_mode, priv->the_buffer[0],
350 priv->orig_sizeflag);
351 if (name != NULL)
352 i386_dis_printf (ins->info, dis_style_mnemonic, "%s", name);
353 else
354 {
355 /* Just print the first byte as a .byte instruction. */
356 i386_dis_printf (ins->info, dis_style_assembler_directive, ".byte ");
357 i386_dis_printf (ins->info, dis_style_immediate, "%#x",
358 (unsigned int) priv->the_buffer[0]);
359 }
360
361 return 1;
362 }
363
364 /* Possible values for prefix requirement. */
365 #define PREFIX_IGNORED_SHIFT 16
366 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
367 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
368 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
369 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
370 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
371
372 /* Opcode prefixes. */
373 #define PREFIX_OPCODE (PREFIX_REPZ \
374 | PREFIX_REPNZ \
375 | PREFIX_DATA)
376
377 /* Prefixes ignored. */
378 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
379 | PREFIX_IGNORED_REPNZ \
380 | PREFIX_IGNORED_DATA)
381
382 #define XX { NULL, 0 }
383 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
384
385 #define Eb { OP_E, b_mode }
386 #define Ebnd { OP_E, bnd_mode }
387 #define EbS { OP_E, b_swap_mode }
388 #define EbndS { OP_E, bnd_swap_mode }
389 #define Ev { OP_E, v_mode }
390 #define Eva { OP_E, va_mode }
391 #define Ev_bnd { OP_E, v_bnd_mode }
392 #define EvS { OP_E, v_swap_mode }
393 #define Ed { OP_E, d_mode }
394 #define Edq { OP_E, dq_mode }
395 #define Edb { OP_E, db_mode }
396 #define Edw { OP_E, dw_mode }
397 #define Eq { OP_E, q_mode }
398 #define indirEv { OP_indirE, indir_v_mode }
399 #define indirEp { OP_indirE, f_mode }
400 #define stackEv { OP_E, stack_v_mode }
401 #define Em { OP_E, m_mode }
402 #define Ew { OP_E, w_mode }
403 #define M { OP_M, 0 } /* lea, lgdt, etc. */
404 #define Ma { OP_M, a_mode }
405 #define Mb { OP_M, b_mode }
406 #define Md { OP_M, d_mode }
407 #define Mdq { OP_M, dq_mode }
408 #define Mo { OP_M, o_mode }
409 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
410 #define Mq { OP_M, q_mode }
411 #define Mv { OP_M, v_mode }
412 #define Mv_bnd { OP_M, v_bndmk_mode }
413 #define Mw { OP_M, w_mode }
414 #define Mx { OP_M, x_mode }
415 #define Mxmm { OP_M, xmm_mode }
416 #define Gb { OP_G, b_mode }
417 #define Gbnd { OP_G, bnd_mode }
418 #define Gv { OP_G, v_mode }
419 #define Gd { OP_G, d_mode }
420 #define Gdq { OP_G, dq_mode }
421 #define Gm { OP_G, m_mode }
422 #define Gva { OP_G, va_mode }
423 #define Gw { OP_G, w_mode }
424 #define Ib { OP_I, b_mode }
425 #define sIb { OP_sI, b_mode } /* sign extened byte */
426 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
427 #define Iv { OP_I, v_mode }
428 #define sIv { OP_sI, v_mode }
429 #define Iv64 { OP_I64, v_mode }
430 #define Id { OP_I, d_mode }
431 #define Iw { OP_I, w_mode }
432 #define I1 { OP_I, const_1_mode }
433 #define Jb { OP_J, b_mode }
434 #define Jv { OP_J, v_mode }
435 #define Jdqw { OP_J, dqw_mode }
436 #define Cm { OP_C, m_mode }
437 #define Dm { OP_D, m_mode }
438 #define Td { OP_T, d_mode }
439 #define Skip_MODRM { OP_Skip_MODRM, 0 }
440
441 #define RMeAX { OP_REG, eAX_reg }
442 #define RMeBX { OP_REG, eBX_reg }
443 #define RMeCX { OP_REG, eCX_reg }
444 #define RMeDX { OP_REG, eDX_reg }
445 #define RMeSP { OP_REG, eSP_reg }
446 #define RMeBP { OP_REG, eBP_reg }
447 #define RMeSI { OP_REG, eSI_reg }
448 #define RMeDI { OP_REG, eDI_reg }
449 #define RMrAX { OP_REG, rAX_reg }
450 #define RMrBX { OP_REG, rBX_reg }
451 #define RMrCX { OP_REG, rCX_reg }
452 #define RMrDX { OP_REG, rDX_reg }
453 #define RMrSP { OP_REG, rSP_reg }
454 #define RMrBP { OP_REG, rBP_reg }
455 #define RMrSI { OP_REG, rSI_reg }
456 #define RMrDI { OP_REG, rDI_reg }
457 #define RMAL { OP_REG, al_reg }
458 #define RMCL { OP_REG, cl_reg }
459 #define RMDL { OP_REG, dl_reg }
460 #define RMBL { OP_REG, bl_reg }
461 #define RMAH { OP_REG, ah_reg }
462 #define RMCH { OP_REG, ch_reg }
463 #define RMDH { OP_REG, dh_reg }
464 #define RMBH { OP_REG, bh_reg }
465 #define RMAX { OP_REG, ax_reg }
466 #define RMDX { OP_REG, dx_reg }
467
468 #define eAX { OP_IMREG, eAX_reg }
469 #define AL { OP_IMREG, al_reg }
470 #define CL { OP_IMREG, cl_reg }
471 #define zAX { OP_IMREG, z_mode_ax_reg }
472 #define indirDX { OP_IMREG, indir_dx_reg }
473
474 #define Sw { OP_SEG, w_mode }
475 #define Sv { OP_SEG, v_mode }
476 #define Ap { OP_DIR, 0 }
477 #define Ob { OP_OFF64, b_mode }
478 #define Ov { OP_OFF64, v_mode }
479 #define Xb { OP_DSreg, eSI_reg }
480 #define Xv { OP_DSreg, eSI_reg }
481 #define Xz { OP_DSreg, eSI_reg }
482 #define Yb { OP_ESreg, eDI_reg }
483 #define Yv { OP_ESreg, eDI_reg }
484 #define DSBX { OP_DSreg, eBX_reg }
485
486 #define es { OP_REG, es_reg }
487 #define ss { OP_REG, ss_reg }
488 #define cs { OP_REG, cs_reg }
489 #define ds { OP_REG, ds_reg }
490 #define fs { OP_REG, fs_reg }
491 #define gs { OP_REG, gs_reg }
492
493 #define MX { OP_MMX, 0 }
494 #define XM { OP_XMM, 0 }
495 #define XMScalar { OP_XMM, scalar_mode }
496 #define XMGatherD { OP_XMM, vex_vsib_d_w_dq_mode }
497 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
498 #define XMM { OP_XMM, xmm_mode }
499 #define TMM { OP_XMM, tmm_mode }
500 #define XMxmmq { OP_XMM, xmmq_mode }
501 #define EM { OP_EM, v_mode }
502 #define EMS { OP_EM, v_swap_mode }
503 #define EMd { OP_EM, d_mode }
504 #define EMx { OP_EM, x_mode }
505 #define EXbwUnit { OP_EX, bw_unit_mode }
506 #define EXb { OP_EX, b_mode }
507 #define EXw { OP_EX, w_mode }
508 #define EXd { OP_EX, d_mode }
509 #define EXdS { OP_EX, d_swap_mode }
510 #define EXwS { OP_EX, w_swap_mode }
511 #define EXq { OP_EX, q_mode }
512 #define EXqS { OP_EX, q_swap_mode }
513 #define EXdq { OP_EX, dq_mode }
514 #define EXx { OP_EX, x_mode }
515 #define EXxh { OP_EX, xh_mode }
516 #define EXxS { OP_EX, x_swap_mode }
517 #define EXxmm { OP_EX, xmm_mode }
518 #define EXymm { OP_EX, ymm_mode }
519 #define EXtmm { OP_EX, tmm_mode }
520 #define EXxmmq { OP_EX, xmmq_mode }
521 #define EXxmmqh { OP_EX, evex_half_bcst_xmmqh_mode }
522 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
523 #define EXxmmdw { OP_EX, xmmdw_mode }
524 #define EXxmmqd { OP_EX, xmmqd_mode }
525 #define EXxmmqdh { OP_EX, evex_half_bcst_xmmqdh_mode }
526 #define EXymmq { OP_EX, ymmq_mode }
527 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
528 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
529 #define MS { OP_MS, v_mode }
530 #define XS { OP_XS, v_mode }
531 #define EMCq { OP_EMC, q_mode }
532 #define MXC { OP_MXC, 0 }
533 #define OPSUF { OP_3DNowSuffix, 0 }
534 #define SEP { SEP_Fixup, 0 }
535 #define CMP { CMP_Fixup, 0 }
536 #define XMM0 { XMM_Fixup, 0 }
537 #define FXSAVE { FXSAVE_Fixup, 0 }
538
539 #define Vex { OP_VEX, x_mode }
540 #define VexW { OP_VexW, x_mode }
541 #define VexScalar { OP_VEX, scalar_mode }
542 #define VexScalarR { OP_VexR, scalar_mode }
543 #define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode }
544 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
545 #define VexGdq { OP_VEX, dq_mode }
546 #define VexTmm { OP_VEX, tmm_mode }
547 #define XMVexI4 { OP_REG_VexI4, x_mode }
548 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
549 #define VexI4 { OP_VexI4, 0 }
550 #define PCLMUL { PCLMUL_Fixup, 0 }
551 #define VPCMP { VPCMP_Fixup, 0 }
552 #define VPCOM { VPCOM_Fixup, 0 }
553
554 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
555 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
556 #define EXxEVexS { OP_Rounding, evex_sae_mode }
557
558 #define MaskG { OP_G, mask_mode }
559 #define MaskE { OP_E, mask_mode }
560 #define MaskBDE { OP_E, mask_bd_mode }
561 #define MaskVex { OP_VEX, mask_mode }
562
563 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
564 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
565
566 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
567
568 /* Used handle "rep" prefix for string instructions. */
569 #define Xbr { REP_Fixup, eSI_reg }
570 #define Xvr { REP_Fixup, eSI_reg }
571 #define Ybr { REP_Fixup, eDI_reg }
572 #define Yvr { REP_Fixup, eDI_reg }
573 #define Yzr { REP_Fixup, eDI_reg }
574 #define indirDXr { REP_Fixup, indir_dx_reg }
575 #define ALr { REP_Fixup, al_reg }
576 #define eAXr { REP_Fixup, eAX_reg }
577
578 /* Used handle HLE prefix for lockable instructions. */
579 #define Ebh1 { HLE_Fixup1, b_mode }
580 #define Evh1 { HLE_Fixup1, v_mode }
581 #define Ebh2 { HLE_Fixup2, b_mode }
582 #define Evh2 { HLE_Fixup2, v_mode }
583 #define Ebh3 { HLE_Fixup3, b_mode }
584 #define Evh3 { HLE_Fixup3, v_mode }
585
586 #define BND { BND_Fixup, 0 }
587 #define NOTRACK { NOTRACK_Fixup, 0 }
588
589 #define cond_jump_flag { NULL, cond_jump_mode }
590 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
591
592 /* bits in sizeflag */
593 #define SUFFIX_ALWAYS 4
594 #define AFLAG 2
595 #define DFLAG 1
596
597 enum
598 {
599 /* byte operand */
600 b_mode = 1,
601 /* byte operand with operand swapped */
602 b_swap_mode,
603 /* byte operand, sign extend like 'T' suffix */
604 b_T_mode,
605 /* operand size depends on prefixes */
606 v_mode,
607 /* operand size depends on prefixes with operand swapped */
608 v_swap_mode,
609 /* operand size depends on address prefix */
610 va_mode,
611 /* word operand */
612 w_mode,
613 /* double word operand */
614 d_mode,
615 /* word operand with operand swapped */
616 w_swap_mode,
617 /* double word operand with operand swapped */
618 d_swap_mode,
619 /* quad word operand */
620 q_mode,
621 /* quad word operand with operand swapped */
622 q_swap_mode,
623 /* ten-byte operand */
624 t_mode,
625 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
626 broadcast enabled. */
627 x_mode,
628 /* Similar to x_mode, but with different EVEX mem shifts. */
629 evex_x_gscat_mode,
630 /* Similar to x_mode, but with yet different EVEX mem shifts. */
631 bw_unit_mode,
632 /* Similar to x_mode, but with disabled broadcast. */
633 evex_x_nobcst_mode,
634 /* Similar to x_mode, but with operands swapped and disabled broadcast
635 in EVEX. */
636 x_swap_mode,
637 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
638 broadcast of 16bit enabled. */
639 xh_mode,
640 /* 16-byte XMM operand */
641 xmm_mode,
642 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
643 memory operand (depending on vector length). Broadcast isn't
644 allowed. */
645 xmmq_mode,
646 /* Same as xmmq_mode, but broadcast is allowed. */
647 evex_half_bcst_xmmq_mode,
648 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
649 memory operand (depending on vector length). 16bit broadcast. */
650 evex_half_bcst_xmmqh_mode,
651 /* 16-byte XMM, word, double word or quad word operand. */
652 xmmdw_mode,
653 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
654 xmmqd_mode,
655 /* 16-byte XMM, double word, quad word operand or xmm word operand.
656 16bit broadcast. */
657 evex_half_bcst_xmmqdh_mode,
658 /* 32-byte YMM operand */
659 ymm_mode,
660 /* quad word, ymmword or zmmword memory operand. */
661 ymmq_mode,
662 /* TMM operand */
663 tmm_mode,
664 /* d_mode in 32bit, q_mode in 64bit mode. */
665 m_mode,
666 /* pair of v_mode operands */
667 a_mode,
668 cond_jump_mode,
669 loop_jcxz_mode,
670 movsxd_mode,
671 v_bnd_mode,
672 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
673 v_bndmk_mode,
674 /* operand size depends on REX.W / VEX.W. */
675 dq_mode,
676 /* Displacements like v_mode without considering Intel64 ISA. */
677 dqw_mode,
678 /* bounds operand */
679 bnd_mode,
680 /* bounds operand with operand swapped */
681 bnd_swap_mode,
682 /* 4- or 6-byte pointer operand */
683 f_mode,
684 const_1_mode,
685 /* v_mode for indirect branch opcodes. */
686 indir_v_mode,
687 /* v_mode for stack-related opcodes. */
688 stack_v_mode,
689 /* non-quad operand size depends on prefixes */
690 z_mode,
691 /* 16-byte operand */
692 o_mode,
693 /* registers like d_mode, memory like b_mode. */
694 db_mode,
695 /* registers like d_mode, memory like w_mode. */
696 dw_mode,
697
698 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
699 vex_vsib_d_w_dq_mode,
700 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
701 vex_vsib_q_w_dq_mode,
702 /* mandatory non-vector SIB. */
703 vex_sibmem_mode,
704
705 /* scalar, ignore vector length. */
706 scalar_mode,
707
708 /* Static rounding. */
709 evex_rounding_mode,
710 /* Static rounding, 64-bit mode only. */
711 evex_rounding_64_mode,
712 /* Supress all exceptions. */
713 evex_sae_mode,
714
715 /* Mask register operand. */
716 mask_mode,
717 /* Mask register operand. */
718 mask_bd_mode,
719
720 es_reg,
721 cs_reg,
722 ss_reg,
723 ds_reg,
724 fs_reg,
725 gs_reg,
726
727 eAX_reg,
728 eCX_reg,
729 eDX_reg,
730 eBX_reg,
731 eSP_reg,
732 eBP_reg,
733 eSI_reg,
734 eDI_reg,
735
736 al_reg,
737 cl_reg,
738 dl_reg,
739 bl_reg,
740 ah_reg,
741 ch_reg,
742 dh_reg,
743 bh_reg,
744
745 ax_reg,
746 cx_reg,
747 dx_reg,
748 bx_reg,
749 sp_reg,
750 bp_reg,
751 si_reg,
752 di_reg,
753
754 rAX_reg,
755 rCX_reg,
756 rDX_reg,
757 rBX_reg,
758 rSP_reg,
759 rBP_reg,
760 rSI_reg,
761 rDI_reg,
762
763 z_mode_ax_reg,
764 indir_dx_reg
765 };
766
767 enum
768 {
769 FLOATCODE = 1,
770 USE_REG_TABLE,
771 USE_MOD_TABLE,
772 USE_RM_TABLE,
773 USE_PREFIX_TABLE,
774 USE_X86_64_TABLE,
775 USE_3BYTE_TABLE,
776 USE_XOP_8F_TABLE,
777 USE_VEX_C4_TABLE,
778 USE_VEX_C5_TABLE,
779 USE_VEX_LEN_TABLE,
780 USE_VEX_W_TABLE,
781 USE_EVEX_TABLE,
782 USE_EVEX_LEN_TABLE
783 };
784
785 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
786
787 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
788 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
789 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
790 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
791 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
792 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
793 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
794 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
795 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
796 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
797 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
798 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
799 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
800 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
801 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
802 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
803
804 enum
805 {
806 REG_80 = 0,
807 REG_81,
808 REG_83,
809 REG_8F,
810 REG_C0,
811 REG_C1,
812 REG_C6,
813 REG_C7,
814 REG_D0,
815 REG_D1,
816 REG_D2,
817 REG_D3,
818 REG_F6,
819 REG_F7,
820 REG_FE,
821 REG_FF,
822 REG_0F00,
823 REG_0F01,
824 REG_0F0D,
825 REG_0F18,
826 REG_0F1C_P_0_MOD_0,
827 REG_0F1E_P_1_MOD_3,
828 REG_0F38D8_PREFIX_1,
829 REG_0F3A0F_PREFIX_1_MOD_3,
830 REG_0F71_MOD_0,
831 REG_0F72_MOD_0,
832 REG_0F73_MOD_0,
833 REG_0FA6,
834 REG_0FA7,
835 REG_0FAE,
836 REG_0FBA,
837 REG_0FC7,
838 REG_VEX_0F71_M_0,
839 REG_VEX_0F72_M_0,
840 REG_VEX_0F73_M_0,
841 REG_VEX_0FAE,
842 REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0,
843 REG_VEX_0F38F3_L_0,
844
845 REG_XOP_09_01_L_0,
846 REG_XOP_09_02_L_0,
847 REG_XOP_09_12_M_1_L_0,
848 REG_XOP_0A_12_L_0,
849
850 REG_EVEX_0F71,
851 REG_EVEX_0F72,
852 REG_EVEX_0F73,
853 REG_EVEX_0F38C6_M_0_L_2,
854 REG_EVEX_0F38C7_M_0_L_2
855 };
856
857 enum
858 {
859 MOD_62_32BIT = 0,
860 MOD_8D,
861 MOD_C4_32BIT,
862 MOD_C5_32BIT,
863 MOD_C6_REG_7,
864 MOD_C7_REG_7,
865 MOD_FF_REG_3,
866 MOD_FF_REG_5,
867 MOD_0F01_REG_0,
868 MOD_0F01_REG_1,
869 MOD_0F01_REG_2,
870 MOD_0F01_REG_3,
871 MOD_0F01_REG_5,
872 MOD_0F01_REG_7,
873 MOD_0F02,
874 MOD_0F03,
875 MOD_0F12_PREFIX_0,
876 MOD_0F12_PREFIX_2,
877 MOD_0F13,
878 MOD_0F16_PREFIX_0,
879 MOD_0F16_PREFIX_2,
880 MOD_0F17,
881 MOD_0F18_REG_0,
882 MOD_0F18_REG_1,
883 MOD_0F18_REG_2,
884 MOD_0F18_REG_3,
885 MOD_0F18_REG_6,
886 MOD_0F18_REG_7,
887 MOD_0F1A_PREFIX_0,
888 MOD_0F1B_PREFIX_0,
889 MOD_0F1B_PREFIX_1,
890 MOD_0F1C_PREFIX_0,
891 MOD_0F1E_PREFIX_1,
892 MOD_0F2B_PREFIX_0,
893 MOD_0F2B_PREFIX_1,
894 MOD_0F2B_PREFIX_2,
895 MOD_0F2B_PREFIX_3,
896 MOD_0F50,
897 MOD_0F71,
898 MOD_0F72,
899 MOD_0F73,
900 MOD_0FAE_REG_0,
901 MOD_0FAE_REG_1,
902 MOD_0FAE_REG_2,
903 MOD_0FAE_REG_3,
904 MOD_0FAE_REG_4,
905 MOD_0FAE_REG_5,
906 MOD_0FAE_REG_6,
907 MOD_0FAE_REG_7,
908 MOD_0FB2,
909 MOD_0FB4,
910 MOD_0FB5,
911 MOD_0FC3,
912 MOD_0FC7_REG_3,
913 MOD_0FC7_REG_4,
914 MOD_0FC7_REG_5,
915 MOD_0FC7_REG_6,
916 MOD_0FC7_REG_7,
917 MOD_0FD7,
918 MOD_0FE7_PREFIX_2,
919 MOD_0F382A,
920 MOD_0F38DC_PREFIX_1,
921 MOD_0F38DD_PREFIX_1,
922 MOD_0F38DE_PREFIX_1,
923 MOD_0F38DF_PREFIX_1,
924 MOD_0F38F5,
925 MOD_0F38F6_PREFIX_0,
926 MOD_0F38F8_PREFIX_1,
927 MOD_0F38F8_PREFIX_2,
928 MOD_0F38F8_PREFIX_3,
929 MOD_0F38F9,
930 MOD_0F38FA_PREFIX_1,
931 MOD_0F38FB_PREFIX_1,
932 MOD_0F3A0F_PREFIX_1,
933
934 MOD_VEX_0F2B,
935 MOD_VEX_0F41_L_1,
936 MOD_VEX_0F42_L_1,
937 MOD_VEX_0F44_L_0,
938 MOD_VEX_0F45_L_1,
939 MOD_VEX_0F46_L_1,
940 MOD_VEX_0F47_L_1,
941 MOD_VEX_0F4A_L_1,
942 MOD_VEX_0F4B_L_1,
943 MOD_VEX_0F71,
944 MOD_VEX_0F72,
945 MOD_VEX_0F73,
946 MOD_VEX_0F91_L_0,
947 MOD_VEX_0F92_L_0,
948 MOD_VEX_0F93_L_0,
949 MOD_VEX_0F98_L_0,
950 MOD_VEX_0F99_L_0,
951 MOD_VEX_0FAE_REG_2,
952 MOD_VEX_0FAE_REG_3,
953 MOD_VEX_0FD7,
954 MOD_VEX_0FE7,
955 MOD_VEX_0F381A,
956 MOD_VEX_0F382A,
957 MOD_VEX_0F382C,
958 MOD_VEX_0F382D,
959 MOD_VEX_0F382E,
960 MOD_VEX_0F382F,
961 MOD_VEX_0F3849_X86_64_L_0_W_0,
962 MOD_VEX_0F384B_X86_64_L_0_W_0,
963 MOD_VEX_0F385A,
964 MOD_VEX_0F385C_X86_64,
965 MOD_VEX_0F385E_X86_64,
966 MOD_VEX_0F386C_X86_64,
967 MOD_VEX_0F388C,
968 MOD_VEX_0F388E,
969 MOD_VEX_0F3A30_L_0,
970 MOD_VEX_0F3A31_L_0,
971 MOD_VEX_0F3A32_L_0,
972 MOD_VEX_0F3A33_L_0,
973
974 MOD_XOP_09_12,
975
976 MOD_EVEX_0F381A,
977 MOD_EVEX_0F381B,
978 MOD_EVEX_0F3828_P_1,
979 MOD_EVEX_0F382A_P_1_W_1,
980 MOD_EVEX_0F3838_P_1,
981 MOD_EVEX_0F383A_P_1_W_0,
982 MOD_EVEX_0F385A,
983 MOD_EVEX_0F385B,
984 MOD_EVEX_0F387A_W_0,
985 MOD_EVEX_0F387B_W_0,
986 MOD_EVEX_0F387C,
987 MOD_EVEX_0F38C6,
988 MOD_EVEX_0F38C7,
989 };
990
991 enum
992 {
993 RM_C6_REG_7 = 0,
994 RM_C7_REG_7,
995 RM_0F01_REG_0,
996 RM_0F01_REG_1,
997 RM_0F01_REG_2,
998 RM_0F01_REG_3,
999 RM_0F01_REG_5_MOD_3,
1000 RM_0F01_REG_7_MOD_3,
1001 RM_0F1E_P_1_MOD_3_REG_7,
1002 RM_0FAE_REG_6_MOD_3_P_0,
1003 RM_0FAE_REG_7_MOD_3,
1004 RM_0F3A0F_P_1_MOD_3_REG_0,
1005
1006 RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0,
1007 RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3,
1008 };
1009
1010 enum
1011 {
1012 PREFIX_90 = 0,
1013 PREFIX_0F00_REG_6_X86_64,
1014 PREFIX_0F01_REG_0_MOD_3_RM_6,
1015 PREFIX_0F01_REG_1_RM_2,
1016 PREFIX_0F01_REG_1_RM_4,
1017 PREFIX_0F01_REG_1_RM_5,
1018 PREFIX_0F01_REG_1_RM_6,
1019 PREFIX_0F01_REG_1_RM_7,
1020 PREFIX_0F01_REG_3_RM_1,
1021 PREFIX_0F01_REG_5_MOD_0,
1022 PREFIX_0F01_REG_5_MOD_3_RM_0,
1023 PREFIX_0F01_REG_5_MOD_3_RM_1,
1024 PREFIX_0F01_REG_5_MOD_3_RM_2,
1025 PREFIX_0F01_REG_5_MOD_3_RM_4,
1026 PREFIX_0F01_REG_5_MOD_3_RM_5,
1027 PREFIX_0F01_REG_5_MOD_3_RM_6,
1028 PREFIX_0F01_REG_5_MOD_3_RM_7,
1029 PREFIX_0F01_REG_7_MOD_3_RM_2,
1030 PREFIX_0F01_REG_7_MOD_3_RM_5,
1031 PREFIX_0F01_REG_7_MOD_3_RM_6,
1032 PREFIX_0F01_REG_7_MOD_3_RM_7,
1033 PREFIX_0F09,
1034 PREFIX_0F10,
1035 PREFIX_0F11,
1036 PREFIX_0F12,
1037 PREFIX_0F16,
1038 PREFIX_0F18_REG_6_MOD_0_X86_64,
1039 PREFIX_0F18_REG_7_MOD_0_X86_64,
1040 PREFIX_0F1A,
1041 PREFIX_0F1B,
1042 PREFIX_0F1C,
1043 PREFIX_0F1E,
1044 PREFIX_0F2A,
1045 PREFIX_0F2B,
1046 PREFIX_0F2C,
1047 PREFIX_0F2D,
1048 PREFIX_0F2E,
1049 PREFIX_0F2F,
1050 PREFIX_0F51,
1051 PREFIX_0F52,
1052 PREFIX_0F53,
1053 PREFIX_0F58,
1054 PREFIX_0F59,
1055 PREFIX_0F5A,
1056 PREFIX_0F5B,
1057 PREFIX_0F5C,
1058 PREFIX_0F5D,
1059 PREFIX_0F5E,
1060 PREFIX_0F5F,
1061 PREFIX_0F60,
1062 PREFIX_0F61,
1063 PREFIX_0F62,
1064 PREFIX_0F6F,
1065 PREFIX_0F70,
1066 PREFIX_0F78,
1067 PREFIX_0F79,
1068 PREFIX_0F7C,
1069 PREFIX_0F7D,
1070 PREFIX_0F7E,
1071 PREFIX_0F7F,
1072 PREFIX_0FAE_REG_0_MOD_3,
1073 PREFIX_0FAE_REG_1_MOD_3,
1074 PREFIX_0FAE_REG_2_MOD_3,
1075 PREFIX_0FAE_REG_3_MOD_3,
1076 PREFIX_0FAE_REG_4_MOD_0,
1077 PREFIX_0FAE_REG_4_MOD_3,
1078 PREFIX_0FAE_REG_5_MOD_3,
1079 PREFIX_0FAE_REG_6_MOD_0,
1080 PREFIX_0FAE_REG_6_MOD_3,
1081 PREFIX_0FAE_REG_7_MOD_0,
1082 PREFIX_0FB8,
1083 PREFIX_0FBC,
1084 PREFIX_0FBD,
1085 PREFIX_0FC2,
1086 PREFIX_0FC7_REG_6_MOD_0,
1087 PREFIX_0FC7_REG_6_MOD_3,
1088 PREFIX_0FC7_REG_7_MOD_3,
1089 PREFIX_0FD0,
1090 PREFIX_0FD6,
1091 PREFIX_0FE6,
1092 PREFIX_0FE7,
1093 PREFIX_0FF0,
1094 PREFIX_0FF7,
1095 PREFIX_0F38D8,
1096 PREFIX_0F38DC,
1097 PREFIX_0F38DD,
1098 PREFIX_0F38DE,
1099 PREFIX_0F38DF,
1100 PREFIX_0F38F0,
1101 PREFIX_0F38F1,
1102 PREFIX_0F38F6,
1103 PREFIX_0F38F8,
1104 PREFIX_0F38FA,
1105 PREFIX_0F38FB,
1106 PREFIX_0F38FC,
1107 PREFIX_0F3A0F,
1108 PREFIX_VEX_0F12,
1109 PREFIX_VEX_0F16,
1110 PREFIX_VEX_0F2A,
1111 PREFIX_VEX_0F2C,
1112 PREFIX_VEX_0F2D,
1113 PREFIX_VEX_0F41_L_1_M_1_W_0,
1114 PREFIX_VEX_0F41_L_1_M_1_W_1,
1115 PREFIX_VEX_0F42_L_1_M_1_W_0,
1116 PREFIX_VEX_0F42_L_1_M_1_W_1,
1117 PREFIX_VEX_0F44_L_0_M_1_W_0,
1118 PREFIX_VEX_0F44_L_0_M_1_W_1,
1119 PREFIX_VEX_0F45_L_1_M_1_W_0,
1120 PREFIX_VEX_0F45_L_1_M_1_W_1,
1121 PREFIX_VEX_0F46_L_1_M_1_W_0,
1122 PREFIX_VEX_0F46_L_1_M_1_W_1,
1123 PREFIX_VEX_0F47_L_1_M_1_W_0,
1124 PREFIX_VEX_0F47_L_1_M_1_W_1,
1125 PREFIX_VEX_0F4A_L_1_M_1_W_0,
1126 PREFIX_VEX_0F4A_L_1_M_1_W_1,
1127 PREFIX_VEX_0F4B_L_1_M_1_W_0,
1128 PREFIX_VEX_0F4B_L_1_M_1_W_1,
1129 PREFIX_VEX_0F6F,
1130 PREFIX_VEX_0F70,
1131 PREFIX_VEX_0F7E,
1132 PREFIX_VEX_0F7F,
1133 PREFIX_VEX_0F90_L_0_W_0,
1134 PREFIX_VEX_0F90_L_0_W_1,
1135 PREFIX_VEX_0F91_L_0_M_0_W_0,
1136 PREFIX_VEX_0F91_L_0_M_0_W_1,
1137 PREFIX_VEX_0F92_L_0_M_1_W_0,
1138 PREFIX_VEX_0F92_L_0_M_1_W_1,
1139 PREFIX_VEX_0F93_L_0_M_1_W_0,
1140 PREFIX_VEX_0F93_L_0_M_1_W_1,
1141 PREFIX_VEX_0F98_L_0_M_1_W_0,
1142 PREFIX_VEX_0F98_L_0_M_1_W_1,
1143 PREFIX_VEX_0F99_L_0_M_1_W_0,
1144 PREFIX_VEX_0F99_L_0_M_1_W_1,
1145 PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0,
1146 PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1,
1147 PREFIX_VEX_0F384B_X86_64_L_0_W_0_M_0,
1148 PREFIX_VEX_0F3850_W_0,
1149 PREFIX_VEX_0F3851_W_0,
1150 PREFIX_VEX_0F385C_X86_64_M_1_L_0_W_0,
1151 PREFIX_VEX_0F385E_X86_64_M_1_L_0_W_0,
1152 PREFIX_VEX_0F386C_X86_64_M_1_L_0_W_0,
1153 PREFIX_VEX_0F3872,
1154 PREFIX_VEX_0F38B0_W_0,
1155 PREFIX_VEX_0F38B1_W_0,
1156 PREFIX_VEX_0F38F5_L_0,
1157 PREFIX_VEX_0F38F6_L_0,
1158 PREFIX_VEX_0F38F7_L_0,
1159 PREFIX_VEX_0F3AF0_L_0,
1160
1161 PREFIX_EVEX_0F5B,
1162 PREFIX_EVEX_0F6F,
1163 PREFIX_EVEX_0F70,
1164 PREFIX_EVEX_0F78,
1165 PREFIX_EVEX_0F79,
1166 PREFIX_EVEX_0F7A,
1167 PREFIX_EVEX_0F7B,
1168 PREFIX_EVEX_0F7E,
1169 PREFIX_EVEX_0F7F,
1170 PREFIX_EVEX_0FC2,
1171 PREFIX_EVEX_0FE6,
1172 PREFIX_EVEX_0F3810,
1173 PREFIX_EVEX_0F3811,
1174 PREFIX_EVEX_0F3812,
1175 PREFIX_EVEX_0F3813,
1176 PREFIX_EVEX_0F3814,
1177 PREFIX_EVEX_0F3815,
1178 PREFIX_EVEX_0F3820,
1179 PREFIX_EVEX_0F3821,
1180 PREFIX_EVEX_0F3822,
1181 PREFIX_EVEX_0F3823,
1182 PREFIX_EVEX_0F3824,
1183 PREFIX_EVEX_0F3825,
1184 PREFIX_EVEX_0F3826,
1185 PREFIX_EVEX_0F3827,
1186 PREFIX_EVEX_0F3828,
1187 PREFIX_EVEX_0F3829,
1188 PREFIX_EVEX_0F382A,
1189 PREFIX_EVEX_0F3830,
1190 PREFIX_EVEX_0F3831,
1191 PREFIX_EVEX_0F3832,
1192 PREFIX_EVEX_0F3833,
1193 PREFIX_EVEX_0F3834,
1194 PREFIX_EVEX_0F3835,
1195 PREFIX_EVEX_0F3838,
1196 PREFIX_EVEX_0F3839,
1197 PREFIX_EVEX_0F383A,
1198 PREFIX_EVEX_0F3852,
1199 PREFIX_EVEX_0F3853,
1200 PREFIX_EVEX_0F3868,
1201 PREFIX_EVEX_0F3872,
1202 PREFIX_EVEX_0F389A,
1203 PREFIX_EVEX_0F389B,
1204 PREFIX_EVEX_0F38AA,
1205 PREFIX_EVEX_0F38AB,
1206
1207 PREFIX_EVEX_0F3A08,
1208 PREFIX_EVEX_0F3A0A,
1209 PREFIX_EVEX_0F3A26,
1210 PREFIX_EVEX_0F3A27,
1211 PREFIX_EVEX_0F3A56,
1212 PREFIX_EVEX_0F3A57,
1213 PREFIX_EVEX_0F3A66,
1214 PREFIX_EVEX_0F3A67,
1215 PREFIX_EVEX_0F3AC2,
1216
1217 PREFIX_EVEX_MAP5_10,
1218 PREFIX_EVEX_MAP5_11,
1219 PREFIX_EVEX_MAP5_1D,
1220 PREFIX_EVEX_MAP5_2A,
1221 PREFIX_EVEX_MAP5_2C,
1222 PREFIX_EVEX_MAP5_2D,
1223 PREFIX_EVEX_MAP5_2E,
1224 PREFIX_EVEX_MAP5_2F,
1225 PREFIX_EVEX_MAP5_51,
1226 PREFIX_EVEX_MAP5_58,
1227 PREFIX_EVEX_MAP5_59,
1228 PREFIX_EVEX_MAP5_5A,
1229 PREFIX_EVEX_MAP5_5B,
1230 PREFIX_EVEX_MAP5_5C,
1231 PREFIX_EVEX_MAP5_5D,
1232 PREFIX_EVEX_MAP5_5E,
1233 PREFIX_EVEX_MAP5_5F,
1234 PREFIX_EVEX_MAP5_78,
1235 PREFIX_EVEX_MAP5_79,
1236 PREFIX_EVEX_MAP5_7A,
1237 PREFIX_EVEX_MAP5_7B,
1238 PREFIX_EVEX_MAP5_7C,
1239 PREFIX_EVEX_MAP5_7D,
1240
1241 PREFIX_EVEX_MAP6_13,
1242 PREFIX_EVEX_MAP6_56,
1243 PREFIX_EVEX_MAP6_57,
1244 PREFIX_EVEX_MAP6_D6,
1245 PREFIX_EVEX_MAP6_D7,
1246 };
1247
1248 enum
1249 {
1250 X86_64_06 = 0,
1251 X86_64_07,
1252 X86_64_0E,
1253 X86_64_16,
1254 X86_64_17,
1255 X86_64_1E,
1256 X86_64_1F,
1257 X86_64_27,
1258 X86_64_2F,
1259 X86_64_37,
1260 X86_64_3F,
1261 X86_64_60,
1262 X86_64_61,
1263 X86_64_62,
1264 X86_64_63,
1265 X86_64_6D,
1266 X86_64_6F,
1267 X86_64_82,
1268 X86_64_9A,
1269 X86_64_C2,
1270 X86_64_C3,
1271 X86_64_C4,
1272 X86_64_C5,
1273 X86_64_CE,
1274 X86_64_D4,
1275 X86_64_D5,
1276 X86_64_E8,
1277 X86_64_E9,
1278 X86_64_EA,
1279 X86_64_0F00_REG_6,
1280 X86_64_0F01_REG_0,
1281 X86_64_0F01_REG_0_MOD_3_RM_6_P_1,
1282 X86_64_0F01_REG_0_MOD_3_RM_6_P_3,
1283 X86_64_0F01_REG_1,
1284 X86_64_0F01_REG_1_RM_2_PREFIX_1,
1285 X86_64_0F01_REG_1_RM_2_PREFIX_3,
1286 X86_64_0F01_REG_1_RM_5_PREFIX_2,
1287 X86_64_0F01_REG_1_RM_6_PREFIX_2,
1288 X86_64_0F01_REG_1_RM_7_PREFIX_2,
1289 X86_64_0F01_REG_2,
1290 X86_64_0F01_REG_3,
1291 X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
1292 X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
1293 X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
1294 X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
1295 X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1,
1296 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
1297 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
1298 X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
1299 X86_64_0F18_REG_6_MOD_0,
1300 X86_64_0F18_REG_7_MOD_0,
1301 X86_64_0F24,
1302 X86_64_0F26,
1303 X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
1304
1305 X86_64_VEX_0F3849,
1306 X86_64_VEX_0F384B,
1307 X86_64_VEX_0F385C,
1308 X86_64_VEX_0F385E,
1309 X86_64_VEX_0F386C,
1310 X86_64_VEX_0F38E0,
1311 X86_64_VEX_0F38E1,
1312 X86_64_VEX_0F38E2,
1313 X86_64_VEX_0F38E3,
1314 X86_64_VEX_0F38E4,
1315 X86_64_VEX_0F38E5,
1316 X86_64_VEX_0F38E6,
1317 X86_64_VEX_0F38E7,
1318 X86_64_VEX_0F38E8,
1319 X86_64_VEX_0F38E9,
1320 X86_64_VEX_0F38EA,
1321 X86_64_VEX_0F38EB,
1322 X86_64_VEX_0F38EC,
1323 X86_64_VEX_0F38ED,
1324 X86_64_VEX_0F38EE,
1325 X86_64_VEX_0F38EF,
1326 };
1327
1328 enum
1329 {
1330 THREE_BYTE_0F38 = 0,
1331 THREE_BYTE_0F3A
1332 };
1333
1334 enum
1335 {
1336 XOP_08 = 0,
1337 XOP_09,
1338 XOP_0A
1339 };
1340
1341 enum
1342 {
1343 VEX_0F = 0,
1344 VEX_0F38,
1345 VEX_0F3A
1346 };
1347
1348 enum
1349 {
1350 EVEX_0F = 0,
1351 EVEX_0F38,
1352 EVEX_0F3A,
1353 EVEX_MAP5,
1354 EVEX_MAP6,
1355 };
1356
1357 enum
1358 {
1359 VEX_LEN_0F12_P_0 = 0,
1360 VEX_LEN_0F12_P_2,
1361 VEX_LEN_0F13,
1362 VEX_LEN_0F16_P_0,
1363 VEX_LEN_0F16_P_2,
1364 VEX_LEN_0F17,
1365 VEX_LEN_0F41,
1366 VEX_LEN_0F42,
1367 VEX_LEN_0F44,
1368 VEX_LEN_0F45,
1369 VEX_LEN_0F46,
1370 VEX_LEN_0F47,
1371 VEX_LEN_0F4A,
1372 VEX_LEN_0F4B,
1373 VEX_LEN_0F6E,
1374 VEX_LEN_0F77,
1375 VEX_LEN_0F7E_P_1,
1376 VEX_LEN_0F7E_P_2,
1377 VEX_LEN_0F90,
1378 VEX_LEN_0F91,
1379 VEX_LEN_0F92,
1380 VEX_LEN_0F93,
1381 VEX_LEN_0F98,
1382 VEX_LEN_0F99,
1383 VEX_LEN_0FAE_R_2_M_0,
1384 VEX_LEN_0FAE_R_3_M_0,
1385 VEX_LEN_0FC4,
1386 VEX_LEN_0FC5,
1387 VEX_LEN_0FD6,
1388 VEX_LEN_0FF7,
1389 VEX_LEN_0F3816,
1390 VEX_LEN_0F3819,
1391 VEX_LEN_0F381A_M_0,
1392 VEX_LEN_0F3836,
1393 VEX_LEN_0F3841,
1394 VEX_LEN_0F3849_X86_64,
1395 VEX_LEN_0F384B_X86_64,
1396 VEX_LEN_0F385A_M_0,
1397 VEX_LEN_0F385C_X86_64_M_1,
1398 VEX_LEN_0F385E_X86_64_M_1,
1399 VEX_LEN_0F386C_X86_64_M_1,
1400 VEX_LEN_0F38DB,
1401 VEX_LEN_0F38F2,
1402 VEX_LEN_0F38F3,
1403 VEX_LEN_0F38F5,
1404 VEX_LEN_0F38F6,
1405 VEX_LEN_0F38F7,
1406 VEX_LEN_0F3A00,
1407 VEX_LEN_0F3A01,
1408 VEX_LEN_0F3A06,
1409 VEX_LEN_0F3A14,
1410 VEX_LEN_0F3A15,
1411 VEX_LEN_0F3A16,
1412 VEX_LEN_0F3A17,
1413 VEX_LEN_0F3A18,
1414 VEX_LEN_0F3A19,
1415 VEX_LEN_0F3A20,
1416 VEX_LEN_0F3A21,
1417 VEX_LEN_0F3A22,
1418 VEX_LEN_0F3A30,
1419 VEX_LEN_0F3A31,
1420 VEX_LEN_0F3A32,
1421 VEX_LEN_0F3A33,
1422 VEX_LEN_0F3A38,
1423 VEX_LEN_0F3A39,
1424 VEX_LEN_0F3A41,
1425 VEX_LEN_0F3A46,
1426 VEX_LEN_0F3A60,
1427 VEX_LEN_0F3A61,
1428 VEX_LEN_0F3A62,
1429 VEX_LEN_0F3A63,
1430 VEX_LEN_0F3ADF,
1431 VEX_LEN_0F3AF0,
1432 VEX_LEN_0FXOP_08_85,
1433 VEX_LEN_0FXOP_08_86,
1434 VEX_LEN_0FXOP_08_87,
1435 VEX_LEN_0FXOP_08_8E,
1436 VEX_LEN_0FXOP_08_8F,
1437 VEX_LEN_0FXOP_08_95,
1438 VEX_LEN_0FXOP_08_96,
1439 VEX_LEN_0FXOP_08_97,
1440 VEX_LEN_0FXOP_08_9E,
1441 VEX_LEN_0FXOP_08_9F,
1442 VEX_LEN_0FXOP_08_A3,
1443 VEX_LEN_0FXOP_08_A6,
1444 VEX_LEN_0FXOP_08_B6,
1445 VEX_LEN_0FXOP_08_C0,
1446 VEX_LEN_0FXOP_08_C1,
1447 VEX_LEN_0FXOP_08_C2,
1448 VEX_LEN_0FXOP_08_C3,
1449 VEX_LEN_0FXOP_08_CC,
1450 VEX_LEN_0FXOP_08_CD,
1451 VEX_LEN_0FXOP_08_CE,
1452 VEX_LEN_0FXOP_08_CF,
1453 VEX_LEN_0FXOP_08_EC,
1454 VEX_LEN_0FXOP_08_ED,
1455 VEX_LEN_0FXOP_08_EE,
1456 VEX_LEN_0FXOP_08_EF,
1457 VEX_LEN_0FXOP_09_01,
1458 VEX_LEN_0FXOP_09_02,
1459 VEX_LEN_0FXOP_09_12_M_1,
1460 VEX_LEN_0FXOP_09_82_W_0,
1461 VEX_LEN_0FXOP_09_83_W_0,
1462 VEX_LEN_0FXOP_09_90,
1463 VEX_LEN_0FXOP_09_91,
1464 VEX_LEN_0FXOP_09_92,
1465 VEX_LEN_0FXOP_09_93,
1466 VEX_LEN_0FXOP_09_94,
1467 VEX_LEN_0FXOP_09_95,
1468 VEX_LEN_0FXOP_09_96,
1469 VEX_LEN_0FXOP_09_97,
1470 VEX_LEN_0FXOP_09_98,
1471 VEX_LEN_0FXOP_09_99,
1472 VEX_LEN_0FXOP_09_9A,
1473 VEX_LEN_0FXOP_09_9B,
1474 VEX_LEN_0FXOP_09_C1,
1475 VEX_LEN_0FXOP_09_C2,
1476 VEX_LEN_0FXOP_09_C3,
1477 VEX_LEN_0FXOP_09_C6,
1478 VEX_LEN_0FXOP_09_C7,
1479 VEX_LEN_0FXOP_09_CB,
1480 VEX_LEN_0FXOP_09_D1,
1481 VEX_LEN_0FXOP_09_D2,
1482 VEX_LEN_0FXOP_09_D3,
1483 VEX_LEN_0FXOP_09_D6,
1484 VEX_LEN_0FXOP_09_D7,
1485 VEX_LEN_0FXOP_09_DB,
1486 VEX_LEN_0FXOP_09_E1,
1487 VEX_LEN_0FXOP_09_E2,
1488 VEX_LEN_0FXOP_09_E3,
1489 VEX_LEN_0FXOP_0A_12,
1490 };
1491
1492 enum
1493 {
1494 EVEX_LEN_0F3816 = 0,
1495 EVEX_LEN_0F3819,
1496 EVEX_LEN_0F381A_M_0,
1497 EVEX_LEN_0F381B_M_0,
1498 EVEX_LEN_0F3836,
1499 EVEX_LEN_0F385A_M_0,
1500 EVEX_LEN_0F385B_M_0,
1501 EVEX_LEN_0F38C6_M_0,
1502 EVEX_LEN_0F38C7_M_0,
1503 EVEX_LEN_0F3A00,
1504 EVEX_LEN_0F3A01,
1505 EVEX_LEN_0F3A18,
1506 EVEX_LEN_0F3A19,
1507 EVEX_LEN_0F3A1A,
1508 EVEX_LEN_0F3A1B,
1509 EVEX_LEN_0F3A23,
1510 EVEX_LEN_0F3A38,
1511 EVEX_LEN_0F3A39,
1512 EVEX_LEN_0F3A3A,
1513 EVEX_LEN_0F3A3B,
1514 EVEX_LEN_0F3A43
1515 };
1516
1517 enum
1518 {
1519 VEX_W_0F41_L_1_M_1 = 0,
1520 VEX_W_0F42_L_1_M_1,
1521 VEX_W_0F44_L_0_M_1,
1522 VEX_W_0F45_L_1_M_1,
1523 VEX_W_0F46_L_1_M_1,
1524 VEX_W_0F47_L_1_M_1,
1525 VEX_W_0F4A_L_1_M_1,
1526 VEX_W_0F4B_L_1_M_1,
1527 VEX_W_0F90_L_0,
1528 VEX_W_0F91_L_0_M_0,
1529 VEX_W_0F92_L_0_M_1,
1530 VEX_W_0F93_L_0_M_1,
1531 VEX_W_0F98_L_0_M_1,
1532 VEX_W_0F99_L_0_M_1,
1533 VEX_W_0F380C,
1534 VEX_W_0F380D,
1535 VEX_W_0F380E,
1536 VEX_W_0F380F,
1537 VEX_W_0F3813,
1538 VEX_W_0F3816_L_1,
1539 VEX_W_0F3818,
1540 VEX_W_0F3819_L_1,
1541 VEX_W_0F381A_M_0_L_1,
1542 VEX_W_0F382C_M_0,
1543 VEX_W_0F382D_M_0,
1544 VEX_W_0F382E_M_0,
1545 VEX_W_0F382F_M_0,
1546 VEX_W_0F3836,
1547 VEX_W_0F3846,
1548 VEX_W_0F3849_X86_64_L_0,
1549 VEX_W_0F384B_X86_64_L_0,
1550 VEX_W_0F3850,
1551 VEX_W_0F3851,
1552 VEX_W_0F3852,
1553 VEX_W_0F3853,
1554 VEX_W_0F3858,
1555 VEX_W_0F3859,
1556 VEX_W_0F385A_M_0_L_0,
1557 VEX_W_0F385C_X86_64_M_1_L_0,
1558 VEX_W_0F385E_X86_64_M_1_L_0,
1559 VEX_W_0F386C_X86_64_M_1_L_0,
1560 VEX_W_0F3872_P_1,
1561 VEX_W_0F3878,
1562 VEX_W_0F3879,
1563 VEX_W_0F38B0,
1564 VEX_W_0F38B1,
1565 VEX_W_0F38B4,
1566 VEX_W_0F38B5,
1567 VEX_W_0F38CF,
1568 VEX_W_0F3A00_L_1,
1569 VEX_W_0F3A01_L_1,
1570 VEX_W_0F3A02,
1571 VEX_W_0F3A04,
1572 VEX_W_0F3A05,
1573 VEX_W_0F3A06_L_1,
1574 VEX_W_0F3A18_L_1,
1575 VEX_W_0F3A19_L_1,
1576 VEX_W_0F3A1D,
1577 VEX_W_0F3A38_L_1,
1578 VEX_W_0F3A39_L_1,
1579 VEX_W_0F3A46_L_1,
1580 VEX_W_0F3A4A,
1581 VEX_W_0F3A4B,
1582 VEX_W_0F3A4C,
1583 VEX_W_0F3ACE,
1584 VEX_W_0F3ACF,
1585
1586 VEX_W_0FXOP_08_85_L_0,
1587 VEX_W_0FXOP_08_86_L_0,
1588 VEX_W_0FXOP_08_87_L_0,
1589 VEX_W_0FXOP_08_8E_L_0,
1590 VEX_W_0FXOP_08_8F_L_0,
1591 VEX_W_0FXOP_08_95_L_0,
1592 VEX_W_0FXOP_08_96_L_0,
1593 VEX_W_0FXOP_08_97_L_0,
1594 VEX_W_0FXOP_08_9E_L_0,
1595 VEX_W_0FXOP_08_9F_L_0,
1596 VEX_W_0FXOP_08_A6_L_0,
1597 VEX_W_0FXOP_08_B6_L_0,
1598 VEX_W_0FXOP_08_C0_L_0,
1599 VEX_W_0FXOP_08_C1_L_0,
1600 VEX_W_0FXOP_08_C2_L_0,
1601 VEX_W_0FXOP_08_C3_L_0,
1602 VEX_W_0FXOP_08_CC_L_0,
1603 VEX_W_0FXOP_08_CD_L_0,
1604 VEX_W_0FXOP_08_CE_L_0,
1605 VEX_W_0FXOP_08_CF_L_0,
1606 VEX_W_0FXOP_08_EC_L_0,
1607 VEX_W_0FXOP_08_ED_L_0,
1608 VEX_W_0FXOP_08_EE_L_0,
1609 VEX_W_0FXOP_08_EF_L_0,
1610
1611 VEX_W_0FXOP_09_80,
1612 VEX_W_0FXOP_09_81,
1613 VEX_W_0FXOP_09_82,
1614 VEX_W_0FXOP_09_83,
1615 VEX_W_0FXOP_09_C1_L_0,
1616 VEX_W_0FXOP_09_C2_L_0,
1617 VEX_W_0FXOP_09_C3_L_0,
1618 VEX_W_0FXOP_09_C6_L_0,
1619 VEX_W_0FXOP_09_C7_L_0,
1620 VEX_W_0FXOP_09_CB_L_0,
1621 VEX_W_0FXOP_09_D1_L_0,
1622 VEX_W_0FXOP_09_D2_L_0,
1623 VEX_W_0FXOP_09_D3_L_0,
1624 VEX_W_0FXOP_09_D6_L_0,
1625 VEX_W_0FXOP_09_D7_L_0,
1626 VEX_W_0FXOP_09_DB_L_0,
1627 VEX_W_0FXOP_09_E1_L_0,
1628 VEX_W_0FXOP_09_E2_L_0,
1629 VEX_W_0FXOP_09_E3_L_0,
1630
1631 EVEX_W_0F5B_P_0,
1632 EVEX_W_0F62,
1633 EVEX_W_0F66,
1634 EVEX_W_0F6A,
1635 EVEX_W_0F6B,
1636 EVEX_W_0F6C,
1637 EVEX_W_0F6D,
1638 EVEX_W_0F6F_P_1,
1639 EVEX_W_0F6F_P_2,
1640 EVEX_W_0F6F_P_3,
1641 EVEX_W_0F70_P_2,
1642 EVEX_W_0F72_R_2,
1643 EVEX_W_0F72_R_6,
1644 EVEX_W_0F73_R_2,
1645 EVEX_W_0F73_R_6,
1646 EVEX_W_0F76,
1647 EVEX_W_0F78_P_0,
1648 EVEX_W_0F78_P_2,
1649 EVEX_W_0F79_P_0,
1650 EVEX_W_0F79_P_2,
1651 EVEX_W_0F7A_P_1,
1652 EVEX_W_0F7A_P_2,
1653 EVEX_W_0F7A_P_3,
1654 EVEX_W_0F7B_P_2,
1655 EVEX_W_0F7E_P_1,
1656 EVEX_W_0F7F_P_1,
1657 EVEX_W_0F7F_P_2,
1658 EVEX_W_0F7F_P_3,
1659 EVEX_W_0FD2,
1660 EVEX_W_0FD3,
1661 EVEX_W_0FD4,
1662 EVEX_W_0FD6,
1663 EVEX_W_0FE6_P_1,
1664 EVEX_W_0FE7,
1665 EVEX_W_0FF2,
1666 EVEX_W_0FF3,
1667 EVEX_W_0FF4,
1668 EVEX_W_0FFA,
1669 EVEX_W_0FFB,
1670 EVEX_W_0FFE,
1671
1672 EVEX_W_0F3810_P_1,
1673 EVEX_W_0F3810_P_2,
1674 EVEX_W_0F3811_P_1,
1675 EVEX_W_0F3811_P_2,
1676 EVEX_W_0F3812_P_1,
1677 EVEX_W_0F3812_P_2,
1678 EVEX_W_0F3813_P_1,
1679 EVEX_W_0F3814_P_1,
1680 EVEX_W_0F3815_P_1,
1681 EVEX_W_0F3819_L_n,
1682 EVEX_W_0F381A_M_0_L_n,
1683 EVEX_W_0F381B_M_0_L_2,
1684 EVEX_W_0F381E,
1685 EVEX_W_0F381F,
1686 EVEX_W_0F3820_P_1,
1687 EVEX_W_0F3821_P_1,
1688 EVEX_W_0F3822_P_1,
1689 EVEX_W_0F3823_P_1,
1690 EVEX_W_0F3824_P_1,
1691 EVEX_W_0F3825_P_1,
1692 EVEX_W_0F3825_P_2,
1693 EVEX_W_0F3828_P_2,
1694 EVEX_W_0F3829_P_2,
1695 EVEX_W_0F382A_P_1,
1696 EVEX_W_0F382A_P_2,
1697 EVEX_W_0F382B,
1698 EVEX_W_0F3830_P_1,
1699 EVEX_W_0F3831_P_1,
1700 EVEX_W_0F3832_P_1,
1701 EVEX_W_0F3833_P_1,
1702 EVEX_W_0F3834_P_1,
1703 EVEX_W_0F3835_P_1,
1704 EVEX_W_0F3835_P_2,
1705 EVEX_W_0F3837,
1706 EVEX_W_0F383A_P_1,
1707 EVEX_W_0F3859,
1708 EVEX_W_0F385A_M_0_L_n,
1709 EVEX_W_0F385B_M_0_L_2,
1710 EVEX_W_0F3870,
1711 EVEX_W_0F3872_P_2,
1712 EVEX_W_0F387A,
1713 EVEX_W_0F387B,
1714 EVEX_W_0F3883,
1715
1716 EVEX_W_0F3A18_L_n,
1717 EVEX_W_0F3A19_L_n,
1718 EVEX_W_0F3A1A_L_2,
1719 EVEX_W_0F3A1B_L_2,
1720 EVEX_W_0F3A21,
1721 EVEX_W_0F3A23_L_n,
1722 EVEX_W_0F3A38_L_n,
1723 EVEX_W_0F3A39_L_n,
1724 EVEX_W_0F3A3A_L_2,
1725 EVEX_W_0F3A3B_L_2,
1726 EVEX_W_0F3A42,
1727 EVEX_W_0F3A43_L_n,
1728 EVEX_W_0F3A70,
1729 EVEX_W_0F3A72,
1730
1731 EVEX_W_MAP5_5B_P_0,
1732 EVEX_W_MAP5_7A_P_3,
1733 };
1734
1735 typedef bool (*op_rtn) (instr_info *ins, int bytemode, int sizeflag);
1736
1737 struct dis386 {
1738 const char *name;
1739 struct
1740 {
1741 op_rtn rtn;
1742 int bytemode;
1743 } op[MAX_OPERANDS];
1744 unsigned int prefix_requirement;
1745 };
1746
1747 /* Upper case letters in the instruction names here are macros.
1748 'A' => print 'b' if no register operands or suffix_always is true
1749 'B' => print 'b' if suffix_always is true
1750 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1751 size prefix
1752 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1753 suffix_always is true
1754 'E' => print 'e' if 32-bit form of jcxz
1755 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1756 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1757 'H' => print ",pt" or ",pn" branch hint
1758 'I' unused.
1759 'J' unused.
1760 'K' => print 'd' or 'q' if rex prefix is present.
1761 'L' unused.
1762 'M' => print 'r' if intel_mnemonic is false.
1763 'N' => print 'n' if instruction has no wait "prefix"
1764 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1765 'P' => behave as 'T' except with register operand outside of suffix_always
1766 mode
1767 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1768 is true
1769 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1770 'S' => print 'w', 'l' or 'q' if suffix_always is true
1771 'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1772 prefix or if suffix_always is true.
1773 'U' unused.
1774 'V' => print 'v' for VEX/EVEX and nothing for legacy encodings.
1775 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1776 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1777 'Y' => no output, mark EVEX.aaa != 0 as bad.
1778 'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1779 '!' => change condition from true to false or from false to true.
1780 '%' => add 1 upper case letter to the macro.
1781 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1782 prefix or suffix_always is true (lcall/ljmp).
1783 '@' => in 64bit mode for Intel64 ISA or if instruction
1784 has no operand sizing prefix, print 'q' if suffix_always is true or
1785 nothing otherwise; behave as 'P' in all other cases
1786
1787 2 upper case letter macros:
1788 "XY" => print 'x' or 'y' if suffix_always is true or no register
1789 operands and no broadcast.
1790 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1791 register operands and no broadcast.
1792 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1793 "XD" => print 'd' if !EVEX or EVEX.W=1, EVEX.W=0 is not a valid encoding
1794 "XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16)
1795 "XS" => print 's' if !EVEX or EVEX.W=0, EVEX.W=1 is not a valid encoding
1796 "XV" => print "{vex} " pseudo prefix
1797 "XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is
1798 is used by an EVEX-encoded (AVX512VL) instruction.
1799 "YK" keep unused, to avoid ambiguity with the combined use of Y and K.
1800 "YX" keep unused, to avoid ambiguity with the combined use of Y and X.
1801 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1802 being false, or no operand at all in 64bit mode, or if suffix_always
1803 is true.
1804 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1805 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1806 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1807 "DQ" => print 'd' or 'q' depending on the VEX.W bit
1808 "BW" => print 'b' or 'w' depending on the VEX.W bit
1809 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1810 an operand size prefix, or suffix_always is true. print
1811 'q' if rex prefix is present.
1812
1813 Many of the above letters print nothing in Intel mode. See "putop"
1814 for the details.
1815
1816 Braces '{' and '}', and vertical bars '|', indicate alternative
1817 mnemonic strings for AT&T and Intel. */
1818
1819 static const struct dis386 dis386[] = {
1820 /* 00 */
1821 { "addB", { Ebh1, Gb }, 0 },
1822 { "addS", { Evh1, Gv }, 0 },
1823 { "addB", { Gb, EbS }, 0 },
1824 { "addS", { Gv, EvS }, 0 },
1825 { "addB", { AL, Ib }, 0 },
1826 { "addS", { eAX, Iv }, 0 },
1827 { X86_64_TABLE (X86_64_06) },
1828 { X86_64_TABLE (X86_64_07) },
1829 /* 08 */
1830 { "orB", { Ebh1, Gb }, 0 },
1831 { "orS", { Evh1, Gv }, 0 },
1832 { "orB", { Gb, EbS }, 0 },
1833 { "orS", { Gv, EvS }, 0 },
1834 { "orB", { AL, Ib }, 0 },
1835 { "orS", { eAX, Iv }, 0 },
1836 { X86_64_TABLE (X86_64_0E) },
1837 { Bad_Opcode }, /* 0x0f extended opcode escape */
1838 /* 10 */
1839 { "adcB", { Ebh1, Gb }, 0 },
1840 { "adcS", { Evh1, Gv }, 0 },
1841 { "adcB", { Gb, EbS }, 0 },
1842 { "adcS", { Gv, EvS }, 0 },
1843 { "adcB", { AL, Ib }, 0 },
1844 { "adcS", { eAX, Iv }, 0 },
1845 { X86_64_TABLE (X86_64_16) },
1846 { X86_64_TABLE (X86_64_17) },
1847 /* 18 */
1848 { "sbbB", { Ebh1, Gb }, 0 },
1849 { "sbbS", { Evh1, Gv }, 0 },
1850 { "sbbB", { Gb, EbS }, 0 },
1851 { "sbbS", { Gv, EvS }, 0 },
1852 { "sbbB", { AL, Ib }, 0 },
1853 { "sbbS", { eAX, Iv }, 0 },
1854 { X86_64_TABLE (X86_64_1E) },
1855 { X86_64_TABLE (X86_64_1F) },
1856 /* 20 */
1857 { "andB", { Ebh1, Gb }, 0 },
1858 { "andS", { Evh1, Gv }, 0 },
1859 { "andB", { Gb, EbS }, 0 },
1860 { "andS", { Gv, EvS }, 0 },
1861 { "andB", { AL, Ib }, 0 },
1862 { "andS", { eAX, Iv }, 0 },
1863 { Bad_Opcode }, /* SEG ES prefix */
1864 { X86_64_TABLE (X86_64_27) },
1865 /* 28 */
1866 { "subB", { Ebh1, Gb }, 0 },
1867 { "subS", { Evh1, Gv }, 0 },
1868 { "subB", { Gb, EbS }, 0 },
1869 { "subS", { Gv, EvS }, 0 },
1870 { "subB", { AL, Ib }, 0 },
1871 { "subS", { eAX, Iv }, 0 },
1872 { Bad_Opcode }, /* SEG CS prefix */
1873 { X86_64_TABLE (X86_64_2F) },
1874 /* 30 */
1875 { "xorB", { Ebh1, Gb }, 0 },
1876 { "xorS", { Evh1, Gv }, 0 },
1877 { "xorB", { Gb, EbS }, 0 },
1878 { "xorS", { Gv, EvS }, 0 },
1879 { "xorB", { AL, Ib }, 0 },
1880 { "xorS", { eAX, Iv }, 0 },
1881 { Bad_Opcode }, /* SEG SS prefix */
1882 { X86_64_TABLE (X86_64_37) },
1883 /* 38 */
1884 { "cmpB", { Eb, Gb }, 0 },
1885 { "cmpS", { Ev, Gv }, 0 },
1886 { "cmpB", { Gb, EbS }, 0 },
1887 { "cmpS", { Gv, EvS }, 0 },
1888 { "cmpB", { AL, Ib }, 0 },
1889 { "cmpS", { eAX, Iv }, 0 },
1890 { Bad_Opcode }, /* SEG DS prefix */
1891 { X86_64_TABLE (X86_64_3F) },
1892 /* 40 */
1893 { "inc{S|}", { RMeAX }, 0 },
1894 { "inc{S|}", { RMeCX }, 0 },
1895 { "inc{S|}", { RMeDX }, 0 },
1896 { "inc{S|}", { RMeBX }, 0 },
1897 { "inc{S|}", { RMeSP }, 0 },
1898 { "inc{S|}", { RMeBP }, 0 },
1899 { "inc{S|}", { RMeSI }, 0 },
1900 { "inc{S|}", { RMeDI }, 0 },
1901 /* 48 */
1902 { "dec{S|}", { RMeAX }, 0 },
1903 { "dec{S|}", { RMeCX }, 0 },
1904 { "dec{S|}", { RMeDX }, 0 },
1905 { "dec{S|}", { RMeBX }, 0 },
1906 { "dec{S|}", { RMeSP }, 0 },
1907 { "dec{S|}", { RMeBP }, 0 },
1908 { "dec{S|}", { RMeSI }, 0 },
1909 { "dec{S|}", { RMeDI }, 0 },
1910 /* 50 */
1911 { "push{!P|}", { RMrAX }, 0 },
1912 { "push{!P|}", { RMrCX }, 0 },
1913 { "push{!P|}", { RMrDX }, 0 },
1914 { "push{!P|}", { RMrBX }, 0 },
1915 { "push{!P|}", { RMrSP }, 0 },
1916 { "push{!P|}", { RMrBP }, 0 },
1917 { "push{!P|}", { RMrSI }, 0 },
1918 { "push{!P|}", { RMrDI }, 0 },
1919 /* 58 */
1920 { "pop{!P|}", { RMrAX }, 0 },
1921 { "pop{!P|}", { RMrCX }, 0 },
1922 { "pop{!P|}", { RMrDX }, 0 },
1923 { "pop{!P|}", { RMrBX }, 0 },
1924 { "pop{!P|}", { RMrSP }, 0 },
1925 { "pop{!P|}", { RMrBP }, 0 },
1926 { "pop{!P|}", { RMrSI }, 0 },
1927 { "pop{!P|}", { RMrDI }, 0 },
1928 /* 60 */
1929 { X86_64_TABLE (X86_64_60) },
1930 { X86_64_TABLE (X86_64_61) },
1931 { X86_64_TABLE (X86_64_62) },
1932 { X86_64_TABLE (X86_64_63) },
1933 { Bad_Opcode }, /* seg fs */
1934 { Bad_Opcode }, /* seg gs */
1935 { Bad_Opcode }, /* op size prefix */
1936 { Bad_Opcode }, /* adr size prefix */
1937 /* 68 */
1938 { "pushP", { sIv }, 0 },
1939 { "imulS", { Gv, Ev, Iv }, 0 },
1940 { "pushP", { sIbT }, 0 },
1941 { "imulS", { Gv, Ev, sIb }, 0 },
1942 { "ins{b|}", { Ybr, indirDX }, 0 },
1943 { X86_64_TABLE (X86_64_6D) },
1944 { "outs{b|}", { indirDXr, Xb }, 0 },
1945 { X86_64_TABLE (X86_64_6F) },
1946 /* 70 */
1947 { "joH", { Jb, BND, cond_jump_flag }, 0 },
1948 { "jnoH", { Jb, BND, cond_jump_flag }, 0 },
1949 { "jbH", { Jb, BND, cond_jump_flag }, 0 },
1950 { "jaeH", { Jb, BND, cond_jump_flag }, 0 },
1951 { "jeH", { Jb, BND, cond_jump_flag }, 0 },
1952 { "jneH", { Jb, BND, cond_jump_flag }, 0 },
1953 { "jbeH", { Jb, BND, cond_jump_flag }, 0 },
1954 { "jaH", { Jb, BND, cond_jump_flag }, 0 },
1955 /* 78 */
1956 { "jsH", { Jb, BND, cond_jump_flag }, 0 },
1957 { "jnsH", { Jb, BND, cond_jump_flag }, 0 },
1958 { "jpH", { Jb, BND, cond_jump_flag }, 0 },
1959 { "jnpH", { Jb, BND, cond_jump_flag }, 0 },
1960 { "jlH", { Jb, BND, cond_jump_flag }, 0 },
1961 { "jgeH", { Jb, BND, cond_jump_flag }, 0 },
1962 { "jleH", { Jb, BND, cond_jump_flag }, 0 },
1963 { "jgH", { Jb, BND, cond_jump_flag }, 0 },
1964 /* 80 */
1965 { REG_TABLE (REG_80) },
1966 { REG_TABLE (REG_81) },
1967 { X86_64_TABLE (X86_64_82) },
1968 { REG_TABLE (REG_83) },
1969 { "testB", { Eb, Gb }, 0 },
1970 { "testS", { Ev, Gv }, 0 },
1971 { "xchgB", { Ebh2, Gb }, 0 },
1972 { "xchgS", { Evh2, Gv }, 0 },
1973 /* 88 */
1974 { "movB", { Ebh3, Gb }, 0 },
1975 { "movS", { Evh3, Gv }, 0 },
1976 { "movB", { Gb, EbS }, 0 },
1977 { "movS", { Gv, EvS }, 0 },
1978 { "movD", { Sv, Sw }, 0 },
1979 { MOD_TABLE (MOD_8D) },
1980 { "movD", { Sw, Sv }, 0 },
1981 { REG_TABLE (REG_8F) },
1982 /* 90 */
1983 { PREFIX_TABLE (PREFIX_90) },
1984 { "xchgS", { RMeCX, eAX }, 0 },
1985 { "xchgS", { RMeDX, eAX }, 0 },
1986 { "xchgS", { RMeBX, eAX }, 0 },
1987 { "xchgS", { RMeSP, eAX }, 0 },
1988 { "xchgS", { RMeBP, eAX }, 0 },
1989 { "xchgS", { RMeSI, eAX }, 0 },
1990 { "xchgS", { RMeDI, eAX }, 0 },
1991 /* 98 */
1992 { "cW{t|}R", { XX }, 0 },
1993 { "cR{t|}O", { XX }, 0 },
1994 { X86_64_TABLE (X86_64_9A) },
1995 { Bad_Opcode }, /* fwait */
1996 { "pushfP", { XX }, 0 },
1997 { "popfP", { XX }, 0 },
1998 { "sahf", { XX }, 0 },
1999 { "lahf", { XX }, 0 },
2000 /* a0 */
2001 { "mov%LB", { AL, Ob }, 0 },
2002 { "mov%LS", { eAX, Ov }, 0 },
2003 { "mov%LB", { Ob, AL }, 0 },
2004 { "mov%LS", { Ov, eAX }, 0 },
2005 { "movs{b|}", { Ybr, Xb }, 0 },
2006 { "movs{R|}", { Yvr, Xv }, 0 },
2007 { "cmps{b|}", { Xb, Yb }, 0 },
2008 { "cmps{R|}", { Xv, Yv }, 0 },
2009 /* a8 */
2010 { "testB", { AL, Ib }, 0 },
2011 { "testS", { eAX, Iv }, 0 },
2012 { "stosB", { Ybr, AL }, 0 },
2013 { "stosS", { Yvr, eAX }, 0 },
2014 { "lodsB", { ALr, Xb }, 0 },
2015 { "lodsS", { eAXr, Xv }, 0 },
2016 { "scasB", { AL, Yb }, 0 },
2017 { "scasS", { eAX, Yv }, 0 },
2018 /* b0 */
2019 { "movB", { RMAL, Ib }, 0 },
2020 { "movB", { RMCL, Ib }, 0 },
2021 { "movB", { RMDL, Ib }, 0 },
2022 { "movB", { RMBL, Ib }, 0 },
2023 { "movB", { RMAH, Ib }, 0 },
2024 { "movB", { RMCH, Ib }, 0 },
2025 { "movB", { RMDH, Ib }, 0 },
2026 { "movB", { RMBH, Ib }, 0 },
2027 /* b8 */
2028 { "mov%LV", { RMeAX, Iv64 }, 0 },
2029 { "mov%LV", { RMeCX, Iv64 }, 0 },
2030 { "mov%LV", { RMeDX, Iv64 }, 0 },
2031 { "mov%LV", { RMeBX, Iv64 }, 0 },
2032 { "mov%LV", { RMeSP, Iv64 }, 0 },
2033 { "mov%LV", { RMeBP, Iv64 }, 0 },
2034 { "mov%LV", { RMeSI, Iv64 }, 0 },
2035 { "mov%LV", { RMeDI, Iv64 }, 0 },
2036 /* c0 */
2037 { REG_TABLE (REG_C0) },
2038 { REG_TABLE (REG_C1) },
2039 { X86_64_TABLE (X86_64_C2) },
2040 { X86_64_TABLE (X86_64_C3) },
2041 { X86_64_TABLE (X86_64_C4) },
2042 { X86_64_TABLE (X86_64_C5) },
2043 { REG_TABLE (REG_C6) },
2044 { REG_TABLE (REG_C7) },
2045 /* c8 */
2046 { "enterP", { Iw, Ib }, 0 },
2047 { "leaveP", { XX }, 0 },
2048 { "{l|}ret{|f}%LP", { Iw }, 0 },
2049 { "{l|}ret{|f}%LP", { XX }, 0 },
2050 { "int3", { XX }, 0 },
2051 { "int", { Ib }, 0 },
2052 { X86_64_TABLE (X86_64_CE) },
2053 { "iret%LP", { XX }, 0 },
2054 /* d0 */
2055 { REG_TABLE (REG_D0) },
2056 { REG_TABLE (REG_D1) },
2057 { REG_TABLE (REG_D2) },
2058 { REG_TABLE (REG_D3) },
2059 { X86_64_TABLE (X86_64_D4) },
2060 { X86_64_TABLE (X86_64_D5) },
2061 { Bad_Opcode },
2062 { "xlat", { DSBX }, 0 },
2063 /* d8 */
2064 { FLOAT },
2065 { FLOAT },
2066 { FLOAT },
2067 { FLOAT },
2068 { FLOAT },
2069 { FLOAT },
2070 { FLOAT },
2071 { FLOAT },
2072 /* e0 */
2073 { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 },
2074 { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 },
2075 { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 },
2076 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 },
2077 { "inB", { AL, Ib }, 0 },
2078 { "inG", { zAX, Ib }, 0 },
2079 { "outB", { Ib, AL }, 0 },
2080 { "outG", { Ib, zAX }, 0 },
2081 /* e8 */
2082 { X86_64_TABLE (X86_64_E8) },
2083 { X86_64_TABLE (X86_64_E9) },
2084 { X86_64_TABLE (X86_64_EA) },
2085 { "jmp", { Jb, BND }, 0 },
2086 { "inB", { AL, indirDX }, 0 },
2087 { "inG", { zAX, indirDX }, 0 },
2088 { "outB", { indirDX, AL }, 0 },
2089 { "outG", { indirDX, zAX }, 0 },
2090 /* f0 */
2091 { Bad_Opcode }, /* lock prefix */
2092 { "int1", { XX }, 0 },
2093 { Bad_Opcode }, /* repne */
2094 { Bad_Opcode }, /* repz */
2095 { "hlt", { XX }, 0 },
2096 { "cmc", { XX }, 0 },
2097 { REG_TABLE (REG_F6) },
2098 { REG_TABLE (REG_F7) },
2099 /* f8 */
2100 { "clc", { XX }, 0 },
2101 { "stc", { XX }, 0 },
2102 { "cli", { XX }, 0 },
2103 { "sti", { XX }, 0 },
2104 { "cld", { XX }, 0 },
2105 { "std", { XX }, 0 },
2106 { REG_TABLE (REG_FE) },
2107 { REG_TABLE (REG_FF) },
2108 };
2109
2110 static const struct dis386 dis386_twobyte[] = {
2111 /* 00 */
2112 { REG_TABLE (REG_0F00 ) },
2113 { REG_TABLE (REG_0F01 ) },
2114 { MOD_TABLE (MOD_0F02) },
2115 { MOD_TABLE (MOD_0F03) },
2116 { Bad_Opcode },
2117 { "syscall", { XX }, 0 },
2118 { "clts", { XX }, 0 },
2119 { "sysret%LQ", { XX }, 0 },
2120 /* 08 */
2121 { "invd", { XX }, 0 },
2122 { PREFIX_TABLE (PREFIX_0F09) },
2123 { Bad_Opcode },
2124 { "ud2", { XX }, 0 },
2125 { Bad_Opcode },
2126 { REG_TABLE (REG_0F0D) },
2127 { "femms", { XX }, 0 },
2128 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2129 /* 10 */
2130 { PREFIX_TABLE (PREFIX_0F10) },
2131 { PREFIX_TABLE (PREFIX_0F11) },
2132 { PREFIX_TABLE (PREFIX_0F12) },
2133 { MOD_TABLE (MOD_0F13) },
2134 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2135 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2136 { PREFIX_TABLE (PREFIX_0F16) },
2137 { MOD_TABLE (MOD_0F17) },
2138 /* 18 */
2139 { REG_TABLE (REG_0F18) },
2140 { "nopQ", { Ev }, 0 },
2141 { PREFIX_TABLE (PREFIX_0F1A) },
2142 { PREFIX_TABLE (PREFIX_0F1B) },
2143 { PREFIX_TABLE (PREFIX_0F1C) },
2144 { "nopQ", { Ev }, 0 },
2145 { PREFIX_TABLE (PREFIX_0F1E) },
2146 { "nopQ", { Ev }, 0 },
2147 /* 20 */
2148 { "movZ", { Em, Cm }, 0 },
2149 { "movZ", { Em, Dm }, 0 },
2150 { "movZ", { Cm, Em }, 0 },
2151 { "movZ", { Dm, Em }, 0 },
2152 { X86_64_TABLE (X86_64_0F24) },
2153 { Bad_Opcode },
2154 { X86_64_TABLE (X86_64_0F26) },
2155 { Bad_Opcode },
2156 /* 28 */
2157 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2158 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2159 { PREFIX_TABLE (PREFIX_0F2A) },
2160 { PREFIX_TABLE (PREFIX_0F2B) },
2161 { PREFIX_TABLE (PREFIX_0F2C) },
2162 { PREFIX_TABLE (PREFIX_0F2D) },
2163 { PREFIX_TABLE (PREFIX_0F2E) },
2164 { PREFIX_TABLE (PREFIX_0F2F) },
2165 /* 30 */
2166 { "wrmsr", { XX }, 0 },
2167 { "rdtsc", { XX }, 0 },
2168 { "rdmsr", { XX }, 0 },
2169 { "rdpmc", { XX }, 0 },
2170 { "sysenter", { SEP }, 0 },
2171 { "sysexit%LQ", { SEP }, 0 },
2172 { Bad_Opcode },
2173 { "getsec", { XX }, 0 },
2174 /* 38 */
2175 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2176 { Bad_Opcode },
2177 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2178 { Bad_Opcode },
2179 { Bad_Opcode },
2180 { Bad_Opcode },
2181 { Bad_Opcode },
2182 { Bad_Opcode },
2183 /* 40 */
2184 { "cmovoS", { Gv, Ev }, 0 },
2185 { "cmovnoS", { Gv, Ev }, 0 },
2186 { "cmovbS", { Gv, Ev }, 0 },
2187 { "cmovaeS", { Gv, Ev }, 0 },
2188 { "cmoveS", { Gv, Ev }, 0 },
2189 { "cmovneS", { Gv, Ev }, 0 },
2190 { "cmovbeS", { Gv, Ev }, 0 },
2191 { "cmovaS", { Gv, Ev }, 0 },
2192 /* 48 */
2193 { "cmovsS", { Gv, Ev }, 0 },
2194 { "cmovnsS", { Gv, Ev }, 0 },
2195 { "cmovpS", { Gv, Ev }, 0 },
2196 { "cmovnpS", { Gv, Ev }, 0 },
2197 { "cmovlS", { Gv, Ev }, 0 },
2198 { "cmovgeS", { Gv, Ev }, 0 },
2199 { "cmovleS", { Gv, Ev }, 0 },
2200 { "cmovgS", { Gv, Ev }, 0 },
2201 /* 50 */
2202 { MOD_TABLE (MOD_0F50) },
2203 { PREFIX_TABLE (PREFIX_0F51) },
2204 { PREFIX_TABLE (PREFIX_0F52) },
2205 { PREFIX_TABLE (PREFIX_0F53) },
2206 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2207 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2208 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2209 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2210 /* 58 */
2211 { PREFIX_TABLE (PREFIX_0F58) },
2212 { PREFIX_TABLE (PREFIX_0F59) },
2213 { PREFIX_TABLE (PREFIX_0F5A) },
2214 { PREFIX_TABLE (PREFIX_0F5B) },
2215 { PREFIX_TABLE (PREFIX_0F5C) },
2216 { PREFIX_TABLE (PREFIX_0F5D) },
2217 { PREFIX_TABLE (PREFIX_0F5E) },
2218 { PREFIX_TABLE (PREFIX_0F5F) },
2219 /* 60 */
2220 { PREFIX_TABLE (PREFIX_0F60) },
2221 { PREFIX_TABLE (PREFIX_0F61) },
2222 { PREFIX_TABLE (PREFIX_0F62) },
2223 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2224 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
2225 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
2226 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
2227 { "packuswb", { MX, EM }, PREFIX_OPCODE },
2228 /* 68 */
2229 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
2230 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
2231 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
2232 { "packssdw", { MX, EM }, PREFIX_OPCODE },
2233 { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2234 { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2235 { "movK", { MX, Edq }, PREFIX_OPCODE },
2236 { PREFIX_TABLE (PREFIX_0F6F) },
2237 /* 70 */
2238 { PREFIX_TABLE (PREFIX_0F70) },
2239 { MOD_TABLE (MOD_0F71) },
2240 { MOD_TABLE (MOD_0F72) },
2241 { MOD_TABLE (MOD_0F73) },
2242 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
2243 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
2244 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
2245 { "emms", { XX }, PREFIX_OPCODE },
2246 /* 78 */
2247 { PREFIX_TABLE (PREFIX_0F78) },
2248 { PREFIX_TABLE (PREFIX_0F79) },
2249 { Bad_Opcode },
2250 { Bad_Opcode },
2251 { PREFIX_TABLE (PREFIX_0F7C) },
2252 { PREFIX_TABLE (PREFIX_0F7D) },
2253 { PREFIX_TABLE (PREFIX_0F7E) },
2254 { PREFIX_TABLE (PREFIX_0F7F) },
2255 /* 80 */
2256 { "joH", { Jv, BND, cond_jump_flag }, 0 },
2257 { "jnoH", { Jv, BND, cond_jump_flag }, 0 },
2258 { "jbH", { Jv, BND, cond_jump_flag }, 0 },
2259 { "jaeH", { Jv, BND, cond_jump_flag }, 0 },
2260 { "jeH", { Jv, BND, cond_jump_flag }, 0 },
2261 { "jneH", { Jv, BND, cond_jump_flag }, 0 },
2262 { "jbeH", { Jv, BND, cond_jump_flag }, 0 },
2263 { "jaH", { Jv, BND, cond_jump_flag }, 0 },
2264 /* 88 */
2265 { "jsH", { Jv, BND, cond_jump_flag }, 0 },
2266 { "jnsH", { Jv, BND, cond_jump_flag }, 0 },
2267 { "jpH", { Jv, BND, cond_jump_flag }, 0 },
2268 { "jnpH", { Jv, BND, cond_jump_flag }, 0 },
2269 { "jlH", { Jv, BND, cond_jump_flag }, 0 },
2270 { "jgeH", { Jv, BND, cond_jump_flag }, 0 },
2271 { "jleH", { Jv, BND, cond_jump_flag }, 0 },
2272 { "jgH", { Jv, BND, cond_jump_flag }, 0 },
2273 /* 90 */
2274 { "seto", { Eb }, 0 },
2275 { "setno", { Eb }, 0 },
2276 { "setb", { Eb }, 0 },
2277 { "setae", { Eb }, 0 },
2278 { "sete", { Eb }, 0 },
2279 { "setne", { Eb }, 0 },
2280 { "setbe", { Eb }, 0 },
2281 { "seta", { Eb }, 0 },
2282 /* 98 */
2283 { "sets", { Eb }, 0 },
2284 { "setns", { Eb }, 0 },
2285 { "setp", { Eb }, 0 },
2286 { "setnp", { Eb }, 0 },
2287 { "setl", { Eb }, 0 },
2288 { "setge", { Eb }, 0 },
2289 { "setle", { Eb }, 0 },
2290 { "setg", { Eb }, 0 },
2291 /* a0 */
2292 { "pushP", { fs }, 0 },
2293 { "popP", { fs }, 0 },
2294 { "cpuid", { XX }, 0 },
2295 { "btS", { Ev, Gv }, 0 },
2296 { "shldS", { Ev, Gv, Ib }, 0 },
2297 { "shldS", { Ev, Gv, CL }, 0 },
2298 { REG_TABLE (REG_0FA6) },
2299 { REG_TABLE (REG_0FA7) },
2300 /* a8 */
2301 { "pushP", { gs }, 0 },
2302 { "popP", { gs }, 0 },
2303 { "rsm", { XX }, 0 },
2304 { "btsS", { Evh1, Gv }, 0 },
2305 { "shrdS", { Ev, Gv, Ib }, 0 },
2306 { "shrdS", { Ev, Gv, CL }, 0 },
2307 { REG_TABLE (REG_0FAE) },
2308 { "imulS", { Gv, Ev }, 0 },
2309 /* b0 */
2310 { "cmpxchgB", { Ebh1, Gb }, 0 },
2311 { "cmpxchgS", { Evh1, Gv }, 0 },
2312 { MOD_TABLE (MOD_0FB2) },
2313 { "btrS", { Evh1, Gv }, 0 },
2314 { MOD_TABLE (MOD_0FB4) },
2315 { MOD_TABLE (MOD_0FB5) },
2316 { "movz{bR|x}", { Gv, Eb }, 0 },
2317 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2318 /* b8 */
2319 { PREFIX_TABLE (PREFIX_0FB8) },
2320 { "ud1S", { Gv, Ev }, 0 },
2321 { REG_TABLE (REG_0FBA) },
2322 { "btcS", { Evh1, Gv }, 0 },
2323 { PREFIX_TABLE (PREFIX_0FBC) },
2324 { PREFIX_TABLE (PREFIX_0FBD) },
2325 { "movs{bR|x}", { Gv, Eb }, 0 },
2326 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2327 /* c0 */
2328 { "xaddB", { Ebh1, Gb }, 0 },
2329 { "xaddS", { Evh1, Gv }, 0 },
2330 { PREFIX_TABLE (PREFIX_0FC2) },
2331 { MOD_TABLE (MOD_0FC3) },
2332 { "pinsrw", { MX, Edw, Ib }, PREFIX_OPCODE },
2333 { "pextrw", { Gd, MS, Ib }, PREFIX_OPCODE },
2334 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
2335 { REG_TABLE (REG_0FC7) },
2336 /* c8 */
2337 { "bswap", { RMeAX }, 0 },
2338 { "bswap", { RMeCX }, 0 },
2339 { "bswap", { RMeDX }, 0 },
2340 { "bswap", { RMeBX }, 0 },
2341 { "bswap", { RMeSP }, 0 },
2342 { "bswap", { RMeBP }, 0 },
2343 { "bswap", { RMeSI }, 0 },
2344 { "bswap", { RMeDI }, 0 },
2345 /* d0 */
2346 { PREFIX_TABLE (PREFIX_0FD0) },
2347 { "psrlw", { MX, EM }, PREFIX_OPCODE },
2348 { "psrld", { MX, EM }, PREFIX_OPCODE },
2349 { "psrlq", { MX, EM }, PREFIX_OPCODE },
2350 { "paddq", { MX, EM }, PREFIX_OPCODE },
2351 { "pmullw", { MX, EM }, PREFIX_OPCODE },
2352 { PREFIX_TABLE (PREFIX_0FD6) },
2353 { MOD_TABLE (MOD_0FD7) },
2354 /* d8 */
2355 { "psubusb", { MX, EM }, PREFIX_OPCODE },
2356 { "psubusw", { MX, EM }, PREFIX_OPCODE },
2357 { "pminub", { MX, EM }, PREFIX_OPCODE },
2358 { "pand", { MX, EM }, PREFIX_OPCODE },
2359 { "paddusb", { MX, EM }, PREFIX_OPCODE },
2360 { "paddusw", { MX, EM }, PREFIX_OPCODE },
2361 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
2362 { "pandn", { MX, EM }, PREFIX_OPCODE },
2363 /* e0 */
2364 { "pavgb", { MX, EM }, PREFIX_OPCODE },
2365 { "psraw", { MX, EM }, PREFIX_OPCODE },
2366 { "psrad", { MX, EM }, PREFIX_OPCODE },
2367 { "pavgw", { MX, EM }, PREFIX_OPCODE },
2368 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
2369 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
2370 { PREFIX_TABLE (PREFIX_0FE6) },
2371 { PREFIX_TABLE (PREFIX_0FE7) },
2372 /* e8 */
2373 { "psubsb", { MX, EM }, PREFIX_OPCODE },
2374 { "psubsw", { MX, EM }, PREFIX_OPCODE },
2375 { "pminsw", { MX, EM }, PREFIX_OPCODE },
2376 { "por", { MX, EM }, PREFIX_OPCODE },
2377 { "paddsb", { MX, EM }, PREFIX_OPCODE },
2378 { "paddsw", { MX, EM }, PREFIX_OPCODE },
2379 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
2380 { "pxor", { MX, EM }, PREFIX_OPCODE },
2381 /* f0 */
2382 { PREFIX_TABLE (PREFIX_0FF0) },
2383 { "psllw", { MX, EM }, PREFIX_OPCODE },
2384 { "pslld", { MX, EM }, PREFIX_OPCODE },
2385 { "psllq", { MX, EM }, PREFIX_OPCODE },
2386 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
2387 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
2388 { "psadbw", { MX, EM }, PREFIX_OPCODE },
2389 { PREFIX_TABLE (PREFIX_0FF7) },
2390 /* f8 */
2391 { "psubb", { MX, EM }, PREFIX_OPCODE },
2392 { "psubw", { MX, EM }, PREFIX_OPCODE },
2393 { "psubd", { MX, EM }, PREFIX_OPCODE },
2394 { "psubq", { MX, EM }, PREFIX_OPCODE },
2395 { "paddb", { MX, EM }, PREFIX_OPCODE },
2396 { "paddw", { MX, EM }, PREFIX_OPCODE },
2397 { "paddd", { MX, EM }, PREFIX_OPCODE },
2398 { "ud0S", { Gv, Ev }, 0 },
2399 };
2400
2401 static const bool onebyte_has_modrm[256] = {
2402 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2403 /* ------------------------------- */
2404 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2405 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2406 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2407 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2408 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2409 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2410 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2411 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2412 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2413 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2414 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2415 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2416 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2417 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2418 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2419 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2420 /* ------------------------------- */
2421 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2422 };
2423
2424 static const bool twobyte_has_modrm[256] = {
2425 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2426 /* ------------------------------- */
2427 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2428 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2429 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2430 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2431 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2432 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2433 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2434 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2435 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2436 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2437 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2438 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2439 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2440 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2441 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2442 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2443 /* ------------------------------- */
2444 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2445 };
2446
2447
2448 struct op
2449 {
2450 const char *name;
2451 unsigned int len;
2452 };
2453
2454 /* If we are accessing mod/rm/reg without need_modrm set, then the
2455 values are stale. Hitting this abort likely indicates that you
2456 need to update onebyte_has_modrm or twobyte_has_modrm. */
2457 #define MODRM_CHECK if (!ins->need_modrm) abort ()
2458
2459 static const char intel_index16[][6] = {
2460 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2461 };
2462
2463 static const char att_names64[][8] = {
2464 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2465 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2466 };
2467 static const char att_names32[][8] = {
2468 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2469 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2470 };
2471 static const char att_names16[][8] = {
2472 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2473 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2474 };
2475 static const char att_names8[][8] = {
2476 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2477 };
2478 static const char att_names8rex[][8] = {
2479 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2480 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2481 };
2482 static const char att_names_seg[][4] = {
2483 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2484 };
2485 static const char att_index64[] = "%riz";
2486 static const char att_index32[] = "%eiz";
2487 static const char att_index16[][8] = {
2488 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2489 };
2490
2491 static const char att_names_mm[][8] = {
2492 "%mm0", "%mm1", "%mm2", "%mm3",
2493 "%mm4", "%mm5", "%mm6", "%mm7"
2494 };
2495
2496 static const char att_names_bnd[][8] = {
2497 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2498 };
2499
2500 static const char att_names_xmm[][8] = {
2501 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2502 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2503 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2504 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2505 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2506 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2507 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2508 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2509 };
2510
2511 static const char att_names_ymm[][8] = {
2512 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2513 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2514 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2515 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2516 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2517 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2518 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2519 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2520 };
2521
2522 static const char att_names_zmm[][8] = {
2523 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2524 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2525 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2526 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2527 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2528 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2529 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2530 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2531 };
2532
2533 static const char att_names_tmm[][8] = {
2534 "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2535 "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2536 };
2537
2538 static const char att_names_mask[][8] = {
2539 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2540 };
2541
2542 static const char *const names_rounding[] =
2543 {
2544 "{rn-",
2545 "{rd-",
2546 "{ru-",
2547 "{rz-"
2548 };
2549
2550 static const struct dis386 reg_table[][8] = {
2551 /* REG_80 */
2552 {
2553 { "addA", { Ebh1, Ib }, 0 },
2554 { "orA", { Ebh1, Ib }, 0 },
2555 { "adcA", { Ebh1, Ib }, 0 },
2556 { "sbbA", { Ebh1, Ib }, 0 },
2557 { "andA", { Ebh1, Ib }, 0 },
2558 { "subA", { Ebh1, Ib }, 0 },
2559 { "xorA", { Ebh1, Ib }, 0 },
2560 { "cmpA", { Eb, Ib }, 0 },
2561 },
2562 /* REG_81 */
2563 {
2564 { "addQ", { Evh1, Iv }, 0 },
2565 { "orQ", { Evh1, Iv }, 0 },
2566 { "adcQ", { Evh1, Iv }, 0 },
2567 { "sbbQ", { Evh1, Iv }, 0 },
2568 { "andQ", { Evh1, Iv }, 0 },
2569 { "subQ", { Evh1, Iv }, 0 },
2570 { "xorQ", { Evh1, Iv }, 0 },
2571 { "cmpQ", { Ev, Iv }, 0 },
2572 },
2573 /* REG_83 */
2574 {
2575 { "addQ", { Evh1, sIb }, 0 },
2576 { "orQ", { Evh1, sIb }, 0 },
2577 { "adcQ", { Evh1, sIb }, 0 },
2578 { "sbbQ", { Evh1, sIb }, 0 },
2579 { "andQ", { Evh1, sIb }, 0 },
2580 { "subQ", { Evh1, sIb }, 0 },
2581 { "xorQ", { Evh1, sIb }, 0 },
2582 { "cmpQ", { Ev, sIb }, 0 },
2583 },
2584 /* REG_8F */
2585 {
2586 { "pop{P|}", { stackEv }, 0 },
2587 { XOP_8F_TABLE (XOP_09) },
2588 { Bad_Opcode },
2589 { Bad_Opcode },
2590 { Bad_Opcode },
2591 { XOP_8F_TABLE (XOP_09) },
2592 },
2593 /* REG_C0 */
2594 {
2595 { "rolA", { Eb, Ib }, 0 },
2596 { "rorA", { Eb, Ib }, 0 },
2597 { "rclA", { Eb, Ib }, 0 },
2598 { "rcrA", { Eb, Ib }, 0 },
2599 { "shlA", { Eb, Ib }, 0 },
2600 { "shrA", { Eb, Ib }, 0 },
2601 { "shlA", { Eb, Ib }, 0 },
2602 { "sarA", { Eb, Ib }, 0 },
2603 },
2604 /* REG_C1 */
2605 {
2606 { "rolQ", { Ev, Ib }, 0 },
2607 { "rorQ", { Ev, Ib }, 0 },
2608 { "rclQ", { Ev, Ib }, 0 },
2609 { "rcrQ", { Ev, Ib }, 0 },
2610 { "shlQ", { Ev, Ib }, 0 },
2611 { "shrQ", { Ev, Ib }, 0 },
2612 { "shlQ", { Ev, Ib }, 0 },
2613 { "sarQ", { Ev, Ib }, 0 },
2614 },
2615 /* REG_C6 */
2616 {
2617 { "movA", { Ebh3, Ib }, 0 },
2618 { Bad_Opcode },
2619 { Bad_Opcode },
2620 { Bad_Opcode },
2621 { Bad_Opcode },
2622 { Bad_Opcode },
2623 { Bad_Opcode },
2624 { MOD_TABLE (MOD_C6_REG_7) },
2625 },
2626 /* REG_C7 */
2627 {
2628 { "movQ", { Evh3, Iv }, 0 },
2629 { Bad_Opcode },
2630 { Bad_Opcode },
2631 { Bad_Opcode },
2632 { Bad_Opcode },
2633 { Bad_Opcode },
2634 { Bad_Opcode },
2635 { MOD_TABLE (MOD_C7_REG_7) },
2636 },
2637 /* REG_D0 */
2638 {
2639 { "rolA", { Eb, I1 }, 0 },
2640 { "rorA", { Eb, I1 }, 0 },
2641 { "rclA", { Eb, I1 }, 0 },
2642 { "rcrA", { Eb, I1 }, 0 },
2643 { "shlA", { Eb, I1 }, 0 },
2644 { "shrA", { Eb, I1 }, 0 },
2645 { "shlA", { Eb, I1 }, 0 },
2646 { "sarA", { Eb, I1 }, 0 },
2647 },
2648 /* REG_D1 */
2649 {
2650 { "rolQ", { Ev, I1 }, 0 },
2651 { "rorQ", { Ev, I1 }, 0 },
2652 { "rclQ", { Ev, I1 }, 0 },
2653 { "rcrQ", { Ev, I1 }, 0 },
2654 { "shlQ", { Ev, I1 }, 0 },
2655 { "shrQ", { Ev, I1 }, 0 },
2656 { "shlQ", { Ev, I1 }, 0 },
2657 { "sarQ", { Ev, I1 }, 0 },
2658 },
2659 /* REG_D2 */
2660 {
2661 { "rolA", { Eb, CL }, 0 },
2662 { "rorA", { Eb, CL }, 0 },
2663 { "rclA", { Eb, CL }, 0 },
2664 { "rcrA", { Eb, CL }, 0 },
2665 { "shlA", { Eb, CL }, 0 },
2666 { "shrA", { Eb, CL }, 0 },
2667 { "shlA", { Eb, CL }, 0 },
2668 { "sarA", { Eb, CL }, 0 },
2669 },
2670 /* REG_D3 */
2671 {
2672 { "rolQ", { Ev, CL }, 0 },
2673 { "rorQ", { Ev, CL }, 0 },
2674 { "rclQ", { Ev, CL }, 0 },
2675 { "rcrQ", { Ev, CL }, 0 },
2676 { "shlQ", { Ev, CL }, 0 },
2677 { "shrQ", { Ev, CL }, 0 },
2678 { "shlQ", { Ev, CL }, 0 },
2679 { "sarQ", { Ev, CL }, 0 },
2680 },
2681 /* REG_F6 */
2682 {
2683 { "testA", { Eb, Ib }, 0 },
2684 { "testA", { Eb, Ib }, 0 },
2685 { "notA", { Ebh1 }, 0 },
2686 { "negA", { Ebh1 }, 0 },
2687 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
2688 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
2689 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
2690 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
2691 },
2692 /* REG_F7 */
2693 {
2694 { "testQ", { Ev, Iv }, 0 },
2695 { "testQ", { Ev, Iv }, 0 },
2696 { "notQ", { Evh1 }, 0 },
2697 { "negQ", { Evh1 }, 0 },
2698 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
2699 { "imulQ", { Ev }, 0 },
2700 { "divQ", { Ev }, 0 },
2701 { "idivQ", { Ev }, 0 },
2702 },
2703 /* REG_FE */
2704 {
2705 { "incA", { Ebh1 }, 0 },
2706 { "decA", { Ebh1 }, 0 },
2707 },
2708 /* REG_FF */
2709 {
2710 { "incQ", { Evh1 }, 0 },
2711 { "decQ", { Evh1 }, 0 },
2712 { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2713 { MOD_TABLE (MOD_FF_REG_3) },
2714 { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2715 { MOD_TABLE (MOD_FF_REG_5) },
2716 { "push{P|}", { stackEv }, 0 },
2717 { Bad_Opcode },
2718 },
2719 /* REG_0F00 */
2720 {
2721 { "sldtD", { Sv }, 0 },
2722 { "strD", { Sv }, 0 },
2723 { "lldt", { Ew }, 0 },
2724 { "ltr", { Ew }, 0 },
2725 { "verr", { Ew }, 0 },
2726 { "verw", { Ew }, 0 },
2727 { X86_64_TABLE (X86_64_0F00_REG_6) },
2728 { Bad_Opcode },
2729 },
2730 /* REG_0F01 */
2731 {
2732 { MOD_TABLE (MOD_0F01_REG_0) },
2733 { MOD_TABLE (MOD_0F01_REG_1) },
2734 { MOD_TABLE (MOD_0F01_REG_2) },
2735 { MOD_TABLE (MOD_0F01_REG_3) },
2736 { "smswD", { Sv }, 0 },
2737 { MOD_TABLE (MOD_0F01_REG_5) },
2738 { "lmsw", { Ew }, 0 },
2739 { MOD_TABLE (MOD_0F01_REG_7) },
2740 },
2741 /* REG_0F0D */
2742 {
2743 { "prefetch", { Mb }, 0 },
2744 { "prefetchw", { Mb }, 0 },
2745 { "prefetchwt1", { Mb }, 0 },
2746 { "prefetch", { Mb }, 0 },
2747 { "prefetch", { Mb }, 0 },
2748 { "prefetch", { Mb }, 0 },
2749 { "prefetch", { Mb }, 0 },
2750 { "prefetch", { Mb }, 0 },
2751 },
2752 /* REG_0F18 */
2753 {
2754 { MOD_TABLE (MOD_0F18_REG_0) },
2755 { MOD_TABLE (MOD_0F18_REG_1) },
2756 { MOD_TABLE (MOD_0F18_REG_2) },
2757 { MOD_TABLE (MOD_0F18_REG_3) },
2758 { "nopQ", { Ev }, 0 },
2759 { "nopQ", { Ev }, 0 },
2760 { MOD_TABLE (MOD_0F18_REG_6) },
2761 { MOD_TABLE (MOD_0F18_REG_7) },
2762 },
2763 /* REG_0F1C_P_0_MOD_0 */
2764 {
2765 { "cldemote", { Mb }, 0 },
2766 { "nopQ", { Ev }, 0 },
2767 { "nopQ", { Ev }, 0 },
2768 { "nopQ", { Ev }, 0 },
2769 { "nopQ", { Ev }, 0 },
2770 { "nopQ", { Ev }, 0 },
2771 { "nopQ", { Ev }, 0 },
2772 { "nopQ", { Ev }, 0 },
2773 },
2774 /* REG_0F1E_P_1_MOD_3 */
2775 {
2776 { "nopQ", { Ev }, PREFIX_IGNORED },
2777 { "rdsspK", { Edq }, 0 },
2778 { "nopQ", { Ev }, PREFIX_IGNORED },
2779 { "nopQ", { Ev }, PREFIX_IGNORED },
2780 { "nopQ", { Ev }, PREFIX_IGNORED },
2781 { "nopQ", { Ev }, PREFIX_IGNORED },
2782 { "nopQ", { Ev }, PREFIX_IGNORED },
2783 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2784 },
2785 /* REG_0F38D8_PREFIX_1 */
2786 {
2787 { "aesencwide128kl", { M }, 0 },
2788 { "aesdecwide128kl", { M }, 0 },
2789 { "aesencwide256kl", { M }, 0 },
2790 { "aesdecwide256kl", { M }, 0 },
2791 },
2792 /* REG_0F3A0F_PREFIX_1_MOD_3 */
2793 {
2794 { RM_TABLE (RM_0F3A0F_P_1_MOD_3_REG_0) },
2795 },
2796 /* REG_0F71_MOD_0 */
2797 {
2798 { Bad_Opcode },
2799 { Bad_Opcode },
2800 { "psrlw", { MS, Ib }, PREFIX_OPCODE },
2801 { Bad_Opcode },
2802 { "psraw", { MS, Ib }, PREFIX_OPCODE },
2803 { Bad_Opcode },
2804 { "psllw", { MS, Ib }, PREFIX_OPCODE },
2805 },
2806 /* REG_0F72_MOD_0 */
2807 {
2808 { Bad_Opcode },
2809 { Bad_Opcode },
2810 { "psrld", { MS, Ib }, PREFIX_OPCODE },
2811 { Bad_Opcode },
2812 { "psrad", { MS, Ib }, PREFIX_OPCODE },
2813 { Bad_Opcode },
2814 { "pslld", { MS, Ib }, PREFIX_OPCODE },
2815 },
2816 /* REG_0F73_MOD_0 */
2817 {
2818 { Bad_Opcode },
2819 { Bad_Opcode },
2820 { "psrlq", { MS, Ib }, PREFIX_OPCODE },
2821 { "psrldq", { XS, Ib }, PREFIX_DATA },
2822 { Bad_Opcode },
2823 { Bad_Opcode },
2824 { "psllq", { MS, Ib }, PREFIX_OPCODE },
2825 { "pslldq", { XS, Ib }, PREFIX_DATA },
2826 },
2827 /* REG_0FA6 */
2828 {
2829 { "montmul", { { OP_0f07, 0 } }, 0 },
2830 { "xsha1", { { OP_0f07, 0 } }, 0 },
2831 { "xsha256", { { OP_0f07, 0 } }, 0 },
2832 },
2833 /* REG_0FA7 */
2834 {
2835 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
2836 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
2837 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
2838 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
2839 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
2840 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
2841 },
2842 /* REG_0FAE */
2843 {
2844 { MOD_TABLE (MOD_0FAE_REG_0) },
2845 { MOD_TABLE (MOD_0FAE_REG_1) },
2846 { MOD_TABLE (MOD_0FAE_REG_2) },
2847 { MOD_TABLE (MOD_0FAE_REG_3) },
2848 { MOD_TABLE (MOD_0FAE_REG_4) },
2849 { MOD_TABLE (MOD_0FAE_REG_5) },
2850 { MOD_TABLE (MOD_0FAE_REG_6) },
2851 { MOD_TABLE (MOD_0FAE_REG_7) },
2852 },
2853 /* REG_0FBA */
2854 {
2855 { Bad_Opcode },
2856 { Bad_Opcode },
2857 { Bad_Opcode },
2858 { Bad_Opcode },
2859 { "btQ", { Ev, Ib }, 0 },
2860 { "btsQ", { Evh1, Ib }, 0 },
2861 { "btrQ", { Evh1, Ib }, 0 },
2862 { "btcQ", { Evh1, Ib }, 0 },
2863 },
2864 /* REG_0FC7 */
2865 {
2866 { Bad_Opcode },
2867 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
2868 { Bad_Opcode },
2869 { MOD_TABLE (MOD_0FC7_REG_3) },
2870 { MOD_TABLE (MOD_0FC7_REG_4) },
2871 { MOD_TABLE (MOD_0FC7_REG_5) },
2872 { MOD_TABLE (MOD_0FC7_REG_6) },
2873 { MOD_TABLE (MOD_0FC7_REG_7) },
2874 },
2875 /* REG_VEX_0F71_M_0 */
2876 {
2877 { Bad_Opcode },
2878 { Bad_Opcode },
2879 { "vpsrlw", { Vex, XS, Ib }, PREFIX_DATA },
2880 { Bad_Opcode },
2881 { "vpsraw", { Vex, XS, Ib }, PREFIX_DATA },
2882 { Bad_Opcode },
2883 { "vpsllw", { Vex, XS, Ib }, PREFIX_DATA },
2884 },
2885 /* REG_VEX_0F72_M_0 */
2886 {
2887 { Bad_Opcode },
2888 { Bad_Opcode },
2889 { "vpsrld", { Vex, XS, Ib }, PREFIX_DATA },
2890 { Bad_Opcode },
2891 { "vpsrad", { Vex, XS, Ib }, PREFIX_DATA },
2892 { Bad_Opcode },
2893 { "vpslld", { Vex, XS, Ib }, PREFIX_DATA },
2894 },
2895 /* REG_VEX_0F73_M_0 */
2896 {
2897 { Bad_Opcode },
2898 { Bad_Opcode },
2899 { "vpsrlq", { Vex, XS, Ib }, PREFIX_DATA },
2900 { "vpsrldq", { Vex, XS, Ib }, PREFIX_DATA },
2901 { Bad_Opcode },
2902 { Bad_Opcode },
2903 { "vpsllq", { Vex, XS, Ib }, PREFIX_DATA },
2904 { "vpslldq", { Vex, XS, Ib }, PREFIX_DATA },
2905 },
2906 /* REG_VEX_0FAE */
2907 {
2908 { Bad_Opcode },
2909 { Bad_Opcode },
2910 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
2911 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
2912 },
2913 /* REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0 */
2914 {
2915 { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0) },
2916 },
2917 /* REG_VEX_0F38F3_L_0 */
2918 {
2919 { Bad_Opcode },
2920 { "blsrS", { VexGdq, Edq }, PREFIX_OPCODE },
2921 { "blsmskS", { VexGdq, Edq }, PREFIX_OPCODE },
2922 { "blsiS", { VexGdq, Edq }, PREFIX_OPCODE },
2923 },
2924 /* REG_XOP_09_01_L_0 */
2925 {
2926 { Bad_Opcode },
2927 { "blcfill", { VexGdq, Edq }, 0 },
2928 { "blsfill", { VexGdq, Edq }, 0 },
2929 { "blcs", { VexGdq, Edq }, 0 },
2930 { "tzmsk", { VexGdq, Edq }, 0 },
2931 { "blcic", { VexGdq, Edq }, 0 },
2932 { "blsic", { VexGdq, Edq }, 0 },
2933 { "t1mskc", { VexGdq, Edq }, 0 },
2934 },
2935 /* REG_XOP_09_02_L_0 */
2936 {
2937 { Bad_Opcode },
2938 { "blcmsk", { VexGdq, Edq }, 0 },
2939 { Bad_Opcode },
2940 { Bad_Opcode },
2941 { Bad_Opcode },
2942 { Bad_Opcode },
2943 { "blci", { VexGdq, Edq }, 0 },
2944 },
2945 /* REG_XOP_09_12_M_1_L_0 */
2946 {
2947 { "llwpcb", { Edq }, 0 },
2948 { "slwpcb", { Edq }, 0 },
2949 },
2950 /* REG_XOP_0A_12_L_0 */
2951 {
2952 { "lwpins", { VexGdq, Ed, Id }, 0 },
2953 { "lwpval", { VexGdq, Ed, Id }, 0 },
2954 },
2955
2956 #include "i386-dis-evex-reg.h"
2957 };
2958
2959 static const struct dis386 prefix_table[][4] = {
2960 /* PREFIX_90 */
2961 {
2962 { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
2963 { "pause", { XX }, 0 },
2964 { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
2965 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
2966 },
2967
2968 /* PREFIX_0F00_REG_6_X86_64 */
2969 {
2970 { Bad_Opcode },
2971 { Bad_Opcode },
2972 { Bad_Opcode },
2973 { "lkgs", { Ew }, 0 },
2974 },
2975
2976 /* PREFIX_0F01_REG_0_MOD_3_RM_6 */
2977 {
2978 { "wrmsrns", { Skip_MODRM }, 0 },
2979 { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_1) },
2980 { Bad_Opcode },
2981 { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_3) },
2982 },
2983
2984 /* PREFIX_0F01_REG_1_RM_2 */
2985 {
2986 { "clac", { Skip_MODRM }, 0 },
2987 { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_1) },
2988 { Bad_Opcode },
2989 { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_3)},
2990 },
2991
2992 /* PREFIX_0F01_REG_1_RM_4 */
2993 {
2994 { Bad_Opcode },
2995 { Bad_Opcode },
2996 { "tdcall", { Skip_MODRM }, 0 },
2997 { Bad_Opcode },
2998 },
2999
3000 /* PREFIX_0F01_REG_1_RM_5 */
3001 {
3002 { Bad_Opcode },
3003 { Bad_Opcode },
3004 { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
3005 { Bad_Opcode },
3006 },
3007
3008 /* PREFIX_0F01_REG_1_RM_6 */
3009 {
3010 { Bad_Opcode },
3011 { Bad_Opcode },
3012 { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
3013 { Bad_Opcode },
3014 },
3015
3016 /* PREFIX_0F01_REG_1_RM_7 */
3017 {
3018 { "encls", { Skip_MODRM }, 0 },
3019 { Bad_Opcode },
3020 { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
3021 { Bad_Opcode },
3022 },
3023
3024 /* PREFIX_0F01_REG_3_RM_1 */
3025 {
3026 { "vmmcall", { Skip_MODRM }, 0 },
3027 { "vmgexit", { Skip_MODRM }, 0 },
3028 { Bad_Opcode },
3029 { "vmgexit", { Skip_MODRM }, 0 },
3030 },
3031
3032 /* PREFIX_0F01_REG_5_MOD_0 */
3033 {
3034 { Bad_Opcode },
3035 { "rstorssp", { Mq }, PREFIX_OPCODE },
3036 },
3037
3038 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3039 {
3040 { "serialize", { Skip_MODRM }, PREFIX_OPCODE },
3041 { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
3042 { Bad_Opcode },
3043 { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE },
3044 },
3045
3046 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3047 {
3048 { Bad_Opcode },
3049 { Bad_Opcode },
3050 { Bad_Opcode },
3051 { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE },
3052 },
3053
3054 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3055 {
3056 { Bad_Opcode },
3057 { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
3058 },
3059
3060 /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3061 {
3062 { Bad_Opcode },
3063 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) },
3064 },
3065
3066 /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3067 {
3068 { Bad_Opcode },
3069 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) },
3070 },
3071
3072 /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3073 {
3074 { "rdpkru", { Skip_MODRM }, 0 },
3075 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) },
3076 },
3077
3078 /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3079 {
3080 { "wrpkru", { Skip_MODRM }, 0 },
3081 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) },
3082 },
3083
3084 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3085 {
3086 { "monitorx", { { OP_Monitor, 0 } }, 0 },
3087 { "mcommit", { Skip_MODRM }, 0 },
3088 },
3089
3090 /* PREFIX_0F01_REG_7_MOD_3_RM_5 */
3091 {
3092 { "rdpru", { Skip_MODRM }, 0 },
3093 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1) },
3094 },
3095
3096 /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3097 {
3098 { "invlpgb", { Skip_MODRM }, 0 },
3099 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) },
3100 { Bad_Opcode },
3101 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) },
3102 },
3103
3104 /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3105 {
3106 { "tlbsync", { Skip_MODRM }, 0 },
3107 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) },
3108 { Bad_Opcode },
3109 { "pvalidate", { Skip_MODRM }, 0 },
3110 },
3111
3112 /* PREFIX_0F09 */
3113 {
3114 { "wbinvd", { XX }, 0 },
3115 { "wbnoinvd", { XX }, 0 },
3116 },
3117
3118 /* PREFIX_0F10 */
3119 {
3120 { "%XEVmovupX", { XM, EXEvexXNoBcst }, 0 },
3121 { "%XEVmovs%XS", { XMScalar, VexScalarR, EXd }, 0 },
3122 { "%XEVmovupX", { XM, EXEvexXNoBcst }, 0 },
3123 { "%XEVmovs%XD", { XMScalar, VexScalarR, EXq }, 0 },
3124 },
3125
3126 /* PREFIX_0F11 */
3127 {
3128 { "%XEVmovupX", { EXxS, XM }, 0 },
3129 { "%XEVmovs%XS", { EXdS, VexScalarR, XMScalar }, 0 },
3130 { "%XEVmovupX", { EXxS, XM }, 0 },
3131 { "%XEVmovs%XD", { EXqS, VexScalarR, XMScalar }, 0 },
3132 },
3133
3134 /* PREFIX_0F12 */
3135 {
3136 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3137 { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3138 { MOD_TABLE (MOD_0F12_PREFIX_2) },
3139 { "movddup", { XM, EXq }, PREFIX_OPCODE },
3140 },
3141
3142 /* PREFIX_0F16 */
3143 {
3144 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3145 { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3146 { MOD_TABLE (MOD_0F16_PREFIX_2) },
3147 },
3148
3149 /* PREFIX_0F18_REG_6_MOD_0_X86_64 */
3150 {
3151 { "prefetchit1", { { PREFETCHI_Fixup, b_mode } }, 0 },
3152 { "nopQ", { Ev }, 0 },
3153 { "nopQ", { Ev }, 0 },
3154 { "nopQ", { Ev }, 0 },
3155 },
3156
3157 /* PREFIX_0F18_REG_7_MOD_0_X86_64 */
3158 {
3159 { "prefetchit0", { { PREFETCHI_Fixup, b_mode } }, 0 },
3160 { "nopQ", { Ev }, 0 },
3161 { "nopQ", { Ev }, 0 },
3162 { "nopQ", { Ev }, 0 },
3163 },
3164
3165 /* PREFIX_0F1A */
3166 {
3167 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3168 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3169 { "bndmov", { Gbnd, Ebnd }, 0 },
3170 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3171 },
3172
3173 /* PREFIX_0F1B */
3174 {
3175 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3176 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3177 { "bndmov", { EbndS, Gbnd }, 0 },
3178 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3179 },
3180
3181 /* PREFIX_0F1C */
3182 {
3183 { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3184 { "nopQ", { Ev }, PREFIX_IGNORED },
3185 { "nopQ", { Ev }, 0 },
3186 { "nopQ", { Ev }, PREFIX_IGNORED },
3187 },
3188
3189 /* PREFIX_0F1E */
3190 {
3191 { "nopQ", { Ev }, 0 },
3192 { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3193 { "nopQ", { Ev }, 0 },
3194 { NULL, { XX }, PREFIX_IGNORED },
3195 },
3196
3197 /* PREFIX_0F2A */
3198 {
3199 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3200 { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3201 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3202 { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3203 },
3204
3205 /* PREFIX_0F2B */
3206 {
3207 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3208 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3209 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3210 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3211 },
3212
3213 /* PREFIX_0F2C */
3214 {
3215 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3216 { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3217 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3218 { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3219 },
3220
3221 /* PREFIX_0F2D */
3222 {
3223 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3224 { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3225 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3226 { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3227 },
3228
3229 /* PREFIX_0F2E */
3230 {
3231 { "%XEVucomisYX", { XMScalar, EXd, EXxEVexS }, 0 },
3232 { Bad_Opcode },
3233 { "%XEVucomisYX", { XMScalar, EXq, EXxEVexS }, 0 },
3234 },
3235
3236 /* PREFIX_0F2F */
3237 {
3238 { "%XEVcomisYX", { XMScalar, EXd, EXxEVexS }, 0 },
3239 { Bad_Opcode },
3240 { "%XEVcomisYX", { XMScalar, EXq, EXxEVexS }, 0 },
3241 },
3242
3243 /* PREFIX_0F51 */
3244 {
3245 { "%XEVsqrtpX", { XM, EXx, EXxEVexR }, 0 },
3246 { "%XEVsqrts%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3247 { "%XEVsqrtpX", { XM, EXx, EXxEVexR }, 0 },
3248 { "%XEVsqrts%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3249 },
3250
3251 /* PREFIX_0F52 */
3252 {
3253 { "Vrsqrtps", { XM, EXx }, 0 },
3254 { "Vrsqrtss", { XMScalar, VexScalar, EXd }, 0 },
3255 },
3256
3257 /* PREFIX_0F53 */
3258 {
3259 { "Vrcpps", { XM, EXx }, 0 },
3260 { "Vrcpss", { XMScalar, VexScalar, EXd }, 0 },
3261 },
3262
3263 /* PREFIX_0F58 */
3264 {
3265 { "%XEVaddpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3266 { "%XEVadds%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3267 { "%XEVaddpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3268 { "%XEVadds%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3269 },
3270
3271 /* PREFIX_0F59 */
3272 {
3273 { "%XEVmulpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3274 { "%XEVmuls%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3275 { "%XEVmulpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3276 { "%XEVmuls%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3277 },
3278
3279 /* PREFIX_0F5A */
3280 {
3281 { "%XEVcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
3282 { "%XEVcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3283 { "%XEVcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
3284 { "%XEVcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3285 },
3286
3287 /* PREFIX_0F5B */
3288 {
3289 { "Vcvtdq2ps", { XM, EXx }, 0 },
3290 { "Vcvttps2dq", { XM, EXx }, 0 },
3291 { "Vcvtps2dq", { XM, EXx }, 0 },
3292 },
3293
3294 /* PREFIX_0F5C */
3295 {
3296 { "%XEVsubpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3297 { "%XEVsubs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3298 { "%XEVsubpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3299 { "%XEVsubs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3300 },
3301
3302 /* PREFIX_0F5D */
3303 {
3304 { "%XEVminpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3305 { "%XEVmins%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3306 { "%XEVminpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3307 { "%XEVmins%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3308 },
3309
3310 /* PREFIX_0F5E */
3311 {
3312 { "%XEVdivpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3313 { "%XEVdivs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3314 { "%XEVdivpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3315 { "%XEVdivs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3316 },
3317
3318 /* PREFIX_0F5F */
3319 {
3320 { "%XEVmaxpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3321 { "%XEVmaxs%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3322 { "%XEVmaxpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3323 { "%XEVmaxs%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3324 },
3325
3326 /* PREFIX_0F60 */
3327 {
3328 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3329 { Bad_Opcode },
3330 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3331 },
3332
3333 /* PREFIX_0F61 */
3334 {
3335 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3336 { Bad_Opcode },
3337 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3338 },
3339
3340 /* PREFIX_0F62 */
3341 {
3342 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3343 { Bad_Opcode },
3344 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3345 },
3346
3347 /* PREFIX_0F6F */
3348 {
3349 { "movq", { MX, EM }, PREFIX_OPCODE },
3350 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3351 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3352 },
3353
3354 /* PREFIX_0F70 */
3355 {
3356 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3357 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3358 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3359 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3360 },
3361
3362 /* PREFIX_0F78 */
3363 {
3364 {"vmread", { Em, Gm }, 0 },
3365 { Bad_Opcode },
3366 {"extrq", { XS, Ib, Ib }, 0 },
3367 {"insertq", { XM, XS, Ib, Ib }, 0 },
3368 },
3369
3370 /* PREFIX_0F79 */
3371 {
3372 {"vmwrite", { Gm, Em }, 0 },
3373 { Bad_Opcode },
3374 {"extrq", { XM, XS }, 0 },
3375 {"insertq", { XM, XS }, 0 },
3376 },
3377
3378 /* PREFIX_0F7C */
3379 {
3380 { Bad_Opcode },
3381 { Bad_Opcode },
3382 { "Vhaddpd", { XM, Vex, EXx }, 0 },
3383 { "Vhaddps", { XM, Vex, EXx }, 0 },
3384 },
3385
3386 /* PREFIX_0F7D */
3387 {
3388 { Bad_Opcode },
3389 { Bad_Opcode },
3390 { "Vhsubpd", { XM, Vex, EXx }, 0 },
3391 { "Vhsubps", { XM, Vex, EXx }, 0 },
3392 },
3393
3394 /* PREFIX_0F7E */
3395 {
3396 { "movK", { Edq, MX }, PREFIX_OPCODE },
3397 { "movq", { XM, EXq }, PREFIX_OPCODE },
3398 { "movK", { Edq, XM }, PREFIX_OPCODE },
3399 },
3400
3401 /* PREFIX_0F7F */
3402 {
3403 { "movq", { EMS, MX }, PREFIX_OPCODE },
3404 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3405 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3406 },
3407
3408 /* PREFIX_0FAE_REG_0_MOD_3 */
3409 {
3410 { Bad_Opcode },
3411 { "rdfsbase", { Ev }, 0 },
3412 },
3413
3414 /* PREFIX_0FAE_REG_1_MOD_3 */
3415 {
3416 { Bad_Opcode },
3417 { "rdgsbase", { Ev }, 0 },
3418 },
3419
3420 /* PREFIX_0FAE_REG_2_MOD_3 */
3421 {
3422 { Bad_Opcode },
3423 { "wrfsbase", { Ev }, 0 },
3424 },
3425
3426 /* PREFIX_0FAE_REG_3_MOD_3 */
3427 {
3428 { Bad_Opcode },
3429 { "wrgsbase", { Ev }, 0 },
3430 },
3431
3432 /* PREFIX_0FAE_REG_4_MOD_0 */
3433 {
3434 { "xsave", { FXSAVE }, 0 },
3435 { "ptwrite{%LQ|}", { Edq }, 0 },
3436 },
3437
3438 /* PREFIX_0FAE_REG_4_MOD_3 */
3439 {
3440 { Bad_Opcode },
3441 { "ptwrite{%LQ|}", { Edq }, 0 },
3442 },
3443
3444 /* PREFIX_0FAE_REG_5_MOD_3 */
3445 {
3446 { "lfence", { Skip_MODRM }, 0 },
3447 { "incsspK", { Edq }, PREFIX_OPCODE },
3448 },
3449
3450 /* PREFIX_0FAE_REG_6_MOD_0 */
3451 {
3452 { "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
3453 { "clrssbsy", { Mq }, PREFIX_OPCODE },
3454 { "clwb", { Mb }, PREFIX_OPCODE },
3455 },
3456
3457 /* PREFIX_0FAE_REG_6_MOD_3 */
3458 {
3459 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3460 { "umonitor", { Eva }, PREFIX_OPCODE },
3461 { "tpause", { Edq }, PREFIX_OPCODE },
3462 { "umwait", { Edq }, PREFIX_OPCODE },
3463 },
3464
3465 /* PREFIX_0FAE_REG_7_MOD_0 */
3466 {
3467 { "clflush", { Mb }, 0 },
3468 { Bad_Opcode },
3469 { "clflushopt", { Mb }, 0 },
3470 },
3471
3472 /* PREFIX_0FB8 */
3473 {
3474 { Bad_Opcode },
3475 { "popcntS", { Gv, Ev }, 0 },
3476 },
3477
3478 /* PREFIX_0FBC */
3479 {
3480 { "bsfS", { Gv, Ev }, 0 },
3481 { "tzcntS", { Gv, Ev }, 0 },
3482 { "bsfS", { Gv, Ev }, 0 },
3483 },
3484
3485 /* PREFIX_0FBD */
3486 {
3487 { "bsrS", { Gv, Ev }, 0 },
3488 { "lzcntS", { Gv, Ev }, 0 },
3489 { "bsrS", { Gv, Ev }, 0 },
3490 },
3491
3492 /* PREFIX_0FC2 */
3493 {
3494 { "VcmppX", { XM, Vex, EXx, CMP }, 0 },
3495 { "Vcmpss", { XMScalar, VexScalar, EXd, CMP }, 0 },
3496 { "VcmppX", { XM, Vex, EXx, CMP }, 0 },
3497 { "Vcmpsd", { XMScalar, VexScalar, EXq, CMP }, 0 },
3498 },
3499
3500 /* PREFIX_0FC7_REG_6_MOD_0 */
3501 {
3502 { "vmptrld",{ Mq }, 0 },
3503 { "vmxon", { Mq }, 0 },
3504 { "vmclear",{ Mq }, 0 },
3505 },
3506
3507 /* PREFIX_0FC7_REG_6_MOD_3 */
3508 {
3509 { "rdrand", { Ev }, 0 },
3510 { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) },
3511 { "rdrand", { Ev }, 0 }
3512 },
3513
3514 /* PREFIX_0FC7_REG_7_MOD_3 */
3515 {
3516 { "rdseed", { Ev }, 0 },
3517 { "rdpid", { Em }, 0 },
3518 { "rdseed", { Ev }, 0 },
3519 },
3520
3521 /* PREFIX_0FD0 */
3522 {
3523 { Bad_Opcode },
3524 { Bad_Opcode },
3525 { "VaddsubpX", { XM, Vex, EXx }, 0 },
3526 { "VaddsubpX", { XM, Vex, EXx }, 0 },
3527 },
3528
3529 /* PREFIX_0FD6 */
3530 {
3531 { Bad_Opcode },
3532 { "movq2dq",{ XM, MS }, 0 },
3533 { "movq", { EXqS, XM }, 0 },
3534 { "movdq2q",{ MX, XS }, 0 },
3535 },
3536
3537 /* PREFIX_0FE6 */
3538 {
3539 { Bad_Opcode },
3540 { "Vcvtdq2pd", { XM, EXxmmq }, 0 },
3541 { "Vcvttpd2dq%XY", { XMM, EXx }, 0 },
3542 { "Vcvtpd2dq%XY", { XMM, EXx }, 0 },
3543 },
3544
3545 /* PREFIX_0FE7 */
3546 {
3547 { "movntq", { Mq, MX }, PREFIX_OPCODE },
3548 { Bad_Opcode },
3549 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3550 },
3551
3552 /* PREFIX_0FF0 */
3553 {
3554 { Bad_Opcode },
3555 { Bad_Opcode },
3556 { Bad_Opcode },
3557 { "Vlddqu", { XM, M }, 0 },
3558 },
3559
3560 /* PREFIX_0FF7 */
3561 {
3562 { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3563 { Bad_Opcode },
3564 { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3565 },
3566
3567 /* PREFIX_0F38D8 */
3568 {
3569 { Bad_Opcode },
3570 { REG_TABLE (REG_0F38D8_PREFIX_1) },
3571 },
3572
3573 /* PREFIX_0F38DC */
3574 {
3575 { Bad_Opcode },
3576 { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3577 { "aesenc", { XM, EXx }, 0 },
3578 },
3579
3580 /* PREFIX_0F38DD */
3581 {
3582 { Bad_Opcode },
3583 { MOD_TABLE (MOD_0F38DD_PREFIX_1) },
3584 { "aesenclast", { XM, EXx }, 0 },
3585 },
3586
3587 /* PREFIX_0F38DE */
3588 {
3589 { Bad_Opcode },
3590 { MOD_TABLE (MOD_0F38DE_PREFIX_1) },
3591 { "aesdec", { XM, EXx }, 0 },
3592 },
3593
3594 /* PREFIX_0F38DF */
3595 {
3596 { Bad_Opcode },
3597 { MOD_TABLE (MOD_0F38DF_PREFIX_1) },
3598 { "aesdeclast", { XM, EXx }, 0 },
3599 },
3600
3601 /* PREFIX_0F38F0 */
3602 {
3603 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3604 { Bad_Opcode },
3605 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3606 { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3607 },
3608
3609 /* PREFIX_0F38F1 */
3610 {
3611 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3612 { Bad_Opcode },
3613 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3614 { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3615 },
3616
3617 /* PREFIX_0F38F6 */
3618 {
3619 { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
3620 { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
3621 { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
3622 { Bad_Opcode },
3623 },
3624
3625 /* PREFIX_0F38F8 */
3626 {
3627 { Bad_Opcode },
3628 { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
3629 { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
3630 { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
3631 },
3632 /* PREFIX_0F38FA */
3633 {
3634 { Bad_Opcode },
3635 { MOD_TABLE (MOD_0F38FA_PREFIX_1) },
3636 },
3637
3638 /* PREFIX_0F38FB */
3639 {
3640 { Bad_Opcode },
3641 { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
3642 },
3643
3644 /* PREFIX_0F38FC */
3645 {
3646 { "aadd", { Mdq, Gdq }, 0 },
3647 { "axor", { Mdq, Gdq }, 0 },
3648 { "aand", { Mdq, Gdq }, 0 },
3649 { "aor", { Mdq, Gdq }, 0 },
3650 },
3651
3652 /* PREFIX_0F3A0F */
3653 {
3654 { Bad_Opcode },
3655 { MOD_TABLE (MOD_0F3A0F_PREFIX_1)},
3656 },
3657
3658 /* PREFIX_VEX_0F12 */
3659 {
3660 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0) },
3661 { "%XEvmov%XSldup", { XM, EXEvexXNoBcst }, 0 },
3662 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
3663 { "%XEvmov%XDdup", { XM, EXymmq }, 0 },
3664 },
3665
3666 /* PREFIX_VEX_0F16 */
3667 {
3668 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0) },
3669 { "%XEvmov%XShdup", { XM, EXEvexXNoBcst }, 0 },
3670 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
3671 },
3672
3673 /* PREFIX_VEX_0F2A */
3674 {
3675 { Bad_Opcode },
3676 { "%XEvcvtsi2ssY{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
3677 { Bad_Opcode },
3678 { "%XEvcvtsi2sdY{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
3679 },
3680
3681 /* PREFIX_VEX_0F2C */
3682 {
3683 { Bad_Opcode },
3684 { "%XEvcvttss2si", { Gdq, EXd, EXxEVexS }, 0 },
3685 { Bad_Opcode },
3686 { "%XEvcvttsd2si", { Gdq, EXq, EXxEVexS }, 0 },
3687 },
3688
3689 /* PREFIX_VEX_0F2D */
3690 {
3691 { Bad_Opcode },
3692 { "%XEvcvtss2si", { Gdq, EXd, EXxEVexR }, 0 },
3693 { Bad_Opcode },
3694 { "%XEvcvtsd2si", { Gdq, EXq, EXxEVexR }, 0 },
3695 },
3696
3697 /* PREFIX_VEX_0F41_L_1_M_1_W_0 */
3698 {
3699 { "kandw", { MaskG, MaskVex, MaskE }, 0 },
3700 { Bad_Opcode },
3701 { "kandb", { MaskG, MaskVex, MaskE }, 0 },
3702 },
3703
3704 /* PREFIX_VEX_0F41_L_1_M_1_W_1 */
3705 {
3706 { "kandq", { MaskG, MaskVex, MaskE }, 0 },
3707 { Bad_Opcode },
3708 { "kandd", { MaskG, MaskVex, MaskE }, 0 },
3709 },
3710
3711 /* PREFIX_VEX_0F42_L_1_M_1_W_0 */
3712 {
3713 { "kandnw", { MaskG, MaskVex, MaskE }, 0 },
3714 { Bad_Opcode },
3715 { "kandnb", { MaskG, MaskVex, MaskE }, 0 },
3716 },
3717
3718 /* PREFIX_VEX_0F42_L_1_M_1_W_1 */
3719 {
3720 { "kandnq", { MaskG, MaskVex, MaskE }, 0 },
3721 { Bad_Opcode },
3722 { "kandnd", { MaskG, MaskVex, MaskE }, 0 },
3723 },
3724
3725 /* PREFIX_VEX_0F44_L_0_M_1_W_0 */
3726 {
3727 { "knotw", { MaskG, MaskE }, 0 },
3728 { Bad_Opcode },
3729 { "knotb", { MaskG, MaskE }, 0 },
3730 },
3731
3732 /* PREFIX_VEX_0F44_L_0_M_1_W_1 */
3733 {
3734 { "knotq", { MaskG, MaskE }, 0 },
3735 { Bad_Opcode },
3736 { "knotd", { MaskG, MaskE }, 0 },
3737 },
3738
3739 /* PREFIX_VEX_0F45_L_1_M_1_W_0 */
3740 {
3741 { "korw", { MaskG, MaskVex, MaskE }, 0 },
3742 { Bad_Opcode },
3743 { "korb", { MaskG, MaskVex, MaskE }, 0 },
3744 },
3745
3746 /* PREFIX_VEX_0F45_L_1_M_1_W_1 */
3747 {
3748 { "korq", { MaskG, MaskVex, MaskE }, 0 },
3749 { Bad_Opcode },
3750 { "kord", { MaskG, MaskVex, MaskE }, 0 },
3751 },
3752
3753 /* PREFIX_VEX_0F46_L_1_M_1_W_0 */
3754 {
3755 { "kxnorw", { MaskG, MaskVex, MaskE }, 0 },
3756 { Bad_Opcode },
3757 { "kxnorb", { MaskG, MaskVex, MaskE }, 0 },
3758 },
3759
3760 /* PREFIX_VEX_0F46_L_1_M_1_W_1 */
3761 {
3762 { "kxnorq", { MaskG, MaskVex, MaskE }, 0 },
3763 { Bad_Opcode },
3764 { "kxnord", { MaskG, MaskVex, MaskE }, 0 },
3765 },
3766
3767 /* PREFIX_VEX_0F47_L_1_M_1_W_0 */
3768 {
3769 { "kxorw", { MaskG, MaskVex, MaskE }, 0 },
3770 { Bad_Opcode },
3771 { "kxorb", { MaskG, MaskVex, MaskE }, 0 },
3772 },
3773
3774 /* PREFIX_VEX_0F47_L_1_M_1_W_1 */
3775 {
3776 { "kxorq", { MaskG, MaskVex, MaskE }, 0 },
3777 { Bad_Opcode },
3778 { "kxord", { MaskG, MaskVex, MaskE }, 0 },
3779 },
3780
3781 /* PREFIX_VEX_0F4A_L_1_M_1_W_0 */
3782 {
3783 { "kaddw", { MaskG, MaskVex, MaskE }, 0 },
3784 { Bad_Opcode },
3785 { "kaddb", { MaskG, MaskVex, MaskE }, 0 },
3786 },
3787
3788 /* PREFIX_VEX_0F4A_L_1_M_1_W_1 */
3789 {
3790 { "kaddq", { MaskG, MaskVex, MaskE }, 0 },
3791 { Bad_Opcode },
3792 { "kaddd", { MaskG, MaskVex, MaskE }, 0 },
3793 },
3794
3795 /* PREFIX_VEX_0F4B_L_1_M_1_W_0 */
3796 {
3797 { "kunpckwd", { MaskG, MaskVex, MaskE }, 0 },
3798 { Bad_Opcode },
3799 { "kunpckbw", { MaskG, MaskVex, MaskE }, 0 },
3800 },
3801
3802 /* PREFIX_VEX_0F4B_L_1_M_1_W_1 */
3803 {
3804 { "kunpckdq", { MaskG, MaskVex, MaskE }, 0 },
3805 },
3806
3807 /* PREFIX_VEX_0F6F */
3808 {
3809 { Bad_Opcode },
3810 { "vmovdqu", { XM, EXx }, 0 },
3811 { "vmovdqa", { XM, EXx }, 0 },
3812 },
3813
3814 /* PREFIX_VEX_0F70 */
3815 {
3816 { Bad_Opcode },
3817 { "vpshufhw", { XM, EXx, Ib }, 0 },
3818 { "vpshufd", { XM, EXx, Ib }, 0 },
3819 { "vpshuflw", { XM, EXx, Ib }, 0 },
3820 },
3821
3822 /* PREFIX_VEX_0F7E */
3823 {
3824 { Bad_Opcode },
3825 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3826 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3827 },
3828
3829 /* PREFIX_VEX_0F7F */
3830 {
3831 { Bad_Opcode },
3832 { "vmovdqu", { EXxS, XM }, 0 },
3833 { "vmovdqa", { EXxS, XM }, 0 },
3834 },
3835
3836 /* PREFIX_VEX_0F90_L_0_W_0 */
3837 {
3838 { "kmovw", { MaskG, MaskE }, 0 },
3839 { Bad_Opcode },
3840 { "kmovb", { MaskG, MaskBDE }, 0 },
3841 },
3842
3843 /* PREFIX_VEX_0F90_L_0_W_1 */
3844 {
3845 { "kmovq", { MaskG, MaskE }, 0 },
3846 { Bad_Opcode },
3847 { "kmovd", { MaskG, MaskBDE }, 0 },
3848 },
3849
3850 /* PREFIX_VEX_0F91_L_0_M_0_W_0 */
3851 {
3852 { "kmovw", { Ew, MaskG }, 0 },
3853 { Bad_Opcode },
3854 { "kmovb", { Eb, MaskG }, 0 },
3855 },
3856
3857 /* PREFIX_VEX_0F91_L_0_M_0_W_1 */
3858 {
3859 { "kmovq", { Eq, MaskG }, 0 },
3860 { Bad_Opcode },
3861 { "kmovd", { Ed, MaskG }, 0 },
3862 },
3863
3864 /* PREFIX_VEX_0F92_L_0_M_1_W_0 */
3865 {
3866 { "kmovw", { MaskG, Edq }, 0 },
3867 { Bad_Opcode },
3868 { "kmovb", { MaskG, Edq }, 0 },
3869 { "kmovd", { MaskG, Edq }, 0 },
3870 },
3871
3872 /* PREFIX_VEX_0F92_L_0_M_1_W_1 */
3873 {
3874 { Bad_Opcode },
3875 { Bad_Opcode },
3876 { Bad_Opcode },
3877 { "kmovK", { MaskG, Edq }, 0 },
3878 },
3879
3880 /* PREFIX_VEX_0F93_L_0_M_1_W_0 */
3881 {
3882 { "kmovw", { Gdq, MaskE }, 0 },
3883 { Bad_Opcode },
3884 { "kmovb", { Gdq, MaskE }, 0 },
3885 { "kmovd", { Gdq, MaskE }, 0 },
3886 },
3887
3888 /* PREFIX_VEX_0F93_L_0_M_1_W_1 */
3889 {
3890 { Bad_Opcode },
3891 { Bad_Opcode },
3892 { Bad_Opcode },
3893 { "kmovK", { Gdq, MaskE }, 0 },
3894 },
3895
3896 /* PREFIX_VEX_0F98_L_0_M_1_W_0 */
3897 {
3898 { "kortestw", { MaskG, MaskE }, 0 },
3899 { Bad_Opcode },
3900 { "kortestb", { MaskG, MaskE }, 0 },
3901 },
3902
3903 /* PREFIX_VEX_0F98_L_0_M_1_W_1 */
3904 {
3905 { "kortestq", { MaskG, MaskE }, 0 },
3906 { Bad_Opcode },
3907 { "kortestd", { MaskG, MaskE }, 0 },
3908 },
3909
3910 /* PREFIX_VEX_0F99_L_0_M_1_W_0 */
3911 {
3912 { "ktestw", { MaskG, MaskE }, 0 },
3913 { Bad_Opcode },
3914 { "ktestb", { MaskG, MaskE }, 0 },
3915 },
3916
3917 /* PREFIX_VEX_0F99_L_0_M_1_W_1 */
3918 {
3919 { "ktestq", { MaskG, MaskE }, 0 },
3920 { Bad_Opcode },
3921 { "ktestd", { MaskG, MaskE }, 0 },
3922 },
3923
3924 /* PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0 */
3925 {
3926 { "ldtilecfg", { M }, 0 },
3927 { Bad_Opcode },
3928 { "sttilecfg", { M }, 0 },
3929 },
3930
3931 /* PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1 */
3932 {
3933 { REG_TABLE (REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0) },
3934 { Bad_Opcode },
3935 { Bad_Opcode },
3936 { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3) },
3937 },
3938
3939 /* PREFIX_VEX_0F384B_X86_64_L_0_W_0_M_0 */
3940 {
3941 { Bad_Opcode },
3942 { "tilestored", { MVexSIBMEM, TMM }, 0 },
3943 { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
3944 { "tileloadd", { TMM, MVexSIBMEM }, 0 },
3945 },
3946
3947 /* PREFIX_VEX_0F3850_W_0 */
3948 {
3949 { "vpdpbuud", { XM, Vex, EXx }, 0 },
3950 { "vpdpbsud", { XM, Vex, EXx }, 0 },
3951 { "%XVvpdpbusd", { XM, Vex, EXx }, 0 },
3952 { "vpdpbssd", { XM, Vex, EXx }, 0 },
3953 },
3954
3955 /* PREFIX_VEX_0F3851_W_0 */
3956 {
3957 { "vpdpbuuds", { XM, Vex, EXx }, 0 },
3958 { "vpdpbsuds", { XM, Vex, EXx }, 0 },
3959 { "%XVvpdpbusds", { XM, Vex, EXx }, 0 },
3960 { "vpdpbssds", { XM, Vex, EXx }, 0 },
3961 },
3962 /* PREFIX_VEX_0F385C_X86_64_M_1_L_0_W_0 */
3963 {
3964 { Bad_Opcode },
3965 { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
3966 { Bad_Opcode },
3967 { "tdpfp16ps", { TMM, EXtmm, VexTmm }, 0 },
3968 },
3969
3970 /* PREFIX_VEX_0F385E_X86_64_M_1_L_0_W_0 */
3971 {
3972 { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
3973 { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
3974 { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
3975 { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
3976 },
3977
3978 /* PREFIX_VEX_0F386C_X86_64_M_1_L_0_W_0 */
3979 {
3980 { "tcmmrlfp16ps", { TMM, EXtmm, VexTmm }, 0 },
3981 { Bad_Opcode },
3982 { "tcmmimfp16ps", { TMM, EXtmm, VexTmm }, 0 },
3983 },
3984
3985 /* PREFIX_VEX_0F3872 */
3986 {
3987 { Bad_Opcode },
3988 { VEX_W_TABLE (VEX_W_0F3872_P_1) },
3989 },
3990
3991 /* PREFIX_VEX_0F38B0_W_0 */
3992 {
3993 { "vcvtneoph2ps", { XM, Mx }, 0 },
3994 { "vcvtneebf162ps", { XM, Mx }, 0 },
3995 { "vcvtneeph2ps", { XM, Mx }, 0 },
3996 { "vcvtneobf162ps", { XM, Mx }, 0 },
3997 },
3998
3999 /* PREFIX_VEX_0F38B1_W_0 */
4000 {
4001 { Bad_Opcode },
4002 { "vbcstnebf162ps", { XM, Mw }, 0 },
4003 { "vbcstnesh2ps", { XM, Mw }, 0 },
4004 },
4005
4006 /* PREFIX_VEX_0F38F5_L_0 */
4007 {
4008 { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
4009 { "pextS", { Gdq, VexGdq, Edq }, 0 },
4010 { Bad_Opcode },
4011 { "pdepS", { Gdq, VexGdq, Edq }, 0 },
4012 },
4013
4014 /* PREFIX_VEX_0F38F6_L_0 */
4015 {
4016 { Bad_Opcode },
4017 { Bad_Opcode },
4018 { Bad_Opcode },
4019 { "mulxS", { Gdq, VexGdq, Edq }, 0 },
4020 },
4021
4022 /* PREFIX_VEX_0F38F7_L_0 */
4023 {
4024 { "bextrS", { Gdq, Edq, VexGdq }, 0 },
4025 { "sarxS", { Gdq, Edq, VexGdq }, 0 },
4026 { "shlxS", { Gdq, Edq, VexGdq }, 0 },
4027 { "shrxS", { Gdq, Edq, VexGdq }, 0 },
4028 },
4029
4030 /* PREFIX_VEX_0F3AF0_L_0 */
4031 {
4032 { Bad_Opcode },
4033 { Bad_Opcode },
4034 { Bad_Opcode },
4035 { "rorxS", { Gdq, Edq, Ib }, 0 },
4036 },
4037
4038 #include "i386-dis-evex-prefix.h"
4039 };
4040
4041 static const struct dis386 x86_64_table[][2] = {
4042 /* X86_64_06 */
4043 {
4044 { "pushP", { es }, 0 },
4045 },
4046
4047 /* X86_64_07 */
4048 {
4049 { "popP", { es }, 0 },
4050 },
4051
4052 /* X86_64_0E */
4053 {
4054 { "pushP", { cs }, 0 },
4055 },
4056
4057 /* X86_64_16 */
4058 {
4059 { "pushP", { ss }, 0 },
4060 },
4061
4062 /* X86_64_17 */
4063 {
4064 { "popP", { ss }, 0 },
4065 },
4066
4067 /* X86_64_1E */
4068 {
4069 { "pushP", { ds }, 0 },
4070 },
4071
4072 /* X86_64_1F */
4073 {
4074 { "popP", { ds }, 0 },
4075 },
4076
4077 /* X86_64_27 */
4078 {
4079 { "daa", { XX }, 0 },
4080 },
4081
4082 /* X86_64_2F */
4083 {
4084 { "das", { XX }, 0 },
4085 },
4086
4087 /* X86_64_37 */
4088 {
4089 { "aaa", { XX }, 0 },
4090 },
4091
4092 /* X86_64_3F */
4093 {
4094 { "aas", { XX }, 0 },
4095 },
4096
4097 /* X86_64_60 */
4098 {
4099 { "pushaP", { XX }, 0 },
4100 },
4101
4102 /* X86_64_61 */
4103 {
4104 { "popaP", { XX }, 0 },
4105 },
4106
4107 /* X86_64_62 */
4108 {
4109 { MOD_TABLE (MOD_62_32BIT) },
4110 { EVEX_TABLE (EVEX_0F) },
4111 },
4112
4113 /* X86_64_63 */
4114 {
4115 { "arpl", { Ew, Gw }, 0 },
4116 { "movs", { Gv, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4117 },
4118
4119 /* X86_64_6D */
4120 {
4121 { "ins{R|}", { Yzr, indirDX }, 0 },
4122 { "ins{G|}", { Yzr, indirDX }, 0 },
4123 },
4124
4125 /* X86_64_6F */
4126 {
4127 { "outs{R|}", { indirDXr, Xz }, 0 },
4128 { "outs{G|}", { indirDXr, Xz }, 0 },
4129 },
4130
4131 /* X86_64_82 */
4132 {
4133 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
4134 { REG_TABLE (REG_80) },
4135 },
4136
4137 /* X86_64_9A */
4138 {
4139 { "{l|}call{P|}", { Ap }, 0 },
4140 },
4141
4142 /* X86_64_C2 */
4143 {
4144 { "retP", { Iw, BND }, 0 },
4145 { "ret@", { Iw, BND }, 0 },
4146 },
4147
4148 /* X86_64_C3 */
4149 {
4150 { "retP", { BND }, 0 },
4151 { "ret@", { BND }, 0 },
4152 },
4153
4154 /* X86_64_C4 */
4155 {
4156 { MOD_TABLE (MOD_C4_32BIT) },
4157 { VEX_C4_TABLE (VEX_0F) },
4158 },
4159
4160 /* X86_64_C5 */
4161 {
4162 { MOD_TABLE (MOD_C5_32BIT) },
4163 { VEX_C5_TABLE (VEX_0F) },
4164 },
4165
4166 /* X86_64_CE */
4167 {
4168 { "into", { XX }, 0 },
4169 },
4170
4171 /* X86_64_D4 */
4172 {
4173 { "aam", { Ib }, 0 },
4174 },
4175
4176 /* X86_64_D5 */
4177 {
4178 { "aad", { Ib }, 0 },
4179 },
4180
4181 /* X86_64_E8 */
4182 {
4183 { "callP", { Jv, BND }, 0 },
4184 { "call@", { Jv, BND }, 0 }
4185 },
4186
4187 /* X86_64_E9 */
4188 {
4189 { "jmpP", { Jv, BND }, 0 },
4190 { "jmp@", { Jv, BND }, 0 }
4191 },
4192
4193 /* X86_64_EA */
4194 {
4195 { "{l|}jmp{P|}", { Ap }, 0 },
4196 },
4197
4198 /* X86_64_0F00_REG_6 */
4199 {
4200 { Bad_Opcode },
4201 { PREFIX_TABLE (PREFIX_0F00_REG_6_X86_64) },
4202 },
4203
4204 /* X86_64_0F01_REG_0 */
4205 {
4206 { "sgdt{Q|Q}", { M }, 0 },
4207 { "sgdt", { M }, 0 },
4208 },
4209
4210 /* X86_64_0F01_REG_0_MOD_3_RM_6_P_1 */
4211 {
4212 { Bad_Opcode },
4213 { "wrmsrlist", { Skip_MODRM }, 0 },
4214 },
4215
4216 /* X86_64_0F01_REG_0_MOD_3_RM_6_P_3 */
4217 {
4218 { Bad_Opcode },
4219 { "rdmsrlist", { Skip_MODRM }, 0 },
4220 },
4221
4222 /* X86_64_0F01_REG_1 */
4223 {
4224 { "sidt{Q|Q}", { M }, 0 },
4225 { "sidt", { M }, 0 },
4226 },
4227
4228 /* X86_64_0F01_REG_1_RM_2_PREFIX_1 */
4229 {
4230 { Bad_Opcode },
4231 { "eretu", { Skip_MODRM }, 0 },
4232 },
4233
4234 /* X86_64_0F01_REG_1_RM_2_PREFIX_3 */
4235 {
4236 { Bad_Opcode },
4237 { "erets", { Skip_MODRM }, 0 },
4238 },
4239
4240 /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4241 {
4242 { Bad_Opcode },
4243 { "seamret", { Skip_MODRM }, 0 },
4244 },
4245
4246 /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4247 {
4248 { Bad_Opcode },
4249 { "seamops", { Skip_MODRM }, 0 },
4250 },
4251
4252 /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4253 {
4254 { Bad_Opcode },
4255 { "seamcall", { Skip_MODRM }, 0 },
4256 },
4257
4258 /* X86_64_0F01_REG_2 */
4259 {
4260 { "lgdt{Q|Q}", { M }, 0 },
4261 { "lgdt", { M }, 0 },
4262 },
4263
4264 /* X86_64_0F01_REG_3 */
4265 {
4266 { "lidt{Q|Q}", { M }, 0 },
4267 { "lidt", { M }, 0 },
4268 },
4269
4270 /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4271 {
4272 { Bad_Opcode },
4273 { "uiret", { Skip_MODRM }, 0 },
4274 },
4275
4276 /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4277 {
4278 { Bad_Opcode },
4279 { "testui", { Skip_MODRM }, 0 },
4280 },
4281
4282 /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4283 {
4284 { Bad_Opcode },
4285 { "clui", { Skip_MODRM }, 0 },
4286 },
4287
4288 /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4289 {
4290 { Bad_Opcode },
4291 { "stui", { Skip_MODRM }, 0 },
4292 },
4293
4294 /* X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1 */
4295 {
4296 { Bad_Opcode },
4297 { "rmpquery", { Skip_MODRM }, 0 },
4298 },
4299
4300 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4301 {
4302 { Bad_Opcode },
4303 { "rmpadjust", { Skip_MODRM }, 0 },
4304 },
4305
4306 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4307 {
4308 { Bad_Opcode },
4309 { "rmpupdate", { Skip_MODRM }, 0 },
4310 },
4311
4312 /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4313 {
4314 { Bad_Opcode },
4315 { "psmash", { Skip_MODRM }, 0 },
4316 },
4317
4318 /* X86_64_0F18_REG_6_MOD_0 */
4319 {
4320 { "nopQ", { Ev }, 0 },
4321 { PREFIX_TABLE (PREFIX_0F18_REG_6_MOD_0_X86_64) },
4322 },
4323
4324 /* X86_64_0F18_REG_7_MOD_0 */
4325 {
4326 { "nopQ", { Ev }, 0 },
4327 { PREFIX_TABLE (PREFIX_0F18_REG_7_MOD_0_X86_64) },
4328 },
4329
4330 {
4331 /* X86_64_0F24 */
4332 { "movZ", { Em, Td }, 0 },
4333 },
4334
4335 {
4336 /* X86_64_0F26 */
4337 { "movZ", { Td, Em }, 0 },
4338 },
4339
4340 /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4341 {
4342 { Bad_Opcode },
4343 { "senduipi", { Eq }, 0 },
4344 },
4345
4346 /* X86_64_VEX_0F3849 */
4347 {
4348 { Bad_Opcode },
4349 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64) },
4350 },
4351
4352 /* X86_64_VEX_0F384B */
4353 {
4354 { Bad_Opcode },
4355 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64) },
4356 },
4357
4358 /* X86_64_VEX_0F385C */
4359 {
4360 { Bad_Opcode },
4361 { MOD_TABLE (MOD_VEX_0F385C_X86_64) },
4362 },
4363
4364 /* X86_64_VEX_0F385E */
4365 {
4366 { Bad_Opcode },
4367 { MOD_TABLE (MOD_VEX_0F385E_X86_64) },
4368 },
4369
4370 /* X86_64_VEX_0F386C */
4371 {
4372 { Bad_Opcode },
4373 { MOD_TABLE (MOD_VEX_0F386C_X86_64) },
4374 },
4375
4376 /* X86_64_VEX_0F38E0 */
4377 {
4378 { Bad_Opcode },
4379 { "cmpoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4380 },
4381
4382 /* X86_64_VEX_0F38E1 */
4383 {
4384 { Bad_Opcode },
4385 { "cmpnoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4386 },
4387
4388 /* X86_64_VEX_0F38E2 */
4389 {
4390 { Bad_Opcode },
4391 { "cmpbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4392 },
4393
4394 /* X86_64_VEX_0F38E3 */
4395 {
4396 { Bad_Opcode },
4397 { "cmpnbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4398 },
4399
4400 /* X86_64_VEX_0F38E4 */
4401 {
4402 { Bad_Opcode },
4403 { "cmpzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4404 },
4405
4406 /* X86_64_VEX_0F38E5 */
4407 {
4408 { Bad_Opcode },
4409 { "cmpnzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4410 },
4411
4412 /* X86_64_VEX_0F38E6 */
4413 {
4414 { Bad_Opcode },
4415 { "cmpbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4416 },
4417
4418 /* X86_64_VEX_0F38E7 */
4419 {
4420 { Bad_Opcode },
4421 { "cmpnbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4422 },
4423
4424 /* X86_64_VEX_0F38E8 */
4425 {
4426 { Bad_Opcode },
4427 { "cmpsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4428 },
4429
4430 /* X86_64_VEX_0F38E9 */
4431 {
4432 { Bad_Opcode },
4433 { "cmpnsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4434 },
4435
4436 /* X86_64_VEX_0F38EA */
4437 {
4438 { Bad_Opcode },
4439 { "cmppxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4440 },
4441
4442 /* X86_64_VEX_0F38EB */
4443 {
4444 { Bad_Opcode },
4445 { "cmpnpxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4446 },
4447
4448 /* X86_64_VEX_0F38EC */
4449 {
4450 { Bad_Opcode },
4451 { "cmplxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4452 },
4453
4454 /* X86_64_VEX_0F38ED */
4455 {
4456 { Bad_Opcode },
4457 { "cmpnlxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4458 },
4459
4460 /* X86_64_VEX_0F38EE */
4461 {
4462 { Bad_Opcode },
4463 { "cmplexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4464 },
4465
4466 /* X86_64_VEX_0F38EF */
4467 {
4468 { Bad_Opcode },
4469 { "cmpnlexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4470 },
4471 };
4472
4473 static const struct dis386 three_byte_table[][256] = {
4474
4475 /* THREE_BYTE_0F38 */
4476 {
4477 /* 00 */
4478 { "pshufb", { MX, EM }, PREFIX_OPCODE },
4479 { "phaddw", { MX, EM }, PREFIX_OPCODE },
4480 { "phaddd", { MX, EM }, PREFIX_OPCODE },
4481 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
4482 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
4483 { "phsubw", { MX, EM }, PREFIX_OPCODE },
4484 { "phsubd", { MX, EM }, PREFIX_OPCODE },
4485 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
4486 /* 08 */
4487 { "psignb", { MX, EM }, PREFIX_OPCODE },
4488 { "psignw", { MX, EM }, PREFIX_OPCODE },
4489 { "psignd", { MX, EM }, PREFIX_OPCODE },
4490 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
4491 { Bad_Opcode },
4492 { Bad_Opcode },
4493 { Bad_Opcode },
4494 { Bad_Opcode },
4495 /* 10 */
4496 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4497 { Bad_Opcode },
4498 { Bad_Opcode },
4499 { Bad_Opcode },
4500 { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4501 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4502 { Bad_Opcode },
4503 { "ptest", { XM, EXx }, PREFIX_DATA },
4504 /* 18 */
4505 { Bad_Opcode },
4506 { Bad_Opcode },
4507 { Bad_Opcode },
4508 { Bad_Opcode },
4509 { "pabsb", { MX, EM }, PREFIX_OPCODE },
4510 { "pabsw", { MX, EM }, PREFIX_OPCODE },
4511 { "pabsd", { MX, EM }, PREFIX_OPCODE },
4512 { Bad_Opcode },
4513 /* 20 */
4514 { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4515 { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4516 { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4517 { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4518 { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4519 { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4520 { Bad_Opcode },
4521 { Bad_Opcode },
4522 /* 28 */
4523 { "pmuldq", { XM, EXx }, PREFIX_DATA },
4524 { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4525 { MOD_TABLE (MOD_0F382A) },
4526 { "packusdw", { XM, EXx }, PREFIX_DATA },
4527 { Bad_Opcode },
4528 { Bad_Opcode },
4529 { Bad_Opcode },
4530 { Bad_Opcode },
4531 /* 30 */
4532 { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4533 { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4534 { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4535 { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4536 { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4537 { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4538 { Bad_Opcode },
4539 { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4540 /* 38 */
4541 { "pminsb", { XM, EXx }, PREFIX_DATA },
4542 { "pminsd", { XM, EXx }, PREFIX_DATA },
4543 { "pminuw", { XM, EXx }, PREFIX_DATA },
4544 { "pminud", { XM, EXx }, PREFIX_DATA },
4545 { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4546 { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4547 { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4548 { "pmaxud", { XM, EXx }, PREFIX_DATA },
4549 /* 40 */
4550 { "pmulld", { XM, EXx }, PREFIX_DATA },
4551 { "phminposuw", { XM, EXx }, PREFIX_DATA },
4552 { Bad_Opcode },
4553 { Bad_Opcode },
4554 { Bad_Opcode },
4555 { Bad_Opcode },
4556 { Bad_Opcode },
4557 { Bad_Opcode },
4558 /* 48 */
4559 { Bad_Opcode },
4560 { Bad_Opcode },
4561 { Bad_Opcode },
4562 { Bad_Opcode },
4563 { Bad_Opcode },
4564 { Bad_Opcode },
4565 { Bad_Opcode },
4566 { Bad_Opcode },
4567 /* 50 */
4568 { Bad_Opcode },
4569 { Bad_Opcode },
4570 { Bad_Opcode },
4571 { Bad_Opcode },
4572 { Bad_Opcode },
4573 { Bad_Opcode },
4574 { Bad_Opcode },
4575 { Bad_Opcode },
4576 /* 58 */
4577 { Bad_Opcode },
4578 { Bad_Opcode },
4579 { Bad_Opcode },
4580 { Bad_Opcode },
4581 { Bad_Opcode },
4582 { Bad_Opcode },
4583 { Bad_Opcode },
4584 { Bad_Opcode },
4585 /* 60 */
4586 { Bad_Opcode },
4587 { Bad_Opcode },
4588 { Bad_Opcode },
4589 { Bad_Opcode },
4590 { Bad_Opcode },
4591 { Bad_Opcode },
4592 { Bad_Opcode },
4593 { Bad_Opcode },
4594 /* 68 */
4595 { Bad_Opcode },
4596 { Bad_Opcode },
4597 { Bad_Opcode },
4598 { Bad_Opcode },
4599 { Bad_Opcode },
4600 { Bad_Opcode },
4601 { Bad_Opcode },
4602 { Bad_Opcode },
4603 /* 70 */
4604 { Bad_Opcode },
4605 { Bad_Opcode },
4606 { Bad_Opcode },
4607 { Bad_Opcode },
4608 { Bad_Opcode },
4609 { Bad_Opcode },
4610 { Bad_Opcode },
4611 { Bad_Opcode },
4612 /* 78 */
4613 { Bad_Opcode },
4614 { Bad_Opcode },
4615 { Bad_Opcode },
4616 { Bad_Opcode },
4617 { Bad_Opcode },
4618 { Bad_Opcode },
4619 { Bad_Opcode },
4620 { Bad_Opcode },
4621 /* 80 */
4622 { "invept", { Gm, Mo }, PREFIX_DATA },
4623 { "invvpid", { Gm, Mo }, PREFIX_DATA },
4624 { "invpcid", { Gm, M }, PREFIX_DATA },
4625 { Bad_Opcode },
4626 { Bad_Opcode },
4627 { Bad_Opcode },
4628 { Bad_Opcode },
4629 { Bad_Opcode },
4630 /* 88 */
4631 { Bad_Opcode },
4632 { Bad_Opcode },
4633 { Bad_Opcode },
4634 { Bad_Opcode },
4635 { Bad_Opcode },
4636 { Bad_Opcode },
4637 { Bad_Opcode },
4638 { Bad_Opcode },
4639 /* 90 */
4640 { Bad_Opcode },
4641 { Bad_Opcode },
4642 { Bad_Opcode },
4643 { Bad_Opcode },
4644 { Bad_Opcode },
4645 { Bad_Opcode },
4646 { Bad_Opcode },
4647 { Bad_Opcode },
4648 /* 98 */
4649 { Bad_Opcode },
4650 { Bad_Opcode },
4651 { Bad_Opcode },
4652 { Bad_Opcode },
4653 { Bad_Opcode },
4654 { Bad_Opcode },
4655 { Bad_Opcode },
4656 { Bad_Opcode },
4657 /* a0 */
4658 { Bad_Opcode },
4659 { Bad_Opcode },
4660 { Bad_Opcode },
4661 { Bad_Opcode },
4662 { Bad_Opcode },
4663 { Bad_Opcode },
4664 { Bad_Opcode },
4665 { Bad_Opcode },
4666 /* a8 */
4667 { Bad_Opcode },
4668 { Bad_Opcode },
4669 { Bad_Opcode },
4670 { Bad_Opcode },
4671 { Bad_Opcode },
4672 { Bad_Opcode },
4673 { Bad_Opcode },
4674 { Bad_Opcode },
4675 /* b0 */
4676 { Bad_Opcode },
4677 { Bad_Opcode },
4678 { Bad_Opcode },
4679 { Bad_Opcode },
4680 { Bad_Opcode },
4681 { Bad_Opcode },
4682 { Bad_Opcode },
4683 { Bad_Opcode },
4684 /* b8 */
4685 { Bad_Opcode },
4686 { Bad_Opcode },
4687 { Bad_Opcode },
4688 { Bad_Opcode },
4689 { Bad_Opcode },
4690 { Bad_Opcode },
4691 { Bad_Opcode },
4692 { Bad_Opcode },
4693 /* c0 */
4694 { Bad_Opcode },
4695 { Bad_Opcode },
4696 { Bad_Opcode },
4697 { Bad_Opcode },
4698 { Bad_Opcode },
4699 { Bad_Opcode },
4700 { Bad_Opcode },
4701 { Bad_Opcode },
4702 /* c8 */
4703 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4704 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4705 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4706 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4707 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4708 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4709 { Bad_Opcode },
4710 { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4711 /* d0 */
4712 { Bad_Opcode },
4713 { Bad_Opcode },
4714 { Bad_Opcode },
4715 { Bad_Opcode },
4716 { Bad_Opcode },
4717 { Bad_Opcode },
4718 { Bad_Opcode },
4719 { Bad_Opcode },
4720 /* d8 */
4721 { PREFIX_TABLE (PREFIX_0F38D8) },
4722 { Bad_Opcode },
4723 { Bad_Opcode },
4724 { "aesimc", { XM, EXx }, PREFIX_DATA },
4725 { PREFIX_TABLE (PREFIX_0F38DC) },
4726 { PREFIX_TABLE (PREFIX_0F38DD) },
4727 { PREFIX_TABLE (PREFIX_0F38DE) },
4728 { PREFIX_TABLE (PREFIX_0F38DF) },
4729 /* e0 */
4730 { Bad_Opcode },
4731 { Bad_Opcode },
4732 { Bad_Opcode },
4733 { Bad_Opcode },
4734 { Bad_Opcode },
4735 { Bad_Opcode },
4736 { Bad_Opcode },
4737 { Bad_Opcode },
4738 /* e8 */
4739 { Bad_Opcode },
4740 { Bad_Opcode },
4741 { Bad_Opcode },
4742 { Bad_Opcode },
4743 { Bad_Opcode },
4744 { Bad_Opcode },
4745 { Bad_Opcode },
4746 { Bad_Opcode },
4747 /* f0 */
4748 { PREFIX_TABLE (PREFIX_0F38F0) },
4749 { PREFIX_TABLE (PREFIX_0F38F1) },
4750 { Bad_Opcode },
4751 { Bad_Opcode },
4752 { Bad_Opcode },
4753 { MOD_TABLE (MOD_0F38F5) },
4754 { PREFIX_TABLE (PREFIX_0F38F6) },
4755 { Bad_Opcode },
4756 /* f8 */
4757 { PREFIX_TABLE (PREFIX_0F38F8) },
4758 { MOD_TABLE (MOD_0F38F9) },
4759 { PREFIX_TABLE (PREFIX_0F38FA) },
4760 { PREFIX_TABLE (PREFIX_0F38FB) },
4761 { PREFIX_TABLE (PREFIX_0F38FC) },
4762 { Bad_Opcode },
4763 { Bad_Opcode },
4764 { Bad_Opcode },
4765 },
4766 /* THREE_BYTE_0F3A */
4767 {
4768 /* 00 */
4769 { Bad_Opcode },
4770 { Bad_Opcode },
4771 { Bad_Opcode },
4772 { Bad_Opcode },
4773 { Bad_Opcode },
4774 { Bad_Opcode },
4775 { Bad_Opcode },
4776 { Bad_Opcode },
4777 /* 08 */
4778 { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4779 { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4780 { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4781 { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4782 { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4783 { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4784 { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4785 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
4786 /* 10 */
4787 { Bad_Opcode },
4788 { Bad_Opcode },
4789 { Bad_Opcode },
4790 { Bad_Opcode },
4791 { "pextrb", { Edb, XM, Ib }, PREFIX_DATA },
4792 { "pextrw", { Edw, XM, Ib }, PREFIX_DATA },
4793 { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4794 { "extractps", { Ed, XM, Ib }, PREFIX_DATA },
4795 /* 18 */
4796 { Bad_Opcode },
4797 { Bad_Opcode },
4798 { Bad_Opcode },
4799 { Bad_Opcode },
4800 { Bad_Opcode },
4801 { Bad_Opcode },
4802 { Bad_Opcode },
4803 { Bad_Opcode },
4804 /* 20 */
4805 { "pinsrb", { XM, Edb, Ib }, PREFIX_DATA },
4806 { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4807 { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4808 { Bad_Opcode },
4809 { Bad_Opcode },
4810 { Bad_Opcode },
4811 { Bad_Opcode },
4812 { Bad_Opcode },
4813 /* 28 */
4814 { Bad_Opcode },
4815 { Bad_Opcode },
4816 { Bad_Opcode },
4817 { Bad_Opcode },
4818 { Bad_Opcode },
4819 { Bad_Opcode },
4820 { Bad_Opcode },
4821 { Bad_Opcode },
4822 /* 30 */
4823 { Bad_Opcode },
4824 { Bad_Opcode },
4825 { Bad_Opcode },
4826 { Bad_Opcode },
4827 { Bad_Opcode },
4828 { Bad_Opcode },
4829 { Bad_Opcode },
4830 { Bad_Opcode },
4831 /* 38 */
4832 { Bad_Opcode },
4833 { Bad_Opcode },
4834 { Bad_Opcode },
4835 { Bad_Opcode },
4836 { Bad_Opcode },
4837 { Bad_Opcode },
4838 { Bad_Opcode },
4839 { Bad_Opcode },
4840 /* 40 */
4841 { "dpps", { XM, EXx, Ib }, PREFIX_DATA },
4842 { "dppd", { XM, EXx, Ib }, PREFIX_DATA },
4843 { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4844 { Bad_Opcode },
4845 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4846 { Bad_Opcode },
4847 { Bad_Opcode },
4848 { Bad_Opcode },
4849 /* 48 */
4850 { Bad_Opcode },
4851 { Bad_Opcode },
4852 { Bad_Opcode },
4853 { Bad_Opcode },
4854 { Bad_Opcode },
4855 { Bad_Opcode },
4856 { Bad_Opcode },
4857 { Bad_Opcode },
4858 /* 50 */
4859 { Bad_Opcode },
4860 { Bad_Opcode },
4861 { Bad_Opcode },
4862 { Bad_Opcode },
4863 { Bad_Opcode },
4864 { Bad_Opcode },
4865 { Bad_Opcode },
4866 { Bad_Opcode },
4867 /* 58 */
4868 { Bad_Opcode },
4869 { Bad_Opcode },
4870 { Bad_Opcode },
4871 { Bad_Opcode },
4872 { Bad_Opcode },
4873 { Bad_Opcode },
4874 { Bad_Opcode },
4875 { Bad_Opcode },
4876 /* 60 */
4877 { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4878 { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4879 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
4880 { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
4881 { Bad_Opcode },
4882 { Bad_Opcode },
4883 { Bad_Opcode },
4884 { Bad_Opcode },
4885 /* 68 */
4886 { Bad_Opcode },
4887 { Bad_Opcode },
4888 { Bad_Opcode },
4889 { Bad_Opcode },
4890 { Bad_Opcode },
4891 { Bad_Opcode },
4892 { Bad_Opcode },
4893 { Bad_Opcode },
4894 /* 70 */
4895 { Bad_Opcode },
4896 { Bad_Opcode },
4897 { Bad_Opcode },
4898 { Bad_Opcode },
4899 { Bad_Opcode },
4900 { Bad_Opcode },
4901 { Bad_Opcode },
4902 { Bad_Opcode },
4903 /* 78 */
4904 { Bad_Opcode },
4905 { Bad_Opcode },
4906 { Bad_Opcode },
4907 { Bad_Opcode },
4908 { Bad_Opcode },
4909 { Bad_Opcode },
4910 { Bad_Opcode },
4911 { Bad_Opcode },
4912 /* 80 */
4913 { Bad_Opcode },
4914 { Bad_Opcode },
4915 { Bad_Opcode },
4916 { Bad_Opcode },
4917 { Bad_Opcode },
4918 { Bad_Opcode },
4919 { Bad_Opcode },
4920 { Bad_Opcode },
4921 /* 88 */
4922 { Bad_Opcode },
4923 { Bad_Opcode },
4924 { Bad_Opcode },
4925 { Bad_Opcode },
4926 { Bad_Opcode },
4927 { Bad_Opcode },
4928 { Bad_Opcode },
4929 { Bad_Opcode },
4930 /* 90 */
4931 { Bad_Opcode },
4932 { Bad_Opcode },
4933 { Bad_Opcode },
4934 { Bad_Opcode },
4935 { Bad_Opcode },
4936 { Bad_Opcode },
4937 { Bad_Opcode },
4938 { Bad_Opcode },
4939 /* 98 */
4940 { Bad_Opcode },
4941 { Bad_Opcode },
4942 { Bad_Opcode },
4943 { Bad_Opcode },
4944 { Bad_Opcode },
4945 { Bad_Opcode },
4946 { Bad_Opcode },
4947 { Bad_Opcode },
4948 /* a0 */
4949 { Bad_Opcode },
4950 { Bad_Opcode },
4951 { Bad_Opcode },
4952 { Bad_Opcode },
4953 { Bad_Opcode },
4954 { Bad_Opcode },
4955 { Bad_Opcode },
4956 { Bad_Opcode },
4957 /* a8 */
4958 { Bad_Opcode },
4959 { Bad_Opcode },
4960 { Bad_Opcode },
4961 { Bad_Opcode },
4962 { Bad_Opcode },
4963 { Bad_Opcode },
4964 { Bad_Opcode },
4965 { Bad_Opcode },
4966 /* b0 */
4967 { Bad_Opcode },
4968 { Bad_Opcode },
4969 { Bad_Opcode },
4970 { Bad_Opcode },
4971 { Bad_Opcode },
4972 { Bad_Opcode },
4973 { Bad_Opcode },
4974 { Bad_Opcode },
4975 /* b8 */
4976 { Bad_Opcode },
4977 { Bad_Opcode },
4978 { Bad_Opcode },
4979 { Bad_Opcode },
4980 { Bad_Opcode },
4981 { Bad_Opcode },
4982 { Bad_Opcode },
4983 { Bad_Opcode },
4984 /* c0 */
4985 { Bad_Opcode },
4986 { Bad_Opcode },
4987 { Bad_Opcode },
4988 { Bad_Opcode },
4989 { Bad_Opcode },
4990 { Bad_Opcode },
4991 { Bad_Opcode },
4992 { Bad_Opcode },
4993 /* c8 */
4994 { Bad_Opcode },
4995 { Bad_Opcode },
4996 { Bad_Opcode },
4997 { Bad_Opcode },
4998 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4999 { Bad_Opcode },
5000 { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
5001 { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
5002 /* d0 */
5003 { Bad_Opcode },
5004 { Bad_Opcode },
5005 { Bad_Opcode },
5006 { Bad_Opcode },
5007 { Bad_Opcode },
5008 { Bad_Opcode },
5009 { Bad_Opcode },
5010 { Bad_Opcode },
5011 /* d8 */
5012 { Bad_Opcode },
5013 { Bad_Opcode },
5014 { Bad_Opcode },
5015 { Bad_Opcode },
5016 { Bad_Opcode },
5017 { Bad_Opcode },
5018 { Bad_Opcode },
5019 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
5020 /* e0 */
5021 { Bad_Opcode },
5022 { Bad_Opcode },
5023 { Bad_Opcode },
5024 { Bad_Opcode },
5025 { Bad_Opcode },
5026 { Bad_Opcode },
5027 { Bad_Opcode },
5028 { Bad_Opcode },
5029 /* e8 */
5030 { Bad_Opcode },
5031 { Bad_Opcode },
5032 { Bad_Opcode },
5033 { Bad_Opcode },
5034 { Bad_Opcode },
5035 { Bad_Opcode },
5036 { Bad_Opcode },
5037 { Bad_Opcode },
5038 /* f0 */
5039 { PREFIX_TABLE (PREFIX_0F3A0F) },
5040 { Bad_Opcode },
5041 { Bad_Opcode },
5042 { Bad_Opcode },
5043 { Bad_Opcode },
5044 { Bad_Opcode },
5045 { Bad_Opcode },
5046 { Bad_Opcode },
5047 /* f8 */
5048 { Bad_Opcode },
5049 { Bad_Opcode },
5050 { Bad_Opcode },
5051 { Bad_Opcode },
5052 { Bad_Opcode },
5053 { Bad_Opcode },
5054 { Bad_Opcode },
5055 { Bad_Opcode },
5056 },
5057 };
5058
5059 static const struct dis386 xop_table[][256] = {
5060 /* XOP_08 */
5061 {
5062 /* 00 */
5063 { Bad_Opcode },
5064 { Bad_Opcode },
5065 { Bad_Opcode },
5066 { Bad_Opcode },
5067 { Bad_Opcode },
5068 { Bad_Opcode },
5069 { Bad_Opcode },
5070 { Bad_Opcode },
5071 /* 08 */
5072 { Bad_Opcode },
5073 { Bad_Opcode },
5074 { Bad_Opcode },
5075 { Bad_Opcode },
5076 { Bad_Opcode },
5077 { Bad_Opcode },
5078 { Bad_Opcode },
5079 { Bad_Opcode },
5080 /* 10 */
5081 { Bad_Opcode },
5082 { Bad_Opcode },
5083 { Bad_Opcode },
5084 { Bad_Opcode },
5085 { Bad_Opcode },
5086 { Bad_Opcode },
5087 { Bad_Opcode },
5088 { Bad_Opcode },
5089 /* 18 */
5090 { Bad_Opcode },
5091 { Bad_Opcode },
5092 { Bad_Opcode },
5093 { Bad_Opcode },
5094 { Bad_Opcode },
5095 { Bad_Opcode },
5096 { Bad_Opcode },
5097 { Bad_Opcode },
5098 /* 20 */
5099 { Bad_Opcode },
5100 { Bad_Opcode },
5101 { Bad_Opcode },
5102 { Bad_Opcode },
5103 { Bad_Opcode },
5104 { Bad_Opcode },
5105 { Bad_Opcode },
5106 { Bad_Opcode },
5107 /* 28 */
5108 { Bad_Opcode },
5109 { Bad_Opcode },
5110 { Bad_Opcode },
5111 { Bad_Opcode },
5112 { Bad_Opcode },
5113 { Bad_Opcode },
5114 { Bad_Opcode },
5115 { Bad_Opcode },
5116 /* 30 */
5117 { Bad_Opcode },
5118 { Bad_Opcode },
5119 { Bad_Opcode },
5120 { Bad_Opcode },
5121 { Bad_Opcode },
5122 { Bad_Opcode },
5123 { Bad_Opcode },
5124 { Bad_Opcode },
5125 /* 38 */
5126 { Bad_Opcode },
5127 { Bad_Opcode },
5128 { Bad_Opcode },
5129 { Bad_Opcode },
5130 { Bad_Opcode },
5131 { Bad_Opcode },
5132 { Bad_Opcode },
5133 { Bad_Opcode },
5134 /* 40 */
5135 { Bad_Opcode },
5136 { Bad_Opcode },
5137 { Bad_Opcode },
5138 { Bad_Opcode },
5139 { Bad_Opcode },
5140 { Bad_Opcode },
5141 { Bad_Opcode },
5142 { Bad_Opcode },
5143 /* 48 */
5144 { Bad_Opcode },
5145 { Bad_Opcode },
5146 { Bad_Opcode },
5147 { Bad_Opcode },
5148 { Bad_Opcode },
5149 { Bad_Opcode },
5150 { Bad_Opcode },
5151 { Bad_Opcode },
5152 /* 50 */
5153 { Bad_Opcode },
5154 { Bad_Opcode },
5155 { Bad_Opcode },
5156 { Bad_Opcode },
5157 { Bad_Opcode },
5158 { Bad_Opcode },
5159 { Bad_Opcode },
5160 { Bad_Opcode },
5161 /* 58 */
5162 { Bad_Opcode },
5163 { Bad_Opcode },
5164 { Bad_Opcode },
5165 { Bad_Opcode },
5166 { Bad_Opcode },
5167 { Bad_Opcode },
5168 { Bad_Opcode },
5169 { Bad_Opcode },
5170 /* 60 */
5171 { Bad_Opcode },
5172 { Bad_Opcode },
5173 { Bad_Opcode },
5174 { Bad_Opcode },
5175 { Bad_Opcode },
5176 { Bad_Opcode },
5177 { Bad_Opcode },
5178 { Bad_Opcode },
5179 /* 68 */
5180 { Bad_Opcode },
5181 { Bad_Opcode },
5182 { Bad_Opcode },
5183 { Bad_Opcode },
5184 { Bad_Opcode },
5185 { Bad_Opcode },
5186 { Bad_Opcode },
5187 { Bad_Opcode },
5188 /* 70 */
5189 { Bad_Opcode },
5190 { Bad_Opcode },
5191 { Bad_Opcode },
5192 { Bad_Opcode },
5193 { Bad_Opcode },
5194 { Bad_Opcode },
5195 { Bad_Opcode },
5196 { Bad_Opcode },
5197 /* 78 */
5198 { Bad_Opcode },
5199 { Bad_Opcode },
5200 { Bad_Opcode },
5201 { Bad_Opcode },
5202 { Bad_Opcode },
5203 { Bad_Opcode },
5204 { Bad_Opcode },
5205 { Bad_Opcode },
5206 /* 80 */
5207 { Bad_Opcode },
5208 { Bad_Opcode },
5209 { Bad_Opcode },
5210 { Bad_Opcode },
5211 { Bad_Opcode },
5212 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
5213 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
5214 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
5215 /* 88 */
5216 { Bad_Opcode },
5217 { Bad_Opcode },
5218 { Bad_Opcode },
5219 { Bad_Opcode },
5220 { Bad_Opcode },
5221 { Bad_Opcode },
5222 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
5223 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
5224 /* 90 */
5225 { Bad_Opcode },
5226 { Bad_Opcode },
5227 { Bad_Opcode },
5228 { Bad_Opcode },
5229 { Bad_Opcode },
5230 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
5231 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
5232 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
5233 /* 98 */
5234 { Bad_Opcode },
5235 { Bad_Opcode },
5236 { Bad_Opcode },
5237 { Bad_Opcode },
5238 { Bad_Opcode },
5239 { Bad_Opcode },
5240 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
5241 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
5242 /* a0 */
5243 { Bad_Opcode },
5244 { Bad_Opcode },
5245 { "vpcmov", { XM, Vex, EXx, XMVexI4 }, 0 },
5246 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
5247 { Bad_Opcode },
5248 { Bad_Opcode },
5249 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
5250 { Bad_Opcode },
5251 /* a8 */
5252 { Bad_Opcode },
5253 { Bad_Opcode },
5254 { Bad_Opcode },
5255 { Bad_Opcode },
5256 { Bad_Opcode },
5257 { Bad_Opcode },
5258 { Bad_Opcode },
5259 { Bad_Opcode },
5260 /* b0 */
5261 { Bad_Opcode },
5262 { Bad_Opcode },
5263 { Bad_Opcode },
5264 { Bad_Opcode },
5265 { Bad_Opcode },
5266 { Bad_Opcode },
5267 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
5268 { Bad_Opcode },
5269 /* b8 */
5270 { Bad_Opcode },
5271 { Bad_Opcode },
5272 { Bad_Opcode },
5273 { Bad_Opcode },
5274 { Bad_Opcode },
5275 { Bad_Opcode },
5276 { Bad_Opcode },
5277 { Bad_Opcode },
5278 /* c0 */
5279 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
5280 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
5281 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
5282 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
5283 { Bad_Opcode },
5284 { Bad_Opcode },
5285 { Bad_Opcode },
5286 { Bad_Opcode },
5287 /* c8 */
5288 { Bad_Opcode },
5289 { Bad_Opcode },
5290 { Bad_Opcode },
5291 { Bad_Opcode },
5292 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
5293 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
5294 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
5295 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
5296 /* d0 */
5297 { Bad_Opcode },
5298 { Bad_Opcode },
5299 { Bad_Opcode },
5300 { Bad_Opcode },
5301 { Bad_Opcode },
5302 { Bad_Opcode },
5303 { Bad_Opcode },
5304 { Bad_Opcode },
5305 /* d8 */
5306 { Bad_Opcode },
5307 { Bad_Opcode },
5308 { Bad_Opcode },
5309 { Bad_Opcode },
5310 { Bad_Opcode },
5311 { Bad_Opcode },
5312 { Bad_Opcode },
5313 { Bad_Opcode },
5314 /* e0 */
5315 { Bad_Opcode },
5316 { Bad_Opcode },
5317 { Bad_Opcode },
5318 { Bad_Opcode },
5319 { Bad_Opcode },
5320 { Bad_Opcode },
5321 { Bad_Opcode },
5322 { Bad_Opcode },
5323 /* e8 */
5324 { Bad_Opcode },
5325 { Bad_Opcode },
5326 { Bad_Opcode },
5327 { Bad_Opcode },
5328 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
5329 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
5330 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
5331 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
5332 /* f0 */
5333 { Bad_Opcode },
5334 { Bad_Opcode },
5335 { Bad_Opcode },
5336 { Bad_Opcode },
5337 { Bad_Opcode },
5338 { Bad_Opcode },
5339 { Bad_Opcode },
5340 { Bad_Opcode },
5341 /* f8 */
5342 { Bad_Opcode },
5343 { Bad_Opcode },
5344 { Bad_Opcode },
5345 { Bad_Opcode },
5346 { Bad_Opcode },
5347 { Bad_Opcode },
5348 { Bad_Opcode },
5349 { Bad_Opcode },
5350 },
5351 /* XOP_09 */
5352 {
5353 /* 00 */
5354 { Bad_Opcode },
5355 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
5356 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
5357 { Bad_Opcode },
5358 { Bad_Opcode },
5359 { Bad_Opcode },
5360 { Bad_Opcode },
5361 { Bad_Opcode },
5362 /* 08 */
5363 { Bad_Opcode },
5364 { Bad_Opcode },
5365 { Bad_Opcode },
5366 { Bad_Opcode },
5367 { Bad_Opcode },
5368 { Bad_Opcode },
5369 { Bad_Opcode },
5370 { Bad_Opcode },
5371 /* 10 */
5372 { Bad_Opcode },
5373 { Bad_Opcode },
5374 { MOD_TABLE (MOD_XOP_09_12) },
5375 { Bad_Opcode },
5376 { Bad_Opcode },
5377 { Bad_Opcode },
5378 { Bad_Opcode },
5379 { Bad_Opcode },
5380 /* 18 */
5381 { Bad_Opcode },
5382 { Bad_Opcode },
5383 { Bad_Opcode },
5384 { Bad_Opcode },
5385 { Bad_Opcode },
5386 { Bad_Opcode },
5387 { Bad_Opcode },
5388 { Bad_Opcode },
5389 /* 20 */
5390 { Bad_Opcode },
5391 { Bad_Opcode },
5392 { Bad_Opcode },
5393 { Bad_Opcode },
5394 { Bad_Opcode },
5395 { Bad_Opcode },
5396 { Bad_Opcode },
5397 { Bad_Opcode },
5398 /* 28 */
5399 { Bad_Opcode },
5400 { Bad_Opcode },
5401 { Bad_Opcode },
5402 { Bad_Opcode },
5403 { Bad_Opcode },
5404 { Bad_Opcode },
5405 { Bad_Opcode },
5406 { Bad_Opcode },
5407 /* 30 */
5408 { Bad_Opcode },
5409 { Bad_Opcode },
5410 { Bad_Opcode },
5411 { Bad_Opcode },
5412 { Bad_Opcode },
5413 { Bad_Opcode },
5414 { Bad_Opcode },
5415 { Bad_Opcode },
5416 /* 38 */
5417 { Bad_Opcode },
5418 { Bad_Opcode },
5419 { Bad_Opcode },
5420 { Bad_Opcode },
5421 { Bad_Opcode },
5422 { Bad_Opcode },
5423 { Bad_Opcode },
5424 { Bad_Opcode },
5425 /* 40 */
5426 { Bad_Opcode },
5427 { Bad_Opcode },
5428 { Bad_Opcode },
5429 { Bad_Opcode },
5430 { Bad_Opcode },
5431 { Bad_Opcode },
5432 { Bad_Opcode },
5433 { Bad_Opcode },
5434 /* 48 */
5435 { Bad_Opcode },
5436 { Bad_Opcode },
5437 { Bad_Opcode },
5438 { Bad_Opcode },
5439 { Bad_Opcode },
5440 { Bad_Opcode },
5441 { Bad_Opcode },
5442 { Bad_Opcode },
5443 /* 50 */
5444 { Bad_Opcode },
5445 { Bad_Opcode },
5446 { Bad_Opcode },
5447 { Bad_Opcode },
5448 { Bad_Opcode },
5449 { Bad_Opcode },
5450 { Bad_Opcode },
5451 { Bad_Opcode },
5452 /* 58 */
5453 { Bad_Opcode },
5454 { Bad_Opcode },
5455 { Bad_Opcode },
5456 { Bad_Opcode },
5457 { Bad_Opcode },
5458 { Bad_Opcode },
5459 { Bad_Opcode },
5460 { Bad_Opcode },
5461 /* 60 */
5462 { Bad_Opcode },
5463 { Bad_Opcode },
5464 { Bad_Opcode },
5465 { Bad_Opcode },
5466 { Bad_Opcode },
5467 { Bad_Opcode },
5468 { Bad_Opcode },
5469 { Bad_Opcode },
5470 /* 68 */
5471 { Bad_Opcode },
5472 { Bad_Opcode },
5473 { Bad_Opcode },
5474 { Bad_Opcode },
5475 { Bad_Opcode },
5476 { Bad_Opcode },
5477 { Bad_Opcode },
5478 { Bad_Opcode },
5479 /* 70 */
5480 { Bad_Opcode },
5481 { Bad_Opcode },
5482 { Bad_Opcode },
5483 { Bad_Opcode },
5484 { Bad_Opcode },
5485 { Bad_Opcode },
5486 { Bad_Opcode },
5487 { Bad_Opcode },
5488 /* 78 */
5489 { Bad_Opcode },
5490 { Bad_Opcode },
5491 { Bad_Opcode },
5492 { Bad_Opcode },
5493 { Bad_Opcode },
5494 { Bad_Opcode },
5495 { Bad_Opcode },
5496 { Bad_Opcode },
5497 /* 80 */
5498 { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
5499 { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
5500 { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
5501 { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
5502 { Bad_Opcode },
5503 { Bad_Opcode },
5504 { Bad_Opcode },
5505 { Bad_Opcode },
5506 /* 88 */
5507 { Bad_Opcode },
5508 { Bad_Opcode },
5509 { Bad_Opcode },
5510 { Bad_Opcode },
5511 { Bad_Opcode },
5512 { Bad_Opcode },
5513 { Bad_Opcode },
5514 { Bad_Opcode },
5515 /* 90 */
5516 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
5517 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
5518 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
5519 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
5520 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
5521 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
5522 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
5523 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
5524 /* 98 */
5525 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
5526 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
5527 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
5528 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
5529 { Bad_Opcode },
5530 { Bad_Opcode },
5531 { Bad_Opcode },
5532 { Bad_Opcode },
5533 /* a0 */
5534 { Bad_Opcode },
5535 { Bad_Opcode },
5536 { Bad_Opcode },
5537 { Bad_Opcode },
5538 { Bad_Opcode },
5539 { Bad_Opcode },
5540 { Bad_Opcode },
5541 { Bad_Opcode },
5542 /* a8 */
5543 { Bad_Opcode },
5544 { Bad_Opcode },
5545 { Bad_Opcode },
5546 { Bad_Opcode },
5547 { Bad_Opcode },
5548 { Bad_Opcode },
5549 { Bad_Opcode },
5550 { Bad_Opcode },
5551 /* b0 */
5552 { Bad_Opcode },
5553 { Bad_Opcode },
5554 { Bad_Opcode },
5555 { Bad_Opcode },
5556 { Bad_Opcode },
5557 { Bad_Opcode },
5558 { Bad_Opcode },
5559 { Bad_Opcode },
5560 /* b8 */
5561 { Bad_Opcode },
5562 { Bad_Opcode },
5563 { Bad_Opcode },
5564 { Bad_Opcode },
5565 { Bad_Opcode },
5566 { Bad_Opcode },
5567 { Bad_Opcode },
5568 { Bad_Opcode },
5569 /* c0 */
5570 { Bad_Opcode },
5571 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
5572 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
5573 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
5574 { Bad_Opcode },
5575 { Bad_Opcode },
5576 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
5577 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
5578 /* c8 */
5579 { Bad_Opcode },
5580 { Bad_Opcode },
5581 { Bad_Opcode },
5582 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
5583 { Bad_Opcode },
5584 { Bad_Opcode },
5585 { Bad_Opcode },
5586 { Bad_Opcode },
5587 /* d0 */
5588 { Bad_Opcode },
5589 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
5590 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
5591 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
5592 { Bad_Opcode },
5593 { Bad_Opcode },
5594 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
5595 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
5596 /* d8 */
5597 { Bad_Opcode },
5598 { Bad_Opcode },
5599 { Bad_Opcode },
5600 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
5601 { Bad_Opcode },
5602 { Bad_Opcode },
5603 { Bad_Opcode },
5604 { Bad_Opcode },
5605 /* e0 */
5606 { Bad_Opcode },
5607 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
5608 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
5609 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
5610 { Bad_Opcode },
5611 { Bad_Opcode },
5612 { Bad_Opcode },
5613 { Bad_Opcode },
5614 /* e8 */
5615 { Bad_Opcode },
5616 { Bad_Opcode },
5617 { Bad_Opcode },
5618 { Bad_Opcode },
5619 { Bad_Opcode },
5620 { Bad_Opcode },
5621 { Bad_Opcode },
5622 { Bad_Opcode },
5623 /* f0 */
5624 { Bad_Opcode },
5625 { Bad_Opcode },
5626 { Bad_Opcode },
5627 { Bad_Opcode },
5628 { Bad_Opcode },
5629 { Bad_Opcode },
5630 { Bad_Opcode },
5631 { Bad_Opcode },
5632 /* f8 */
5633 { Bad_Opcode },
5634 { Bad_Opcode },
5635 { Bad_Opcode },
5636 { Bad_Opcode },
5637 { Bad_Opcode },
5638 { Bad_Opcode },
5639 { Bad_Opcode },
5640 { Bad_Opcode },
5641 },
5642 /* XOP_0A */
5643 {
5644 /* 00 */
5645 { Bad_Opcode },
5646 { Bad_Opcode },
5647 { Bad_Opcode },
5648 { Bad_Opcode },
5649 { Bad_Opcode },
5650 { Bad_Opcode },
5651 { Bad_Opcode },
5652 { Bad_Opcode },
5653 /* 08 */
5654 { Bad_Opcode },
5655 { Bad_Opcode },
5656 { Bad_Opcode },
5657 { Bad_Opcode },
5658 { Bad_Opcode },
5659 { Bad_Opcode },
5660 { Bad_Opcode },
5661 { Bad_Opcode },
5662 /* 10 */
5663 { "bextrS", { Gdq, Edq, Id }, 0 },
5664 { Bad_Opcode },
5665 { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
5666 { Bad_Opcode },
5667 { Bad_Opcode },
5668 { Bad_Opcode },
5669 { Bad_Opcode },
5670 { Bad_Opcode },
5671 /* 18 */
5672 { Bad_Opcode },
5673 { Bad_Opcode },
5674 { Bad_Opcode },
5675 { Bad_Opcode },
5676 { Bad_Opcode },
5677 { Bad_Opcode },
5678 { Bad_Opcode },
5679 { Bad_Opcode },
5680 /* 20 */
5681 { Bad_Opcode },
5682 { Bad_Opcode },
5683 { Bad_Opcode },
5684 { Bad_Opcode },
5685 { Bad_Opcode },
5686 { Bad_Opcode },
5687 { Bad_Opcode },
5688 { Bad_Opcode },
5689 /* 28 */
5690 { Bad_Opcode },
5691 { Bad_Opcode },
5692 { Bad_Opcode },
5693 { Bad_Opcode },
5694 { Bad_Opcode },
5695 { Bad_Opcode },
5696 { Bad_Opcode },
5697 { Bad_Opcode },
5698 /* 30 */
5699 { Bad_Opcode },
5700 { Bad_Opcode },
5701 { Bad_Opcode },
5702 { Bad_Opcode },
5703 { Bad_Opcode },
5704 { Bad_Opcode },
5705 { Bad_Opcode },
5706 { Bad_Opcode },
5707 /* 38 */
5708 { Bad_Opcode },
5709 { Bad_Opcode },
5710 { Bad_Opcode },
5711 { Bad_Opcode },
5712 { Bad_Opcode },
5713 { Bad_Opcode },
5714 { Bad_Opcode },
5715 { Bad_Opcode },
5716 /* 40 */
5717 { Bad_Opcode },
5718 { Bad_Opcode },
5719 { Bad_Opcode },
5720 { Bad_Opcode },
5721 { Bad_Opcode },
5722 { Bad_Opcode },
5723 { Bad_Opcode },
5724 { Bad_Opcode },
5725 /* 48 */
5726 { Bad_Opcode },
5727 { Bad_Opcode },
5728 { Bad_Opcode },
5729 { Bad_Opcode },
5730 { Bad_Opcode },
5731 { Bad_Opcode },
5732 { Bad_Opcode },
5733 { Bad_Opcode },
5734 /* 50 */
5735 { Bad_Opcode },
5736 { Bad_Opcode },
5737 { Bad_Opcode },
5738 { Bad_Opcode },
5739 { Bad_Opcode },
5740 { Bad_Opcode },
5741 { Bad_Opcode },
5742 { Bad_Opcode },
5743 /* 58 */
5744 { Bad_Opcode },
5745 { Bad_Opcode },
5746 { Bad_Opcode },
5747 { Bad_Opcode },
5748 { Bad_Opcode },
5749 { Bad_Opcode },
5750 { Bad_Opcode },
5751 { Bad_Opcode },
5752 /* 60 */
5753 { Bad_Opcode },
5754 { Bad_Opcode },
5755 { Bad_Opcode },
5756 { Bad_Opcode },
5757 { Bad_Opcode },
5758 { Bad_Opcode },
5759 { Bad_Opcode },
5760 { Bad_Opcode },
5761 /* 68 */
5762 { Bad_Opcode },
5763 { Bad_Opcode },
5764 { Bad_Opcode },
5765 { Bad_Opcode },
5766 { Bad_Opcode },
5767 { Bad_Opcode },
5768 { Bad_Opcode },
5769 { Bad_Opcode },
5770 /* 70 */
5771 { Bad_Opcode },
5772 { Bad_Opcode },
5773 { Bad_Opcode },
5774 { Bad_Opcode },
5775 { Bad_Opcode },
5776 { Bad_Opcode },
5777 { Bad_Opcode },
5778 { Bad_Opcode },
5779 /* 78 */
5780 { Bad_Opcode },
5781 { Bad_Opcode },
5782 { Bad_Opcode },
5783 { Bad_Opcode },
5784 { Bad_Opcode },
5785 { Bad_Opcode },
5786 { Bad_Opcode },
5787 { Bad_Opcode },
5788 /* 80 */
5789 { Bad_Opcode },
5790 { Bad_Opcode },
5791 { Bad_Opcode },
5792 { Bad_Opcode },
5793 { Bad_Opcode },
5794 { Bad_Opcode },
5795 { Bad_Opcode },
5796 { Bad_Opcode },
5797 /* 88 */
5798 { Bad_Opcode },
5799 { Bad_Opcode },
5800 { Bad_Opcode },
5801 { Bad_Opcode },
5802 { Bad_Opcode },
5803 { Bad_Opcode },
5804 { Bad_Opcode },
5805 { Bad_Opcode },
5806 /* 90 */
5807 { Bad_Opcode },
5808 { Bad_Opcode },
5809 { Bad_Opcode },
5810 { Bad_Opcode },
5811 { Bad_Opcode },
5812 { Bad_Opcode },
5813 { Bad_Opcode },
5814 { Bad_Opcode },
5815 /* 98 */
5816 { Bad_Opcode },
5817 { Bad_Opcode },
5818 { Bad_Opcode },
5819 { Bad_Opcode },
5820 { Bad_Opcode },
5821 { Bad_Opcode },
5822 { Bad_Opcode },
5823 { Bad_Opcode },
5824 /* a0 */
5825 { Bad_Opcode },
5826 { Bad_Opcode },
5827 { Bad_Opcode },
5828 { Bad_Opcode },
5829 { Bad_Opcode },
5830 { Bad_Opcode },
5831 { Bad_Opcode },
5832 { Bad_Opcode },
5833 /* a8 */
5834 { Bad_Opcode },
5835 { Bad_Opcode },
5836 { Bad_Opcode },
5837 { Bad_Opcode },
5838 { Bad_Opcode },
5839 { Bad_Opcode },
5840 { Bad_Opcode },
5841 { Bad_Opcode },
5842 /* b0 */
5843 { Bad_Opcode },
5844 { Bad_Opcode },
5845 { Bad_Opcode },
5846 { Bad_Opcode },
5847 { Bad_Opcode },
5848 { Bad_Opcode },
5849 { Bad_Opcode },
5850 { Bad_Opcode },
5851 /* b8 */
5852 { Bad_Opcode },
5853 { Bad_Opcode },
5854 { Bad_Opcode },
5855 { Bad_Opcode },
5856 { Bad_Opcode },
5857 { Bad_Opcode },
5858 { Bad_Opcode },
5859 { Bad_Opcode },
5860 /* c0 */
5861 { Bad_Opcode },
5862 { Bad_Opcode },
5863 { Bad_Opcode },
5864 { Bad_Opcode },
5865 { Bad_Opcode },
5866 { Bad_Opcode },
5867 { Bad_Opcode },
5868 { Bad_Opcode },
5869 /* c8 */
5870 { Bad_Opcode },
5871 { Bad_Opcode },
5872 { Bad_Opcode },
5873 { Bad_Opcode },
5874 { Bad_Opcode },
5875 { Bad_Opcode },
5876 { Bad_Opcode },
5877 { Bad_Opcode },
5878 /* d0 */
5879 { Bad_Opcode },
5880 { Bad_Opcode },
5881 { Bad_Opcode },
5882 { Bad_Opcode },
5883 { Bad_Opcode },
5884 { Bad_Opcode },
5885 { Bad_Opcode },
5886 { Bad_Opcode },
5887 /* d8 */
5888 { Bad_Opcode },
5889 { Bad_Opcode },
5890 { Bad_Opcode },
5891 { Bad_Opcode },
5892 { Bad_Opcode },
5893 { Bad_Opcode },
5894 { Bad_Opcode },
5895 { Bad_Opcode },
5896 /* e0 */
5897 { Bad_Opcode },
5898 { Bad_Opcode },
5899 { Bad_Opcode },
5900 { Bad_Opcode },
5901 { Bad_Opcode },
5902 { Bad_Opcode },
5903 { Bad_Opcode },
5904 { Bad_Opcode },
5905 /* e8 */
5906 { Bad_Opcode },
5907 { Bad_Opcode },
5908 { Bad_Opcode },
5909 { Bad_Opcode },
5910 { Bad_Opcode },
5911 { Bad_Opcode },
5912 { Bad_Opcode },
5913 { Bad_Opcode },
5914 /* f0 */
5915 { Bad_Opcode },
5916 { Bad_Opcode },
5917 { Bad_Opcode },
5918 { Bad_Opcode },
5919 { Bad_Opcode },
5920 { Bad_Opcode },
5921 { Bad_Opcode },
5922 { Bad_Opcode },
5923 /* f8 */
5924 { Bad_Opcode },
5925 { Bad_Opcode },
5926 { Bad_Opcode },
5927 { Bad_Opcode },
5928 { Bad_Opcode },
5929 { Bad_Opcode },
5930 { Bad_Opcode },
5931 { Bad_Opcode },
5932 },
5933 };
5934
5935 static const struct dis386 vex_table[][256] = {
5936 /* VEX_0F */
5937 {
5938 /* 00 */
5939 { Bad_Opcode },
5940 { Bad_Opcode },
5941 { Bad_Opcode },
5942 { Bad_Opcode },
5943 { Bad_Opcode },
5944 { Bad_Opcode },
5945 { Bad_Opcode },
5946 { Bad_Opcode },
5947 /* 08 */
5948 { Bad_Opcode },
5949 { Bad_Opcode },
5950 { Bad_Opcode },
5951 { Bad_Opcode },
5952 { Bad_Opcode },
5953 { Bad_Opcode },
5954 { Bad_Opcode },
5955 { Bad_Opcode },
5956 /* 10 */
5957 { PREFIX_TABLE (PREFIX_0F10) },
5958 { PREFIX_TABLE (PREFIX_0F11) },
5959 { PREFIX_TABLE (PREFIX_VEX_0F12) },
5960 { VEX_LEN_TABLE (VEX_LEN_0F13) },
5961 { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5962 { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5963 { PREFIX_TABLE (PREFIX_VEX_0F16) },
5964 { VEX_LEN_TABLE (VEX_LEN_0F17) },
5965 /* 18 */
5966 { Bad_Opcode },
5967 { Bad_Opcode },
5968 { Bad_Opcode },
5969 { Bad_Opcode },
5970 { Bad_Opcode },
5971 { Bad_Opcode },
5972 { Bad_Opcode },
5973 { Bad_Opcode },
5974 /* 20 */
5975 { Bad_Opcode },
5976 { Bad_Opcode },
5977 { Bad_Opcode },
5978 { Bad_Opcode },
5979 { Bad_Opcode },
5980 { Bad_Opcode },
5981 { Bad_Opcode },
5982 { Bad_Opcode },
5983 /* 28 */
5984 { "vmovapX", { XM, EXx }, PREFIX_OPCODE },
5985 { "vmovapX", { EXxS, XM }, PREFIX_OPCODE },
5986 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
5987 { MOD_TABLE (MOD_VEX_0F2B) },
5988 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
5989 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
5990 { PREFIX_TABLE (PREFIX_0F2E) },
5991 { PREFIX_TABLE (PREFIX_0F2F) },
5992 /* 30 */
5993 { Bad_Opcode },
5994 { Bad_Opcode },
5995 { Bad_Opcode },
5996 { Bad_Opcode },
5997 { Bad_Opcode },
5998 { Bad_Opcode },
5999 { Bad_Opcode },
6000 { Bad_Opcode },
6001 /* 38 */
6002 { Bad_Opcode },
6003 { Bad_Opcode },
6004 { Bad_Opcode },
6005 { Bad_Opcode },
6006 { Bad_Opcode },
6007 { Bad_Opcode },
6008 { Bad_Opcode },
6009 { Bad_Opcode },
6010 /* 40 */
6011 { Bad_Opcode },
6012 { VEX_LEN_TABLE (VEX_LEN_0F41) },
6013 { VEX_LEN_TABLE (VEX_LEN_0F42) },
6014 { Bad_Opcode },
6015 { VEX_LEN_TABLE (VEX_LEN_0F44) },
6016 { VEX_LEN_TABLE (VEX_LEN_0F45) },
6017 { VEX_LEN_TABLE (VEX_LEN_0F46) },
6018 { VEX_LEN_TABLE (VEX_LEN_0F47) },
6019 /* 48 */
6020 { Bad_Opcode },
6021 { Bad_Opcode },
6022 { VEX_LEN_TABLE (VEX_LEN_0F4A) },
6023 { VEX_LEN_TABLE (VEX_LEN_0F4B) },
6024 { Bad_Opcode },
6025 { Bad_Opcode },
6026 { Bad_Opcode },
6027 { Bad_Opcode },
6028 /* 50 */
6029 { MOD_TABLE (MOD_0F50) },
6030 { PREFIX_TABLE (PREFIX_0F51) },
6031 { PREFIX_TABLE (PREFIX_0F52) },
6032 { PREFIX_TABLE (PREFIX_0F53) },
6033 { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6034 { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6035 { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6036 { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6037 /* 58 */
6038 { PREFIX_TABLE (PREFIX_0F58) },
6039 { PREFIX_TABLE (PREFIX_0F59) },
6040 { PREFIX_TABLE (PREFIX_0F5A) },
6041 { PREFIX_TABLE (PREFIX_0F5B) },
6042 { PREFIX_TABLE (PREFIX_0F5C) },
6043 { PREFIX_TABLE (PREFIX_0F5D) },
6044 { PREFIX_TABLE (PREFIX_0F5E) },
6045 { PREFIX_TABLE (PREFIX_0F5F) },
6046 /* 60 */
6047 { "vpunpcklbw", { XM, Vex, EXx }, PREFIX_DATA },
6048 { "vpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA },
6049 { "vpunpckldq", { XM, Vex, EXx }, PREFIX_DATA },
6050 { "vpacksswb", { XM, Vex, EXx }, PREFIX_DATA },
6051 { "vpcmpgtb", { XM, Vex, EXx }, PREFIX_DATA },
6052 { "vpcmpgtw", { XM, Vex, EXx }, PREFIX_DATA },
6053 { "vpcmpgtd", { XM, Vex, EXx }, PREFIX_DATA },
6054 { "vpackuswb", { XM, Vex, EXx }, PREFIX_DATA },
6055 /* 68 */
6056 { "vpunpckhbw", { XM, Vex, EXx }, PREFIX_DATA },
6057 { "vpunpckhwd", { XM, Vex, EXx }, PREFIX_DATA },
6058 { "vpunpckhdq", { XM, Vex, EXx }, PREFIX_DATA },
6059 { "vpackssdw", { XM, Vex, EXx }, PREFIX_DATA },
6060 { "vpunpcklqdq", { XM, Vex, EXx }, PREFIX_DATA },
6061 { "vpunpckhqdq", { XM, Vex, EXx }, PREFIX_DATA },
6062 { VEX_LEN_TABLE (VEX_LEN_0F6E) },
6063 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
6064 /* 70 */
6065 { PREFIX_TABLE (PREFIX_VEX_0F70) },
6066 { MOD_TABLE (MOD_VEX_0F71) },
6067 { MOD_TABLE (MOD_VEX_0F72) },
6068 { MOD_TABLE (MOD_VEX_0F73) },
6069 { "vpcmpeqb", { XM, Vex, EXx }, PREFIX_DATA },
6070 { "vpcmpeqw", { XM, Vex, EXx }, PREFIX_DATA },
6071 { "vpcmpeqd", { XM, Vex, EXx }, PREFIX_DATA },
6072 { VEX_LEN_TABLE (VEX_LEN_0F77) },
6073 /* 78 */
6074 { Bad_Opcode },
6075 { Bad_Opcode },
6076 { Bad_Opcode },
6077 { Bad_Opcode },
6078 { PREFIX_TABLE (PREFIX_0F7C) },
6079 { PREFIX_TABLE (PREFIX_0F7D) },
6080 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
6081 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
6082 /* 80 */
6083 { Bad_Opcode },
6084 { Bad_Opcode },
6085 { Bad_Opcode },
6086 { Bad_Opcode },
6087 { Bad_Opcode },
6088 { Bad_Opcode },
6089 { Bad_Opcode },
6090 { Bad_Opcode },
6091 /* 88 */
6092 { Bad_Opcode },
6093 { Bad_Opcode },
6094 { Bad_Opcode },
6095 { Bad_Opcode },
6096 { Bad_Opcode },
6097 { Bad_Opcode },
6098 { Bad_Opcode },
6099 { Bad_Opcode },
6100 /* 90 */
6101 { VEX_LEN_TABLE (VEX_LEN_0F90) },
6102 { VEX_LEN_TABLE (VEX_LEN_0F91) },
6103 { VEX_LEN_TABLE (VEX_LEN_0F92) },
6104 { VEX_LEN_TABLE (VEX_LEN_0F93) },
6105 { Bad_Opcode },
6106 { Bad_Opcode },
6107 { Bad_Opcode },
6108 { Bad_Opcode },
6109 /* 98 */
6110 { VEX_LEN_TABLE (VEX_LEN_0F98) },
6111 { VEX_LEN_TABLE (VEX_LEN_0F99) },
6112 { Bad_Opcode },
6113 { Bad_Opcode },
6114 { Bad_Opcode },
6115 { Bad_Opcode },
6116 { Bad_Opcode },
6117 { Bad_Opcode },
6118 /* a0 */
6119 { Bad_Opcode },
6120 { Bad_Opcode },
6121 { Bad_Opcode },
6122 { Bad_Opcode },
6123 { Bad_Opcode },
6124 { Bad_Opcode },
6125 { Bad_Opcode },
6126 { Bad_Opcode },
6127 /* a8 */
6128 { Bad_Opcode },
6129 { Bad_Opcode },
6130 { Bad_Opcode },
6131 { Bad_Opcode },
6132 { Bad_Opcode },
6133 { Bad_Opcode },
6134 { REG_TABLE (REG_VEX_0FAE) },
6135 { Bad_Opcode },
6136 /* b0 */
6137 { Bad_Opcode },
6138 { Bad_Opcode },
6139 { Bad_Opcode },
6140 { Bad_Opcode },
6141 { Bad_Opcode },
6142 { Bad_Opcode },
6143 { Bad_Opcode },
6144 { Bad_Opcode },
6145 /* b8 */
6146 { Bad_Opcode },
6147 { Bad_Opcode },
6148 { Bad_Opcode },
6149 { Bad_Opcode },
6150 { Bad_Opcode },
6151 { Bad_Opcode },
6152 { Bad_Opcode },
6153 { Bad_Opcode },
6154 /* c0 */
6155 { Bad_Opcode },
6156 { Bad_Opcode },
6157 { PREFIX_TABLE (PREFIX_0FC2) },
6158 { Bad_Opcode },
6159 { VEX_LEN_TABLE (VEX_LEN_0FC4) },
6160 { VEX_LEN_TABLE (VEX_LEN_0FC5) },
6161 { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6162 { Bad_Opcode },
6163 /* c8 */
6164 { Bad_Opcode },
6165 { Bad_Opcode },
6166 { Bad_Opcode },
6167 { Bad_Opcode },
6168 { Bad_Opcode },
6169 { Bad_Opcode },
6170 { Bad_Opcode },
6171 { Bad_Opcode },
6172 /* d0 */
6173 { PREFIX_TABLE (PREFIX_0FD0) },
6174 { "vpsrlw", { XM, Vex, EXxmm }, PREFIX_DATA },
6175 { "vpsrld", { XM, Vex, EXxmm }, PREFIX_DATA },
6176 { "vpsrlq", { XM, Vex, EXxmm }, PREFIX_DATA },
6177 { "vpaddq", { XM, Vex, EXx }, PREFIX_DATA },
6178 { "vpmullw", { XM, Vex, EXx }, PREFIX_DATA },
6179 { VEX_LEN_TABLE (VEX_LEN_0FD6) },
6180 { MOD_TABLE (MOD_VEX_0FD7) },
6181 /* d8 */
6182 { "vpsubusb", { XM, Vex, EXx }, PREFIX_DATA },
6183 { "vpsubusw", { XM, Vex, EXx }, PREFIX_DATA },
6184 { "vpminub", { XM, Vex, EXx }, PREFIX_DATA },
6185 { "vpand", { XM, Vex, EXx }, PREFIX_DATA },
6186 { "vpaddusb", { XM, Vex, EXx }, PREFIX_DATA },
6187 { "vpaddusw", { XM, Vex, EXx }, PREFIX_DATA },
6188 { "vpmaxub", { XM, Vex, EXx }, PREFIX_DATA },
6189 { "vpandn", { XM, Vex, EXx }, PREFIX_DATA },
6190 /* e0 */
6191 { "vpavgb", { XM, Vex, EXx }, PREFIX_DATA },
6192 { "vpsraw", { XM, Vex, EXxmm }, PREFIX_DATA },
6193 { "vpsrad", { XM, Vex, EXxmm }, PREFIX_DATA },
6194 { "vpavgw", { XM, Vex, EXx }, PREFIX_DATA },
6195 { "vpmulhuw", { XM, Vex, EXx }, PREFIX_DATA },
6196 { "vpmulhw", { XM, Vex, EXx }, PREFIX_DATA },
6197 { PREFIX_TABLE (PREFIX_0FE6) },
6198 { MOD_TABLE (MOD_VEX_0FE7) },
6199 /* e8 */
6200 { "vpsubsb", { XM, Vex, EXx }, PREFIX_DATA },
6201 { "vpsubsw", { XM, Vex, EXx }, PREFIX_DATA },
6202 { "vpminsw", { XM, Vex, EXx }, PREFIX_DATA },
6203 { "vpor", { XM, Vex, EXx }, PREFIX_DATA },
6204 { "vpaddsb", { XM, Vex, EXx }, PREFIX_DATA },
6205 { "vpaddsw", { XM, Vex, EXx }, PREFIX_DATA },
6206 { "vpmaxsw", { XM, Vex, EXx }, PREFIX_DATA },
6207 { "vpxor", { XM, Vex, EXx }, PREFIX_DATA },
6208 /* f0 */
6209 { PREFIX_TABLE (PREFIX_0FF0) },
6210 { "vpsllw", { XM, Vex, EXxmm }, PREFIX_DATA },
6211 { "vpslld", { XM, Vex, EXxmm }, PREFIX_DATA },
6212 { "vpsllq", { XM, Vex, EXxmm }, PREFIX_DATA },
6213 { "vpmuludq", { XM, Vex, EXx }, PREFIX_DATA },
6214 { "vpmaddwd", { XM, Vex, EXx }, PREFIX_DATA },
6215 { "vpsadbw", { XM, Vex, EXx }, PREFIX_DATA },
6216 { VEX_LEN_TABLE (VEX_LEN_0FF7) },
6217 /* f8 */
6218 { "vpsubb", { XM, Vex, EXx }, PREFIX_DATA },
6219 { "vpsubw", { XM, Vex, EXx }, PREFIX_DATA },
6220 { "vpsubd", { XM, Vex, EXx }, PREFIX_DATA },
6221 { "vpsubq", { XM, Vex, EXx }, PREFIX_DATA },
6222 { "vpaddb", { XM, Vex, EXx }, PREFIX_DATA },
6223 { "vpaddw", { XM, Vex, EXx }, PREFIX_DATA },
6224 { "vpaddd", { XM, Vex, EXx }, PREFIX_DATA },
6225 { Bad_Opcode },
6226 },
6227 /* VEX_0F38 */
6228 {
6229 /* 00 */
6230 { "vpshufb", { XM, Vex, EXx }, PREFIX_DATA },
6231 { "vphaddw", { XM, Vex, EXx }, PREFIX_DATA },
6232 { "vphaddd", { XM, Vex, EXx }, PREFIX_DATA },
6233 { "vphaddsw", { XM, Vex, EXx }, PREFIX_DATA },
6234 { "vpmaddubsw", { XM, Vex, EXx }, PREFIX_DATA },
6235 { "vphsubw", { XM, Vex, EXx }, PREFIX_DATA },
6236 { "vphsubd", { XM, Vex, EXx }, PREFIX_DATA },
6237 { "vphsubsw", { XM, Vex, EXx }, PREFIX_DATA },
6238 /* 08 */
6239 { "vpsignb", { XM, Vex, EXx }, PREFIX_DATA },
6240 { "vpsignw", { XM, Vex, EXx }, PREFIX_DATA },
6241 { "vpsignd", { XM, Vex, EXx }, PREFIX_DATA },
6242 { "vpmulhrsw", { XM, Vex, EXx }, PREFIX_DATA },
6243 { VEX_W_TABLE (VEX_W_0F380C) },
6244 { VEX_W_TABLE (VEX_W_0F380D) },
6245 { VEX_W_TABLE (VEX_W_0F380E) },
6246 { VEX_W_TABLE (VEX_W_0F380F) },
6247 /* 10 */
6248 { Bad_Opcode },
6249 { Bad_Opcode },
6250 { Bad_Opcode },
6251 { VEX_W_TABLE (VEX_W_0F3813) },
6252 { Bad_Opcode },
6253 { Bad_Opcode },
6254 { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6255 { "vptest", { XM, EXx }, PREFIX_DATA },
6256 /* 18 */
6257 { VEX_W_TABLE (VEX_W_0F3818) },
6258 { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6259 { MOD_TABLE (MOD_VEX_0F381A) },
6260 { Bad_Opcode },
6261 { "vpabsb", { XM, EXx }, PREFIX_DATA },
6262 { "vpabsw", { XM, EXx }, PREFIX_DATA },
6263 { "vpabsd", { XM, EXx }, PREFIX_DATA },
6264 { Bad_Opcode },
6265 /* 20 */
6266 { "vpmovsxbw", { XM, EXxmmq }, PREFIX_DATA },
6267 { "vpmovsxbd", { XM, EXxmmqd }, PREFIX_DATA },
6268 { "vpmovsxbq", { XM, EXxmmdw }, PREFIX_DATA },
6269 { "vpmovsxwd", { XM, EXxmmq }, PREFIX_DATA },
6270 { "vpmovsxwq", { XM, EXxmmqd }, PREFIX_DATA },
6271 { "vpmovsxdq", { XM, EXxmmq }, PREFIX_DATA },
6272 { Bad_Opcode },
6273 { Bad_Opcode },
6274 /* 28 */
6275 { "vpmuldq", { XM, Vex, EXx }, PREFIX_DATA },
6276 { "vpcmpeqq", { XM, Vex, EXx }, PREFIX_DATA },
6277 { MOD_TABLE (MOD_VEX_0F382A) },
6278 { "vpackusdw", { XM, Vex, EXx }, PREFIX_DATA },
6279 { MOD_TABLE (MOD_VEX_0F382C) },
6280 { MOD_TABLE (MOD_VEX_0F382D) },
6281 { MOD_TABLE (MOD_VEX_0F382E) },
6282 { MOD_TABLE (MOD_VEX_0F382F) },
6283 /* 30 */
6284 { "vpmovzxbw", { XM, EXxmmq }, PREFIX_DATA },
6285 { "vpmovzxbd", { XM, EXxmmqd }, PREFIX_DATA },
6286 { "vpmovzxbq", { XM, EXxmmdw }, PREFIX_DATA },
6287 { "vpmovzxwd", { XM, EXxmmq }, PREFIX_DATA },
6288 { "vpmovzxwq", { XM, EXxmmqd }, PREFIX_DATA },
6289 { "vpmovzxdq", { XM, EXxmmq }, PREFIX_DATA },
6290 { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6291 { "vpcmpgtq", { XM, Vex, EXx }, PREFIX_DATA },
6292 /* 38 */
6293 { "vpminsb", { XM, Vex, EXx }, PREFIX_DATA },
6294 { "vpminsd", { XM, Vex, EXx }, PREFIX_DATA },
6295 { "vpminuw", { XM, Vex, EXx }, PREFIX_DATA },
6296 { "vpminud", { XM, Vex, EXx }, PREFIX_DATA },
6297 { "vpmaxsb", { XM, Vex, EXx }, PREFIX_DATA },
6298 { "vpmaxsd", { XM, Vex, EXx }, PREFIX_DATA },
6299 { "vpmaxuw", { XM, Vex, EXx }, PREFIX_DATA },
6300 { "vpmaxud", { XM, Vex, EXx }, PREFIX_DATA },
6301 /* 40 */
6302 { "vpmulld", { XM, Vex, EXx }, PREFIX_DATA },
6303 { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6304 { Bad_Opcode },
6305 { Bad_Opcode },
6306 { Bad_Opcode },
6307 { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6308 { VEX_W_TABLE (VEX_W_0F3846) },
6309 { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6310 /* 48 */
6311 { Bad_Opcode },
6312 { X86_64_TABLE (X86_64_VEX_0F3849) },
6313 { Bad_Opcode },
6314 { X86_64_TABLE (X86_64_VEX_0F384B) },
6315 { Bad_Opcode },
6316 { Bad_Opcode },
6317 { Bad_Opcode },
6318 { Bad_Opcode },
6319 /* 50 */
6320 { VEX_W_TABLE (VEX_W_0F3850) },
6321 { VEX_W_TABLE (VEX_W_0F3851) },
6322 { VEX_W_TABLE (VEX_W_0F3852) },
6323 { VEX_W_TABLE (VEX_W_0F3853) },
6324 { Bad_Opcode },
6325 { Bad_Opcode },
6326 { Bad_Opcode },
6327 { Bad_Opcode },
6328 /* 58 */
6329 { VEX_W_TABLE (VEX_W_0F3858) },
6330 { VEX_W_TABLE (VEX_W_0F3859) },
6331 { MOD_TABLE (MOD_VEX_0F385A) },
6332 { Bad_Opcode },
6333 { X86_64_TABLE (X86_64_VEX_0F385C) },
6334 { Bad_Opcode },
6335 { X86_64_TABLE (X86_64_VEX_0F385E) },
6336 { Bad_Opcode },
6337 /* 60 */
6338 { Bad_Opcode },
6339 { Bad_Opcode },
6340 { Bad_Opcode },
6341 { Bad_Opcode },
6342 { Bad_Opcode },
6343 { Bad_Opcode },
6344 { Bad_Opcode },
6345 { Bad_Opcode },
6346 /* 68 */
6347 { Bad_Opcode },
6348 { Bad_Opcode },
6349 { Bad_Opcode },
6350 { Bad_Opcode },
6351 { X86_64_TABLE (X86_64_VEX_0F386C) },
6352 { Bad_Opcode },
6353 { Bad_Opcode },
6354 { Bad_Opcode },
6355 /* 70 */
6356 { Bad_Opcode },
6357 { Bad_Opcode },
6358 { PREFIX_TABLE (PREFIX_VEX_0F3872) },
6359 { Bad_Opcode },
6360 { Bad_Opcode },
6361 { Bad_Opcode },
6362 { Bad_Opcode },
6363 { Bad_Opcode },
6364 /* 78 */
6365 { VEX_W_TABLE (VEX_W_0F3878) },
6366 { VEX_W_TABLE (VEX_W_0F3879) },
6367 { Bad_Opcode },
6368 { Bad_Opcode },
6369 { Bad_Opcode },
6370 { Bad_Opcode },
6371 { Bad_Opcode },
6372 { Bad_Opcode },
6373 /* 80 */
6374 { Bad_Opcode },
6375 { Bad_Opcode },
6376 { Bad_Opcode },
6377 { Bad_Opcode },
6378 { Bad_Opcode },
6379 { Bad_Opcode },
6380 { Bad_Opcode },
6381 { Bad_Opcode },
6382 /* 88 */
6383 { Bad_Opcode },
6384 { Bad_Opcode },
6385 { Bad_Opcode },
6386 { Bad_Opcode },
6387 { MOD_TABLE (MOD_VEX_0F388C) },
6388 { Bad_Opcode },
6389 { MOD_TABLE (MOD_VEX_0F388E) },
6390 { Bad_Opcode },
6391 /* 90 */
6392 { "vpgatherd%DQ", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6393 { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6394 { "vgatherdp%XW", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6395 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6396 { Bad_Opcode },
6397 { Bad_Opcode },
6398 { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6399 { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6400 /* 98 */
6401 { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6402 { "vfmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6403 { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6404 { "vfmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6405 { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6406 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6407 { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6408 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6409 /* a0 */
6410 { Bad_Opcode },
6411 { Bad_Opcode },
6412 { Bad_Opcode },
6413 { Bad_Opcode },
6414 { Bad_Opcode },
6415 { Bad_Opcode },
6416 { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6417 { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6418 /* a8 */
6419 { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6420 { "vfmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6421 { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6422 { "vfmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6423 { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6424 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6425 { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6426 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6427 /* b0 */
6428 { VEX_W_TABLE (VEX_W_0F38B0) },
6429 { VEX_W_TABLE (VEX_W_0F38B1) },
6430 { Bad_Opcode },
6431 { Bad_Opcode },
6432 { VEX_W_TABLE (VEX_W_0F38B4) },
6433 { VEX_W_TABLE (VEX_W_0F38B5) },
6434 { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6435 { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6436 /* b8 */
6437 { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6438 { "vfmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6439 { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6440 { "vfmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6441 { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6442 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6443 { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6444 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6445 /* c0 */
6446 { Bad_Opcode },
6447 { Bad_Opcode },
6448 { Bad_Opcode },
6449 { Bad_Opcode },
6450 { Bad_Opcode },
6451 { Bad_Opcode },
6452 { Bad_Opcode },
6453 { Bad_Opcode },
6454 /* c8 */
6455 { Bad_Opcode },
6456 { Bad_Opcode },
6457 { Bad_Opcode },
6458 { Bad_Opcode },
6459 { Bad_Opcode },
6460 { Bad_Opcode },
6461 { Bad_Opcode },
6462 { VEX_W_TABLE (VEX_W_0F38CF) },
6463 /* d0 */
6464 { Bad_Opcode },
6465 { Bad_Opcode },
6466 { Bad_Opcode },
6467 { Bad_Opcode },
6468 { Bad_Opcode },
6469 { Bad_Opcode },
6470 { Bad_Opcode },
6471 { Bad_Opcode },
6472 /* d8 */
6473 { Bad_Opcode },
6474 { Bad_Opcode },
6475 { Bad_Opcode },
6476 { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6477 { "vaesenc", { XM, Vex, EXx }, PREFIX_DATA },
6478 { "vaesenclast", { XM, Vex, EXx }, PREFIX_DATA },
6479 { "vaesdec", { XM, Vex, EXx }, PREFIX_DATA },
6480 { "vaesdeclast", { XM, Vex, EXx }, PREFIX_DATA },
6481 /* e0 */
6482 { X86_64_TABLE (X86_64_VEX_0F38E0) },
6483 { X86_64_TABLE (X86_64_VEX_0F38E1) },
6484 { X86_64_TABLE (X86_64_VEX_0F38E2) },
6485 { X86_64_TABLE (X86_64_VEX_0F38E3) },
6486 { X86_64_TABLE (X86_64_VEX_0F38E4) },
6487 { X86_64_TABLE (X86_64_VEX_0F38E5) },
6488 { X86_64_TABLE (X86_64_VEX_0F38E6) },
6489 { X86_64_TABLE (X86_64_VEX_0F38E7) },
6490 /* e8 */
6491 { X86_64_TABLE (X86_64_VEX_0F38E8) },
6492 { X86_64_TABLE (X86_64_VEX_0F38E9) },
6493 { X86_64_TABLE (X86_64_VEX_0F38EA) },
6494 { X86_64_TABLE (X86_64_VEX_0F38EB) },
6495 { X86_64_TABLE (X86_64_VEX_0F38EC) },
6496 { X86_64_TABLE (X86_64_VEX_0F38ED) },
6497 { X86_64_TABLE (X86_64_VEX_0F38EE) },
6498 { X86_64_TABLE (X86_64_VEX_0F38EF) },
6499 /* f0 */
6500 { Bad_Opcode },
6501 { Bad_Opcode },
6502 { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6503 { VEX_LEN_TABLE (VEX_LEN_0F38F3) },
6504 { Bad_Opcode },
6505 { VEX_LEN_TABLE (VEX_LEN_0F38F5) },
6506 { VEX_LEN_TABLE (VEX_LEN_0F38F6) },
6507 { VEX_LEN_TABLE (VEX_LEN_0F38F7) },
6508 /* f8 */
6509 { Bad_Opcode },
6510 { Bad_Opcode },
6511 { Bad_Opcode },
6512 { Bad_Opcode },
6513 { Bad_Opcode },
6514 { Bad_Opcode },
6515 { Bad_Opcode },
6516 { Bad_Opcode },
6517 },
6518 /* VEX_0F3A */
6519 {
6520 /* 00 */
6521 { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6522 { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6523 { VEX_W_TABLE (VEX_W_0F3A02) },
6524 { Bad_Opcode },
6525 { VEX_W_TABLE (VEX_W_0F3A04) },
6526 { VEX_W_TABLE (VEX_W_0F3A05) },
6527 { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6528 { Bad_Opcode },
6529 /* 08 */
6530 { "vroundps", { XM, EXx, Ib }, PREFIX_DATA },
6531 { "vroundpd", { XM, EXx, Ib }, PREFIX_DATA },
6532 { "vroundss", { XMScalar, VexScalar, EXd, Ib }, PREFIX_DATA },
6533 { "vroundsd", { XMScalar, VexScalar, EXq, Ib }, PREFIX_DATA },
6534 { "vblendps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6535 { "vblendpd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6536 { "vpblendw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6537 { "vpalignr", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6538 /* 10 */
6539 { Bad_Opcode },
6540 { Bad_Opcode },
6541 { Bad_Opcode },
6542 { Bad_Opcode },
6543 { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6544 { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6545 { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6546 { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6547 /* 18 */
6548 { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6549 { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6550 { Bad_Opcode },
6551 { Bad_Opcode },
6552 { Bad_Opcode },
6553 { VEX_W_TABLE (VEX_W_0F3A1D) },
6554 { Bad_Opcode },
6555 { Bad_Opcode },
6556 /* 20 */
6557 { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6558 { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6559 { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6560 { Bad_Opcode },
6561 { Bad_Opcode },
6562 { Bad_Opcode },
6563 { Bad_Opcode },
6564 { Bad_Opcode },
6565 /* 28 */
6566 { Bad_Opcode },
6567 { Bad_Opcode },
6568 { Bad_Opcode },
6569 { Bad_Opcode },
6570 { Bad_Opcode },
6571 { Bad_Opcode },
6572 { Bad_Opcode },
6573 { Bad_Opcode },
6574 /* 30 */
6575 { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6576 { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6577 { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6578 { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6579 { Bad_Opcode },
6580 { Bad_Opcode },
6581 { Bad_Opcode },
6582 { Bad_Opcode },
6583 /* 38 */
6584 { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6585 { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6586 { Bad_Opcode },
6587 { Bad_Opcode },
6588 { Bad_Opcode },
6589 { Bad_Opcode },
6590 { Bad_Opcode },
6591 { Bad_Opcode },
6592 /* 40 */
6593 { "vdpps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6594 { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6595 { "vmpsadbw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6596 { Bad_Opcode },
6597 { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6598 { Bad_Opcode },
6599 { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6600 { Bad_Opcode },
6601 /* 48 */
6602 { "vpermil2ps", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6603 { "vpermil2pd", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6604 { VEX_W_TABLE (VEX_W_0F3A4A) },
6605 { VEX_W_TABLE (VEX_W_0F3A4B) },
6606 { VEX_W_TABLE (VEX_W_0F3A4C) },
6607 { Bad_Opcode },
6608 { Bad_Opcode },
6609 { Bad_Opcode },
6610 /* 50 */
6611 { Bad_Opcode },
6612 { Bad_Opcode },
6613 { Bad_Opcode },
6614 { Bad_Opcode },
6615 { Bad_Opcode },
6616 { Bad_Opcode },
6617 { Bad_Opcode },
6618 { Bad_Opcode },
6619 /* 58 */
6620 { Bad_Opcode },
6621 { Bad_Opcode },
6622 { Bad_Opcode },
6623 { Bad_Opcode },
6624 { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6625 { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6626 { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6627 { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6628 /* 60 */
6629 { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6630 { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6631 { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6632 { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6633 { Bad_Opcode },
6634 { Bad_Opcode },
6635 { Bad_Opcode },
6636 { Bad_Opcode },
6637 /* 68 */
6638 { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6639 { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6640 { "vfmaddss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6641 { "vfmaddsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6642 { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6643 { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6644 { "vfmsubss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6645 { "vfmsubsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6646 /* 70 */
6647 { Bad_Opcode },
6648 { Bad_Opcode },
6649 { Bad_Opcode },
6650 { Bad_Opcode },
6651 { Bad_Opcode },
6652 { Bad_Opcode },
6653 { Bad_Opcode },
6654 { Bad_Opcode },
6655 /* 78 */
6656 { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6657 { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6658 { "vfnmaddss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6659 { "vfnmaddsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6660 { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6661 { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6662 { "vfnmsubss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6663 { "vfnmsubsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6664 /* 80 */
6665 { Bad_Opcode },
6666 { Bad_Opcode },
6667 { Bad_Opcode },
6668 { Bad_Opcode },
6669 { Bad_Opcode },
6670 { Bad_Opcode },
6671 { Bad_Opcode },
6672 { Bad_Opcode },
6673 /* 88 */
6674 { Bad_Opcode },
6675 { Bad_Opcode },
6676 { Bad_Opcode },
6677 { Bad_Opcode },
6678 { Bad_Opcode },
6679 { Bad_Opcode },
6680 { Bad_Opcode },
6681 { Bad_Opcode },
6682 /* 90 */
6683 { Bad_Opcode },
6684 { Bad_Opcode },
6685 { Bad_Opcode },
6686 { Bad_Opcode },
6687 { Bad_Opcode },
6688 { Bad_Opcode },
6689 { Bad_Opcode },
6690 { Bad_Opcode },
6691 /* 98 */
6692 { Bad_Opcode },
6693 { Bad_Opcode },
6694 { Bad_Opcode },
6695 { Bad_Opcode },
6696 { Bad_Opcode },
6697 { Bad_Opcode },
6698 { Bad_Opcode },
6699 { Bad_Opcode },
6700 /* a0 */
6701 { Bad_Opcode },
6702 { Bad_Opcode },
6703 { Bad_Opcode },
6704 { Bad_Opcode },
6705 { Bad_Opcode },
6706 { Bad_Opcode },
6707 { Bad_Opcode },
6708 { Bad_Opcode },
6709 /* a8 */
6710 { Bad_Opcode },
6711 { Bad_Opcode },
6712 { Bad_Opcode },
6713 { Bad_Opcode },
6714 { Bad_Opcode },
6715 { Bad_Opcode },
6716 { Bad_Opcode },
6717 { Bad_Opcode },
6718 /* b0 */
6719 { Bad_Opcode },
6720 { Bad_Opcode },
6721 { Bad_Opcode },
6722 { Bad_Opcode },
6723 { Bad_Opcode },
6724 { Bad_Opcode },
6725 { Bad_Opcode },
6726 { Bad_Opcode },
6727 /* b8 */
6728 { Bad_Opcode },
6729 { Bad_Opcode },
6730 { Bad_Opcode },
6731 { Bad_Opcode },
6732 { Bad_Opcode },
6733 { Bad_Opcode },
6734 { Bad_Opcode },
6735 { Bad_Opcode },
6736 /* c0 */
6737 { Bad_Opcode },
6738 { Bad_Opcode },
6739 { Bad_Opcode },
6740 { Bad_Opcode },
6741 { Bad_Opcode },
6742 { Bad_Opcode },
6743 { Bad_Opcode },
6744 { Bad_Opcode },
6745 /* c8 */
6746 { Bad_Opcode },
6747 { Bad_Opcode },
6748 { Bad_Opcode },
6749 { Bad_Opcode },
6750 { Bad_Opcode },
6751 { Bad_Opcode },
6752 { VEX_W_TABLE (VEX_W_0F3ACE) },
6753 { VEX_W_TABLE (VEX_W_0F3ACF) },
6754 /* d0 */
6755 { Bad_Opcode },
6756 { Bad_Opcode },
6757 { Bad_Opcode },
6758 { Bad_Opcode },
6759 { Bad_Opcode },
6760 { Bad_Opcode },
6761 { Bad_Opcode },
6762 { Bad_Opcode },
6763 /* d8 */
6764 { Bad_Opcode },
6765 { Bad_Opcode },
6766 { Bad_Opcode },
6767 { Bad_Opcode },
6768 { Bad_Opcode },
6769 { Bad_Opcode },
6770 { Bad_Opcode },
6771 { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6772 /* e0 */
6773 { Bad_Opcode },
6774 { Bad_Opcode },
6775 { Bad_Opcode },
6776 { Bad_Opcode },
6777 { Bad_Opcode },
6778 { Bad_Opcode },
6779 { Bad_Opcode },
6780 { Bad_Opcode },
6781 /* e8 */
6782 { Bad_Opcode },
6783 { Bad_Opcode },
6784 { Bad_Opcode },
6785 { Bad_Opcode },
6786 { Bad_Opcode },
6787 { Bad_Opcode },
6788 { Bad_Opcode },
6789 { Bad_Opcode },
6790 /* f0 */
6791 { VEX_LEN_TABLE (VEX_LEN_0F3AF0) },
6792 { Bad_Opcode },
6793 { Bad_Opcode },
6794 { Bad_Opcode },
6795 { Bad_Opcode },
6796 { Bad_Opcode },
6797 { Bad_Opcode },
6798 { Bad_Opcode },
6799 /* f8 */
6800 { Bad_Opcode },
6801 { Bad_Opcode },
6802 { Bad_Opcode },
6803 { Bad_Opcode },
6804 { Bad_Opcode },
6805 { Bad_Opcode },
6806 { Bad_Opcode },
6807 { Bad_Opcode },
6808 },
6809 };
6810
6811 #include "i386-dis-evex.h"
6812
6813 static const struct dis386 vex_len_table[][2] = {
6814 /* VEX_LEN_0F12_P_0 */
6815 {
6816 { MOD_TABLE (MOD_0F12_PREFIX_0) },
6817 },
6818
6819 /* VEX_LEN_0F12_P_2 */
6820 {
6821 { MOD_TABLE (MOD_0F12_PREFIX_2) },
6822 },
6823
6824 /* VEX_LEN_0F13 */
6825 {
6826 { MOD_TABLE (MOD_0F13) },
6827 },
6828
6829 /* VEX_LEN_0F16_P_0 */
6830 {
6831 { MOD_TABLE (MOD_0F16_PREFIX_0) },
6832 },
6833
6834 /* VEX_LEN_0F16_P_2 */
6835 {
6836 { MOD_TABLE (MOD_0F16_PREFIX_2) },
6837 },
6838
6839 /* VEX_LEN_0F17 */
6840 {
6841 { MOD_TABLE (MOD_0F17) },
6842 },
6843
6844 /* VEX_LEN_0F41 */
6845 {
6846 { Bad_Opcode },
6847 { MOD_TABLE (MOD_VEX_0F41_L_1) },
6848 },
6849
6850 /* VEX_LEN_0F42 */
6851 {
6852 { Bad_Opcode },
6853 { MOD_TABLE (MOD_VEX_0F42_L_1) },
6854 },
6855
6856 /* VEX_LEN_0F44 */
6857 {
6858 { MOD_TABLE (MOD_VEX_0F44_L_0) },
6859 },
6860
6861 /* VEX_LEN_0F45 */
6862 {
6863 { Bad_Opcode },
6864 { MOD_TABLE (MOD_VEX_0F45_L_1) },
6865 },
6866
6867 /* VEX_LEN_0F46 */
6868 {
6869 { Bad_Opcode },
6870 { MOD_TABLE (MOD_VEX_0F46_L_1) },
6871 },
6872
6873 /* VEX_LEN_0F47 */
6874 {
6875 { Bad_Opcode },
6876 { MOD_TABLE (MOD_VEX_0F47_L_1) },
6877 },
6878
6879 /* VEX_LEN_0F4A */
6880 {
6881 { Bad_Opcode },
6882 { MOD_TABLE (MOD_VEX_0F4A_L_1) },
6883 },
6884
6885 /* VEX_LEN_0F4B */
6886 {
6887 { Bad_Opcode },
6888 { MOD_TABLE (MOD_VEX_0F4B_L_1) },
6889 },
6890
6891 /* VEX_LEN_0F6E */
6892 {
6893 { "%XEvmovYK", { XMScalar, Edq }, PREFIX_DATA },
6894 },
6895
6896 /* VEX_LEN_0F77 */
6897 {
6898 { "vzeroupper", { XX }, 0 },
6899 { "vzeroall", { XX }, 0 },
6900 },
6901
6902 /* VEX_LEN_0F7E_P_1 */
6903 {
6904 { "%XEvmovqY", { XMScalar, EXq }, 0 },
6905 },
6906
6907 /* VEX_LEN_0F7E_P_2 */
6908 {
6909 { "%XEvmovK", { Edq, XMScalar }, 0 },
6910 },
6911
6912 /* VEX_LEN_0F90 */
6913 {
6914 { VEX_W_TABLE (VEX_W_0F90_L_0) },
6915 },
6916
6917 /* VEX_LEN_0F91 */
6918 {
6919 { MOD_TABLE (MOD_VEX_0F91_L_0) },
6920 },
6921
6922 /* VEX_LEN_0F92 */
6923 {
6924 { MOD_TABLE (MOD_VEX_0F92_L_0) },
6925 },
6926
6927 /* VEX_LEN_0F93 */
6928 {
6929 { MOD_TABLE (MOD_VEX_0F93_L_0) },
6930 },
6931
6932 /* VEX_LEN_0F98 */
6933 {
6934 { MOD_TABLE (MOD_VEX_0F98_L_0) },
6935 },
6936
6937 /* VEX_LEN_0F99 */
6938 {
6939 { MOD_TABLE (MOD_VEX_0F99_L_0) },
6940 },
6941
6942 /* VEX_LEN_0FAE_R_2_M_0 */
6943 {
6944 { "vldmxcsr", { Md }, 0 },
6945 },
6946
6947 /* VEX_LEN_0FAE_R_3_M_0 */
6948 {
6949 { "vstmxcsr", { Md }, 0 },
6950 },
6951
6952 /* VEX_LEN_0FC4 */
6953 {
6954 { "%XEvpinsrwY", { XM, Vex, Edw, Ib }, PREFIX_DATA },
6955 },
6956
6957 /* VEX_LEN_0FC5 */
6958 {
6959 { "%XEvpextrw", { Gd, XS, Ib }, PREFIX_DATA },
6960 },
6961
6962 /* VEX_LEN_0FD6 */
6963 {
6964 { "%XEvmovqY", { EXqS, XMScalar }, PREFIX_DATA },
6965 },
6966
6967 /* VEX_LEN_0FF7 */
6968 {
6969 { "vmaskmovdqu", { XM, XS }, PREFIX_DATA },
6970 },
6971
6972 /* VEX_LEN_0F3816 */
6973 {
6974 { Bad_Opcode },
6975 { VEX_W_TABLE (VEX_W_0F3816_L_1) },
6976 },
6977
6978 /* VEX_LEN_0F3819 */
6979 {
6980 { Bad_Opcode },
6981 { VEX_W_TABLE (VEX_W_0F3819_L_1) },
6982 },
6983
6984 /* VEX_LEN_0F381A_M_0 */
6985 {
6986 { Bad_Opcode },
6987 { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) },
6988 },
6989
6990 /* VEX_LEN_0F3836 */
6991 {
6992 { Bad_Opcode },
6993 { VEX_W_TABLE (VEX_W_0F3836) },
6994 },
6995
6996 /* VEX_LEN_0F3841 */
6997 {
6998 { "vphminposuw", { XM, EXx }, PREFIX_DATA },
6999 },
7000
7001 /* VEX_LEN_0F3849_X86_64 */
7002 {
7003 { VEX_W_TABLE (VEX_W_0F3849_X86_64_L_0) },
7004 },
7005
7006 /* VEX_LEN_0F384B_X86_64 */
7007 {
7008 { VEX_W_TABLE (VEX_W_0F384B_X86_64_L_0) },
7009 },
7010
7011 /* VEX_LEN_0F385A_M_0 */
7012 {
7013 { Bad_Opcode },
7014 { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) },
7015 },
7016
7017 /* VEX_LEN_0F385C_X86_64_M_1 */
7018 {
7019 { VEX_W_TABLE (VEX_W_0F385C_X86_64_M_1_L_0) },
7020 },
7021
7022 /* VEX_LEN_0F385E_X86_64_M_1 */
7023 {
7024 { VEX_W_TABLE (VEX_W_0F385E_X86_64_M_1_L_0) },
7025 },
7026
7027 /* VEX_LEN_0F386C_X86_64_M_1 */
7028 {
7029 { VEX_W_TABLE (VEX_W_0F386C_X86_64_M_1_L_0) },
7030 },
7031
7032 /* VEX_LEN_0F38DB */
7033 {
7034 { "vaesimc", { XM, EXx }, PREFIX_DATA },
7035 },
7036
7037 /* VEX_LEN_0F38F2 */
7038 {
7039 { "andnS", { Gdq, VexGdq, Edq }, PREFIX_OPCODE },
7040 },
7041
7042 /* VEX_LEN_0F38F3 */
7043 {
7044 { REG_TABLE(REG_VEX_0F38F3_L_0) },
7045 },
7046
7047 /* VEX_LEN_0F38F5 */
7048 {
7049 { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0) },
7050 },
7051
7052 /* VEX_LEN_0F38F6 */
7053 {
7054 { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0) },
7055 },
7056
7057 /* VEX_LEN_0F38F7 */
7058 {
7059 { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0) },
7060 },
7061
7062 /* VEX_LEN_0F3A00 */
7063 {
7064 { Bad_Opcode },
7065 { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
7066 },
7067
7068 /* VEX_LEN_0F3A01 */
7069 {
7070 { Bad_Opcode },
7071 { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
7072 },
7073
7074 /* VEX_LEN_0F3A06 */
7075 {
7076 { Bad_Opcode },
7077 { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
7078 },
7079
7080 /* VEX_LEN_0F3A14 */
7081 {
7082 { "%XEvpextrb", { Edb, XM, Ib }, PREFIX_DATA },
7083 },
7084
7085 /* VEX_LEN_0F3A15 */
7086 {
7087 { "%XEvpextrw", { Edw, XM, Ib }, PREFIX_DATA },
7088 },
7089
7090 /* VEX_LEN_0F3A16 */
7091 {
7092 { "%XEvpextrK", { Edq, XM, Ib }, PREFIX_DATA },
7093 },
7094
7095 /* VEX_LEN_0F3A17 */
7096 {
7097 { "%XEvextractps", { Ed, XM, Ib }, PREFIX_DATA },
7098 },
7099
7100 /* VEX_LEN_0F3A18 */
7101 {
7102 { Bad_Opcode },
7103 { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
7104 },
7105
7106 /* VEX_LEN_0F3A19 */
7107 {
7108 { Bad_Opcode },
7109 { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7110 },
7111
7112 /* VEX_LEN_0F3A20 */
7113 {
7114 { "%XEvpinsrbY", { XM, Vex, Edb, Ib }, PREFIX_DATA },
7115 },
7116
7117 /* VEX_LEN_0F3A21 */
7118 {
7119 { "%XEvinsertpsY", { XM, Vex, EXd, Ib }, PREFIX_DATA },
7120 },
7121
7122 /* VEX_LEN_0F3A22 */
7123 {
7124 { "%XEvpinsrYK", { XM, Vex, Edq, Ib }, PREFIX_DATA },
7125 },
7126
7127 /* VEX_LEN_0F3A30 */
7128 {
7129 { MOD_TABLE (MOD_VEX_0F3A30_L_0) },
7130 },
7131
7132 /* VEX_LEN_0F3A31 */
7133 {
7134 { MOD_TABLE (MOD_VEX_0F3A31_L_0) },
7135 },
7136
7137 /* VEX_LEN_0F3A32 */
7138 {
7139 { MOD_TABLE (MOD_VEX_0F3A32_L_0) },
7140 },
7141
7142 /* VEX_LEN_0F3A33 */
7143 {
7144 { MOD_TABLE (MOD_VEX_0F3A33_L_0) },
7145 },
7146
7147 /* VEX_LEN_0F3A38 */
7148 {
7149 { Bad_Opcode },
7150 { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7151 },
7152
7153 /* VEX_LEN_0F3A39 */
7154 {
7155 { Bad_Opcode },
7156 { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7157 },
7158
7159 /* VEX_LEN_0F3A41 */
7160 {
7161 { "vdppd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7162 },
7163
7164 /* VEX_LEN_0F3A46 */
7165 {
7166 { Bad_Opcode },
7167 { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7168 },
7169
7170 /* VEX_LEN_0F3A60 */
7171 {
7172 { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7173 },
7174
7175 /* VEX_LEN_0F3A61 */
7176 {
7177 { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7178 },
7179
7180 /* VEX_LEN_0F3A62 */
7181 {
7182 { "vpcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
7183 },
7184
7185 /* VEX_LEN_0F3A63 */
7186 {
7187 { "vpcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
7188 },
7189
7190 /* VEX_LEN_0F3ADF */
7191 {
7192 { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7193 },
7194
7195 /* VEX_LEN_0F3AF0 */
7196 {
7197 { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
7198 },
7199
7200 /* VEX_LEN_0FXOP_08_85 */
7201 {
7202 { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
7203 },
7204
7205 /* VEX_LEN_0FXOP_08_86 */
7206 {
7207 { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
7208 },
7209
7210 /* VEX_LEN_0FXOP_08_87 */
7211 {
7212 { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
7213 },
7214
7215 /* VEX_LEN_0FXOP_08_8E */
7216 {
7217 { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
7218 },
7219
7220 /* VEX_LEN_0FXOP_08_8F */
7221 {
7222 { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
7223 },
7224
7225 /* VEX_LEN_0FXOP_08_95 */
7226 {
7227 { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
7228 },
7229
7230 /* VEX_LEN_0FXOP_08_96 */
7231 {
7232 { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
7233 },
7234
7235 /* VEX_LEN_0FXOP_08_97 */
7236 {
7237 { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
7238 },
7239
7240 /* VEX_LEN_0FXOP_08_9E */
7241 {
7242 { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
7243 },
7244
7245 /* VEX_LEN_0FXOP_08_9F */
7246 {
7247 { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
7248 },
7249
7250 /* VEX_LEN_0FXOP_08_A3 */
7251 {
7252 { "vpperm", { XM, Vex, EXx, XMVexI4 }, 0 },
7253 },
7254
7255 /* VEX_LEN_0FXOP_08_A6 */
7256 {
7257 { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
7258 },
7259
7260 /* VEX_LEN_0FXOP_08_B6 */
7261 {
7262 { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
7263 },
7264
7265 /* VEX_LEN_0FXOP_08_C0 */
7266 {
7267 { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
7268 },
7269
7270 /* VEX_LEN_0FXOP_08_C1 */
7271 {
7272 { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
7273 },
7274
7275 /* VEX_LEN_0FXOP_08_C2 */
7276 {
7277 { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
7278 },
7279
7280 /* VEX_LEN_0FXOP_08_C3 */
7281 {
7282 { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
7283 },
7284
7285 /* VEX_LEN_0FXOP_08_CC */
7286 {
7287 { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
7288 },
7289
7290 /* VEX_LEN_0FXOP_08_CD */
7291 {
7292 { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
7293 },
7294
7295 /* VEX_LEN_0FXOP_08_CE */
7296 {
7297 { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
7298 },
7299
7300 /* VEX_LEN_0FXOP_08_CF */
7301 {
7302 { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
7303 },
7304
7305 /* VEX_LEN_0FXOP_08_EC */
7306 {
7307 { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
7308 },
7309
7310 /* VEX_LEN_0FXOP_08_ED */
7311 {
7312 { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
7313 },
7314
7315 /* VEX_LEN_0FXOP_08_EE */
7316 {
7317 { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
7318 },
7319
7320 /* VEX_LEN_0FXOP_08_EF */
7321 {
7322 { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
7323 },
7324
7325 /* VEX_LEN_0FXOP_09_01 */
7326 {
7327 { REG_TABLE (REG_XOP_09_01_L_0) },
7328 },
7329
7330 /* VEX_LEN_0FXOP_09_02 */
7331 {
7332 { REG_TABLE (REG_XOP_09_02_L_0) },
7333 },
7334
7335 /* VEX_LEN_0FXOP_09_12_M_1 */
7336 {
7337 { REG_TABLE (REG_XOP_09_12_M_1_L_0) },
7338 },
7339
7340 /* VEX_LEN_0FXOP_09_82_W_0 */
7341 {
7342 { "vfrczss", { XM, EXd }, 0 },
7343 },
7344
7345 /* VEX_LEN_0FXOP_09_83_W_0 */
7346 {
7347 { "vfrczsd", { XM, EXq }, 0 },
7348 },
7349
7350 /* VEX_LEN_0FXOP_09_90 */
7351 {
7352 { "vprotb", { XM, EXx, VexW }, 0 },
7353 },
7354
7355 /* VEX_LEN_0FXOP_09_91 */
7356 {
7357 { "vprotw", { XM, EXx, VexW }, 0 },
7358 },
7359
7360 /* VEX_LEN_0FXOP_09_92 */
7361 {
7362 { "vprotd", { XM, EXx, VexW }, 0 },
7363 },
7364
7365 /* VEX_LEN_0FXOP_09_93 */
7366 {
7367 { "vprotq", { XM, EXx, VexW }, 0 },
7368 },
7369
7370 /* VEX_LEN_0FXOP_09_94 */
7371 {
7372 { "vpshlb", { XM, EXx, VexW }, 0 },
7373 },
7374
7375 /* VEX_LEN_0FXOP_09_95 */
7376 {
7377 { "vpshlw", { XM, EXx, VexW }, 0 },
7378 },
7379
7380 /* VEX_LEN_0FXOP_09_96 */
7381 {
7382 { "vpshld", { XM, EXx, VexW }, 0 },
7383 },
7384
7385 /* VEX_LEN_0FXOP_09_97 */
7386 {
7387 { "vpshlq", { XM, EXx, VexW }, 0 },
7388 },
7389
7390 /* VEX_LEN_0FXOP_09_98 */
7391 {
7392 { "vpshab", { XM, EXx, VexW }, 0 },
7393 },
7394
7395 /* VEX_LEN_0FXOP_09_99 */
7396 {
7397 { "vpshaw", { XM, EXx, VexW }, 0 },
7398 },
7399
7400 /* VEX_LEN_0FXOP_09_9A */
7401 {
7402 { "vpshad", { XM, EXx, VexW }, 0 },
7403 },
7404
7405 /* VEX_LEN_0FXOP_09_9B */
7406 {
7407 { "vpshaq", { XM, EXx, VexW }, 0 },
7408 },
7409
7410 /* VEX_LEN_0FXOP_09_C1 */
7411 {
7412 { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
7413 },
7414
7415 /* VEX_LEN_0FXOP_09_C2 */
7416 {
7417 { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
7418 },
7419
7420 /* VEX_LEN_0FXOP_09_C3 */
7421 {
7422 { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
7423 },
7424
7425 /* VEX_LEN_0FXOP_09_C6 */
7426 {
7427 { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
7428 },
7429
7430 /* VEX_LEN_0FXOP_09_C7 */
7431 {
7432 { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
7433 },
7434
7435 /* VEX_LEN_0FXOP_09_CB */
7436 {
7437 { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
7438 },
7439
7440 /* VEX_LEN_0FXOP_09_D1 */
7441 {
7442 { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
7443 },
7444
7445 /* VEX_LEN_0FXOP_09_D2 */
7446 {
7447 { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
7448 },
7449
7450 /* VEX_LEN_0FXOP_09_D3 */
7451 {
7452 { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
7453 },
7454
7455 /* VEX_LEN_0FXOP_09_D6 */
7456 {
7457 { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
7458 },
7459
7460 /* VEX_LEN_0FXOP_09_D7 */
7461 {
7462 { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
7463 },
7464
7465 /* VEX_LEN_0FXOP_09_DB */
7466 {
7467 { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
7468 },
7469
7470 /* VEX_LEN_0FXOP_09_E1 */
7471 {
7472 { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
7473 },
7474
7475 /* VEX_LEN_0FXOP_09_E2 */
7476 {
7477 { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
7478 },
7479
7480 /* VEX_LEN_0FXOP_09_E3 */
7481 {
7482 { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
7483 },
7484
7485 /* VEX_LEN_0FXOP_0A_12 */
7486 {
7487 { REG_TABLE (REG_XOP_0A_12_L_0) },
7488 },
7489 };
7490
7491 #include "i386-dis-evex-len.h"
7492
7493 static const struct dis386 vex_w_table[][2] = {
7494 {
7495 /* VEX_W_0F41_L_1_M_1 */
7496 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_0) },
7497 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_1) },
7498 },
7499 {
7500 /* VEX_W_0F42_L_1_M_1 */
7501 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_0) },
7502 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_1) },
7503 },
7504 {
7505 /* VEX_W_0F44_L_0_M_1 */
7506 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_0) },
7507 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_1) },
7508 },
7509 {
7510 /* VEX_W_0F45_L_1_M_1 */
7511 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_0) },
7512 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_1) },
7513 },
7514 {
7515 /* VEX_W_0F46_L_1_M_1 */
7516 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_0) },
7517 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_1) },
7518 },
7519 {
7520 /* VEX_W_0F47_L_1_M_1 */
7521 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_0) },
7522 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_1) },
7523 },
7524 {
7525 /* VEX_W_0F4A_L_1_M_1 */
7526 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_0) },
7527 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_1) },
7528 },
7529 {
7530 /* VEX_W_0F4B_L_1_M_1 */
7531 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_0) },
7532 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_1) },
7533 },
7534 {
7535 /* VEX_W_0F90_L_0 */
7536 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0) },
7537 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1) },
7538 },
7539 {
7540 /* VEX_W_0F91_L_0_M_0 */
7541 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_0) },
7542 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_1) },
7543 },
7544 {
7545 /* VEX_W_0F92_L_0_M_1 */
7546 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_0) },
7547 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_1) },
7548 },
7549 {
7550 /* VEX_W_0F93_L_0_M_1 */
7551 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_0) },
7552 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_1) },
7553 },
7554 {
7555 /* VEX_W_0F98_L_0_M_1 */
7556 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_0) },
7557 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_1) },
7558 },
7559 {
7560 /* VEX_W_0F99_L_0_M_1 */
7561 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_0) },
7562 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_1) },
7563 },
7564 {
7565 /* VEX_W_0F380C */
7566 { "%XEvpermilps", { XM, Vex, EXx }, PREFIX_DATA },
7567 },
7568 {
7569 /* VEX_W_0F380D */
7570 { "vpermilpd", { XM, Vex, EXx }, PREFIX_DATA },
7571 },
7572 {
7573 /* VEX_W_0F380E */
7574 { "vtestps", { XM, EXx }, PREFIX_DATA },
7575 },
7576 {
7577 /* VEX_W_0F380F */
7578 { "vtestpd", { XM, EXx }, PREFIX_DATA },
7579 },
7580 {
7581 /* VEX_W_0F3813 */
7582 { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7583 },
7584 {
7585 /* VEX_W_0F3816_L_1 */
7586 { "vpermps", { XM, Vex, EXx }, PREFIX_DATA },
7587 },
7588 {
7589 /* VEX_W_0F3818 */
7590 { "%XEvbroadcastss", { XM, EXd }, PREFIX_DATA },
7591 },
7592 {
7593 /* VEX_W_0F3819_L_1 */
7594 { "vbroadcastsd", { XM, EXq }, PREFIX_DATA },
7595 },
7596 {
7597 /* VEX_W_0F381A_M_0_L_1 */
7598 { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7599 },
7600 {
7601 /* VEX_W_0F382C_M_0 */
7602 { "vmaskmovps", { XM, Vex, Mx }, PREFIX_DATA },
7603 },
7604 {
7605 /* VEX_W_0F382D_M_0 */
7606 { "vmaskmovpd", { XM, Vex, Mx }, PREFIX_DATA },
7607 },
7608 {
7609 /* VEX_W_0F382E_M_0 */
7610 { "vmaskmovps", { Mx, Vex, XM }, PREFIX_DATA },
7611 },
7612 {
7613 /* VEX_W_0F382F_M_0 */
7614 { "vmaskmovpd", { Mx, Vex, XM }, PREFIX_DATA },
7615 },
7616 {
7617 /* VEX_W_0F3836 */
7618 { "vpermd", { XM, Vex, EXx }, PREFIX_DATA },
7619 },
7620 {
7621 /* VEX_W_0F3846 */
7622 { "vpsravd", { XM, Vex, EXx }, PREFIX_DATA },
7623 },
7624 {
7625 /* VEX_W_0F3849_X86_64_L_0 */
7626 { MOD_TABLE (MOD_VEX_0F3849_X86_64_L_0_W_0) },
7627 },
7628 {
7629 /* VEX_W_0F384B_X86_64_L_0 */
7630 { MOD_TABLE (MOD_VEX_0F384B_X86_64_L_0_W_0) },
7631 },
7632 {
7633 /* VEX_W_0F3850 */
7634 { PREFIX_TABLE (PREFIX_VEX_0F3850_W_0) },
7635 },
7636 {
7637 /* VEX_W_0F3851 */
7638 { PREFIX_TABLE (PREFIX_VEX_0F3851_W_0) },
7639 },
7640 {
7641 /* VEX_W_0F3852 */
7642 { "%XVvpdpwssd", { XM, Vex, EXx }, PREFIX_DATA },
7643 },
7644 {
7645 /* VEX_W_0F3853 */
7646 { "%XVvpdpwssds", { XM, Vex, EXx }, PREFIX_DATA },
7647 },
7648 {
7649 /* VEX_W_0F3858 */
7650 { "%XEvpbroadcastd", { XM, EXd }, PREFIX_DATA },
7651 },
7652 {
7653 /* VEX_W_0F3859 */
7654 { "vpbroadcastq", { XM, EXq }, PREFIX_DATA },
7655 },
7656 {
7657 /* VEX_W_0F385A_M_0_L_0 */
7658 { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7659 },
7660 {
7661 /* VEX_W_0F385C_X86_64_M_1_L_0 */
7662 { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64_M_1_L_0_W_0) },
7663 },
7664 {
7665 /* VEX_W_0F385E_X86_64_M_1_L_0 */
7666 { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64_M_1_L_0_W_0) },
7667 },
7668 {
7669 /* VEX_W_0F386C_X86_64_M_1_L_0 */
7670 { PREFIX_TABLE (PREFIX_VEX_0F386C_X86_64_M_1_L_0_W_0) },
7671 },
7672 {
7673 /* VEX_W_0F3872_P_1 */
7674 { "%XVvcvtneps2bf16%XY", { XMM, EXx }, 0 },
7675 },
7676 {
7677 /* VEX_W_0F3878 */
7678 { "%XEvpbroadcastb", { XM, EXb }, PREFIX_DATA },
7679 },
7680 {
7681 /* VEX_W_0F3879 */
7682 { "%XEvpbroadcastw", { XM, EXw }, PREFIX_DATA },
7683 },
7684 {
7685 /* VEX_W_0F38B0 */
7686 { PREFIX_TABLE (PREFIX_VEX_0F38B0_W_0) },
7687 },
7688 {
7689 /* VEX_W_0F38B1 */
7690 { PREFIX_TABLE (PREFIX_VEX_0F38B1_W_0) },
7691 },
7692 {
7693 /* VEX_W_0F38B4 */
7694 { Bad_Opcode },
7695 { "%XVvpmadd52luq", { XM, Vex, EXx }, PREFIX_DATA },
7696 },
7697 {
7698 /* VEX_W_0F38B5 */
7699 { Bad_Opcode },
7700 { "%XVvpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA },
7701 },
7702 {
7703 /* VEX_W_0F38CF */
7704 { "%XEvgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7705 },
7706 {
7707 /* VEX_W_0F3A00_L_1 */
7708 { Bad_Opcode },
7709 { "%XEvpermq", { XM, EXx, Ib }, PREFIX_DATA },
7710 },
7711 {
7712 /* VEX_W_0F3A01_L_1 */
7713 { Bad_Opcode },
7714 { "%XEvpermpd", { XM, EXx, Ib }, PREFIX_DATA },
7715 },
7716 {
7717 /* VEX_W_0F3A02 */
7718 { "vpblendd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7719 },
7720 {
7721 /* VEX_W_0F3A04 */
7722 { "%XEvpermilps", { XM, EXx, Ib }, PREFIX_DATA },
7723 },
7724 {
7725 /* VEX_W_0F3A05 */
7726 { "vpermilpd", { XM, EXx, Ib }, PREFIX_DATA },
7727 },
7728 {
7729 /* VEX_W_0F3A06_L_1 */
7730 { "vperm2f128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7731 },
7732 {
7733 /* VEX_W_0F3A18_L_1 */
7734 { "vinsertf128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7735 },
7736 {
7737 /* VEX_W_0F3A19_L_1 */
7738 { "vextractf128", { EXxmm, XM, Ib }, PREFIX_DATA },
7739 },
7740 {
7741 /* VEX_W_0F3A1D */
7742 { "%XEvcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7743 },
7744 {
7745 /* VEX_W_0F3A38_L_1 */
7746 { "vinserti128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7747 },
7748 {
7749 /* VEX_W_0F3A39_L_1 */
7750 { "vextracti128", { EXxmm, XM, Ib }, PREFIX_DATA },
7751 },
7752 {
7753 /* VEX_W_0F3A46_L_1 */
7754 { "vperm2i128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7755 },
7756 {
7757 /* VEX_W_0F3A4A */
7758 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7759 },
7760 {
7761 /* VEX_W_0F3A4B */
7762 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7763 },
7764 {
7765 /* VEX_W_0F3A4C */
7766 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7767 },
7768 {
7769 /* VEX_W_0F3ACE */
7770 { Bad_Opcode },
7771 { "%XEvgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7772 },
7773 {
7774 /* VEX_W_0F3ACF */
7775 { Bad_Opcode },
7776 { "%XEvgf2p8affineinvqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7777 },
7778 /* VEX_W_0FXOP_08_85_L_0 */
7779 {
7780 { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 },
7781 },
7782 /* VEX_W_0FXOP_08_86_L_0 */
7783 {
7784 { "vpmacsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7785 },
7786 /* VEX_W_0FXOP_08_87_L_0 */
7787 {
7788 { "vpmacssdql", { XM, Vex, EXx, XMVexI4 }, 0 },
7789 },
7790 /* VEX_W_0FXOP_08_8E_L_0 */
7791 {
7792 { "vpmacssdd", { XM, Vex, EXx, XMVexI4 }, 0 },
7793 },
7794 /* VEX_W_0FXOP_08_8F_L_0 */
7795 {
7796 { "vpmacssdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
7797 },
7798 /* VEX_W_0FXOP_08_95_L_0 */
7799 {
7800 { "vpmacsww", { XM, Vex, EXx, XMVexI4 }, 0 },
7801 },
7802 /* VEX_W_0FXOP_08_96_L_0 */
7803 {
7804 { "vpmacswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7805 },
7806 /* VEX_W_0FXOP_08_97_L_0 */
7807 {
7808 { "vpmacsdql", { XM, Vex, EXx, XMVexI4 }, 0 },
7809 },
7810 /* VEX_W_0FXOP_08_9E_L_0 */
7811 {
7812 { "vpmacsdd", { XM, Vex, EXx, XMVexI4 }, 0 },
7813 },
7814 /* VEX_W_0FXOP_08_9F_L_0 */
7815 {
7816 { "vpmacsdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
7817 },
7818 /* VEX_W_0FXOP_08_A6_L_0 */
7819 {
7820 { "vpmadcsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7821 },
7822 /* VEX_W_0FXOP_08_B6_L_0 */
7823 {
7824 { "vpmadcswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7825 },
7826 /* VEX_W_0FXOP_08_C0_L_0 */
7827 {
7828 { "vprotb", { XM, EXx, Ib }, 0 },
7829 },
7830 /* VEX_W_0FXOP_08_C1_L_0 */
7831 {
7832 { "vprotw", { XM, EXx, Ib }, 0 },
7833 },
7834 /* VEX_W_0FXOP_08_C2_L_0 */
7835 {
7836 { "vprotd", { XM, EXx, Ib }, 0 },
7837 },
7838 /* VEX_W_0FXOP_08_C3_L_0 */
7839 {
7840 { "vprotq", { XM, EXx, Ib }, 0 },
7841 },
7842 /* VEX_W_0FXOP_08_CC_L_0 */
7843 {
7844 { "vpcomb", { XM, Vex, EXx, VPCOM }, 0 },
7845 },
7846 /* VEX_W_0FXOP_08_CD_L_0 */
7847 {
7848 { "vpcomw", { XM, Vex, EXx, VPCOM }, 0 },
7849 },
7850 /* VEX_W_0FXOP_08_CE_L_0 */
7851 {
7852 { "vpcomd", { XM, Vex, EXx, VPCOM }, 0 },
7853 },
7854 /* VEX_W_0FXOP_08_CF_L_0 */
7855 {
7856 { "vpcomq", { XM, Vex, EXx, VPCOM }, 0 },
7857 },
7858 /* VEX_W_0FXOP_08_EC_L_0 */
7859 {
7860 { "vpcomub", { XM, Vex, EXx, VPCOM }, 0 },
7861 },
7862 /* VEX_W_0FXOP_08_ED_L_0 */
7863 {
7864 { "vpcomuw", { XM, Vex, EXx, VPCOM }, 0 },
7865 },
7866 /* VEX_W_0FXOP_08_EE_L_0 */
7867 {
7868 { "vpcomud", { XM, Vex, EXx, VPCOM }, 0 },
7869 },
7870 /* VEX_W_0FXOP_08_EF_L_0 */
7871 {
7872 { "vpcomuq", { XM, Vex, EXx, VPCOM }, 0 },
7873 },
7874 /* VEX_W_0FXOP_09_80 */
7875 {
7876 { "vfrczps", { XM, EXx }, 0 },
7877 },
7878 /* VEX_W_0FXOP_09_81 */
7879 {
7880 { "vfrczpd", { XM, EXx }, 0 },
7881 },
7882 /* VEX_W_0FXOP_09_82 */
7883 {
7884 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
7885 },
7886 /* VEX_W_0FXOP_09_83 */
7887 {
7888 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
7889 },
7890 /* VEX_W_0FXOP_09_C1_L_0 */
7891 {
7892 { "vphaddbw", { XM, EXxmm }, 0 },
7893 },
7894 /* VEX_W_0FXOP_09_C2_L_0 */
7895 {
7896 { "vphaddbd", { XM, EXxmm }, 0 },
7897 },
7898 /* VEX_W_0FXOP_09_C3_L_0 */
7899 {
7900 { "vphaddbq", { XM, EXxmm }, 0 },
7901 },
7902 /* VEX_W_0FXOP_09_C6_L_0 */
7903 {
7904 { "vphaddwd", { XM, EXxmm }, 0 },
7905 },
7906 /* VEX_W_0FXOP_09_C7_L_0 */
7907 {
7908 { "vphaddwq", { XM, EXxmm }, 0 },
7909 },
7910 /* VEX_W_0FXOP_09_CB_L_0 */
7911 {
7912 { "vphadddq", { XM, EXxmm }, 0 },
7913 },
7914 /* VEX_W_0FXOP_09_D1_L_0 */
7915 {
7916 { "vphaddubw", { XM, EXxmm }, 0 },
7917 },
7918 /* VEX_W_0FXOP_09_D2_L_0 */
7919 {
7920 { "vphaddubd", { XM, EXxmm }, 0 },
7921 },
7922 /* VEX_W_0FXOP_09_D3_L_0 */
7923 {
7924 { "vphaddubq", { XM, EXxmm }, 0 },
7925 },
7926 /* VEX_W_0FXOP_09_D6_L_0 */
7927 {
7928 { "vphadduwd", { XM, EXxmm }, 0 },
7929 },
7930 /* VEX_W_0FXOP_09_D7_L_0 */
7931 {
7932 { "vphadduwq", { XM, EXxmm }, 0 },
7933 },
7934 /* VEX_W_0FXOP_09_DB_L_0 */
7935 {
7936 { "vphaddudq", { XM, EXxmm }, 0 },
7937 },
7938 /* VEX_W_0FXOP_09_E1_L_0 */
7939 {
7940 { "vphsubbw", { XM, EXxmm }, 0 },
7941 },
7942 /* VEX_W_0FXOP_09_E2_L_0 */
7943 {
7944 { "vphsubwd", { XM, EXxmm }, 0 },
7945 },
7946 /* VEX_W_0FXOP_09_E3_L_0 */
7947 {
7948 { "vphsubdq", { XM, EXxmm }, 0 },
7949 },
7950
7951 #include "i386-dis-evex-w.h"
7952 };
7953
7954 static const struct dis386 mod_table[][2] = {
7955 {
7956 /* MOD_62_32BIT */
7957 { "bound{S|}", { Gv, Ma }, 0 },
7958 { EVEX_TABLE (EVEX_0F) },
7959 },
7960 {
7961 /* MOD_8D */
7962 { "leaS", { Gv, M }, 0 },
7963 },
7964 {
7965 /* MOD_C4_32BIT */
7966 { "lesS", { Gv, Mp }, 0 },
7967 { VEX_C4_TABLE (VEX_0F) },
7968 },
7969 {
7970 /* MOD_C5_32BIT */
7971 { "ldsS", { Gv, Mp }, 0 },
7972 { VEX_C5_TABLE (VEX_0F) },
7973 },
7974 {
7975 /* MOD_C6_REG_7 */
7976 { Bad_Opcode },
7977 { RM_TABLE (RM_C6_REG_7) },
7978 },
7979 {
7980 /* MOD_C7_REG_7 */
7981 { Bad_Opcode },
7982 { RM_TABLE (RM_C7_REG_7) },
7983 },
7984 {
7985 /* MOD_FF_REG_3 */
7986 { "{l|}call^", { indirEp }, 0 },
7987 },
7988 {
7989 /* MOD_FF_REG_5 */
7990 { "{l|}jmp^", { indirEp }, 0 },
7991 },
7992 {
7993 /* MOD_0F01_REG_0 */
7994 { X86_64_TABLE (X86_64_0F01_REG_0) },
7995 { RM_TABLE (RM_0F01_REG_0) },
7996 },
7997 {
7998 /* MOD_0F01_REG_1 */
7999 { X86_64_TABLE (X86_64_0F01_REG_1) },
8000 { RM_TABLE (RM_0F01_REG_1) },
8001 },
8002 {
8003 /* MOD_0F01_REG_2 */
8004 { X86_64_TABLE (X86_64_0F01_REG_2) },
8005 { RM_TABLE (RM_0F01_REG_2) },
8006 },
8007 {
8008 /* MOD_0F01_REG_3 */
8009 { X86_64_TABLE (X86_64_0F01_REG_3) },
8010 { RM_TABLE (RM_0F01_REG_3) },
8011 },
8012 {
8013 /* MOD_0F01_REG_5 */
8014 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
8015 { RM_TABLE (RM_0F01_REG_5_MOD_3) },
8016 },
8017 {
8018 /* MOD_0F01_REG_7 */
8019 { "invlpg", { Mb }, 0 },
8020 { RM_TABLE (RM_0F01_REG_7_MOD_3) },
8021 },
8022 {
8023 /* MOD_0F02 */
8024 { "larS", { Gv, Mw }, 0 },
8025 { "larS", { Gv, Ev }, 0 },
8026 },
8027 {
8028 /* MOD_0F03 */
8029 { "lslS", { Gv, Mw }, 0 },
8030 { "lslS", { Gv, Ev }, 0 },
8031 },
8032 {
8033 /* MOD_0F12_PREFIX_0 */
8034 { "%XEVmovlpYX", { XM, Vex, EXq }, 0 },
8035 { "%XEVmovhlpY%XS", { XM, Vex, EXq }, 0 },
8036 },
8037 {
8038 /* MOD_0F12_PREFIX_2 */
8039 { "%XEVmovlpYX", { XM, Vex, EXq }, 0 },
8040 },
8041 {
8042 /* MOD_0F13 */
8043 { "%XEVmovlpYX", { EXq, XM }, PREFIX_OPCODE },
8044 },
8045 {
8046 /* MOD_0F16_PREFIX_0 */
8047 { "%XEVmovhpYX", { XM, Vex, EXq }, 0 },
8048 { "%XEVmovlhpY%XS", { XM, Vex, EXq }, 0 },
8049 },
8050 {
8051 /* MOD_0F16_PREFIX_2 */
8052 { "%XEVmovhpYX", { XM, Vex, EXq }, 0 },
8053 },
8054 {
8055 /* MOD_0F17 */
8056 { "%XEVmovhpYX", { EXq, XM }, PREFIX_OPCODE },
8057 },
8058 {
8059 /* MOD_0F18_REG_0 */
8060 { "prefetchnta", { Mb }, 0 },
8061 { "nopQ", { Ev }, 0 },
8062 },
8063 {
8064 /* MOD_0F18_REG_1 */
8065 { "prefetcht0", { Mb }, 0 },
8066 { "nopQ", { Ev }, 0 },
8067 },
8068 {
8069 /* MOD_0F18_REG_2 */
8070 { "prefetcht1", { Mb }, 0 },
8071 { "nopQ", { Ev }, 0 },
8072 },
8073 {
8074 /* MOD_0F18_REG_3 */
8075 { "prefetcht2", { Mb }, 0 },
8076 { "nopQ", { Ev }, 0 },
8077 },
8078 {
8079 /* MOD_0F18_REG_6 */
8080 { X86_64_TABLE (X86_64_0F18_REG_6_MOD_0) },
8081 { "nopQ", { Ev }, 0 },
8082 },
8083 {
8084 /* MOD_0F18_REG_7 */
8085 { X86_64_TABLE (X86_64_0F18_REG_7_MOD_0) },
8086 { "nopQ", { Ev }, 0 },
8087 },
8088 {
8089 /* MOD_0F1A_PREFIX_0 */
8090 { "bndldx", { Gbnd, Mv_bnd }, 0 },
8091 { "nopQ", { Ev }, 0 },
8092 },
8093 {
8094 /* MOD_0F1B_PREFIX_0 */
8095 { "bndstx", { Mv_bnd, Gbnd }, 0 },
8096 { "nopQ", { Ev }, 0 },
8097 },
8098 {
8099 /* MOD_0F1B_PREFIX_1 */
8100 { "bndmk", { Gbnd, Mv_bnd }, 0 },
8101 { "nopQ", { Ev }, PREFIX_IGNORED },
8102 },
8103 {
8104 /* MOD_0F1C_PREFIX_0 */
8105 { REG_TABLE (REG_0F1C_P_0_MOD_0) },
8106 { "nopQ", { Ev }, 0 },
8107 },
8108 {
8109 /* MOD_0F1E_PREFIX_1 */
8110 { "nopQ", { Ev }, PREFIX_IGNORED },
8111 { REG_TABLE (REG_0F1E_P_1_MOD_3) },
8112 },
8113 {
8114 /* MOD_0F2B_PREFIX_0 */
8115 {"movntps", { Mx, XM }, PREFIX_OPCODE },
8116 },
8117 {
8118 /* MOD_0F2B_PREFIX_1 */
8119 {"movntss", { Md, XM }, PREFIX_OPCODE },
8120 },
8121 {
8122 /* MOD_0F2B_PREFIX_2 */
8123 {"movntpd", { Mx, XM }, PREFIX_OPCODE },
8124 },
8125 {
8126 /* MOD_0F2B_PREFIX_3 */
8127 {"movntsd", { Mq, XM }, PREFIX_OPCODE },
8128 },
8129 {
8130 /* MOD_0F50 */
8131 { Bad_Opcode },
8132 { "VmovmskpX", { Gdq, XS }, PREFIX_OPCODE },
8133 },
8134 {
8135 /* MOD_0F71 */
8136 { Bad_Opcode },
8137 { REG_TABLE (REG_0F71_MOD_0) },
8138 },
8139 {
8140 /* MOD_0F72 */
8141 { Bad_Opcode },
8142 { REG_TABLE (REG_0F72_MOD_0) },
8143 },
8144 {
8145 /* MOD_0F73 */
8146 { Bad_Opcode },
8147 { REG_TABLE (REG_0F73_MOD_0) },
8148 },
8149 {
8150 /* MOD_0FAE_REG_0 */
8151 { "fxsave", { FXSAVE }, 0 },
8152 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8153 },
8154 {
8155 /* MOD_0FAE_REG_1 */
8156 { "fxrstor", { FXSAVE }, 0 },
8157 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8158 },
8159 {
8160 /* MOD_0FAE_REG_2 */
8161 { "ldmxcsr", { Md }, 0 },
8162 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8163 },
8164 {
8165 /* MOD_0FAE_REG_3 */
8166 { "stmxcsr", { Md }, 0 },
8167 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8168 },
8169 {
8170 /* MOD_0FAE_REG_4 */
8171 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8172 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8173 },
8174 {
8175 /* MOD_0FAE_REG_5 */
8176 { "xrstor", { FXSAVE }, PREFIX_OPCODE },
8177 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8178 },
8179 {
8180 /* MOD_0FAE_REG_6 */
8181 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8182 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8183 },
8184 {
8185 /* MOD_0FAE_REG_7 */
8186 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8187 { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8188 },
8189 {
8190 /* MOD_0FB2 */
8191 { "lssS", { Gv, Mp }, 0 },
8192 },
8193 {
8194 /* MOD_0FB4 */
8195 { "lfsS", { Gv, Mp }, 0 },
8196 },
8197 {
8198 /* MOD_0FB5 */
8199 { "lgsS", { Gv, Mp }, 0 },
8200 },
8201 {
8202 /* MOD_0FC3 */
8203 { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
8204 },
8205 {
8206 /* MOD_0FC7_REG_3 */
8207 { "xrstors", { FXSAVE }, 0 },
8208 },
8209 {
8210 /* MOD_0FC7_REG_4 */
8211 { "xsavec", { FXSAVE }, 0 },
8212 },
8213 {
8214 /* MOD_0FC7_REG_5 */
8215 { "xsaves", { FXSAVE }, 0 },
8216 },
8217 {
8218 /* MOD_0FC7_REG_6 */
8219 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8220 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8221 },
8222 {
8223 /* MOD_0FC7_REG_7 */
8224 { "vmptrst", { Mq }, 0 },
8225 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8226 },
8227 {
8228 /* MOD_0FD7 */
8229 { Bad_Opcode },
8230 { "pmovmskb", { Gdq, MS }, 0 },
8231 },
8232 {
8233 /* MOD_0FE7_PREFIX_2 */
8234 { "movntdq", { Mx, XM }, 0 },
8235 },
8236 {
8237 /* MOD_0F382A */
8238 { "movntdqa", { XM, Mx }, PREFIX_DATA },
8239 },
8240 {
8241 /* MOD_0F38DC_PREFIX_1 */
8242 { "aesenc128kl", { XM, M }, 0 },
8243 { "loadiwkey", { XM, EXx }, 0 },
8244 },
8245 {
8246 /* MOD_0F38DD_PREFIX_1 */
8247 { "aesdec128kl", { XM, M }, 0 },
8248 },
8249 {
8250 /* MOD_0F38DE_PREFIX_1 */
8251 { "aesenc256kl", { XM, M }, 0 },
8252 },
8253 {
8254 /* MOD_0F38DF_PREFIX_1 */
8255 { "aesdec256kl", { XM, M }, 0 },
8256 },
8257 {
8258 /* MOD_0F38F5 */
8259 { "wrussK", { M, Gdq }, PREFIX_DATA },
8260 },
8261 {
8262 /* MOD_0F38F6_PREFIX_0 */
8263 { "wrssK", { M, Gdq }, PREFIX_OPCODE },
8264 },
8265 {
8266 /* MOD_0F38F8_PREFIX_1 */
8267 { "enqcmds", { Gva, M }, PREFIX_OPCODE },
8268 },
8269 {
8270 /* MOD_0F38F8_PREFIX_2 */
8271 { "movdir64b", { Gva, M }, PREFIX_OPCODE },
8272 },
8273 {
8274 /* MOD_0F38F8_PREFIX_3 */
8275 { "enqcmd", { Gva, M }, PREFIX_OPCODE },
8276 },
8277 {
8278 /* MOD_0F38F9 */
8279 { "movdiri", { Edq, Gdq }, PREFIX_OPCODE },
8280 },
8281 {
8282 /* MOD_0F38FA_PREFIX_1 */
8283 { Bad_Opcode },
8284 { "encodekey128", { Gd, Ed }, 0 },
8285 },
8286 {
8287 /* MOD_0F38FB_PREFIX_1 */
8288 { Bad_Opcode },
8289 { "encodekey256", { Gd, Ed }, 0 },
8290 },
8291 {
8292 /* MOD_0F3A0F_PREFIX_1 */
8293 { Bad_Opcode },
8294 { REG_TABLE (REG_0F3A0F_PREFIX_1_MOD_3) },
8295 },
8296 {
8297 /* MOD_VEX_0F2B */
8298 { "%XEvmovntpX", { Mx, XM }, PREFIX_OPCODE },
8299 },
8300 {
8301 /* MOD_VEX_0F41_L_1 */
8302 { Bad_Opcode },
8303 { VEX_W_TABLE (VEX_W_0F41_L_1_M_1) },
8304 },
8305 {
8306 /* MOD_VEX_0F42_L_1 */
8307 { Bad_Opcode },
8308 { VEX_W_TABLE (VEX_W_0F42_L_1_M_1) },
8309 },
8310 {
8311 /* MOD_VEX_0F44_L_0 */
8312 { Bad_Opcode },
8313 { VEX_W_TABLE (VEX_W_0F44_L_0_M_1) },
8314 },
8315 {
8316 /* MOD_VEX_0F45_L_1 */
8317 { Bad_Opcode },
8318 { VEX_W_TABLE (VEX_W_0F45_L_1_M_1) },
8319 },
8320 {
8321 /* MOD_VEX_0F46_L_1 */
8322 { Bad_Opcode },
8323 { VEX_W_TABLE (VEX_W_0F46_L_1_M_1) },
8324 },
8325 {
8326 /* MOD_VEX_0F47_L_1 */
8327 { Bad_Opcode },
8328 { VEX_W_TABLE (VEX_W_0F47_L_1_M_1) },
8329 },
8330 {
8331 /* MOD_VEX_0F4A_L_1 */
8332 { Bad_Opcode },
8333 { VEX_W_TABLE (VEX_W_0F4A_L_1_M_1) },
8334 },
8335 {
8336 /* MOD_VEX_0F4B_L_1 */
8337 { Bad_Opcode },
8338 { VEX_W_TABLE (VEX_W_0F4B_L_1_M_1) },
8339 },
8340 {
8341 /* MOD_VEX_0F71 */
8342 { Bad_Opcode },
8343 { REG_TABLE (REG_VEX_0F71_M_0) },
8344 },
8345 {
8346 /* MOD_VEX_0F72 */
8347 { Bad_Opcode },
8348 { REG_TABLE (REG_VEX_0F72_M_0) },
8349 },
8350 {
8351 /* MOD_VEX_0F73 */
8352 { Bad_Opcode },
8353 { REG_TABLE (REG_VEX_0F73_M_0) },
8354 },
8355 {
8356 /* MOD_VEX_0F91_L_0 */
8357 { VEX_W_TABLE (VEX_W_0F91_L_0_M_0) },
8358 },
8359 {
8360 /* MOD_VEX_0F92_L_0 */
8361 { Bad_Opcode },
8362 { VEX_W_TABLE (VEX_W_0F92_L_0_M_1) },
8363 },
8364 {
8365 /* MOD_VEX_0F93_L_0 */
8366 { Bad_Opcode },
8367 { VEX_W_TABLE (VEX_W_0F93_L_0_M_1) },
8368 },
8369 {
8370 /* MOD_VEX_0F98_L_0 */
8371 { Bad_Opcode },
8372 { VEX_W_TABLE (VEX_W_0F98_L_0_M_1) },
8373 },
8374 {
8375 /* MOD_VEX_0F99_L_0 */
8376 { Bad_Opcode },
8377 { VEX_W_TABLE (VEX_W_0F99_L_0_M_1) },
8378 },
8379 {
8380 /* MOD_VEX_0FAE_REG_2 */
8381 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
8382 },
8383 {
8384 /* MOD_VEX_0FAE_REG_3 */
8385 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
8386 },
8387 {
8388 /* MOD_VEX_0FD7 */
8389 { Bad_Opcode },
8390 { "vpmovmskb", { Gdq, XS }, PREFIX_DATA },
8391 },
8392 {
8393 /* MOD_VEX_0FE7 */
8394 { "vmovntdq", { Mx, XM }, PREFIX_DATA },
8395 },
8396 {
8397 /* MOD_VEX_0F381A */
8398 { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) },
8399 },
8400 {
8401 /* MOD_VEX_0F382A */
8402 { "vmovntdqa", { XM, Mx }, PREFIX_DATA },
8403 },
8404 {
8405 /* MOD_VEX_0F382C */
8406 { VEX_W_TABLE (VEX_W_0F382C_M_0) },
8407 },
8408 {
8409 /* MOD_VEX_0F382D */
8410 { VEX_W_TABLE (VEX_W_0F382D_M_0) },
8411 },
8412 {
8413 /* MOD_VEX_0F382E */
8414 { VEX_W_TABLE (VEX_W_0F382E_M_0) },
8415 },
8416 {
8417 /* MOD_VEX_0F382F */
8418 { VEX_W_TABLE (VEX_W_0F382F_M_0) },
8419 },
8420 {
8421 /* MOD_VEX_0F3849_X86_64_L_0_W_0 */
8422 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0) },
8423 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1) },
8424 },
8425 {
8426 /* MOD_VEX_0F384B_X86_64_L_0_W_0 */
8427 { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64_L_0_W_0_M_0) },
8428 },
8429 {
8430 /* MOD_VEX_0F385A */
8431 { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) },
8432 },
8433 {
8434 /* MOD_VEX_0F385C_X86_64 */
8435 { Bad_Opcode },
8436 { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_M_1) },
8437 },
8438 {
8439 /* MOD_VEX_0F385E_X86_64 */
8440 { Bad_Opcode },
8441 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_M_1) },
8442 },
8443 {
8444 /* MOD_VEX_0F386C_X86_64 */
8445 { Bad_Opcode },
8446 { VEX_LEN_TABLE (VEX_LEN_0F386C_X86_64_M_1) },
8447 },
8448 {
8449 /* MOD_VEX_0F388C */
8450 { "vpmaskmov%DQ", { XM, Vex, Mx }, PREFIX_DATA },
8451 },
8452 {
8453 /* MOD_VEX_0F388E */
8454 { "vpmaskmov%DQ", { Mx, Vex, XM }, PREFIX_DATA },
8455 },
8456 {
8457 /* MOD_VEX_0F3A30_L_0 */
8458 { Bad_Opcode },
8459 { "kshiftr%BW", { MaskG, MaskE, Ib }, PREFIX_DATA },
8460 },
8461 {
8462 /* MOD_VEX_0F3A31_L_0 */
8463 { Bad_Opcode },
8464 { "kshiftr%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA },
8465 },
8466 {
8467 /* MOD_VEX_0F3A32_L_0 */
8468 { Bad_Opcode },
8469 { "kshiftl%BW", { MaskG, MaskE, Ib }, PREFIX_DATA },
8470 },
8471 {
8472 /* MOD_VEX_0F3A33_L_0 */
8473 { Bad_Opcode },
8474 { "kshiftl%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA },
8475 },
8476 {
8477 /* MOD_XOP_09_12 */
8478 { Bad_Opcode },
8479 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
8480 },
8481
8482 #include "i386-dis-evex-mod.h"
8483 };
8484
8485 static const struct dis386 rm_table[][8] = {
8486 {
8487 /* RM_C6_REG_7 */
8488 { "xabort", { Skip_MODRM, Ib }, 0 },
8489 },
8490 {
8491 /* RM_C7_REG_7 */
8492 { "xbeginT", { Skip_MODRM, Jdqw }, 0 },
8493 },
8494 {
8495 /* RM_0F01_REG_0 */
8496 { "enclv", { Skip_MODRM }, 0 },
8497 { "vmcall", { Skip_MODRM }, 0 },
8498 { "vmlaunch", { Skip_MODRM }, 0 },
8499 { "vmresume", { Skip_MODRM }, 0 },
8500 { "vmxoff", { Skip_MODRM }, 0 },
8501 { "pconfig", { Skip_MODRM }, 0 },
8502 { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_6) },
8503 },
8504 {
8505 /* RM_0F01_REG_1 */
8506 { "monitor", { { OP_Monitor, 0 } }, 0 },
8507 { "mwait", { { OP_Mwait, 0 } }, 0 },
8508 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_2) },
8509 { "stac", { Skip_MODRM }, 0 },
8510 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
8511 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
8512 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
8513 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
8514 },
8515 {
8516 /* RM_0F01_REG_2 */
8517 { "xgetbv", { Skip_MODRM }, 0 },
8518 { "xsetbv", { Skip_MODRM }, 0 },
8519 { Bad_Opcode },
8520 { Bad_Opcode },
8521 { "vmfunc", { Skip_MODRM }, 0 },
8522 { "xend", { Skip_MODRM }, 0 },
8523 { "xtest", { Skip_MODRM }, 0 },
8524 { "enclu", { Skip_MODRM }, 0 },
8525 },
8526 {
8527 /* RM_0F01_REG_3 */
8528 { "vmrun", { Skip_MODRM }, 0 },
8529 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8530 { "vmload", { Skip_MODRM }, 0 },
8531 { "vmsave", { Skip_MODRM }, 0 },
8532 { "stgi", { Skip_MODRM }, 0 },
8533 { "clgi", { Skip_MODRM }, 0 },
8534 { "skinit", { Skip_MODRM }, 0 },
8535 { "invlpga", { Skip_MODRM }, 0 },
8536 },
8537 {
8538 /* RM_0F01_REG_5_MOD_3 */
8539 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8540 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8541 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8542 { Bad_Opcode },
8543 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) },
8544 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) },
8545 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) },
8546 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) },
8547 },
8548 {
8549 /* RM_0F01_REG_7_MOD_3 */
8550 { "swapgs", { Skip_MODRM }, 0 },
8551 { "rdtscp", { Skip_MODRM }, 0 },
8552 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8553 { "mwaitx", { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8554 { "clzero", { Skip_MODRM }, 0 },
8555 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_5) },
8556 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) },
8557 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) },
8558 },
8559 {
8560 /* RM_0F1E_P_1_MOD_3_REG_7 */
8561 { "nopQ", { Ev }, PREFIX_IGNORED },
8562 { "nopQ", { Ev }, PREFIX_IGNORED },
8563 { "endbr64", { Skip_MODRM }, 0 },
8564 { "endbr32", { Skip_MODRM }, 0 },
8565 { "nopQ", { Ev }, PREFIX_IGNORED },
8566 { "nopQ", { Ev }, PREFIX_IGNORED },
8567 { "nopQ", { Ev }, PREFIX_IGNORED },
8568 { "nopQ", { Ev }, PREFIX_IGNORED },
8569 },
8570 {
8571 /* RM_0FAE_REG_6_MOD_3 */
8572 { "mfence", { Skip_MODRM }, 0 },
8573 },
8574 {
8575 /* RM_0FAE_REG_7_MOD_3 */
8576 { "sfence", { Skip_MODRM }, 0 },
8577 },
8578 {
8579 /* RM_0F3A0F_P_1_MOD_3_REG_0 */
8580 { "hreset", { Skip_MODRM, Ib }, 0 },
8581 },
8582 {
8583 /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0 */
8584 { "tilerelease", { Skip_MODRM }, 0 },
8585 },
8586 {
8587 /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3 */
8588 { "tilezero", { TMM, Skip_MODRM }, 0 },
8589 },
8590 };
8591
8592 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8593
8594 /* The values used here must be non-zero, fit in 'unsigned char', and not be
8595 in conflict with actual prefix opcodes. */
8596 #define REP_PREFIX 0x01
8597 #define XACQUIRE_PREFIX 0x02
8598 #define XRELEASE_PREFIX 0x03
8599 #define BND_PREFIX 0x04
8600 #define NOTRACK_PREFIX 0x05
8601
8602 static enum {
8603 ckp_okay,
8604 ckp_bogus,
8605 ckp_fetch_error,
8606 }
8607 ckprefix (instr_info *ins)
8608 {
8609 int i, length;
8610 uint8_t newrex;
8611
8612 i = 0;
8613 length = 0;
8614 /* The maximum instruction length is 15bytes. */
8615 while (length < MAX_CODE_LENGTH - 1)
8616 {
8617 if (!fetch_code (ins->info, ins->codep + 1))
8618 return ckp_fetch_error;
8619 newrex = 0;
8620 switch (*ins->codep)
8621 {
8622 /* REX prefixes family. */
8623 case 0x40:
8624 case 0x41:
8625 case 0x42:
8626 case 0x43:
8627 case 0x44:
8628 case 0x45:
8629 case 0x46:
8630 case 0x47:
8631 case 0x48:
8632 case 0x49:
8633 case 0x4a:
8634 case 0x4b:
8635 case 0x4c:
8636 case 0x4d:
8637 case 0x4e:
8638 case 0x4f:
8639 if (ins->address_mode == mode_64bit)
8640 newrex = *ins->codep;
8641 else
8642 return ckp_okay;
8643 ins->last_rex_prefix = i;
8644 break;
8645 case 0xf3:
8646 ins->prefixes |= PREFIX_REPZ;
8647 ins->last_repz_prefix = i;
8648 break;
8649 case 0xf2:
8650 ins->prefixes |= PREFIX_REPNZ;
8651 ins->last_repnz_prefix = i;
8652 break;
8653 case 0xf0:
8654 ins->prefixes |= PREFIX_LOCK;
8655 ins->last_lock_prefix = i;
8656 break;
8657 case 0x2e:
8658 ins->prefixes |= PREFIX_CS;
8659 ins->last_seg_prefix = i;
8660 if (ins->address_mode != mode_64bit)
8661 ins->active_seg_prefix = PREFIX_CS;
8662 break;
8663 case 0x36:
8664 ins->prefixes |= PREFIX_SS;
8665 ins->last_seg_prefix = i;
8666 if (ins->address_mode != mode_64bit)
8667 ins->active_seg_prefix = PREFIX_SS;
8668 break;
8669 case 0x3e:
8670 ins->prefixes |= PREFIX_DS;
8671 ins->last_seg_prefix = i;
8672 if (ins->address_mode != mode_64bit)
8673 ins->active_seg_prefix = PREFIX_DS;
8674 break;
8675 case 0x26:
8676 ins->prefixes |= PREFIX_ES;
8677 ins->last_seg_prefix = i;
8678 if (ins->address_mode != mode_64bit)
8679 ins->active_seg_prefix = PREFIX_ES;
8680 break;
8681 case 0x64:
8682 ins->prefixes |= PREFIX_FS;
8683 ins->last_seg_prefix = i;
8684 ins->active_seg_prefix = PREFIX_FS;
8685 break;
8686 case 0x65:
8687 ins->prefixes |= PREFIX_GS;
8688 ins->last_seg_prefix = i;
8689 ins->active_seg_prefix = PREFIX_GS;
8690 break;
8691 case 0x66:
8692 ins->prefixes |= PREFIX_DATA;
8693 ins->last_data_prefix = i;
8694 break;
8695 case 0x67:
8696 ins->prefixes |= PREFIX_ADDR;
8697 ins->last_addr_prefix = i;
8698 break;
8699 case FWAIT_OPCODE:
8700 /* fwait is really an instruction. If there are prefixes
8701 before the fwait, they belong to the fwait, *not* to the
8702 following instruction. */
8703 ins->fwait_prefix = i;
8704 if (ins->prefixes || ins->rex)
8705 {
8706 ins->prefixes |= PREFIX_FWAIT;
8707 ins->codep++;
8708 /* This ensures that the previous REX prefixes are noticed
8709 as unused prefixes, as in the return case below. */
8710 return ins->rex ? ckp_bogus : ckp_okay;
8711 }
8712 ins->prefixes = PREFIX_FWAIT;
8713 break;
8714 default:
8715 return ckp_okay;
8716 }
8717 /* Rex is ignored when followed by another prefix. */
8718 if (ins->rex)
8719 return ckp_bogus;
8720 if (*ins->codep != FWAIT_OPCODE)
8721 ins->all_prefixes[i++] = *ins->codep;
8722 ins->rex = newrex;
8723 ins->codep++;
8724 length++;
8725 }
8726 return ckp_bogus;
8727 }
8728
8729 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8730 prefix byte. */
8731
8732 static const char *
8733 prefix_name (enum address_mode mode, uint8_t pref, int sizeflag)
8734 {
8735 static const char *rexes [16] =
8736 {
8737 "rex", /* 0x40 */
8738 "rex.B", /* 0x41 */
8739 "rex.X", /* 0x42 */
8740 "rex.XB", /* 0x43 */
8741 "rex.R", /* 0x44 */
8742 "rex.RB", /* 0x45 */
8743 "rex.RX", /* 0x46 */
8744 "rex.RXB", /* 0x47 */
8745 "rex.W", /* 0x48 */
8746 "rex.WB", /* 0x49 */
8747 "rex.WX", /* 0x4a */
8748 "rex.WXB", /* 0x4b */
8749 "rex.WR", /* 0x4c */
8750 "rex.WRB", /* 0x4d */
8751 "rex.WRX", /* 0x4e */
8752 "rex.WRXB", /* 0x4f */
8753 };
8754
8755 switch (pref)
8756 {
8757 /* REX prefixes family. */
8758 case 0x40:
8759 case 0x41:
8760 case 0x42:
8761 case 0x43:
8762 case 0x44:
8763 case 0x45:
8764 case 0x46:
8765 case 0x47:
8766 case 0x48:
8767 case 0x49:
8768 case 0x4a:
8769 case 0x4b:
8770 case 0x4c:
8771 case 0x4d:
8772 case 0x4e:
8773 case 0x4f:
8774 return rexes [pref - 0x40];
8775 case 0xf3:
8776 return "repz";
8777 case 0xf2:
8778 return "repnz";
8779 case 0xf0:
8780 return "lock";
8781 case 0x2e:
8782 return "cs";
8783 case 0x36:
8784 return "ss";
8785 case 0x3e:
8786 return "ds";
8787 case 0x26:
8788 return "es";
8789 case 0x64:
8790 return "fs";
8791 case 0x65:
8792 return "gs";
8793 case 0x66:
8794 return (sizeflag & DFLAG) ? "data16" : "data32";
8795 case 0x67:
8796 if (mode == mode_64bit)
8797 return (sizeflag & AFLAG) ? "addr32" : "addr64";
8798 else
8799 return (sizeflag & AFLAG) ? "addr16" : "addr32";
8800 case FWAIT_OPCODE:
8801 return "fwait";
8802 case REP_PREFIX:
8803 return "rep";
8804 case XACQUIRE_PREFIX:
8805 return "xacquire";
8806 case XRELEASE_PREFIX:
8807 return "xrelease";
8808 case BND_PREFIX:
8809 return "bnd";
8810 case NOTRACK_PREFIX:
8811 return "notrack";
8812 default:
8813 return NULL;
8814 }
8815 }
8816
8817 void
8818 print_i386_disassembler_options (FILE *stream)
8819 {
8820 fprintf (stream, _("\n\
8821 The following i386/x86-64 specific disassembler options are supported for use\n\
8822 with the -M switch (multiple options should be separated by commas):\n"));
8823
8824 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
8825 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
8826 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
8827 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
8828 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
8829 fprintf (stream, _(" att-mnemonic\n"
8830 " Display instruction in AT&T mnemonic\n"));
8831 fprintf (stream, _(" intel-mnemonic\n"
8832 " Display instruction in Intel mnemonic\n"));
8833 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
8834 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
8835 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
8836 fprintf (stream, _(" data32 Assume 32bit data size\n"));
8837 fprintf (stream, _(" data16 Assume 16bit data size\n"));
8838 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
8839 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
8840 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
8841 }
8842
8843 /* Bad opcode. */
8844 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
8845
8846 /* Fetch error indicator. */
8847 static const struct dis386 err_opcode = { NULL, { XX }, 0 };
8848
8849 /* Get a pointer to struct dis386 with a valid name. */
8850
8851 static const struct dis386 *
8852 get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
8853 {
8854 int vindex, vex_table_index;
8855
8856 if (dp->name != NULL)
8857 return dp;
8858
8859 switch (dp->op[0].bytemode)
8860 {
8861 case USE_REG_TABLE:
8862 dp = &reg_table[dp->op[1].bytemode][ins->modrm.reg];
8863 break;
8864
8865 case USE_MOD_TABLE:
8866 vindex = ins->modrm.mod == 0x3 ? 1 : 0;
8867 dp = &mod_table[dp->op[1].bytemode][vindex];
8868 break;
8869
8870 case USE_RM_TABLE:
8871 dp = &rm_table[dp->op[1].bytemode][ins->modrm.rm];
8872 break;
8873
8874 case USE_PREFIX_TABLE:
8875 if (ins->need_vex)
8876 {
8877 /* The prefix in VEX is implicit. */
8878 switch (ins->vex.prefix)
8879 {
8880 case 0:
8881 vindex = 0;
8882 break;
8883 case REPE_PREFIX_OPCODE:
8884 vindex = 1;
8885 break;
8886 case DATA_PREFIX_OPCODE:
8887 vindex = 2;
8888 break;
8889 case REPNE_PREFIX_OPCODE:
8890 vindex = 3;
8891 break;
8892 default:
8893 abort ();
8894 break;
8895 }
8896 }
8897 else
8898 {
8899 int last_prefix = -1;
8900 int prefix = 0;
8901 vindex = 0;
8902 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
8903 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
8904 last one wins. */
8905 if ((ins->prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
8906 {
8907 if (ins->last_repz_prefix > ins->last_repnz_prefix)
8908 {
8909 vindex = 1;
8910 prefix = PREFIX_REPZ;
8911 last_prefix = ins->last_repz_prefix;
8912 }
8913 else
8914 {
8915 vindex = 3;
8916 prefix = PREFIX_REPNZ;
8917 last_prefix = ins->last_repnz_prefix;
8918 }
8919
8920 /* Check if prefix should be ignored. */
8921 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
8922 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
8923 & prefix) != 0
8924 && !prefix_table[dp->op[1].bytemode][vindex].name)
8925 vindex = 0;
8926 }
8927
8928 if (vindex == 0 && (ins->prefixes & PREFIX_DATA) != 0)
8929 {
8930 vindex = 2;
8931 prefix = PREFIX_DATA;
8932 last_prefix = ins->last_data_prefix;
8933 }
8934
8935 if (vindex != 0)
8936 {
8937 ins->used_prefixes |= prefix;
8938 ins->all_prefixes[last_prefix] = 0;
8939 }
8940 }
8941 dp = &prefix_table[dp->op[1].bytemode][vindex];
8942 break;
8943
8944 case USE_X86_64_TABLE:
8945 vindex = ins->address_mode == mode_64bit ? 1 : 0;
8946 dp = &x86_64_table[dp->op[1].bytemode][vindex];
8947 break;
8948
8949 case USE_3BYTE_TABLE:
8950 if (!fetch_code (ins->info, ins->codep + 2))
8951 return &err_opcode;
8952 vindex = *ins->codep++;
8953 dp = &three_byte_table[dp->op[1].bytemode][vindex];
8954 ins->end_codep = ins->codep;
8955 if (!fetch_modrm (ins))
8956 return &err_opcode;
8957 break;
8958
8959 case USE_VEX_LEN_TABLE:
8960 if (!ins->need_vex)
8961 abort ();
8962
8963 switch (ins->vex.length)
8964 {
8965 case 128:
8966 vindex = 0;
8967 break;
8968 case 512:
8969 /* This allows re-using in particular table entries where only
8970 128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid. */
8971 if (ins->vex.evex)
8972 {
8973 case 256:
8974 vindex = 1;
8975 break;
8976 }
8977 /* Fall through. */
8978 default:
8979 abort ();
8980 break;
8981 }
8982
8983 dp = &vex_len_table[dp->op[1].bytemode][vindex];
8984 break;
8985
8986 case USE_EVEX_LEN_TABLE:
8987 if (!ins->vex.evex)
8988 abort ();
8989
8990 switch (ins->vex.length)
8991 {
8992 case 128:
8993 vindex = 0;
8994 break;
8995 case 256:
8996 vindex = 1;
8997 break;
8998 case 512:
8999 vindex = 2;
9000 break;
9001 default:
9002 abort ();
9003 break;
9004 }
9005
9006 dp = &evex_len_table[dp->op[1].bytemode][vindex];
9007 break;
9008
9009 case USE_XOP_8F_TABLE:
9010 if (!fetch_code (ins->info, ins->codep + 3))
9011 return &err_opcode;
9012 ins->rex = ~(*ins->codep >> 5) & 0x7;
9013
9014 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
9015 switch ((*ins->codep & 0x1f))
9016 {
9017 default:
9018 dp = &bad_opcode;
9019 return dp;
9020 case 0x8:
9021 vex_table_index = XOP_08;
9022 break;
9023 case 0x9:
9024 vex_table_index = XOP_09;
9025 break;
9026 case 0xa:
9027 vex_table_index = XOP_0A;
9028 break;
9029 }
9030 ins->codep++;
9031 ins->vex.w = *ins->codep & 0x80;
9032 if (ins->vex.w && ins->address_mode == mode_64bit)
9033 ins->rex |= REX_W;
9034
9035 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9036 if (ins->address_mode != mode_64bit)
9037 {
9038 /* In 16/32-bit mode REX_B is silently ignored. */
9039 ins->rex &= ~REX_B;
9040 }
9041
9042 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9043 switch ((*ins->codep & 0x3))
9044 {
9045 case 0:
9046 break;
9047 case 1:
9048 ins->vex.prefix = DATA_PREFIX_OPCODE;
9049 break;
9050 case 2:
9051 ins->vex.prefix = REPE_PREFIX_OPCODE;
9052 break;
9053 case 3:
9054 ins->vex.prefix = REPNE_PREFIX_OPCODE;
9055 break;
9056 }
9057 ins->need_vex = true;
9058 ins->codep++;
9059 vindex = *ins->codep++;
9060 dp = &xop_table[vex_table_index][vindex];
9061
9062 ins->end_codep = ins->codep;
9063 if (!fetch_modrm (ins))
9064 return &err_opcode;
9065
9066 /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9067 having to decode the bits for every otherwise valid encoding. */
9068 if (ins->vex.prefix)
9069 return &bad_opcode;
9070 break;
9071
9072 case USE_VEX_C4_TABLE:
9073 /* VEX prefix. */
9074 if (!fetch_code (ins->info, ins->codep + 3))
9075 return &err_opcode;
9076 ins->rex = ~(*ins->codep >> 5) & 0x7;
9077 switch ((*ins->codep & 0x1f))
9078 {
9079 default:
9080 dp = &bad_opcode;
9081 return dp;
9082 case 0x1:
9083 vex_table_index = VEX_0F;
9084 break;
9085 case 0x2:
9086 vex_table_index = VEX_0F38;
9087 break;
9088 case 0x3:
9089 vex_table_index = VEX_0F3A;
9090 break;
9091 }
9092 ins->codep++;
9093 ins->vex.w = *ins->codep & 0x80;
9094 if (ins->address_mode == mode_64bit)
9095 {
9096 if (ins->vex.w)
9097 ins->rex |= REX_W;
9098 }
9099 else
9100 {
9101 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9102 is ignored, other REX bits are 0 and the highest bit in
9103 VEX.vvvv is also ignored (but we mustn't clear it here). */
9104 ins->rex = 0;
9105 }
9106 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9107 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9108 switch ((*ins->codep & 0x3))
9109 {
9110 case 0:
9111 break;
9112 case 1:
9113 ins->vex.prefix = DATA_PREFIX_OPCODE;
9114 break;
9115 case 2:
9116 ins->vex.prefix = REPE_PREFIX_OPCODE;
9117 break;
9118 case 3:
9119 ins->vex.prefix = REPNE_PREFIX_OPCODE;
9120 break;
9121 }
9122 ins->need_vex = true;
9123 ins->codep++;
9124 vindex = *ins->codep++;
9125 dp = &vex_table[vex_table_index][vindex];
9126 ins->end_codep = ins->codep;
9127 /* There is no MODRM byte for VEX0F 77. */
9128 if ((vex_table_index != VEX_0F || vindex != 0x77)
9129 && !fetch_modrm (ins))
9130 return &err_opcode;
9131 break;
9132
9133 case USE_VEX_C5_TABLE:
9134 /* VEX prefix. */
9135 if (!fetch_code (ins->info, ins->codep + 2))
9136 return &err_opcode;
9137 ins->rex = (*ins->codep & 0x80) ? 0 : REX_R;
9138
9139 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9140 VEX.vvvv is 1. */
9141 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9142 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9143 switch ((*ins->codep & 0x3))
9144 {
9145 case 0:
9146 break;
9147 case 1:
9148 ins->vex.prefix = DATA_PREFIX_OPCODE;
9149 break;
9150 case 2:
9151 ins->vex.prefix = REPE_PREFIX_OPCODE;
9152 break;
9153 case 3:
9154 ins->vex.prefix = REPNE_PREFIX_OPCODE;
9155 break;
9156 }
9157 ins->need_vex = true;
9158 ins->codep++;
9159 vindex = *ins->codep++;
9160 dp = &vex_table[dp->op[1].bytemode][vindex];
9161 ins->end_codep = ins->codep;
9162 /* There is no MODRM byte for VEX 77. */
9163 if (vindex != 0x77 && !fetch_modrm (ins))
9164 return &err_opcode;
9165 break;
9166
9167 case USE_VEX_W_TABLE:
9168 if (!ins->need_vex)
9169 abort ();
9170
9171 dp = &vex_w_table[dp->op[1].bytemode][ins->vex.w];
9172 break;
9173
9174 case USE_EVEX_TABLE:
9175 ins->two_source_ops = false;
9176 /* EVEX prefix. */
9177 ins->vex.evex = true;
9178 if (!fetch_code (ins->info, ins->codep + 4))
9179 return &err_opcode;
9180 /* The first byte after 0x62. */
9181 ins->rex = ~(*ins->codep >> 5) & 0x7;
9182 ins->vex.r = *ins->codep & 0x10;
9183 switch ((*ins->codep & 0xf))
9184 {
9185 default:
9186 return &bad_opcode;
9187 case 0x1:
9188 vex_table_index = EVEX_0F;
9189 break;
9190 case 0x2:
9191 vex_table_index = EVEX_0F38;
9192 break;
9193 case 0x3:
9194 vex_table_index = EVEX_0F3A;
9195 break;
9196 case 0x5:
9197 vex_table_index = EVEX_MAP5;
9198 break;
9199 case 0x6:
9200 vex_table_index = EVEX_MAP6;
9201 break;
9202 }
9203
9204 /* The second byte after 0x62. */
9205 ins->codep++;
9206 ins->vex.w = *ins->codep & 0x80;
9207 if (ins->vex.w && ins->address_mode == mode_64bit)
9208 ins->rex |= REX_W;
9209
9210 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9211
9212 /* The U bit. */
9213 if (!(*ins->codep & 0x4))
9214 return &bad_opcode;
9215
9216 switch ((*ins->codep & 0x3))
9217 {
9218 case 0:
9219 break;
9220 case 1:
9221 ins->vex.prefix = DATA_PREFIX_OPCODE;
9222 break;
9223 case 2:
9224 ins->vex.prefix = REPE_PREFIX_OPCODE;
9225 break;
9226 case 3:
9227 ins->vex.prefix = REPNE_PREFIX_OPCODE;
9228 break;
9229 }
9230
9231 /* The third byte after 0x62. */
9232 ins->codep++;
9233
9234 /* Remember the static rounding bits. */
9235 ins->vex.ll = (*ins->codep >> 5) & 3;
9236 ins->vex.b = *ins->codep & 0x10;
9237
9238 ins->vex.v = *ins->codep & 0x8;
9239 ins->vex.mask_register_specifier = *ins->codep & 0x7;
9240 ins->vex.zeroing = *ins->codep & 0x80;
9241
9242 if (ins->address_mode != mode_64bit)
9243 {
9244 /* In 16/32-bit mode silently ignore following bits. */
9245 ins->rex &= ~REX_B;
9246 ins->vex.r = true;
9247 }
9248
9249 ins->need_vex = true;
9250 ins->codep++;
9251 vindex = *ins->codep++;
9252 dp = &evex_table[vex_table_index][vindex];
9253 ins->end_codep = ins->codep;
9254 if (!fetch_modrm (ins))
9255 return &err_opcode;
9256
9257 /* Set vector length. */
9258 if (ins->modrm.mod == 3 && ins->vex.b)
9259 ins->vex.length = 512;
9260 else
9261 {
9262 switch (ins->vex.ll)
9263 {
9264 case 0x0:
9265 ins->vex.length = 128;
9266 break;
9267 case 0x1:
9268 ins->vex.length = 256;
9269 break;
9270 case 0x2:
9271 ins->vex.length = 512;
9272 break;
9273 default:
9274 return &bad_opcode;
9275 }
9276 }
9277 break;
9278
9279 case 0:
9280 dp = &bad_opcode;
9281 break;
9282
9283 default:
9284 abort ();
9285 }
9286
9287 if (dp->name != NULL)
9288 return dp;
9289 else
9290 return get_valid_dis386 (dp, ins);
9291 }
9292
9293 static bool
9294 get_sib (instr_info *ins, int sizeflag)
9295 {
9296 /* If modrm.mod == 3, operand must be register. */
9297 if (ins->need_modrm
9298 && ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
9299 && ins->modrm.mod != 3
9300 && ins->modrm.rm == 4)
9301 {
9302 if (!fetch_code (ins->info, ins->codep + 2))
9303 return false;
9304 ins->sib.index = (ins->codep[1] >> 3) & 7;
9305 ins->sib.scale = (ins->codep[1] >> 6) & 3;
9306 ins->sib.base = ins->codep[1] & 7;
9307 ins->has_sib = true;
9308 }
9309 else
9310 ins->has_sib = false;
9311
9312 return true;
9313 }
9314
9315 /* Like oappend_with_style (below) but always with text style. */
9316
9317 static void
9318 oappend (instr_info *ins, const char *s)
9319 {
9320 oappend_with_style (ins, s, dis_style_text);
9321 }
9322
9323 /* Like oappend (above), but S is a string starting with '%'. In
9324 Intel syntax, the '%' is elided. */
9325
9326 static void
9327 oappend_register (instr_info *ins, const char *s)
9328 {
9329 oappend_with_style (ins, s + ins->intel_syntax, dis_style_register);
9330 }
9331
9332 /* Wrap around a call to INS->info->fprintf_styled_func, printing FMT.
9333 STYLE is the default style to use in the fprintf_styled_func calls,
9334 however, FMT might include embedded style markers (see oappend_style),
9335 these embedded markers are not printed, but instead change the style
9336 used in the next fprintf_styled_func call. */
9337
9338 static void ATTRIBUTE_PRINTF_3
9339 i386_dis_printf (const disassemble_info *info, enum disassembler_style style,
9340 const char *fmt, ...)
9341 {
9342 va_list ap;
9343 enum disassembler_style curr_style = style;
9344 const char *start, *curr;
9345 char staging_area[40];
9346
9347 va_start (ap, fmt);
9348 /* In particular print_insn()'s processing of op_txt[] can hand rather long
9349 strings here. Bypass vsnprintf() in such cases to avoid capacity issues
9350 with the staging area. */
9351 if (strcmp (fmt, "%s"))
9352 {
9353 int res = vsnprintf (staging_area, sizeof (staging_area), fmt, ap);
9354
9355 va_end (ap);
9356
9357 if (res < 0)
9358 return;
9359
9360 if ((size_t) res >= sizeof (staging_area))
9361 abort ();
9362
9363 start = curr = staging_area;
9364 }
9365 else
9366 {
9367 start = curr = va_arg (ap, const char *);
9368 va_end (ap);
9369 }
9370
9371 do
9372 {
9373 if (*curr == '\0'
9374 || (*curr == STYLE_MARKER_CHAR
9375 && ISXDIGIT (*(curr + 1))
9376 && *(curr + 2) == STYLE_MARKER_CHAR))
9377 {
9378 /* Output content between our START position and CURR. */
9379 int len = curr - start;
9380 int n = (*info->fprintf_styled_func) (info->stream, curr_style,
9381 "%.*s", len, start);
9382 if (n < 0)
9383 break;
9384
9385 if (*curr == '\0')
9386 break;
9387
9388 /* Skip over the initial STYLE_MARKER_CHAR. */
9389 ++curr;
9390
9391 /* Update the CURR_STYLE. As there are less than 16 styles, it
9392 is possible, that if the input is corrupted in some way, that
9393 we might set CURR_STYLE to an invalid value. Don't worry
9394 though, we check for this situation. */
9395 if (*curr >= '0' && *curr <= '9')
9396 curr_style = (enum disassembler_style) (*curr - '0');
9397 else if (*curr >= 'a' && *curr <= 'f')
9398 curr_style = (enum disassembler_style) (*curr - 'a' + 10);
9399 else
9400 curr_style = dis_style_text;
9401
9402 /* Check for an invalid style having been selected. This should
9403 never happen, but it doesn't hurt to be a little paranoid. */
9404 if (curr_style > dis_style_comment_start)
9405 curr_style = dis_style_text;
9406
9407 /* Skip the hex character, and the closing STYLE_MARKER_CHAR. */
9408 curr += 2;
9409
9410 /* Reset the START to after the style marker. */
9411 start = curr;
9412 }
9413 else
9414 ++curr;
9415 }
9416 while (true);
9417 }
9418
9419 static int
9420 print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax)
9421 {
9422 const struct dis386 *dp;
9423 int i;
9424 int ret;
9425 char *op_txt[MAX_OPERANDS];
9426 int needcomma;
9427 bool intel_swap_2_3;
9428 int sizeflag, orig_sizeflag;
9429 const char *p;
9430 struct dis_private priv;
9431 int prefix_length;
9432 int op_count;
9433 instr_info ins = {
9434 .info = info,
9435 .intel_syntax = intel_syntax >= 0
9436 ? intel_syntax
9437 : (info->mach & bfd_mach_i386_intel_syntax) != 0,
9438 .intel_mnemonic = !SYSV386_COMPAT,
9439 .op_index[0 ... MAX_OPERANDS - 1] = -1,
9440 .start_pc = pc,
9441 .start_codep = priv.the_buffer,
9442 .codep = priv.the_buffer,
9443 .obufp = ins.obuf,
9444 .last_lock_prefix = -1,
9445 .last_repz_prefix = -1,
9446 .last_repnz_prefix = -1,
9447 .last_data_prefix = -1,
9448 .last_addr_prefix = -1,
9449 .last_rex_prefix = -1,
9450 .last_seg_prefix = -1,
9451 .fwait_prefix = -1,
9452 };
9453 char op_out[MAX_OPERANDS][MAX_OPERAND_BUFFER_SIZE];
9454
9455 priv.orig_sizeflag = AFLAG | DFLAG;
9456 if ((info->mach & bfd_mach_i386_i386) != 0)
9457 ins.address_mode = mode_32bit;
9458 else if (info->mach == bfd_mach_i386_i8086)
9459 {
9460 ins.address_mode = mode_16bit;
9461 priv.orig_sizeflag = 0;
9462 }
9463 else
9464 ins.address_mode = mode_64bit;
9465
9466 for (p = info->disassembler_options; p != NULL;)
9467 {
9468 if (startswith (p, "amd64"))
9469 ins.isa64 = amd64;
9470 else if (startswith (p, "intel64"))
9471 ins.isa64 = intel64;
9472 else if (startswith (p, "x86-64"))
9473 {
9474 ins.address_mode = mode_64bit;
9475 priv.orig_sizeflag |= AFLAG | DFLAG;
9476 }
9477 else if (startswith (p, "i386"))
9478 {
9479 ins.address_mode = mode_32bit;
9480 priv.orig_sizeflag |= AFLAG | DFLAG;
9481 }
9482 else if (startswith (p, "i8086"))
9483 {
9484 ins.address_mode = mode_16bit;
9485 priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9486 }
9487 else if (startswith (p, "intel"))
9488 {
9489 ins.intel_syntax = 1;
9490 if (startswith (p + 5, "-mnemonic"))
9491 ins.intel_mnemonic = true;
9492 }
9493 else if (startswith (p, "att"))
9494 {
9495 ins.intel_syntax = 0;
9496 if (startswith (p + 3, "-mnemonic"))
9497 ins.intel_mnemonic = false;
9498 }
9499 else if (startswith (p, "addr"))
9500 {
9501 if (ins.address_mode == mode_64bit)
9502 {
9503 if (p[4] == '3' && p[5] == '2')
9504 priv.orig_sizeflag &= ~AFLAG;
9505 else if (p[4] == '6' && p[5] == '4')
9506 priv.orig_sizeflag |= AFLAG;
9507 }
9508 else
9509 {
9510 if (p[4] == '1' && p[5] == '6')
9511 priv.orig_sizeflag &= ~AFLAG;
9512 else if (p[4] == '3' && p[5] == '2')
9513 priv.orig_sizeflag |= AFLAG;
9514 }
9515 }
9516 else if (startswith (p, "data"))
9517 {
9518 if (p[4] == '1' && p[5] == '6')
9519 priv.orig_sizeflag &= ~DFLAG;
9520 else if (p[4] == '3' && p[5] == '2')
9521 priv.orig_sizeflag |= DFLAG;
9522 }
9523 else if (startswith (p, "suffix"))
9524 priv.orig_sizeflag |= SUFFIX_ALWAYS;
9525
9526 p = strchr (p, ',');
9527 if (p != NULL)
9528 p++;
9529 }
9530
9531 if (ins.address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9532 {
9533 i386_dis_printf (info, dis_style_text, _("64-bit address is disabled"));
9534 return -1;
9535 }
9536
9537 if (ins.intel_syntax)
9538 {
9539 ins.open_char = '[';
9540 ins.close_char = ']';
9541 ins.separator_char = '+';
9542 ins.scale_char = '*';
9543 }
9544 else
9545 {
9546 ins.open_char = '(';
9547 ins.close_char = ')';
9548 ins.separator_char = ',';
9549 ins.scale_char = ',';
9550 }
9551
9552 /* The output looks better if we put 7 bytes on a line, since that
9553 puts most long word instructions on a single line. */
9554 info->bytes_per_line = 7;
9555
9556 info->private_data = &priv;
9557 priv.fetched = 0;
9558 priv.insn_start = pc;
9559
9560 for (i = 0; i < MAX_OPERANDS; ++i)
9561 {
9562 op_out[i][0] = 0;
9563 ins.op_out[i] = op_out[i];
9564 }
9565
9566 sizeflag = priv.orig_sizeflag;
9567
9568 switch (ckprefix (&ins))
9569 {
9570 case ckp_okay:
9571 break;
9572
9573 case ckp_bogus:
9574 /* Too many prefixes or unused REX prefixes. */
9575 for (i = 0;
9576 i < (int) ARRAY_SIZE (ins.all_prefixes) && ins.all_prefixes[i];
9577 i++)
9578 i386_dis_printf (info, dis_style_mnemonic, "%s%s",
9579 (i == 0 ? "" : " "),
9580 prefix_name (ins.address_mode, ins.all_prefixes[i],
9581 sizeflag));
9582 ret = i;
9583 goto out;
9584
9585 case ckp_fetch_error:
9586 goto fetch_error_out;
9587 }
9588
9589 ins.nr_prefixes = ins.codep - ins.start_codep;
9590
9591 if (!fetch_code (info, ins.codep + 1))
9592 {
9593 fetch_error_out:
9594 ret = fetch_error (&ins);
9595 goto out;
9596 }
9597
9598 ins.two_source_ops = (*ins.codep == 0x62 || *ins.codep == 0xc8);
9599
9600 if ((ins.prefixes & PREFIX_FWAIT)
9601 && (*ins.codep < 0xd8 || *ins.codep > 0xdf))
9602 {
9603 /* Handle ins.prefixes before fwait. */
9604 for (i = 0; i < ins.fwait_prefix && ins.all_prefixes[i];
9605 i++)
9606 i386_dis_printf (info, dis_style_mnemonic, "%s ",
9607 prefix_name (ins.address_mode, ins.all_prefixes[i],
9608 sizeflag));
9609 i386_dis_printf (info, dis_style_mnemonic, "fwait");
9610 ret = i + 1;
9611 goto out;
9612 }
9613
9614 if (*ins.codep == 0x0f)
9615 {
9616 unsigned char threebyte;
9617
9618 ins.codep++;
9619 if (!fetch_code (info, ins.codep + 1))
9620 goto fetch_error_out;
9621 threebyte = *ins.codep;
9622 dp = &dis386_twobyte[threebyte];
9623 ins.need_modrm = twobyte_has_modrm[threebyte];
9624 ins.codep++;
9625 }
9626 else
9627 {
9628 dp = &dis386[*ins.codep];
9629 ins.need_modrm = onebyte_has_modrm[*ins.codep];
9630 ins.codep++;
9631 }
9632
9633 /* Save sizeflag for printing the extra ins.prefixes later before updating
9634 it for mnemonic and operand processing. The prefix names depend
9635 only on the address mode. */
9636 orig_sizeflag = sizeflag;
9637 if (ins.prefixes & PREFIX_ADDR)
9638 sizeflag ^= AFLAG;
9639 if ((ins.prefixes & PREFIX_DATA))
9640 sizeflag ^= DFLAG;
9641
9642 ins.end_codep = ins.codep;
9643 if (ins.need_modrm && !fetch_modrm (&ins))
9644 goto fetch_error_out;
9645
9646 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9647 {
9648 if (!get_sib (&ins, sizeflag)
9649 || !dofloat (&ins, sizeflag))
9650 goto fetch_error_out;
9651 }
9652 else
9653 {
9654 dp = get_valid_dis386 (dp, &ins);
9655 if (dp == &err_opcode)
9656 goto fetch_error_out;
9657 if (dp != NULL && putop (&ins, dp->name, sizeflag) == 0)
9658 {
9659 if (!get_sib (&ins, sizeflag))
9660 goto fetch_error_out;
9661 for (i = 0; i < MAX_OPERANDS; ++i)
9662 {
9663 ins.obufp = ins.op_out[i];
9664 ins.op_ad = MAX_OPERANDS - 1 - i;
9665 if (dp->op[i].rtn
9666 && !dp->op[i].rtn (&ins, dp->op[i].bytemode, sizeflag))
9667 goto fetch_error_out;
9668 /* For EVEX instruction after the last operand masking
9669 should be printed. */
9670 if (i == 0 && ins.vex.evex)
9671 {
9672 /* Don't print {%k0}. */
9673 if (ins.vex.mask_register_specifier)
9674 {
9675 const char *reg_name
9676 = att_names_mask[ins.vex.mask_register_specifier];
9677
9678 oappend (&ins, "{");
9679 oappend_register (&ins, reg_name);
9680 oappend (&ins, "}");
9681
9682 if (ins.vex.zeroing)
9683 oappend (&ins, "{z}");
9684 }
9685 else if (ins.vex.zeroing)
9686 {
9687 oappend (&ins, "{bad}");
9688 continue;
9689 }
9690
9691 /* Instructions with a mask register destination allow for
9692 zeroing-masking only (if any masking at all), which is
9693 _not_ expressed by EVEX.z. */
9694 if (ins.vex.zeroing && dp->op[0].bytemode == mask_mode)
9695 ins.illegal_masking = true;
9696
9697 /* S/G insns require a mask and don't allow
9698 zeroing-masking. */
9699 if ((dp->op[0].bytemode == vex_vsib_d_w_dq_mode
9700 || dp->op[0].bytemode == vex_vsib_q_w_dq_mode)
9701 && (ins.vex.mask_register_specifier == 0
9702 || ins.vex.zeroing))
9703 ins.illegal_masking = true;
9704
9705 if (ins.illegal_masking)
9706 oappend (&ins, "/(bad)");
9707 }
9708 }
9709
9710 /* Check whether rounding control was enabled for an insn not
9711 supporting it. */
9712 if (ins.modrm.mod == 3 && ins.vex.b
9713 && !(ins.evex_used & EVEX_b_used))
9714 {
9715 for (i = 0; i < MAX_OPERANDS; ++i)
9716 {
9717 ins.obufp = ins.op_out[i];
9718 if (*ins.obufp)
9719 continue;
9720 oappend (&ins, names_rounding[ins.vex.ll]);
9721 oappend (&ins, "bad}");
9722 break;
9723 }
9724 }
9725 }
9726 }
9727
9728 /* Clear instruction information. */
9729 info->insn_info_valid = 0;
9730 info->branch_delay_insns = 0;
9731 info->data_size = 0;
9732 info->insn_type = dis_noninsn;
9733 info->target = 0;
9734 info->target2 = 0;
9735
9736 /* Reset jump operation indicator. */
9737 ins.op_is_jump = false;
9738 {
9739 int jump_detection = 0;
9740
9741 /* Extract flags. */
9742 for (i = 0; i < MAX_OPERANDS; ++i)
9743 {
9744 if ((dp->op[i].rtn == OP_J)
9745 || (dp->op[i].rtn == OP_indirE))
9746 jump_detection |= 1;
9747 else if ((dp->op[i].rtn == BND_Fixup)
9748 || (!dp->op[i].rtn && !dp->op[i].bytemode))
9749 jump_detection |= 2;
9750 else if ((dp->op[i].bytemode == cond_jump_mode)
9751 || (dp->op[i].bytemode == loop_jcxz_mode))
9752 jump_detection |= 4;
9753 }
9754
9755 /* Determine if this is a jump or branch. */
9756 if ((jump_detection & 0x3) == 0x3)
9757 {
9758 ins.op_is_jump = true;
9759 if (jump_detection & 0x4)
9760 info->insn_type = dis_condbranch;
9761 else
9762 info->insn_type = (dp->name && !strncmp (dp->name, "call", 4))
9763 ? dis_jsr : dis_branch;
9764 }
9765 }
9766
9767 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9768 are all 0s in inverted form. */
9769 if (ins.need_vex && ins.vex.register_specifier != 0)
9770 {
9771 i386_dis_printf (info, dis_style_text, "(bad)");
9772 ret = ins.end_codep - priv.the_buffer;
9773 goto out;
9774 }
9775
9776 switch (dp->prefix_requirement)
9777 {
9778 case PREFIX_DATA:
9779 /* If only the data prefix is marked as mandatory, its absence renders
9780 the encoding invalid. Most other PREFIX_OPCODE rules still apply. */
9781 if (ins.need_vex ? !ins.vex.prefix : !(ins.prefixes & PREFIX_DATA))
9782 {
9783 i386_dis_printf (info, dis_style_text, "(bad)");
9784 ret = ins.end_codep - priv.the_buffer;
9785 goto out;
9786 }
9787 ins.used_prefixes |= PREFIX_DATA;
9788 /* Fall through. */
9789 case PREFIX_OPCODE:
9790 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
9791 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
9792 used by putop and MMX/SSE operand and may be overridden by the
9793 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
9794 separately. */
9795 if (((ins.need_vex
9796 ? ins.vex.prefix == REPE_PREFIX_OPCODE
9797 || ins.vex.prefix == REPNE_PREFIX_OPCODE
9798 : (ins.prefixes
9799 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9800 && (ins.used_prefixes
9801 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
9802 || (((ins.need_vex
9803 ? ins.vex.prefix == DATA_PREFIX_OPCODE
9804 : ((ins.prefixes
9805 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
9806 == PREFIX_DATA))
9807 && (ins.used_prefixes & PREFIX_DATA) == 0))
9808 || (ins.vex.evex && dp->prefix_requirement != PREFIX_DATA
9809 && !ins.vex.w != !(ins.used_prefixes & PREFIX_DATA)))
9810 {
9811 i386_dis_printf (info, dis_style_text, "(bad)");
9812 ret = ins.end_codep - priv.the_buffer;
9813 goto out;
9814 }
9815 break;
9816
9817 case PREFIX_IGNORED:
9818 /* Zap data size and rep prefixes from used_prefixes and reinstate their
9819 origins in all_prefixes. */
9820 ins.used_prefixes &= ~PREFIX_OPCODE;
9821 if (ins.last_data_prefix >= 0)
9822 ins.all_prefixes[ins.last_data_prefix] = 0x66;
9823 if (ins.last_repz_prefix >= 0)
9824 ins.all_prefixes[ins.last_repz_prefix] = 0xf3;
9825 if (ins.last_repnz_prefix >= 0)
9826 ins.all_prefixes[ins.last_repnz_prefix] = 0xf2;
9827 break;
9828 }
9829
9830 /* Check if the REX prefix is used. */
9831 if ((ins.rex ^ ins.rex_used) == 0
9832 && !ins.need_vex && ins.last_rex_prefix >= 0)
9833 ins.all_prefixes[ins.last_rex_prefix] = 0;
9834
9835 /* Check if the SEG prefix is used. */
9836 if ((ins.prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
9837 | PREFIX_FS | PREFIX_GS)) != 0
9838 && (ins.used_prefixes & ins.active_seg_prefix) != 0)
9839 ins.all_prefixes[ins.last_seg_prefix] = 0;
9840
9841 /* Check if the ADDR prefix is used. */
9842 if ((ins.prefixes & PREFIX_ADDR) != 0
9843 && (ins.used_prefixes & PREFIX_ADDR) != 0)
9844 ins.all_prefixes[ins.last_addr_prefix] = 0;
9845
9846 /* Check if the DATA prefix is used. */
9847 if ((ins.prefixes & PREFIX_DATA) != 0
9848 && (ins.used_prefixes & PREFIX_DATA) != 0
9849 && !ins.need_vex)
9850 ins.all_prefixes[ins.last_data_prefix] = 0;
9851
9852 /* Print the extra ins.prefixes. */
9853 prefix_length = 0;
9854 for (i = 0; i < (int) ARRAY_SIZE (ins.all_prefixes); i++)
9855 if (ins.all_prefixes[i])
9856 {
9857 const char *name = prefix_name (ins.address_mode, ins.all_prefixes[i],
9858 orig_sizeflag);
9859
9860 if (name == NULL)
9861 abort ();
9862 prefix_length += strlen (name) + 1;
9863 i386_dis_printf (info, dis_style_mnemonic, "%s ", name);
9864 }
9865
9866 /* Check maximum code length. */
9867 if ((ins.codep - ins.start_codep) > MAX_CODE_LENGTH)
9868 {
9869 i386_dis_printf (info, dis_style_text, "(bad)");
9870 ret = MAX_CODE_LENGTH;
9871 goto out;
9872 }
9873
9874 /* Calculate the number of operands this instruction has. */
9875 op_count = 0;
9876 for (i = 0; i < MAX_OPERANDS; ++i)
9877 if (*ins.op_out[i] != '\0')
9878 ++op_count;
9879
9880 /* Calculate the number of spaces to print after the mnemonic. */
9881 ins.obufp = ins.mnemonicendp;
9882 if (op_count > 0)
9883 {
9884 i = strlen (ins.obuf) + prefix_length;
9885 if (i < 7)
9886 i = 7 - i;
9887 else
9888 i = 1;
9889 }
9890 else
9891 i = 0;
9892
9893 /* Print the instruction mnemonic along with any trailing whitespace. */
9894 i386_dis_printf (info, dis_style_mnemonic, "%s%*s", ins.obuf, i, "");
9895
9896 /* The enter and bound instructions are printed with operands in the same
9897 order as the intel book; everything else is printed in reverse order. */
9898 intel_swap_2_3 = false;
9899 if (ins.intel_syntax || ins.two_source_ops)
9900 {
9901 for (i = 0; i < MAX_OPERANDS; ++i)
9902 op_txt[i] = ins.op_out[i];
9903
9904 if (ins.intel_syntax && dp && dp->op[2].rtn == OP_Rounding
9905 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
9906 {
9907 op_txt[2] = ins.op_out[3];
9908 op_txt[3] = ins.op_out[2];
9909 intel_swap_2_3 = true;
9910 }
9911
9912 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
9913 {
9914 bool riprel;
9915
9916 ins.op_ad = ins.op_index[i];
9917 ins.op_index[i] = ins.op_index[MAX_OPERANDS - 1 - i];
9918 ins.op_index[MAX_OPERANDS - 1 - i] = ins.op_ad;
9919 riprel = ins.op_riprel[i];
9920 ins.op_riprel[i] = ins.op_riprel[MAX_OPERANDS - 1 - i];
9921 ins.op_riprel[MAX_OPERANDS - 1 - i] = riprel;
9922 }
9923 }
9924 else
9925 {
9926 for (i = 0; i < MAX_OPERANDS; ++i)
9927 op_txt[MAX_OPERANDS - 1 - i] = ins.op_out[i];
9928 }
9929
9930 needcomma = 0;
9931 for (i = 0; i < MAX_OPERANDS; ++i)
9932 if (*op_txt[i])
9933 {
9934 /* In Intel syntax embedded rounding / SAE are not separate operands.
9935 Instead they're attached to the prior register operand. Simply
9936 suppress emission of the comma to achieve that effect. */
9937 switch (i & -(ins.intel_syntax && dp))
9938 {
9939 case 2:
9940 if (dp->op[2].rtn == OP_Rounding && !intel_swap_2_3)
9941 needcomma = 0;
9942 break;
9943 case 3:
9944 if (dp->op[3].rtn == OP_Rounding || intel_swap_2_3)
9945 needcomma = 0;
9946 break;
9947 }
9948 if (needcomma)
9949 i386_dis_printf (info, dis_style_text, ",");
9950 if (ins.op_index[i] != -1 && !ins.op_riprel[i])
9951 {
9952 bfd_vma target = (bfd_vma) ins.op_address[ins.op_index[i]];
9953
9954 if (ins.op_is_jump)
9955 {
9956 info->insn_info_valid = 1;
9957 info->branch_delay_insns = 0;
9958 info->data_size = 0;
9959 info->target = target;
9960 info->target2 = 0;
9961 }
9962 (*info->print_address_func) (target, info);
9963 }
9964 else
9965 i386_dis_printf (info, dis_style_text, "%s", op_txt[i]);
9966 needcomma = 1;
9967 }
9968
9969 for (i = 0; i < MAX_OPERANDS; i++)
9970 if (ins.op_index[i] != -1 && ins.op_riprel[i])
9971 {
9972 i386_dis_printf (info, dis_style_comment_start, " # ");
9973 (*info->print_address_func)
9974 ((bfd_vma)(ins.start_pc + (ins.codep - ins.start_codep)
9975 + ins.op_address[ins.op_index[i]]),
9976 info);
9977 break;
9978 }
9979 ret = ins.codep - priv.the_buffer;
9980 out:
9981 info->private_data = NULL;
9982 return ret;
9983 }
9984
9985 /* Here for backwards compatibility. When gdb stops using
9986 print_insn_i386_att and print_insn_i386_intel these functions can
9987 disappear, and print_insn_i386 be merged into print_insn. */
9988 int
9989 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9990 {
9991 return print_insn (pc, info, 0);
9992 }
9993
9994 int
9995 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9996 {
9997 return print_insn (pc, info, 1);
9998 }
9999
10000 int
10001 print_insn_i386 (bfd_vma pc, disassemble_info *info)
10002 {
10003 return print_insn (pc, info, -1);
10004 }
10005
10006 static const char *float_mem[] = {
10007 /* d8 */
10008 "fadd{s|}",
10009 "fmul{s|}",
10010 "fcom{s|}",
10011 "fcomp{s|}",
10012 "fsub{s|}",
10013 "fsubr{s|}",
10014 "fdiv{s|}",
10015 "fdivr{s|}",
10016 /* d9 */
10017 "fld{s|}",
10018 "(bad)",
10019 "fst{s|}",
10020 "fstp{s|}",
10021 "fldenv{C|C}",
10022 "fldcw",
10023 "fNstenv{C|C}",
10024 "fNstcw",
10025 /* da */
10026 "fiadd{l|}",
10027 "fimul{l|}",
10028 "ficom{l|}",
10029 "ficomp{l|}",
10030 "fisub{l|}",
10031 "fisubr{l|}",
10032 "fidiv{l|}",
10033 "fidivr{l|}",
10034 /* db */
10035 "fild{l|}",
10036 "fisttp{l|}",
10037 "fist{l|}",
10038 "fistp{l|}",
10039 "(bad)",
10040 "fld{t|}",
10041 "(bad)",
10042 "fstp{t|}",
10043 /* dc */
10044 "fadd{l|}",
10045 "fmul{l|}",
10046 "fcom{l|}",
10047 "fcomp{l|}",
10048 "fsub{l|}",
10049 "fsubr{l|}",
10050 "fdiv{l|}",
10051 "fdivr{l|}",
10052 /* dd */
10053 "fld{l|}",
10054 "fisttp{ll|}",
10055 "fst{l||}",
10056 "fstp{l|}",
10057 "frstor{C|C}",
10058 "(bad)",
10059 "fNsave{C|C}",
10060 "fNstsw",
10061 /* de */
10062 "fiadd{s|}",
10063 "fimul{s|}",
10064 "ficom{s|}",
10065 "ficomp{s|}",
10066 "fisub{s|}",
10067 "fisubr{s|}",
10068 "fidiv{s|}",
10069 "fidivr{s|}",
10070 /* df */
10071 "fild{s|}",
10072 "fisttp{s|}",
10073 "fist{s|}",
10074 "fistp{s|}",
10075 "fbld",
10076 "fild{ll|}",
10077 "fbstp",
10078 "fistp{ll|}",
10079 };
10080
10081 static const unsigned char float_mem_mode[] = {
10082 /* d8 */
10083 d_mode,
10084 d_mode,
10085 d_mode,
10086 d_mode,
10087 d_mode,
10088 d_mode,
10089 d_mode,
10090 d_mode,
10091 /* d9 */
10092 d_mode,
10093 0,
10094 d_mode,
10095 d_mode,
10096 0,
10097 w_mode,
10098 0,
10099 w_mode,
10100 /* da */
10101 d_mode,
10102 d_mode,
10103 d_mode,
10104 d_mode,
10105 d_mode,
10106 d_mode,
10107 d_mode,
10108 d_mode,
10109 /* db */
10110 d_mode,
10111 d_mode,
10112 d_mode,
10113 d_mode,
10114 0,
10115 t_mode,
10116 0,
10117 t_mode,
10118 /* dc */
10119 q_mode,
10120 q_mode,
10121 q_mode,
10122 q_mode,
10123 q_mode,
10124 q_mode,
10125 q_mode,
10126 q_mode,
10127 /* dd */
10128 q_mode,
10129 q_mode,
10130 q_mode,
10131 q_mode,
10132 0,
10133 0,
10134 0,
10135 w_mode,
10136 /* de */
10137 w_mode,
10138 w_mode,
10139 w_mode,
10140 w_mode,
10141 w_mode,
10142 w_mode,
10143 w_mode,
10144 w_mode,
10145 /* df */
10146 w_mode,
10147 w_mode,
10148 w_mode,
10149 w_mode,
10150 t_mode,
10151 q_mode,
10152 t_mode,
10153 q_mode
10154 };
10155
10156 #define ST { OP_ST, 0 }
10157 #define STi { OP_STi, 0 }
10158
10159 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10160 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10161 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10162 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10163 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10164 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10165 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10166 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10167 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10168
10169 static const struct dis386 float_reg[][8] = {
10170 /* d8 */
10171 {
10172 { "fadd", { ST, STi }, 0 },
10173 { "fmul", { ST, STi }, 0 },
10174 { "fcom", { STi }, 0 },
10175 { "fcomp", { STi }, 0 },
10176 { "fsub", { ST, STi }, 0 },
10177 { "fsubr", { ST, STi }, 0 },
10178 { "fdiv", { ST, STi }, 0 },
10179 { "fdivr", { ST, STi }, 0 },
10180 },
10181 /* d9 */
10182 {
10183 { "fld", { STi }, 0 },
10184 { "fxch", { STi }, 0 },
10185 { FGRPd9_2 },
10186 { Bad_Opcode },
10187 { FGRPd9_4 },
10188 { FGRPd9_5 },
10189 { FGRPd9_6 },
10190 { FGRPd9_7 },
10191 },
10192 /* da */
10193 {
10194 { "fcmovb", { ST, STi }, 0 },
10195 { "fcmove", { ST, STi }, 0 },
10196 { "fcmovbe",{ ST, STi }, 0 },
10197 { "fcmovu", { ST, STi }, 0 },
10198 { Bad_Opcode },
10199 { FGRPda_5 },
10200 { Bad_Opcode },
10201 { Bad_Opcode },
10202 },
10203 /* db */
10204 {
10205 { "fcmovnb",{ ST, STi }, 0 },
10206 { "fcmovne",{ ST, STi }, 0 },
10207 { "fcmovnbe",{ ST, STi }, 0 },
10208 { "fcmovnu",{ ST, STi }, 0 },
10209 { FGRPdb_4 },
10210 { "fucomi", { ST, STi }, 0 },
10211 { "fcomi", { ST, STi }, 0 },
10212 { Bad_Opcode },
10213 },
10214 /* dc */
10215 {
10216 { "fadd", { STi, ST }, 0 },
10217 { "fmul", { STi, ST }, 0 },
10218 { Bad_Opcode },
10219 { Bad_Opcode },
10220 { "fsub{!M|r}", { STi, ST }, 0 },
10221 { "fsub{M|}", { STi, ST }, 0 },
10222 { "fdiv{!M|r}", { STi, ST }, 0 },
10223 { "fdiv{M|}", { STi, ST }, 0 },
10224 },
10225 /* dd */
10226 {
10227 { "ffree", { STi }, 0 },
10228 { Bad_Opcode },
10229 { "fst", { STi }, 0 },
10230 { "fstp", { STi }, 0 },
10231 { "fucom", { STi }, 0 },
10232 { "fucomp", { STi }, 0 },
10233 { Bad_Opcode },
10234 { Bad_Opcode },
10235 },
10236 /* de */
10237 {
10238 { "faddp", { STi, ST }, 0 },
10239 { "fmulp", { STi, ST }, 0 },
10240 { Bad_Opcode },
10241 { FGRPde_3 },
10242 { "fsub{!M|r}p", { STi, ST }, 0 },
10243 { "fsub{M|}p", { STi, ST }, 0 },
10244 { "fdiv{!M|r}p", { STi, ST }, 0 },
10245 { "fdiv{M|}p", { STi, ST }, 0 },
10246 },
10247 /* df */
10248 {
10249 { "ffreep", { STi }, 0 },
10250 { Bad_Opcode },
10251 { Bad_Opcode },
10252 { Bad_Opcode },
10253 { FGRPdf_4 },
10254 { "fucomip", { ST, STi }, 0 },
10255 { "fcomip", { ST, STi }, 0 },
10256 { Bad_Opcode },
10257 },
10258 };
10259
10260 static const char *const fgrps[][8] = {
10261 /* Bad opcode 0 */
10262 {
10263 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10264 },
10265
10266 /* d9_2 1 */
10267 {
10268 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10269 },
10270
10271 /* d9_4 2 */
10272 {
10273 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10274 },
10275
10276 /* d9_5 3 */
10277 {
10278 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10279 },
10280
10281 /* d9_6 4 */
10282 {
10283 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10284 },
10285
10286 /* d9_7 5 */
10287 {
10288 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10289 },
10290
10291 /* da_5 6 */
10292 {
10293 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10294 },
10295
10296 /* db_4 7 */
10297 {
10298 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10299 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10300 },
10301
10302 /* de_3 8 */
10303 {
10304 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10305 },
10306
10307 /* df_4 9 */
10308 {
10309 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10310 },
10311 };
10312
10313 static void
10314 swap_operand (instr_info *ins)
10315 {
10316 ins->mnemonicendp[0] = '.';
10317 ins->mnemonicendp[1] = 's';
10318 ins->mnemonicendp[2] = '\0';
10319 ins->mnemonicendp += 2;
10320 }
10321
10322 static bool
10323 OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10324 int sizeflag ATTRIBUTE_UNUSED)
10325 {
10326 /* Skip mod/rm byte. */
10327 MODRM_CHECK;
10328 ins->codep++;
10329 return true;
10330 }
10331
10332 static bool
10333 dofloat (instr_info *ins, int sizeflag)
10334 {
10335 const struct dis386 *dp;
10336 unsigned char floatop = ins->codep[-1];
10337
10338 if (ins->modrm.mod != 3)
10339 {
10340 int fp_indx = (floatop - 0xd8) * 8 + ins->modrm.reg;
10341
10342 putop (ins, float_mem[fp_indx], sizeflag);
10343 ins->obufp = ins->op_out[0];
10344 ins->op_ad = 2;
10345 return OP_E (ins, float_mem_mode[fp_indx], sizeflag);
10346 }
10347 /* Skip mod/rm byte. */
10348 MODRM_CHECK;
10349 ins->codep++;
10350
10351 dp = &float_reg[floatop - 0xd8][ins->modrm.reg];
10352 if (dp->name == NULL)
10353 {
10354 putop (ins, fgrps[dp->op[0].bytemode][ins->modrm.rm], sizeflag);
10355
10356 /* Instruction fnstsw is only one with strange arg. */
10357 if (floatop == 0xdf && ins->codep[-1] == 0xe0)
10358 strcpy (ins->op_out[0], att_names16[0] + ins->intel_syntax);
10359 }
10360 else
10361 {
10362 putop (ins, dp->name, sizeflag);
10363
10364 ins->obufp = ins->op_out[0];
10365 ins->op_ad = 2;
10366 if (dp->op[0].rtn
10367 && !dp->op[0].rtn (ins, dp->op[0].bytemode, sizeflag))
10368 return false;
10369
10370 ins->obufp = ins->op_out[1];
10371 ins->op_ad = 1;
10372 if (dp->op[1].rtn
10373 && !dp->op[1].rtn (ins, dp->op[1].bytemode, sizeflag))
10374 return false;
10375 }
10376 return true;
10377 }
10378
10379 static bool
10380 OP_ST (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10381 int sizeflag ATTRIBUTE_UNUSED)
10382 {
10383 oappend_register (ins, "%st");
10384 return true;
10385 }
10386
10387 static bool
10388 OP_STi (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10389 int sizeflag ATTRIBUTE_UNUSED)
10390 {
10391 char scratch[8];
10392 int res = snprintf (scratch, ARRAY_SIZE (scratch), "%%st(%d)", ins->modrm.rm);
10393
10394 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
10395 abort ();
10396 oappend_register (ins, scratch);
10397 return true;
10398 }
10399
10400 /* Capital letters in template are macros. */
10401 static int
10402 putop (instr_info *ins, const char *in_template, int sizeflag)
10403 {
10404 const char *p;
10405 int alt = 0;
10406 int cond = 1;
10407 unsigned int l = 0, len = 0;
10408 char last[4];
10409
10410 for (p = in_template; *p; p++)
10411 {
10412 if (len > l)
10413 {
10414 if (l >= sizeof (last) || !ISUPPER (*p))
10415 abort ();
10416 last[l++] = *p;
10417 continue;
10418 }
10419 switch (*p)
10420 {
10421 default:
10422 *ins->obufp++ = *p;
10423 break;
10424 case '%':
10425 len++;
10426 break;
10427 case '!':
10428 cond = 0;
10429 break;
10430 case '{':
10431 if (ins->intel_syntax)
10432 {
10433 while (*++p != '|')
10434 if (*p == '}' || *p == '\0')
10435 abort ();
10436 alt = 1;
10437 }
10438 break;
10439 case '|':
10440 while (*++p != '}')
10441 {
10442 if (*p == '\0')
10443 abort ();
10444 }
10445 break;
10446 case '}':
10447 alt = 0;
10448 break;
10449 case 'A':
10450 if (ins->intel_syntax)
10451 break;
10452 if ((ins->need_modrm && ins->modrm.mod != 3)
10453 || (sizeflag & SUFFIX_ALWAYS))
10454 *ins->obufp++ = 'b';
10455 break;
10456 case 'B':
10457 if (l == 0)
10458 {
10459 case_B:
10460 if (ins->intel_syntax)
10461 break;
10462 if (sizeflag & SUFFIX_ALWAYS)
10463 *ins->obufp++ = 'b';
10464 }
10465 else if (l == 1 && last[0] == 'L')
10466 {
10467 if (ins->address_mode == mode_64bit
10468 && !(ins->prefixes & PREFIX_ADDR))
10469 {
10470 *ins->obufp++ = 'a';
10471 *ins->obufp++ = 'b';
10472 *ins->obufp++ = 's';
10473 }
10474
10475 goto case_B;
10476 }
10477 else
10478 abort ();
10479 break;
10480 case 'C':
10481 if (ins->intel_syntax && !alt)
10482 break;
10483 if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10484 {
10485 if (sizeflag & DFLAG)
10486 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10487 else
10488 *ins->obufp++ = ins->intel_syntax ? 'w' : 's';
10489 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10490 }
10491 break;
10492 case 'D':
10493 if (l == 1)
10494 {
10495 switch (last[0])
10496 {
10497 case 'X':
10498 if (!ins->vex.evex || ins->vex.w)
10499 *ins->obufp++ = 'd';
10500 else
10501 oappend (ins, "{bad}");
10502 break;
10503 default:
10504 abort ();
10505 }
10506 break;
10507 }
10508 if (l)
10509 abort ();
10510 if (ins->intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10511 break;
10512 USED_REX (REX_W);
10513 if (ins->modrm.mod == 3)
10514 {
10515 if (ins->rex & REX_W)
10516 *ins->obufp++ = 'q';
10517 else
10518 {
10519 if (sizeflag & DFLAG)
10520 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10521 else
10522 *ins->obufp++ = 'w';
10523 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10524 }
10525 }
10526 else
10527 *ins->obufp++ = 'w';
10528 break;
10529 case 'E':
10530 if (l == 1)
10531 {
10532 switch (last[0])
10533 {
10534 case 'X':
10535 if (!ins->vex.evex || ins->vex.b || ins->vex.ll >= 2
10536 || !ins->vex.r
10537 || (ins->modrm.mod == 3 && (ins->rex & REX_X))
10538 || !ins->vex.v || ins->vex.mask_register_specifier)
10539 break;
10540 /* AVX512 extends a number of V*D insns to also have V*Q variants,
10541 merely distinguished by EVEX.W. Look for a use of the
10542 respective macro. */
10543 if (ins->vex.w)
10544 {
10545 const char *pct = strchr (p + 1, '%');
10546
10547 if (pct != NULL && pct[1] == 'D' && pct[2] == 'Q')
10548 break;
10549 }
10550 *ins->obufp++ = '{';
10551 *ins->obufp++ = 'e';
10552 *ins->obufp++ = 'v';
10553 *ins->obufp++ = 'e';
10554 *ins->obufp++ = 'x';
10555 *ins->obufp++ = '}';
10556 *ins->obufp++ = ' ';
10557 break;
10558 default:
10559 abort ();
10560 }
10561 break;
10562 }
10563 /* For jcxz/jecxz */
10564 if (ins->address_mode == mode_64bit)
10565 {
10566 if (sizeflag & AFLAG)
10567 *ins->obufp++ = 'r';
10568 else
10569 *ins->obufp++ = 'e';
10570 }
10571 else
10572 if (sizeflag & AFLAG)
10573 *ins->obufp++ = 'e';
10574 ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10575 break;
10576 case 'F':
10577 if (ins->intel_syntax)
10578 break;
10579 if ((ins->prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10580 {
10581 if (sizeflag & AFLAG)
10582 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
10583 else
10584 *ins->obufp++ = ins->address_mode == mode_64bit ? 'l' : 'w';
10585 ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10586 }
10587 break;
10588 case 'G':
10589 if (ins->intel_syntax || (ins->obufp[-1] != 's'
10590 && !(sizeflag & SUFFIX_ALWAYS)))
10591 break;
10592 if ((ins->rex & REX_W) || (sizeflag & DFLAG))
10593 *ins->obufp++ = 'l';
10594 else
10595 *ins->obufp++ = 'w';
10596 if (!(ins->rex & REX_W))
10597 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10598 break;
10599 case 'H':
10600 if (l == 0)
10601 {
10602 if (ins->intel_syntax)
10603 break;
10604 if ((ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10605 || (ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10606 {
10607 ins->used_prefixes |= ins->prefixes & (PREFIX_CS | PREFIX_DS);
10608 *ins->obufp++ = ',';
10609 *ins->obufp++ = 'p';
10610
10611 /* Set active_seg_prefix even if not set in 64-bit mode
10612 because here it is a valid branch hint. */
10613 if (ins->prefixes & PREFIX_DS)
10614 {
10615 ins->active_seg_prefix = PREFIX_DS;
10616 *ins->obufp++ = 't';
10617 }
10618 else
10619 {
10620 ins->active_seg_prefix = PREFIX_CS;
10621 *ins->obufp++ = 'n';
10622 }
10623 }
10624 }
10625 else if (l == 1 && last[0] == 'X')
10626 {
10627 if (!ins->vex.w)
10628 *ins->obufp++ = 'h';
10629 else
10630 oappend (ins, "{bad}");
10631 }
10632 else
10633 abort ();
10634 break;
10635 case 'K':
10636 USED_REX (REX_W);
10637 if (ins->rex & REX_W)
10638 *ins->obufp++ = 'q';
10639 else
10640 *ins->obufp++ = 'd';
10641 break;
10642 case 'L':
10643 abort ();
10644 case 'M':
10645 if (ins->intel_mnemonic != cond)
10646 *ins->obufp++ = 'r';
10647 break;
10648 case 'N':
10649 if ((ins->prefixes & PREFIX_FWAIT) == 0)
10650 *ins->obufp++ = 'n';
10651 else
10652 ins->used_prefixes |= PREFIX_FWAIT;
10653 break;
10654 case 'O':
10655 USED_REX (REX_W);
10656 if (ins->rex & REX_W)
10657 *ins->obufp++ = 'o';
10658 else if (ins->intel_syntax && (sizeflag & DFLAG))
10659 *ins->obufp++ = 'q';
10660 else
10661 *ins->obufp++ = 'd';
10662 if (!(ins->rex & REX_W))
10663 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10664 break;
10665 case '@':
10666 if (ins->address_mode == mode_64bit
10667 && (ins->isa64 == intel64 || (ins->rex & REX_W)
10668 || !(ins->prefixes & PREFIX_DATA)))
10669 {
10670 if (sizeflag & SUFFIX_ALWAYS)
10671 *ins->obufp++ = 'q';
10672 break;
10673 }
10674 /* Fall through. */
10675 case 'P':
10676 if (l == 0)
10677 {
10678 if ((ins->modrm.mod == 3 || !cond)
10679 && !(sizeflag & SUFFIX_ALWAYS))
10680 break;
10681 /* Fall through. */
10682 case 'T':
10683 if ((!(ins->rex & REX_W) && (ins->prefixes & PREFIX_DATA))
10684 || ((sizeflag & SUFFIX_ALWAYS)
10685 && ins->address_mode != mode_64bit))
10686 {
10687 *ins->obufp++ = (sizeflag & DFLAG)
10688 ? ins->intel_syntax ? 'd' : 'l' : 'w';
10689 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10690 }
10691 else if (sizeflag & SUFFIX_ALWAYS)
10692 *ins->obufp++ = 'q';
10693 }
10694 else if (l == 1 && last[0] == 'L')
10695 {
10696 if ((ins->prefixes & PREFIX_DATA)
10697 || (ins->rex & REX_W)
10698 || (sizeflag & SUFFIX_ALWAYS))
10699 {
10700 USED_REX (REX_W);
10701 if (ins->rex & REX_W)
10702 *ins->obufp++ = 'q';
10703 else
10704 {
10705 if (sizeflag & DFLAG)
10706 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10707 else
10708 *ins->obufp++ = 'w';
10709 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10710 }
10711 }
10712 }
10713 else
10714 abort ();
10715 break;
10716 case 'Q':
10717 if (l == 0)
10718 {
10719 if (ins->intel_syntax && !alt)
10720 break;
10721 USED_REX (REX_W);
10722 if ((ins->need_modrm && ins->modrm.mod != 3)
10723 || (sizeflag & SUFFIX_ALWAYS))
10724 {
10725 if (ins->rex & REX_W)
10726 *ins->obufp++ = 'q';
10727 else
10728 {
10729 if (sizeflag & DFLAG)
10730 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10731 else
10732 *ins->obufp++ = 'w';
10733 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10734 }
10735 }
10736 }
10737 else if (l == 1 && last[0] == 'D')
10738 *ins->obufp++ = ins->vex.w ? 'q' : 'd';
10739 else if (l == 1 && last[0] == 'L')
10740 {
10741 if (cond ? ins->modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10742 : ins->address_mode != mode_64bit)
10743 break;
10744 if ((ins->rex & REX_W))
10745 {
10746 USED_REX (REX_W);
10747 *ins->obufp++ = 'q';
10748 }
10749 else if ((ins->address_mode == mode_64bit && cond)
10750 || (sizeflag & SUFFIX_ALWAYS))
10751 *ins->obufp++ = ins->intel_syntax? 'd' : 'l';
10752 }
10753 else
10754 abort ();
10755 break;
10756 case 'R':
10757 USED_REX (REX_W);
10758 if (ins->rex & REX_W)
10759 *ins->obufp++ = 'q';
10760 else if (sizeflag & DFLAG)
10761 {
10762 if (ins->intel_syntax)
10763 *ins->obufp++ = 'd';
10764 else
10765 *ins->obufp++ = 'l';
10766 }
10767 else
10768 *ins->obufp++ = 'w';
10769 if (ins->intel_syntax && !p[1]
10770 && ((ins->rex & REX_W) || (sizeflag & DFLAG)))
10771 *ins->obufp++ = 'e';
10772 if (!(ins->rex & REX_W))
10773 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10774 break;
10775 case 'S':
10776 if (l == 0)
10777 {
10778 case_S:
10779 if (ins->intel_syntax)
10780 break;
10781 if (sizeflag & SUFFIX_ALWAYS)
10782 {
10783 if (ins->rex & REX_W)
10784 *ins->obufp++ = 'q';
10785 else
10786 {
10787 if (sizeflag & DFLAG)
10788 *ins->obufp++ = 'l';
10789 else
10790 *ins->obufp++ = 'w';
10791 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10792 }
10793 }
10794 break;
10795 }
10796 if (l != 1)
10797 abort ();
10798 switch (last[0])
10799 {
10800 case 'L':
10801 if (ins->address_mode == mode_64bit
10802 && !(ins->prefixes & PREFIX_ADDR))
10803 {
10804 *ins->obufp++ = 'a';
10805 *ins->obufp++ = 'b';
10806 *ins->obufp++ = 's';
10807 }
10808
10809 goto case_S;
10810 case 'X':
10811 if (!ins->vex.evex || !ins->vex.w)
10812 *ins->obufp++ = 's';
10813 else
10814 oappend (ins, "{bad}");
10815 break;
10816 default:
10817 abort ();
10818 }
10819 break;
10820 case 'V':
10821 if (l == 0)
10822 {
10823 if (ins->need_vex)
10824 *ins->obufp++ = 'v';
10825 }
10826 else if (l == 1)
10827 {
10828 switch (last[0])
10829 {
10830 case 'X':
10831 if (ins->vex.evex)
10832 break;
10833 *ins->obufp++ = '{';
10834 *ins->obufp++ = 'v';
10835 *ins->obufp++ = 'e';
10836 *ins->obufp++ = 'x';
10837 *ins->obufp++ = '}';
10838 *ins->obufp++ = ' ';
10839 break;
10840 case 'L':
10841 if (ins->rex & REX_W)
10842 {
10843 *ins->obufp++ = 'a';
10844 *ins->obufp++ = 'b';
10845 *ins->obufp++ = 's';
10846 }
10847 goto case_S;
10848 default:
10849 abort ();
10850 }
10851 }
10852 else
10853 abort ();
10854 break;
10855 case 'W':
10856 if (l == 0)
10857 {
10858 /* operand size flag for cwtl, cbtw */
10859 USED_REX (REX_W);
10860 if (ins->rex & REX_W)
10861 {
10862 if (ins->intel_syntax)
10863 *ins->obufp++ = 'd';
10864 else
10865 *ins->obufp++ = 'l';
10866 }
10867 else if (sizeflag & DFLAG)
10868 *ins->obufp++ = 'w';
10869 else
10870 *ins->obufp++ = 'b';
10871 if (!(ins->rex & REX_W))
10872 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10873 }
10874 else if (l == 1)
10875 {
10876 if (!ins->need_vex)
10877 abort ();
10878 if (last[0] == 'X')
10879 *ins->obufp++ = ins->vex.w ? 'd': 's';
10880 else if (last[0] == 'B')
10881 *ins->obufp++ = ins->vex.w ? 'w': 'b';
10882 else
10883 abort ();
10884 }
10885 else
10886 abort ();
10887 break;
10888 case 'X':
10889 if (l != 0)
10890 abort ();
10891 if (ins->need_vex
10892 ? ins->vex.prefix == DATA_PREFIX_OPCODE
10893 : ins->prefixes & PREFIX_DATA)
10894 {
10895 *ins->obufp++ = 'd';
10896 ins->used_prefixes |= PREFIX_DATA;
10897 }
10898 else
10899 *ins->obufp++ = 's';
10900 break;
10901 case 'Y':
10902 if (l == 0)
10903 {
10904 if (ins->vex.mask_register_specifier)
10905 ins->illegal_masking = true;
10906 }
10907 else if (l == 1 && last[0] == 'X')
10908 {
10909 if (!ins->need_vex)
10910 break;
10911 if (ins->intel_syntax
10912 || ((ins->modrm.mod == 3 || ins->vex.b)
10913 && !(sizeflag & SUFFIX_ALWAYS)))
10914 break;
10915 switch (ins->vex.length)
10916 {
10917 case 128:
10918 *ins->obufp++ = 'x';
10919 break;
10920 case 256:
10921 *ins->obufp++ = 'y';
10922 break;
10923 case 512:
10924 if (!ins->vex.evex)
10925 default:
10926 abort ();
10927 }
10928 }
10929 else
10930 abort ();
10931 break;
10932 case 'Z':
10933 if (l == 0)
10934 {
10935 /* These insns ignore ModR/M.mod: Force it to 3 for OP_E(). */
10936 ins->modrm.mod = 3;
10937 if (!ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
10938 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
10939 }
10940 else if (l == 1 && last[0] == 'X')
10941 {
10942 if (!ins->vex.evex)
10943 abort ();
10944 if (ins->intel_syntax
10945 || ((ins->modrm.mod == 3 || ins->vex.b)
10946 && !(sizeflag & SUFFIX_ALWAYS)))
10947 break;
10948 switch (ins->vex.length)
10949 {
10950 case 128:
10951 *ins->obufp++ = 'x';
10952 break;
10953 case 256:
10954 *ins->obufp++ = 'y';
10955 break;
10956 case 512:
10957 *ins->obufp++ = 'z';
10958 break;
10959 default:
10960 abort ();
10961 }
10962 }
10963 else
10964 abort ();
10965 break;
10966 case '^':
10967 if (ins->intel_syntax)
10968 break;
10969 if (ins->isa64 == intel64 && (ins->rex & REX_W))
10970 {
10971 USED_REX (REX_W);
10972 *ins->obufp++ = 'q';
10973 break;
10974 }
10975 if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10976 {
10977 if (sizeflag & DFLAG)
10978 *ins->obufp++ = 'l';
10979 else
10980 *ins->obufp++ = 'w';
10981 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10982 }
10983 break;
10984 }
10985
10986 if (len == l)
10987 len = l = 0;
10988 }
10989 *ins->obufp = 0;
10990 ins->mnemonicendp = ins->obufp;
10991 return 0;
10992 }
10993
10994 /* Add a style marker to *INS->obufp that encodes STYLE. This assumes that
10995 the buffer pointed to by INS->obufp has space. A style marker is made
10996 from the STYLE_MARKER_CHAR followed by STYLE converted to a single hex
10997 digit, followed by another STYLE_MARKER_CHAR. This function assumes
10998 that the number of styles is not greater than 16. */
10999
11000 static void
11001 oappend_insert_style (instr_info *ins, enum disassembler_style style)
11002 {
11003 unsigned num = (unsigned) style;
11004
11005 /* We currently assume that STYLE can be encoded as a single hex
11006 character. If more styles are added then this might start to fail,
11007 and we'll need to expand this code. */
11008 if (num > 0xf)
11009 abort ();
11010
11011 *ins->obufp++ = STYLE_MARKER_CHAR;
11012 *ins->obufp++ = (num < 10 ? ('0' + num)
11013 : ((num < 16) ? ('a' + (num - 10)) : '0'));
11014 *ins->obufp++ = STYLE_MARKER_CHAR;
11015
11016 /* This final null character is not strictly necessary, after inserting a
11017 style marker we should always be inserting some additional content.
11018 However, having the buffer null terminated doesn't cost much, and make
11019 it easier to debug what's going on. Also, if we do ever forget to add
11020 any additional content after this style marker, then the buffer will
11021 still be well formed. */
11022 *ins->obufp = '\0';
11023 }
11024
11025 static void
11026 oappend_with_style (instr_info *ins, const char *s,
11027 enum disassembler_style style)
11028 {
11029 oappend_insert_style (ins, style);
11030 ins->obufp = stpcpy (ins->obufp, s);
11031 }
11032
11033 /* Add a single character C to the buffer pointer to by INS->obufp, marking
11034 the style for the character as STYLE. */
11035
11036 static void
11037 oappend_char_with_style (instr_info *ins, const char c,
11038 enum disassembler_style style)
11039 {
11040 oappend_insert_style (ins, style);
11041 *ins->obufp++ = c;
11042 *ins->obufp = '\0';
11043 }
11044
11045 /* Like oappend_char_with_style, but always uses dis_style_text. */
11046
11047 static void
11048 oappend_char (instr_info *ins, const char c)
11049 {
11050 oappend_char_with_style (ins, c, dis_style_text);
11051 }
11052
11053 static void
11054 append_seg (instr_info *ins)
11055 {
11056 /* Only print the active segment register. */
11057 if (!ins->active_seg_prefix)
11058 return;
11059
11060 ins->used_prefixes |= ins->active_seg_prefix;
11061 switch (ins->active_seg_prefix)
11062 {
11063 case PREFIX_CS:
11064 oappend_register (ins, att_names_seg[1]);
11065 break;
11066 case PREFIX_DS:
11067 oappend_register (ins, att_names_seg[3]);
11068 break;
11069 case PREFIX_SS:
11070 oappend_register (ins, att_names_seg[2]);
11071 break;
11072 case PREFIX_ES:
11073 oappend_register (ins, att_names_seg[0]);
11074 break;
11075 case PREFIX_FS:
11076 oappend_register (ins, att_names_seg[4]);
11077 break;
11078 case PREFIX_GS:
11079 oappend_register (ins, att_names_seg[5]);
11080 break;
11081 default:
11082 break;
11083 }
11084 oappend_char (ins, ':');
11085 }
11086
11087 static bool
11088 OP_indirE (instr_info *ins, int bytemode, int sizeflag)
11089 {
11090 if (!ins->intel_syntax)
11091 oappend (ins, "*");
11092 return OP_E (ins, bytemode, sizeflag);
11093 }
11094
11095 static void
11096 print_operand_value (instr_info *ins, bfd_vma disp,
11097 enum disassembler_style style)
11098 {
11099 char tmp[30];
11100
11101 if (ins->address_mode != mode_64bit)
11102 disp &= 0xffffffff;
11103 sprintf (tmp, "0x%" PRIx64, (uint64_t) disp);
11104 oappend_with_style (ins, tmp, style);
11105 }
11106
11107 /* Like oappend, but called for immediate operands. */
11108
11109 static void
11110 oappend_immediate (instr_info *ins, bfd_vma imm)
11111 {
11112 if (!ins->intel_syntax)
11113 oappend_char_with_style (ins, '$', dis_style_immediate);
11114 print_operand_value (ins, imm, dis_style_immediate);
11115 }
11116
11117 /* Put DISP in BUF as signed hex number. */
11118
11119 static void
11120 print_displacement (instr_info *ins, bfd_signed_vma val)
11121 {
11122 char tmp[30];
11123
11124 if (val < 0)
11125 {
11126 oappend_char_with_style (ins, '-', dis_style_address_offset);
11127 val = (bfd_vma) 0 - val;
11128
11129 /* Check for possible overflow. */
11130 if (val < 0)
11131 {
11132 switch (ins->address_mode)
11133 {
11134 case mode_64bit:
11135 oappend_with_style (ins, "0x8000000000000000",
11136 dis_style_address_offset);
11137 break;
11138 case mode_32bit:
11139 oappend_with_style (ins, "0x80000000",
11140 dis_style_address_offset);
11141 break;
11142 case mode_16bit:
11143 oappend_with_style (ins, "0x8000",
11144 dis_style_address_offset);
11145 break;
11146 }
11147 return;
11148 }
11149 }
11150
11151 sprintf (tmp, "0x%" PRIx64, (int64_t) val);
11152 oappend_with_style (ins, tmp, dis_style_address_offset);
11153 }
11154
11155 static void
11156 intel_operand_size (instr_info *ins, int bytemode, int sizeflag)
11157 {
11158 if (ins->vex.b)
11159 {
11160 if (!ins->vex.no_broadcast)
11161 switch (bytemode)
11162 {
11163 case x_mode:
11164 case evex_half_bcst_xmmq_mode:
11165 if (ins->vex.w)
11166 oappend (ins, "QWORD BCST ");
11167 else
11168 oappend (ins, "DWORD BCST ");
11169 break;
11170 case xh_mode:
11171 case evex_half_bcst_xmmqh_mode:
11172 case evex_half_bcst_xmmqdh_mode:
11173 oappend (ins, "WORD BCST ");
11174 break;
11175 default:
11176 ins->vex.no_broadcast = true;
11177 break;
11178 }
11179 return;
11180 }
11181 switch (bytemode)
11182 {
11183 case b_mode:
11184 case b_swap_mode:
11185 case db_mode:
11186 oappend (ins, "BYTE PTR ");
11187 break;
11188 case w_mode:
11189 case w_swap_mode:
11190 case dw_mode:
11191 oappend (ins, "WORD PTR ");
11192 break;
11193 case indir_v_mode:
11194 if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11195 {
11196 oappend (ins, "QWORD PTR ");
11197 break;
11198 }
11199 /* Fall through. */
11200 case stack_v_mode:
11201 if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11202 || (ins->rex & REX_W)))
11203 {
11204 oappend (ins, "QWORD PTR ");
11205 break;
11206 }
11207 /* Fall through. */
11208 case v_mode:
11209 case v_swap_mode:
11210 case dq_mode:
11211 USED_REX (REX_W);
11212 if (ins->rex & REX_W)
11213 oappend (ins, "QWORD PTR ");
11214 else if (bytemode == dq_mode)
11215 oappend (ins, "DWORD PTR ");
11216 else
11217 {
11218 if (sizeflag & DFLAG)
11219 oappend (ins, "DWORD PTR ");
11220 else
11221 oappend (ins, "WORD PTR ");
11222 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11223 }
11224 break;
11225 case z_mode:
11226 if ((ins->rex & REX_W) || (sizeflag & DFLAG))
11227 *ins->obufp++ = 'D';
11228 oappend (ins, "WORD PTR ");
11229 if (!(ins->rex & REX_W))
11230 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11231 break;
11232 case a_mode:
11233 if (sizeflag & DFLAG)
11234 oappend (ins, "QWORD PTR ");
11235 else
11236 oappend (ins, "DWORD PTR ");
11237 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11238 break;
11239 case movsxd_mode:
11240 if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11241 oappend (ins, "WORD PTR ");
11242 else
11243 oappend (ins, "DWORD PTR ");
11244 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11245 break;
11246 case d_mode:
11247 case d_swap_mode:
11248 oappend (ins, "DWORD PTR ");
11249 break;
11250 case q_mode:
11251 case q_swap_mode:
11252 oappend (ins, "QWORD PTR ");
11253 break;
11254 case m_mode:
11255 if (ins->address_mode == mode_64bit)
11256 oappend (ins, "QWORD PTR ");
11257 else
11258 oappend (ins, "DWORD PTR ");
11259 break;
11260 case f_mode:
11261 if (sizeflag & DFLAG)
11262 oappend (ins, "FWORD PTR ");
11263 else
11264 oappend (ins, "DWORD PTR ");
11265 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11266 break;
11267 case t_mode:
11268 oappend (ins, "TBYTE PTR ");
11269 break;
11270 case x_mode:
11271 case xh_mode:
11272 case x_swap_mode:
11273 case evex_x_gscat_mode:
11274 case evex_x_nobcst_mode:
11275 case bw_unit_mode:
11276 if (ins->need_vex)
11277 {
11278 switch (ins->vex.length)
11279 {
11280 case 128:
11281 oappend (ins, "XMMWORD PTR ");
11282 break;
11283 case 256:
11284 oappend (ins, "YMMWORD PTR ");
11285 break;
11286 case 512:
11287 oappend (ins, "ZMMWORD PTR ");
11288 break;
11289 default:
11290 abort ();
11291 }
11292 }
11293 else
11294 oappend (ins, "XMMWORD PTR ");
11295 break;
11296 case xmm_mode:
11297 oappend (ins, "XMMWORD PTR ");
11298 break;
11299 case ymm_mode:
11300 oappend (ins, "YMMWORD PTR ");
11301 break;
11302 case xmmq_mode:
11303 case evex_half_bcst_xmmqh_mode:
11304 case evex_half_bcst_xmmq_mode:
11305 switch (ins->vex.length)
11306 {
11307 case 0:
11308 case 128:
11309 oappend (ins, "QWORD PTR ");
11310 break;
11311 case 256:
11312 oappend (ins, "XMMWORD PTR ");
11313 break;
11314 case 512:
11315 oappend (ins, "YMMWORD PTR ");
11316 break;
11317 default:
11318 abort ();
11319 }
11320 break;
11321 case xmmdw_mode:
11322 if (!ins->need_vex)
11323 abort ();
11324
11325 switch (ins->vex.length)
11326 {
11327 case 128:
11328 oappend (ins, "WORD PTR ");
11329 break;
11330 case 256:
11331 oappend (ins, "DWORD PTR ");
11332 break;
11333 case 512:
11334 oappend (ins, "QWORD PTR ");
11335 break;
11336 default:
11337 abort ();
11338 }
11339 break;
11340 case xmmqd_mode:
11341 case evex_half_bcst_xmmqdh_mode:
11342 if (!ins->need_vex)
11343 abort ();
11344
11345 switch (ins->vex.length)
11346 {
11347 case 128:
11348 oappend (ins, "DWORD PTR ");
11349 break;
11350 case 256:
11351 oappend (ins, "QWORD PTR ");
11352 break;
11353 case 512:
11354 oappend (ins, "XMMWORD PTR ");
11355 break;
11356 default:
11357 abort ();
11358 }
11359 break;
11360 case ymmq_mode:
11361 if (!ins->need_vex)
11362 abort ();
11363
11364 switch (ins->vex.length)
11365 {
11366 case 128:
11367 oappend (ins, "QWORD PTR ");
11368 break;
11369 case 256:
11370 oappend (ins, "YMMWORD PTR ");
11371 break;
11372 case 512:
11373 oappend (ins, "ZMMWORD PTR ");
11374 break;
11375 default:
11376 abort ();
11377 }
11378 break;
11379 case o_mode:
11380 oappend (ins, "OWORD PTR ");
11381 break;
11382 case vex_vsib_d_w_dq_mode:
11383 case vex_vsib_q_w_dq_mode:
11384 if (!ins->need_vex)
11385 abort ();
11386 if (ins->vex.w)
11387 oappend (ins, "QWORD PTR ");
11388 else
11389 oappend (ins, "DWORD PTR ");
11390 break;
11391 case mask_bd_mode:
11392 if (!ins->need_vex || ins->vex.length != 128)
11393 abort ();
11394 if (ins->vex.w)
11395 oappend (ins, "DWORD PTR ");
11396 else
11397 oappend (ins, "BYTE PTR ");
11398 break;
11399 case mask_mode:
11400 if (!ins->need_vex)
11401 abort ();
11402 if (ins->vex.w)
11403 oappend (ins, "QWORD PTR ");
11404 else
11405 oappend (ins, "WORD PTR ");
11406 break;
11407 case v_bnd_mode:
11408 case v_bndmk_mode:
11409 default:
11410 break;
11411 }
11412 }
11413
11414 static void
11415 print_register (instr_info *ins, unsigned int reg, unsigned int rexmask,
11416 int bytemode, int sizeflag)
11417 {
11418 const char (*names)[8];
11419
11420 /* Masking is invalid for insns with GPR destination. Set the flag uniformly,
11421 as the consumer will inspect it only for the destination operand. */
11422 if (bytemode != mask_mode && ins->vex.mask_register_specifier)
11423 ins->illegal_masking = true;
11424
11425 USED_REX (rexmask);
11426 if (ins->rex & rexmask)
11427 reg += 8;
11428
11429 switch (bytemode)
11430 {
11431 case b_mode:
11432 case b_swap_mode:
11433 if (reg & 4)
11434 USED_REX (0);
11435 if (ins->rex)
11436 names = att_names8rex;
11437 else
11438 names = att_names8;
11439 break;
11440 case w_mode:
11441 names = att_names16;
11442 break;
11443 case d_mode:
11444 case dw_mode:
11445 case db_mode:
11446 names = att_names32;
11447 break;
11448 case q_mode:
11449 names = att_names64;
11450 break;
11451 case m_mode:
11452 case v_bnd_mode:
11453 names = ins->address_mode == mode_64bit ? att_names64 : att_names32;
11454 break;
11455 case bnd_mode:
11456 case bnd_swap_mode:
11457 if (reg > 0x3)
11458 {
11459 oappend (ins, "(bad)");
11460 return;
11461 }
11462 names = att_names_bnd;
11463 break;
11464 case indir_v_mode:
11465 if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11466 {
11467 names = att_names64;
11468 break;
11469 }
11470 /* Fall through. */
11471 case stack_v_mode:
11472 if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11473 || (ins->rex & REX_W)))
11474 {
11475 names = att_names64;
11476 break;
11477 }
11478 bytemode = v_mode;
11479 /* Fall through. */
11480 case v_mode:
11481 case v_swap_mode:
11482 case dq_mode:
11483 USED_REX (REX_W);
11484 if (ins->rex & REX_W)
11485 names = att_names64;
11486 else if (bytemode != v_mode && bytemode != v_swap_mode)
11487 names = att_names32;
11488 else
11489 {
11490 if (sizeflag & DFLAG)
11491 names = att_names32;
11492 else
11493 names = att_names16;
11494 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11495 }
11496 break;
11497 case movsxd_mode:
11498 if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11499 names = att_names16;
11500 else
11501 names = att_names32;
11502 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11503 break;
11504 case va_mode:
11505 names = (ins->address_mode == mode_64bit
11506 ? att_names64 : att_names32);
11507 if (!(ins->prefixes & PREFIX_ADDR))
11508 names = (ins->address_mode == mode_16bit
11509 ? att_names16 : names);
11510 else
11511 {
11512 /* Remove "addr16/addr32". */
11513 ins->all_prefixes[ins->last_addr_prefix] = 0;
11514 names = (ins->address_mode != mode_32bit
11515 ? att_names32 : att_names16);
11516 ins->used_prefixes |= PREFIX_ADDR;
11517 }
11518 break;
11519 case mask_bd_mode:
11520 case mask_mode:
11521 if (reg > 0x7)
11522 {
11523 oappend (ins, "(bad)");
11524 return;
11525 }
11526 names = att_names_mask;
11527 break;
11528 case 0:
11529 return;
11530 default:
11531 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
11532 return;
11533 }
11534 oappend_register (ins, names[reg]);
11535 }
11536
11537 static bool
11538 get8s (instr_info *ins, bfd_vma *res)
11539 {
11540 if (!fetch_code (ins->info, ins->codep + 1))
11541 return false;
11542 *res = ((bfd_vma) *ins->codep++ ^ 0x80) - 0x80;
11543 return true;
11544 }
11545
11546 static bool
11547 get16 (instr_info *ins, bfd_vma *res)
11548 {
11549 if (!fetch_code (ins->info, ins->codep + 2))
11550 return false;
11551 *res = *ins->codep++;
11552 *res |= (bfd_vma) *ins->codep++ << 8;
11553 return true;
11554 }
11555
11556 static bool
11557 get16s (instr_info *ins, bfd_vma *res)
11558 {
11559 if (!get16 (ins, res))
11560 return false;
11561 *res = (*res ^ 0x8000) - 0x8000;
11562 return true;
11563 }
11564
11565 static bool
11566 get32 (instr_info *ins, bfd_vma *res)
11567 {
11568 if (!fetch_code (ins->info, ins->codep + 4))
11569 return false;
11570 *res = *ins->codep++;
11571 *res |= (bfd_vma) *ins->codep++ << 8;
11572 *res |= (bfd_vma) *ins->codep++ << 16;
11573 *res |= (bfd_vma) *ins->codep++ << 24;
11574 return true;
11575 }
11576
11577 static bool
11578 get32s (instr_info *ins, bfd_vma *res)
11579 {
11580 if (!get32 (ins, res))
11581 return false;
11582
11583 *res = (*res ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
11584
11585 return true;
11586 }
11587
11588 static bool
11589 get64 (instr_info *ins, uint64_t *res)
11590 {
11591 unsigned int a;
11592 unsigned int b;
11593
11594 if (!fetch_code (ins->info, ins->codep + 8))
11595 return false;
11596 a = *ins->codep++;
11597 a |= (unsigned int) *ins->codep++ << 8;
11598 a |= (unsigned int) *ins->codep++ << 16;
11599 a |= (unsigned int) *ins->codep++ << 24;
11600 b = *ins->codep++;
11601 b |= (unsigned int) *ins->codep++ << 8;
11602 b |= (unsigned int) *ins->codep++ << 16;
11603 b |= (unsigned int) *ins->codep++ << 24;
11604 *res = a + ((uint64_t) b << 32);
11605 return true;
11606 }
11607
11608 static void
11609 set_op (instr_info *ins, bfd_vma op, bool riprel)
11610 {
11611 ins->op_index[ins->op_ad] = ins->op_ad;
11612 if (ins->address_mode == mode_64bit)
11613 ins->op_address[ins->op_ad] = op;
11614 else /* Mask to get a 32-bit address. */
11615 ins->op_address[ins->op_ad] = op & 0xffffffff;
11616 ins->op_riprel[ins->op_ad] = riprel;
11617 }
11618
11619 static bool
11620 BadOp (instr_info *ins)
11621 {
11622 /* Throw away prefixes and 1st. opcode byte. */
11623 struct dis_private *priv = ins->info->private_data;
11624
11625 ins->codep = priv->the_buffer + ins->nr_prefixes + 1;
11626 ins->obufp = stpcpy (ins->obufp, "(bad)");
11627 return true;
11628 }
11629
11630 static bool
11631 OP_E_memory (instr_info *ins, int bytemode, int sizeflag)
11632 {
11633 int add = (ins->rex & REX_B) ? 8 : 0;
11634 int riprel = 0;
11635 int shift;
11636
11637 if (ins->vex.evex)
11638 {
11639
11640 /* Zeroing-masking is invalid for memory destinations. Set the flag
11641 uniformly, as the consumer will inspect it only for the destination
11642 operand. */
11643 if (ins->vex.zeroing)
11644 ins->illegal_masking = true;
11645
11646 switch (bytemode)
11647 {
11648 case dw_mode:
11649 case w_mode:
11650 case w_swap_mode:
11651 shift = 1;
11652 break;
11653 case db_mode:
11654 case b_mode:
11655 shift = 0;
11656 break;
11657 case dq_mode:
11658 if (ins->address_mode != mode_64bit)
11659 {
11660 case d_mode:
11661 case d_swap_mode:
11662 shift = 2;
11663 break;
11664 }
11665 /* fall through */
11666 case vex_vsib_d_w_dq_mode:
11667 case vex_vsib_q_w_dq_mode:
11668 case evex_x_gscat_mode:
11669 shift = ins->vex.w ? 3 : 2;
11670 break;
11671 case xh_mode:
11672 case evex_half_bcst_xmmqh_mode:
11673 case evex_half_bcst_xmmqdh_mode:
11674 if (ins->vex.b)
11675 {
11676 shift = ins->vex.w ? 2 : 1;
11677 break;
11678 }
11679 /* Fall through. */
11680 case x_mode:
11681 case evex_half_bcst_xmmq_mode:
11682 if (ins->vex.b)
11683 {
11684 shift = ins->vex.w ? 3 : 2;
11685 break;
11686 }
11687 /* Fall through. */
11688 case xmmqd_mode:
11689 case xmmdw_mode:
11690 case xmmq_mode:
11691 case ymmq_mode:
11692 case evex_x_nobcst_mode:
11693 case x_swap_mode:
11694 switch (ins->vex.length)
11695 {
11696 case 128:
11697 shift = 4;
11698 break;
11699 case 256:
11700 shift = 5;
11701 break;
11702 case 512:
11703 shift = 6;
11704 break;
11705 default:
11706 abort ();
11707 }
11708 /* Make necessary corrections to shift for modes that need it. */
11709 if (bytemode == xmmq_mode
11710 || bytemode == evex_half_bcst_xmmqh_mode
11711 || bytemode == evex_half_bcst_xmmq_mode
11712 || (bytemode == ymmq_mode && ins->vex.length == 128))
11713 shift -= 1;
11714 else if (bytemode == xmmqd_mode
11715 || bytemode == evex_half_bcst_xmmqdh_mode)
11716 shift -= 2;
11717 else if (bytemode == xmmdw_mode)
11718 shift -= 3;
11719 break;
11720 case ymm_mode:
11721 shift = 5;
11722 break;
11723 case xmm_mode:
11724 shift = 4;
11725 break;
11726 case q_mode:
11727 case q_swap_mode:
11728 shift = 3;
11729 break;
11730 case bw_unit_mode:
11731 shift = ins->vex.w ? 1 : 0;
11732 break;
11733 default:
11734 abort ();
11735 }
11736 }
11737 else
11738 shift = 0;
11739
11740 USED_REX (REX_B);
11741 if (ins->intel_syntax)
11742 intel_operand_size (ins, bytemode, sizeflag);
11743 append_seg (ins);
11744
11745 if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
11746 {
11747 /* 32/64 bit address mode */
11748 bfd_vma disp = 0;
11749 int havedisp;
11750 int havebase;
11751 int needindex;
11752 int needaddr32;
11753 int base, rbase;
11754 int vindex = 0;
11755 int scale = 0;
11756 int addr32flag = !((sizeflag & AFLAG)
11757 || bytemode == v_bnd_mode
11758 || bytemode == v_bndmk_mode
11759 || bytemode == bnd_mode
11760 || bytemode == bnd_swap_mode);
11761 bool check_gather = false;
11762 const char (*indexes)[8] = NULL;
11763
11764 havebase = 1;
11765 base = ins->modrm.rm;
11766
11767 if (base == 4)
11768 {
11769 vindex = ins->sib.index;
11770 USED_REX (REX_X);
11771 if (ins->rex & REX_X)
11772 vindex += 8;
11773 switch (bytemode)
11774 {
11775 case vex_vsib_d_w_dq_mode:
11776 case vex_vsib_q_w_dq_mode:
11777 if (!ins->need_vex)
11778 abort ();
11779 if (ins->vex.evex)
11780 {
11781 if (!ins->vex.v)
11782 vindex += 16;
11783 check_gather = ins->obufp == ins->op_out[1];
11784 }
11785
11786 switch (ins->vex.length)
11787 {
11788 case 128:
11789 indexes = att_names_xmm;
11790 break;
11791 case 256:
11792 if (!ins->vex.w
11793 || bytemode == vex_vsib_q_w_dq_mode)
11794 indexes = att_names_ymm;
11795 else
11796 indexes = att_names_xmm;
11797 break;
11798 case 512:
11799 if (!ins->vex.w
11800 || bytemode == vex_vsib_q_w_dq_mode)
11801 indexes = att_names_zmm;
11802 else
11803 indexes = att_names_ymm;
11804 break;
11805 default:
11806 abort ();
11807 }
11808 break;
11809 default:
11810 if (vindex != 4)
11811 indexes = ins->address_mode == mode_64bit && !addr32flag
11812 ? att_names64 : att_names32;
11813 break;
11814 }
11815 scale = ins->sib.scale;
11816 base = ins->sib.base;
11817 ins->codep++;
11818 }
11819 else
11820 {
11821 /* Check for mandatory SIB. */
11822 if (bytemode == vex_vsib_d_w_dq_mode
11823 || bytemode == vex_vsib_q_w_dq_mode
11824 || bytemode == vex_sibmem_mode)
11825 {
11826 oappend (ins, "(bad)");
11827 return true;
11828 }
11829 }
11830 rbase = base + add;
11831
11832 switch (ins->modrm.mod)
11833 {
11834 case 0:
11835 if (base == 5)
11836 {
11837 havebase = 0;
11838 if (ins->address_mode == mode_64bit && !ins->has_sib)
11839 riprel = 1;
11840 if (!get32s (ins, &disp))
11841 return false;
11842 if (riprel && bytemode == v_bndmk_mode)
11843 {
11844 oappend (ins, "(bad)");
11845 return true;
11846 }
11847 }
11848 break;
11849 case 1:
11850 if (!get8s (ins, &disp))
11851 return false;
11852 if (ins->vex.evex && shift > 0)
11853 disp <<= shift;
11854 break;
11855 case 2:
11856 if (!get32s (ins, &disp))
11857 return false;
11858 break;
11859 }
11860
11861 needindex = 0;
11862 needaddr32 = 0;
11863 if (ins->has_sib
11864 && !havebase
11865 && !indexes
11866 && ins->address_mode != mode_16bit)
11867 {
11868 if (ins->address_mode == mode_64bit)
11869 {
11870 if (addr32flag)
11871 {
11872 /* Without base nor index registers, zero-extend the
11873 lower 32-bit displacement to 64 bits. */
11874 disp &= 0xffffffff;
11875 needindex = 1;
11876 }
11877 needaddr32 = 1;
11878 }
11879 else
11880 {
11881 /* In 32-bit mode, we need index register to tell [offset]
11882 from [eiz*1 + offset]. */
11883 needindex = 1;
11884 }
11885 }
11886
11887 havedisp = (havebase
11888 || needindex
11889 || (ins->has_sib && (indexes || scale != 0)));
11890
11891 if (!ins->intel_syntax)
11892 if (ins->modrm.mod != 0 || base == 5)
11893 {
11894 if (havedisp || riprel)
11895 print_displacement (ins, disp);
11896 else
11897 print_operand_value (ins, disp, dis_style_address_offset);
11898 if (riprel)
11899 {
11900 set_op (ins, disp, true);
11901 oappend_char (ins, '(');
11902 oappend_with_style (ins, !addr32flag ? "%rip" : "%eip",
11903 dis_style_register);
11904 oappend_char (ins, ')');
11905 }
11906 }
11907
11908 if ((havebase || indexes || needindex || needaddr32 || riprel)
11909 && (ins->address_mode != mode_64bit
11910 || ((bytemode != v_bnd_mode)
11911 && (bytemode != v_bndmk_mode)
11912 && (bytemode != bnd_mode)
11913 && (bytemode != bnd_swap_mode))))
11914 ins->used_prefixes |= PREFIX_ADDR;
11915
11916 if (havedisp || (ins->intel_syntax && riprel))
11917 {
11918 oappend_char (ins, ins->open_char);
11919 if (ins->intel_syntax && riprel)
11920 {
11921 set_op (ins, disp, true);
11922 oappend_with_style (ins, !addr32flag ? "rip" : "eip",
11923 dis_style_register);
11924 }
11925 if (havebase)
11926 oappend_register
11927 (ins,
11928 (ins->address_mode == mode_64bit && !addr32flag
11929 ? att_names64 : att_names32)[rbase]);
11930 if (ins->has_sib)
11931 {
11932 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
11933 print index to tell base + index from base. */
11934 if (scale != 0
11935 || needindex
11936 || indexes
11937 || (havebase && base != ESP_REG_NUM))
11938 {
11939 if (!ins->intel_syntax || havebase)
11940 oappend_char (ins, ins->separator_char);
11941 if (indexes)
11942 {
11943 if (ins->address_mode == mode_64bit || vindex < 16)
11944 oappend_register (ins, indexes[vindex]);
11945 else
11946 oappend (ins, "(bad)");
11947 }
11948 else
11949 oappend_register (ins,
11950 ins->address_mode == mode_64bit
11951 && !addr32flag
11952 ? att_index64
11953 : att_index32);
11954
11955 oappend_char (ins, ins->scale_char);
11956 oappend_char_with_style (ins, '0' + (1 << scale),
11957 dis_style_immediate);
11958 }
11959 }
11960 if (ins->intel_syntax
11961 && (disp || ins->modrm.mod != 0 || base == 5))
11962 {
11963 if (!havedisp || (bfd_signed_vma) disp >= 0)
11964 oappend_char (ins, '+');
11965 if (havedisp)
11966 print_displacement (ins, disp);
11967 else
11968 print_operand_value (ins, disp, dis_style_address_offset);
11969 }
11970
11971 oappend_char (ins, ins->close_char);
11972
11973 if (check_gather)
11974 {
11975 /* Both XMM/YMM/ZMM registers must be distinct. */
11976 int modrm_reg = ins->modrm.reg;
11977
11978 if (ins->rex & REX_R)
11979 modrm_reg += 8;
11980 if (!ins->vex.r)
11981 modrm_reg += 16;
11982 if (vindex == modrm_reg)
11983 oappend (ins, "/(bad)");
11984 }
11985 }
11986 else if (ins->intel_syntax)
11987 {
11988 if (ins->modrm.mod != 0 || base == 5)
11989 {
11990 if (!ins->active_seg_prefix)
11991 {
11992 oappend_register (ins, att_names_seg[ds_reg - es_reg]);
11993 oappend (ins, ":");
11994 }
11995 print_operand_value (ins, disp, dis_style_text);
11996 }
11997 }
11998 }
11999 else if (bytemode == v_bnd_mode
12000 || bytemode == v_bndmk_mode
12001 || bytemode == bnd_mode
12002 || bytemode == bnd_swap_mode
12003 || bytemode == vex_vsib_d_w_dq_mode
12004 || bytemode == vex_vsib_q_w_dq_mode)
12005 {
12006 oappend (ins, "(bad)");
12007 return true;
12008 }
12009 else
12010 {
12011 /* 16 bit address mode */
12012 bfd_vma disp = 0;
12013
12014 ins->used_prefixes |= ins->prefixes & PREFIX_ADDR;
12015 switch (ins->modrm.mod)
12016 {
12017 case 0:
12018 if (ins->modrm.rm == 6)
12019 {
12020 case 2:
12021 if (!get16s (ins, &disp))
12022 return false;
12023 }
12024 break;
12025 case 1:
12026 if (!get8s (ins, &disp))
12027 return false;
12028 if (ins->vex.evex && shift > 0)
12029 disp <<= shift;
12030 break;
12031 }
12032
12033 if (!ins->intel_syntax)
12034 if (ins->modrm.mod != 0 || ins->modrm.rm == 6)
12035 print_displacement (ins, disp);
12036
12037 if (ins->modrm.mod != 0 || ins->modrm.rm != 6)
12038 {
12039 oappend_char (ins, ins->open_char);
12040 oappend (ins, ins->intel_syntax ? intel_index16[ins->modrm.rm]
12041 : att_index16[ins->modrm.rm]);
12042 if (ins->intel_syntax
12043 && (disp || ins->modrm.mod != 0 || ins->modrm.rm == 6))
12044 {
12045 if ((bfd_signed_vma) disp >= 0)
12046 oappend_char (ins, '+');
12047 print_displacement (ins, disp);
12048 }
12049
12050 oappend_char (ins, ins->close_char);
12051 }
12052 else if (ins->intel_syntax)
12053 {
12054 if (!ins->active_seg_prefix)
12055 {
12056 oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12057 oappend (ins, ":");
12058 }
12059 print_operand_value (ins, disp & 0xffff, dis_style_text);
12060 }
12061 }
12062 if (ins->vex.b)
12063 {
12064 ins->evex_used |= EVEX_b_used;
12065
12066 /* Broadcast can only ever be valid for memory sources. */
12067 if (ins->obufp == ins->op_out[0])
12068 ins->vex.no_broadcast = true;
12069
12070 if (!ins->vex.no_broadcast
12071 && (!ins->intel_syntax || !(ins->evex_used & EVEX_len_used)))
12072 {
12073 if (bytemode == xh_mode)
12074 {
12075 switch (ins->vex.length)
12076 {
12077 case 128:
12078 oappend (ins, "{1to8}");
12079 break;
12080 case 256:
12081 oappend (ins, "{1to16}");
12082 break;
12083 case 512:
12084 oappend (ins, "{1to32}");
12085 break;
12086 default:
12087 abort ();
12088 }
12089 }
12090 else if (bytemode == q_mode
12091 || bytemode == ymmq_mode)
12092 ins->vex.no_broadcast = true;
12093 else if (ins->vex.w
12094 || bytemode == evex_half_bcst_xmmqdh_mode
12095 || bytemode == evex_half_bcst_xmmq_mode)
12096 {
12097 switch (ins->vex.length)
12098 {
12099 case 128:
12100 oappend (ins, "{1to2}");
12101 break;
12102 case 256:
12103 oappend (ins, "{1to4}");
12104 break;
12105 case 512:
12106 oappend (ins, "{1to8}");
12107 break;
12108 default:
12109 abort ();
12110 }
12111 }
12112 else if (bytemode == x_mode
12113 || bytemode == evex_half_bcst_xmmqh_mode)
12114 {
12115 switch (ins->vex.length)
12116 {
12117 case 128:
12118 oappend (ins, "{1to4}");
12119 break;
12120 case 256:
12121 oappend (ins, "{1to8}");
12122 break;
12123 case 512:
12124 oappend (ins, "{1to16}");
12125 break;
12126 default:
12127 abort ();
12128 }
12129 }
12130 else
12131 ins->vex.no_broadcast = true;
12132 }
12133 if (ins->vex.no_broadcast)
12134 oappend (ins, "{bad}");
12135 }
12136
12137 return true;
12138 }
12139
12140 static bool
12141 OP_E (instr_info *ins, int bytemode, int sizeflag)
12142 {
12143 /* Skip mod/rm byte. */
12144 MODRM_CHECK;
12145 ins->codep++;
12146
12147 if (ins->modrm.mod == 3)
12148 {
12149 if ((sizeflag & SUFFIX_ALWAYS)
12150 && (bytemode == b_swap_mode
12151 || bytemode == bnd_swap_mode
12152 || bytemode == v_swap_mode))
12153 swap_operand (ins);
12154
12155 print_register (ins, ins->modrm.rm, REX_B, bytemode, sizeflag);
12156 return true;
12157 }
12158
12159 /* Masking is invalid for insns with GPR-like memory destination. Set the
12160 flag uniformly, as the consumer will inspect it only for the destination
12161 operand. */
12162 if (ins->vex.mask_register_specifier)
12163 ins->illegal_masking = true;
12164
12165 return OP_E_memory (ins, bytemode, sizeflag);
12166 }
12167
12168 static bool
12169 OP_G (instr_info *ins, int bytemode, int sizeflag)
12170 {
12171 if (ins->vex.evex && !ins->vex.r && ins->address_mode == mode_64bit)
12172 oappend (ins, "(bad)");
12173 else
12174 print_register (ins, ins->modrm.reg, REX_R, bytemode, sizeflag);
12175 return true;
12176 }
12177
12178 static bool
12179 OP_REG (instr_info *ins, int code, int sizeflag)
12180 {
12181 const char *s;
12182 int add;
12183
12184 switch (code)
12185 {
12186 case es_reg: case ss_reg: case cs_reg:
12187 case ds_reg: case fs_reg: case gs_reg:
12188 oappend_register (ins, att_names_seg[code - es_reg]);
12189 return true;
12190 }
12191
12192 USED_REX (REX_B);
12193 if (ins->rex & REX_B)
12194 add = 8;
12195 else
12196 add = 0;
12197
12198 switch (code)
12199 {
12200 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12201 case sp_reg: case bp_reg: case si_reg: case di_reg:
12202 s = att_names16[code - ax_reg + add];
12203 break;
12204 case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12205 USED_REX (0);
12206 /* Fall through. */
12207 case al_reg: case cl_reg: case dl_reg: case bl_reg:
12208 if (ins->rex)
12209 s = att_names8rex[code - al_reg + add];
12210 else
12211 s = att_names8[code - al_reg];
12212 break;
12213 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12214 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12215 if (ins->address_mode == mode_64bit
12216 && ((sizeflag & DFLAG) || (ins->rex & REX_W)))
12217 {
12218 s = att_names64[code - rAX_reg + add];
12219 break;
12220 }
12221 code += eAX_reg - rAX_reg;
12222 /* Fall through. */
12223 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12224 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12225 USED_REX (REX_W);
12226 if (ins->rex & REX_W)
12227 s = att_names64[code - eAX_reg + add];
12228 else
12229 {
12230 if (sizeflag & DFLAG)
12231 s = att_names32[code - eAX_reg + add];
12232 else
12233 s = att_names16[code - eAX_reg + add];
12234 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12235 }
12236 break;
12237 default:
12238 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12239 return true;
12240 }
12241 oappend_register (ins, s);
12242 return true;
12243 }
12244
12245 static bool
12246 OP_IMREG (instr_info *ins, int code, int sizeflag)
12247 {
12248 const char *s;
12249
12250 switch (code)
12251 {
12252 case indir_dx_reg:
12253 if (!ins->intel_syntax)
12254 {
12255 oappend (ins, "(%dx)");
12256 return true;
12257 }
12258 s = att_names16[dx_reg - ax_reg];
12259 break;
12260 case al_reg: case cl_reg:
12261 s = att_names8[code - al_reg];
12262 break;
12263 case eAX_reg:
12264 USED_REX (REX_W);
12265 if (ins->rex & REX_W)
12266 {
12267 s = *att_names64;
12268 break;
12269 }
12270 /* Fall through. */
12271 case z_mode_ax_reg:
12272 if ((ins->rex & REX_W) || (sizeflag & DFLAG))
12273 s = *att_names32;
12274 else
12275 s = *att_names16;
12276 if (!(ins->rex & REX_W))
12277 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12278 break;
12279 default:
12280 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12281 return true;
12282 }
12283 oappend_register (ins, s);
12284 return true;
12285 }
12286
12287 static bool
12288 OP_I (instr_info *ins, int bytemode, int sizeflag)
12289 {
12290 bfd_vma op;
12291
12292 switch (bytemode)
12293 {
12294 case b_mode:
12295 if (!fetch_code (ins->info, ins->codep + 1))
12296 return false;
12297 op = *ins->codep++;
12298 break;
12299 case v_mode:
12300 USED_REX (REX_W);
12301 if (ins->rex & REX_W)
12302 {
12303 if (!get32s (ins, &op))
12304 return false;
12305 }
12306 else
12307 {
12308 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12309 if (sizeflag & DFLAG)
12310 {
12311 case d_mode:
12312 if (!get32 (ins, &op))
12313 return false;
12314 }
12315 else
12316 {
12317 /* Fall through. */
12318 case w_mode:
12319 if (!get16 (ins, &op))
12320 return false;
12321 }
12322 }
12323 break;
12324 case const_1_mode:
12325 if (ins->intel_syntax)
12326 oappend (ins, "1");
12327 return true;
12328 default:
12329 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12330 return true;
12331 }
12332
12333 oappend_immediate (ins, op);
12334 return true;
12335 }
12336
12337 static bool
12338 OP_I64 (instr_info *ins, int bytemode, int sizeflag)
12339 {
12340 uint64_t op;
12341
12342 if (bytemode != v_mode || ins->address_mode != mode_64bit
12343 || !(ins->rex & REX_W))
12344 return OP_I (ins, bytemode, sizeflag);
12345
12346 USED_REX (REX_W);
12347
12348 if (!get64 (ins, &op))
12349 return false;
12350
12351 oappend_immediate (ins, op);
12352 return true;
12353 }
12354
12355 static bool
12356 OP_sI (instr_info *ins, int bytemode, int sizeflag)
12357 {
12358 bfd_vma op;
12359
12360 switch (bytemode)
12361 {
12362 case b_mode:
12363 case b_T_mode:
12364 if (!get8s (ins, &op))
12365 return false;
12366 if (bytemode == b_T_mode)
12367 {
12368 if (ins->address_mode != mode_64bit
12369 || !((sizeflag & DFLAG) || (ins->rex & REX_W)))
12370 {
12371 /* The operand-size prefix is overridden by a REX prefix. */
12372 if ((sizeflag & DFLAG) || (ins->rex & REX_W))
12373 op &= 0xffffffff;
12374 else
12375 op &= 0xffff;
12376 }
12377 }
12378 else
12379 {
12380 if (!(ins->rex & REX_W))
12381 {
12382 if (sizeflag & DFLAG)
12383 op &= 0xffffffff;
12384 else
12385 op &= 0xffff;
12386 }
12387 }
12388 break;
12389 case v_mode:
12390 /* The operand-size prefix is overridden by a REX prefix. */
12391 if (!(sizeflag & DFLAG) && !(ins->rex & REX_W))
12392 {
12393 if (!get16 (ins, &op))
12394 return false;
12395 }
12396 else if (!get32s (ins, &op))
12397 return false;
12398 break;
12399 default:
12400 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12401 return true;
12402 }
12403
12404 oappend_immediate (ins, op);
12405 return true;
12406 }
12407
12408 static bool
12409 OP_J (instr_info *ins, int bytemode, int sizeflag)
12410 {
12411 bfd_vma disp;
12412 bfd_vma mask = -1;
12413 bfd_vma segment = 0;
12414
12415 switch (bytemode)
12416 {
12417 case b_mode:
12418 if (!get8s (ins, &disp))
12419 return false;
12420 break;
12421 case v_mode:
12422 case dqw_mode:
12423 if ((sizeflag & DFLAG)
12424 || (ins->address_mode == mode_64bit
12425 && ((ins->isa64 == intel64 && bytemode != dqw_mode)
12426 || (ins->rex & REX_W))))
12427 {
12428 if (!get32s (ins, &disp))
12429 return false;
12430 }
12431 else
12432 {
12433 if (!get16s (ins, &disp))
12434 return false;
12435 /* In 16bit mode, address is wrapped around at 64k within
12436 the same segment. Otherwise, a data16 prefix on a jump
12437 instruction means that the pc is masked to 16 bits after
12438 the displacement is added! */
12439 mask = 0xffff;
12440 if ((ins->prefixes & PREFIX_DATA) == 0)
12441 segment = ((ins->start_pc + (ins->codep - ins->start_codep))
12442 & ~((bfd_vma) 0xffff));
12443 }
12444 if (ins->address_mode != mode_64bit
12445 || (ins->isa64 != intel64 && !(ins->rex & REX_W)))
12446 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12447 break;
12448 default:
12449 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12450 return true;
12451 }
12452 disp = ((ins->start_pc + (ins->codep - ins->start_codep) + disp) & mask)
12453 | segment;
12454 set_op (ins, disp, false);
12455 print_operand_value (ins, disp, dis_style_text);
12456 return true;
12457 }
12458
12459 static bool
12460 OP_SEG (instr_info *ins, int bytemode, int sizeflag)
12461 {
12462 if (bytemode == w_mode)
12463 {
12464 oappend_register (ins, att_names_seg[ins->modrm.reg]);
12465 return true;
12466 }
12467 return OP_E (ins, ins->modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12468 }
12469
12470 static bool
12471 OP_DIR (instr_info *ins, int dummy ATTRIBUTE_UNUSED, int sizeflag)
12472 {
12473 bfd_vma seg, offset;
12474 int res;
12475 char scratch[24];
12476
12477 if (sizeflag & DFLAG)
12478 {
12479 if (!get32 (ins, &offset))
12480 return false;;
12481 }
12482 else if (!get16 (ins, &offset))
12483 return false;
12484 if (!get16 (ins, &seg))
12485 return false;;
12486 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12487
12488 res = snprintf (scratch, ARRAY_SIZE (scratch),
12489 ins->intel_syntax ? "0x%x:0x%x" : "$0x%x,$0x%x",
12490 (unsigned) seg, (unsigned) offset);
12491 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12492 abort ();
12493 oappend (ins, scratch);
12494 return true;
12495 }
12496
12497 static bool
12498 OP_OFF (instr_info *ins, int bytemode, int sizeflag)
12499 {
12500 bfd_vma off;
12501
12502 if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12503 intel_operand_size (ins, bytemode, sizeflag);
12504 append_seg (ins);
12505
12506 if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
12507 {
12508 if (!get32 (ins, &off))
12509 return false;
12510 }
12511 else
12512 {
12513 if (!get16 (ins, &off))
12514 return false;
12515 }
12516
12517 if (ins->intel_syntax)
12518 {
12519 if (!ins->active_seg_prefix)
12520 {
12521 oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12522 oappend (ins, ":");
12523 }
12524 }
12525 print_operand_value (ins, off, dis_style_address_offset);
12526 return true;
12527 }
12528
12529 static bool
12530 OP_OFF64 (instr_info *ins, int bytemode, int sizeflag)
12531 {
12532 uint64_t off;
12533
12534 if (ins->address_mode != mode_64bit
12535 || (ins->prefixes & PREFIX_ADDR))
12536 return OP_OFF (ins, bytemode, sizeflag);
12537
12538 if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12539 intel_operand_size (ins, bytemode, sizeflag);
12540 append_seg (ins);
12541
12542 if (!get64 (ins, &off))
12543 return false;
12544
12545 if (ins->intel_syntax)
12546 {
12547 if (!ins->active_seg_prefix)
12548 {
12549 oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12550 oappend (ins, ":");
12551 }
12552 }
12553 print_operand_value (ins, off, dis_style_address_offset);
12554 return true;
12555 }
12556
12557 static void
12558 ptr_reg (instr_info *ins, int code, int sizeflag)
12559 {
12560 const char *s;
12561
12562 *ins->obufp++ = ins->open_char;
12563 ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
12564 if (ins->address_mode == mode_64bit)
12565 {
12566 if (!(sizeflag & AFLAG))
12567 s = att_names32[code - eAX_reg];
12568 else
12569 s = att_names64[code - eAX_reg];
12570 }
12571 else if (sizeflag & AFLAG)
12572 s = att_names32[code - eAX_reg];
12573 else
12574 s = att_names16[code - eAX_reg];
12575 oappend_register (ins, s);
12576 oappend_char (ins, ins->close_char);
12577 }
12578
12579 static bool
12580 OP_ESreg (instr_info *ins, int code, int sizeflag)
12581 {
12582 if (ins->intel_syntax)
12583 {
12584 switch (ins->codep[-1])
12585 {
12586 case 0x6d: /* insw/insl */
12587 intel_operand_size (ins, z_mode, sizeflag);
12588 break;
12589 case 0xa5: /* movsw/movsl/movsq */
12590 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12591 case 0xab: /* stosw/stosl */
12592 case 0xaf: /* scasw/scasl */
12593 intel_operand_size (ins, v_mode, sizeflag);
12594 break;
12595 default:
12596 intel_operand_size (ins, b_mode, sizeflag);
12597 }
12598 }
12599 oappend_register (ins, att_names_seg[0]);
12600 oappend_char (ins, ':');
12601 ptr_reg (ins, code, sizeflag);
12602 return true;
12603 }
12604
12605 static bool
12606 OP_DSreg (instr_info *ins, int code, int sizeflag)
12607 {
12608 if (ins->intel_syntax)
12609 {
12610 switch (ins->codep[-1])
12611 {
12612 case 0x6f: /* outsw/outsl */
12613 intel_operand_size (ins, z_mode, sizeflag);
12614 break;
12615 case 0xa5: /* movsw/movsl/movsq */
12616 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12617 case 0xad: /* lodsw/lodsl/lodsq */
12618 intel_operand_size (ins, v_mode, sizeflag);
12619 break;
12620 default:
12621 intel_operand_size (ins, b_mode, sizeflag);
12622 }
12623 }
12624 /* Set ins->active_seg_prefix to PREFIX_DS if it is unset so that the
12625 default segment register DS is printed. */
12626 if (!ins->active_seg_prefix)
12627 ins->active_seg_prefix = PREFIX_DS;
12628 append_seg (ins);
12629 ptr_reg (ins, code, sizeflag);
12630 return true;
12631 }
12632
12633 static bool
12634 OP_C (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12635 int sizeflag ATTRIBUTE_UNUSED)
12636 {
12637 int add, res;
12638 char scratch[8];
12639
12640 if (ins->rex & REX_R)
12641 {
12642 USED_REX (REX_R);
12643 add = 8;
12644 }
12645 else if (ins->address_mode != mode_64bit && (ins->prefixes & PREFIX_LOCK))
12646 {
12647 ins->all_prefixes[ins->last_lock_prefix] = 0;
12648 ins->used_prefixes |= PREFIX_LOCK;
12649 add = 8;
12650 }
12651 else
12652 add = 0;
12653 res = snprintf (scratch, ARRAY_SIZE (scratch), "%%cr%d",
12654 ins->modrm.reg + add);
12655 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12656 abort ();
12657 oappend_register (ins, scratch);
12658 return true;
12659 }
12660
12661 static bool
12662 OP_D (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12663 int sizeflag ATTRIBUTE_UNUSED)
12664 {
12665 int add, res;
12666 char scratch[8];
12667
12668 USED_REX (REX_R);
12669 if (ins->rex & REX_R)
12670 add = 8;
12671 else
12672 add = 0;
12673 res = snprintf (scratch, ARRAY_SIZE (scratch),
12674 ins->intel_syntax ? "dr%d" : "%%db%d",
12675 ins->modrm.reg + add);
12676 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12677 abort ();
12678 oappend (ins, scratch);
12679 return true;
12680 }
12681
12682 static bool
12683 OP_T (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12684 int sizeflag ATTRIBUTE_UNUSED)
12685 {
12686 int res;
12687 char scratch[8];
12688
12689 res = snprintf (scratch, ARRAY_SIZE (scratch), "%%tr%d", ins->modrm.reg);
12690 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12691 abort ();
12692 oappend_register (ins, scratch);
12693 return true;
12694 }
12695
12696 static bool
12697 OP_MMX (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12698 int sizeflag ATTRIBUTE_UNUSED)
12699 {
12700 int reg = ins->modrm.reg;
12701 const char (*names)[8];
12702
12703 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12704 if (ins->prefixes & PREFIX_DATA)
12705 {
12706 names = att_names_xmm;
12707 USED_REX (REX_R);
12708 if (ins->rex & REX_R)
12709 reg += 8;
12710 }
12711 else
12712 names = att_names_mm;
12713 oappend_register (ins, names[reg]);
12714 return true;
12715 }
12716
12717 static void
12718 print_vector_reg (instr_info *ins, unsigned int reg, int bytemode)
12719 {
12720 const char (*names)[8];
12721
12722 if (bytemode == xmmq_mode
12723 || bytemode == evex_half_bcst_xmmqh_mode
12724 || bytemode == evex_half_bcst_xmmq_mode)
12725 {
12726 switch (ins->vex.length)
12727 {
12728 case 0:
12729 case 128:
12730 case 256:
12731 names = att_names_xmm;
12732 break;
12733 case 512:
12734 names = att_names_ymm;
12735 ins->evex_used |= EVEX_len_used;
12736 break;
12737 default:
12738 abort ();
12739 }
12740 }
12741 else if (bytemode == ymm_mode)
12742 names = att_names_ymm;
12743 else if (bytemode == tmm_mode)
12744 {
12745 if (reg >= 8)
12746 {
12747 oappend (ins, "(bad)");
12748 return;
12749 }
12750 names = att_names_tmm;
12751 }
12752 else if (ins->need_vex
12753 && bytemode != xmm_mode
12754 && bytemode != scalar_mode
12755 && bytemode != xmmdw_mode
12756 && bytemode != xmmqd_mode
12757 && bytemode != evex_half_bcst_xmmqdh_mode
12758 && bytemode != w_swap_mode
12759 && bytemode != b_mode
12760 && bytemode != w_mode
12761 && bytemode != d_mode
12762 && bytemode != q_mode)
12763 {
12764 ins->evex_used |= EVEX_len_used;
12765 switch (ins->vex.length)
12766 {
12767 case 128:
12768 names = att_names_xmm;
12769 break;
12770 case 256:
12771 if (ins->vex.w
12772 || bytemode != vex_vsib_q_w_dq_mode)
12773 names = att_names_ymm;
12774 else
12775 names = att_names_xmm;
12776 break;
12777 case 512:
12778 if (ins->vex.w
12779 || bytemode != vex_vsib_q_w_dq_mode)
12780 names = att_names_zmm;
12781 else
12782 names = att_names_ymm;
12783 break;
12784 default:
12785 abort ();
12786 }
12787 }
12788 else
12789 names = att_names_xmm;
12790 oappend_register (ins, names[reg]);
12791 }
12792
12793 static bool
12794 OP_XMM (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12795 {
12796 unsigned int reg = ins->modrm.reg;
12797
12798 USED_REX (REX_R);
12799 if (ins->rex & REX_R)
12800 reg += 8;
12801 if (ins->vex.evex)
12802 {
12803 if (!ins->vex.r)
12804 reg += 16;
12805 }
12806
12807 if (bytemode == tmm_mode)
12808 ins->modrm.reg = reg;
12809 else if (bytemode == scalar_mode)
12810 ins->vex.no_broadcast = true;
12811
12812 print_vector_reg (ins, reg, bytemode);
12813 return true;
12814 }
12815
12816 static bool
12817 OP_EM (instr_info *ins, int bytemode, int sizeflag)
12818 {
12819 int reg;
12820 const char (*names)[8];
12821
12822 if (ins->modrm.mod != 3)
12823 {
12824 if (ins->intel_syntax
12825 && (bytemode == v_mode || bytemode == v_swap_mode))
12826 {
12827 bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
12828 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12829 }
12830 return OP_E (ins, bytemode, sizeflag);
12831 }
12832
12833 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12834 swap_operand (ins);
12835
12836 /* Skip mod/rm byte. */
12837 MODRM_CHECK;
12838 ins->codep++;
12839 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12840 reg = ins->modrm.rm;
12841 if (ins->prefixes & PREFIX_DATA)
12842 {
12843 names = att_names_xmm;
12844 USED_REX (REX_B);
12845 if (ins->rex & REX_B)
12846 reg += 8;
12847 }
12848 else
12849 names = att_names_mm;
12850 oappend_register (ins, names[reg]);
12851 return true;
12852 }
12853
12854 /* cvt* are the only instructions in sse2 which have
12855 both SSE and MMX operands and also have 0x66 prefix
12856 in their opcode. 0x66 was originally used to differentiate
12857 between SSE and MMX instruction(operands). So we have to handle the
12858 cvt* separately using OP_EMC and OP_MXC */
12859 static bool
12860 OP_EMC (instr_info *ins, int bytemode, int sizeflag)
12861 {
12862 if (ins->modrm.mod != 3)
12863 {
12864 if (ins->intel_syntax && bytemode == v_mode)
12865 {
12866 bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
12867 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12868 }
12869 return OP_E (ins, bytemode, sizeflag);
12870 }
12871
12872 /* Skip mod/rm byte. */
12873 MODRM_CHECK;
12874 ins->codep++;
12875 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12876 oappend_register (ins, att_names_mm[ins->modrm.rm]);
12877 return true;
12878 }
12879
12880 static bool
12881 OP_MXC (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12882 int sizeflag ATTRIBUTE_UNUSED)
12883 {
12884 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12885 oappend_register (ins, att_names_mm[ins->modrm.reg]);
12886 return true;
12887 }
12888
12889 static bool
12890 OP_EX (instr_info *ins, int bytemode, int sizeflag)
12891 {
12892 int reg;
12893
12894 /* Skip mod/rm byte. */
12895 MODRM_CHECK;
12896 ins->codep++;
12897
12898 if (bytemode == dq_mode)
12899 bytemode = ins->vex.w ? q_mode : d_mode;
12900
12901 if (ins->modrm.mod != 3)
12902 return OP_E_memory (ins, bytemode, sizeflag);
12903
12904 reg = ins->modrm.rm;
12905 USED_REX (REX_B);
12906 if (ins->rex & REX_B)
12907 reg += 8;
12908 if (ins->vex.evex)
12909 {
12910 USED_REX (REX_X);
12911 if ((ins->rex & REX_X))
12912 reg += 16;
12913 }
12914
12915 if ((sizeflag & SUFFIX_ALWAYS)
12916 && (bytemode == x_swap_mode
12917 || bytemode == w_swap_mode
12918 || bytemode == d_swap_mode
12919 || bytemode == q_swap_mode))
12920 swap_operand (ins);
12921
12922 if (bytemode == tmm_mode)
12923 ins->modrm.rm = reg;
12924
12925 print_vector_reg (ins, reg, bytemode);
12926 return true;
12927 }
12928
12929 static bool
12930 OP_MS (instr_info *ins, int bytemode, int sizeflag)
12931 {
12932 if (ins->modrm.mod == 3)
12933 return OP_EM (ins, bytemode, sizeflag);
12934 return BadOp (ins);
12935 }
12936
12937 static bool
12938 OP_XS (instr_info *ins, int bytemode, int sizeflag)
12939 {
12940 if (ins->modrm.mod == 3)
12941 return OP_EX (ins, bytemode, sizeflag);
12942 return BadOp (ins);
12943 }
12944
12945 static bool
12946 OP_M (instr_info *ins, int bytemode, int sizeflag)
12947 {
12948 /* Skip mod/rm byte. */
12949 MODRM_CHECK;
12950 ins->codep++;
12951
12952 if (ins->modrm.mod == 3)
12953 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12954 return BadOp (ins);
12955 return OP_E_memory (ins, bytemode, sizeflag);
12956 }
12957
12958 static bool
12959 OP_0f07 (instr_info *ins, int bytemode, int sizeflag)
12960 {
12961 if (ins->modrm.mod != 3 || ins->modrm.rm != 0)
12962 return BadOp (ins);
12963 return OP_E (ins, bytemode, sizeflag);
12964 }
12965
12966 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
12967 32bit mode and "xchg %rax,%rax" in 64bit mode. */
12968
12969 static bool
12970 NOP_Fixup (instr_info *ins, int opnd, int sizeflag)
12971 {
12972 if ((ins->prefixes & PREFIX_DATA) == 0 && (ins->rex & REX_B) == 0)
12973 {
12974 ins->mnemonicendp = stpcpy (ins->obuf, "nop");
12975 return true;
12976 }
12977 if (opnd == 0)
12978 return OP_REG (ins, eAX_reg, sizeflag);
12979 return OP_IMREG (ins, eAX_reg, sizeflag);
12980 }
12981
12982 static const char *const Suffix3DNow[] = {
12983 /* 00 */ NULL, NULL, NULL, NULL,
12984 /* 04 */ NULL, NULL, NULL, NULL,
12985 /* 08 */ NULL, NULL, NULL, NULL,
12986 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
12987 /* 10 */ NULL, NULL, NULL, NULL,
12988 /* 14 */ NULL, NULL, NULL, NULL,
12989 /* 18 */ NULL, NULL, NULL, NULL,
12990 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
12991 /* 20 */ NULL, NULL, NULL, NULL,
12992 /* 24 */ NULL, NULL, NULL, NULL,
12993 /* 28 */ NULL, NULL, NULL, NULL,
12994 /* 2C */ NULL, NULL, NULL, NULL,
12995 /* 30 */ NULL, NULL, NULL, NULL,
12996 /* 34 */ NULL, NULL, NULL, NULL,
12997 /* 38 */ NULL, NULL, NULL, NULL,
12998 /* 3C */ NULL, NULL, NULL, NULL,
12999 /* 40 */ NULL, NULL, NULL, NULL,
13000 /* 44 */ NULL, NULL, NULL, NULL,
13001 /* 48 */ NULL, NULL, NULL, NULL,
13002 /* 4C */ NULL, NULL, NULL, NULL,
13003 /* 50 */ NULL, NULL, NULL, NULL,
13004 /* 54 */ NULL, NULL, NULL, NULL,
13005 /* 58 */ NULL, NULL, NULL, NULL,
13006 /* 5C */ NULL, NULL, NULL, NULL,
13007 /* 60 */ NULL, NULL, NULL, NULL,
13008 /* 64 */ NULL, NULL, NULL, NULL,
13009 /* 68 */ NULL, NULL, NULL, NULL,
13010 /* 6C */ NULL, NULL, NULL, NULL,
13011 /* 70 */ NULL, NULL, NULL, NULL,
13012 /* 74 */ NULL, NULL, NULL, NULL,
13013 /* 78 */ NULL, NULL, NULL, NULL,
13014 /* 7C */ NULL, NULL, NULL, NULL,
13015 /* 80 */ NULL, NULL, NULL, NULL,
13016 /* 84 */ NULL, NULL, NULL, NULL,
13017 /* 88 */ NULL, NULL, "pfnacc", NULL,
13018 /* 8C */ NULL, NULL, "pfpnacc", NULL,
13019 /* 90 */ "pfcmpge", NULL, NULL, NULL,
13020 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
13021 /* 98 */ NULL, NULL, "pfsub", NULL,
13022 /* 9C */ NULL, NULL, "pfadd", NULL,
13023 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
13024 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
13025 /* A8 */ NULL, NULL, "pfsubr", NULL,
13026 /* AC */ NULL, NULL, "pfacc", NULL,
13027 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
13028 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
13029 /* B8 */ NULL, NULL, NULL, "pswapd",
13030 /* BC */ NULL, NULL, NULL, "pavgusb",
13031 /* C0 */ NULL, NULL, NULL, NULL,
13032 /* C4 */ NULL, NULL, NULL, NULL,
13033 /* C8 */ NULL, NULL, NULL, NULL,
13034 /* CC */ NULL, NULL, NULL, NULL,
13035 /* D0 */ NULL, NULL, NULL, NULL,
13036 /* D4 */ NULL, NULL, NULL, NULL,
13037 /* D8 */ NULL, NULL, NULL, NULL,
13038 /* DC */ NULL, NULL, NULL, NULL,
13039 /* E0 */ NULL, NULL, NULL, NULL,
13040 /* E4 */ NULL, NULL, NULL, NULL,
13041 /* E8 */ NULL, NULL, NULL, NULL,
13042 /* EC */ NULL, NULL, NULL, NULL,
13043 /* F0 */ NULL, NULL, NULL, NULL,
13044 /* F4 */ NULL, NULL, NULL, NULL,
13045 /* F8 */ NULL, NULL, NULL, NULL,
13046 /* FC */ NULL, NULL, NULL, NULL,
13047 };
13048
13049 static bool
13050 OP_3DNowSuffix (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13051 int sizeflag ATTRIBUTE_UNUSED)
13052 {
13053 const char *mnemonic;
13054
13055 if (!fetch_code (ins->info, ins->codep + 1))
13056 return false;
13057 /* AMD 3DNow! instructions are specified by an opcode suffix in the
13058 place where an 8-bit immediate would normally go. ie. the last
13059 byte of the instruction. */
13060 ins->obufp = ins->mnemonicendp;
13061 mnemonic = Suffix3DNow[*ins->codep++];
13062 if (mnemonic)
13063 ins->obufp = stpcpy (ins->obufp, mnemonic);
13064 else
13065 {
13066 /* Since a variable sized ins->modrm/ins->sib chunk is between the start
13067 of the opcode (0x0f0f) and the opcode suffix, we need to do
13068 all the ins->modrm processing first, and don't know until now that
13069 we have a bad opcode. This necessitates some cleaning up. */
13070 ins->op_out[0][0] = '\0';
13071 ins->op_out[1][0] = '\0';
13072 BadOp (ins);
13073 }
13074 ins->mnemonicendp = ins->obufp;
13075 return true;
13076 }
13077
13078 static const struct op simd_cmp_op[] =
13079 {
13080 { STRING_COMMA_LEN ("eq") },
13081 { STRING_COMMA_LEN ("lt") },
13082 { STRING_COMMA_LEN ("le") },
13083 { STRING_COMMA_LEN ("unord") },
13084 { STRING_COMMA_LEN ("neq") },
13085 { STRING_COMMA_LEN ("nlt") },
13086 { STRING_COMMA_LEN ("nle") },
13087 { STRING_COMMA_LEN ("ord") }
13088 };
13089
13090 static const struct op vex_cmp_op[] =
13091 {
13092 { STRING_COMMA_LEN ("eq_uq") },
13093 { STRING_COMMA_LEN ("nge") },
13094 { STRING_COMMA_LEN ("ngt") },
13095 { STRING_COMMA_LEN ("false") },
13096 { STRING_COMMA_LEN ("neq_oq") },
13097 { STRING_COMMA_LEN ("ge") },
13098 { STRING_COMMA_LEN ("gt") },
13099 { STRING_COMMA_LEN ("true") },
13100 { STRING_COMMA_LEN ("eq_os") },
13101 { STRING_COMMA_LEN ("lt_oq") },
13102 { STRING_COMMA_LEN ("le_oq") },
13103 { STRING_COMMA_LEN ("unord_s") },
13104 { STRING_COMMA_LEN ("neq_us") },
13105 { STRING_COMMA_LEN ("nlt_uq") },
13106 { STRING_COMMA_LEN ("nle_uq") },
13107 { STRING_COMMA_LEN ("ord_s") },
13108 { STRING_COMMA_LEN ("eq_us") },
13109 { STRING_COMMA_LEN ("nge_uq") },
13110 { STRING_COMMA_LEN ("ngt_uq") },
13111 { STRING_COMMA_LEN ("false_os") },
13112 { STRING_COMMA_LEN ("neq_os") },
13113 { STRING_COMMA_LEN ("ge_oq") },
13114 { STRING_COMMA_LEN ("gt_oq") },
13115 { STRING_COMMA_LEN ("true_us") },
13116 };
13117
13118 static bool
13119 CMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13120 int sizeflag ATTRIBUTE_UNUSED)
13121 {
13122 unsigned int cmp_type;
13123
13124 if (!fetch_code (ins->info, ins->codep + 1))
13125 return false;
13126 cmp_type = *ins->codep++;
13127 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13128 {
13129 char suffix[3];
13130 char *p = ins->mnemonicendp - 2;
13131 suffix[0] = p[0];
13132 suffix[1] = p[1];
13133 suffix[2] = '\0';
13134 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13135 ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13136 }
13137 else if (ins->need_vex
13138 && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13139 {
13140 char suffix[3];
13141 char *p = ins->mnemonicendp - 2;
13142 suffix[0] = p[0];
13143 suffix[1] = p[1];
13144 suffix[2] = '\0';
13145 cmp_type -= ARRAY_SIZE (simd_cmp_op);
13146 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13147 ins->mnemonicendp += vex_cmp_op[cmp_type].len;
13148 }
13149 else
13150 {
13151 /* We have a reserved extension byte. Output it directly. */
13152 oappend_immediate (ins, cmp_type);
13153 }
13154 return true;
13155 }
13156
13157 static bool
13158 OP_Mwait (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13159 {
13160 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
13161 if (!ins->intel_syntax)
13162 {
13163 strcpy (ins->op_out[0], att_names32[0] + ins->intel_syntax);
13164 strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13165 if (bytemode == eBX_reg)
13166 strcpy (ins->op_out[2], att_names32[3] + ins->intel_syntax);
13167 ins->two_source_ops = true;
13168 }
13169 /* Skip mod/rm byte. */
13170 MODRM_CHECK;
13171 ins->codep++;
13172 return true;
13173 }
13174
13175 static bool
13176 OP_Monitor (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13177 int sizeflag ATTRIBUTE_UNUSED)
13178 {
13179 /* monitor %{e,r,}ax,%ecx,%edx" */
13180 if (!ins->intel_syntax)
13181 {
13182 const char (*names)[8] = (ins->address_mode == mode_64bit
13183 ? att_names64 : att_names32);
13184
13185 if (ins->prefixes & PREFIX_ADDR)
13186 {
13187 /* Remove "addr16/addr32". */
13188 ins->all_prefixes[ins->last_addr_prefix] = 0;
13189 names = (ins->address_mode != mode_32bit
13190 ? att_names32 : att_names16);
13191 ins->used_prefixes |= PREFIX_ADDR;
13192 }
13193 else if (ins->address_mode == mode_16bit)
13194 names = att_names16;
13195 strcpy (ins->op_out[0], names[0] + ins->intel_syntax);
13196 strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13197 strcpy (ins->op_out[2], att_names32[2] + ins->intel_syntax);
13198 ins->two_source_ops = true;
13199 }
13200 /* Skip mod/rm byte. */
13201 MODRM_CHECK;
13202 ins->codep++;
13203 return true;
13204 }
13205
13206 static bool
13207 REP_Fixup (instr_info *ins, int bytemode, int sizeflag)
13208 {
13209 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13210 lods and stos. */
13211 if (ins->prefixes & PREFIX_REPZ)
13212 ins->all_prefixes[ins->last_repz_prefix] = REP_PREFIX;
13213
13214 switch (bytemode)
13215 {
13216 case al_reg:
13217 case eAX_reg:
13218 case indir_dx_reg:
13219 return OP_IMREG (ins, bytemode, sizeflag);
13220 case eDI_reg:
13221 return OP_ESreg (ins, bytemode, sizeflag);
13222 case eSI_reg:
13223 return OP_DSreg (ins, bytemode, sizeflag);
13224 default:
13225 abort ();
13226 break;
13227 }
13228 return true;
13229 }
13230
13231 static bool
13232 SEP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13233 int sizeflag ATTRIBUTE_UNUSED)
13234 {
13235 if (ins->isa64 != amd64)
13236 return true;
13237
13238 ins->obufp = ins->obuf;
13239 BadOp (ins);
13240 ins->mnemonicendp = ins->obufp;
13241 ++ins->codep;
13242 return true;
13243 }
13244
13245 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13246 "bnd". */
13247
13248 static bool
13249 BND_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13250 int sizeflag ATTRIBUTE_UNUSED)
13251 {
13252 if (ins->prefixes & PREFIX_REPNZ)
13253 ins->all_prefixes[ins->last_repnz_prefix] = BND_PREFIX;
13254 return true;
13255 }
13256
13257 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13258 "notrack". */
13259
13260 static bool
13261 NOTRACK_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13262 int sizeflag ATTRIBUTE_UNUSED)
13263 {
13264 /* Since active_seg_prefix is not set in 64-bit mode, check whether
13265 we've seen a PREFIX_DS. */
13266 if ((ins->prefixes & PREFIX_DS) != 0
13267 && (ins->address_mode != mode_64bit || ins->last_data_prefix < 0))
13268 {
13269 /* NOTRACK prefix is only valid on indirect branch instructions.
13270 NB: DATA prefix is unsupported for Intel64. */
13271 ins->active_seg_prefix = 0;
13272 ins->all_prefixes[ins->last_seg_prefix] = NOTRACK_PREFIX;
13273 }
13274 return true;
13275 }
13276
13277 /* Similar to OP_E. But the 0xf2/0xf3 ins->prefixes should be displayed as
13278 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13279 */
13280
13281 static bool
13282 HLE_Fixup1 (instr_info *ins, int bytemode, int sizeflag)
13283 {
13284 if (ins->modrm.mod != 3
13285 && (ins->prefixes & PREFIX_LOCK) != 0)
13286 {
13287 if (ins->prefixes & PREFIX_REPZ)
13288 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13289 if (ins->prefixes & PREFIX_REPNZ)
13290 ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13291 }
13292
13293 return OP_E (ins, bytemode, sizeflag);
13294 }
13295
13296 /* Similar to OP_E. But the 0xf2/0xf3 ins->prefixes should be displayed as
13297 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
13298 */
13299
13300 static bool
13301 HLE_Fixup2 (instr_info *ins, int bytemode, int sizeflag)
13302 {
13303 if (ins->modrm.mod != 3)
13304 {
13305 if (ins->prefixes & PREFIX_REPZ)
13306 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13307 if (ins->prefixes & PREFIX_REPNZ)
13308 ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13309 }
13310
13311 return OP_E (ins, bytemode, sizeflag);
13312 }
13313
13314 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
13315 "xrelease" for memory operand. No check for LOCK prefix. */
13316
13317 static bool
13318 HLE_Fixup3 (instr_info *ins, int bytemode, int sizeflag)
13319 {
13320 if (ins->modrm.mod != 3
13321 && ins->last_repz_prefix > ins->last_repnz_prefix
13322 && (ins->prefixes & PREFIX_REPZ) != 0)
13323 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13324
13325 return OP_E (ins, bytemode, sizeflag);
13326 }
13327
13328 static bool
13329 CMPXCHG8B_Fixup (instr_info *ins, int bytemode, int sizeflag)
13330 {
13331 USED_REX (REX_W);
13332 if (ins->rex & REX_W)
13333 {
13334 /* Change cmpxchg8b to cmpxchg16b. */
13335 char *p = ins->mnemonicendp - 2;
13336 ins->mnemonicendp = stpcpy (p, "16b");
13337 bytemode = o_mode;
13338 }
13339 else if ((ins->prefixes & PREFIX_LOCK) != 0)
13340 {
13341 if (ins->prefixes & PREFIX_REPZ)
13342 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13343 if (ins->prefixes & PREFIX_REPNZ)
13344 ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13345 }
13346
13347 return OP_M (ins, bytemode, sizeflag);
13348 }
13349
13350 static bool
13351 XMM_Fixup (instr_info *ins, int reg, int sizeflag ATTRIBUTE_UNUSED)
13352 {
13353 const char (*names)[8] = att_names_xmm;
13354
13355 if (ins->need_vex)
13356 {
13357 switch (ins->vex.length)
13358 {
13359 case 128:
13360 break;
13361 case 256:
13362 names = att_names_ymm;
13363 break;
13364 default:
13365 abort ();
13366 }
13367 }
13368 oappend_register (ins, names[reg]);
13369 return true;
13370 }
13371
13372 static bool
13373 FXSAVE_Fixup (instr_info *ins, int bytemode, int sizeflag)
13374 {
13375 /* Add proper suffix to "fxsave" and "fxrstor". */
13376 USED_REX (REX_W);
13377 if (ins->rex & REX_W)
13378 {
13379 char *p = ins->mnemonicendp;
13380 *p++ = '6';
13381 *p++ = '4';
13382 *p = '\0';
13383 ins->mnemonicendp = p;
13384 }
13385 return OP_M (ins, bytemode, sizeflag);
13386 }
13387
13388 /* Display the destination register operand for instructions with
13389 VEX. */
13390
13391 static bool
13392 OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13393 {
13394 int reg, modrm_reg, sib_index = -1;
13395 const char (*names)[8];
13396
13397 if (!ins->need_vex)
13398 return true;
13399
13400 reg = ins->vex.register_specifier;
13401 ins->vex.register_specifier = 0;
13402 if (ins->address_mode != mode_64bit)
13403 {
13404 if (ins->vex.evex && !ins->vex.v)
13405 {
13406 oappend (ins, "(bad)");
13407 return true;
13408 }
13409
13410 reg &= 7;
13411 }
13412 else if (ins->vex.evex && !ins->vex.v)
13413 reg += 16;
13414
13415 switch (bytemode)
13416 {
13417 case scalar_mode:
13418 oappend_register (ins, att_names_xmm[reg]);
13419 return true;
13420
13421 case vex_vsib_d_w_dq_mode:
13422 case vex_vsib_q_w_dq_mode:
13423 /* This must be the 3rd operand. */
13424 if (ins->obufp != ins->op_out[2])
13425 abort ();
13426 if (ins->vex.length == 128
13427 || (bytemode != vex_vsib_d_w_dq_mode
13428 && !ins->vex.w))
13429 oappend_register (ins, att_names_xmm[reg]);
13430 else
13431 oappend_register (ins, att_names_ymm[reg]);
13432
13433 /* All 3 XMM/YMM registers must be distinct. */
13434 modrm_reg = ins->modrm.reg;
13435 if (ins->rex & REX_R)
13436 modrm_reg += 8;
13437
13438 if (ins->has_sib && ins->modrm.rm == 4)
13439 {
13440 sib_index = ins->sib.index;
13441 if (ins->rex & REX_X)
13442 sib_index += 8;
13443 }
13444
13445 if (reg == modrm_reg || reg == sib_index)
13446 strcpy (ins->obufp, "/(bad)");
13447 if (modrm_reg == sib_index || modrm_reg == reg)
13448 strcat (ins->op_out[0], "/(bad)");
13449 if (sib_index == modrm_reg || sib_index == reg)
13450 strcat (ins->op_out[1], "/(bad)");
13451
13452 return true;
13453
13454 case tmm_mode:
13455 /* All 3 TMM registers must be distinct. */
13456 if (reg >= 8)
13457 oappend (ins, "(bad)");
13458 else
13459 {
13460 /* This must be the 3rd operand. */
13461 if (ins->obufp != ins->op_out[2])
13462 abort ();
13463 oappend_register (ins, att_names_tmm[reg]);
13464 if (reg == ins->modrm.reg || reg == ins->modrm.rm)
13465 strcpy (ins->obufp, "/(bad)");
13466 }
13467
13468 if (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg
13469 || ins->modrm.rm == reg)
13470 {
13471 if (ins->modrm.reg <= 8
13472 && (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg))
13473 strcat (ins->op_out[0], "/(bad)");
13474 if (ins->modrm.rm <= 8
13475 && (ins->modrm.rm == ins->modrm.reg || ins->modrm.rm == reg))
13476 strcat (ins->op_out[1], "/(bad)");
13477 }
13478
13479 return true;
13480 }
13481
13482 switch (ins->vex.length)
13483 {
13484 case 128:
13485 switch (bytemode)
13486 {
13487 case x_mode:
13488 names = att_names_xmm;
13489 ins->evex_used |= EVEX_len_used;
13490 break;
13491 case dq_mode:
13492 if (ins->rex & REX_W)
13493 names = att_names64;
13494 else
13495 names = att_names32;
13496 break;
13497 case mask_bd_mode:
13498 case mask_mode:
13499 if (reg > 0x7)
13500 {
13501 oappend (ins, "(bad)");
13502 return true;
13503 }
13504 names = att_names_mask;
13505 break;
13506 default:
13507 abort ();
13508 return true;
13509 }
13510 break;
13511 case 256:
13512 switch (bytemode)
13513 {
13514 case x_mode:
13515 names = att_names_ymm;
13516 ins->evex_used |= EVEX_len_used;
13517 break;
13518 case mask_bd_mode:
13519 case mask_mode:
13520 if (reg <= 0x7)
13521 {
13522 names = att_names_mask;
13523 break;
13524 }
13525 /* Fall through. */
13526 default:
13527 /* See PR binutils/20893 for a reproducer. */
13528 oappend (ins, "(bad)");
13529 return true;
13530 }
13531 break;
13532 case 512:
13533 names = att_names_zmm;
13534 ins->evex_used |= EVEX_len_used;
13535 break;
13536 default:
13537 abort ();
13538 break;
13539 }
13540 oappend_register (ins, names[reg]);
13541 return true;
13542 }
13543
13544 static bool
13545 OP_VexR (instr_info *ins, int bytemode, int sizeflag)
13546 {
13547 if (ins->modrm.mod == 3)
13548 return OP_VEX (ins, bytemode, sizeflag);
13549 return true;
13550 }
13551
13552 static bool
13553 OP_VexW (instr_info *ins, int bytemode, int sizeflag)
13554 {
13555 OP_VEX (ins, bytemode, sizeflag);
13556
13557 if (ins->vex.w)
13558 {
13559 /* Swap 2nd and 3rd operands. */
13560 char *tmp = ins->op_out[2];
13561
13562 ins->op_out[2] = ins->op_out[1];
13563 ins->op_out[1] = tmp;
13564 }
13565 return true;
13566 }
13567
13568 static bool
13569 OP_REG_VexI4 (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13570 {
13571 int reg;
13572 const char (*names)[8] = att_names_xmm;
13573
13574 if (!fetch_code (ins->info, ins->codep + 1))
13575 return false;
13576 reg = *ins->codep++;
13577
13578 if (bytemode != x_mode && bytemode != scalar_mode)
13579 abort ();
13580
13581 reg >>= 4;
13582 if (ins->address_mode != mode_64bit)
13583 reg &= 7;
13584
13585 if (bytemode == x_mode && ins->vex.length == 256)
13586 names = att_names_ymm;
13587
13588 oappend_register (ins, names[reg]);
13589
13590 if (ins->vex.w)
13591 {
13592 /* Swap 3rd and 4th operands. */
13593 char *tmp = ins->op_out[3];
13594
13595 ins->op_out[3] = ins->op_out[2];
13596 ins->op_out[2] = tmp;
13597 }
13598 return true;
13599 }
13600
13601 static bool
13602 OP_VexI4 (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13603 int sizeflag ATTRIBUTE_UNUSED)
13604 {
13605 oappend_immediate (ins, ins->codep[-1] & 0xf);
13606 return true;
13607 }
13608
13609 static bool
13610 VPCMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13611 int sizeflag ATTRIBUTE_UNUSED)
13612 {
13613 unsigned int cmp_type;
13614
13615 if (!ins->vex.evex)
13616 abort ();
13617
13618 if (!fetch_code (ins->info, ins->codep + 1))
13619 return false;
13620 cmp_type = *ins->codep++;
13621 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13622 If it's the case, print suffix, otherwise - print the immediate. */
13623 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13624 && cmp_type != 3
13625 && cmp_type != 7)
13626 {
13627 char suffix[3];
13628 char *p = ins->mnemonicendp - 2;
13629
13630 /* vpcmp* can have both one- and two-lettered suffix. */
13631 if (p[0] == 'p')
13632 {
13633 p++;
13634 suffix[0] = p[0];
13635 suffix[1] = '\0';
13636 }
13637 else
13638 {
13639 suffix[0] = p[0];
13640 suffix[1] = p[1];
13641 suffix[2] = '\0';
13642 }
13643
13644 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13645 ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13646 }
13647 else
13648 {
13649 /* We have a reserved extension byte. Output it directly. */
13650 oappend_immediate (ins, cmp_type);
13651 }
13652 return true;
13653 }
13654
13655 static const struct op xop_cmp_op[] =
13656 {
13657 { STRING_COMMA_LEN ("lt") },
13658 { STRING_COMMA_LEN ("le") },
13659 { STRING_COMMA_LEN ("gt") },
13660 { STRING_COMMA_LEN ("ge") },
13661 { STRING_COMMA_LEN ("eq") },
13662 { STRING_COMMA_LEN ("neq") },
13663 { STRING_COMMA_LEN ("false") },
13664 { STRING_COMMA_LEN ("true") }
13665 };
13666
13667 static bool
13668 VPCOM_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13669 int sizeflag ATTRIBUTE_UNUSED)
13670 {
13671 unsigned int cmp_type;
13672
13673 if (!fetch_code (ins->info, ins->codep + 1))
13674 return false;
13675 cmp_type = *ins->codep++;
13676 if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13677 {
13678 char suffix[3];
13679 char *p = ins->mnemonicendp - 2;
13680
13681 /* vpcom* can have both one- and two-lettered suffix. */
13682 if (p[0] == 'm')
13683 {
13684 p++;
13685 suffix[0] = p[0];
13686 suffix[1] = '\0';
13687 }
13688 else
13689 {
13690 suffix[0] = p[0];
13691 suffix[1] = p[1];
13692 suffix[2] = '\0';
13693 }
13694
13695 sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13696 ins->mnemonicendp += xop_cmp_op[cmp_type].len;
13697 }
13698 else
13699 {
13700 /* We have a reserved extension byte. Output it directly. */
13701 oappend_immediate (ins, cmp_type);
13702 }
13703 return true;
13704 }
13705
13706 static const struct op pclmul_op[] =
13707 {
13708 { STRING_COMMA_LEN ("lql") },
13709 { STRING_COMMA_LEN ("hql") },
13710 { STRING_COMMA_LEN ("lqh") },
13711 { STRING_COMMA_LEN ("hqh") }
13712 };
13713
13714 static bool
13715 PCLMUL_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13716 int sizeflag ATTRIBUTE_UNUSED)
13717 {
13718 unsigned int pclmul_type;
13719
13720 if (!fetch_code (ins->info, ins->codep + 1))
13721 return false;
13722 pclmul_type = *ins->codep++;
13723 switch (pclmul_type)
13724 {
13725 case 0x10:
13726 pclmul_type = 2;
13727 break;
13728 case 0x11:
13729 pclmul_type = 3;
13730 break;
13731 default:
13732 break;
13733 }
13734 if (pclmul_type < ARRAY_SIZE (pclmul_op))
13735 {
13736 char suffix[4];
13737 char *p = ins->mnemonicendp - 3;
13738 suffix[0] = p[0];
13739 suffix[1] = p[1];
13740 suffix[2] = p[2];
13741 suffix[3] = '\0';
13742 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13743 ins->mnemonicendp += pclmul_op[pclmul_type].len;
13744 }
13745 else
13746 {
13747 /* We have a reserved extension byte. Output it directly. */
13748 oappend_immediate (ins, pclmul_type);
13749 }
13750 return true;
13751 }
13752
13753 static bool
13754 MOVSXD_Fixup (instr_info *ins, int bytemode, int sizeflag)
13755 {
13756 /* Add proper suffix to "movsxd". */
13757 char *p = ins->mnemonicendp;
13758
13759 switch (bytemode)
13760 {
13761 case movsxd_mode:
13762 if (!ins->intel_syntax)
13763 {
13764 USED_REX (REX_W);
13765 if (ins->rex & REX_W)
13766 {
13767 *p++ = 'l';
13768 *p++ = 'q';
13769 break;
13770 }
13771 }
13772
13773 *p++ = 'x';
13774 *p++ = 'd';
13775 break;
13776 default:
13777 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
13778 break;
13779 }
13780
13781 ins->mnemonicendp = p;
13782 *p = '\0';
13783 return OP_E (ins, bytemode, sizeflag);
13784 }
13785
13786 static bool
13787 DistinctDest_Fixup (instr_info *ins, int bytemode, int sizeflag)
13788 {
13789 unsigned int reg = ins->vex.register_specifier;
13790 unsigned int modrm_reg = ins->modrm.reg;
13791 unsigned int modrm_rm = ins->modrm.rm;
13792
13793 /* Calc destination register number. */
13794 if (ins->rex & REX_R)
13795 modrm_reg += 8;
13796 if (!ins->vex.r)
13797 modrm_reg += 16;
13798
13799 /* Calc src1 register number. */
13800 if (ins->address_mode != mode_64bit)
13801 reg &= 7;
13802 else if (ins->vex.evex && !ins->vex.v)
13803 reg += 16;
13804
13805 /* Calc src2 register number. */
13806 if (ins->modrm.mod == 3)
13807 {
13808 if (ins->rex & REX_B)
13809 modrm_rm += 8;
13810 if (ins->rex & REX_X)
13811 modrm_rm += 16;
13812 }
13813
13814 /* Destination and source registers must be distinct, output bad if
13815 dest == src1 or dest == src2. */
13816 if (modrm_reg == reg
13817 || (ins->modrm.mod == 3
13818 && modrm_reg == modrm_rm))
13819 {
13820 oappend (ins, "(bad)");
13821 return true;
13822 }
13823 return OP_XMM (ins, bytemode, sizeflag);
13824 }
13825
13826 static bool
13827 OP_Rounding (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13828 {
13829 if (ins->modrm.mod != 3 || !ins->vex.b)
13830 return true;
13831
13832 switch (bytemode)
13833 {
13834 case evex_rounding_64_mode:
13835 if (ins->address_mode != mode_64bit || !ins->vex.w)
13836 return true;
13837 /* Fall through. */
13838 case evex_rounding_mode:
13839 ins->evex_used |= EVEX_b_used;
13840 oappend (ins, names_rounding[ins->vex.ll]);
13841 break;
13842 case evex_sae_mode:
13843 ins->evex_used |= EVEX_b_used;
13844 oappend (ins, "{");
13845 break;
13846 default:
13847 abort ();
13848 }
13849 oappend (ins, "sae}");
13850 return true;
13851 }
13852
13853 static bool
13854 PREFETCHI_Fixup (instr_info *ins, int bytemode, int sizeflag)
13855 {
13856 if (ins->modrm.mod != 0 || ins->modrm.rm != 5)
13857 {
13858 if (ins->intel_syntax)
13859 {
13860 ins->mnemonicendp = stpcpy (ins->obuf, "nop ");
13861 }
13862 else
13863 {
13864 USED_REX (REX_W);
13865 if (ins->rex & REX_W)
13866 ins->mnemonicendp = stpcpy (ins->obuf, "nopq ");
13867 else
13868 {
13869 if (sizeflag & DFLAG)
13870 ins->mnemonicendp = stpcpy (ins->obuf, "nopl ");
13871 else
13872 ins->mnemonicendp = stpcpy (ins->obuf, "nopw ");
13873 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13874 }
13875 }
13876 bytemode = v_mode;
13877 }
13878
13879 return OP_M (ins, bytemode, sizeflag);
13880 }
A mirror of the official binutils-gdb repository