1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2020 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
44 static int print_insn (bfd_vma
, disassemble_info
*);
45 static void dofloat (int);
46 static void OP_ST (int, int);
47 static void OP_STi (int, int);
48 static int putop (const char *, int);
49 static void oappend (const char *);
50 static void append_seg (void);
51 static void OP_indirE (int, int);
52 static void print_operand_value (char *, int, bfd_vma
);
53 static void OP_E_register (int, int);
54 static void OP_E_memory (int, int);
55 static void print_displacement (char *, bfd_vma
);
56 static void OP_E (int, int);
57 static void OP_G (int, int);
58 static bfd_vma
get64 (void);
59 static bfd_signed_vma
get32 (void);
60 static bfd_signed_vma
get32s (void);
61 static int get16 (void);
62 static void set_op (bfd_vma
, int);
63 static void OP_Skip_MODRM (int, int);
64 static void OP_REG (int, int);
65 static void OP_IMREG (int, int);
66 static void OP_I (int, int);
67 static void OP_I64 (int, int);
68 static void OP_sI (int, int);
69 static void OP_J (int, int);
70 static void OP_SEG (int, int);
71 static void OP_DIR (int, int);
72 static void OP_OFF (int, int);
73 static void OP_OFF64 (int, int);
74 static void ptr_reg (int, int);
75 static void OP_ESreg (int, int);
76 static void OP_DSreg (int, int);
77 static void OP_C (int, int);
78 static void OP_D (int, int);
79 static void OP_T (int, int);
80 static void OP_R (int, int);
81 static void OP_MMX (int, int);
82 static void OP_XMM (int, int);
83 static void OP_EM (int, int);
84 static void OP_EX (int, int);
85 static void OP_EMC (int,int);
86 static void OP_MXC (int,int);
87 static void OP_MS (int, int);
88 static void OP_XS (int, int);
89 static void OP_M (int, int);
90 static void OP_VEX (int, int);
91 static void OP_VexR (int, int);
92 static void OP_VexW (int, int);
93 static void OP_Rounding (int, int);
94 static void OP_REG_VexI4 (int, int);
95 static void OP_VexI4 (int, int);
96 static void PCLMUL_Fixup (int, int);
97 static void VPCMP_Fixup (int, int);
98 static void VPCOM_Fixup (int, int);
99 static void OP_0f07 (int, int);
100 static void OP_Monitor (int, int);
101 static void OP_Mwait (int, int);
102 static void NOP_Fixup1 (int, int);
103 static void NOP_Fixup2 (int, int);
104 static void OP_3DNowSuffix (int, int);
105 static void CMP_Fixup (int, int);
106 static void BadOp (void);
107 static void REP_Fixup (int, int);
108 static void SEP_Fixup (int, int);
109 static void BND_Fixup (int, int);
110 static void NOTRACK_Fixup (int, int);
111 static void HLE_Fixup1 (int, int);
112 static void HLE_Fixup2 (int, int);
113 static void HLE_Fixup3 (int, int);
114 static void CMPXCHG8B_Fixup (int, int);
115 static void XMM_Fixup (int, int);
116 static void FXSAVE_Fixup (int, int);
118 static void MOVSXD_Fixup (int, int);
120 static void OP_Mask (int, int);
123 /* Points to first byte not fetched. */
124 bfd_byte
*max_fetched
;
125 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
128 OPCODES_SIGJMP_BUF bailout
;
138 enum address_mode address_mode
;
140 /* Flags for the prefixes for the current instruction. See below. */
143 /* REX prefix the current instruction. See below. */
145 /* Bits of REX we've already used. */
147 /* Mark parts used in the REX prefix. When we are testing for
148 empty prefix (for 8bit register REX extension), just mask it
149 out. Otherwise test for REX bit is excuse for existence of REX
150 only in case value is nonzero. */
151 #define USED_REX(value) \
156 rex_used |= (value) | REX_OPCODE; \
159 rex_used |= REX_OPCODE; \
162 /* Flags for prefixes which we somehow handled when printing the
163 current instruction. */
164 static int used_prefixes
;
166 /* Flags stored in PREFIXES. */
167 #define PREFIX_REPZ 1
168 #define PREFIX_REPNZ 2
169 #define PREFIX_LOCK 4
171 #define PREFIX_SS 0x10
172 #define PREFIX_DS 0x20
173 #define PREFIX_ES 0x40
174 #define PREFIX_FS 0x80
175 #define PREFIX_GS 0x100
176 #define PREFIX_DATA 0x200
177 #define PREFIX_ADDR 0x400
178 #define PREFIX_FWAIT 0x800
180 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
181 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
183 #define FETCH_DATA(info, addr) \
184 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
185 ? 1 : fetch_data ((info), (addr)))
188 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
191 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
192 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
194 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
195 status
= (*info
->read_memory_func
) (start
,
197 addr
- priv
->max_fetched
,
203 /* If we did manage to read at least one byte, then
204 print_insn_i386 will do something sensible. Otherwise, print
205 an error. We do that here because this is where we know
207 if (priv
->max_fetched
== priv
->the_buffer
)
208 (*info
->memory_error_func
) (status
, start
, info
);
209 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
212 priv
->max_fetched
= addr
;
216 /* Possible values for prefix requirement. */
217 #define PREFIX_IGNORED_SHIFT 16
218 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
219 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
220 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
221 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
222 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
224 /* Opcode prefixes. */
225 #define PREFIX_OPCODE (PREFIX_REPZ \
229 /* Prefixes ignored. */
230 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
231 | PREFIX_IGNORED_REPNZ \
232 | PREFIX_IGNORED_DATA)
234 #define XX { NULL, 0 }
235 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
237 #define Eb { OP_E, b_mode }
238 #define Ebnd { OP_E, bnd_mode }
239 #define EbS { OP_E, b_swap_mode }
240 #define EbndS { OP_E, bnd_swap_mode }
241 #define Ev { OP_E, v_mode }
242 #define Eva { OP_E, va_mode }
243 #define Ev_bnd { OP_E, v_bnd_mode }
244 #define EvS { OP_E, v_swap_mode }
245 #define Ed { OP_E, d_mode }
246 #define Edq { OP_E, dq_mode }
247 #define Edqw { OP_E, dqw_mode }
248 #define Edqb { OP_E, dqb_mode }
249 #define Edb { OP_E, db_mode }
250 #define Edw { OP_E, dw_mode }
251 #define Edqd { OP_E, dqd_mode }
252 #define Eq { OP_E, q_mode }
253 #define indirEv { OP_indirE, indir_v_mode }
254 #define indirEp { OP_indirE, f_mode }
255 #define stackEv { OP_E, stack_v_mode }
256 #define Em { OP_E, m_mode }
257 #define Ew { OP_E, w_mode }
258 #define M { OP_M, 0 } /* lea, lgdt, etc. */
259 #define Ma { OP_M, a_mode }
260 #define Mb { OP_M, b_mode }
261 #define Md { OP_M, d_mode }
262 #define Mo { OP_M, o_mode }
263 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
264 #define Mq { OP_M, q_mode }
265 #define Mv { OP_M, v_mode }
266 #define Mv_bnd { OP_M, v_bndmk_mode }
267 #define Mx { OP_M, x_mode }
268 #define Mxmm { OP_M, xmm_mode }
269 #define Gb { OP_G, b_mode }
270 #define Gbnd { OP_G, bnd_mode }
271 #define Gv { OP_G, v_mode }
272 #define Gd { OP_G, d_mode }
273 #define Gdq { OP_G, dq_mode }
274 #define Gm { OP_G, m_mode }
275 #define Gva { OP_G, va_mode }
276 #define Gw { OP_G, w_mode }
277 #define Rd { OP_R, d_mode }
278 #define Rdq { OP_R, dq_mode }
279 #define Rm { OP_R, m_mode }
280 #define Ib { OP_I, b_mode }
281 #define sIb { OP_sI, b_mode } /* sign extened byte */
282 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
283 #define Iv { OP_I, v_mode }
284 #define sIv { OP_sI, v_mode }
285 #define Iv64 { OP_I64, v_mode }
286 #define Id { OP_I, d_mode }
287 #define Iw { OP_I, w_mode }
288 #define I1 { OP_I, const_1_mode }
289 #define Jb { OP_J, b_mode }
290 #define Jv { OP_J, v_mode }
291 #define Jdqw { OP_J, dqw_mode }
292 #define Cm { OP_C, m_mode }
293 #define Dm { OP_D, m_mode }
294 #define Td { OP_T, d_mode }
295 #define Skip_MODRM { OP_Skip_MODRM, 0 }
297 #define RMeAX { OP_REG, eAX_reg }
298 #define RMeBX { OP_REG, eBX_reg }
299 #define RMeCX { OP_REG, eCX_reg }
300 #define RMeDX { OP_REG, eDX_reg }
301 #define RMeSP { OP_REG, eSP_reg }
302 #define RMeBP { OP_REG, eBP_reg }
303 #define RMeSI { OP_REG, eSI_reg }
304 #define RMeDI { OP_REG, eDI_reg }
305 #define RMrAX { OP_REG, rAX_reg }
306 #define RMrBX { OP_REG, rBX_reg }
307 #define RMrCX { OP_REG, rCX_reg }
308 #define RMrDX { OP_REG, rDX_reg }
309 #define RMrSP { OP_REG, rSP_reg }
310 #define RMrBP { OP_REG, rBP_reg }
311 #define RMrSI { OP_REG, rSI_reg }
312 #define RMrDI { OP_REG, rDI_reg }
313 #define RMAL { OP_REG, al_reg }
314 #define RMCL { OP_REG, cl_reg }
315 #define RMDL { OP_REG, dl_reg }
316 #define RMBL { OP_REG, bl_reg }
317 #define RMAH { OP_REG, ah_reg }
318 #define RMCH { OP_REG, ch_reg }
319 #define RMDH { OP_REG, dh_reg }
320 #define RMBH { OP_REG, bh_reg }
321 #define RMAX { OP_REG, ax_reg }
322 #define RMDX { OP_REG, dx_reg }
324 #define eAX { OP_IMREG, eAX_reg }
325 #define AL { OP_IMREG, al_reg }
326 #define CL { OP_IMREG, cl_reg }
327 #define zAX { OP_IMREG, z_mode_ax_reg }
328 #define indirDX { OP_IMREG, indir_dx_reg }
330 #define Sw { OP_SEG, w_mode }
331 #define Sv { OP_SEG, v_mode }
332 #define Ap { OP_DIR, 0 }
333 #define Ob { OP_OFF64, b_mode }
334 #define Ov { OP_OFF64, v_mode }
335 #define Xb { OP_DSreg, eSI_reg }
336 #define Xv { OP_DSreg, eSI_reg }
337 #define Xz { OP_DSreg, eSI_reg }
338 #define Yb { OP_ESreg, eDI_reg }
339 #define Yv { OP_ESreg, eDI_reg }
340 #define DSBX { OP_DSreg, eBX_reg }
342 #define es { OP_REG, es_reg }
343 #define ss { OP_REG, ss_reg }
344 #define cs { OP_REG, cs_reg }
345 #define ds { OP_REG, ds_reg }
346 #define fs { OP_REG, fs_reg }
347 #define gs { OP_REG, gs_reg }
349 #define MX { OP_MMX, 0 }
350 #define XM { OP_XMM, 0 }
351 #define XMScalar { OP_XMM, scalar_mode }
352 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
353 #define XMM { OP_XMM, xmm_mode }
354 #define TMM { OP_XMM, tmm_mode }
355 #define XMxmmq { OP_XMM, xmmq_mode }
356 #define EM { OP_EM, v_mode }
357 #define EMS { OP_EM, v_swap_mode }
358 #define EMd { OP_EM, d_mode }
359 #define EMx { OP_EM, x_mode }
360 #define EXbwUnit { OP_EX, bw_unit_mode }
361 #define EXw { OP_EX, w_mode }
362 #define EXd { OP_EX, d_mode }
363 #define EXdS { OP_EX, d_swap_mode }
364 #define EXq { OP_EX, q_mode }
365 #define EXqS { OP_EX, q_swap_mode }
366 #define EXx { OP_EX, x_mode }
367 #define EXxS { OP_EX, x_swap_mode }
368 #define EXxmm { OP_EX, xmm_mode }
369 #define EXymm { OP_EX, ymm_mode }
370 #define EXtmm { OP_EX, tmm_mode }
371 #define EXxmmq { OP_EX, xmmq_mode }
372 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
373 #define EXxmm_mb { OP_EX, xmm_mb_mode }
374 #define EXxmm_mw { OP_EX, xmm_mw_mode }
375 #define EXxmm_md { OP_EX, xmm_md_mode }
376 #define EXxmm_mq { OP_EX, xmm_mq_mode }
377 #define EXxmmdw { OP_EX, xmmdw_mode }
378 #define EXxmmqd { OP_EX, xmmqd_mode }
379 #define EXymmq { OP_EX, ymmq_mode }
380 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
381 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
382 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
383 #define MS { OP_MS, v_mode }
384 #define XS { OP_XS, v_mode }
385 #define EMCq { OP_EMC, q_mode }
386 #define MXC { OP_MXC, 0 }
387 #define OPSUF { OP_3DNowSuffix, 0 }
388 #define SEP { SEP_Fixup, 0 }
389 #define CMP { CMP_Fixup, 0 }
390 #define XMM0 { XMM_Fixup, 0 }
391 #define FXSAVE { FXSAVE_Fixup, 0 }
393 #define Vex { OP_VEX, vex_mode }
394 #define VexW { OP_VexW, vex_mode }
395 #define VexScalar { OP_VEX, vex_scalar_mode }
396 #define VexScalarR { OP_VexR, vex_scalar_mode }
397 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
398 #define VexGdq { OP_VEX, dq_mode }
399 #define VexTmm { OP_VEX, tmm_mode }
400 #define XMVexI4 { OP_REG_VexI4, x_mode }
401 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
402 #define VexI4 { OP_VexI4, 0 }
403 #define PCLMUL { PCLMUL_Fixup, 0 }
404 #define VPCMP { VPCMP_Fixup, 0 }
405 #define VPCOM { VPCOM_Fixup, 0 }
407 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
408 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
409 #define EXxEVexS { OP_Rounding, evex_sae_mode }
411 #define XMask { OP_Mask, mask_mode }
412 #define MaskG { OP_G, mask_mode }
413 #define MaskE { OP_E, mask_mode }
414 #define MaskBDE { OP_E, mask_bd_mode }
415 #define MaskR { OP_R, mask_mode }
416 #define MaskVex { OP_VEX, mask_mode }
418 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
419 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
420 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
421 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
423 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
425 /* Used handle "rep" prefix for string instructions. */
426 #define Xbr { REP_Fixup, eSI_reg }
427 #define Xvr { REP_Fixup, eSI_reg }
428 #define Ybr { REP_Fixup, eDI_reg }
429 #define Yvr { REP_Fixup, eDI_reg }
430 #define Yzr { REP_Fixup, eDI_reg }
431 #define indirDXr { REP_Fixup, indir_dx_reg }
432 #define ALr { REP_Fixup, al_reg }
433 #define eAXr { REP_Fixup, eAX_reg }
435 /* Used handle HLE prefix for lockable instructions. */
436 #define Ebh1 { HLE_Fixup1, b_mode }
437 #define Evh1 { HLE_Fixup1, v_mode }
438 #define Ebh2 { HLE_Fixup2, b_mode }
439 #define Evh2 { HLE_Fixup2, v_mode }
440 #define Ebh3 { HLE_Fixup3, b_mode }
441 #define Evh3 { HLE_Fixup3, v_mode }
443 #define BND { BND_Fixup, 0 }
444 #define NOTRACK { NOTRACK_Fixup, 0 }
446 #define cond_jump_flag { NULL, cond_jump_mode }
447 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
449 /* bits in sizeflag */
450 #define SUFFIX_ALWAYS 4
458 /* byte operand with operand swapped */
460 /* byte operand, sign extend like 'T' suffix */
462 /* operand size depends on prefixes */
464 /* operand size depends on prefixes with operand swapped */
466 /* operand size depends on address prefix */
470 /* double word operand */
472 /* double word operand with operand swapped */
474 /* quad word operand */
476 /* quad word operand with operand swapped */
478 /* ten-byte operand */
480 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
481 broadcast enabled. */
483 /* Similar to x_mode, but with different EVEX mem shifts. */
485 /* Similar to x_mode, but with yet different EVEX mem shifts. */
487 /* Similar to x_mode, but with disabled broadcast. */
489 /* Similar to x_mode, but with operands swapped and disabled broadcast
492 /* 16-byte XMM operand */
494 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
495 memory operand (depending on vector length). Broadcast isn't
498 /* Same as xmmq_mode, but broadcast is allowed. */
499 evex_half_bcst_xmmq_mode
,
500 /* XMM register or byte memory operand */
502 /* XMM register or word memory operand */
504 /* XMM register or double word memory operand */
506 /* XMM register or quad word memory operand */
508 /* 16-byte XMM, word, double word or quad word operand. */
510 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
512 /* 32-byte YMM operand */
514 /* quad word, ymmword or zmmword memory operand. */
516 /* 32-byte YMM or 16-byte word operand */
520 /* d_mode in 32bit, q_mode in 64bit mode. */
522 /* pair of v_mode operands */
528 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
530 /* operand size depends on REX prefixes. */
532 /* registers like dq_mode, memory like w_mode, displacements like
533 v_mode without considering Intel64 ISA. */
537 /* bounds operand with operand swapped */
539 /* 4- or 6-byte pointer operand */
542 /* v_mode for indirect branch opcodes. */
544 /* v_mode for stack-related opcodes. */
546 /* non-quad operand size depends on prefixes */
548 /* 16-byte operand */
550 /* registers like dq_mode, memory like b_mode. */
552 /* registers like d_mode, memory like b_mode. */
554 /* registers like d_mode, memory like w_mode. */
556 /* registers like dq_mode, memory like d_mode. */
558 /* normal vex mode */
561 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
562 vex_vsib_d_w_dq_mode
,
563 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
565 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
566 vex_vsib_q_w_dq_mode
,
567 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
569 /* mandatory non-vector SIB. */
572 /* scalar, ignore vector length. */
574 /* like vex_mode, ignore vector length. */
576 /* Operand size depends on the VEX.W bit, ignore vector length. */
577 vex_scalar_w_dq_mode
,
579 /* Static rounding. */
581 /* Static rounding, 64-bit mode only. */
582 evex_rounding_64_mode
,
583 /* Supress all exceptions. */
586 /* Mask register operand. */
588 /* Mask register operand. */
656 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
658 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
659 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
660 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
661 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
662 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
663 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
664 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
665 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
666 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
667 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
668 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
669 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
670 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
671 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
672 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
673 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
711 REG_VEX_0F3849_X86_64_P_0_W_0_M_1
,
716 REG_0FXOP_09_12_M_1_L_0
,
796 MOD_VEX_0F3849_X86_64_P_0_W_0
,
797 MOD_VEX_0F3849_X86_64_P_2_W_0
,
798 MOD_VEX_0F3849_X86_64_P_3_W_0
,
799 MOD_VEX_0F384B_X86_64_P_1_W_0
,
800 MOD_VEX_0F384B_X86_64_P_2_W_0
,
801 MOD_VEX_0F384B_X86_64_P_3_W_0
,
802 MOD_VEX_0F385C_X86_64_P_1_W_0
,
803 MOD_VEX_0F385E_X86_64_P_0_W_0
,
804 MOD_VEX_0F385E_X86_64_P_1_W_0
,
805 MOD_VEX_0F385E_X86_64_P_2_W_0
,
806 MOD_VEX_0F385E_X86_64_P_3_W_0
,
816 MOD_VEX_0F12_PREFIX_0
,
817 MOD_VEX_0F12_PREFIX_2
,
819 MOD_VEX_0F16_PREFIX_0
,
820 MOD_VEX_0F16_PREFIX_2
,
823 MOD_VEX_W_0_0F41_P_0_LEN_1
,
824 MOD_VEX_W_1_0F41_P_0_LEN_1
,
825 MOD_VEX_W_0_0F41_P_2_LEN_1
,
826 MOD_VEX_W_1_0F41_P_2_LEN_1
,
827 MOD_VEX_W_0_0F42_P_0_LEN_1
,
828 MOD_VEX_W_1_0F42_P_0_LEN_1
,
829 MOD_VEX_W_0_0F42_P_2_LEN_1
,
830 MOD_VEX_W_1_0F42_P_2_LEN_1
,
831 MOD_VEX_W_0_0F44_P_0_LEN_1
,
832 MOD_VEX_W_1_0F44_P_0_LEN_1
,
833 MOD_VEX_W_0_0F44_P_2_LEN_1
,
834 MOD_VEX_W_1_0F44_P_2_LEN_1
,
835 MOD_VEX_W_0_0F45_P_0_LEN_1
,
836 MOD_VEX_W_1_0F45_P_0_LEN_1
,
837 MOD_VEX_W_0_0F45_P_2_LEN_1
,
838 MOD_VEX_W_1_0F45_P_2_LEN_1
,
839 MOD_VEX_W_0_0F46_P_0_LEN_1
,
840 MOD_VEX_W_1_0F46_P_0_LEN_1
,
841 MOD_VEX_W_0_0F46_P_2_LEN_1
,
842 MOD_VEX_W_1_0F46_P_2_LEN_1
,
843 MOD_VEX_W_0_0F47_P_0_LEN_1
,
844 MOD_VEX_W_1_0F47_P_0_LEN_1
,
845 MOD_VEX_W_0_0F47_P_2_LEN_1
,
846 MOD_VEX_W_1_0F47_P_2_LEN_1
,
847 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
848 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
849 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
850 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
851 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
852 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
853 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
865 MOD_VEX_W_0_0F91_P_0_LEN_0
,
866 MOD_VEX_W_1_0F91_P_0_LEN_0
,
867 MOD_VEX_W_0_0F91_P_2_LEN_0
,
868 MOD_VEX_W_1_0F91_P_2_LEN_0
,
869 MOD_VEX_W_0_0F92_P_0_LEN_0
,
870 MOD_VEX_W_0_0F92_P_2_LEN_0
,
871 MOD_VEX_0F92_P_3_LEN_0
,
872 MOD_VEX_W_0_0F93_P_0_LEN_0
,
873 MOD_VEX_W_0_0F93_P_2_LEN_0
,
874 MOD_VEX_0F93_P_3_LEN_0
,
875 MOD_VEX_W_0_0F98_P_0_LEN_0
,
876 MOD_VEX_W_1_0F98_P_0_LEN_0
,
877 MOD_VEX_W_0_0F98_P_2_LEN_0
,
878 MOD_VEX_W_1_0F98_P_2_LEN_0
,
879 MOD_VEX_W_0_0F99_P_0_LEN_0
,
880 MOD_VEX_W_1_0F99_P_0_LEN_0
,
881 MOD_VEX_W_0_0F99_P_2_LEN_0
,
882 MOD_VEX_W_1_0F99_P_2_LEN_0
,
885 MOD_VEX_0FD7_PREFIX_2
,
886 MOD_VEX_0FE7_PREFIX_2
,
887 MOD_VEX_0FF0_PREFIX_3
,
888 MOD_VEX_0F381A_PREFIX_2
,
889 MOD_VEX_0F382A_PREFIX_2
,
890 MOD_VEX_0F382C_PREFIX_2
,
891 MOD_VEX_0F382D_PREFIX_2
,
892 MOD_VEX_0F382E_PREFIX_2
,
893 MOD_VEX_0F382F_PREFIX_2
,
894 MOD_VEX_0F385A_PREFIX_2
,
895 MOD_VEX_0F388C_PREFIX_2
,
896 MOD_VEX_0F388E_PREFIX_2
,
897 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
898 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
899 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
900 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
901 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
902 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
903 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
904 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
908 MOD_EVEX_0F12_PREFIX_0
,
909 MOD_EVEX_0F12_PREFIX_2
,
911 MOD_EVEX_0F16_PREFIX_0
,
912 MOD_EVEX_0F16_PREFIX_2
,
915 MOD_EVEX_0F381A_P_2_W_0
,
916 MOD_EVEX_0F381A_P_2_W_1
,
917 MOD_EVEX_0F381B_P_2_W_0
,
918 MOD_EVEX_0F381B_P_2_W_1
,
919 MOD_EVEX_0F385A_P_2_W_0
,
920 MOD_EVEX_0F385A_P_2_W_1
,
921 MOD_EVEX_0F385B_P_2_W_0
,
922 MOD_EVEX_0F385B_P_2_W_1
,
923 MOD_EVEX_0F38C6_REG_1
,
924 MOD_EVEX_0F38C6_REG_2
,
925 MOD_EVEX_0F38C6_REG_5
,
926 MOD_EVEX_0F38C6_REG_6
,
927 MOD_EVEX_0F38C7_REG_1
,
928 MOD_EVEX_0F38C7_REG_2
,
929 MOD_EVEX_0F38C7_REG_5
,
930 MOD_EVEX_0F38C7_REG_6
943 RM_0F1E_P_1_MOD_3_REG_7
,
944 RM_0FAE_REG_6_MOD_3_P_0
,
946 RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
952 PREFIX_0F01_REG_3_RM_1
,
953 PREFIX_0F01_REG_5_MOD_0
,
954 PREFIX_0F01_REG_5_MOD_3_RM_0
,
955 PREFIX_0F01_REG_5_MOD_3_RM_1
,
956 PREFIX_0F01_REG_5_MOD_3_RM_2
,
957 PREFIX_0F01_REG_7_MOD_3_RM_2
,
958 PREFIX_0F01_REG_7_MOD_3_RM_3
,
1000 PREFIX_0FAE_REG_0_MOD_3
,
1001 PREFIX_0FAE_REG_1_MOD_3
,
1002 PREFIX_0FAE_REG_2_MOD_3
,
1003 PREFIX_0FAE_REG_3_MOD_3
,
1004 PREFIX_0FAE_REG_4_MOD_0
,
1005 PREFIX_0FAE_REG_4_MOD_3
,
1006 PREFIX_0FAE_REG_5_MOD_0
,
1007 PREFIX_0FAE_REG_5_MOD_3
,
1008 PREFIX_0FAE_REG_6_MOD_0
,
1009 PREFIX_0FAE_REG_6_MOD_3
,
1010 PREFIX_0FAE_REG_7_MOD_0
,
1016 PREFIX_0FC7_REG_6_MOD_0
,
1017 PREFIX_0FC7_REG_6_MOD_3
,
1018 PREFIX_0FC7_REG_7_MOD_3
,
1148 PREFIX_VEX_0F71_REG_2
,
1149 PREFIX_VEX_0F71_REG_4
,
1150 PREFIX_VEX_0F71_REG_6
,
1151 PREFIX_VEX_0F72_REG_2
,
1152 PREFIX_VEX_0F72_REG_4
,
1153 PREFIX_VEX_0F72_REG_6
,
1154 PREFIX_VEX_0F73_REG_2
,
1155 PREFIX_VEX_0F73_REG_3
,
1156 PREFIX_VEX_0F73_REG_6
,
1157 PREFIX_VEX_0F73_REG_7
,
1282 PREFIX_VEX_0F3849_X86_64
,
1283 PREFIX_VEX_0F384B_X86_64
,
1287 PREFIX_VEX_0F385C_X86_64
,
1288 PREFIX_VEX_0F385E_X86_64
,
1334 PREFIX_VEX_0F38F3_REG_1
,
1335 PREFIX_VEX_0F38F3_REG_2
,
1336 PREFIX_VEX_0F38F3_REG_3
,
1433 PREFIX_EVEX_0F71_REG_2
,
1434 PREFIX_EVEX_0F71_REG_4
,
1435 PREFIX_EVEX_0F71_REG_6
,
1436 PREFIX_EVEX_0F72_REG_0
,
1437 PREFIX_EVEX_0F72_REG_1
,
1438 PREFIX_EVEX_0F72_REG_2
,
1439 PREFIX_EVEX_0F72_REG_4
,
1440 PREFIX_EVEX_0F72_REG_6
,
1441 PREFIX_EVEX_0F73_REG_2
,
1442 PREFIX_EVEX_0F73_REG_3
,
1443 PREFIX_EVEX_0F73_REG_6
,
1444 PREFIX_EVEX_0F73_REG_7
,
1566 PREFIX_EVEX_0F38C6_REG_1
,
1567 PREFIX_EVEX_0F38C6_REG_2
,
1568 PREFIX_EVEX_0F38C6_REG_5
,
1569 PREFIX_EVEX_0F38C6_REG_6
,
1570 PREFIX_EVEX_0F38C7_REG_1
,
1571 PREFIX_EVEX_0F38C7_REG_2
,
1572 PREFIX_EVEX_0F38C7_REG_5
,
1573 PREFIX_EVEX_0F38C7_REG_6
,
1670 THREE_BYTE_0F38
= 0,
1697 VEX_LEN_0F12_P_0_M_0
= 0,
1698 VEX_LEN_0F12_P_0_M_1
,
1699 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1701 VEX_LEN_0F16_P_0_M_0
,
1702 VEX_LEN_0F16_P_0_M_1
,
1703 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1739 VEX_LEN_0FAE_R_2_M_0
,
1740 VEX_LEN_0FAE_R_3_M_0
,
1747 VEX_LEN_0F381A_P_2_M_0
,
1750 VEX_LEN_0F3849_X86_64_P_0_W_0_M_0
,
1751 VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0
,
1752 VEX_LEN_0F3849_X86_64_P_2_W_0_M_0
,
1753 VEX_LEN_0F3849_X86_64_P_3_W_0_M_0
,
1754 VEX_LEN_0F384B_X86_64_P_1_W_0_M_0
,
1755 VEX_LEN_0F384B_X86_64_P_2_W_0_M_0
,
1756 VEX_LEN_0F384B_X86_64_P_3_W_0_M_0
,
1757 VEX_LEN_0F385A_P_2_M_0
,
1758 VEX_LEN_0F385C_X86_64_P_1_W_0_M_0
,
1759 VEX_LEN_0F385E_X86_64_P_0_W_0_M_0
,
1760 VEX_LEN_0F385E_X86_64_P_1_W_0_M_0
,
1761 VEX_LEN_0F385E_X86_64_P_2_W_0_M_0
,
1762 VEX_LEN_0F385E_X86_64_P_3_W_0_M_0
,
1765 VEX_LEN_0F38F3_R_1_P_0
,
1766 VEX_LEN_0F38F3_R_2_P_0
,
1767 VEX_LEN_0F38F3_R_3_P_0
,
1802 VEX_LEN_0FXOP_08_85
,
1803 VEX_LEN_0FXOP_08_86
,
1804 VEX_LEN_0FXOP_08_87
,
1805 VEX_LEN_0FXOP_08_8E
,
1806 VEX_LEN_0FXOP_08_8F
,
1807 VEX_LEN_0FXOP_08_95
,
1808 VEX_LEN_0FXOP_08_96
,
1809 VEX_LEN_0FXOP_08_97
,
1810 VEX_LEN_0FXOP_08_9E
,
1811 VEX_LEN_0FXOP_08_9F
,
1812 VEX_LEN_0FXOP_08_A3
,
1813 VEX_LEN_0FXOP_08_A6
,
1814 VEX_LEN_0FXOP_08_B6
,
1815 VEX_LEN_0FXOP_08_C0
,
1816 VEX_LEN_0FXOP_08_C1
,
1817 VEX_LEN_0FXOP_08_C2
,
1818 VEX_LEN_0FXOP_08_C3
,
1819 VEX_LEN_0FXOP_08_CC
,
1820 VEX_LEN_0FXOP_08_CD
,
1821 VEX_LEN_0FXOP_08_CE
,
1822 VEX_LEN_0FXOP_08_CF
,
1823 VEX_LEN_0FXOP_08_EC
,
1824 VEX_LEN_0FXOP_08_ED
,
1825 VEX_LEN_0FXOP_08_EE
,
1826 VEX_LEN_0FXOP_08_EF
,
1827 VEX_LEN_0FXOP_09_01
,
1828 VEX_LEN_0FXOP_09_02
,
1829 VEX_LEN_0FXOP_09_12_M_1
,
1830 VEX_LEN_0FXOP_09_82_W_0
,
1831 VEX_LEN_0FXOP_09_83_W_0
,
1832 VEX_LEN_0FXOP_09_90
,
1833 VEX_LEN_0FXOP_09_91
,
1834 VEX_LEN_0FXOP_09_92
,
1835 VEX_LEN_0FXOP_09_93
,
1836 VEX_LEN_0FXOP_09_94
,
1837 VEX_LEN_0FXOP_09_95
,
1838 VEX_LEN_0FXOP_09_96
,
1839 VEX_LEN_0FXOP_09_97
,
1840 VEX_LEN_0FXOP_09_98
,
1841 VEX_LEN_0FXOP_09_99
,
1842 VEX_LEN_0FXOP_09_9A
,
1843 VEX_LEN_0FXOP_09_9B
,
1844 VEX_LEN_0FXOP_09_C1
,
1845 VEX_LEN_0FXOP_09_C2
,
1846 VEX_LEN_0FXOP_09_C3
,
1847 VEX_LEN_0FXOP_09_C6
,
1848 VEX_LEN_0FXOP_09_C7
,
1849 VEX_LEN_0FXOP_09_CB
,
1850 VEX_LEN_0FXOP_09_D1
,
1851 VEX_LEN_0FXOP_09_D2
,
1852 VEX_LEN_0FXOP_09_D3
,
1853 VEX_LEN_0FXOP_09_D6
,
1854 VEX_LEN_0FXOP_09_D7
,
1855 VEX_LEN_0FXOP_09_DB
,
1856 VEX_LEN_0FXOP_09_E1
,
1857 VEX_LEN_0FXOP_09_E2
,
1858 VEX_LEN_0FXOP_09_E3
,
1859 VEX_LEN_0FXOP_0A_12
,
1864 EVEX_LEN_0F6E_P_2
= 0,
1870 EVEX_LEN_0F3816_P_2
,
1871 EVEX_LEN_0F3819_P_2_W_0
,
1872 EVEX_LEN_0F3819_P_2_W_1
,
1873 EVEX_LEN_0F381A_P_2_W_0_M_0
,
1874 EVEX_LEN_0F381A_P_2_W_1_M_0
,
1875 EVEX_LEN_0F381B_P_2_W_0_M_0
,
1876 EVEX_LEN_0F381B_P_2_W_1_M_0
,
1877 EVEX_LEN_0F3836_P_2
,
1878 EVEX_LEN_0F385A_P_2_W_0_M_0
,
1879 EVEX_LEN_0F385A_P_2_W_1_M_0
,
1880 EVEX_LEN_0F385B_P_2_W_0_M_0
,
1881 EVEX_LEN_0F385B_P_2_W_1_M_0
,
1882 EVEX_LEN_0F38C6_REG_1_PREFIX_2
,
1883 EVEX_LEN_0F38C6_REG_2_PREFIX_2
,
1884 EVEX_LEN_0F38C6_REG_5_PREFIX_2
,
1885 EVEX_LEN_0F38C6_REG_6_PREFIX_2
,
1886 EVEX_LEN_0F38C7_R_1_P_2_W_0
,
1887 EVEX_LEN_0F38C7_R_1_P_2_W_1
,
1888 EVEX_LEN_0F38C7_R_2_P_2_W_0
,
1889 EVEX_LEN_0F38C7_R_2_P_2_W_1
,
1890 EVEX_LEN_0F38C7_R_5_P_2_W_0
,
1891 EVEX_LEN_0F38C7_R_5_P_2_W_1
,
1892 EVEX_LEN_0F38C7_R_6_P_2_W_0
,
1893 EVEX_LEN_0F38C7_R_6_P_2_W_1
,
1894 EVEX_LEN_0F3A00_P_2_W_1
,
1895 EVEX_LEN_0F3A01_P_2_W_1
,
1896 EVEX_LEN_0F3A14_P_2
,
1897 EVEX_LEN_0F3A15_P_2
,
1898 EVEX_LEN_0F3A16_P_2
,
1899 EVEX_LEN_0F3A17_P_2
,
1900 EVEX_LEN_0F3A18_P_2_W_0
,
1901 EVEX_LEN_0F3A18_P_2_W_1
,
1902 EVEX_LEN_0F3A19_P_2_W_0
,
1903 EVEX_LEN_0F3A19_P_2_W_1
,
1904 EVEX_LEN_0F3A1A_P_2_W_0
,
1905 EVEX_LEN_0F3A1A_P_2_W_1
,
1906 EVEX_LEN_0F3A1B_P_2_W_0
,
1907 EVEX_LEN_0F3A1B_P_2_W_1
,
1908 EVEX_LEN_0F3A20_P_2
,
1909 EVEX_LEN_0F3A21_P_2_W_0
,
1910 EVEX_LEN_0F3A22_P_2
,
1911 EVEX_LEN_0F3A23_P_2_W_0
,
1912 EVEX_LEN_0F3A23_P_2_W_1
,
1913 EVEX_LEN_0F3A38_P_2_W_0
,
1914 EVEX_LEN_0F3A38_P_2_W_1
,
1915 EVEX_LEN_0F3A39_P_2_W_0
,
1916 EVEX_LEN_0F3A39_P_2_W_1
,
1917 EVEX_LEN_0F3A3A_P_2_W_0
,
1918 EVEX_LEN_0F3A3A_P_2_W_1
,
1919 EVEX_LEN_0F3A3B_P_2_W_0
,
1920 EVEX_LEN_0F3A3B_P_2_W_1
,
1921 EVEX_LEN_0F3A43_P_2_W_0
,
1922 EVEX_LEN_0F3A43_P_2_W_1
1927 VEX_W_0F41_P_0_LEN_1
= 0,
1928 VEX_W_0F41_P_2_LEN_1
,
1929 VEX_W_0F42_P_0_LEN_1
,
1930 VEX_W_0F42_P_2_LEN_1
,
1931 VEX_W_0F44_P_0_LEN_0
,
1932 VEX_W_0F44_P_2_LEN_0
,
1933 VEX_W_0F45_P_0_LEN_1
,
1934 VEX_W_0F45_P_2_LEN_1
,
1935 VEX_W_0F46_P_0_LEN_1
,
1936 VEX_W_0F46_P_2_LEN_1
,
1937 VEX_W_0F47_P_0_LEN_1
,
1938 VEX_W_0F47_P_2_LEN_1
,
1939 VEX_W_0F4A_P_0_LEN_1
,
1940 VEX_W_0F4A_P_2_LEN_1
,
1941 VEX_W_0F4B_P_0_LEN_1
,
1942 VEX_W_0F4B_P_2_LEN_1
,
1943 VEX_W_0F90_P_0_LEN_0
,
1944 VEX_W_0F90_P_2_LEN_0
,
1945 VEX_W_0F91_P_0_LEN_0
,
1946 VEX_W_0F91_P_2_LEN_0
,
1947 VEX_W_0F92_P_0_LEN_0
,
1948 VEX_W_0F92_P_2_LEN_0
,
1949 VEX_W_0F93_P_0_LEN_0
,
1950 VEX_W_0F93_P_2_LEN_0
,
1951 VEX_W_0F98_P_0_LEN_0
,
1952 VEX_W_0F98_P_2_LEN_0
,
1953 VEX_W_0F99_P_0_LEN_0
,
1954 VEX_W_0F99_P_2_LEN_0
,
1963 VEX_W_0F381A_P_2_M_0_L_0
,
1964 VEX_W_0F382C_P_2_M_0
,
1965 VEX_W_0F382D_P_2_M_0
,
1966 VEX_W_0F382E_P_2_M_0
,
1967 VEX_W_0F382F_P_2_M_0
,
1970 VEX_W_0F3849_X86_64_P_0
,
1971 VEX_W_0F3849_X86_64_P_2
,
1972 VEX_W_0F3849_X86_64_P_3
,
1973 VEX_W_0F384B_X86_64_P_1
,
1974 VEX_W_0F384B_X86_64_P_2
,
1975 VEX_W_0F384B_X86_64_P_3
,
1978 VEX_W_0F385A_P_2_M_0_L_0
,
1979 VEX_W_0F385C_X86_64_P_1
,
1980 VEX_W_0F385E_X86_64_P_0
,
1981 VEX_W_0F385E_X86_64_P_1
,
1982 VEX_W_0F385E_X86_64_P_2
,
1983 VEX_W_0F385E_X86_64_P_3
,
1992 VEX_W_0F3A06_P_2_L_0
,
1993 VEX_W_0F3A18_P_2_L_0
,
1994 VEX_W_0F3A19_P_2_L_0
,
1996 VEX_W_0F3A30_P_2_LEN_0
,
1997 VEX_W_0F3A31_P_2_LEN_0
,
1998 VEX_W_0F3A32_P_2_LEN_0
,
1999 VEX_W_0F3A33_P_2_LEN_0
,
2000 VEX_W_0F3A38_P_2_L_0
,
2001 VEX_W_0F3A39_P_2_L_0
,
2002 VEX_W_0F3A46_P_2_L_0
,
2009 VEX_W_0FXOP_08_85_L_0
,
2010 VEX_W_0FXOP_08_86_L_0
,
2011 VEX_W_0FXOP_08_87_L_0
,
2012 VEX_W_0FXOP_08_8E_L_0
,
2013 VEX_W_0FXOP_08_8F_L_0
,
2014 VEX_W_0FXOP_08_95_L_0
,
2015 VEX_W_0FXOP_08_96_L_0
,
2016 VEX_W_0FXOP_08_97_L_0
,
2017 VEX_W_0FXOP_08_9E_L_0
,
2018 VEX_W_0FXOP_08_9F_L_0
,
2019 VEX_W_0FXOP_08_A6_L_0
,
2020 VEX_W_0FXOP_08_B6_L_0
,
2021 VEX_W_0FXOP_08_C0_L_0
,
2022 VEX_W_0FXOP_08_C1_L_0
,
2023 VEX_W_0FXOP_08_C2_L_0
,
2024 VEX_W_0FXOP_08_C3_L_0
,
2025 VEX_W_0FXOP_08_CC_L_0
,
2026 VEX_W_0FXOP_08_CD_L_0
,
2027 VEX_W_0FXOP_08_CE_L_0
,
2028 VEX_W_0FXOP_08_CF_L_0
,
2029 VEX_W_0FXOP_08_EC_L_0
,
2030 VEX_W_0FXOP_08_ED_L_0
,
2031 VEX_W_0FXOP_08_EE_L_0
,
2032 VEX_W_0FXOP_08_EF_L_0
,
2038 VEX_W_0FXOP_09_C1_L_0
,
2039 VEX_W_0FXOP_09_C2_L_0
,
2040 VEX_W_0FXOP_09_C3_L_0
,
2041 VEX_W_0FXOP_09_C6_L_0
,
2042 VEX_W_0FXOP_09_C7_L_0
,
2043 VEX_W_0FXOP_09_CB_L_0
,
2044 VEX_W_0FXOP_09_D1_L_0
,
2045 VEX_W_0FXOP_09_D2_L_0
,
2046 VEX_W_0FXOP_09_D3_L_0
,
2047 VEX_W_0FXOP_09_D6_L_0
,
2048 VEX_W_0FXOP_09_D7_L_0
,
2049 VEX_W_0FXOP_09_DB_L_0
,
2050 VEX_W_0FXOP_09_E1_L_0
,
2051 VEX_W_0FXOP_09_E2_L_0
,
2052 VEX_W_0FXOP_09_E3_L_0
,
2058 EVEX_W_0F12_P_0_M_1
,
2061 EVEX_W_0F16_P_0_M_1
,
2095 EVEX_W_0F72_R_2_P_2
,
2096 EVEX_W_0F72_R_6_P_2
,
2097 EVEX_W_0F73_R_2_P_2
,
2098 EVEX_W_0F73_R_6_P_2
,
2181 EVEX_W_0F38C7_R_1_P_2
,
2182 EVEX_W_0F38C7_R_2_P_2
,
2183 EVEX_W_0F38C7_R_5_P_2
,
2184 EVEX_W_0F38C7_R_6_P_2
,
2209 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2218 unsigned int prefix_requirement
;
2221 /* Upper case letters in the instruction names here are macros.
2222 'A' => print 'b' if no register operands or suffix_always is true
2223 'B' => print 'b' if suffix_always is true
2224 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2226 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2227 suffix_always is true
2228 'E' => print 'e' if 32-bit form of jcxz
2229 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2230 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2231 'H' => print ",pt" or ",pn" branch hint
2234 'K' => print 'd' or 'q' if rex prefix is present.
2235 'L' => print 'l' if suffix_always is true
2236 'M' => print 'r' if intel_mnemonic is false.
2237 'N' => print 'n' if instruction has no wait "prefix"
2238 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2239 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2240 or suffix_always is true. print 'q' if rex prefix is present.
2241 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2243 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2244 'S' => print 'w', 'l' or 'q' if suffix_always is true
2245 'T' => print 'q' in 64bit mode if instruction has no operand size
2246 prefix and behave as 'P' otherwise
2247 'U' => print 'q' in 64bit mode if instruction has no operand size
2248 prefix and behave as 'Q' otherwise
2249 'V' => print 'q' in 64bit mode if instruction has no operand size
2250 prefix and behave as 'S' otherwise
2251 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2252 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2254 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2255 '!' => change condition from true to false or from false to true.
2256 '%' => add 1 upper case letter to the macro.
2257 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
2258 prefix or suffix_always is true (lcall/ljmp).
2259 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2260 on operand size prefix.
2261 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2262 has no operand size prefix for AMD64 ISA, behave as 'P'
2265 2 upper case letter macros:
2266 "XY" => print 'x' or 'y' if suffix_always is true or no register
2267 operands and no broadcast.
2268 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2269 register operands and no broadcast.
2270 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2271 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
2272 being false, or no operand at all in 64bit mode, or if suffix_always
2274 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2275 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2276 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2277 "DQ" => print 'd' or 'q' depending on the VEX.W bit
2278 "BW" => print 'b' or 'w' depending on the EVEX.W bit
2279 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2280 an operand size prefix, or suffix_always is true. print
2281 'q' if rex prefix is present.
2283 Many of the above letters print nothing in Intel mode. See "putop"
2286 Braces '{' and '}', and vertical bars '|', indicate alternative
2287 mnemonic strings for AT&T and Intel. */
2289 static const struct dis386 dis386
[] = {
2291 { "addB", { Ebh1
, Gb
}, 0 },
2292 { "addS", { Evh1
, Gv
}, 0 },
2293 { "addB", { Gb
, EbS
}, 0 },
2294 { "addS", { Gv
, EvS
}, 0 },
2295 { "addB", { AL
, Ib
}, 0 },
2296 { "addS", { eAX
, Iv
}, 0 },
2297 { X86_64_TABLE (X86_64_06
) },
2298 { X86_64_TABLE (X86_64_07
) },
2300 { "orB", { Ebh1
, Gb
}, 0 },
2301 { "orS", { Evh1
, Gv
}, 0 },
2302 { "orB", { Gb
, EbS
}, 0 },
2303 { "orS", { Gv
, EvS
}, 0 },
2304 { "orB", { AL
, Ib
}, 0 },
2305 { "orS", { eAX
, Iv
}, 0 },
2306 { X86_64_TABLE (X86_64_0E
) },
2307 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2309 { "adcB", { Ebh1
, Gb
}, 0 },
2310 { "adcS", { Evh1
, Gv
}, 0 },
2311 { "adcB", { Gb
, EbS
}, 0 },
2312 { "adcS", { Gv
, EvS
}, 0 },
2313 { "adcB", { AL
, Ib
}, 0 },
2314 { "adcS", { eAX
, Iv
}, 0 },
2315 { X86_64_TABLE (X86_64_16
) },
2316 { X86_64_TABLE (X86_64_17
) },
2318 { "sbbB", { Ebh1
, Gb
}, 0 },
2319 { "sbbS", { Evh1
, Gv
}, 0 },
2320 { "sbbB", { Gb
, EbS
}, 0 },
2321 { "sbbS", { Gv
, EvS
}, 0 },
2322 { "sbbB", { AL
, Ib
}, 0 },
2323 { "sbbS", { eAX
, Iv
}, 0 },
2324 { X86_64_TABLE (X86_64_1E
) },
2325 { X86_64_TABLE (X86_64_1F
) },
2327 { "andB", { Ebh1
, Gb
}, 0 },
2328 { "andS", { Evh1
, Gv
}, 0 },
2329 { "andB", { Gb
, EbS
}, 0 },
2330 { "andS", { Gv
, EvS
}, 0 },
2331 { "andB", { AL
, Ib
}, 0 },
2332 { "andS", { eAX
, Iv
}, 0 },
2333 { Bad_Opcode
}, /* SEG ES prefix */
2334 { X86_64_TABLE (X86_64_27
) },
2336 { "subB", { Ebh1
, Gb
}, 0 },
2337 { "subS", { Evh1
, Gv
}, 0 },
2338 { "subB", { Gb
, EbS
}, 0 },
2339 { "subS", { Gv
, EvS
}, 0 },
2340 { "subB", { AL
, Ib
}, 0 },
2341 { "subS", { eAX
, Iv
}, 0 },
2342 { Bad_Opcode
}, /* SEG CS prefix */
2343 { X86_64_TABLE (X86_64_2F
) },
2345 { "xorB", { Ebh1
, Gb
}, 0 },
2346 { "xorS", { Evh1
, Gv
}, 0 },
2347 { "xorB", { Gb
, EbS
}, 0 },
2348 { "xorS", { Gv
, EvS
}, 0 },
2349 { "xorB", { AL
, Ib
}, 0 },
2350 { "xorS", { eAX
, Iv
}, 0 },
2351 { Bad_Opcode
}, /* SEG SS prefix */
2352 { X86_64_TABLE (X86_64_37
) },
2354 { "cmpB", { Eb
, Gb
}, 0 },
2355 { "cmpS", { Ev
, Gv
}, 0 },
2356 { "cmpB", { Gb
, EbS
}, 0 },
2357 { "cmpS", { Gv
, EvS
}, 0 },
2358 { "cmpB", { AL
, Ib
}, 0 },
2359 { "cmpS", { eAX
, Iv
}, 0 },
2360 { Bad_Opcode
}, /* SEG DS prefix */
2361 { X86_64_TABLE (X86_64_3F
) },
2363 { "inc{S|}", { RMeAX
}, 0 },
2364 { "inc{S|}", { RMeCX
}, 0 },
2365 { "inc{S|}", { RMeDX
}, 0 },
2366 { "inc{S|}", { RMeBX
}, 0 },
2367 { "inc{S|}", { RMeSP
}, 0 },
2368 { "inc{S|}", { RMeBP
}, 0 },
2369 { "inc{S|}", { RMeSI
}, 0 },
2370 { "inc{S|}", { RMeDI
}, 0 },
2372 { "dec{S|}", { RMeAX
}, 0 },
2373 { "dec{S|}", { RMeCX
}, 0 },
2374 { "dec{S|}", { RMeDX
}, 0 },
2375 { "dec{S|}", { RMeBX
}, 0 },
2376 { "dec{S|}", { RMeSP
}, 0 },
2377 { "dec{S|}", { RMeBP
}, 0 },
2378 { "dec{S|}", { RMeSI
}, 0 },
2379 { "dec{S|}", { RMeDI
}, 0 },
2381 { "pushV", { RMrAX
}, 0 },
2382 { "pushV", { RMrCX
}, 0 },
2383 { "pushV", { RMrDX
}, 0 },
2384 { "pushV", { RMrBX
}, 0 },
2385 { "pushV", { RMrSP
}, 0 },
2386 { "pushV", { RMrBP
}, 0 },
2387 { "pushV", { RMrSI
}, 0 },
2388 { "pushV", { RMrDI
}, 0 },
2390 { "popV", { RMrAX
}, 0 },
2391 { "popV", { RMrCX
}, 0 },
2392 { "popV", { RMrDX
}, 0 },
2393 { "popV", { RMrBX
}, 0 },
2394 { "popV", { RMrSP
}, 0 },
2395 { "popV", { RMrBP
}, 0 },
2396 { "popV", { RMrSI
}, 0 },
2397 { "popV", { RMrDI
}, 0 },
2399 { X86_64_TABLE (X86_64_60
) },
2400 { X86_64_TABLE (X86_64_61
) },
2401 { X86_64_TABLE (X86_64_62
) },
2402 { X86_64_TABLE (X86_64_63
) },
2403 { Bad_Opcode
}, /* seg fs */
2404 { Bad_Opcode
}, /* seg gs */
2405 { Bad_Opcode
}, /* op size prefix */
2406 { Bad_Opcode
}, /* adr size prefix */
2408 { "pushT", { sIv
}, 0 },
2409 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2410 { "pushT", { sIbT
}, 0 },
2411 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2412 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2413 { X86_64_TABLE (X86_64_6D
) },
2414 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2415 { X86_64_TABLE (X86_64_6F
) },
2417 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2418 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2419 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2420 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2421 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2422 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2423 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2424 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2426 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2427 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2428 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2429 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2430 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2431 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2432 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2433 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2435 { REG_TABLE (REG_80
) },
2436 { REG_TABLE (REG_81
) },
2437 { X86_64_TABLE (X86_64_82
) },
2438 { REG_TABLE (REG_83
) },
2439 { "testB", { Eb
, Gb
}, 0 },
2440 { "testS", { Ev
, Gv
}, 0 },
2441 { "xchgB", { Ebh2
, Gb
}, 0 },
2442 { "xchgS", { Evh2
, Gv
}, 0 },
2444 { "movB", { Ebh3
, Gb
}, 0 },
2445 { "movS", { Evh3
, Gv
}, 0 },
2446 { "movB", { Gb
, EbS
}, 0 },
2447 { "movS", { Gv
, EvS
}, 0 },
2448 { "movD", { Sv
, Sw
}, 0 },
2449 { MOD_TABLE (MOD_8D
) },
2450 { "movD", { Sw
, Sv
}, 0 },
2451 { REG_TABLE (REG_8F
) },
2453 { PREFIX_TABLE (PREFIX_90
) },
2454 { "xchgS", { RMeCX
, eAX
}, 0 },
2455 { "xchgS", { RMeDX
, eAX
}, 0 },
2456 { "xchgS", { RMeBX
, eAX
}, 0 },
2457 { "xchgS", { RMeSP
, eAX
}, 0 },
2458 { "xchgS", { RMeBP
, eAX
}, 0 },
2459 { "xchgS", { RMeSI
, eAX
}, 0 },
2460 { "xchgS", { RMeDI
, eAX
}, 0 },
2462 { "cW{t|}R", { XX
}, 0 },
2463 { "cR{t|}O", { XX
}, 0 },
2464 { X86_64_TABLE (X86_64_9A
) },
2465 { Bad_Opcode
}, /* fwait */
2466 { "pushfT", { XX
}, 0 },
2467 { "popfT", { XX
}, 0 },
2468 { "sahf", { XX
}, 0 },
2469 { "lahf", { XX
}, 0 },
2471 { "mov%LB", { AL
, Ob
}, 0 },
2472 { "mov%LS", { eAX
, Ov
}, 0 },
2473 { "mov%LB", { Ob
, AL
}, 0 },
2474 { "mov%LS", { Ov
, eAX
}, 0 },
2475 { "movs{b|}", { Ybr
, Xb
}, 0 },
2476 { "movs{R|}", { Yvr
, Xv
}, 0 },
2477 { "cmps{b|}", { Xb
, Yb
}, 0 },
2478 { "cmps{R|}", { Xv
, Yv
}, 0 },
2480 { "testB", { AL
, Ib
}, 0 },
2481 { "testS", { eAX
, Iv
}, 0 },
2482 { "stosB", { Ybr
, AL
}, 0 },
2483 { "stosS", { Yvr
, eAX
}, 0 },
2484 { "lodsB", { ALr
, Xb
}, 0 },
2485 { "lodsS", { eAXr
, Xv
}, 0 },
2486 { "scasB", { AL
, Yb
}, 0 },
2487 { "scasS", { eAX
, Yv
}, 0 },
2489 { "movB", { RMAL
, Ib
}, 0 },
2490 { "movB", { RMCL
, Ib
}, 0 },
2491 { "movB", { RMDL
, Ib
}, 0 },
2492 { "movB", { RMBL
, Ib
}, 0 },
2493 { "movB", { RMAH
, Ib
}, 0 },
2494 { "movB", { RMCH
, Ib
}, 0 },
2495 { "movB", { RMDH
, Ib
}, 0 },
2496 { "movB", { RMBH
, Ib
}, 0 },
2498 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2499 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2500 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2501 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2502 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2503 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2504 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2505 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2507 { REG_TABLE (REG_C0
) },
2508 { REG_TABLE (REG_C1
) },
2509 { X86_64_TABLE (X86_64_C2
) },
2510 { X86_64_TABLE (X86_64_C3
) },
2511 { X86_64_TABLE (X86_64_C4
) },
2512 { X86_64_TABLE (X86_64_C5
) },
2513 { REG_TABLE (REG_C6
) },
2514 { REG_TABLE (REG_C7
) },
2516 { "enterT", { Iw
, Ib
}, 0 },
2517 { "leaveT", { XX
}, 0 },
2518 { "{l|}ret{|f}P", { Iw
}, 0 },
2519 { "{l|}ret{|f}P", { XX
}, 0 },
2520 { "int3", { XX
}, 0 },
2521 { "int", { Ib
}, 0 },
2522 { X86_64_TABLE (X86_64_CE
) },
2523 { "iret%LP", { XX
}, 0 },
2525 { REG_TABLE (REG_D0
) },
2526 { REG_TABLE (REG_D1
) },
2527 { REG_TABLE (REG_D2
) },
2528 { REG_TABLE (REG_D3
) },
2529 { X86_64_TABLE (X86_64_D4
) },
2530 { X86_64_TABLE (X86_64_D5
) },
2532 { "xlat", { DSBX
}, 0 },
2543 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2544 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2545 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2546 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2547 { "inB", { AL
, Ib
}, 0 },
2548 { "inG", { zAX
, Ib
}, 0 },
2549 { "outB", { Ib
, AL
}, 0 },
2550 { "outG", { Ib
, zAX
}, 0 },
2552 { X86_64_TABLE (X86_64_E8
) },
2553 { X86_64_TABLE (X86_64_E9
) },
2554 { X86_64_TABLE (X86_64_EA
) },
2555 { "jmp", { Jb
, BND
}, 0 },
2556 { "inB", { AL
, indirDX
}, 0 },
2557 { "inG", { zAX
, indirDX
}, 0 },
2558 { "outB", { indirDX
, AL
}, 0 },
2559 { "outG", { indirDX
, zAX
}, 0 },
2561 { Bad_Opcode
}, /* lock prefix */
2562 { "icebp", { XX
}, 0 },
2563 { Bad_Opcode
}, /* repne */
2564 { Bad_Opcode
}, /* repz */
2565 { "hlt", { XX
}, 0 },
2566 { "cmc", { XX
}, 0 },
2567 { REG_TABLE (REG_F6
) },
2568 { REG_TABLE (REG_F7
) },
2570 { "clc", { XX
}, 0 },
2571 { "stc", { XX
}, 0 },
2572 { "cli", { XX
}, 0 },
2573 { "sti", { XX
}, 0 },
2574 { "cld", { XX
}, 0 },
2575 { "std", { XX
}, 0 },
2576 { REG_TABLE (REG_FE
) },
2577 { REG_TABLE (REG_FF
) },
2580 static const struct dis386 dis386_twobyte
[] = {
2582 { REG_TABLE (REG_0F00
) },
2583 { REG_TABLE (REG_0F01
) },
2584 { "larS", { Gv
, Ew
}, 0 },
2585 { "lslS", { Gv
, Ew
}, 0 },
2587 { "syscall", { XX
}, 0 },
2588 { "clts", { XX
}, 0 },
2589 { "sysret%LQ", { XX
}, 0 },
2591 { "invd", { XX
}, 0 },
2592 { PREFIX_TABLE (PREFIX_0F09
) },
2594 { "ud2", { XX
}, 0 },
2596 { REG_TABLE (REG_0F0D
) },
2597 { "femms", { XX
}, 0 },
2598 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2600 { PREFIX_TABLE (PREFIX_0F10
) },
2601 { PREFIX_TABLE (PREFIX_0F11
) },
2602 { PREFIX_TABLE (PREFIX_0F12
) },
2603 { MOD_TABLE (MOD_0F13
) },
2604 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2605 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2606 { PREFIX_TABLE (PREFIX_0F16
) },
2607 { MOD_TABLE (MOD_0F17
) },
2609 { REG_TABLE (REG_0F18
) },
2610 { "nopQ", { Ev
}, 0 },
2611 { PREFIX_TABLE (PREFIX_0F1A
) },
2612 { PREFIX_TABLE (PREFIX_0F1B
) },
2613 { PREFIX_TABLE (PREFIX_0F1C
) },
2614 { "nopQ", { Ev
}, 0 },
2615 { PREFIX_TABLE (PREFIX_0F1E
) },
2616 { "nopQ", { Ev
}, 0 },
2618 { "movZ", { Rm
, Cm
}, 0 },
2619 { "movZ", { Rm
, Dm
}, 0 },
2620 { "movZ", { Cm
, Rm
}, 0 },
2621 { "movZ", { Dm
, Rm
}, 0 },
2622 { MOD_TABLE (MOD_0F24
) },
2624 { MOD_TABLE (MOD_0F26
) },
2627 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2628 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2629 { PREFIX_TABLE (PREFIX_0F2A
) },
2630 { PREFIX_TABLE (PREFIX_0F2B
) },
2631 { PREFIX_TABLE (PREFIX_0F2C
) },
2632 { PREFIX_TABLE (PREFIX_0F2D
) },
2633 { PREFIX_TABLE (PREFIX_0F2E
) },
2634 { PREFIX_TABLE (PREFIX_0F2F
) },
2636 { "wrmsr", { XX
}, 0 },
2637 { "rdtsc", { XX
}, 0 },
2638 { "rdmsr", { XX
}, 0 },
2639 { "rdpmc", { XX
}, 0 },
2640 { "sysenter", { SEP
}, 0 },
2641 { "sysexit", { SEP
}, 0 },
2643 { "getsec", { XX
}, 0 },
2645 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2647 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2654 { "cmovoS", { Gv
, Ev
}, 0 },
2655 { "cmovnoS", { Gv
, Ev
}, 0 },
2656 { "cmovbS", { Gv
, Ev
}, 0 },
2657 { "cmovaeS", { Gv
, Ev
}, 0 },
2658 { "cmoveS", { Gv
, Ev
}, 0 },
2659 { "cmovneS", { Gv
, Ev
}, 0 },
2660 { "cmovbeS", { Gv
, Ev
}, 0 },
2661 { "cmovaS", { Gv
, Ev
}, 0 },
2663 { "cmovsS", { Gv
, Ev
}, 0 },
2664 { "cmovnsS", { Gv
, Ev
}, 0 },
2665 { "cmovpS", { Gv
, Ev
}, 0 },
2666 { "cmovnpS", { Gv
, Ev
}, 0 },
2667 { "cmovlS", { Gv
, Ev
}, 0 },
2668 { "cmovgeS", { Gv
, Ev
}, 0 },
2669 { "cmovleS", { Gv
, Ev
}, 0 },
2670 { "cmovgS", { Gv
, Ev
}, 0 },
2672 { MOD_TABLE (MOD_0F50
) },
2673 { PREFIX_TABLE (PREFIX_0F51
) },
2674 { PREFIX_TABLE (PREFIX_0F52
) },
2675 { PREFIX_TABLE (PREFIX_0F53
) },
2676 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2677 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2678 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2679 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2681 { PREFIX_TABLE (PREFIX_0F58
) },
2682 { PREFIX_TABLE (PREFIX_0F59
) },
2683 { PREFIX_TABLE (PREFIX_0F5A
) },
2684 { PREFIX_TABLE (PREFIX_0F5B
) },
2685 { PREFIX_TABLE (PREFIX_0F5C
) },
2686 { PREFIX_TABLE (PREFIX_0F5D
) },
2687 { PREFIX_TABLE (PREFIX_0F5E
) },
2688 { PREFIX_TABLE (PREFIX_0F5F
) },
2690 { PREFIX_TABLE (PREFIX_0F60
) },
2691 { PREFIX_TABLE (PREFIX_0F61
) },
2692 { PREFIX_TABLE (PREFIX_0F62
) },
2693 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2694 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2695 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2696 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2697 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2699 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2700 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2701 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2702 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2703 { PREFIX_TABLE (PREFIX_0F6C
) },
2704 { PREFIX_TABLE (PREFIX_0F6D
) },
2705 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2706 { PREFIX_TABLE (PREFIX_0F6F
) },
2708 { PREFIX_TABLE (PREFIX_0F70
) },
2709 { REG_TABLE (REG_0F71
) },
2710 { REG_TABLE (REG_0F72
) },
2711 { REG_TABLE (REG_0F73
) },
2712 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2713 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2714 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2715 { "emms", { XX
}, PREFIX_OPCODE
},
2717 { PREFIX_TABLE (PREFIX_0F78
) },
2718 { PREFIX_TABLE (PREFIX_0F79
) },
2721 { PREFIX_TABLE (PREFIX_0F7C
) },
2722 { PREFIX_TABLE (PREFIX_0F7D
) },
2723 { PREFIX_TABLE (PREFIX_0F7E
) },
2724 { PREFIX_TABLE (PREFIX_0F7F
) },
2726 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2727 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2728 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2729 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2730 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2731 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2732 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2733 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2735 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2736 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2737 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2738 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2739 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2740 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2741 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2742 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2744 { "seto", { Eb
}, 0 },
2745 { "setno", { Eb
}, 0 },
2746 { "setb", { Eb
}, 0 },
2747 { "setae", { Eb
}, 0 },
2748 { "sete", { Eb
}, 0 },
2749 { "setne", { Eb
}, 0 },
2750 { "setbe", { Eb
}, 0 },
2751 { "seta", { Eb
}, 0 },
2753 { "sets", { Eb
}, 0 },
2754 { "setns", { Eb
}, 0 },
2755 { "setp", { Eb
}, 0 },
2756 { "setnp", { Eb
}, 0 },
2757 { "setl", { Eb
}, 0 },
2758 { "setge", { Eb
}, 0 },
2759 { "setle", { Eb
}, 0 },
2760 { "setg", { Eb
}, 0 },
2762 { "pushT", { fs
}, 0 },
2763 { "popT", { fs
}, 0 },
2764 { "cpuid", { XX
}, 0 },
2765 { "btS", { Ev
, Gv
}, 0 },
2766 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2767 { "shldS", { Ev
, Gv
, CL
}, 0 },
2768 { REG_TABLE (REG_0FA6
) },
2769 { REG_TABLE (REG_0FA7
) },
2771 { "pushT", { gs
}, 0 },
2772 { "popT", { gs
}, 0 },
2773 { "rsm", { XX
}, 0 },
2774 { "btsS", { Evh1
, Gv
}, 0 },
2775 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2776 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2777 { REG_TABLE (REG_0FAE
) },
2778 { "imulS", { Gv
, Ev
}, 0 },
2780 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2781 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2782 { MOD_TABLE (MOD_0FB2
) },
2783 { "btrS", { Evh1
, Gv
}, 0 },
2784 { MOD_TABLE (MOD_0FB4
) },
2785 { MOD_TABLE (MOD_0FB5
) },
2786 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2787 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2789 { PREFIX_TABLE (PREFIX_0FB8
) },
2790 { "ud1S", { Gv
, Ev
}, 0 },
2791 { REG_TABLE (REG_0FBA
) },
2792 { "btcS", { Evh1
, Gv
}, 0 },
2793 { PREFIX_TABLE (PREFIX_0FBC
) },
2794 { PREFIX_TABLE (PREFIX_0FBD
) },
2795 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2796 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2798 { "xaddB", { Ebh1
, Gb
}, 0 },
2799 { "xaddS", { Evh1
, Gv
}, 0 },
2800 { PREFIX_TABLE (PREFIX_0FC2
) },
2801 { MOD_TABLE (MOD_0FC3
) },
2802 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
2803 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
2804 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2805 { REG_TABLE (REG_0FC7
) },
2807 { "bswap", { RMeAX
}, 0 },
2808 { "bswap", { RMeCX
}, 0 },
2809 { "bswap", { RMeDX
}, 0 },
2810 { "bswap", { RMeBX
}, 0 },
2811 { "bswap", { RMeSP
}, 0 },
2812 { "bswap", { RMeBP
}, 0 },
2813 { "bswap", { RMeSI
}, 0 },
2814 { "bswap", { RMeDI
}, 0 },
2816 { PREFIX_TABLE (PREFIX_0FD0
) },
2817 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2818 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2819 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2820 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2821 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2822 { PREFIX_TABLE (PREFIX_0FD6
) },
2823 { MOD_TABLE (MOD_0FD7
) },
2825 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2826 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2827 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2828 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2829 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2830 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2831 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2832 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2834 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2835 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2836 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2837 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2838 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2839 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2840 { PREFIX_TABLE (PREFIX_0FE6
) },
2841 { PREFIX_TABLE (PREFIX_0FE7
) },
2843 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
2844 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
2845 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
2846 { "por", { MX
, EM
}, PREFIX_OPCODE
},
2847 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
2848 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
2849 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
2850 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
2852 { PREFIX_TABLE (PREFIX_0FF0
) },
2853 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
2854 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
2855 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
2856 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
2857 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
2858 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
2859 { PREFIX_TABLE (PREFIX_0FF7
) },
2861 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
2862 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
2863 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
2864 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
2865 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
2866 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
2867 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
2868 { "ud0S", { Gv
, Ev
}, 0 },
2871 static const unsigned char onebyte_has_modrm
[256] = {
2872 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2873 /* ------------------------------- */
2874 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2875 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2876 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2877 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2878 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2879 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2880 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2881 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2882 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2883 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2884 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2885 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2886 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2887 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2888 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2889 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2890 /* ------------------------------- */
2891 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2894 static const unsigned char twobyte_has_modrm
[256] = {
2895 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2896 /* ------------------------------- */
2897 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2898 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2899 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2900 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2901 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2902 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2903 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2904 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2905 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2906 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2907 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2908 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2909 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2910 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2911 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2912 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2913 /* ------------------------------- */
2914 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2917 static char obuf
[100];
2919 static char *mnemonicendp
;
2920 static char scratchbuf
[100];
2921 static unsigned char *start_codep
;
2922 static unsigned char *insn_codep
;
2923 static unsigned char *codep
;
2924 static unsigned char *end_codep
;
2925 static int last_lock_prefix
;
2926 static int last_repz_prefix
;
2927 static int last_repnz_prefix
;
2928 static int last_data_prefix
;
2929 static int last_addr_prefix
;
2930 static int last_rex_prefix
;
2931 static int last_seg_prefix
;
2932 static int fwait_prefix
;
2933 /* The active segment register prefix. */
2934 static int active_seg_prefix
;
2935 #define MAX_CODE_LENGTH 15
2936 /* We can up to 14 prefixes since the maximum instruction length is
2938 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
2939 static disassemble_info
*the_info
;
2947 static unsigned char need_modrm
;
2957 int register_specifier
;
2964 int mask_register_specifier
;
2970 static unsigned char need_vex
;
2978 /* If we are accessing mod/rm/reg without need_modrm set, then the
2979 values are stale. Hitting this abort likely indicates that you
2980 need to update onebyte_has_modrm or twobyte_has_modrm. */
2981 #define MODRM_CHECK if (!need_modrm) abort ()
2983 static const char **names64
;
2984 static const char **names32
;
2985 static const char **names16
;
2986 static const char **names8
;
2987 static const char **names8rex
;
2988 static const char **names_seg
;
2989 static const char *index64
;
2990 static const char *index32
;
2991 static const char **index16
;
2992 static const char **names_bnd
;
2994 static const char *intel_names64
[] = {
2995 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2996 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2998 static const char *intel_names32
[] = {
2999 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3000 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3002 static const char *intel_names16
[] = {
3003 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3004 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3006 static const char *intel_names8
[] = {
3007 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3009 static const char *intel_names8rex
[] = {
3010 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3011 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3013 static const char *intel_names_seg
[] = {
3014 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3016 static const char *intel_index64
= "riz";
3017 static const char *intel_index32
= "eiz";
3018 static const char *intel_index16
[] = {
3019 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3022 static const char *att_names64
[] = {
3023 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3024 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3026 static const char *att_names32
[] = {
3027 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3028 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3030 static const char *att_names16
[] = {
3031 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3032 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3034 static const char *att_names8
[] = {
3035 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3037 static const char *att_names8rex
[] = {
3038 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3039 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3041 static const char *att_names_seg
[] = {
3042 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3044 static const char *att_index64
= "%riz";
3045 static const char *att_index32
= "%eiz";
3046 static const char *att_index16
[] = {
3047 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3050 static const char **names_mm
;
3051 static const char *intel_names_mm
[] = {
3052 "mm0", "mm1", "mm2", "mm3",
3053 "mm4", "mm5", "mm6", "mm7"
3055 static const char *att_names_mm
[] = {
3056 "%mm0", "%mm1", "%mm2", "%mm3",
3057 "%mm4", "%mm5", "%mm6", "%mm7"
3060 static const char *intel_names_bnd
[] = {
3061 "bnd0", "bnd1", "bnd2", "bnd3"
3064 static const char *att_names_bnd
[] = {
3065 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3068 static const char **names_xmm
;
3069 static const char *intel_names_xmm
[] = {
3070 "xmm0", "xmm1", "xmm2", "xmm3",
3071 "xmm4", "xmm5", "xmm6", "xmm7",
3072 "xmm8", "xmm9", "xmm10", "xmm11",
3073 "xmm12", "xmm13", "xmm14", "xmm15",
3074 "xmm16", "xmm17", "xmm18", "xmm19",
3075 "xmm20", "xmm21", "xmm22", "xmm23",
3076 "xmm24", "xmm25", "xmm26", "xmm27",
3077 "xmm28", "xmm29", "xmm30", "xmm31"
3079 static const char *att_names_xmm
[] = {
3080 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3081 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3082 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3083 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3084 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3085 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3086 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3087 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3090 static const char **names_ymm
;
3091 static const char *intel_names_ymm
[] = {
3092 "ymm0", "ymm1", "ymm2", "ymm3",
3093 "ymm4", "ymm5", "ymm6", "ymm7",
3094 "ymm8", "ymm9", "ymm10", "ymm11",
3095 "ymm12", "ymm13", "ymm14", "ymm15",
3096 "ymm16", "ymm17", "ymm18", "ymm19",
3097 "ymm20", "ymm21", "ymm22", "ymm23",
3098 "ymm24", "ymm25", "ymm26", "ymm27",
3099 "ymm28", "ymm29", "ymm30", "ymm31"
3101 static const char *att_names_ymm
[] = {
3102 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3103 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3104 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3105 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3106 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3107 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3108 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3109 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3112 static const char **names_zmm
;
3113 static const char *intel_names_zmm
[] = {
3114 "zmm0", "zmm1", "zmm2", "zmm3",
3115 "zmm4", "zmm5", "zmm6", "zmm7",
3116 "zmm8", "zmm9", "zmm10", "zmm11",
3117 "zmm12", "zmm13", "zmm14", "zmm15",
3118 "zmm16", "zmm17", "zmm18", "zmm19",
3119 "zmm20", "zmm21", "zmm22", "zmm23",
3120 "zmm24", "zmm25", "zmm26", "zmm27",
3121 "zmm28", "zmm29", "zmm30", "zmm31"
3123 static const char *att_names_zmm
[] = {
3124 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3125 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3126 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3127 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3128 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3129 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3130 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3131 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3134 static const char **names_tmm
;
3135 static const char *intel_names_tmm
[] = {
3136 "tmm0", "tmm1", "tmm2", "tmm3",
3137 "tmm4", "tmm5", "tmm6", "tmm7"
3139 static const char *att_names_tmm
[] = {
3140 "%tmm0", "%tmm1", "%tmm2", "%tmm3",
3141 "%tmm4", "%tmm5", "%tmm6", "%tmm7"
3144 static const char **names_mask
;
3145 static const char *intel_names_mask
[] = {
3146 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3148 static const char *att_names_mask
[] = {
3149 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3152 static const char *names_rounding
[] =
3160 static const struct dis386 reg_table
[][8] = {
3163 { "addA", { Ebh1
, Ib
}, 0 },
3164 { "orA", { Ebh1
, Ib
}, 0 },
3165 { "adcA", { Ebh1
, Ib
}, 0 },
3166 { "sbbA", { Ebh1
, Ib
}, 0 },
3167 { "andA", { Ebh1
, Ib
}, 0 },
3168 { "subA", { Ebh1
, Ib
}, 0 },
3169 { "xorA", { Ebh1
, Ib
}, 0 },
3170 { "cmpA", { Eb
, Ib
}, 0 },
3174 { "addQ", { Evh1
, Iv
}, 0 },
3175 { "orQ", { Evh1
, Iv
}, 0 },
3176 { "adcQ", { Evh1
, Iv
}, 0 },
3177 { "sbbQ", { Evh1
, Iv
}, 0 },
3178 { "andQ", { Evh1
, Iv
}, 0 },
3179 { "subQ", { Evh1
, Iv
}, 0 },
3180 { "xorQ", { Evh1
, Iv
}, 0 },
3181 { "cmpQ", { Ev
, Iv
}, 0 },
3185 { "addQ", { Evh1
, sIb
}, 0 },
3186 { "orQ", { Evh1
, sIb
}, 0 },
3187 { "adcQ", { Evh1
, sIb
}, 0 },
3188 { "sbbQ", { Evh1
, sIb
}, 0 },
3189 { "andQ", { Evh1
, sIb
}, 0 },
3190 { "subQ", { Evh1
, sIb
}, 0 },
3191 { "xorQ", { Evh1
, sIb
}, 0 },
3192 { "cmpQ", { Ev
, sIb
}, 0 },
3196 { "popU", { stackEv
}, 0 },
3197 { XOP_8F_TABLE (XOP_09
) },
3201 { XOP_8F_TABLE (XOP_09
) },
3205 { "rolA", { Eb
, Ib
}, 0 },
3206 { "rorA", { Eb
, Ib
}, 0 },
3207 { "rclA", { Eb
, Ib
}, 0 },
3208 { "rcrA", { Eb
, Ib
}, 0 },
3209 { "shlA", { Eb
, Ib
}, 0 },
3210 { "shrA", { Eb
, Ib
}, 0 },
3211 { "shlA", { Eb
, Ib
}, 0 },
3212 { "sarA", { Eb
, Ib
}, 0 },
3216 { "rolQ", { Ev
, Ib
}, 0 },
3217 { "rorQ", { Ev
, Ib
}, 0 },
3218 { "rclQ", { Ev
, Ib
}, 0 },
3219 { "rcrQ", { Ev
, Ib
}, 0 },
3220 { "shlQ", { Ev
, Ib
}, 0 },
3221 { "shrQ", { Ev
, Ib
}, 0 },
3222 { "shlQ", { Ev
, Ib
}, 0 },
3223 { "sarQ", { Ev
, Ib
}, 0 },
3227 { "movA", { Ebh3
, Ib
}, 0 },
3234 { MOD_TABLE (MOD_C6_REG_7
) },
3238 { "movQ", { Evh3
, Iv
}, 0 },
3245 { MOD_TABLE (MOD_C7_REG_7
) },
3249 { "rolA", { Eb
, I1
}, 0 },
3250 { "rorA", { Eb
, I1
}, 0 },
3251 { "rclA", { Eb
, I1
}, 0 },
3252 { "rcrA", { Eb
, I1
}, 0 },
3253 { "shlA", { Eb
, I1
}, 0 },
3254 { "shrA", { Eb
, I1
}, 0 },
3255 { "shlA", { Eb
, I1
}, 0 },
3256 { "sarA", { Eb
, I1
}, 0 },
3260 { "rolQ", { Ev
, I1
}, 0 },
3261 { "rorQ", { Ev
, I1
}, 0 },
3262 { "rclQ", { Ev
, I1
}, 0 },
3263 { "rcrQ", { Ev
, I1
}, 0 },
3264 { "shlQ", { Ev
, I1
}, 0 },
3265 { "shrQ", { Ev
, I1
}, 0 },
3266 { "shlQ", { Ev
, I1
}, 0 },
3267 { "sarQ", { Ev
, I1
}, 0 },
3271 { "rolA", { Eb
, CL
}, 0 },
3272 { "rorA", { Eb
, CL
}, 0 },
3273 { "rclA", { Eb
, CL
}, 0 },
3274 { "rcrA", { Eb
, CL
}, 0 },
3275 { "shlA", { Eb
, CL
}, 0 },
3276 { "shrA", { Eb
, CL
}, 0 },
3277 { "shlA", { Eb
, CL
}, 0 },
3278 { "sarA", { Eb
, CL
}, 0 },
3282 { "rolQ", { Ev
, CL
}, 0 },
3283 { "rorQ", { Ev
, CL
}, 0 },
3284 { "rclQ", { Ev
, CL
}, 0 },
3285 { "rcrQ", { Ev
, CL
}, 0 },
3286 { "shlQ", { Ev
, CL
}, 0 },
3287 { "shrQ", { Ev
, CL
}, 0 },
3288 { "shlQ", { Ev
, CL
}, 0 },
3289 { "sarQ", { Ev
, CL
}, 0 },
3293 { "testA", { Eb
, Ib
}, 0 },
3294 { "testA", { Eb
, Ib
}, 0 },
3295 { "notA", { Ebh1
}, 0 },
3296 { "negA", { Ebh1
}, 0 },
3297 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3298 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3299 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3300 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3304 { "testQ", { Ev
, Iv
}, 0 },
3305 { "testQ", { Ev
, Iv
}, 0 },
3306 { "notQ", { Evh1
}, 0 },
3307 { "negQ", { Evh1
}, 0 },
3308 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3309 { "imulQ", { Ev
}, 0 },
3310 { "divQ", { Ev
}, 0 },
3311 { "idivQ", { Ev
}, 0 },
3315 { "incA", { Ebh1
}, 0 },
3316 { "decA", { Ebh1
}, 0 },
3320 { "incQ", { Evh1
}, 0 },
3321 { "decQ", { Evh1
}, 0 },
3322 { "call{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3323 { MOD_TABLE (MOD_FF_REG_3
) },
3324 { "jmp{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3325 { MOD_TABLE (MOD_FF_REG_5
) },
3326 { "pushU", { stackEv
}, 0 },
3331 { "sldtD", { Sv
}, 0 },
3332 { "strD", { Sv
}, 0 },
3333 { "lldt", { Ew
}, 0 },
3334 { "ltr", { Ew
}, 0 },
3335 { "verr", { Ew
}, 0 },
3336 { "verw", { Ew
}, 0 },
3342 { MOD_TABLE (MOD_0F01_REG_0
) },
3343 { MOD_TABLE (MOD_0F01_REG_1
) },
3344 { MOD_TABLE (MOD_0F01_REG_2
) },
3345 { MOD_TABLE (MOD_0F01_REG_3
) },
3346 { "smswD", { Sv
}, 0 },
3347 { MOD_TABLE (MOD_0F01_REG_5
) },
3348 { "lmsw", { Ew
}, 0 },
3349 { MOD_TABLE (MOD_0F01_REG_7
) },
3353 { "prefetch", { Mb
}, 0 },
3354 { "prefetchw", { Mb
}, 0 },
3355 { "prefetchwt1", { Mb
}, 0 },
3356 { "prefetch", { Mb
}, 0 },
3357 { "prefetch", { Mb
}, 0 },
3358 { "prefetch", { Mb
}, 0 },
3359 { "prefetch", { Mb
}, 0 },
3360 { "prefetch", { Mb
}, 0 },
3364 { MOD_TABLE (MOD_0F18_REG_0
) },
3365 { MOD_TABLE (MOD_0F18_REG_1
) },
3366 { MOD_TABLE (MOD_0F18_REG_2
) },
3367 { MOD_TABLE (MOD_0F18_REG_3
) },
3368 { MOD_TABLE (MOD_0F18_REG_4
) },
3369 { MOD_TABLE (MOD_0F18_REG_5
) },
3370 { MOD_TABLE (MOD_0F18_REG_6
) },
3371 { MOD_TABLE (MOD_0F18_REG_7
) },
3373 /* REG_0F1C_P_0_MOD_0 */
3375 { "cldemote", { Mb
}, 0 },
3376 { "nopQ", { Ev
}, 0 },
3377 { "nopQ", { Ev
}, 0 },
3378 { "nopQ", { Ev
}, 0 },
3379 { "nopQ", { Ev
}, 0 },
3380 { "nopQ", { Ev
}, 0 },
3381 { "nopQ", { Ev
}, 0 },
3382 { "nopQ", { Ev
}, 0 },
3384 /* REG_0F1E_P_1_MOD_3 */
3386 { "nopQ", { Ev
}, 0 },
3387 { "rdsspK", { Rdq
}, PREFIX_OPCODE
},
3388 { "nopQ", { Ev
}, 0 },
3389 { "nopQ", { Ev
}, 0 },
3390 { "nopQ", { Ev
}, 0 },
3391 { "nopQ", { Ev
}, 0 },
3392 { "nopQ", { Ev
}, 0 },
3393 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7
) },
3399 { MOD_TABLE (MOD_0F71_REG_2
) },
3401 { MOD_TABLE (MOD_0F71_REG_4
) },
3403 { MOD_TABLE (MOD_0F71_REG_6
) },
3409 { MOD_TABLE (MOD_0F72_REG_2
) },
3411 { MOD_TABLE (MOD_0F72_REG_4
) },
3413 { MOD_TABLE (MOD_0F72_REG_6
) },
3419 { MOD_TABLE (MOD_0F73_REG_2
) },
3420 { MOD_TABLE (MOD_0F73_REG_3
) },
3423 { MOD_TABLE (MOD_0F73_REG_6
) },
3424 { MOD_TABLE (MOD_0F73_REG_7
) },
3428 { "montmul", { { OP_0f07
, 0 } }, 0 },
3429 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3430 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3434 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3435 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3436 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3437 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3438 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3439 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3443 { MOD_TABLE (MOD_0FAE_REG_0
) },
3444 { MOD_TABLE (MOD_0FAE_REG_1
) },
3445 { MOD_TABLE (MOD_0FAE_REG_2
) },
3446 { MOD_TABLE (MOD_0FAE_REG_3
) },
3447 { MOD_TABLE (MOD_0FAE_REG_4
) },
3448 { MOD_TABLE (MOD_0FAE_REG_5
) },
3449 { MOD_TABLE (MOD_0FAE_REG_6
) },
3450 { MOD_TABLE (MOD_0FAE_REG_7
) },
3458 { "btQ", { Ev
, Ib
}, 0 },
3459 { "btsQ", { Evh1
, Ib
}, 0 },
3460 { "btrQ", { Evh1
, Ib
}, 0 },
3461 { "btcQ", { Evh1
, Ib
}, 0 },
3466 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3468 { MOD_TABLE (MOD_0FC7_REG_3
) },
3469 { MOD_TABLE (MOD_0FC7_REG_4
) },
3470 { MOD_TABLE (MOD_0FC7_REG_5
) },
3471 { MOD_TABLE (MOD_0FC7_REG_6
) },
3472 { MOD_TABLE (MOD_0FC7_REG_7
) },
3478 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3480 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3482 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3488 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3490 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3492 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3498 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3499 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3502 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3503 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3509 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3510 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3512 /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
3514 { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
) },
3516 /* REG_VEX_0F38F3 */
3519 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3520 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3521 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3523 /* REG_0FXOP_09_01_L_0 */
3526 { "blcfill", { VexGdq
, Edq
}, 0 },
3527 { "blsfill", { VexGdq
, Edq
}, 0 },
3528 { "blcs", { VexGdq
, Edq
}, 0 },
3529 { "tzmsk", { VexGdq
, Edq
}, 0 },
3530 { "blcic", { VexGdq
, Edq
}, 0 },
3531 { "blsic", { VexGdq
, Edq
}, 0 },
3532 { "t1mskc", { VexGdq
, Edq
}, 0 },
3534 /* REG_0FXOP_09_02_L_0 */
3537 { "blcmsk", { VexGdq
, Edq
}, 0 },
3542 { "blci", { VexGdq
, Edq
}, 0 },
3544 /* REG_0FXOP_09_12_M_1_L_0 */
3546 { "llwpcb", { Edq
}, 0 },
3547 { "slwpcb", { Edq
}, 0 },
3549 /* REG_0FXOP_0A_12_L_0 */
3551 { "lwpins", { VexGdq
, Ed
, Id
}, 0 },
3552 { "lwpval", { VexGdq
, Ed
, Id
}, 0 },
3555 #include "i386-dis-evex-reg.h"
3558 static const struct dis386 prefix_table
[][4] = {
3561 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3562 { "pause", { XX
}, 0 },
3563 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3564 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3567 /* PREFIX_0F01_REG_3_RM_1 */
3569 { "vmmcall", { Skip_MODRM
}, 0 },
3570 { "vmgexit", { Skip_MODRM
}, 0 },
3572 { "vmgexit", { Skip_MODRM
}, 0 },
3575 /* PREFIX_0F01_REG_5_MOD_0 */
3578 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3581 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3583 { "serialize", { Skip_MODRM
}, PREFIX_OPCODE
},
3584 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3586 { "xsusldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3589 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3594 { "xresldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3597 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3600 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3603 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3605 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
3606 { "mcommit", { Skip_MODRM
}, 0 },
3609 /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3611 { "mwaitx", { { OP_Mwait
, eBX_reg
} }, 0 },
3616 { "wbinvd", { XX
}, 0 },
3617 { "wbnoinvd", { XX
}, 0 },
3622 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3623 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3624 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3625 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3630 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3631 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3632 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3633 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3638 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3639 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3640 { MOD_TABLE (MOD_0F12_PREFIX_2
) },
3641 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3646 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3647 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3648 { MOD_TABLE (MOD_0F16_PREFIX_2
) },
3653 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3654 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3655 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3656 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3661 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3662 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3663 { "bndmov", { EbndS
, Gbnd
}, 0 },
3664 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3669 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3670 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3671 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3672 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3677 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3678 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3679 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3680 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3685 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3686 { "cvtsi2ss{%LQ|}", { XM
, Edq
}, PREFIX_OPCODE
},
3687 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3688 { "cvtsi2sd{%LQ|}", { XM
, Edq
}, 0 },
3693 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3694 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3695 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3696 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3701 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3702 { "cvttss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3703 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3704 { "cvttsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3709 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3710 { "cvtss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3711 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3712 { "cvtsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3717 { "ucomiss",{ XM
, EXd
}, 0 },
3719 { "ucomisd",{ XM
, EXq
}, 0 },
3724 { "comiss", { XM
, EXd
}, 0 },
3726 { "comisd", { XM
, EXq
}, 0 },
3731 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3732 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3733 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3734 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3739 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3740 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3745 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3746 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3751 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3752 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3753 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3754 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3759 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3760 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3761 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3762 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3767 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3768 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3769 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3770 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3775 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3776 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3777 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3782 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3783 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3784 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3785 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3790 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3791 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3792 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3793 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3798 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3799 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3800 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3801 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3806 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3807 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3808 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3809 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3814 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3816 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3821 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3823 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3828 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3830 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3837 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3844 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3849 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3850 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3851 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3856 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3857 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3858 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3859 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3862 /* PREFIX_0F73_REG_3 */
3866 { "psrldq", { XS
, Ib
}, 0 },
3869 /* PREFIX_0F73_REG_7 */
3873 { "pslldq", { XS
, Ib
}, 0 },
3878 {"vmread", { Em
, Gm
}, 0 },
3880 {"extrq", { XS
, Ib
, Ib
}, 0 },
3881 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3886 {"vmwrite", { Gm
, Em
}, 0 },
3888 {"extrq", { XM
, XS
}, 0 },
3889 {"insertq", { XM
, XS
}, 0 },
3896 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3897 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3904 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3905 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3910 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3911 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3912 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3917 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3918 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3919 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3922 /* PREFIX_0FAE_REG_0_MOD_3 */
3925 { "rdfsbase", { Ev
}, 0 },
3928 /* PREFIX_0FAE_REG_1_MOD_3 */
3931 { "rdgsbase", { Ev
}, 0 },
3934 /* PREFIX_0FAE_REG_2_MOD_3 */
3937 { "wrfsbase", { Ev
}, 0 },
3940 /* PREFIX_0FAE_REG_3_MOD_3 */
3943 { "wrgsbase", { Ev
}, 0 },
3946 /* PREFIX_0FAE_REG_4_MOD_0 */
3948 { "xsave", { FXSAVE
}, 0 },
3949 { "ptwrite{%LQ|}", { Edq
}, 0 },
3952 /* PREFIX_0FAE_REG_4_MOD_3 */
3955 { "ptwrite{%LQ|}", { Edq
}, 0 },
3958 /* PREFIX_0FAE_REG_5_MOD_0 */
3960 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
3963 /* PREFIX_0FAE_REG_5_MOD_3 */
3965 { "lfence", { Skip_MODRM
}, 0 },
3966 { "incsspK", { Rdq
}, PREFIX_OPCODE
},
3969 /* PREFIX_0FAE_REG_6_MOD_0 */
3971 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
3972 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
3973 { "clwb", { Mb
}, PREFIX_OPCODE
},
3976 /* PREFIX_0FAE_REG_6_MOD_3 */
3978 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0
) },
3979 { "umonitor", { Eva
}, PREFIX_OPCODE
},
3980 { "tpause", { Edq
}, PREFIX_OPCODE
},
3981 { "umwait", { Edq
}, PREFIX_OPCODE
},
3984 /* PREFIX_0FAE_REG_7_MOD_0 */
3986 { "clflush", { Mb
}, 0 },
3988 { "clflushopt", { Mb
}, 0 },
3994 { "popcntS", { Gv
, Ev
}, 0 },
3999 { "bsfS", { Gv
, Ev
}, 0 },
4000 { "tzcntS", { Gv
, Ev
}, 0 },
4001 { "bsfS", { Gv
, Ev
}, 0 },
4006 { "bsrS", { Gv
, Ev
}, 0 },
4007 { "lzcntS", { Gv
, Ev
}, 0 },
4008 { "bsrS", { Gv
, Ev
}, 0 },
4013 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4014 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4015 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4016 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4019 /* PREFIX_0FC3_MOD_0 */
4021 { "movntiS", { Edq
, Gdq
}, PREFIX_OPCODE
},
4024 /* PREFIX_0FC7_REG_6_MOD_0 */
4026 { "vmptrld",{ Mq
}, 0 },
4027 { "vmxon", { Mq
}, 0 },
4028 { "vmclear",{ Mq
}, 0 },
4031 /* PREFIX_0FC7_REG_6_MOD_3 */
4033 { "rdrand", { Ev
}, 0 },
4035 { "rdrand", { Ev
}, 0 }
4038 /* PREFIX_0FC7_REG_7_MOD_3 */
4040 { "rdseed", { Ev
}, 0 },
4041 { "rdpid", { Em
}, 0 },
4042 { "rdseed", { Ev
}, 0 },
4049 { "addsubpd", { XM
, EXx
}, 0 },
4050 { "addsubps", { XM
, EXx
}, 0 },
4056 { "movq2dq",{ XM
, MS
}, 0 },
4057 { "movq", { EXqS
, XM
}, 0 },
4058 { "movdq2q",{ MX
, XS
}, 0 },
4064 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4065 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4066 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4071 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4073 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4081 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4086 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4088 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4095 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4102 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4109 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4116 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4123 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4130 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4137 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4144 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4151 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4158 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4165 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4172 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4179 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4186 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4193 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4200 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4207 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4214 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4221 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4228 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4235 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4242 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4249 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4256 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4263 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4270 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4277 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4284 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4291 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4298 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4305 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4312 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4319 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4326 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4331 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4336 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4341 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4346 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4351 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4356 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4363 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_OPCODE
},
4370 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4377 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4384 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4391 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4398 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4403 { "movbeS", { Gv
, Mv
}, PREFIX_OPCODE
},
4405 { "movbeS", { Gv
, Mv
}, PREFIX_OPCODE
},
4406 { "crc32A", { Gdq
, Eb
}, PREFIX_OPCODE
},
4411 { "movbeS", { Mv
, Gv
}, PREFIX_OPCODE
},
4413 { "movbeS", { Mv
, Gv
}, PREFIX_OPCODE
},
4414 { "crc32Q", { Gdq
, Ev
}, PREFIX_OPCODE
},
4421 { MOD_TABLE (MOD_0F38F5_PREFIX_2
) },
4426 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
4427 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4428 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4435 { MOD_TABLE (MOD_0F38F8_PREFIX_1
) },
4436 { MOD_TABLE (MOD_0F38F8_PREFIX_2
) },
4437 { MOD_TABLE (MOD_0F38F8_PREFIX_3
) },
4442 { MOD_TABLE (MOD_0F38F9_PREFIX_0
) },
4449 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4456 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4463 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4470 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4477 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4484 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4491 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4498 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4505 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4512 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4519 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4526 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4533 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4540 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4547 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4554 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4561 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4568 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4575 { "pcmpestrm!%LQ", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4582 { "pcmpestri!%LQ", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4589 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4596 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4601 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4608 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4615 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4622 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4625 /* PREFIX_VEX_0F10 */
4627 { "vmovups", { XM
, EXx
}, 0 },
4628 { "vmovss", { XMScalar
, VexScalarR
, EXxmm_md
}, 0 },
4629 { "vmovupd", { XM
, EXx
}, 0 },
4630 { "vmovsd", { XMScalar
, VexScalarR
, EXxmm_mq
}, 0 },
4633 /* PREFIX_VEX_0F11 */
4635 { "vmovups", { EXxS
, XM
}, 0 },
4636 { "vmovss", { EXdS
, VexScalarR
, XMScalar
}, 0 },
4637 { "vmovupd", { EXxS
, XM
}, 0 },
4638 { "vmovsd", { EXqS
, VexScalarR
, XMScalar
}, 0 },
4641 /* PREFIX_VEX_0F12 */
4643 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4644 { "vmovsldup", { XM
, EXx
}, 0 },
4645 { MOD_TABLE (MOD_VEX_0F12_PREFIX_2
) },
4646 { "vmovddup", { XM
, EXymmq
}, 0 },
4649 /* PREFIX_VEX_0F16 */
4651 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4652 { "vmovshdup", { XM
, EXx
}, 0 },
4653 { MOD_TABLE (MOD_VEX_0F16_PREFIX_2
) },
4656 /* PREFIX_VEX_0F2A */
4659 { "vcvtsi2ss{%LQ|}", { XMScalar
, VexScalar
, Edq
}, 0 },
4661 { "vcvtsi2sd{%LQ|}", { XMScalar
, VexScalar
, Edq
}, 0 },
4664 /* PREFIX_VEX_0F2C */
4667 { "vcvttss2si", { Gdq
, EXxmm_md
}, 0 },
4669 { "vcvttsd2si", { Gdq
, EXxmm_mq
}, 0 },
4672 /* PREFIX_VEX_0F2D */
4675 { "vcvtss2si", { Gdq
, EXxmm_md
}, 0 },
4677 { "vcvtsd2si", { Gdq
, EXxmm_mq
}, 0 },
4680 /* PREFIX_VEX_0F2E */
4682 { "vucomiss", { XMScalar
, EXxmm_md
}, 0 },
4684 { "vucomisd", { XMScalar
, EXxmm_mq
}, 0 },
4687 /* PREFIX_VEX_0F2F */
4689 { "vcomiss", { XMScalar
, EXxmm_md
}, 0 },
4691 { "vcomisd", { XMScalar
, EXxmm_mq
}, 0 },
4694 /* PREFIX_VEX_0F41 */
4696 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4698 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4701 /* PREFIX_VEX_0F42 */
4703 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4705 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4708 /* PREFIX_VEX_0F44 */
4710 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4712 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4715 /* PREFIX_VEX_0F45 */
4717 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4719 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4722 /* PREFIX_VEX_0F46 */
4724 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4726 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4729 /* PREFIX_VEX_0F47 */
4731 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4733 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4736 /* PREFIX_VEX_0F4A */
4738 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4740 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4743 /* PREFIX_VEX_0F4B */
4745 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4747 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4750 /* PREFIX_VEX_0F51 */
4752 { "vsqrtps", { XM
, EXx
}, 0 },
4753 { "vsqrtss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4754 { "vsqrtpd", { XM
, EXx
}, 0 },
4755 { "vsqrtsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4758 /* PREFIX_VEX_0F52 */
4760 { "vrsqrtps", { XM
, EXx
}, 0 },
4761 { "vrsqrtss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4764 /* PREFIX_VEX_0F53 */
4766 { "vrcpps", { XM
, EXx
}, 0 },
4767 { "vrcpss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4770 /* PREFIX_VEX_0F58 */
4772 { "vaddps", { XM
, Vex
, EXx
}, 0 },
4773 { "vaddss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4774 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
4775 { "vaddsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4778 /* PREFIX_VEX_0F59 */
4780 { "vmulps", { XM
, Vex
, EXx
}, 0 },
4781 { "vmulss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4782 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
4783 { "vmulsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4786 /* PREFIX_VEX_0F5A */
4788 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
4789 { "vcvtss2sd", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4790 { "vcvtpd2ps%XY",{ XMM
, EXx
}, 0 },
4791 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4794 /* PREFIX_VEX_0F5B */
4796 { "vcvtdq2ps", { XM
, EXx
}, 0 },
4797 { "vcvttps2dq", { XM
, EXx
}, 0 },
4798 { "vcvtps2dq", { XM
, EXx
}, 0 },
4801 /* PREFIX_VEX_0F5C */
4803 { "vsubps", { XM
, Vex
, EXx
}, 0 },
4804 { "vsubss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4805 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
4806 { "vsubsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4809 /* PREFIX_VEX_0F5D */
4811 { "vminps", { XM
, Vex
, EXx
}, 0 },
4812 { "vminss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4813 { "vminpd", { XM
, Vex
, EXx
}, 0 },
4814 { "vminsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4817 /* PREFIX_VEX_0F5E */
4819 { "vdivps", { XM
, Vex
, EXx
}, 0 },
4820 { "vdivss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4821 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
4822 { "vdivsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4825 /* PREFIX_VEX_0F5F */
4827 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
4828 { "vmaxss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4829 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
4830 { "vmaxsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4833 /* PREFIX_VEX_0F60 */
4837 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
4840 /* PREFIX_VEX_0F61 */
4844 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
4847 /* PREFIX_VEX_0F62 */
4851 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
4854 /* PREFIX_VEX_0F63 */
4858 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
4861 /* PREFIX_VEX_0F64 */
4865 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
4868 /* PREFIX_VEX_0F65 */
4872 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
4875 /* PREFIX_VEX_0F66 */
4879 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
4882 /* PREFIX_VEX_0F67 */
4886 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
4889 /* PREFIX_VEX_0F68 */
4893 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
4896 /* PREFIX_VEX_0F69 */
4900 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
4903 /* PREFIX_VEX_0F6A */
4907 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
4910 /* PREFIX_VEX_0F6B */
4914 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
4917 /* PREFIX_VEX_0F6C */
4921 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
4924 /* PREFIX_VEX_0F6D */
4928 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
4931 /* PREFIX_VEX_0F6E */
4935 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4938 /* PREFIX_VEX_0F6F */
4941 { "vmovdqu", { XM
, EXx
}, 0 },
4942 { "vmovdqa", { XM
, EXx
}, 0 },
4945 /* PREFIX_VEX_0F70 */
4948 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
4949 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
4950 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
4953 /* PREFIX_VEX_0F71_REG_2 */
4957 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
4960 /* PREFIX_VEX_0F71_REG_4 */
4964 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
4967 /* PREFIX_VEX_0F71_REG_6 */
4971 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
4974 /* PREFIX_VEX_0F72_REG_2 */
4978 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
4981 /* PREFIX_VEX_0F72_REG_4 */
4985 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
4988 /* PREFIX_VEX_0F72_REG_6 */
4992 { "vpslld", { Vex
, XS
, Ib
}, 0 },
4995 /* PREFIX_VEX_0F73_REG_2 */
4999 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
5002 /* PREFIX_VEX_0F73_REG_3 */
5006 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
5009 /* PREFIX_VEX_0F73_REG_6 */
5013 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
5016 /* PREFIX_VEX_0F73_REG_7 */
5020 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
5023 /* PREFIX_VEX_0F74 */
5027 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
5030 /* PREFIX_VEX_0F75 */
5034 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
5037 /* PREFIX_VEX_0F76 */
5041 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
5044 /* PREFIX_VEX_0F77 */
5046 { VEX_LEN_TABLE (VEX_LEN_0F77_P_0
) },
5049 /* PREFIX_VEX_0F7C */
5053 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
5054 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
5057 /* PREFIX_VEX_0F7D */
5061 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
5062 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
5065 /* PREFIX_VEX_0F7E */
5068 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5069 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5072 /* PREFIX_VEX_0F7F */
5075 { "vmovdqu", { EXxS
, XM
}, 0 },
5076 { "vmovdqa", { EXxS
, XM
}, 0 },
5079 /* PREFIX_VEX_0F90 */
5081 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5083 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5086 /* PREFIX_VEX_0F91 */
5088 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5090 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5093 /* PREFIX_VEX_0F92 */
5095 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5097 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5098 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5101 /* PREFIX_VEX_0F93 */
5103 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5105 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5106 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5109 /* PREFIX_VEX_0F98 */
5111 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5113 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5116 /* PREFIX_VEX_0F99 */
5118 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5120 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5123 /* PREFIX_VEX_0FC2 */
5125 { "vcmpps", { XM
, Vex
, EXx
, CMP
}, 0 },
5126 { "vcmpss", { XMScalar
, VexScalar
, EXxmm_md
, CMP
}, 0 },
5127 { "vcmppd", { XM
, Vex
, EXx
, CMP
}, 0 },
5128 { "vcmpsd", { XMScalar
, VexScalar
, EXxmm_mq
, CMP
}, 0 },
5131 /* PREFIX_VEX_0FC4 */
5135 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5138 /* PREFIX_VEX_0FC5 */
5142 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5145 /* PREFIX_VEX_0FD0 */
5149 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
5150 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
5153 /* PREFIX_VEX_0FD1 */
5157 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
5160 /* PREFIX_VEX_0FD2 */
5164 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
5167 /* PREFIX_VEX_0FD3 */
5171 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
5174 /* PREFIX_VEX_0FD4 */
5178 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
5181 /* PREFIX_VEX_0FD5 */
5185 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
5188 /* PREFIX_VEX_0FD6 */
5192 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5195 /* PREFIX_VEX_0FD7 */
5199 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5202 /* PREFIX_VEX_0FD8 */
5206 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
5209 /* PREFIX_VEX_0FD9 */
5213 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
5216 /* PREFIX_VEX_0FDA */
5220 { "vpminub", { XM
, Vex
, EXx
}, 0 },
5223 /* PREFIX_VEX_0FDB */
5227 { "vpand", { XM
, Vex
, EXx
}, 0 },
5230 /* PREFIX_VEX_0FDC */
5234 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
5237 /* PREFIX_VEX_0FDD */
5241 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
5244 /* PREFIX_VEX_0FDE */
5248 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
5251 /* PREFIX_VEX_0FDF */
5255 { "vpandn", { XM
, Vex
, EXx
}, 0 },
5258 /* PREFIX_VEX_0FE0 */
5262 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
5265 /* PREFIX_VEX_0FE1 */
5269 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
5272 /* PREFIX_VEX_0FE2 */
5276 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
5279 /* PREFIX_VEX_0FE3 */
5283 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
5286 /* PREFIX_VEX_0FE4 */
5290 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
5293 /* PREFIX_VEX_0FE5 */
5297 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
5300 /* PREFIX_VEX_0FE6 */
5303 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
5304 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
5305 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
5308 /* PREFIX_VEX_0FE7 */
5312 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5315 /* PREFIX_VEX_0FE8 */
5319 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
5322 /* PREFIX_VEX_0FE9 */
5326 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
5329 /* PREFIX_VEX_0FEA */
5333 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
5336 /* PREFIX_VEX_0FEB */
5340 { "vpor", { XM
, Vex
, EXx
}, 0 },
5343 /* PREFIX_VEX_0FEC */
5347 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
5350 /* PREFIX_VEX_0FED */
5354 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
5357 /* PREFIX_VEX_0FEE */
5361 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
5364 /* PREFIX_VEX_0FEF */
5368 { "vpxor", { XM
, Vex
, EXx
}, 0 },
5371 /* PREFIX_VEX_0FF0 */
5376 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5379 /* PREFIX_VEX_0FF1 */
5383 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
5386 /* PREFIX_VEX_0FF2 */
5390 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
5393 /* PREFIX_VEX_0FF3 */
5397 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
5400 /* PREFIX_VEX_0FF4 */
5404 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
5407 /* PREFIX_VEX_0FF5 */
5411 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
5414 /* PREFIX_VEX_0FF6 */
5418 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
5421 /* PREFIX_VEX_0FF7 */
5425 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5428 /* PREFIX_VEX_0FF8 */
5432 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
5435 /* PREFIX_VEX_0FF9 */
5439 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
5442 /* PREFIX_VEX_0FFA */
5446 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
5449 /* PREFIX_VEX_0FFB */
5453 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
5456 /* PREFIX_VEX_0FFC */
5460 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
5463 /* PREFIX_VEX_0FFD */
5467 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
5470 /* PREFIX_VEX_0FFE */
5474 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
5477 /* PREFIX_VEX_0F3800 */
5481 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
5484 /* PREFIX_VEX_0F3801 */
5488 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
5491 /* PREFIX_VEX_0F3802 */
5495 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
5498 /* PREFIX_VEX_0F3803 */
5502 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
5505 /* PREFIX_VEX_0F3804 */
5509 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
5512 /* PREFIX_VEX_0F3805 */
5516 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
5519 /* PREFIX_VEX_0F3806 */
5523 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
5526 /* PREFIX_VEX_0F3807 */
5530 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
5533 /* PREFIX_VEX_0F3808 */
5537 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
5540 /* PREFIX_VEX_0F3809 */
5544 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
5547 /* PREFIX_VEX_0F380A */
5551 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
5554 /* PREFIX_VEX_0F380B */
5558 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
5561 /* PREFIX_VEX_0F380C */
5565 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5568 /* PREFIX_VEX_0F380D */
5572 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5575 /* PREFIX_VEX_0F380E */
5579 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5582 /* PREFIX_VEX_0F380F */
5586 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5589 /* PREFIX_VEX_0F3813 */
5593 { VEX_W_TABLE (VEX_W_0F3813_P_2
) },
5596 /* PREFIX_VEX_0F3816 */
5600 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5603 /* PREFIX_VEX_0F3817 */
5607 { "vptest", { XM
, EXx
}, 0 },
5610 /* PREFIX_VEX_0F3818 */
5614 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5617 /* PREFIX_VEX_0F3819 */
5621 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5624 /* PREFIX_VEX_0F381A */
5628 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5631 /* PREFIX_VEX_0F381C */
5635 { "vpabsb", { XM
, EXx
}, 0 },
5638 /* PREFIX_VEX_0F381D */
5642 { "vpabsw", { XM
, EXx
}, 0 },
5645 /* PREFIX_VEX_0F381E */
5649 { "vpabsd", { XM
, EXx
}, 0 },
5652 /* PREFIX_VEX_0F3820 */
5656 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
5659 /* PREFIX_VEX_0F3821 */
5663 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
5666 /* PREFIX_VEX_0F3822 */
5670 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
5673 /* PREFIX_VEX_0F3823 */
5677 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
5680 /* PREFIX_VEX_0F3824 */
5684 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
5687 /* PREFIX_VEX_0F3825 */
5691 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
5694 /* PREFIX_VEX_0F3828 */
5698 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
5701 /* PREFIX_VEX_0F3829 */
5705 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
5708 /* PREFIX_VEX_0F382A */
5712 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5715 /* PREFIX_VEX_0F382B */
5719 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
5722 /* PREFIX_VEX_0F382C */
5726 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5729 /* PREFIX_VEX_0F382D */
5733 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5736 /* PREFIX_VEX_0F382E */
5740 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5743 /* PREFIX_VEX_0F382F */
5747 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5750 /* PREFIX_VEX_0F3830 */
5754 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
5757 /* PREFIX_VEX_0F3831 */
5761 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
5764 /* PREFIX_VEX_0F3832 */
5768 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
5771 /* PREFIX_VEX_0F3833 */
5775 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
5778 /* PREFIX_VEX_0F3834 */
5782 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
5785 /* PREFIX_VEX_0F3835 */
5789 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
5792 /* PREFIX_VEX_0F3836 */
5796 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5799 /* PREFIX_VEX_0F3837 */
5803 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
5806 /* PREFIX_VEX_0F3838 */
5810 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
5813 /* PREFIX_VEX_0F3839 */
5817 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
5820 /* PREFIX_VEX_0F383A */
5824 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
5827 /* PREFIX_VEX_0F383B */
5831 { "vpminud", { XM
, Vex
, EXx
}, 0 },
5834 /* PREFIX_VEX_0F383C */
5838 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
5841 /* PREFIX_VEX_0F383D */
5845 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
5848 /* PREFIX_VEX_0F383E */
5852 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
5855 /* PREFIX_VEX_0F383F */
5859 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
5862 /* PREFIX_VEX_0F3840 */
5866 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
5869 /* PREFIX_VEX_0F3841 */
5873 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5876 /* PREFIX_VEX_0F3845 */
5880 { "vpsrlv%DQ", { XM
, Vex
, EXx
}, 0 },
5883 /* PREFIX_VEX_0F3846 */
5887 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5890 /* PREFIX_VEX_0F3847 */
5894 { "vpsllv%DQ", { XM
, Vex
, EXx
}, 0 },
5897 /* PREFIX_VEX_0F3849_X86_64 */
5899 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0
) },
5901 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2
) },
5902 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3
) },
5905 /* PREFIX_VEX_0F384B_X86_64 */
5908 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1
) },
5909 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2
) },
5910 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3
) },
5913 /* PREFIX_VEX_0F3858 */
5917 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5920 /* PREFIX_VEX_0F3859 */
5924 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5927 /* PREFIX_VEX_0F385A */
5931 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5934 /* PREFIX_VEX_0F385C_X86_64 */
5937 { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1
) },
5941 /* PREFIX_VEX_0F385E_X86_64 */
5943 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0
) },
5944 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1
) },
5945 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2
) },
5946 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3
) },
5949 /* PREFIX_VEX_0F3878 */
5953 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5956 /* PREFIX_VEX_0F3879 */
5960 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5963 /* PREFIX_VEX_0F388C */
5967 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5970 /* PREFIX_VEX_0F388E */
5974 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
5977 /* PREFIX_VEX_0F3890 */
5981 { "vpgatherd%DQ", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5984 /* PREFIX_VEX_0F3891 */
5988 { "vpgatherq%DQ", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
5991 /* PREFIX_VEX_0F3892 */
5995 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5998 /* PREFIX_VEX_0F3893 */
6002 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6005 /* PREFIX_VEX_0F3896 */
6009 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6012 /* PREFIX_VEX_0F3897 */
6016 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6019 /* PREFIX_VEX_0F3898 */
6023 { "vfmadd132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6026 /* PREFIX_VEX_0F3899 */
6030 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6033 /* PREFIX_VEX_0F389A */
6037 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6040 /* PREFIX_VEX_0F389B */
6044 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6047 /* PREFIX_VEX_0F389C */
6051 { "vfnmadd132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6054 /* PREFIX_VEX_0F389D */
6058 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6061 /* PREFIX_VEX_0F389E */
6065 { "vfnmsub132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6068 /* PREFIX_VEX_0F389F */
6072 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6075 /* PREFIX_VEX_0F38A6 */
6079 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6083 /* PREFIX_VEX_0F38A7 */
6087 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6090 /* PREFIX_VEX_0F38A8 */
6094 { "vfmadd213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6097 /* PREFIX_VEX_0F38A9 */
6101 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6104 /* PREFIX_VEX_0F38AA */
6108 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6111 /* PREFIX_VEX_0F38AB */
6115 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6118 /* PREFIX_VEX_0F38AC */
6122 { "vfnmadd213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6125 /* PREFIX_VEX_0F38AD */
6129 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6132 /* PREFIX_VEX_0F38AE */
6136 { "vfnmsub213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6139 /* PREFIX_VEX_0F38AF */
6143 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6146 /* PREFIX_VEX_0F38B6 */
6150 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6153 /* PREFIX_VEX_0F38B7 */
6157 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6160 /* PREFIX_VEX_0F38B8 */
6164 { "vfmadd231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6167 /* PREFIX_VEX_0F38B9 */
6171 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6174 /* PREFIX_VEX_0F38BA */
6178 { "vfmsub231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6181 /* PREFIX_VEX_0F38BB */
6185 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6188 /* PREFIX_VEX_0F38BC */
6192 { "vfnmadd231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6195 /* PREFIX_VEX_0F38BD */
6199 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6202 /* PREFIX_VEX_0F38BE */
6206 { "vfnmsub231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6209 /* PREFIX_VEX_0F38BF */
6213 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6216 /* PREFIX_VEX_0F38CF */
6220 { VEX_W_TABLE (VEX_W_0F38CF_P_2
) },
6223 /* PREFIX_VEX_0F38DB */
6227 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6230 /* PREFIX_VEX_0F38DC */
6234 { "vaesenc", { XM
, Vex
, EXx
}, 0 },
6237 /* PREFIX_VEX_0F38DD */
6241 { "vaesenclast", { XM
, Vex
, EXx
}, 0 },
6244 /* PREFIX_VEX_0F38DE */
6248 { "vaesdec", { XM
, Vex
, EXx
}, 0 },
6251 /* PREFIX_VEX_0F38DF */
6255 { "vaesdeclast", { XM
, Vex
, EXx
}, 0 },
6258 /* PREFIX_VEX_0F38F2 */
6260 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6263 /* PREFIX_VEX_0F38F3_REG_1 */
6265 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6268 /* PREFIX_VEX_0F38F3_REG_2 */
6270 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6273 /* PREFIX_VEX_0F38F3_REG_3 */
6275 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6278 /* PREFIX_VEX_0F38F5 */
6280 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6281 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6283 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6286 /* PREFIX_VEX_0F38F6 */
6291 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6294 /* PREFIX_VEX_0F38F7 */
6296 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6297 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6298 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6299 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6302 /* PREFIX_VEX_0F3A00 */
6306 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6309 /* PREFIX_VEX_0F3A01 */
6313 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6316 /* PREFIX_VEX_0F3A02 */
6320 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6323 /* PREFIX_VEX_0F3A04 */
6327 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6330 /* PREFIX_VEX_0F3A05 */
6334 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6337 /* PREFIX_VEX_0F3A06 */
6341 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6344 /* PREFIX_VEX_0F3A08 */
6348 { "vroundps", { XM
, EXx
, Ib
}, 0 },
6351 /* PREFIX_VEX_0F3A09 */
6355 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
6358 /* PREFIX_VEX_0F3A0A */
6362 { "vroundss", { XMScalar
, VexScalar
, EXxmm_md
, Ib
}, 0 },
6365 /* PREFIX_VEX_0F3A0B */
6369 { "vroundsd", { XMScalar
, VexScalar
, EXxmm_mq
, Ib
}, 0 },
6372 /* PREFIX_VEX_0F3A0C */
6376 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
6379 /* PREFIX_VEX_0F3A0D */
6383 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
6386 /* PREFIX_VEX_0F3A0E */
6390 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
6393 /* PREFIX_VEX_0F3A0F */
6397 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
6400 /* PREFIX_VEX_0F3A14 */
6404 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6407 /* PREFIX_VEX_0F3A15 */
6411 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6414 /* PREFIX_VEX_0F3A16 */
6418 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6421 /* PREFIX_VEX_0F3A17 */
6425 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6428 /* PREFIX_VEX_0F3A18 */
6432 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6435 /* PREFIX_VEX_0F3A19 */
6439 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6442 /* PREFIX_VEX_0F3A1D */
6446 { VEX_W_TABLE (VEX_W_0F3A1D_P_2
) },
6449 /* PREFIX_VEX_0F3A20 */
6453 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6456 /* PREFIX_VEX_0F3A21 */
6460 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6463 /* PREFIX_VEX_0F3A22 */
6467 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6470 /* PREFIX_VEX_0F3A30 */
6474 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6477 /* PREFIX_VEX_0F3A31 */
6481 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6484 /* PREFIX_VEX_0F3A32 */
6488 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6491 /* PREFIX_VEX_0F3A33 */
6495 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6498 /* PREFIX_VEX_0F3A38 */
6502 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6505 /* PREFIX_VEX_0F3A39 */
6509 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6512 /* PREFIX_VEX_0F3A40 */
6516 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
6519 /* PREFIX_VEX_0F3A41 */
6523 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6526 /* PREFIX_VEX_0F3A42 */
6530 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
6533 /* PREFIX_VEX_0F3A44 */
6537 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, 0 },
6540 /* PREFIX_VEX_0F3A46 */
6544 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6547 /* PREFIX_VEX_0F3A48 */
6551 { "vpermil2ps", { XM
, Vex
, EXx
, XMVexI4
, VexI4
}, 0 },
6554 /* PREFIX_VEX_0F3A49 */
6558 { "vpermil2pd", { XM
, Vex
, EXx
, XMVexI4
, VexI4
}, 0 },
6561 /* PREFIX_VEX_0F3A4A */
6565 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6568 /* PREFIX_VEX_0F3A4B */
6572 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6575 /* PREFIX_VEX_0F3A4C */
6579 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6582 /* PREFIX_VEX_0F3A5C */
6586 { "vfmaddsubps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6589 /* PREFIX_VEX_0F3A5D */
6593 { "vfmaddsubpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6596 /* PREFIX_VEX_0F3A5E */
6600 { "vfmsubaddps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6603 /* PREFIX_VEX_0F3A5F */
6607 { "vfmsubaddpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6610 /* PREFIX_VEX_0F3A60 */
6614 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6618 /* PREFIX_VEX_0F3A61 */
6622 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6625 /* PREFIX_VEX_0F3A62 */
6629 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6632 /* PREFIX_VEX_0F3A63 */
6636 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6639 /* PREFIX_VEX_0F3A68 */
6643 { "vfmaddps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6646 /* PREFIX_VEX_0F3A69 */
6650 { "vfmaddpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6653 /* PREFIX_VEX_0F3A6A */
6657 { "vfmaddss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, 0 },
6660 /* PREFIX_VEX_0F3A6B */
6664 { "vfmaddsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, 0 },
6667 /* PREFIX_VEX_0F3A6C */
6671 { "vfmsubps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6674 /* PREFIX_VEX_0F3A6D */
6678 { "vfmsubpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6681 /* PREFIX_VEX_0F3A6E */
6685 { "vfmsubss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, 0 },
6688 /* PREFIX_VEX_0F3A6F */
6692 { "vfmsubsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, 0 },
6695 /* PREFIX_VEX_0F3A78 */
6699 { "vfnmaddps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6702 /* PREFIX_VEX_0F3A79 */
6706 { "vfnmaddpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6709 /* PREFIX_VEX_0F3A7A */
6713 { "vfnmaddss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, 0 },
6716 /* PREFIX_VEX_0F3A7B */
6720 { "vfnmaddsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, 0 },
6723 /* PREFIX_VEX_0F3A7C */
6727 { "vfnmsubps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6731 /* PREFIX_VEX_0F3A7D */
6735 { "vfnmsubpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
6738 /* PREFIX_VEX_0F3A7E */
6742 { "vfnmsubss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, 0 },
6745 /* PREFIX_VEX_0F3A7F */
6749 { "vfnmsubsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, 0 },
6752 /* PREFIX_VEX_0F3ACE */
6756 { VEX_W_TABLE (VEX_W_0F3ACE_P_2
) },
6759 /* PREFIX_VEX_0F3ACF */
6763 { VEX_W_TABLE (VEX_W_0F3ACF_P_2
) },
6766 /* PREFIX_VEX_0F3ADF */
6770 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6773 /* PREFIX_VEX_0F3AF0 */
6778 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6781 #include "i386-dis-evex-prefix.h"
6784 static const struct dis386 x86_64_table
[][2] = {
6787 { "pushP", { es
}, 0 },
6792 { "popP", { es
}, 0 },
6797 { "pushP", { cs
}, 0 },
6802 { "pushP", { ss
}, 0 },
6807 { "popP", { ss
}, 0 },
6812 { "pushP", { ds
}, 0 },
6817 { "popP", { ds
}, 0 },
6822 { "daa", { XX
}, 0 },
6827 { "das", { XX
}, 0 },
6832 { "aaa", { XX
}, 0 },
6837 { "aas", { XX
}, 0 },
6842 { "pushaP", { XX
}, 0 },
6847 { "popaP", { XX
}, 0 },
6852 { MOD_TABLE (MOD_62_32BIT
) },
6853 { EVEX_TABLE (EVEX_0F
) },
6858 { "arpl", { Ew
, Gw
}, 0 },
6859 { "movs", { { OP_G
, movsxd_mode
}, { MOVSXD_Fixup
, movsxd_mode
} }, 0 },
6864 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6865 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6870 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6871 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6876 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
6877 { REG_TABLE (REG_80
) },
6882 { "{l|}call{T|}", { Ap
}, 0 },
6887 { "retP", { Iw
, BND
}, 0 },
6888 { "ret@", { Iw
, BND
}, 0 },
6893 { "retP", { BND
}, 0 },
6894 { "ret@", { BND
}, 0 },
6899 { MOD_TABLE (MOD_C4_32BIT
) },
6900 { VEX_C4_TABLE (VEX_0F
) },
6905 { MOD_TABLE (MOD_C5_32BIT
) },
6906 { VEX_C5_TABLE (VEX_0F
) },
6911 { "into", { XX
}, 0 },
6916 { "aam", { Ib
}, 0 },
6921 { "aad", { Ib
}, 0 },
6926 { "callP", { Jv
, BND
}, 0 },
6927 { "call@", { Jv
, BND
}, 0 }
6932 { "jmpP", { Jv
, BND
}, 0 },
6933 { "jmp@", { Jv
, BND
}, 0 }
6938 { "{l|}jmp{T|}", { Ap
}, 0 },
6941 /* X86_64_0F01_REG_0 */
6943 { "sgdt{Q|Q}", { M
}, 0 },
6944 { "sgdt", { M
}, 0 },
6947 /* X86_64_0F01_REG_1 */
6949 { "sidt{Q|Q}", { M
}, 0 },
6950 { "sidt", { M
}, 0 },
6953 /* X86_64_0F01_REG_2 */
6955 { "lgdt{Q|Q}", { M
}, 0 },
6956 { "lgdt", { M
}, 0 },
6959 /* X86_64_0F01_REG_3 */
6961 { "lidt{Q|Q}", { M
}, 0 },
6962 { "lidt", { M
}, 0 },
6965 /* X86_64_VEX_0F3849 */
6968 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64
) },
6971 /* X86_64_VEX_0F384B */
6974 { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64
) },
6977 /* X86_64_VEX_0F385C */
6980 { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64
) },
6983 /* X86_64_VEX_0F385E */
6986 { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64
) },
6990 static const struct dis386 three_byte_table
[][256] = {
6992 /* THREE_BYTE_0F38 */
6995 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
6996 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
6997 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
6998 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
6999 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
7000 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
7001 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
7002 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
7004 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
7005 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
7006 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
7007 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
7013 { PREFIX_TABLE (PREFIX_0F3810
) },
7017 { PREFIX_TABLE (PREFIX_0F3814
) },
7018 { PREFIX_TABLE (PREFIX_0F3815
) },
7020 { PREFIX_TABLE (PREFIX_0F3817
) },
7026 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
7027 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
7028 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
7031 { PREFIX_TABLE (PREFIX_0F3820
) },
7032 { PREFIX_TABLE (PREFIX_0F3821
) },
7033 { PREFIX_TABLE (PREFIX_0F3822
) },
7034 { PREFIX_TABLE (PREFIX_0F3823
) },
7035 { PREFIX_TABLE (PREFIX_0F3824
) },
7036 { PREFIX_TABLE (PREFIX_0F3825
) },
7040 { PREFIX_TABLE (PREFIX_0F3828
) },
7041 { PREFIX_TABLE (PREFIX_0F3829
) },
7042 { PREFIX_TABLE (PREFIX_0F382A
) },
7043 { PREFIX_TABLE (PREFIX_0F382B
) },
7049 { PREFIX_TABLE (PREFIX_0F3830
) },
7050 { PREFIX_TABLE (PREFIX_0F3831
) },
7051 { PREFIX_TABLE (PREFIX_0F3832
) },
7052 { PREFIX_TABLE (PREFIX_0F3833
) },
7053 { PREFIX_TABLE (PREFIX_0F3834
) },
7054 { PREFIX_TABLE (PREFIX_0F3835
) },
7056 { PREFIX_TABLE (PREFIX_0F3837
) },
7058 { PREFIX_TABLE (PREFIX_0F3838
) },
7059 { PREFIX_TABLE (PREFIX_0F3839
) },
7060 { PREFIX_TABLE (PREFIX_0F383A
) },
7061 { PREFIX_TABLE (PREFIX_0F383B
) },
7062 { PREFIX_TABLE (PREFIX_0F383C
) },
7063 { PREFIX_TABLE (PREFIX_0F383D
) },
7064 { PREFIX_TABLE (PREFIX_0F383E
) },
7065 { PREFIX_TABLE (PREFIX_0F383F
) },
7067 { PREFIX_TABLE (PREFIX_0F3840
) },
7068 { PREFIX_TABLE (PREFIX_0F3841
) },
7139 { PREFIX_TABLE (PREFIX_0F3880
) },
7140 { PREFIX_TABLE (PREFIX_0F3881
) },
7141 { PREFIX_TABLE (PREFIX_0F3882
) },
7220 { PREFIX_TABLE (PREFIX_0F38C8
) },
7221 { PREFIX_TABLE (PREFIX_0F38C9
) },
7222 { PREFIX_TABLE (PREFIX_0F38CA
) },
7223 { PREFIX_TABLE (PREFIX_0F38CB
) },
7224 { PREFIX_TABLE (PREFIX_0F38CC
) },
7225 { PREFIX_TABLE (PREFIX_0F38CD
) },
7227 { PREFIX_TABLE (PREFIX_0F38CF
) },
7241 { PREFIX_TABLE (PREFIX_0F38DB
) },
7242 { PREFIX_TABLE (PREFIX_0F38DC
) },
7243 { PREFIX_TABLE (PREFIX_0F38DD
) },
7244 { PREFIX_TABLE (PREFIX_0F38DE
) },
7245 { PREFIX_TABLE (PREFIX_0F38DF
) },
7265 { PREFIX_TABLE (PREFIX_0F38F0
) },
7266 { PREFIX_TABLE (PREFIX_0F38F1
) },
7270 { PREFIX_TABLE (PREFIX_0F38F5
) },
7271 { PREFIX_TABLE (PREFIX_0F38F6
) },
7274 { PREFIX_TABLE (PREFIX_0F38F8
) },
7275 { PREFIX_TABLE (PREFIX_0F38F9
) },
7283 /* THREE_BYTE_0F3A */
7295 { PREFIX_TABLE (PREFIX_0F3A08
) },
7296 { PREFIX_TABLE (PREFIX_0F3A09
) },
7297 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7298 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7299 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7300 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7301 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7302 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7308 { PREFIX_TABLE (PREFIX_0F3A14
) },
7309 { PREFIX_TABLE (PREFIX_0F3A15
) },
7310 { PREFIX_TABLE (PREFIX_0F3A16
) },
7311 { PREFIX_TABLE (PREFIX_0F3A17
) },
7322 { PREFIX_TABLE (PREFIX_0F3A20
) },
7323 { PREFIX_TABLE (PREFIX_0F3A21
) },
7324 { PREFIX_TABLE (PREFIX_0F3A22
) },
7358 { PREFIX_TABLE (PREFIX_0F3A40
) },
7359 { PREFIX_TABLE (PREFIX_0F3A41
) },
7360 { PREFIX_TABLE (PREFIX_0F3A42
) },
7362 { PREFIX_TABLE (PREFIX_0F3A44
) },
7394 { PREFIX_TABLE (PREFIX_0F3A60
) },
7395 { PREFIX_TABLE (PREFIX_0F3A61
) },
7396 { PREFIX_TABLE (PREFIX_0F3A62
) },
7397 { PREFIX_TABLE (PREFIX_0F3A63
) },
7515 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7517 { PREFIX_TABLE (PREFIX_0F3ACE
) },
7518 { PREFIX_TABLE (PREFIX_0F3ACF
) },
7536 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7576 static const struct dis386 xop_table
[][256] = {
7729 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85
) },
7730 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86
) },
7731 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87
) },
7739 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E
) },
7740 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F
) },
7747 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95
) },
7748 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96
) },
7749 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97
) },
7757 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E
) },
7758 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F
) },
7762 { "vpcmov", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7763 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3
) },
7766 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6
) },
7784 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6
) },
7796 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0
) },
7797 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1
) },
7798 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2
) },
7799 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3
) },
7809 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7810 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7811 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7812 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7845 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7846 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7847 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7848 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
7872 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01
) },
7873 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02
) },
7891 { MOD_TABLE (MOD_VEX_0FXOP_09_12
) },
8015 { VEX_W_TABLE (VEX_W_0FXOP_09_80
) },
8016 { VEX_W_TABLE (VEX_W_0FXOP_09_81
) },
8017 { VEX_W_TABLE (VEX_W_0FXOP_09_82
) },
8018 { VEX_W_TABLE (VEX_W_0FXOP_09_83
) },
8033 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90
) },
8034 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91
) },
8035 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92
) },
8036 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93
) },
8037 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94
) },
8038 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95
) },
8039 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96
) },
8040 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97
) },
8042 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98
) },
8043 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99
) },
8044 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A
) },
8045 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B
) },
8088 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1
) },
8089 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2
) },
8090 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3
) },
8093 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6
) },
8094 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7
) },
8099 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB
) },
8106 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1
) },
8107 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2
) },
8108 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3
) },
8111 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6
) },
8112 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7
) },
8117 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB
) },
8124 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1
) },
8125 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2
) },
8126 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3
) },
8180 { "bextrS", { Gdq
, Edq
, Id
}, 0 },
8182 { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12
) },
8452 static const struct dis386 vex_table
[][256] = {
8474 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8475 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8476 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8477 { MOD_TABLE (MOD_VEX_0F13
) },
8478 { "vunpcklpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8479 { "vunpckhpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8480 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8481 { MOD_TABLE (MOD_VEX_0F17
) },
8501 { "vmovapX", { XM
, EXx
}, PREFIX_OPCODE
},
8502 { "vmovapX", { EXxS
, XM
}, PREFIX_OPCODE
},
8503 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8504 { MOD_TABLE (MOD_VEX_0F2B
) },
8505 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8506 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8507 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8508 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8529 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8530 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8532 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8533 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8534 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8535 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8539 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8540 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8546 { MOD_TABLE (MOD_VEX_0F50
) },
8547 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8548 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8549 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8550 { "vandpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8551 { "vandnpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8552 { "vorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8553 { "vxorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8555 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8556 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8557 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8558 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8559 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8560 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8561 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8562 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8564 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8565 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8566 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8567 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8568 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8569 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8570 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8571 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8573 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8574 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8575 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8576 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8577 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8578 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8579 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8580 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8582 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8583 { REG_TABLE (REG_VEX_0F71
) },
8584 { REG_TABLE (REG_VEX_0F72
) },
8585 { REG_TABLE (REG_VEX_0F73
) },
8586 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8587 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8588 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8589 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8595 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8596 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8597 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8598 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8618 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8619 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8620 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8621 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8627 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8628 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8651 { REG_TABLE (REG_VEX_0FAE
) },
8674 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8676 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8677 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8678 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, PREFIX_OPCODE
},
8690 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8691 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8692 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8693 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8694 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8695 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8696 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8697 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8699 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8700 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8701 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8702 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8703 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8704 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8705 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8706 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8708 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8709 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8710 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8711 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8712 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8713 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8714 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8715 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8717 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8718 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8719 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8720 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8721 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8722 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8723 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8724 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8726 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8727 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8728 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8729 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8730 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8731 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8732 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8733 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8735 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8736 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8737 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8738 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8739 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8740 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8741 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8747 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8748 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8749 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8750 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8751 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8752 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8753 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8754 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8756 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8758 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8759 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8760 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8762 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8763 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8768 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8771 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8774 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8775 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8776 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8779 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8780 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8783 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8784 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8785 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8786 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8787 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8788 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8792 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8793 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8794 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8795 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8796 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8797 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8798 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8799 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8801 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8802 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8803 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8804 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8805 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8806 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8807 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8808 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8810 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8811 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8812 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8813 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8814 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8815 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8816 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8817 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8819 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8820 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8824 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8825 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8826 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8829 { X86_64_TABLE (X86_64_VEX_0F3849
) },
8831 { X86_64_TABLE (X86_64_VEX_0F384B
) },
8846 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8847 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8848 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
8850 { X86_64_TABLE (X86_64_VEX_0F385C
) },
8852 { X86_64_TABLE (X86_64_VEX_0F385E
) },
8882 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
8883 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
8904 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
8906 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
8909 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
8910 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
8911 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
8912 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
8916 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
8918 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
8919 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
8920 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
8921 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
8922 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
8923 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
8924 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
8925 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
8934 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
8936 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
8939 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
8940 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
8941 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
8942 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
8943 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
8951 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
8952 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
8954 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
8955 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
8956 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
8957 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
8958 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
8959 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
8960 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
8961 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
8979 { PREFIX_TABLE (PREFIX_VEX_0F38CF
) },
8993 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
8994 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
8995 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
8996 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
8997 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
9019 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
9020 { REG_TABLE (REG_VEX_0F38F3
) },
9022 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
9023 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
9024 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
9038 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
9039 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
9040 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
9042 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
9043 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
9047 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
9048 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9049 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9050 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9051 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9052 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9053 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9054 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9060 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9061 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9062 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9063 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9065 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9066 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9070 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9074 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9075 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9076 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9092 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9093 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9094 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9095 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9101 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9102 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9110 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9111 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9112 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9114 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9116 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9119 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9120 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9121 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9122 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9123 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9141 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9142 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9143 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9144 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9146 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9147 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9148 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9149 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9155 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9156 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9157 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9158 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9159 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9160 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9161 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9162 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9173 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9174 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9175 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9176 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9177 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9178 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9179 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9180 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9269 { PREFIX_TABLE(PREFIX_VEX_0F3ACE
) },
9270 { PREFIX_TABLE(PREFIX_VEX_0F3ACF
) },
9288 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9308 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9328 #include "i386-dis-evex.h"
9330 static const struct dis386 vex_len_table
[][2] = {
9331 /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
9333 { "vmovlpX", { XM
, Vex
, EXq
}, 0 },
9336 /* VEX_LEN_0F12_P_0_M_1 */
9338 { "vmovhlps", { XM
, Vex
, EXq
}, 0 },
9341 /* VEX_LEN_0F13_M_0 */
9343 { "vmovlpX", { EXq
, XM
}, PREFIX_OPCODE
},
9346 /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
9348 { "vmovhpX", { XM
, Vex
, EXq
}, 0 },
9351 /* VEX_LEN_0F16_P_0_M_1 */
9353 { "vmovlhps", { XM
, Vex
, EXq
}, 0 },
9356 /* VEX_LEN_0F17_M_0 */
9358 { "vmovhpX", { EXq
, XM
}, PREFIX_OPCODE
},
9361 /* VEX_LEN_0F41_P_0 */
9364 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9366 /* VEX_LEN_0F41_P_2 */
9369 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9371 /* VEX_LEN_0F42_P_0 */
9374 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9376 /* VEX_LEN_0F42_P_2 */
9379 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9381 /* VEX_LEN_0F44_P_0 */
9383 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9385 /* VEX_LEN_0F44_P_2 */
9387 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9389 /* VEX_LEN_0F45_P_0 */
9392 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9394 /* VEX_LEN_0F45_P_2 */
9397 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9399 /* VEX_LEN_0F46_P_0 */
9402 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9404 /* VEX_LEN_0F46_P_2 */
9407 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9409 /* VEX_LEN_0F47_P_0 */
9412 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9414 /* VEX_LEN_0F47_P_2 */
9417 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9419 /* VEX_LEN_0F4A_P_0 */
9422 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9424 /* VEX_LEN_0F4A_P_2 */
9427 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9429 /* VEX_LEN_0F4B_P_0 */
9432 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9434 /* VEX_LEN_0F4B_P_2 */
9437 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9440 /* VEX_LEN_0F6E_P_2 */
9442 { "vmovK", { XMScalar
, Edq
}, 0 },
9445 /* VEX_LEN_0F77_P_1 */
9447 { "vzeroupper", { XX
}, 0 },
9448 { "vzeroall", { XX
}, 0 },
9451 /* VEX_LEN_0F7E_P_1 */
9453 { "vmovq", { XMScalar
, EXxmm_mq
}, 0 },
9456 /* VEX_LEN_0F7E_P_2 */
9458 { "vmovK", { Edq
, XMScalar
}, 0 },
9461 /* VEX_LEN_0F90_P_0 */
9463 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9466 /* VEX_LEN_0F90_P_2 */
9468 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9471 /* VEX_LEN_0F91_P_0 */
9473 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9476 /* VEX_LEN_0F91_P_2 */
9478 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9481 /* VEX_LEN_0F92_P_0 */
9483 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9486 /* VEX_LEN_0F92_P_2 */
9488 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9491 /* VEX_LEN_0F92_P_3 */
9493 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0
) },
9496 /* VEX_LEN_0F93_P_0 */
9498 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9501 /* VEX_LEN_0F93_P_2 */
9503 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9506 /* VEX_LEN_0F93_P_3 */
9508 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0
) },
9511 /* VEX_LEN_0F98_P_0 */
9513 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9516 /* VEX_LEN_0F98_P_2 */
9518 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9521 /* VEX_LEN_0F99_P_0 */
9523 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9526 /* VEX_LEN_0F99_P_2 */
9528 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9531 /* VEX_LEN_0FAE_R_2_M_0 */
9533 { "vldmxcsr", { Md
}, 0 },
9536 /* VEX_LEN_0FAE_R_3_M_0 */
9538 { "vstmxcsr", { Md
}, 0 },
9541 /* VEX_LEN_0FC4_P_2 */
9543 { "vpinsrw", { XM
, Vex
, Edqw
, Ib
}, 0 },
9546 /* VEX_LEN_0FC5_P_2 */
9548 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
9551 /* VEX_LEN_0FD6_P_2 */
9553 { "vmovq", { EXqS
, XMScalar
}, 0 },
9556 /* VEX_LEN_0FF7_P_2 */
9558 { "vmaskmovdqu", { XM
, XS
}, 0 },
9561 /* VEX_LEN_0F3816_P_2 */
9564 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9567 /* VEX_LEN_0F3819_P_2 */
9570 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9573 /* VEX_LEN_0F381A_P_2_M_0 */
9576 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0_L_0
) },
9579 /* VEX_LEN_0F3836_P_2 */
9582 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9585 /* VEX_LEN_0F3841_P_2 */
9587 { "vphminposuw", { XM
, EXx
}, 0 },
9590 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
9592 { "ldtilecfg", { M
}, 0 },
9595 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
9597 { "tilerelease", { Skip_MODRM
}, 0 },
9600 /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
9602 { "sttilecfg", { M
}, 0 },
9605 /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
9607 { "tilezero", { TMM
, Skip_MODRM
}, 0 },
9610 /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
9612 { "tilestored", { MVexSIBMEM
, TMM
}, 0 },
9614 /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
9616 { "tileloaddt1", { TMM
, MVexSIBMEM
}, 0 },
9619 /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
9621 { "tileloadd", { TMM
, MVexSIBMEM
}, 0 },
9624 /* VEX_LEN_0F385A_P_2_M_0 */
9627 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0_L_0
) },
9630 /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
9632 { "tdpbf16ps", { TMM
, EXtmm
, VexTmm
}, 0 },
9635 /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
9637 { "tdpbuud", {TMM
, EXtmm
, VexTmm
}, 0 },
9640 /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
9642 { "tdpbsud", {TMM
, EXtmm
, VexTmm
}, 0 },
9645 /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
9647 { "tdpbusd", {TMM
, EXtmm
, VexTmm
}, 0 },
9650 /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
9652 { "tdpbssd", {TMM
, EXtmm
, VexTmm
}, 0 },
9655 /* VEX_LEN_0F38DB_P_2 */
9657 { "vaesimc", { XM
, EXx
}, 0 },
9660 /* VEX_LEN_0F38F2_P_0 */
9662 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
9665 /* VEX_LEN_0F38F3_R_1_P_0 */
9667 { "blsrS", { VexGdq
, Edq
}, 0 },
9670 /* VEX_LEN_0F38F3_R_2_P_0 */
9672 { "blsmskS", { VexGdq
, Edq
}, 0 },
9675 /* VEX_LEN_0F38F3_R_3_P_0 */
9677 { "blsiS", { VexGdq
, Edq
}, 0 },
9680 /* VEX_LEN_0F38F5_P_0 */
9682 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
9685 /* VEX_LEN_0F38F5_P_1 */
9687 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
9690 /* VEX_LEN_0F38F5_P_3 */
9692 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
9695 /* VEX_LEN_0F38F6_P_3 */
9697 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
9700 /* VEX_LEN_0F38F7_P_0 */
9702 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
9705 /* VEX_LEN_0F38F7_P_1 */
9707 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
9710 /* VEX_LEN_0F38F7_P_2 */
9712 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
9715 /* VEX_LEN_0F38F7_P_3 */
9717 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
9720 /* VEX_LEN_0F3A00_P_2 */
9723 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
9726 /* VEX_LEN_0F3A01_P_2 */
9729 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
9732 /* VEX_LEN_0F3A06_P_2 */
9735 { VEX_W_TABLE (VEX_W_0F3A06_P_2_L_0
) },
9738 /* VEX_LEN_0F3A14_P_2 */
9740 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
9743 /* VEX_LEN_0F3A15_P_2 */
9745 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
9748 /* VEX_LEN_0F3A16_P_2 */
9750 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
9753 /* VEX_LEN_0F3A17_P_2 */
9755 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
9758 /* VEX_LEN_0F3A18_P_2 */
9761 { VEX_W_TABLE (VEX_W_0F3A18_P_2_L_0
) },
9764 /* VEX_LEN_0F3A19_P_2 */
9767 { VEX_W_TABLE (VEX_W_0F3A19_P_2_L_0
) },
9770 /* VEX_LEN_0F3A20_P_2 */
9772 { "vpinsrb", { XM
, Vex
, Edqb
, Ib
}, 0 },
9775 /* VEX_LEN_0F3A21_P_2 */
9777 { "vinsertps", { XM
, Vex
, EXd
, Ib
}, 0 },
9780 /* VEX_LEN_0F3A22_P_2 */
9782 { "vpinsrK", { XM
, Vex
, Edq
, Ib
}, 0 },
9785 /* VEX_LEN_0F3A30_P_2 */
9787 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
9790 /* VEX_LEN_0F3A31_P_2 */
9792 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
9795 /* VEX_LEN_0F3A32_P_2 */
9797 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
9800 /* VEX_LEN_0F3A33_P_2 */
9802 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
9805 /* VEX_LEN_0F3A38_P_2 */
9808 { VEX_W_TABLE (VEX_W_0F3A38_P_2_L_0
) },
9811 /* VEX_LEN_0F3A39_P_2 */
9814 { VEX_W_TABLE (VEX_W_0F3A39_P_2_L_0
) },
9817 /* VEX_LEN_0F3A41_P_2 */
9819 { "vdppd", { XM
, Vex
, EXx
, Ib
}, 0 },
9822 /* VEX_LEN_0F3A46_P_2 */
9825 { VEX_W_TABLE (VEX_W_0F3A46_P_2_L_0
) },
9828 /* VEX_LEN_0F3A60_P_2 */
9830 { "vpcmpestrm!%LQ", { XM
, EXx
, Ib
}, 0 },
9833 /* VEX_LEN_0F3A61_P_2 */
9835 { "vpcmpestri!%LQ", { XM
, EXx
, Ib
}, 0 },
9838 /* VEX_LEN_0F3A62_P_2 */
9840 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
9843 /* VEX_LEN_0F3A63_P_2 */
9845 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
9848 /* VEX_LEN_0F3ADF_P_2 */
9850 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
9853 /* VEX_LEN_0F3AF0_P_3 */
9855 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
9858 /* VEX_LEN_0FXOP_08_85 */
9860 { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0
) },
9863 /* VEX_LEN_0FXOP_08_86 */
9865 { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0
) },
9868 /* VEX_LEN_0FXOP_08_87 */
9870 { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0
) },
9873 /* VEX_LEN_0FXOP_08_8E */
9875 { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0
) },
9878 /* VEX_LEN_0FXOP_08_8F */
9880 { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0
) },
9883 /* VEX_LEN_0FXOP_08_95 */
9885 { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0
) },
9888 /* VEX_LEN_0FXOP_08_96 */
9890 { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0
) },
9893 /* VEX_LEN_0FXOP_08_97 */
9895 { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0
) },
9898 /* VEX_LEN_0FXOP_08_9E */
9900 { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0
) },
9903 /* VEX_LEN_0FXOP_08_9F */
9905 { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0
) },
9908 /* VEX_LEN_0FXOP_08_A3 */
9910 { "vpperm", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
9913 /* VEX_LEN_0FXOP_08_A6 */
9915 { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0
) },
9918 /* VEX_LEN_0FXOP_08_B6 */
9920 { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0
) },
9923 /* VEX_LEN_0FXOP_08_C0 */
9925 { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0
) },
9928 /* VEX_LEN_0FXOP_08_C1 */
9930 { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0
) },
9933 /* VEX_LEN_0FXOP_08_C2 */
9935 { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0
) },
9938 /* VEX_LEN_0FXOP_08_C3 */
9940 { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0
) },
9943 /* VEX_LEN_0FXOP_08_CC */
9945 { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0
) },
9948 /* VEX_LEN_0FXOP_08_CD */
9950 { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0
) },
9953 /* VEX_LEN_0FXOP_08_CE */
9955 { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0
) },
9958 /* VEX_LEN_0FXOP_08_CF */
9960 { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0
) },
9963 /* VEX_LEN_0FXOP_08_EC */
9965 { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0
) },
9968 /* VEX_LEN_0FXOP_08_ED */
9970 { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0
) },
9973 /* VEX_LEN_0FXOP_08_EE */
9975 { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0
) },
9978 /* VEX_LEN_0FXOP_08_EF */
9980 { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0
) },
9983 /* VEX_LEN_0FXOP_09_01 */
9985 { REG_TABLE (REG_0FXOP_09_01_L_0
) },
9988 /* VEX_LEN_0FXOP_09_02 */
9990 { REG_TABLE (REG_0FXOP_09_02_L_0
) },
9993 /* VEX_LEN_0FXOP_09_12_M_1 */
9995 { REG_TABLE (REG_0FXOP_09_12_M_1_L_0
) },
9998 /* VEX_LEN_0FXOP_09_82_W_0 */
10000 { "vfrczss", { XM
, EXd
}, 0 },
10003 /* VEX_LEN_0FXOP_09_83_W_0 */
10005 { "vfrczsd", { XM
, EXq
}, 0 },
10008 /* VEX_LEN_0FXOP_09_90 */
10010 { "vprotb", { XM
, EXx
, VexW
}, 0 },
10013 /* VEX_LEN_0FXOP_09_91 */
10015 { "vprotw", { XM
, EXx
, VexW
}, 0 },
10018 /* VEX_LEN_0FXOP_09_92 */
10020 { "vprotd", { XM
, EXx
, VexW
}, 0 },
10023 /* VEX_LEN_0FXOP_09_93 */
10025 { "vprotq", { XM
, EXx
, VexW
}, 0 },
10028 /* VEX_LEN_0FXOP_09_94 */
10030 { "vpshlb", { XM
, EXx
, VexW
}, 0 },
10033 /* VEX_LEN_0FXOP_09_95 */
10035 { "vpshlw", { XM
, EXx
, VexW
}, 0 },
10038 /* VEX_LEN_0FXOP_09_96 */
10040 { "vpshld", { XM
, EXx
, VexW
}, 0 },
10043 /* VEX_LEN_0FXOP_09_97 */
10045 { "vpshlq", { XM
, EXx
, VexW
}, 0 },
10048 /* VEX_LEN_0FXOP_09_98 */
10050 { "vpshab", { XM
, EXx
, VexW
}, 0 },
10053 /* VEX_LEN_0FXOP_09_99 */
10055 { "vpshaw", { XM
, EXx
, VexW
}, 0 },
10058 /* VEX_LEN_0FXOP_09_9A */
10060 { "vpshad", { XM
, EXx
, VexW
}, 0 },
10063 /* VEX_LEN_0FXOP_09_9B */
10065 { "vpshaq", { XM
, EXx
, VexW
}, 0 },
10068 /* VEX_LEN_0FXOP_09_C1 */
10070 { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0
) },
10073 /* VEX_LEN_0FXOP_09_C2 */
10075 { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0
) },
10078 /* VEX_LEN_0FXOP_09_C3 */
10080 { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0
) },
10083 /* VEX_LEN_0FXOP_09_C6 */
10085 { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0
) },
10088 /* VEX_LEN_0FXOP_09_C7 */
10090 { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0
) },
10093 /* VEX_LEN_0FXOP_09_CB */
10095 { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0
) },
10098 /* VEX_LEN_0FXOP_09_D1 */
10100 { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0
) },
10103 /* VEX_LEN_0FXOP_09_D2 */
10105 { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0
) },
10108 /* VEX_LEN_0FXOP_09_D3 */
10110 { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0
) },
10113 /* VEX_LEN_0FXOP_09_D6 */
10115 { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0
) },
10118 /* VEX_LEN_0FXOP_09_D7 */
10120 { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0
) },
10123 /* VEX_LEN_0FXOP_09_DB */
10125 { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0
) },
10128 /* VEX_LEN_0FXOP_09_E1 */
10130 { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0
) },
10133 /* VEX_LEN_0FXOP_09_E2 */
10135 { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0
) },
10138 /* VEX_LEN_0FXOP_09_E3 */
10140 { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0
) },
10143 /* VEX_LEN_0FXOP_0A_12 */
10145 { REG_TABLE (REG_0FXOP_0A_12_L_0
) },
10149 #include "i386-dis-evex-len.h"
10151 static const struct dis386 vex_w_table
[][2] = {
10153 /* VEX_W_0F41_P_0_LEN_1 */
10154 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
10155 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
10158 /* VEX_W_0F41_P_2_LEN_1 */
10159 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
10160 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
10163 /* VEX_W_0F42_P_0_LEN_1 */
10164 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
10165 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
10168 /* VEX_W_0F42_P_2_LEN_1 */
10169 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
10170 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
10173 /* VEX_W_0F44_P_0_LEN_0 */
10174 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
10175 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
10178 /* VEX_W_0F44_P_2_LEN_0 */
10179 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
10180 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
10183 /* VEX_W_0F45_P_0_LEN_1 */
10184 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
10185 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
10188 /* VEX_W_0F45_P_2_LEN_1 */
10189 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
10190 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
10193 /* VEX_W_0F46_P_0_LEN_1 */
10194 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
10195 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
10198 /* VEX_W_0F46_P_2_LEN_1 */
10199 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
10200 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
10203 /* VEX_W_0F47_P_0_LEN_1 */
10204 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
10205 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
10208 /* VEX_W_0F47_P_2_LEN_1 */
10209 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
10210 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
10213 /* VEX_W_0F4A_P_0_LEN_1 */
10214 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
10215 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
10218 /* VEX_W_0F4A_P_2_LEN_1 */
10219 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
10220 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
10223 /* VEX_W_0F4B_P_0_LEN_1 */
10224 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
10225 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
10228 /* VEX_W_0F4B_P_2_LEN_1 */
10229 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
10232 /* VEX_W_0F90_P_0_LEN_0 */
10233 { "kmovw", { MaskG
, MaskE
}, 0 },
10234 { "kmovq", { MaskG
, MaskE
}, 0 },
10237 /* VEX_W_0F90_P_2_LEN_0 */
10238 { "kmovb", { MaskG
, MaskBDE
}, 0 },
10239 { "kmovd", { MaskG
, MaskBDE
}, 0 },
10242 /* VEX_W_0F91_P_0_LEN_0 */
10243 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
10244 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
10247 /* VEX_W_0F91_P_2_LEN_0 */
10248 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
10249 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
10252 /* VEX_W_0F92_P_0_LEN_0 */
10253 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
10256 /* VEX_W_0F92_P_2_LEN_0 */
10257 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
10260 /* VEX_W_0F93_P_0_LEN_0 */
10261 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
10264 /* VEX_W_0F93_P_2_LEN_0 */
10265 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
10268 /* VEX_W_0F98_P_0_LEN_0 */
10269 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
10270 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
10273 /* VEX_W_0F98_P_2_LEN_0 */
10274 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
10275 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
10278 /* VEX_W_0F99_P_0_LEN_0 */
10279 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
10280 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
10283 /* VEX_W_0F99_P_2_LEN_0 */
10284 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
10285 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
10288 /* VEX_W_0F380C_P_2 */
10289 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
10292 /* VEX_W_0F380D_P_2 */
10293 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
10296 /* VEX_W_0F380E_P_2 */
10297 { "vtestps", { XM
, EXx
}, 0 },
10300 /* VEX_W_0F380F_P_2 */
10301 { "vtestpd", { XM
, EXx
}, 0 },
10304 /* VEX_W_0F3813_P_2 */
10305 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
10308 /* VEX_W_0F3816_P_2 */
10309 { "vpermps", { XM
, Vex
, EXx
}, 0 },
10312 /* VEX_W_0F3818_P_2 */
10313 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
10316 /* VEX_W_0F3819_P_2 */
10317 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
10320 /* VEX_W_0F381A_P_2_M_0_L_0 */
10321 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
10324 /* VEX_W_0F382C_P_2_M_0 */
10325 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
10328 /* VEX_W_0F382D_P_2_M_0 */
10329 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
10332 /* VEX_W_0F382E_P_2_M_0 */
10333 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
10336 /* VEX_W_0F382F_P_2_M_0 */
10337 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
10340 /* VEX_W_0F3836_P_2 */
10341 { "vpermd", { XM
, Vex
, EXx
}, 0 },
10344 /* VEX_W_0F3846_P_2 */
10345 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
10348 /* VEX_W_0F3849_X86_64_P_0 */
10349 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0
) },
10352 /* VEX_W_0F3849_X86_64_P_2 */
10353 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0
) },
10356 /* VEX_W_0F3849_X86_64_P_3 */
10357 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0
) },
10360 /* VEX_W_0F384B_X86_64_P_1 */
10361 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0
) },
10364 /* VEX_W_0F384B_X86_64_P_2 */
10365 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0
) },
10368 /* VEX_W_0F384B_X86_64_P_3 */
10369 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0
) },
10372 /* VEX_W_0F3858_P_2 */
10373 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
10376 /* VEX_W_0F3859_P_2 */
10377 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
10380 /* VEX_W_0F385A_P_2_M_0_L_0 */
10381 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
10384 /* VEX_W_0F385C_X86_64_P_1 */
10385 { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0
) },
10388 /* VEX_W_0F385E_X86_64_P_0 */
10389 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0
) },
10392 /* VEX_W_0F385E_X86_64_P_1 */
10393 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0
) },
10396 /* VEX_W_0F385E_X86_64_P_2 */
10397 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0
) },
10400 /* VEX_W_0F385E_X86_64_P_3 */
10401 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0
) },
10404 /* VEX_W_0F3878_P_2 */
10405 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
10408 /* VEX_W_0F3879_P_2 */
10409 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
10412 /* VEX_W_0F38CF_P_2 */
10413 { "vgf2p8mulb", { XM
, Vex
, EXx
}, 0 },
10416 /* VEX_W_0F3A00_P_2 */
10418 { "vpermq", { XM
, EXx
, Ib
}, 0 },
10421 /* VEX_W_0F3A01_P_2 */
10423 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
10426 /* VEX_W_0F3A02_P_2 */
10427 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
10430 /* VEX_W_0F3A04_P_2 */
10431 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
10434 /* VEX_W_0F3A05_P_2 */
10435 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
10438 /* VEX_W_0F3A06_P_2_L_0 */
10439 { "vperm2f128", { XM
, Vex
, EXx
, Ib
}, 0 },
10442 /* VEX_W_0F3A18_P_2_L_0 */
10443 { "vinsertf128", { XM
, Vex
, EXxmm
, Ib
}, 0 },
10446 /* VEX_W_0F3A19_P_2_L_0 */
10447 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
10450 /* VEX_W_0F3A1D_P_2 */
10451 { "vcvtps2ph", { EXxmmq
, XM
, EXxEVexS
, Ib
}, 0 },
10454 /* VEX_W_0F3A30_P_2_LEN_0 */
10455 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
10456 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
10459 /* VEX_W_0F3A31_P_2_LEN_0 */
10460 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
10461 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
10464 /* VEX_W_0F3A32_P_2_LEN_0 */
10465 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
10466 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
10469 /* VEX_W_0F3A33_P_2_LEN_0 */
10470 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
10471 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
10474 /* VEX_W_0F3A38_P_2_L_0 */
10475 { "vinserti128", { XM
, Vex
, EXxmm
, Ib
}, 0 },
10478 /* VEX_W_0F3A39_P_2_L_0 */
10479 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
10482 /* VEX_W_0F3A46_P_2_L_0 */
10483 { "vperm2i128", { XM
, Vex
, EXx
, Ib
}, 0 },
10486 /* VEX_W_0F3A4A_P_2 */
10487 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10490 /* VEX_W_0F3A4B_P_2 */
10491 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10494 /* VEX_W_0F3A4C_P_2 */
10495 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10498 /* VEX_W_0F3ACE_P_2 */
10500 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10503 /* VEX_W_0F3ACF_P_2 */
10505 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10507 /* VEX_W_0FXOP_08_85_L_0 */
10509 { "vpmacssww", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10511 /* VEX_W_0FXOP_08_86_L_0 */
10513 { "vpmacsswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10515 /* VEX_W_0FXOP_08_87_L_0 */
10517 { "vpmacssdql", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10519 /* VEX_W_0FXOP_08_8E_L_0 */
10521 { "vpmacssdd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10523 /* VEX_W_0FXOP_08_8F_L_0 */
10525 { "vpmacssdqh", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10527 /* VEX_W_0FXOP_08_95_L_0 */
10529 { "vpmacsww", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10531 /* VEX_W_0FXOP_08_96_L_0 */
10533 { "vpmacswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10535 /* VEX_W_0FXOP_08_97_L_0 */
10537 { "vpmacsdql", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10539 /* VEX_W_0FXOP_08_9E_L_0 */
10541 { "vpmacsdd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10543 /* VEX_W_0FXOP_08_9F_L_0 */
10545 { "vpmacsdqh", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10547 /* VEX_W_0FXOP_08_A6_L_0 */
10549 { "vpmadcsswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10551 /* VEX_W_0FXOP_08_B6_L_0 */
10553 { "vpmadcswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10555 /* VEX_W_0FXOP_08_C0_L_0 */
10557 { "vprotb", { XM
, EXx
, Ib
}, 0 },
10559 /* VEX_W_0FXOP_08_C1_L_0 */
10561 { "vprotw", { XM
, EXx
, Ib
}, 0 },
10563 /* VEX_W_0FXOP_08_C2_L_0 */
10565 { "vprotd", { XM
, EXx
, Ib
}, 0 },
10567 /* VEX_W_0FXOP_08_C3_L_0 */
10569 { "vprotq", { XM
, EXx
, Ib
}, 0 },
10571 /* VEX_W_0FXOP_08_CC_L_0 */
10573 { "vpcomb", { XM
, Vex
, EXx
, VPCOM
}, 0 },
10575 /* VEX_W_0FXOP_08_CD_L_0 */
10577 { "vpcomw", { XM
, Vex
, EXx
, VPCOM
}, 0 },
10579 /* VEX_W_0FXOP_08_CE_L_0 */
10581 { "vpcomd", { XM
, Vex
, EXx
, VPCOM
}, 0 },
10583 /* VEX_W_0FXOP_08_CF_L_0 */
10585 { "vpcomq", { XM
, Vex
, EXx
, VPCOM
}, 0 },
10587 /* VEX_W_0FXOP_08_EC_L_0 */
10589 { "vpcomub", { XM
, Vex
, EXx
, VPCOM
}, 0 },
10591 /* VEX_W_0FXOP_08_ED_L_0 */
10593 { "vpcomuw", { XM
, Vex
, EXx
, VPCOM
}, 0 },
10595 /* VEX_W_0FXOP_08_EE_L_0 */
10597 { "vpcomud", { XM
, Vex
, EXx
, VPCOM
}, 0 },
10599 /* VEX_W_0FXOP_08_EF_L_0 */
10601 { "vpcomuq", { XM
, Vex
, EXx
, VPCOM
}, 0 },
10603 /* VEX_W_0FXOP_09_80 */
10605 { "vfrczps", { XM
, EXx
}, 0 },
10607 /* VEX_W_0FXOP_09_81 */
10609 { "vfrczpd", { XM
, EXx
}, 0 },
10611 /* VEX_W_0FXOP_09_82 */
10613 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0
) },
10615 /* VEX_W_0FXOP_09_83 */
10617 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0
) },
10619 /* VEX_W_0FXOP_09_C1_L_0 */
10621 { "vphaddbw", { XM
, EXxmm
}, 0 },
10623 /* VEX_W_0FXOP_09_C2_L_0 */
10625 { "vphaddbd", { XM
, EXxmm
}, 0 },
10627 /* VEX_W_0FXOP_09_C3_L_0 */
10629 { "vphaddbq", { XM
, EXxmm
}, 0 },
10631 /* VEX_W_0FXOP_09_C6_L_0 */
10633 { "vphaddwd", { XM
, EXxmm
}, 0 },
10635 /* VEX_W_0FXOP_09_C7_L_0 */
10637 { "vphaddwq", { XM
, EXxmm
}, 0 },
10639 /* VEX_W_0FXOP_09_CB_L_0 */
10641 { "vphadddq", { XM
, EXxmm
}, 0 },
10643 /* VEX_W_0FXOP_09_D1_L_0 */
10645 { "vphaddubw", { XM
, EXxmm
}, 0 },
10647 /* VEX_W_0FXOP_09_D2_L_0 */
10649 { "vphaddubd", { XM
, EXxmm
}, 0 },
10651 /* VEX_W_0FXOP_09_D3_L_0 */
10653 { "vphaddubq", { XM
, EXxmm
}, 0 },
10655 /* VEX_W_0FXOP_09_D6_L_0 */
10657 { "vphadduwd", { XM
, EXxmm
}, 0 },
10659 /* VEX_W_0FXOP_09_D7_L_0 */
10661 { "vphadduwq", { XM
, EXxmm
}, 0 },
10663 /* VEX_W_0FXOP_09_DB_L_0 */
10665 { "vphaddudq", { XM
, EXxmm
}, 0 },
10667 /* VEX_W_0FXOP_09_E1_L_0 */
10669 { "vphsubbw", { XM
, EXxmm
}, 0 },
10671 /* VEX_W_0FXOP_09_E2_L_0 */
10673 { "vphsubwd", { XM
, EXxmm
}, 0 },
10675 /* VEX_W_0FXOP_09_E3_L_0 */
10677 { "vphsubdq", { XM
, EXxmm
}, 0 },
10680 #include "i386-dis-evex-w.h"
10683 static const struct dis386 mod_table
[][2] = {
10686 { "leaS", { Gv
, M
}, 0 },
10691 { RM_TABLE (RM_C6_REG_7
) },
10696 { RM_TABLE (RM_C7_REG_7
) },
10700 { "{l|}call^", { indirEp
}, 0 },
10704 { "{l|}jmp^", { indirEp
}, 0 },
10707 /* MOD_0F01_REG_0 */
10708 { X86_64_TABLE (X86_64_0F01_REG_0
) },
10709 { RM_TABLE (RM_0F01_REG_0
) },
10712 /* MOD_0F01_REG_1 */
10713 { X86_64_TABLE (X86_64_0F01_REG_1
) },
10714 { RM_TABLE (RM_0F01_REG_1
) },
10717 /* MOD_0F01_REG_2 */
10718 { X86_64_TABLE (X86_64_0F01_REG_2
) },
10719 { RM_TABLE (RM_0F01_REG_2
) },
10722 /* MOD_0F01_REG_3 */
10723 { X86_64_TABLE (X86_64_0F01_REG_3
) },
10724 { RM_TABLE (RM_0F01_REG_3
) },
10727 /* MOD_0F01_REG_5 */
10728 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0
) },
10729 { RM_TABLE (RM_0F01_REG_5_MOD_3
) },
10732 /* MOD_0F01_REG_7 */
10733 { "invlpg", { Mb
}, 0 },
10734 { RM_TABLE (RM_0F01_REG_7_MOD_3
) },
10737 /* MOD_0F12_PREFIX_0 */
10738 { "movlpX", { XM
, EXq
}, 0 },
10739 { "movhlps", { XM
, EXq
}, 0 },
10742 /* MOD_0F12_PREFIX_2 */
10743 { "movlpX", { XM
, EXq
}, 0 },
10747 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
10750 /* MOD_0F16_PREFIX_0 */
10751 { "movhpX", { XM
, EXq
}, 0 },
10752 { "movlhps", { XM
, EXq
}, 0 },
10755 /* MOD_0F16_PREFIX_2 */
10756 { "movhpX", { XM
, EXq
}, 0 },
10760 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
10763 /* MOD_0F18_REG_0 */
10764 { "prefetchnta", { Mb
}, 0 },
10767 /* MOD_0F18_REG_1 */
10768 { "prefetcht0", { Mb
}, 0 },
10771 /* MOD_0F18_REG_2 */
10772 { "prefetcht1", { Mb
}, 0 },
10775 /* MOD_0F18_REG_3 */
10776 { "prefetcht2", { Mb
}, 0 },
10779 /* MOD_0F18_REG_4 */
10780 { "nop/reserved", { Mb
}, 0 },
10783 /* MOD_0F18_REG_5 */
10784 { "nop/reserved", { Mb
}, 0 },
10787 /* MOD_0F18_REG_6 */
10788 { "nop/reserved", { Mb
}, 0 },
10791 /* MOD_0F18_REG_7 */
10792 { "nop/reserved", { Mb
}, 0 },
10795 /* MOD_0F1A_PREFIX_0 */
10796 { "bndldx", { Gbnd
, Mv_bnd
}, 0 },
10797 { "nopQ", { Ev
}, 0 },
10800 /* MOD_0F1B_PREFIX_0 */
10801 { "bndstx", { Mv_bnd
, Gbnd
}, 0 },
10802 { "nopQ", { Ev
}, 0 },
10805 /* MOD_0F1B_PREFIX_1 */
10806 { "bndmk", { Gbnd
, Mv_bnd
}, 0 },
10807 { "nopQ", { Ev
}, 0 },
10810 /* MOD_0F1C_PREFIX_0 */
10811 { REG_TABLE (REG_0F1C_P_0_MOD_0
) },
10812 { "nopQ", { Ev
}, 0 },
10815 /* MOD_0F1E_PREFIX_1 */
10816 { "nopQ", { Ev
}, 0 },
10817 { REG_TABLE (REG_0F1E_P_1_MOD_3
) },
10822 { "movL", { Rd
, Td
}, 0 },
10827 { "movL", { Td
, Rd
}, 0 },
10830 /* MOD_0F2B_PREFIX_0 */
10831 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
10834 /* MOD_0F2B_PREFIX_1 */
10835 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
10838 /* MOD_0F2B_PREFIX_2 */
10839 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
10842 /* MOD_0F2B_PREFIX_3 */
10843 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
10848 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
10851 /* MOD_0F71_REG_2 */
10853 { "psrlw", { MS
, Ib
}, 0 },
10856 /* MOD_0F71_REG_4 */
10858 { "psraw", { MS
, Ib
}, 0 },
10861 /* MOD_0F71_REG_6 */
10863 { "psllw", { MS
, Ib
}, 0 },
10866 /* MOD_0F72_REG_2 */
10868 { "psrld", { MS
, Ib
}, 0 },
10871 /* MOD_0F72_REG_4 */
10873 { "psrad", { MS
, Ib
}, 0 },
10876 /* MOD_0F72_REG_6 */
10878 { "pslld", { MS
, Ib
}, 0 },
10881 /* MOD_0F73_REG_2 */
10883 { "psrlq", { MS
, Ib
}, 0 },
10886 /* MOD_0F73_REG_3 */
10888 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
10891 /* MOD_0F73_REG_6 */
10893 { "psllq", { MS
, Ib
}, 0 },
10896 /* MOD_0F73_REG_7 */
10898 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
10901 /* MOD_0FAE_REG_0 */
10902 { "fxsave", { FXSAVE
}, 0 },
10903 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3
) },
10906 /* MOD_0FAE_REG_1 */
10907 { "fxrstor", { FXSAVE
}, 0 },
10908 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3
) },
10911 /* MOD_0FAE_REG_2 */
10912 { "ldmxcsr", { Md
}, 0 },
10913 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3
) },
10916 /* MOD_0FAE_REG_3 */
10917 { "stmxcsr", { Md
}, 0 },
10918 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3
) },
10921 /* MOD_0FAE_REG_4 */
10922 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0
) },
10923 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3
) },
10926 /* MOD_0FAE_REG_5 */
10927 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0
) },
10928 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3
) },
10931 /* MOD_0FAE_REG_6 */
10932 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0
) },
10933 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3
) },
10936 /* MOD_0FAE_REG_7 */
10937 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0
) },
10938 { RM_TABLE (RM_0FAE_REG_7_MOD_3
) },
10942 { "lssS", { Gv
, Mp
}, 0 },
10946 { "lfsS", { Gv
, Mp
}, 0 },
10950 { "lgsS", { Gv
, Mp
}, 0 },
10954 { PREFIX_TABLE (PREFIX_0FC3_MOD_0
) },
10957 /* MOD_0FC7_REG_3 */
10958 { "xrstors", { FXSAVE
}, 0 },
10961 /* MOD_0FC7_REG_4 */
10962 { "xsavec", { FXSAVE
}, 0 },
10965 /* MOD_0FC7_REG_5 */
10966 { "xsaves", { FXSAVE
}, 0 },
10969 /* MOD_0FC7_REG_6 */
10970 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0
) },
10971 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3
) }
10974 /* MOD_0FC7_REG_7 */
10975 { "vmptrst", { Mq
}, 0 },
10976 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3
) }
10981 { "pmovmskb", { Gdq
, MS
}, 0 },
10984 /* MOD_0FE7_PREFIX_2 */
10985 { "movntdq", { Mx
, XM
}, 0 },
10988 /* MOD_0FF0_PREFIX_3 */
10989 { "lddqu", { XM
, M
}, 0 },
10992 /* MOD_0F382A_PREFIX_2 */
10993 { "movntdqa", { XM
, Mx
}, 0 },
10996 /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
10997 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0
) },
10998 { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1
) },
11001 /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
11002 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0
) },
11005 /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
11007 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0
) },
11010 /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
11011 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0
) },
11014 /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
11015 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0
) },
11018 /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
11019 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0
) },
11022 /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
11024 { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0
) },
11027 /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
11029 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0
) },
11032 /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
11034 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0
) },
11037 /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
11039 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0
) },
11042 /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
11044 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0
) },
11047 /* MOD_0F38F5_PREFIX_2 */
11048 { "wrussK", { M
, Gdq
}, PREFIX_OPCODE
},
11051 /* MOD_0F38F6_PREFIX_0 */
11052 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
11055 /* MOD_0F38F8_PREFIX_1 */
11056 { "enqcmds", { Gva
, M
}, PREFIX_OPCODE
},
11059 /* MOD_0F38F8_PREFIX_2 */
11060 { "movdir64b", { Gva
, M
}, PREFIX_OPCODE
},
11063 /* MOD_0F38F8_PREFIX_3 */
11064 { "enqcmd", { Gva
, M
}, PREFIX_OPCODE
},
11067 /* MOD_0F38F9_PREFIX_0 */
11068 { "movdiri", { Ev
, Gv
}, PREFIX_OPCODE
},
11072 { "bound{S|}", { Gv
, Ma
}, 0 },
11073 { EVEX_TABLE (EVEX_0F
) },
11077 { "lesS", { Gv
, Mp
}, 0 },
11078 { VEX_C4_TABLE (VEX_0F
) },
11082 { "ldsS", { Gv
, Mp
}, 0 },
11083 { VEX_C5_TABLE (VEX_0F
) },
11086 /* MOD_VEX_0F12_PREFIX_0 */
11087 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
11088 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
11091 /* MOD_VEX_0F12_PREFIX_2 */
11092 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0
) },
11096 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
11099 /* MOD_VEX_0F16_PREFIX_0 */
11100 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
11101 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
11104 /* MOD_VEX_0F16_PREFIX_2 */
11105 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0
) },
11109 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
11113 { "vmovntpX", { Mx
, XM
}, PREFIX_OPCODE
},
11116 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11118 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
11121 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11123 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
11126 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11128 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
11131 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11133 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
11136 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11138 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
11141 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11143 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
11146 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11148 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
11151 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11153 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
11156 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11158 { "knotw", { MaskG
, MaskR
}, 0 },
11161 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11163 { "knotq", { MaskG
, MaskR
}, 0 },
11166 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11168 { "knotb", { MaskG
, MaskR
}, 0 },
11171 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11173 { "knotd", { MaskG
, MaskR
}, 0 },
11176 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11178 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
11181 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11183 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
11186 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11188 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
11191 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11193 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
11196 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11198 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
11201 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11203 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
11206 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11208 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
11211 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11213 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
11216 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11218 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
11221 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11223 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
11226 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11228 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
11231 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11233 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
11236 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11238 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
11241 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11243 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
11246 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11248 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
11251 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11253 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
11256 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11258 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
11261 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11263 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
11266 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11268 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
11273 { "vmovmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
11276 /* MOD_VEX_0F71_REG_2 */
11278 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
11281 /* MOD_VEX_0F71_REG_4 */
11283 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
11286 /* MOD_VEX_0F71_REG_6 */
11288 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
11291 /* MOD_VEX_0F72_REG_2 */
11293 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
11296 /* MOD_VEX_0F72_REG_4 */
11298 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
11301 /* MOD_VEX_0F72_REG_6 */
11303 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
11306 /* MOD_VEX_0F73_REG_2 */
11308 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
11311 /* MOD_VEX_0F73_REG_3 */
11313 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
11316 /* MOD_VEX_0F73_REG_6 */
11318 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
11321 /* MOD_VEX_0F73_REG_7 */
11323 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
11326 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11327 { "kmovw", { Ew
, MaskG
}, 0 },
11331 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11332 { "kmovq", { Eq
, MaskG
}, 0 },
11336 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11337 { "kmovb", { Eb
, MaskG
}, 0 },
11341 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11342 { "kmovd", { Ed
, MaskG
}, 0 },
11346 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
11348 { "kmovw", { MaskG
, Rdq
}, 0 },
11351 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
11353 { "kmovb", { MaskG
, Rdq
}, 0 },
11356 /* MOD_VEX_0F92_P_3_LEN_0 */
11358 { "kmovK", { MaskG
, Rdq
}, 0 },
11361 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
11363 { "kmovw", { Gdq
, MaskR
}, 0 },
11366 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
11368 { "kmovb", { Gdq
, MaskR
}, 0 },
11371 /* MOD_VEX_0F93_P_3_LEN_0 */
11373 { "kmovK", { Gdq
, MaskR
}, 0 },
11376 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
11378 { "kortestw", { MaskG
, MaskR
}, 0 },
11381 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
11383 { "kortestq", { MaskG
, MaskR
}, 0 },
11386 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
11388 { "kortestb", { MaskG
, MaskR
}, 0 },
11391 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
11393 { "kortestd", { MaskG
, MaskR
}, 0 },
11396 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
11398 { "ktestw", { MaskG
, MaskR
}, 0 },
11401 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
11403 { "ktestq", { MaskG
, MaskR
}, 0 },
11406 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
11408 { "ktestb", { MaskG
, MaskR
}, 0 },
11411 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
11413 { "ktestd", { MaskG
, MaskR
}, 0 },
11416 /* MOD_VEX_0FAE_REG_2 */
11417 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
11420 /* MOD_VEX_0FAE_REG_3 */
11421 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
11424 /* MOD_VEX_0FD7_PREFIX_2 */
11426 { "vpmovmskb", { Gdq
, XS
}, 0 },
11429 /* MOD_VEX_0FE7_PREFIX_2 */
11430 { "vmovntdq", { Mx
, XM
}, 0 },
11433 /* MOD_VEX_0FF0_PREFIX_3 */
11434 { "vlddqu", { XM
, M
}, 0 },
11437 /* MOD_VEX_0F381A_PREFIX_2 */
11438 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
11441 /* MOD_VEX_0F382A_PREFIX_2 */
11442 { "vmovntdqa", { XM
, Mx
}, 0 },
11445 /* MOD_VEX_0F382C_PREFIX_2 */
11446 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
11449 /* MOD_VEX_0F382D_PREFIX_2 */
11450 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
11453 /* MOD_VEX_0F382E_PREFIX_2 */
11454 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
11457 /* MOD_VEX_0F382F_PREFIX_2 */
11458 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
11461 /* MOD_VEX_0F385A_PREFIX_2 */
11462 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
11465 /* MOD_VEX_0F388C_PREFIX_2 */
11466 { "vpmaskmov%DQ", { XM
, Vex
, Mx
}, 0 },
11469 /* MOD_VEX_0F388E_PREFIX_2 */
11470 { "vpmaskmov%DQ", { Mx
, Vex
, XM
}, 0 },
11473 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
11475 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
11478 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
11480 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
11483 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
11485 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
11488 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
11490 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
11493 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
11495 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
11498 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
11500 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
11503 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
11505 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
11508 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
11510 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
11513 /* MOD_VEX_0FXOP_09_12 */
11515 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1
) },
11518 #include "i386-dis-evex-mod.h"
11521 static const struct dis386 rm_table
[][8] = {
11524 { "xabort", { Skip_MODRM
, Ib
}, 0 },
11528 { "xbeginT", { Skip_MODRM
, Jdqw
}, 0 },
11531 /* RM_0F01_REG_0 */
11532 { "enclv", { Skip_MODRM
}, 0 },
11533 { "vmcall", { Skip_MODRM
}, 0 },
11534 { "vmlaunch", { Skip_MODRM
}, 0 },
11535 { "vmresume", { Skip_MODRM
}, 0 },
11536 { "vmxoff", { Skip_MODRM
}, 0 },
11537 { "pconfig", { Skip_MODRM
}, 0 },
11540 /* RM_0F01_REG_1 */
11541 { "monitor", { { OP_Monitor
, 0 } }, 0 },
11542 { "mwait", { { OP_Mwait
, 0 } }, 0 },
11543 { "clac", { Skip_MODRM
}, 0 },
11544 { "stac", { Skip_MODRM
}, 0 },
11548 { "encls", { Skip_MODRM
}, 0 },
11551 /* RM_0F01_REG_2 */
11552 { "xgetbv", { Skip_MODRM
}, 0 },
11553 { "xsetbv", { Skip_MODRM
}, 0 },
11556 { "vmfunc", { Skip_MODRM
}, 0 },
11557 { "xend", { Skip_MODRM
}, 0 },
11558 { "xtest", { Skip_MODRM
}, 0 },
11559 { "enclu", { Skip_MODRM
}, 0 },
11562 /* RM_0F01_REG_3 */
11563 { "vmrun", { Skip_MODRM
}, 0 },
11564 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1
) },
11565 { "vmload", { Skip_MODRM
}, 0 },
11566 { "vmsave", { Skip_MODRM
}, 0 },
11567 { "stgi", { Skip_MODRM
}, 0 },
11568 { "clgi", { Skip_MODRM
}, 0 },
11569 { "skinit", { Skip_MODRM
}, 0 },
11570 { "invlpga", { Skip_MODRM
}, 0 },
11573 /* RM_0F01_REG_5_MOD_3 */
11574 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0
) },
11575 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1
) },
11576 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2
) },
11580 { "rdpkru", { Skip_MODRM
}, 0 },
11581 { "wrpkru", { Skip_MODRM
}, 0 },
11584 /* RM_0F01_REG_7_MOD_3 */
11585 { "swapgs", { Skip_MODRM
}, 0 },
11586 { "rdtscp", { Skip_MODRM
}, 0 },
11587 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2
) },
11588 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3
) },
11589 { "clzero", { Skip_MODRM
}, 0 },
11590 { "rdpru", { Skip_MODRM
}, 0 },
11593 /* RM_0F1E_P_1_MOD_3_REG_7 */
11594 { "nopQ", { Ev
}, 0 },
11595 { "nopQ", { Ev
}, 0 },
11596 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
11597 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
11598 { "nopQ", { Ev
}, 0 },
11599 { "nopQ", { Ev
}, 0 },
11600 { "nopQ", { Ev
}, 0 },
11601 { "nopQ", { Ev
}, 0 },
11604 /* RM_0FAE_REG_6_MOD_3 */
11605 { "mfence", { Skip_MODRM
}, 0 },
11608 /* RM_0FAE_REG_7_MOD_3 */
11609 { "sfence", { Skip_MODRM
}, 0 },
11613 /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
11614 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0
) },
11618 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11620 /* We use the high bit to indicate different name for the same
11622 #define REP_PREFIX (0xf3 | 0x100)
11623 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11624 #define XRELEASE_PREFIX (0xf3 | 0x400)
11625 #define BND_PREFIX (0xf2 | 0x400)
11626 #define NOTRACK_PREFIX (0x3e | 0x100)
11628 /* Remember if the current op is a jump instruction. */
11629 static bfd_boolean op_is_jump
= FALSE
;
11634 int newrex
, i
, length
;
11639 last_lock_prefix
= -1;
11640 last_repz_prefix
= -1;
11641 last_repnz_prefix
= -1;
11642 last_data_prefix
= -1;
11643 last_addr_prefix
= -1;
11644 last_rex_prefix
= -1;
11645 last_seg_prefix
= -1;
11647 active_seg_prefix
= 0;
11648 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11649 all_prefixes
[i
] = 0;
11652 /* The maximum instruction length is 15bytes. */
11653 while (length
< MAX_CODE_LENGTH
- 1)
11655 FETCH_DATA (the_info
, codep
+ 1);
11659 /* REX prefixes family. */
11676 if (address_mode
== mode_64bit
)
11680 last_rex_prefix
= i
;
11683 prefixes
|= PREFIX_REPZ
;
11684 last_repz_prefix
= i
;
11687 prefixes
|= PREFIX_REPNZ
;
11688 last_repnz_prefix
= i
;
11691 prefixes
|= PREFIX_LOCK
;
11692 last_lock_prefix
= i
;
11695 prefixes
|= PREFIX_CS
;
11696 last_seg_prefix
= i
;
11697 active_seg_prefix
= PREFIX_CS
;
11700 prefixes
|= PREFIX_SS
;
11701 last_seg_prefix
= i
;
11702 active_seg_prefix
= PREFIX_SS
;
11705 prefixes
|= PREFIX_DS
;
11706 last_seg_prefix
= i
;
11707 active_seg_prefix
= PREFIX_DS
;
11710 prefixes
|= PREFIX_ES
;
11711 last_seg_prefix
= i
;
11712 active_seg_prefix
= PREFIX_ES
;
11715 prefixes
|= PREFIX_FS
;
11716 last_seg_prefix
= i
;
11717 active_seg_prefix
= PREFIX_FS
;
11720 prefixes
|= PREFIX_GS
;
11721 last_seg_prefix
= i
;
11722 active_seg_prefix
= PREFIX_GS
;
11725 prefixes
|= PREFIX_DATA
;
11726 last_data_prefix
= i
;
11729 prefixes
|= PREFIX_ADDR
;
11730 last_addr_prefix
= i
;
11733 /* fwait is really an instruction. If there are prefixes
11734 before the fwait, they belong to the fwait, *not* to the
11735 following instruction. */
11737 if (prefixes
|| rex
)
11739 prefixes
|= PREFIX_FWAIT
;
11741 /* This ensures that the previous REX prefixes are noticed
11742 as unused prefixes, as in the return case below. */
11746 prefixes
= PREFIX_FWAIT
;
11751 /* Rex is ignored when followed by another prefix. */
11757 if (*codep
!= FWAIT_OPCODE
)
11758 all_prefixes
[i
++] = *codep
;
11766 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11769 static const char *
11770 prefix_name (int pref
, int sizeflag
)
11772 static const char *rexes
[16] =
11775 "rex.B", /* 0x41 */
11776 "rex.X", /* 0x42 */
11777 "rex.XB", /* 0x43 */
11778 "rex.R", /* 0x44 */
11779 "rex.RB", /* 0x45 */
11780 "rex.RX", /* 0x46 */
11781 "rex.RXB", /* 0x47 */
11782 "rex.W", /* 0x48 */
11783 "rex.WB", /* 0x49 */
11784 "rex.WX", /* 0x4a */
11785 "rex.WXB", /* 0x4b */
11786 "rex.WR", /* 0x4c */
11787 "rex.WRB", /* 0x4d */
11788 "rex.WRX", /* 0x4e */
11789 "rex.WRXB", /* 0x4f */
11794 /* REX prefixes family. */
11811 return rexes
[pref
- 0x40];
11831 return (sizeflag
& DFLAG
) ? "data16" : "data32";
11833 if (address_mode
== mode_64bit
)
11834 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
11836 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
11841 case XACQUIRE_PREFIX
:
11843 case XRELEASE_PREFIX
:
11847 case NOTRACK_PREFIX
:
11854 static char op_out
[MAX_OPERANDS
][100];
11855 static int op_ad
, op_index
[MAX_OPERANDS
];
11856 static int two_source_ops
;
11857 static bfd_vma op_address
[MAX_OPERANDS
];
11858 static bfd_vma op_riprel
[MAX_OPERANDS
];
11859 static bfd_vma start_pc
;
11862 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11863 * (see topic "Redundant prefixes" in the "Differences from 8086"
11864 * section of the "Virtual 8086 Mode" chapter.)
11865 * 'pc' should be the address of this instruction, it will
11866 * be used to print the target address if this is a relative jump or call
11867 * The function returns the length of this instruction in bytes.
11870 static char intel_syntax
;
11871 static char intel_mnemonic
= !SYSV386_COMPAT
;
11872 static char open_char
;
11873 static char close_char
;
11874 static char separator_char
;
11875 static char scale_char
;
11883 static enum x86_64_isa isa64
;
11885 /* Here for backwards compatibility. When gdb stops using
11886 print_insn_i386_att and print_insn_i386_intel these functions can
11887 disappear, and print_insn_i386 be merged into print_insn. */
11889 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
11893 return print_insn (pc
, info
);
11897 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
11901 return print_insn (pc
, info
);
11905 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
11909 return print_insn (pc
, info
);
11913 print_i386_disassembler_options (FILE *stream
)
11915 fprintf (stream
, _("\n\
11916 The following i386/x86-64 specific disassembler options are supported for use\n\
11917 with the -M switch (multiple options should be separated by commas):\n"));
11919 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
11920 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
11921 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
11922 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
11923 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
11924 fprintf (stream
, _(" att-mnemonic\n"
11925 " Display instruction in AT&T mnemonic\n"));
11926 fprintf (stream
, _(" intel-mnemonic\n"
11927 " Display instruction in Intel mnemonic\n"));
11928 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
11929 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
11930 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
11931 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
11932 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
11933 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11934 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
11935 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
11939 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
11941 /* Get a pointer to struct dis386 with a valid name. */
11943 static const struct dis386
*
11944 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
11946 int vindex
, vex_table_index
;
11948 if (dp
->name
!= NULL
)
11951 switch (dp
->op
[0].bytemode
)
11953 case USE_REG_TABLE
:
11954 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
11957 case USE_MOD_TABLE
:
11958 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
11959 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
11963 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
11966 case USE_PREFIX_TABLE
:
11969 /* The prefix in VEX is implicit. */
11970 switch (vex
.prefix
)
11975 case REPE_PREFIX_OPCODE
:
11978 case DATA_PREFIX_OPCODE
:
11981 case REPNE_PREFIX_OPCODE
:
11991 int last_prefix
= -1;
11994 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11995 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11997 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
11999 if (last_repz_prefix
> last_repnz_prefix
)
12002 prefix
= PREFIX_REPZ
;
12003 last_prefix
= last_repz_prefix
;
12008 prefix
= PREFIX_REPNZ
;
12009 last_prefix
= last_repnz_prefix
;
12012 /* Check if prefix should be ignored. */
12013 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
12014 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
12019 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
12022 prefix
= PREFIX_DATA
;
12023 last_prefix
= last_data_prefix
;
12028 used_prefixes
|= prefix
;
12029 all_prefixes
[last_prefix
] = 0;
12032 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
12035 case USE_X86_64_TABLE
:
12036 vindex
= address_mode
== mode_64bit
? 1 : 0;
12037 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
12040 case USE_3BYTE_TABLE
:
12041 FETCH_DATA (info
, codep
+ 2);
12043 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
12045 modrm
.mod
= (*codep
>> 6) & 3;
12046 modrm
.reg
= (*codep
>> 3) & 7;
12047 modrm
.rm
= *codep
& 7;
12050 case USE_VEX_LEN_TABLE
:
12054 switch (vex
.length
)
12067 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
12070 case USE_EVEX_LEN_TABLE
:
12074 switch (vex
.length
)
12090 dp
= &evex_len_table
[dp
->op
[1].bytemode
][vindex
];
12093 case USE_XOP_8F_TABLE
:
12094 FETCH_DATA (info
, codep
+ 3);
12095 rex
= ~(*codep
>> 5) & 0x7;
12097 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12098 switch ((*codep
& 0x1f))
12104 vex_table_index
= XOP_08
;
12107 vex_table_index
= XOP_09
;
12110 vex_table_index
= XOP_0A
;
12114 vex
.w
= *codep
& 0x80;
12115 if (vex
.w
&& address_mode
== mode_64bit
)
12118 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12119 if (address_mode
!= mode_64bit
)
12121 /* In 16/32-bit mode REX_B is silently ignored. */
12125 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12126 switch ((*codep
& 0x3))
12131 vex
.prefix
= DATA_PREFIX_OPCODE
;
12134 vex
.prefix
= REPE_PREFIX_OPCODE
;
12137 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12143 dp
= &xop_table
[vex_table_index
][vindex
];
12146 FETCH_DATA (info
, codep
+ 1);
12147 modrm
.mod
= (*codep
>> 6) & 3;
12148 modrm
.reg
= (*codep
>> 3) & 7;
12149 modrm
.rm
= *codep
& 7;
12151 /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
12152 having to decode the bits for every otherwise valid encoding. */
12154 return &bad_opcode
;
12157 case USE_VEX_C4_TABLE
:
12159 FETCH_DATA (info
, codep
+ 3);
12160 rex
= ~(*codep
>> 5) & 0x7;
12161 switch ((*codep
& 0x1f))
12167 vex_table_index
= VEX_0F
;
12170 vex_table_index
= VEX_0F38
;
12173 vex_table_index
= VEX_0F3A
;
12177 vex
.w
= *codep
& 0x80;
12178 if (address_mode
== mode_64bit
)
12185 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12186 is ignored, other REX bits are 0 and the highest bit in
12187 VEX.vvvv is also ignored (but we mustn't clear it here). */
12190 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12191 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12192 switch ((*codep
& 0x3))
12197 vex
.prefix
= DATA_PREFIX_OPCODE
;
12200 vex
.prefix
= REPE_PREFIX_OPCODE
;
12203 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12209 dp
= &vex_table
[vex_table_index
][vindex
];
12211 /* There is no MODRM byte for VEX0F 77. */
12212 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
12214 FETCH_DATA (info
, codep
+ 1);
12215 modrm
.mod
= (*codep
>> 6) & 3;
12216 modrm
.reg
= (*codep
>> 3) & 7;
12217 modrm
.rm
= *codep
& 7;
12221 case USE_VEX_C5_TABLE
:
12223 FETCH_DATA (info
, codep
+ 2);
12224 rex
= (*codep
& 0x80) ? 0 : REX_R
;
12226 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12228 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12229 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12230 switch ((*codep
& 0x3))
12235 vex
.prefix
= DATA_PREFIX_OPCODE
;
12238 vex
.prefix
= REPE_PREFIX_OPCODE
;
12241 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12247 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
12249 /* There is no MODRM byte for VEX 77. */
12250 if (vindex
!= 0x77)
12252 FETCH_DATA (info
, codep
+ 1);
12253 modrm
.mod
= (*codep
>> 6) & 3;
12254 modrm
.reg
= (*codep
>> 3) & 7;
12255 modrm
.rm
= *codep
& 7;
12259 case USE_VEX_W_TABLE
:
12263 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
12266 case USE_EVEX_TABLE
:
12267 two_source_ops
= 0;
12270 FETCH_DATA (info
, codep
+ 4);
12271 /* The first byte after 0x62. */
12272 rex
= ~(*codep
>> 5) & 0x7;
12273 vex
.r
= *codep
& 0x10;
12274 switch ((*codep
& 0xf))
12277 return &bad_opcode
;
12279 vex_table_index
= EVEX_0F
;
12282 vex_table_index
= EVEX_0F38
;
12285 vex_table_index
= EVEX_0F3A
;
12289 /* The second byte after 0x62. */
12291 vex
.w
= *codep
& 0x80;
12292 if (vex
.w
&& address_mode
== mode_64bit
)
12295 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12298 if (!(*codep
& 0x4))
12299 return &bad_opcode
;
12301 switch ((*codep
& 0x3))
12306 vex
.prefix
= DATA_PREFIX_OPCODE
;
12309 vex
.prefix
= REPE_PREFIX_OPCODE
;
12312 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12316 /* The third byte after 0x62. */
12319 /* Remember the static rounding bits. */
12320 vex
.ll
= (*codep
>> 5) & 3;
12321 vex
.b
= (*codep
& 0x10) != 0;
12323 vex
.v
= *codep
& 0x8;
12324 vex
.mask_register_specifier
= *codep
& 0x7;
12325 vex
.zeroing
= *codep
& 0x80;
12327 if (address_mode
!= mode_64bit
)
12329 /* In 16/32-bit mode silently ignore following bits. */
12338 dp
= &evex_table
[vex_table_index
][vindex
];
12340 FETCH_DATA (info
, codep
+ 1);
12341 modrm
.mod
= (*codep
>> 6) & 3;
12342 modrm
.reg
= (*codep
>> 3) & 7;
12343 modrm
.rm
= *codep
& 7;
12345 /* Set vector length. */
12346 if (modrm
.mod
== 3 && vex
.b
)
12362 return &bad_opcode
;
12375 if (dp
->name
!= NULL
)
12378 return get_valid_dis386 (dp
, info
);
12382 get_sib (disassemble_info
*info
, int sizeflag
)
12384 /* If modrm.mod == 3, operand must be register. */
12386 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
12390 FETCH_DATA (info
, codep
+ 2);
12391 sib
.index
= (codep
[1] >> 3) & 7;
12392 sib
.scale
= (codep
[1] >> 6) & 3;
12393 sib
.base
= codep
[1] & 7;
12398 print_insn (bfd_vma pc
, disassemble_info
*info
)
12400 const struct dis386
*dp
;
12402 char *op_txt
[MAX_OPERANDS
];
12404 int sizeflag
, orig_sizeflag
;
12406 struct dis_private priv
;
12409 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
12410 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
12411 address_mode
= mode_32bit
;
12412 else if (info
->mach
== bfd_mach_i386_i8086
)
12414 address_mode
= mode_16bit
;
12415 priv
.orig_sizeflag
= 0;
12418 address_mode
= mode_64bit
;
12420 if (intel_syntax
== (char) -1)
12421 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
12423 for (p
= info
->disassembler_options
; p
!= NULL
; )
12425 if (CONST_STRNEQ (p
, "amd64"))
12427 else if (CONST_STRNEQ (p
, "intel64"))
12429 else if (CONST_STRNEQ (p
, "x86-64"))
12431 address_mode
= mode_64bit
;
12432 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
12434 else if (CONST_STRNEQ (p
, "i386"))
12436 address_mode
= mode_32bit
;
12437 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
12439 else if (CONST_STRNEQ (p
, "i8086"))
12441 address_mode
= mode_16bit
;
12442 priv
.orig_sizeflag
&= ~(AFLAG
| DFLAG
);
12444 else if (CONST_STRNEQ (p
, "intel"))
12447 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
12448 intel_mnemonic
= 1;
12450 else if (CONST_STRNEQ (p
, "att"))
12453 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
12454 intel_mnemonic
= 0;
12456 else if (CONST_STRNEQ (p
, "addr"))
12458 if (address_mode
== mode_64bit
)
12460 if (p
[4] == '3' && p
[5] == '2')
12461 priv
.orig_sizeflag
&= ~AFLAG
;
12462 else if (p
[4] == '6' && p
[5] == '4')
12463 priv
.orig_sizeflag
|= AFLAG
;
12467 if (p
[4] == '1' && p
[5] == '6')
12468 priv
.orig_sizeflag
&= ~AFLAG
;
12469 else if (p
[4] == '3' && p
[5] == '2')
12470 priv
.orig_sizeflag
|= AFLAG
;
12473 else if (CONST_STRNEQ (p
, "data"))
12475 if (p
[4] == '1' && p
[5] == '6')
12476 priv
.orig_sizeflag
&= ~DFLAG
;
12477 else if (p
[4] == '3' && p
[5] == '2')
12478 priv
.orig_sizeflag
|= DFLAG
;
12480 else if (CONST_STRNEQ (p
, "suffix"))
12481 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
12483 p
= strchr (p
, ',');
12488 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
12490 (*info
->fprintf_func
) (info
->stream
,
12491 _("64-bit address is disabled"));
12497 names64
= intel_names64
;
12498 names32
= intel_names32
;
12499 names16
= intel_names16
;
12500 names8
= intel_names8
;
12501 names8rex
= intel_names8rex
;
12502 names_seg
= intel_names_seg
;
12503 names_mm
= intel_names_mm
;
12504 names_bnd
= intel_names_bnd
;
12505 names_xmm
= intel_names_xmm
;
12506 names_ymm
= intel_names_ymm
;
12507 names_zmm
= intel_names_zmm
;
12508 names_tmm
= intel_names_tmm
;
12509 index64
= intel_index64
;
12510 index32
= intel_index32
;
12511 names_mask
= intel_names_mask
;
12512 index16
= intel_index16
;
12515 separator_char
= '+';
12520 names64
= att_names64
;
12521 names32
= att_names32
;
12522 names16
= att_names16
;
12523 names8
= att_names8
;
12524 names8rex
= att_names8rex
;
12525 names_seg
= att_names_seg
;
12526 names_mm
= att_names_mm
;
12527 names_bnd
= att_names_bnd
;
12528 names_xmm
= att_names_xmm
;
12529 names_ymm
= att_names_ymm
;
12530 names_zmm
= att_names_zmm
;
12531 names_tmm
= att_names_tmm
;
12532 index64
= att_index64
;
12533 index32
= att_index32
;
12534 names_mask
= att_names_mask
;
12535 index16
= att_index16
;
12538 separator_char
= ',';
12542 /* The output looks better if we put 7 bytes on a line, since that
12543 puts most long word instructions on a single line. Use 8 bytes
12545 if ((info
->mach
& bfd_mach_l1om
) != 0)
12546 info
->bytes_per_line
= 8;
12548 info
->bytes_per_line
= 7;
12550 info
->private_data
= &priv
;
12551 priv
.max_fetched
= priv
.the_buffer
;
12552 priv
.insn_start
= pc
;
12555 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12563 start_codep
= priv
.the_buffer
;
12564 codep
= priv
.the_buffer
;
12566 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
12570 /* Getting here means we tried for data but didn't get it. That
12571 means we have an incomplete instruction of some sort. Just
12572 print the first byte as a prefix or a .byte pseudo-op. */
12573 if (codep
> priv
.the_buffer
)
12575 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
12577 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
12580 /* Just print the first byte as a .byte instruction. */
12581 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
12582 (unsigned int) priv
.the_buffer
[0]);
12592 sizeflag
= priv
.orig_sizeflag
;
12594 if (!ckprefix () || rex_used
)
12596 /* Too many prefixes or unused REX prefixes. */
12598 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
12600 (*info
->fprintf_func
) (info
->stream
, "%s%s",
12602 prefix_name (all_prefixes
[i
], sizeflag
));
12606 insn_codep
= codep
;
12608 FETCH_DATA (info
, codep
+ 1);
12609 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
12611 if (((prefixes
& PREFIX_FWAIT
)
12612 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
12614 /* Handle prefixes before fwait. */
12615 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
12617 (*info
->fprintf_func
) (info
->stream
, "%s ",
12618 prefix_name (all_prefixes
[i
], sizeflag
));
12619 (*info
->fprintf_func
) (info
->stream
, "fwait");
12623 if (*codep
== 0x0f)
12625 unsigned char threebyte
;
12628 FETCH_DATA (info
, codep
+ 1);
12629 threebyte
= *codep
;
12630 dp
= &dis386_twobyte
[threebyte
];
12631 need_modrm
= twobyte_has_modrm
[*codep
];
12636 dp
= &dis386
[*codep
];
12637 need_modrm
= onebyte_has_modrm
[*codep
];
12641 /* Save sizeflag for printing the extra prefixes later before updating
12642 it for mnemonic and operand processing. The prefix names depend
12643 only on the address mode. */
12644 orig_sizeflag
= sizeflag
;
12645 if (prefixes
& PREFIX_ADDR
)
12647 if ((prefixes
& PREFIX_DATA
))
12653 FETCH_DATA (info
, codep
+ 1);
12654 modrm
.mod
= (*codep
>> 6) & 3;
12655 modrm
.reg
= (*codep
>> 3) & 7;
12656 modrm
.rm
= *codep
& 7;
12660 memset (&vex
, 0, sizeof (vex
));
12662 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
12664 get_sib (info
, sizeflag
);
12665 dofloat (sizeflag
);
12669 dp
= get_valid_dis386 (dp
, info
);
12670 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
12672 get_sib (info
, sizeflag
);
12673 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12676 op_ad
= MAX_OPERANDS
- 1 - i
;
12678 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
12679 /* For EVEX instruction after the last operand masking
12680 should be printed. */
12681 if (i
== 0 && vex
.evex
)
12683 /* Don't print {%k0}. */
12684 if (vex
.mask_register_specifier
)
12687 oappend (names_mask
[vex
.mask_register_specifier
]);
12697 /* Clear instruction information. */
12700 the_info
->insn_info_valid
= 0;
12701 the_info
->branch_delay_insns
= 0;
12702 the_info
->data_size
= 0;
12703 the_info
->insn_type
= dis_noninsn
;
12704 the_info
->target
= 0;
12705 the_info
->target2
= 0;
12708 /* Reset jump operation indicator. */
12709 op_is_jump
= FALSE
;
12712 int jump_detection
= 0;
12714 /* Extract flags. */
12715 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12717 if ((dp
->op
[i
].rtn
== OP_J
)
12718 || (dp
->op
[i
].rtn
== OP_indirE
))
12719 jump_detection
|= 1;
12720 else if ((dp
->op
[i
].rtn
== BND_Fixup
)
12721 || (!dp
->op
[i
].rtn
&& !dp
->op
[i
].bytemode
))
12722 jump_detection
|= 2;
12723 else if ((dp
->op
[i
].bytemode
== cond_jump_mode
)
12724 || (dp
->op
[i
].bytemode
== loop_jcxz_mode
))
12725 jump_detection
|= 4;
12728 /* Determine if this is a jump or branch. */
12729 if ((jump_detection
& 0x3) == 0x3)
12732 if (jump_detection
& 0x4)
12733 the_info
->insn_type
= dis_condbranch
;
12735 the_info
->insn_type
=
12736 (dp
->name
&& !strncmp(dp
->name
, "call", 4))
12737 ? dis_jsr
: dis_branch
;
12741 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12742 are all 0s in inverted form. */
12743 if (need_vex
&& vex
.register_specifier
!= 0)
12745 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12746 return end_codep
- priv
.the_buffer
;
12749 /* Check if the REX prefix is used. */
12750 if ((rex
^ rex_used
) == 0 && !need_vex
&& last_rex_prefix
>= 0)
12751 all_prefixes
[last_rex_prefix
] = 0;
12753 /* Check if the SEG prefix is used. */
12754 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
12755 | PREFIX_FS
| PREFIX_GS
)) != 0
12756 && (used_prefixes
& active_seg_prefix
) != 0)
12757 all_prefixes
[last_seg_prefix
] = 0;
12759 /* Check if the ADDR prefix is used. */
12760 if ((prefixes
& PREFIX_ADDR
) != 0
12761 && (used_prefixes
& PREFIX_ADDR
) != 0)
12762 all_prefixes
[last_addr_prefix
] = 0;
12764 /* Check if the DATA prefix is used. */
12765 if ((prefixes
& PREFIX_DATA
) != 0
12766 && (used_prefixes
& PREFIX_DATA
) != 0
12768 all_prefixes
[last_data_prefix
] = 0;
12770 /* Print the extra prefixes. */
12772 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12773 if (all_prefixes
[i
])
12776 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
12779 prefix_length
+= strlen (name
) + 1;
12780 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
12783 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12784 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
12785 used by putop and MMX/SSE operand and may be overriden by the
12786 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12788 if (dp
->prefix_requirement
== PREFIX_OPCODE
12790 ? vex
.prefix
== REPE_PREFIX_OPCODE
12791 || vex
.prefix
== REPNE_PREFIX_OPCODE
12793 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
12795 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
12797 ? vex
.prefix
== DATA_PREFIX_OPCODE
12799 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
12801 && (used_prefixes
& PREFIX_DATA
) == 0))
12802 || (vex
.evex
&& !vex
.w
!= !(used_prefixes
& PREFIX_DATA
))))
12804 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12805 return end_codep
- priv
.the_buffer
;
12808 /* Check maximum code length. */
12809 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
12811 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12812 return MAX_CODE_LENGTH
;
12815 obufp
= mnemonicendp
;
12816 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
12819 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
12821 /* The enter and bound instructions are printed with operands in the same
12822 order as the intel book; everything else is printed in reverse order. */
12823 if (intel_syntax
|| two_source_ops
)
12827 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12828 op_txt
[i
] = op_out
[i
];
12830 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
12831 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
12833 op_txt
[2] = op_out
[3];
12834 op_txt
[3] = op_out
[2];
12837 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
12839 op_ad
= op_index
[i
];
12840 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
12841 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
12842 riprel
= op_riprel
[i
];
12843 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
12844 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
12849 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12850 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
12854 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12858 (*info
->fprintf_func
) (info
->stream
, ",");
12859 if (op_index
[i
] != -1 && !op_riprel
[i
])
12861 bfd_vma target
= (bfd_vma
) op_address
[op_index
[i
]];
12863 if (the_info
&& op_is_jump
)
12865 the_info
->insn_info_valid
= 1;
12866 the_info
->branch_delay_insns
= 0;
12867 the_info
->data_size
= 0;
12868 the_info
->target
= target
;
12869 the_info
->target2
= 0;
12871 (*info
->print_address_func
) (target
, info
);
12874 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
12878 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12879 if (op_index
[i
] != -1 && op_riprel
[i
])
12881 (*info
->fprintf_func
) (info
->stream
, " # ");
12882 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
12883 + op_address
[op_index
[i
]]), info
);
12886 return codep
- priv
.the_buffer
;
12889 static const char *float_mem
[] = {
12964 static const unsigned char float_mem_mode
[] = {
13039 #define ST { OP_ST, 0 }
13040 #define STi { OP_STi, 0 }
13042 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13043 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13044 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13045 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13046 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13047 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13048 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13049 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13050 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13052 static const struct dis386 float_reg
[][8] = {
13055 { "fadd", { ST
, STi
}, 0 },
13056 { "fmul", { ST
, STi
}, 0 },
13057 { "fcom", { STi
}, 0 },
13058 { "fcomp", { STi
}, 0 },
13059 { "fsub", { ST
, STi
}, 0 },
13060 { "fsubr", { ST
, STi
}, 0 },
13061 { "fdiv", { ST
, STi
}, 0 },
13062 { "fdivr", { ST
, STi
}, 0 },
13066 { "fld", { STi
}, 0 },
13067 { "fxch", { STi
}, 0 },
13077 { "fcmovb", { ST
, STi
}, 0 },
13078 { "fcmove", { ST
, STi
}, 0 },
13079 { "fcmovbe",{ ST
, STi
}, 0 },
13080 { "fcmovu", { ST
, STi
}, 0 },
13088 { "fcmovnb",{ ST
, STi
}, 0 },
13089 { "fcmovne",{ ST
, STi
}, 0 },
13090 { "fcmovnbe",{ ST
, STi
}, 0 },
13091 { "fcmovnu",{ ST
, STi
}, 0 },
13093 { "fucomi", { ST
, STi
}, 0 },
13094 { "fcomi", { ST
, STi
}, 0 },
13099 { "fadd", { STi
, ST
}, 0 },
13100 { "fmul", { STi
, ST
}, 0 },
13103 { "fsub{!M|r}", { STi
, ST
}, 0 },
13104 { "fsub{M|}", { STi
, ST
}, 0 },
13105 { "fdiv{!M|r}", { STi
, ST
}, 0 },
13106 { "fdiv{M|}", { STi
, ST
}, 0 },
13110 { "ffree", { STi
}, 0 },
13112 { "fst", { STi
}, 0 },
13113 { "fstp", { STi
}, 0 },
13114 { "fucom", { STi
}, 0 },
13115 { "fucomp", { STi
}, 0 },
13121 { "faddp", { STi
, ST
}, 0 },
13122 { "fmulp", { STi
, ST
}, 0 },
13125 { "fsub{!M|r}p", { STi
, ST
}, 0 },
13126 { "fsub{M|}p", { STi
, ST
}, 0 },
13127 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
13128 { "fdiv{M|}p", { STi
, ST
}, 0 },
13132 { "ffreep", { STi
}, 0 },
13137 { "fucomip", { ST
, STi
}, 0 },
13138 { "fcomip", { ST
, STi
}, 0 },
13143 static char *fgrps
[][8] = {
13146 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13151 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13156 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13161 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13166 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13171 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13176 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13181 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13182 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13187 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13192 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13197 swap_operand (void)
13199 mnemonicendp
[0] = '.';
13200 mnemonicendp
[1] = 's';
13205 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
13206 int sizeflag ATTRIBUTE_UNUSED
)
13208 /* Skip mod/rm byte. */
13214 dofloat (int sizeflag
)
13216 const struct dis386
*dp
;
13217 unsigned char floatop
;
13219 floatop
= codep
[-1];
13221 if (modrm
.mod
!= 3)
13223 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
13225 putop (float_mem
[fp_indx
], sizeflag
);
13228 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
13231 /* Skip mod/rm byte. */
13235 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
13236 if (dp
->name
== NULL
)
13238 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
13240 /* Instruction fnstsw is only one with strange arg. */
13241 if (floatop
== 0xdf && codep
[-1] == 0xe0)
13242 strcpy (op_out
[0], names16
[0]);
13246 putop (dp
->name
, sizeflag
);
13251 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
13256 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
13260 /* Like oappend (below), but S is a string starting with '%'.
13261 In Intel syntax, the '%' is elided. */
13263 oappend_maybe_intel (const char *s
)
13265 oappend (s
+ intel_syntax
);
13269 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13271 oappend_maybe_intel ("%st");
13275 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13277 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
13278 oappend_maybe_intel (scratchbuf
);
13281 /* Capital letters in template are macros. */
13283 putop (const char *in_template
, int sizeflag
)
13288 unsigned int l
= 0, len
= 0;
13291 for (p
= in_template
; *p
; p
++)
13295 if (l
>= sizeof (last
) || !ISUPPER (*p
))
13314 while (*++p
!= '|')
13315 if (*p
== '}' || *p
== '\0')
13321 while (*++p
!= '}')
13333 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13342 if (sizeflag
& SUFFIX_ALWAYS
)
13345 else if (l
== 1 && last
[0] == 'L')
13347 if (address_mode
== mode_64bit
13348 && !(prefixes
& PREFIX_ADDR
))
13361 if (intel_syntax
&& !alt
)
13363 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13365 if (sizeflag
& DFLAG
)
13366 *obufp
++ = intel_syntax
? 'd' : 'l';
13368 *obufp
++ = intel_syntax
? 'w' : 's';
13369 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13373 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
13376 if (modrm
.mod
== 3)
13382 if (sizeflag
& DFLAG
)
13383 *obufp
++ = intel_syntax
? 'd' : 'l';
13386 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13392 case 'E': /* For jcxz/jecxz */
13393 if (address_mode
== mode_64bit
)
13395 if (sizeflag
& AFLAG
)
13401 if (sizeflag
& AFLAG
)
13403 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
13408 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
13410 if (sizeflag
& AFLAG
)
13411 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
13413 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
13414 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
13418 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
13420 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13424 if (!(rex
& REX_W
))
13425 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13430 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
13431 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
13433 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
13436 if (prefixes
& PREFIX_DS
)
13452 if (l
!= 1 || last
[0] != 'X')
13454 if (!need_vex
|| !vex
.evex
)
13457 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
13459 switch (vex
.length
)
13477 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
13482 /* Fall through. */
13490 if (sizeflag
& SUFFIX_ALWAYS
)
13494 if (intel_mnemonic
!= cond
)
13498 if ((prefixes
& PREFIX_FWAIT
) == 0)
13501 used_prefixes
|= PREFIX_FWAIT
;
13507 else if (intel_syntax
&& (sizeflag
& DFLAG
))
13511 if (!(rex
& REX_W
))
13512 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13516 && address_mode
== mode_64bit
13517 && isa64
== intel64
)
13522 /* Fall through. */
13525 && address_mode
== mode_64bit
13526 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13531 /* Fall through. */
13539 if ((rex
& REX_W
) == 0
13540 && (prefixes
& PREFIX_DATA
))
13542 if ((sizeflag
& DFLAG
) == 0)
13544 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13548 if ((prefixes
& PREFIX_DATA
)
13550 || (sizeflag
& SUFFIX_ALWAYS
))
13557 if (sizeflag
& DFLAG
)
13561 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13565 else if (l
== 1 && last
[0] == 'L')
13567 if ((prefixes
& PREFIX_DATA
)
13569 || (sizeflag
& SUFFIX_ALWAYS
))
13576 if (sizeflag
& DFLAG
)
13577 *obufp
++ = intel_syntax
? 'd' : 'l';
13580 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13590 if (address_mode
== mode_64bit
13591 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13593 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13597 /* Fall through. */
13603 if (intel_syntax
&& !alt
)
13606 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13612 if (sizeflag
& DFLAG
)
13613 *obufp
++ = intel_syntax
? 'd' : 'l';
13616 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13620 else if (l
== 1 && last
[0] == 'D')
13621 *obufp
++ = vex
.w
? 'q' : 'd';
13622 else if (l
== 1 && last
[0] == 'L')
13624 if (cond
? modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)
13625 : address_mode
!= mode_64bit
)
13632 else if((address_mode
== mode_64bit
&& need_modrm
&& cond
)
13633 || (sizeflag
& SUFFIX_ALWAYS
))
13634 *obufp
++ = intel_syntax
? 'd' : 'l';
13643 else if (sizeflag
& DFLAG
)
13652 if (intel_syntax
&& !p
[1]
13653 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
13655 if (!(rex
& REX_W
))
13656 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13663 if (address_mode
== mode_64bit
13664 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13666 if (sizeflag
& SUFFIX_ALWAYS
)
13671 else if (l
== 1 && last
[0] == 'L')
13682 /* Fall through. */
13690 if (sizeflag
& SUFFIX_ALWAYS
)
13696 if (sizeflag
& DFLAG
)
13700 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13704 else if (l
== 1 && last
[0] == 'L')
13706 if (address_mode
== mode_64bit
13707 && !(prefixes
& PREFIX_ADDR
))
13723 ? vex
.prefix
== DATA_PREFIX_OPCODE
13724 : prefixes
& PREFIX_DATA
)
13727 used_prefixes
|= PREFIX_DATA
;
13733 if (l
== 1 && last
[0] == 'X')
13738 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
13740 switch (vex
.length
)
13760 /* operand size flag for cwtl, cbtw */
13769 else if (sizeflag
& DFLAG
)
13773 if (!(rex
& REX_W
))
13774 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13780 if (last
[0] == 'X')
13781 *obufp
++ = vex
.w
? 'd': 's';
13782 else if (last
[0] == 'B')
13783 *obufp
++ = vex
.w
? 'w': 'b';
13793 if (isa64
== intel64
&& (rex
& REX_W
))
13799 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13801 if (sizeflag
& DFLAG
)
13805 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13811 if (address_mode
== mode_64bit
13812 && (isa64
== intel64
13813 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
13815 else if ((prefixes
& PREFIX_DATA
))
13817 if (!(sizeflag
& DFLAG
))
13819 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13828 mnemonicendp
= obufp
;
13833 oappend (const char *s
)
13835 obufp
= stpcpy (obufp
, s
);
13841 /* Only print the active segment register. */
13842 if (!active_seg_prefix
)
13845 used_prefixes
|= active_seg_prefix
;
13846 switch (active_seg_prefix
)
13849 oappend_maybe_intel ("%cs:");
13852 oappend_maybe_intel ("%ds:");
13855 oappend_maybe_intel ("%ss:");
13858 oappend_maybe_intel ("%es:");
13861 oappend_maybe_intel ("%fs:");
13864 oappend_maybe_intel ("%gs:");
13872 OP_indirE (int bytemode
, int sizeflag
)
13876 OP_E (bytemode
, sizeflag
);
13880 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
13882 if (address_mode
== mode_64bit
)
13890 sprintf_vma (tmp
, disp
);
13891 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
13892 strcpy (buf
+ 2, tmp
+ i
);
13896 bfd_signed_vma v
= disp
;
13903 /* Check for possible overflow on 0x8000000000000000. */
13906 strcpy (buf
, "9223372036854775808");
13920 tmp
[28 - i
] = (v
% 10) + '0';
13924 strcpy (buf
, tmp
+ 29 - i
);
13930 sprintf (buf
, "0x%x", (unsigned int) disp
);
13932 sprintf (buf
, "%d", (int) disp
);
13936 /* Put DISP in BUF as signed hex number. */
13939 print_displacement (char *buf
, bfd_vma disp
)
13941 bfd_signed_vma val
= disp
;
13950 /* Check for possible overflow. */
13953 switch (address_mode
)
13956 strcpy (buf
+ j
, "0x8000000000000000");
13959 strcpy (buf
+ j
, "0x80000000");
13962 strcpy (buf
+ j
, "0x8000");
13972 sprintf_vma (tmp
, (bfd_vma
) val
);
13973 for (i
= 0; tmp
[i
] == '0'; i
++)
13975 if (tmp
[i
] == '\0')
13977 strcpy (buf
+ j
, tmp
+ i
);
13981 intel_operand_size (int bytemode
, int sizeflag
)
13985 && (bytemode
== x_mode
13986 || bytemode
== evex_half_bcst_xmmq_mode
))
13989 oappend ("QWORD PTR ");
13991 oappend ("DWORD PTR ");
14000 oappend ("BYTE PTR ");
14005 oappend ("WORD PTR ");
14008 if (address_mode
== mode_64bit
&& isa64
== intel64
)
14010 oappend ("QWORD PTR ");
14013 /* Fall through. */
14015 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14017 oappend ("QWORD PTR ");
14020 /* Fall through. */
14026 oappend ("QWORD PTR ");
14029 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
14030 oappend ("DWORD PTR ");
14032 oappend ("WORD PTR ");
14033 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14037 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14039 oappend ("WORD PTR ");
14040 if (!(rex
& REX_W
))
14041 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14044 if (sizeflag
& DFLAG
)
14045 oappend ("QWORD PTR ");
14047 oappend ("DWORD PTR ");
14048 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14051 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
14052 oappend ("WORD PTR ");
14054 oappend ("DWORD PTR ");
14055 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14060 oappend ("DWORD PTR ");
14064 oappend ("QWORD PTR ");
14067 if (address_mode
== mode_64bit
)
14068 oappend ("QWORD PTR ");
14070 oappend ("DWORD PTR ");
14073 if (sizeflag
& DFLAG
)
14074 oappend ("FWORD PTR ");
14076 oappend ("DWORD PTR ");
14077 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14080 oappend ("TBYTE PTR ");
14084 case evex_x_gscat_mode
:
14085 case evex_x_nobcst_mode
:
14089 switch (vex
.length
)
14092 oappend ("XMMWORD PTR ");
14095 oappend ("YMMWORD PTR ");
14098 oappend ("ZMMWORD PTR ");
14105 oappend ("XMMWORD PTR ");
14108 oappend ("XMMWORD PTR ");
14111 oappend ("YMMWORD PTR ");
14114 case evex_half_bcst_xmmq_mode
:
14118 switch (vex
.length
)
14121 oappend ("QWORD PTR ");
14124 oappend ("XMMWORD PTR ");
14127 oappend ("YMMWORD PTR ");
14137 switch (vex
.length
)
14142 oappend ("BYTE PTR ");
14152 switch (vex
.length
)
14157 oappend ("WORD PTR ");
14167 switch (vex
.length
)
14172 oappend ("DWORD PTR ");
14182 switch (vex
.length
)
14187 oappend ("QWORD PTR ");
14197 switch (vex
.length
)
14200 oappend ("WORD PTR ");
14203 oappend ("DWORD PTR ");
14206 oappend ("QWORD PTR ");
14216 switch (vex
.length
)
14219 oappend ("DWORD PTR ");
14222 oappend ("QWORD PTR ");
14225 oappend ("XMMWORD PTR ");
14235 switch (vex
.length
)
14238 oappend ("QWORD PTR ");
14241 oappend ("YMMWORD PTR ");
14244 oappend ("ZMMWORD PTR ");
14254 switch (vex
.length
)
14258 oappend ("XMMWORD PTR ");
14265 oappend ("OWORD PTR ");
14267 case vex_scalar_w_dq_mode
:
14272 oappend ("QWORD PTR ");
14274 oappend ("DWORD PTR ");
14276 case vex_vsib_d_w_dq_mode
:
14277 case vex_vsib_q_w_dq_mode
:
14284 oappend ("QWORD PTR ");
14286 oappend ("DWORD PTR ");
14290 switch (vex
.length
)
14293 oappend ("XMMWORD PTR ");
14296 oappend ("YMMWORD PTR ");
14299 oappend ("ZMMWORD PTR ");
14306 case vex_vsib_q_w_d_mode
:
14307 case vex_vsib_d_w_d_mode
:
14308 if (!need_vex
|| !vex
.evex
)
14311 switch (vex
.length
)
14314 oappend ("QWORD PTR ");
14317 oappend ("XMMWORD PTR ");
14320 oappend ("YMMWORD PTR ");
14328 if (!need_vex
|| vex
.length
!= 128)
14331 oappend ("DWORD PTR ");
14333 oappend ("BYTE PTR ");
14339 oappend ("QWORD PTR ");
14341 oappend ("WORD PTR ");
14351 OP_E_register (int bytemode
, int sizeflag
)
14353 int reg
= modrm
.rm
;
14354 const char **names
;
14360 if ((sizeflag
& SUFFIX_ALWAYS
)
14361 && (bytemode
== b_swap_mode
14362 || bytemode
== bnd_swap_mode
14363 || bytemode
== v_swap_mode
))
14390 names
= address_mode
== mode_64bit
? names64
: names32
;
14393 case bnd_swap_mode
:
14402 if (address_mode
== mode_64bit
&& isa64
== intel64
)
14407 /* Fall through. */
14409 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14415 /* Fall through. */
14427 if ((sizeflag
& DFLAG
)
14428 || (bytemode
!= v_mode
14429 && bytemode
!= v_swap_mode
))
14433 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14437 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
14441 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14444 names
= (address_mode
== mode_64bit
14445 ? names64
: names32
);
14446 if (!(prefixes
& PREFIX_ADDR
))
14447 names
= (address_mode
== mode_16bit
14448 ? names16
: names
);
14451 /* Remove "addr16/addr32". */
14452 all_prefixes
[last_addr_prefix
] = 0;
14453 names
= (address_mode
!= mode_32bit
14454 ? names32
: names16
);
14455 used_prefixes
|= PREFIX_ADDR
;
14465 names
= names_mask
;
14470 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14473 oappend (names
[reg
]);
14477 OP_E_memory (int bytemode
, int sizeflag
)
14480 int add
= (rex
& REX_B
) ? 8 : 0;
14486 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
14488 && bytemode
!= x_mode
14489 && bytemode
!= xmmq_mode
14490 && bytemode
!= evex_half_bcst_xmmq_mode
)
14508 if (address_mode
!= mode_64bit
)
14518 case vex_scalar_w_dq_mode
:
14519 case vex_vsib_d_w_dq_mode
:
14520 case vex_vsib_d_w_d_mode
:
14521 case vex_vsib_q_w_dq_mode
:
14522 case vex_vsib_q_w_d_mode
:
14523 case evex_x_gscat_mode
:
14524 shift
= vex
.w
? 3 : 2;
14527 case evex_half_bcst_xmmq_mode
:
14531 shift
= vex
.w
? 3 : 2;
14534 /* Fall through. */
14538 case evex_x_nobcst_mode
:
14540 switch (vex
.length
)
14554 /* Make necessary corrections to shift for modes that need it. */
14555 if (bytemode
== xmmq_mode
14556 || bytemode
== evex_half_bcst_xmmq_mode
14557 || (bytemode
== ymmq_mode
&& vex
.length
== 128))
14559 else if (bytemode
== xmmqd_mode
)
14561 else if (bytemode
== xmmdw_mode
)
14576 shift
= vex
.w
? 1 : 0;
14587 intel_operand_size (bytemode
, sizeflag
);
14590 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14592 /* 32/64 bit address mode */
14602 int addr32flag
= !((sizeflag
& AFLAG
)
14603 || bytemode
== v_bnd_mode
14604 || bytemode
== v_bndmk_mode
14605 || bytemode
== bnd_mode
14606 || bytemode
== bnd_swap_mode
);
14607 const char **indexes64
= names64
;
14608 const char **indexes32
= names32
;
14618 vindex
= sib
.index
;
14624 case vex_vsib_d_w_dq_mode
:
14625 case vex_vsib_d_w_d_mode
:
14626 case vex_vsib_q_w_dq_mode
:
14627 case vex_vsib_q_w_d_mode
:
14637 switch (vex
.length
)
14640 indexes64
= indexes32
= names_xmm
;
14644 || bytemode
== vex_vsib_q_w_dq_mode
14645 || bytemode
== vex_vsib_q_w_d_mode
)
14646 indexes64
= indexes32
= names_ymm
;
14648 indexes64
= indexes32
= names_xmm
;
14652 || bytemode
== vex_vsib_q_w_dq_mode
14653 || bytemode
== vex_vsib_q_w_d_mode
)
14654 indexes64
= indexes32
= names_zmm
;
14656 indexes64
= indexes32
= names_ymm
;
14663 haveindex
= vindex
!= 4;
14672 /* mandatory non-vector SIB must have sib */
14673 if (bytemode
== vex_sibmem_mode
)
14679 rbase
= base
+ add
;
14687 if (address_mode
== mode_64bit
&& !havesib
)
14690 if (riprel
&& bytemode
== v_bndmk_mode
)
14698 FETCH_DATA (the_info
, codep
+ 1);
14700 if ((disp
& 0x80) != 0)
14702 if (vex
.evex
&& shift
> 0)
14715 && address_mode
!= mode_16bit
)
14717 if (address_mode
== mode_64bit
)
14719 /* Display eiz instead of addr32. */
14720 needindex
= addr32flag
;
14725 /* In 32-bit mode, we need index register to tell [offset]
14726 from [eiz*1 + offset]. */
14731 havedisp
= (havebase
14733 || (havesib
&& (haveindex
|| scale
!= 0)));
14736 if (modrm
.mod
!= 0 || base
== 5)
14738 if (havedisp
|| riprel
)
14739 print_displacement (scratchbuf
, disp
);
14741 print_operand_value (scratchbuf
, 1, disp
);
14742 oappend (scratchbuf
);
14746 oappend (!addr32flag
? "(%rip)" : "(%eip)");
14750 if ((havebase
|| haveindex
|| needindex
|| needaddr32
|| riprel
)
14751 && (address_mode
!= mode_64bit
14752 || ((bytemode
!= v_bnd_mode
)
14753 && (bytemode
!= v_bndmk_mode
)
14754 && (bytemode
!= bnd_mode
)
14755 && (bytemode
!= bnd_swap_mode
))))
14756 used_prefixes
|= PREFIX_ADDR
;
14758 if (havedisp
|| (intel_syntax
&& riprel
))
14760 *obufp
++ = open_char
;
14761 if (intel_syntax
&& riprel
)
14764 oappend (!addr32flag
? "rip" : "eip");
14768 oappend (address_mode
== mode_64bit
&& !addr32flag
14769 ? names64
[rbase
] : names32
[rbase
]);
14772 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14773 print index to tell base + index from base. */
14777 || (havebase
&& base
!= ESP_REG_NUM
))
14779 if (!intel_syntax
|| havebase
)
14781 *obufp
++ = separator_char
;
14785 oappend (address_mode
== mode_64bit
&& !addr32flag
14786 ? indexes64
[vindex
] : indexes32
[vindex
]);
14788 oappend (address_mode
== mode_64bit
&& !addr32flag
14789 ? index64
: index32
);
14791 *obufp
++ = scale_char
;
14793 sprintf (scratchbuf
, "%d", 1 << scale
);
14794 oappend (scratchbuf
);
14798 && (disp
|| modrm
.mod
!= 0 || base
== 5))
14800 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
14805 else if (modrm
.mod
!= 1 && disp
!= -disp
)
14809 disp
= - (bfd_signed_vma
) disp
;
14813 print_displacement (scratchbuf
, disp
);
14815 print_operand_value (scratchbuf
, 1, disp
);
14816 oappend (scratchbuf
);
14819 *obufp
++ = close_char
;
14822 else if (intel_syntax
)
14824 if (modrm
.mod
!= 0 || base
== 5)
14826 if (!active_seg_prefix
)
14828 oappend (names_seg
[ds_reg
- es_reg
]);
14831 print_operand_value (scratchbuf
, 1, disp
);
14832 oappend (scratchbuf
);
14836 else if (bytemode
== v_bnd_mode
14837 || bytemode
== v_bndmk_mode
14838 || bytemode
== bnd_mode
14839 || bytemode
== bnd_swap_mode
)
14846 /* 16 bit address mode */
14847 used_prefixes
|= prefixes
& PREFIX_ADDR
;
14854 if ((disp
& 0x8000) != 0)
14859 FETCH_DATA (the_info
, codep
+ 1);
14861 if ((disp
& 0x80) != 0)
14863 if (vex
.evex
&& shift
> 0)
14868 if ((disp
& 0x8000) != 0)
14874 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
14876 print_displacement (scratchbuf
, disp
);
14877 oappend (scratchbuf
);
14880 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
14882 *obufp
++ = open_char
;
14884 oappend (index16
[modrm
.rm
]);
14886 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
14888 if ((bfd_signed_vma
) disp
>= 0)
14893 else if (modrm
.mod
!= 1)
14897 disp
= - (bfd_signed_vma
) disp
;
14900 print_displacement (scratchbuf
, disp
);
14901 oappend (scratchbuf
);
14904 *obufp
++ = close_char
;
14907 else if (intel_syntax
)
14909 if (!active_seg_prefix
)
14911 oappend (names_seg
[ds_reg
- es_reg
]);
14914 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
14915 oappend (scratchbuf
);
14918 if (vex
.evex
&& vex
.b
14919 && (bytemode
== x_mode
14920 || bytemode
== xmmq_mode
14921 || bytemode
== evex_half_bcst_xmmq_mode
))
14924 || bytemode
== xmmq_mode
14925 || bytemode
== evex_half_bcst_xmmq_mode
)
14927 switch (vex
.length
)
14930 oappend ("{1to2}");
14933 oappend ("{1to4}");
14936 oappend ("{1to8}");
14944 switch (vex
.length
)
14947 oappend ("{1to4}");
14950 oappend ("{1to8}");
14953 oappend ("{1to16}");
14963 OP_E (int bytemode
, int sizeflag
)
14965 /* Skip mod/rm byte. */
14969 if (modrm
.mod
== 3)
14970 OP_E_register (bytemode
, sizeflag
);
14972 OP_E_memory (bytemode
, sizeflag
);
14976 OP_G (int bytemode
, int sizeflag
)
14979 const char **names
;
14989 oappend (names8rex
[modrm
.reg
+ add
]);
14991 oappend (names8
[modrm
.reg
+ add
]);
14994 oappend (names16
[modrm
.reg
+ add
]);
14999 oappend (names32
[modrm
.reg
+ add
]);
15002 oappend (names64
[modrm
.reg
+ add
]);
15005 if (modrm
.reg
> 0x3)
15010 oappend (names_bnd
[modrm
.reg
]);
15020 oappend (names64
[modrm
.reg
+ add
]);
15023 if ((sizeflag
& DFLAG
)
15024 || (bytemode
!= v_mode
&& bytemode
!= movsxd_mode
))
15025 oappend (names32
[modrm
.reg
+ add
]);
15027 oappend (names16
[modrm
.reg
+ add
]);
15028 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15032 names
= (address_mode
== mode_64bit
15033 ? names64
: names32
);
15034 if (!(prefixes
& PREFIX_ADDR
))
15036 if (address_mode
== mode_16bit
)
15041 /* Remove "addr16/addr32". */
15042 all_prefixes
[last_addr_prefix
] = 0;
15043 names
= (address_mode
!= mode_32bit
15044 ? names32
: names16
);
15045 used_prefixes
|= PREFIX_ADDR
;
15047 oappend (names
[modrm
.reg
+ add
]);
15050 if (address_mode
== mode_64bit
)
15051 oappend (names64
[modrm
.reg
+ add
]);
15053 oappend (names32
[modrm
.reg
+ add
]);
15057 if ((modrm
.reg
+ add
) > 0x7)
15062 oappend (names_mask
[modrm
.reg
+ add
]);
15065 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15078 FETCH_DATA (the_info
, codep
+ 8);
15079 a
= *codep
++ & 0xff;
15080 a
|= (*codep
++ & 0xff) << 8;
15081 a
|= (*codep
++ & 0xff) << 16;
15082 a
|= (*codep
++ & 0xffu
) << 24;
15083 b
= *codep
++ & 0xff;
15084 b
|= (*codep
++ & 0xff) << 8;
15085 b
|= (*codep
++ & 0xff) << 16;
15086 b
|= (*codep
++ & 0xffu
) << 24;
15087 x
= a
+ ((bfd_vma
) b
<< 32);
15095 static bfd_signed_vma
15098 bfd_signed_vma x
= 0;
15100 FETCH_DATA (the_info
, codep
+ 4);
15101 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15102 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15103 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15104 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15108 static bfd_signed_vma
15111 bfd_signed_vma x
= 0;
15113 FETCH_DATA (the_info
, codep
+ 4);
15114 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15115 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15116 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15117 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15119 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
15129 FETCH_DATA (the_info
, codep
+ 2);
15130 x
= *codep
++ & 0xff;
15131 x
|= (*codep
++ & 0xff) << 8;
15136 set_op (bfd_vma op
, int riprel
)
15138 op_index
[op_ad
] = op_ad
;
15139 if (address_mode
== mode_64bit
)
15141 op_address
[op_ad
] = op
;
15142 op_riprel
[op_ad
] = riprel
;
15146 /* Mask to get a 32-bit address. */
15147 op_address
[op_ad
] = op
& 0xffffffff;
15148 op_riprel
[op_ad
] = riprel
& 0xffffffff;
15153 OP_REG (int code
, int sizeflag
)
15160 case es_reg
: case ss_reg
: case cs_reg
:
15161 case ds_reg
: case fs_reg
: case gs_reg
:
15162 oappend (names_seg
[code
- es_reg
]);
15174 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15175 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15176 s
= names16
[code
- ax_reg
+ add
];
15178 case ah_reg
: case ch_reg
: case dh_reg
: case bh_reg
:
15180 /* Fall through. */
15181 case al_reg
: case cl_reg
: case dl_reg
: case bl_reg
:
15183 s
= names8rex
[code
- al_reg
+ add
];
15185 s
= names8
[code
- al_reg
];
15187 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
15188 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
15189 if (address_mode
== mode_64bit
15190 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15192 s
= names64
[code
- rAX_reg
+ add
];
15195 code
+= eAX_reg
- rAX_reg
;
15196 /* Fall through. */
15197 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15198 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15201 s
= names64
[code
- eAX_reg
+ add
];
15204 if (sizeflag
& DFLAG
)
15205 s
= names32
[code
- eAX_reg
+ add
];
15207 s
= names16
[code
- eAX_reg
+ add
];
15208 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15212 s
= INTERNAL_DISASSEMBLER_ERROR
;
15219 OP_IMREG (int code
, int sizeflag
)
15231 case al_reg
: case cl_reg
:
15232 s
= names8
[code
- al_reg
];
15241 /* Fall through. */
15242 case z_mode_ax_reg
:
15243 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
15247 if (!(rex
& REX_W
))
15248 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15251 s
= INTERNAL_DISASSEMBLER_ERROR
;
15258 OP_I (int bytemode
, int sizeflag
)
15261 bfd_signed_vma mask
= -1;
15266 FETCH_DATA (the_info
, codep
+ 1);
15276 if (sizeflag
& DFLAG
)
15286 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15302 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15307 scratchbuf
[0] = '$';
15308 print_operand_value (scratchbuf
+ 1, 1, op
);
15309 oappend_maybe_intel (scratchbuf
);
15310 scratchbuf
[0] = '\0';
15314 OP_I64 (int bytemode
, int sizeflag
)
15316 if (bytemode
!= v_mode
|| address_mode
!= mode_64bit
|| !(rex
& REX_W
))
15318 OP_I (bytemode
, sizeflag
);
15324 scratchbuf
[0] = '$';
15325 print_operand_value (scratchbuf
+ 1, 1, get64 ());
15326 oappend_maybe_intel (scratchbuf
);
15327 scratchbuf
[0] = '\0';
15331 OP_sI (int bytemode
, int sizeflag
)
15339 FETCH_DATA (the_info
, codep
+ 1);
15341 if ((op
& 0x80) != 0)
15343 if (bytemode
== b_T_mode
)
15345 if (address_mode
!= mode_64bit
15346 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15348 /* The operand-size prefix is overridden by a REX prefix. */
15349 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15357 if (!(rex
& REX_W
))
15359 if (sizeflag
& DFLAG
)
15367 /* The operand-size prefix is overridden by a REX prefix. */
15368 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15374 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15378 scratchbuf
[0] = '$';
15379 print_operand_value (scratchbuf
+ 1, 1, op
);
15380 oappend_maybe_intel (scratchbuf
);
15384 OP_J (int bytemode
, int sizeflag
)
15388 bfd_vma segment
= 0;
15393 FETCH_DATA (the_info
, codep
+ 1);
15395 if ((disp
& 0x80) != 0)
15399 if (isa64
!= intel64
)
15402 if ((sizeflag
& DFLAG
)
15403 || (address_mode
== mode_64bit
15404 && ((isa64
== intel64
&& bytemode
!= dqw_mode
)
15405 || (rex
& REX_W
))))
15410 if ((disp
& 0x8000) != 0)
15412 /* In 16bit mode, address is wrapped around at 64k within
15413 the same segment. Otherwise, a data16 prefix on a jump
15414 instruction means that the pc is masked to 16 bits after
15415 the displacement is added! */
15417 if ((prefixes
& PREFIX_DATA
) == 0)
15418 segment
= ((start_pc
+ (codep
- start_codep
))
15419 & ~((bfd_vma
) 0xffff));
15421 if (address_mode
!= mode_64bit
15422 || (isa64
!= intel64
&& !(rex
& REX_W
)))
15423 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15426 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15429 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
15431 print_operand_value (scratchbuf
, 1, disp
);
15432 oappend (scratchbuf
);
15436 OP_SEG (int bytemode
, int sizeflag
)
15438 if (bytemode
== w_mode
)
15439 oappend (names_seg
[modrm
.reg
]);
15441 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
15445 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
15449 if (sizeflag
& DFLAG
)
15459 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15461 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
15463 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
15464 oappend (scratchbuf
);
15468 OP_OFF (int bytemode
, int sizeflag
)
15472 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
15473 intel_operand_size (bytemode
, sizeflag
);
15476 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15483 if (!active_seg_prefix
)
15485 oappend (names_seg
[ds_reg
- es_reg
]);
15489 print_operand_value (scratchbuf
, 1, off
);
15490 oappend (scratchbuf
);
15494 OP_OFF64 (int bytemode
, int sizeflag
)
15498 if (address_mode
!= mode_64bit
15499 || (prefixes
& PREFIX_ADDR
))
15501 OP_OFF (bytemode
, sizeflag
);
15505 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
15506 intel_operand_size (bytemode
, sizeflag
);
15513 if (!active_seg_prefix
)
15515 oappend (names_seg
[ds_reg
- es_reg
]);
15519 print_operand_value (scratchbuf
, 1, off
);
15520 oappend (scratchbuf
);
15524 ptr_reg (int code
, int sizeflag
)
15528 *obufp
++ = open_char
;
15529 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
15530 if (address_mode
== mode_64bit
)
15532 if (!(sizeflag
& AFLAG
))
15533 s
= names32
[code
- eAX_reg
];
15535 s
= names64
[code
- eAX_reg
];
15537 else if (sizeflag
& AFLAG
)
15538 s
= names32
[code
- eAX_reg
];
15540 s
= names16
[code
- eAX_reg
];
15542 *obufp
++ = close_char
;
15547 OP_ESreg (int code
, int sizeflag
)
15553 case 0x6d: /* insw/insl */
15554 intel_operand_size (z_mode
, sizeflag
);
15556 case 0xa5: /* movsw/movsl/movsq */
15557 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15558 case 0xab: /* stosw/stosl */
15559 case 0xaf: /* scasw/scasl */
15560 intel_operand_size (v_mode
, sizeflag
);
15563 intel_operand_size (b_mode
, sizeflag
);
15566 oappend_maybe_intel ("%es:");
15567 ptr_reg (code
, sizeflag
);
15571 OP_DSreg (int code
, int sizeflag
)
15577 case 0x6f: /* outsw/outsl */
15578 intel_operand_size (z_mode
, sizeflag
);
15580 case 0xa5: /* movsw/movsl/movsq */
15581 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15582 case 0xad: /* lodsw/lodsl/lodsq */
15583 intel_operand_size (v_mode
, sizeflag
);
15586 intel_operand_size (b_mode
, sizeflag
);
15589 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15590 default segment register DS is printed. */
15591 if (!active_seg_prefix
)
15592 active_seg_prefix
= PREFIX_DS
;
15594 ptr_reg (code
, sizeflag
);
15598 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15606 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
15608 all_prefixes
[last_lock_prefix
] = 0;
15609 used_prefixes
|= PREFIX_LOCK
;
15614 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
15615 oappend_maybe_intel (scratchbuf
);
15619 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15628 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
15630 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
15631 oappend (scratchbuf
);
15635 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15637 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
15638 oappend_maybe_intel (scratchbuf
);
15642 OP_R (int bytemode
, int sizeflag
)
15644 /* Skip mod/rm byte. */
15647 OP_E_register (bytemode
, sizeflag
);
15651 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15653 int reg
= modrm
.reg
;
15654 const char **names
;
15656 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15657 if (prefixes
& PREFIX_DATA
)
15666 oappend (names
[reg
]);
15670 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15672 int reg
= modrm
.reg
;
15673 const char **names
;
15685 && bytemode
!= xmm_mode
15686 && bytemode
!= xmmq_mode
15687 && bytemode
!= evex_half_bcst_xmmq_mode
15688 && bytemode
!= ymm_mode
15689 && bytemode
!= tmm_mode
15690 && bytemode
!= scalar_mode
)
15692 switch (vex
.length
)
15699 || (bytemode
!= vex_vsib_q_w_dq_mode
15700 && bytemode
!= vex_vsib_q_w_d_mode
))
15712 else if (bytemode
== xmmq_mode
15713 || bytemode
== evex_half_bcst_xmmq_mode
)
15715 switch (vex
.length
)
15728 else if (bytemode
== tmm_mode
)
15738 else if (bytemode
== ymm_mode
)
15742 oappend (names
[reg
]);
15746 OP_EM (int bytemode
, int sizeflag
)
15749 const char **names
;
15751 if (modrm
.mod
!= 3)
15754 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
15756 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15757 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15759 OP_E (bytemode
, sizeflag
);
15763 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
15766 /* Skip mod/rm byte. */
15769 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15771 if (prefixes
& PREFIX_DATA
)
15780 oappend (names
[reg
]);
15783 /* cvt* are the only instructions in sse2 which have
15784 both SSE and MMX operands and also have 0x66 prefix
15785 in their opcode. 0x66 was originally used to differentiate
15786 between SSE and MMX instruction(operands). So we have to handle the
15787 cvt* separately using OP_EMC and OP_MXC */
15789 OP_EMC (int bytemode
, int sizeflag
)
15791 if (modrm
.mod
!= 3)
15793 if (intel_syntax
&& bytemode
== v_mode
)
15795 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15796 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15798 OP_E (bytemode
, sizeflag
);
15802 /* Skip mod/rm byte. */
15805 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15806 oappend (names_mm
[modrm
.rm
]);
15810 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15812 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15813 oappend (names_mm
[modrm
.reg
]);
15817 OP_EX (int bytemode
, int sizeflag
)
15820 const char **names
;
15822 /* Skip mod/rm byte. */
15826 if (modrm
.mod
!= 3)
15828 OP_E_memory (bytemode
, sizeflag
);
15843 if ((sizeflag
& SUFFIX_ALWAYS
)
15844 && (bytemode
== x_swap_mode
15845 || bytemode
== d_swap_mode
15846 || bytemode
== q_swap_mode
))
15850 && bytemode
!= xmm_mode
15851 && bytemode
!= xmmdw_mode
15852 && bytemode
!= xmmqd_mode
15853 && bytemode
!= xmm_mb_mode
15854 && bytemode
!= xmm_mw_mode
15855 && bytemode
!= xmm_md_mode
15856 && bytemode
!= xmm_mq_mode
15857 && bytemode
!= xmmq_mode
15858 && bytemode
!= evex_half_bcst_xmmq_mode
15859 && bytemode
!= ymm_mode
15860 && bytemode
!= tmm_mode
15861 && bytemode
!= vex_scalar_w_dq_mode
)
15863 switch (vex
.length
)
15878 else if (bytemode
== xmmq_mode
15879 || bytemode
== evex_half_bcst_xmmq_mode
)
15881 switch (vex
.length
)
15894 else if (bytemode
== tmm_mode
)
15904 else if (bytemode
== ymm_mode
)
15908 oappend (names
[reg
]);
15912 OP_MS (int bytemode
, int sizeflag
)
15914 if (modrm
.mod
== 3)
15915 OP_EM (bytemode
, sizeflag
);
15921 OP_XS (int bytemode
, int sizeflag
)
15923 if (modrm
.mod
== 3)
15924 OP_EX (bytemode
, sizeflag
);
15930 OP_M (int bytemode
, int sizeflag
)
15932 if (modrm
.mod
== 3)
15933 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15936 OP_E (bytemode
, sizeflag
);
15940 OP_0f07 (int bytemode
, int sizeflag
)
15942 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
15945 OP_E (bytemode
, sizeflag
);
15948 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15949 32bit mode and "xchg %rax,%rax" in 64bit mode. */
15952 NOP_Fixup1 (int bytemode
, int sizeflag
)
15954 if ((prefixes
& PREFIX_DATA
) != 0
15957 && address_mode
== mode_64bit
))
15958 OP_REG (bytemode
, sizeflag
);
15960 strcpy (obuf
, "nop");
15964 NOP_Fixup2 (int bytemode
, int sizeflag
)
15966 if ((prefixes
& PREFIX_DATA
) != 0
15969 && address_mode
== mode_64bit
))
15970 OP_IMREG (bytemode
, sizeflag
);
15973 static const char *const Suffix3DNow
[] = {
15974 /* 00 */ NULL
, NULL
, NULL
, NULL
,
15975 /* 04 */ NULL
, NULL
, NULL
, NULL
,
15976 /* 08 */ NULL
, NULL
, NULL
, NULL
,
15977 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
15978 /* 10 */ NULL
, NULL
, NULL
, NULL
,
15979 /* 14 */ NULL
, NULL
, NULL
, NULL
,
15980 /* 18 */ NULL
, NULL
, NULL
, NULL
,
15981 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
15982 /* 20 */ NULL
, NULL
, NULL
, NULL
,
15983 /* 24 */ NULL
, NULL
, NULL
, NULL
,
15984 /* 28 */ NULL
, NULL
, NULL
, NULL
,
15985 /* 2C */ NULL
, NULL
, NULL
, NULL
,
15986 /* 30 */ NULL
, NULL
, NULL
, NULL
,
15987 /* 34 */ NULL
, NULL
, NULL
, NULL
,
15988 /* 38 */ NULL
, NULL
, NULL
, NULL
,
15989 /* 3C */ NULL
, NULL
, NULL
, NULL
,
15990 /* 40 */ NULL
, NULL
, NULL
, NULL
,
15991 /* 44 */ NULL
, NULL
, NULL
, NULL
,
15992 /* 48 */ NULL
, NULL
, NULL
, NULL
,
15993 /* 4C */ NULL
, NULL
, NULL
, NULL
,
15994 /* 50 */ NULL
, NULL
, NULL
, NULL
,
15995 /* 54 */ NULL
, NULL
, NULL
, NULL
,
15996 /* 58 */ NULL
, NULL
, NULL
, NULL
,
15997 /* 5C */ NULL
, NULL
, NULL
, NULL
,
15998 /* 60 */ NULL
, NULL
, NULL
, NULL
,
15999 /* 64 */ NULL
, NULL
, NULL
, NULL
,
16000 /* 68 */ NULL
, NULL
, NULL
, NULL
,
16001 /* 6C */ NULL
, NULL
, NULL
, NULL
,
16002 /* 70 */ NULL
, NULL
, NULL
, NULL
,
16003 /* 74 */ NULL
, NULL
, NULL
, NULL
,
16004 /* 78 */ NULL
, NULL
, NULL
, NULL
,
16005 /* 7C */ NULL
, NULL
, NULL
, NULL
,
16006 /* 80 */ NULL
, NULL
, NULL
, NULL
,
16007 /* 84 */ NULL
, NULL
, NULL
, NULL
,
16008 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
16009 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
16010 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
16011 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
16012 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
16013 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
16014 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
16015 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
16016 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
16017 /* AC */ NULL
, NULL
, "pfacc", NULL
,
16018 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
16019 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
16020 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
16021 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
16022 /* C0 */ NULL
, NULL
, NULL
, NULL
,
16023 /* C4 */ NULL
, NULL
, NULL
, NULL
,
16024 /* C8 */ NULL
, NULL
, NULL
, NULL
,
16025 /* CC */ NULL
, NULL
, NULL
, NULL
,
16026 /* D0 */ NULL
, NULL
, NULL
, NULL
,
16027 /* D4 */ NULL
, NULL
, NULL
, NULL
,
16028 /* D8 */ NULL
, NULL
, NULL
, NULL
,
16029 /* DC */ NULL
, NULL
, NULL
, NULL
,
16030 /* E0 */ NULL
, NULL
, NULL
, NULL
,
16031 /* E4 */ NULL
, NULL
, NULL
, NULL
,
16032 /* E8 */ NULL
, NULL
, NULL
, NULL
,
16033 /* EC */ NULL
, NULL
, NULL
, NULL
,
16034 /* F0 */ NULL
, NULL
, NULL
, NULL
,
16035 /* F4 */ NULL
, NULL
, NULL
, NULL
,
16036 /* F8 */ NULL
, NULL
, NULL
, NULL
,
16037 /* FC */ NULL
, NULL
, NULL
, NULL
,
16041 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16043 const char *mnemonic
;
16045 FETCH_DATA (the_info
, codep
+ 1);
16046 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16047 place where an 8-bit immediate would normally go. ie. the last
16048 byte of the instruction. */
16049 obufp
= mnemonicendp
;
16050 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
16052 oappend (mnemonic
);
16055 /* Since a variable sized modrm/sib chunk is between the start
16056 of the opcode (0x0f0f) and the opcode suffix, we need to do
16057 all the modrm processing first, and don't know until now that
16058 we have a bad opcode. This necessitates some cleaning up. */
16059 op_out
[0][0] = '\0';
16060 op_out
[1][0] = '\0';
16063 mnemonicendp
= obufp
;
16066 static const struct op simd_cmp_op
[] =
16068 { STRING_COMMA_LEN ("eq") },
16069 { STRING_COMMA_LEN ("lt") },
16070 { STRING_COMMA_LEN ("le") },
16071 { STRING_COMMA_LEN ("unord") },
16072 { STRING_COMMA_LEN ("neq") },
16073 { STRING_COMMA_LEN ("nlt") },
16074 { STRING_COMMA_LEN ("nle") },
16075 { STRING_COMMA_LEN ("ord") }
16078 static const struct op vex_cmp_op
[] =
16080 { STRING_COMMA_LEN ("eq_uq") },
16081 { STRING_COMMA_LEN ("nge") },
16082 { STRING_COMMA_LEN ("ngt") },
16083 { STRING_COMMA_LEN ("false") },
16084 { STRING_COMMA_LEN ("neq_oq") },
16085 { STRING_COMMA_LEN ("ge") },
16086 { STRING_COMMA_LEN ("gt") },
16087 { STRING_COMMA_LEN ("true") },
16088 { STRING_COMMA_LEN ("eq_os") },
16089 { STRING_COMMA_LEN ("lt_oq") },
16090 { STRING_COMMA_LEN ("le_oq") },
16091 { STRING_COMMA_LEN ("unord_s") },
16092 { STRING_COMMA_LEN ("neq_us") },
16093 { STRING_COMMA_LEN ("nlt_uq") },
16094 { STRING_COMMA_LEN ("nle_uq") },
16095 { STRING_COMMA_LEN ("ord_s") },
16096 { STRING_COMMA_LEN ("eq_us") },
16097 { STRING_COMMA_LEN ("nge_uq") },
16098 { STRING_COMMA_LEN ("ngt_uq") },
16099 { STRING_COMMA_LEN ("false_os") },
16100 { STRING_COMMA_LEN ("neq_os") },
16101 { STRING_COMMA_LEN ("ge_oq") },
16102 { STRING_COMMA_LEN ("gt_oq") },
16103 { STRING_COMMA_LEN ("true_us") },
16107 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16109 unsigned int cmp_type
;
16111 FETCH_DATA (the_info
, codep
+ 1);
16112 cmp_type
= *codep
++ & 0xff;
16113 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
16116 char *p
= mnemonicendp
- 2;
16120 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16121 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16124 && cmp_type
< ARRAY_SIZE (simd_cmp_op
) + ARRAY_SIZE (vex_cmp_op
))
16127 char *p
= mnemonicendp
- 2;
16131 cmp_type
-= ARRAY_SIZE (simd_cmp_op
);
16132 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
16133 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
16137 /* We have a reserved extension byte. Output it directly. */
16138 scratchbuf
[0] = '$';
16139 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16140 oappend_maybe_intel (scratchbuf
);
16141 scratchbuf
[0] = '\0';
16146 OP_Mwait (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16148 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
16151 strcpy (op_out
[0], names32
[0]);
16152 strcpy (op_out
[1], names32
[1]);
16153 if (bytemode
== eBX_reg
)
16154 strcpy (op_out
[2], names32
[3]);
16155 two_source_ops
= 1;
16157 /* Skip mod/rm byte. */
16163 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
16164 int sizeflag ATTRIBUTE_UNUSED
)
16166 /* monitor %{e,r,}ax,%ecx,%edx" */
16169 const char **names
= (address_mode
== mode_64bit
16170 ? names64
: names32
);
16172 if (prefixes
& PREFIX_ADDR
)
16174 /* Remove "addr16/addr32". */
16175 all_prefixes
[last_addr_prefix
] = 0;
16176 names
= (address_mode
!= mode_32bit
16177 ? names32
: names16
);
16178 used_prefixes
|= PREFIX_ADDR
;
16180 else if (address_mode
== mode_16bit
)
16182 strcpy (op_out
[0], names
[0]);
16183 strcpy (op_out
[1], names32
[1]);
16184 strcpy (op_out
[2], names32
[2]);
16185 two_source_ops
= 1;
16187 /* Skip mod/rm byte. */
16195 /* Throw away prefixes and 1st. opcode byte. */
16196 codep
= insn_codep
+ 1;
16201 REP_Fixup (int bytemode
, int sizeflag
)
16203 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16205 if (prefixes
& PREFIX_REPZ
)
16206 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
16213 OP_IMREG (bytemode
, sizeflag
);
16216 OP_ESreg (bytemode
, sizeflag
);
16219 OP_DSreg (bytemode
, sizeflag
);
16228 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16230 if ( isa64
!= amd64
)
16235 mnemonicendp
= obufp
;
16239 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16243 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16245 if (prefixes
& PREFIX_REPNZ
)
16246 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
16249 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16253 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16254 int sizeflag ATTRIBUTE_UNUSED
)
16256 if (active_seg_prefix
== PREFIX_DS
16257 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
16259 /* NOTRACK prefix is only valid on indirect branch instructions.
16260 NB: DATA prefix is unsupported for Intel64. */
16261 active_seg_prefix
= 0;
16262 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
16266 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16267 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16271 HLE_Fixup1 (int bytemode
, int sizeflag
)
16274 && (prefixes
& PREFIX_LOCK
) != 0)
16276 if (prefixes
& PREFIX_REPZ
)
16277 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16278 if (prefixes
& PREFIX_REPNZ
)
16279 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16282 OP_E (bytemode
, sizeflag
);
16285 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16286 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
16290 HLE_Fixup2 (int bytemode
, int sizeflag
)
16292 if (modrm
.mod
!= 3)
16294 if (prefixes
& PREFIX_REPZ
)
16295 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16296 if (prefixes
& PREFIX_REPNZ
)
16297 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16300 OP_E (bytemode
, sizeflag
);
16303 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
16304 "xrelease" for memory operand. No check for LOCK prefix. */
16307 HLE_Fixup3 (int bytemode
, int sizeflag
)
16310 && last_repz_prefix
> last_repnz_prefix
16311 && (prefixes
& PREFIX_REPZ
) != 0)
16312 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16314 OP_E (bytemode
, sizeflag
);
16318 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
16323 /* Change cmpxchg8b to cmpxchg16b. */
16324 char *p
= mnemonicendp
- 2;
16325 mnemonicendp
= stpcpy (p
, "16b");
16328 else if ((prefixes
& PREFIX_LOCK
) != 0)
16330 if (prefixes
& PREFIX_REPZ
)
16331 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16332 if (prefixes
& PREFIX_REPNZ
)
16333 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16336 OP_M (bytemode
, sizeflag
);
16340 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
16342 const char **names
;
16346 switch (vex
.length
)
16360 oappend (names
[reg
]);
16364 FXSAVE_Fixup (int bytemode
, int sizeflag
)
16366 /* Add proper suffix to "fxsave" and "fxrstor". */
16370 char *p
= mnemonicendp
;
16376 OP_M (bytemode
, sizeflag
);
16379 /* Display the destination register operand for instructions with
16383 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16386 const char **names
;
16391 reg
= vex
.register_specifier
;
16392 vex
.register_specifier
= 0;
16393 if (address_mode
!= mode_64bit
)
16395 else if (vex
.evex
&& !vex
.v
)
16398 if (bytemode
== vex_scalar_mode
)
16400 oappend (names_xmm
[reg
]);
16404 if (bytemode
== tmm_mode
)
16406 /* All 3 TMM registers must be distinct. */
16411 /* This must be the 3rd operand. */
16412 if (obufp
!= op_out
[2])
16414 oappend (names_tmm
[reg
]);
16415 if (reg
== modrm
.reg
|| reg
== modrm
.rm
)
16416 strcpy (obufp
, "/(bad)");
16419 if (modrm
.reg
== modrm
.rm
|| modrm
.reg
== reg
|| modrm
.rm
== reg
)
16422 && (modrm
.reg
== modrm
.rm
|| modrm
.reg
== reg
))
16423 strcat (op_out
[0], "/(bad)");
16425 && (modrm
.rm
== modrm
.reg
|| modrm
.rm
== reg
))
16426 strcat (op_out
[1], "/(bad)");
16432 switch (vex
.length
)
16438 case vex_vsib_q_w_dq_mode
:
16439 case vex_vsib_q_w_d_mode
:
16455 names
= names_mask
;
16468 case vex_vsib_q_w_dq_mode
:
16469 case vex_vsib_q_w_d_mode
:
16470 names
= vex
.w
? names_ymm
: names_xmm
;
16479 names
= names_mask
;
16482 /* See PR binutils/20893 for a reproducer. */
16494 oappend (names
[reg
]);
16498 OP_VexR (int bytemode
, int sizeflag
)
16500 if (modrm
.mod
== 3)
16501 OP_VEX (bytemode
, sizeflag
);
16505 OP_VexW (int bytemode
, int sizeflag
)
16507 OP_VEX (bytemode
, sizeflag
);
16511 /* Swap 2nd and 3rd operands. */
16512 strcpy (scratchbuf
, op_out
[2]);
16513 strcpy (op_out
[2], op_out
[1]);
16514 strcpy (op_out
[1], scratchbuf
);
16519 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16522 const char **names
= names_xmm
;
16524 FETCH_DATA (the_info
, codep
+ 1);
16527 if (bytemode
!= x_mode
&& bytemode
!= scalar_mode
)
16531 if (address_mode
!= mode_64bit
)
16534 if (bytemode
== x_mode
&& vex
.length
== 256)
16537 oappend (names
[reg
]);
16541 /* Swap 3rd and 4th operands. */
16542 strcpy (scratchbuf
, op_out
[3]);
16543 strcpy (op_out
[3], op_out
[2]);
16544 strcpy (op_out
[2], scratchbuf
);
16549 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED
,
16550 int sizeflag ATTRIBUTE_UNUSED
)
16552 scratchbuf
[0] = '$';
16553 print_operand_value (scratchbuf
+ 1, 1, codep
[-1] & 0xf);
16554 oappend_maybe_intel (scratchbuf
);
16558 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16559 int sizeflag ATTRIBUTE_UNUSED
)
16561 unsigned int cmp_type
;
16566 FETCH_DATA (the_info
, codep
+ 1);
16567 cmp_type
= *codep
++ & 0xff;
16568 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16569 If it's the case, print suffix, otherwise - print the immediate. */
16570 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
16575 char *p
= mnemonicendp
- 2;
16577 /* vpcmp* can have both one- and two-lettered suffix. */
16591 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16592 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16596 /* We have a reserved extension byte. Output it directly. */
16597 scratchbuf
[0] = '$';
16598 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16599 oappend_maybe_intel (scratchbuf
);
16600 scratchbuf
[0] = '\0';
16604 static const struct op xop_cmp_op
[] =
16606 { STRING_COMMA_LEN ("lt") },
16607 { STRING_COMMA_LEN ("le") },
16608 { STRING_COMMA_LEN ("gt") },
16609 { STRING_COMMA_LEN ("ge") },
16610 { STRING_COMMA_LEN ("eq") },
16611 { STRING_COMMA_LEN ("neq") },
16612 { STRING_COMMA_LEN ("false") },
16613 { STRING_COMMA_LEN ("true") }
16617 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16618 int sizeflag ATTRIBUTE_UNUSED
)
16620 unsigned int cmp_type
;
16622 FETCH_DATA (the_info
, codep
+ 1);
16623 cmp_type
= *codep
++ & 0xff;
16624 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
16627 char *p
= mnemonicendp
- 2;
16629 /* vpcom* can have both one- and two-lettered suffix. */
16643 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
16644 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
16648 /* We have a reserved extension byte. Output it directly. */
16649 scratchbuf
[0] = '$';
16650 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16651 oappend_maybe_intel (scratchbuf
);
16652 scratchbuf
[0] = '\0';
16656 static const struct op pclmul_op
[] =
16658 { STRING_COMMA_LEN ("lql") },
16659 { STRING_COMMA_LEN ("hql") },
16660 { STRING_COMMA_LEN ("lqh") },
16661 { STRING_COMMA_LEN ("hqh") }
16665 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16666 int sizeflag ATTRIBUTE_UNUSED
)
16668 unsigned int pclmul_type
;
16670 FETCH_DATA (the_info
, codep
+ 1);
16671 pclmul_type
= *codep
++ & 0xff;
16672 switch (pclmul_type
)
16683 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
16686 char *p
= mnemonicendp
- 3;
16691 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
16692 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
16696 /* We have a reserved extension byte. Output it directly. */
16697 scratchbuf
[0] = '$';
16698 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
16699 oappend_maybe_intel (scratchbuf
);
16700 scratchbuf
[0] = '\0';
16705 MOVSXD_Fixup (int bytemode
, int sizeflag
)
16707 /* Add proper suffix to "movsxd". */
16708 char *p
= mnemonicendp
;
16733 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16740 OP_E (bytemode
, sizeflag
);
16744 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16747 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
16751 if ((rex
& REX_R
) != 0 || !vex
.r
)
16757 oappend (names_mask
[modrm
.reg
]);
16761 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16763 if (modrm
.mod
== 3 && vex
.b
)
16766 case evex_rounding_64_mode
:
16767 if (address_mode
!= mode_64bit
)
16772 /* Fall through. */
16773 case evex_rounding_mode
:
16774 oappend (names_rounding
[vex
.ll
]);
16776 case evex_sae_mode
: