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x86/Intel: adjust representation of embedded rounding / SAE
[thirdparty/binutils-gdb.git] / opcodes / i386-dis.c
1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2022 Free Software Foundation, Inc.
3
4 This file is part of the GNU opcodes library.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
23 July 1988
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
27
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
34
35 #include "sysdep.h"
36 #include "disassemble.h"
37 #include "opintl.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
41
42 #include <setjmp.h>
43 typedef struct instr_info instr_info;
44
45 static int print_insn (bfd_vma, instr_info *);
46 static void dofloat (instr_info *, int);
47 static void OP_ST (instr_info *, int, int);
48 static void OP_STi (instr_info *, int, int);
49 static int putop (instr_info *, const char *, int);
50 static void oappend (instr_info *, const char *);
51 static void append_seg (instr_info *);
52 static void OP_indirE (instr_info *, int, int);
53 static void print_operand_value (instr_info *, char *, int, bfd_vma);
54 static void OP_E_memory (instr_info *, int, int);
55 static void print_displacement (instr_info *, char *, bfd_vma);
56 static void OP_E (instr_info *, int, int);
57 static void OP_G (instr_info *, int, int);
58 static bfd_vma get64 (instr_info *);
59 static bfd_signed_vma get32 (instr_info *);
60 static bfd_signed_vma get32s (instr_info *);
61 static int get16 (instr_info *);
62 static void set_op (instr_info *, bfd_vma, bool);
63 static void OP_Skip_MODRM (instr_info *, int, int);
64 static void OP_REG (instr_info *, int, int);
65 static void OP_IMREG (instr_info *, int, int);
66 static void OP_I (instr_info *, int, int);
67 static void OP_I64 (instr_info *, int, int);
68 static void OP_sI (instr_info *, int, int);
69 static void OP_J (instr_info *, int, int);
70 static void OP_SEG (instr_info *, int, int);
71 static void OP_DIR (instr_info *, int, int);
72 static void OP_OFF (instr_info *, int, int);
73 static void OP_OFF64 (instr_info *, int, int);
74 static void ptr_reg (instr_info *, int, int);
75 static void OP_ESreg (instr_info *, int, int);
76 static void OP_DSreg (instr_info *, int, int);
77 static void OP_C (instr_info *, int, int);
78 static void OP_D (instr_info *, int, int);
79 static void OP_T (instr_info *, int, int);
80 static void OP_MMX (instr_info *, int, int);
81 static void OP_XMM (instr_info *, int, int);
82 static void OP_EM (instr_info *, int, int);
83 static void OP_EX (instr_info *, int, int);
84 static void OP_EMC (instr_info *, int,int);
85 static void OP_MXC (instr_info *, int,int);
86 static void OP_MS (instr_info *, int, int);
87 static void OP_XS (instr_info *, int, int);
88 static void OP_M (instr_info *, int, int);
89 static void OP_VEX (instr_info *, int, int);
90 static void OP_VexR (instr_info *, int, int);
91 static void OP_VexW (instr_info *, int, int);
92 static void OP_Rounding (instr_info *, int, int);
93 static void OP_REG_VexI4 (instr_info *, int, int);
94 static void OP_VexI4 (instr_info *, int, int);
95 static void PCLMUL_Fixup (instr_info *, int, int);
96 static void VPCMP_Fixup (instr_info *, int, int);
97 static void VPCOM_Fixup (instr_info *, int, int);
98 static void OP_0f07 (instr_info *, int, int);
99 static void OP_Monitor (instr_info *, int, int);
100 static void OP_Mwait (instr_info *, int, int);
101 static void NOP_Fixup (instr_info *, int, int);
102 static void OP_3DNowSuffix (instr_info *, int, int);
103 static void CMP_Fixup (instr_info *, int, int);
104 static void BadOp (instr_info *);
105 static void REP_Fixup (instr_info *, int, int);
106 static void SEP_Fixup (instr_info *, int, int);
107 static void BND_Fixup (instr_info *, int, int);
108 static void NOTRACK_Fixup (instr_info *, int, int);
109 static void HLE_Fixup1 (instr_info *, int, int);
110 static void HLE_Fixup2 (instr_info *, int, int);
111 static void HLE_Fixup3 (instr_info *, int, int);
112 static void CMPXCHG8B_Fixup (instr_info *, int, int);
113 static void XMM_Fixup (instr_info *, int, int);
114 static void FXSAVE_Fixup (instr_info *, int, int);
115
116 static void MOVSXD_Fixup (instr_info *, int, int);
117 static void DistinctDest_Fixup (instr_info *, int, int);
118
119 struct dis_private {
120 /* Points to first byte not fetched. */
121 bfd_byte *max_fetched;
122 bfd_byte the_buffer[MAX_MNEM_SIZE];
123 bfd_vma insn_start;
124 int orig_sizeflag;
125 OPCODES_SIGJMP_BUF bailout;
126 };
127
128 enum address_mode
129 {
130 mode_16bit,
131 mode_32bit,
132 mode_64bit
133 };
134
135 enum x86_64_isa
136 {
137 amd64 = 1,
138 intel64
139 };
140
141 struct instr_info
142 {
143 enum address_mode address_mode;
144
145 /* Flags for the prefixes for the current instruction. See below. */
146 int prefixes;
147
148 /* REX prefix the current instruction. See below. */
149 unsigned char rex;
150 /* Bits of REX we've already used. */
151 unsigned char rex_used;
152
153 bool need_modrm;
154 bool need_vex;
155 bool has_sib;
156
157 /* Flags for ins->prefixes which we somehow handled when printing the
158 current instruction. */
159 int used_prefixes;
160
161 /* Flags for EVEX bits which we somehow handled when printing the
162 current instruction. */
163 int evex_used;
164
165 char obuf[100];
166 char *obufp;
167 char *mnemonicendp;
168 char scratchbuf[100];
169 unsigned char *start_codep;
170 unsigned char *insn_codep;
171 unsigned char *codep;
172 unsigned char *end_codep;
173 int last_lock_prefix;
174 int last_repz_prefix;
175 int last_repnz_prefix;
176 int last_data_prefix;
177 int last_addr_prefix;
178 int last_rex_prefix;
179 int last_seg_prefix;
180 int fwait_prefix;
181 /* The active segment register prefix. */
182 int active_seg_prefix;
183
184 #define MAX_CODE_LENGTH 15
185 /* We can up to 14 ins->prefixes since the maximum instruction length is
186 15bytes. */
187 int all_prefixes[MAX_CODE_LENGTH - 1];
188 disassemble_info *info;
189
190 struct
191 {
192 int mod;
193 int reg;
194 int rm;
195 }
196 modrm;
197
198 struct
199 {
200 int scale;
201 int index;
202 int base;
203 }
204 sib;
205
206 struct
207 {
208 int register_specifier;
209 int length;
210 int prefix;
211 int mask_register_specifier;
212 int ll;
213 bool w;
214 bool evex;
215 bool r;
216 bool v;
217 bool zeroing;
218 bool b;
219 bool no_broadcast;
220 }
221 vex;
222
223 /* Remember if the current op is a jump instruction. */
224 bool op_is_jump;
225
226 bool two_source_ops;
227
228 unsigned char op_ad;
229 signed char op_index[MAX_OPERANDS];
230 bool op_riprel[MAX_OPERANDS];
231 char op_out[MAX_OPERANDS][100];
232 bfd_vma op_address[MAX_OPERANDS];
233 bfd_vma start_pc;
234
235 /* On the 386's of 1988, the maximum length of an instruction is 15 bytes.
236 * (see topic "Redundant ins->prefixes" in the "Differences from 8086"
237 * section of the "Virtual 8086 Mode" chapter.)
238 * 'pc' should be the address of this instruction, it will
239 * be used to print the target address if this is a relative jump or call
240 * The function returns the length of this instruction in bytes.
241 */
242 char intel_syntax;
243 bool intel_mnemonic;
244 char open_char;
245 char close_char;
246 char separator_char;
247 char scale_char;
248
249 enum x86_64_isa isa64;
250
251 };
252
253 /* Mark parts used in the REX prefix. When we are testing for
254 empty prefix (for 8bit register REX extension), just mask it
255 out. Otherwise test for REX bit is excuse for existence of REX
256 only in case value is nonzero. */
257 #define USED_REX(value) \
258 { \
259 if (value) \
260 { \
261 if ((ins->rex & value)) \
262 ins->rex_used |= (value) | REX_OPCODE; \
263 } \
264 else \
265 ins->rex_used |= REX_OPCODE; \
266 }
267
268
269 #define EVEX_b_used 1
270 #define EVEX_len_used 2
271
272 /* Flags stored in PREFIXES. */
273 #define PREFIX_REPZ 1
274 #define PREFIX_REPNZ 2
275 #define PREFIX_LOCK 4
276 #define PREFIX_CS 8
277 #define PREFIX_SS 0x10
278 #define PREFIX_DS 0x20
279 #define PREFIX_ES 0x40
280 #define PREFIX_FS 0x80
281 #define PREFIX_GS 0x100
282 #define PREFIX_DATA 0x200
283 #define PREFIX_ADDR 0x400
284 #define PREFIX_FWAIT 0x800
285
286 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
287 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
288 on error. */
289 #define FETCH_DATA(info, addr) \
290 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
291 ? 1 : fetch_data ((info), (addr)))
292
293 static int
294 fetch_data (struct disassemble_info *info, bfd_byte *addr)
295 {
296 int status;
297 struct dis_private *priv = (struct dis_private *) info->private_data;
298 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
299
300 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
301 status = (*info->read_memory_func) (start,
302 priv->max_fetched,
303 addr - priv->max_fetched,
304 info);
305 else
306 status = -1;
307 if (status != 0)
308 {
309 /* If we did manage to read at least one byte, then
310 print_insn_i386 will do something sensible. Otherwise, print
311 an error. We do that here because this is where we know
312 STATUS. */
313 if (priv->max_fetched == priv->the_buffer)
314 (*info->memory_error_func) (status, start, info);
315 OPCODES_SIGLONGJMP (priv->bailout, 1);
316 }
317 else
318 priv->max_fetched = addr;
319 return 1;
320 }
321
322 /* Possible values for prefix requirement. */
323 #define PREFIX_IGNORED_SHIFT 16
324 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
325 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
326 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
327 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
328 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
329
330 /* Opcode prefixes. */
331 #define PREFIX_OPCODE (PREFIX_REPZ \
332 | PREFIX_REPNZ \
333 | PREFIX_DATA)
334
335 /* Prefixes ignored. */
336 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
337 | PREFIX_IGNORED_REPNZ \
338 | PREFIX_IGNORED_DATA)
339
340 #define XX { NULL, 0 }
341 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
342
343 #define Eb { OP_E, b_mode }
344 #define Ebnd { OP_E, bnd_mode }
345 #define EbS { OP_E, b_swap_mode }
346 #define EbndS { OP_E, bnd_swap_mode }
347 #define Ev { OP_E, v_mode }
348 #define Eva { OP_E, va_mode }
349 #define Ev_bnd { OP_E, v_bnd_mode }
350 #define EvS { OP_E, v_swap_mode }
351 #define Ed { OP_E, d_mode }
352 #define Edq { OP_E, dq_mode }
353 #define Edb { OP_E, db_mode }
354 #define Edw { OP_E, dw_mode }
355 #define Eq { OP_E, q_mode }
356 #define indirEv { OP_indirE, indir_v_mode }
357 #define indirEp { OP_indirE, f_mode }
358 #define stackEv { OP_E, stack_v_mode }
359 #define Em { OP_E, m_mode }
360 #define Ew { OP_E, w_mode }
361 #define M { OP_M, 0 } /* lea, lgdt, etc. */
362 #define Ma { OP_M, a_mode }
363 #define Mb { OP_M, b_mode }
364 #define Md { OP_M, d_mode }
365 #define Mo { OP_M, o_mode }
366 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
367 #define Mq { OP_M, q_mode }
368 #define Mv { OP_M, v_mode }
369 #define Mv_bnd { OP_M, v_bndmk_mode }
370 #define Mx { OP_M, x_mode }
371 #define Mxmm { OP_M, xmm_mode }
372 #define Gb { OP_G, b_mode }
373 #define Gbnd { OP_G, bnd_mode }
374 #define Gv { OP_G, v_mode }
375 #define Gd { OP_G, d_mode }
376 #define Gdq { OP_G, dq_mode }
377 #define Gm { OP_G, m_mode }
378 #define Gva { OP_G, va_mode }
379 #define Gw { OP_G, w_mode }
380 #define Ib { OP_I, b_mode }
381 #define sIb { OP_sI, b_mode } /* sign extened byte */
382 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
383 #define Iv { OP_I, v_mode }
384 #define sIv { OP_sI, v_mode }
385 #define Iv64 { OP_I64, v_mode }
386 #define Id { OP_I, d_mode }
387 #define Iw { OP_I, w_mode }
388 #define I1 { OP_I, const_1_mode }
389 #define Jb { OP_J, b_mode }
390 #define Jv { OP_J, v_mode }
391 #define Jdqw { OP_J, dqw_mode }
392 #define Cm { OP_C, m_mode }
393 #define Dm { OP_D, m_mode }
394 #define Td { OP_T, d_mode }
395 #define Skip_MODRM { OP_Skip_MODRM, 0 }
396
397 #define RMeAX { OP_REG, eAX_reg }
398 #define RMeBX { OP_REG, eBX_reg }
399 #define RMeCX { OP_REG, eCX_reg }
400 #define RMeDX { OP_REG, eDX_reg }
401 #define RMeSP { OP_REG, eSP_reg }
402 #define RMeBP { OP_REG, eBP_reg }
403 #define RMeSI { OP_REG, eSI_reg }
404 #define RMeDI { OP_REG, eDI_reg }
405 #define RMrAX { OP_REG, rAX_reg }
406 #define RMrBX { OP_REG, rBX_reg }
407 #define RMrCX { OP_REG, rCX_reg }
408 #define RMrDX { OP_REG, rDX_reg }
409 #define RMrSP { OP_REG, rSP_reg }
410 #define RMrBP { OP_REG, rBP_reg }
411 #define RMrSI { OP_REG, rSI_reg }
412 #define RMrDI { OP_REG, rDI_reg }
413 #define RMAL { OP_REG, al_reg }
414 #define RMCL { OP_REG, cl_reg }
415 #define RMDL { OP_REG, dl_reg }
416 #define RMBL { OP_REG, bl_reg }
417 #define RMAH { OP_REG, ah_reg }
418 #define RMCH { OP_REG, ch_reg }
419 #define RMDH { OP_REG, dh_reg }
420 #define RMBH { OP_REG, bh_reg }
421 #define RMAX { OP_REG, ax_reg }
422 #define RMDX { OP_REG, dx_reg }
423
424 #define eAX { OP_IMREG, eAX_reg }
425 #define AL { OP_IMREG, al_reg }
426 #define CL { OP_IMREG, cl_reg }
427 #define zAX { OP_IMREG, z_mode_ax_reg }
428 #define indirDX { OP_IMREG, indir_dx_reg }
429
430 #define Sw { OP_SEG, w_mode }
431 #define Sv { OP_SEG, v_mode }
432 #define Ap { OP_DIR, 0 }
433 #define Ob { OP_OFF64, b_mode }
434 #define Ov { OP_OFF64, v_mode }
435 #define Xb { OP_DSreg, eSI_reg }
436 #define Xv { OP_DSreg, eSI_reg }
437 #define Xz { OP_DSreg, eSI_reg }
438 #define Yb { OP_ESreg, eDI_reg }
439 #define Yv { OP_ESreg, eDI_reg }
440 #define DSBX { OP_DSreg, eBX_reg }
441
442 #define es { OP_REG, es_reg }
443 #define ss { OP_REG, ss_reg }
444 #define cs { OP_REG, cs_reg }
445 #define ds { OP_REG, ds_reg }
446 #define fs { OP_REG, fs_reg }
447 #define gs { OP_REG, gs_reg }
448
449 #define MX { OP_MMX, 0 }
450 #define XM { OP_XMM, 0 }
451 #define XMScalar { OP_XMM, scalar_mode }
452 #define XMGatherD { OP_XMM, vex_vsib_d_w_dq_mode }
453 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
454 #define XMM { OP_XMM, xmm_mode }
455 #define TMM { OP_XMM, tmm_mode }
456 #define XMxmmq { OP_XMM, xmmq_mode }
457 #define EM { OP_EM, v_mode }
458 #define EMS { OP_EM, v_swap_mode }
459 #define EMd { OP_EM, d_mode }
460 #define EMx { OP_EM, x_mode }
461 #define EXbwUnit { OP_EX, bw_unit_mode }
462 #define EXb { OP_EX, b_mode }
463 #define EXw { OP_EX, w_mode }
464 #define EXd { OP_EX, d_mode }
465 #define EXdS { OP_EX, d_swap_mode }
466 #define EXwS { OP_EX, w_swap_mode }
467 #define EXq { OP_EX, q_mode }
468 #define EXqS { OP_EX, q_swap_mode }
469 #define EXdq { OP_EX, dq_mode }
470 #define EXx { OP_EX, x_mode }
471 #define EXxh { OP_EX, xh_mode }
472 #define EXxS { OP_EX, x_swap_mode }
473 #define EXxmm { OP_EX, xmm_mode }
474 #define EXymm { OP_EX, ymm_mode }
475 #define EXtmm { OP_EX, tmm_mode }
476 #define EXxmmq { OP_EX, xmmq_mode }
477 #define EXxmmqh { OP_EX, evex_half_bcst_xmmqh_mode }
478 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
479 #define EXxmmdw { OP_EX, xmmdw_mode }
480 #define EXxmmqd { OP_EX, xmmqd_mode }
481 #define EXxmmqdh { OP_EX, evex_half_bcst_xmmqdh_mode }
482 #define EXymmq { OP_EX, ymmq_mode }
483 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
484 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
485 #define MS { OP_MS, v_mode }
486 #define XS { OP_XS, v_mode }
487 #define EMCq { OP_EMC, q_mode }
488 #define MXC { OP_MXC, 0 }
489 #define OPSUF { OP_3DNowSuffix, 0 }
490 #define SEP { SEP_Fixup, 0 }
491 #define CMP { CMP_Fixup, 0 }
492 #define XMM0 { XMM_Fixup, 0 }
493 #define FXSAVE { FXSAVE_Fixup, 0 }
494
495 #define Vex { OP_VEX, x_mode }
496 #define VexW { OP_VexW, x_mode }
497 #define VexScalar { OP_VEX, scalar_mode }
498 #define VexScalarR { OP_VexR, scalar_mode }
499 #define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode }
500 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
501 #define VexGdq { OP_VEX, dq_mode }
502 #define VexTmm { OP_VEX, tmm_mode }
503 #define XMVexI4 { OP_REG_VexI4, x_mode }
504 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
505 #define VexI4 { OP_VexI4, 0 }
506 #define PCLMUL { PCLMUL_Fixup, 0 }
507 #define VPCMP { VPCMP_Fixup, 0 }
508 #define VPCOM { VPCOM_Fixup, 0 }
509
510 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
511 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
512 #define EXxEVexS { OP_Rounding, evex_sae_mode }
513
514 #define MaskG { OP_G, mask_mode }
515 #define MaskE { OP_E, mask_mode }
516 #define MaskBDE { OP_E, mask_bd_mode }
517 #define MaskVex { OP_VEX, mask_mode }
518
519 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
520 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
521
522 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
523
524 /* Used handle "rep" prefix for string instructions. */
525 #define Xbr { REP_Fixup, eSI_reg }
526 #define Xvr { REP_Fixup, eSI_reg }
527 #define Ybr { REP_Fixup, eDI_reg }
528 #define Yvr { REP_Fixup, eDI_reg }
529 #define Yzr { REP_Fixup, eDI_reg }
530 #define indirDXr { REP_Fixup, indir_dx_reg }
531 #define ALr { REP_Fixup, al_reg }
532 #define eAXr { REP_Fixup, eAX_reg }
533
534 /* Used handle HLE prefix for lockable instructions. */
535 #define Ebh1 { HLE_Fixup1, b_mode }
536 #define Evh1 { HLE_Fixup1, v_mode }
537 #define Ebh2 { HLE_Fixup2, b_mode }
538 #define Evh2 { HLE_Fixup2, v_mode }
539 #define Ebh3 { HLE_Fixup3, b_mode }
540 #define Evh3 { HLE_Fixup3, v_mode }
541
542 #define BND { BND_Fixup, 0 }
543 #define NOTRACK { NOTRACK_Fixup, 0 }
544
545 #define cond_jump_flag { NULL, cond_jump_mode }
546 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
547
548 /* bits in sizeflag */
549 #define SUFFIX_ALWAYS 4
550 #define AFLAG 2
551 #define DFLAG 1
552
553 enum
554 {
555 /* byte operand */
556 b_mode = 1,
557 /* byte operand with operand swapped */
558 b_swap_mode,
559 /* byte operand, sign extend like 'T' suffix */
560 b_T_mode,
561 /* operand size depends on prefixes */
562 v_mode,
563 /* operand size depends on prefixes with operand swapped */
564 v_swap_mode,
565 /* operand size depends on address prefix */
566 va_mode,
567 /* word operand */
568 w_mode,
569 /* double word operand */
570 d_mode,
571 /* word operand with operand swapped */
572 w_swap_mode,
573 /* double word operand with operand swapped */
574 d_swap_mode,
575 /* quad word operand */
576 q_mode,
577 /* quad word operand with operand swapped */
578 q_swap_mode,
579 /* ten-byte operand */
580 t_mode,
581 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
582 broadcast enabled. */
583 x_mode,
584 /* Similar to x_mode, but with different EVEX mem shifts. */
585 evex_x_gscat_mode,
586 /* Similar to x_mode, but with yet different EVEX mem shifts. */
587 bw_unit_mode,
588 /* Similar to x_mode, but with disabled broadcast. */
589 evex_x_nobcst_mode,
590 /* Similar to x_mode, but with operands swapped and disabled broadcast
591 in EVEX. */
592 x_swap_mode,
593 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
594 broadcast of 16bit enabled. */
595 xh_mode,
596 /* 16-byte XMM operand */
597 xmm_mode,
598 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
599 memory operand (depending on vector length). Broadcast isn't
600 allowed. */
601 xmmq_mode,
602 /* Same as xmmq_mode, but broadcast is allowed. */
603 evex_half_bcst_xmmq_mode,
604 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
605 memory operand (depending on vector length). 16bit broadcast. */
606 evex_half_bcst_xmmqh_mode,
607 /* 16-byte XMM, word, double word or quad word operand. */
608 xmmdw_mode,
609 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
610 xmmqd_mode,
611 /* 16-byte XMM, double word, quad word operand or xmm word operand.
612 16bit broadcast. */
613 evex_half_bcst_xmmqdh_mode,
614 /* 32-byte YMM operand */
615 ymm_mode,
616 /* quad word, ymmword or zmmword memory operand. */
617 ymmq_mode,
618 /* TMM operand */
619 tmm_mode,
620 /* d_mode in 32bit, q_mode in 64bit mode. */
621 m_mode,
622 /* pair of v_mode operands */
623 a_mode,
624 cond_jump_mode,
625 loop_jcxz_mode,
626 movsxd_mode,
627 v_bnd_mode,
628 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
629 v_bndmk_mode,
630 /* operand size depends on REX.W / VEX.W. */
631 dq_mode,
632 /* Displacements like v_mode without considering Intel64 ISA. */
633 dqw_mode,
634 /* bounds operand */
635 bnd_mode,
636 /* bounds operand with operand swapped */
637 bnd_swap_mode,
638 /* 4- or 6-byte pointer operand */
639 f_mode,
640 const_1_mode,
641 /* v_mode for indirect branch opcodes. */
642 indir_v_mode,
643 /* v_mode for stack-related opcodes. */
644 stack_v_mode,
645 /* non-quad operand size depends on prefixes */
646 z_mode,
647 /* 16-byte operand */
648 o_mode,
649 /* registers like d_mode, memory like b_mode. */
650 db_mode,
651 /* registers like d_mode, memory like w_mode. */
652 dw_mode,
653
654 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
655 vex_vsib_d_w_dq_mode,
656 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
657 vex_vsib_q_w_dq_mode,
658 /* mandatory non-vector SIB. */
659 vex_sibmem_mode,
660
661 /* scalar, ignore vector length. */
662 scalar_mode,
663
664 /* Static rounding. */
665 evex_rounding_mode,
666 /* Static rounding, 64-bit mode only. */
667 evex_rounding_64_mode,
668 /* Supress all exceptions. */
669 evex_sae_mode,
670
671 /* Mask register operand. */
672 mask_mode,
673 /* Mask register operand. */
674 mask_bd_mode,
675
676 es_reg,
677 cs_reg,
678 ss_reg,
679 ds_reg,
680 fs_reg,
681 gs_reg,
682
683 eAX_reg,
684 eCX_reg,
685 eDX_reg,
686 eBX_reg,
687 eSP_reg,
688 eBP_reg,
689 eSI_reg,
690 eDI_reg,
691
692 al_reg,
693 cl_reg,
694 dl_reg,
695 bl_reg,
696 ah_reg,
697 ch_reg,
698 dh_reg,
699 bh_reg,
700
701 ax_reg,
702 cx_reg,
703 dx_reg,
704 bx_reg,
705 sp_reg,
706 bp_reg,
707 si_reg,
708 di_reg,
709
710 rAX_reg,
711 rCX_reg,
712 rDX_reg,
713 rBX_reg,
714 rSP_reg,
715 rBP_reg,
716 rSI_reg,
717 rDI_reg,
718
719 z_mode_ax_reg,
720 indir_dx_reg
721 };
722
723 enum
724 {
725 FLOATCODE = 1,
726 USE_REG_TABLE,
727 USE_MOD_TABLE,
728 USE_RM_TABLE,
729 USE_PREFIX_TABLE,
730 USE_X86_64_TABLE,
731 USE_3BYTE_TABLE,
732 USE_XOP_8F_TABLE,
733 USE_VEX_C4_TABLE,
734 USE_VEX_C5_TABLE,
735 USE_VEX_LEN_TABLE,
736 USE_VEX_W_TABLE,
737 USE_EVEX_TABLE,
738 USE_EVEX_LEN_TABLE
739 };
740
741 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
742
743 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
744 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
745 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
746 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
747 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
748 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
749 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
750 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
751 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
752 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
753 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
754 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
755 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
756 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
757 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
758 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
759
760 enum
761 {
762 REG_80 = 0,
763 REG_81,
764 REG_83,
765 REG_8F,
766 REG_C0,
767 REG_C1,
768 REG_C6,
769 REG_C7,
770 REG_D0,
771 REG_D1,
772 REG_D2,
773 REG_D3,
774 REG_F6,
775 REG_F7,
776 REG_FE,
777 REG_FF,
778 REG_0F00,
779 REG_0F01,
780 REG_0F0D,
781 REG_0F18,
782 REG_0F1C_P_0_MOD_0,
783 REG_0F1E_P_1_MOD_3,
784 REG_0F38D8_PREFIX_1,
785 REG_0F3A0F_PREFIX_1_MOD_3,
786 REG_0F71_MOD_0,
787 REG_0F72_MOD_0,
788 REG_0F73_MOD_0,
789 REG_0FA6,
790 REG_0FA7,
791 REG_0FAE,
792 REG_0FBA,
793 REG_0FC7,
794 REG_VEX_0F71_M_0,
795 REG_VEX_0F72_M_0,
796 REG_VEX_0F73_M_0,
797 REG_VEX_0FAE,
798 REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
799 REG_VEX_0F38F3_L_0,
800
801 REG_XOP_09_01_L_0,
802 REG_XOP_09_02_L_0,
803 REG_XOP_09_12_M_1_L_0,
804 REG_XOP_0A_12_L_0,
805
806 REG_EVEX_0F71,
807 REG_EVEX_0F72,
808 REG_EVEX_0F73,
809 REG_EVEX_0F38C6_M_0_L_2,
810 REG_EVEX_0F38C7_M_0_L_2
811 };
812
813 enum
814 {
815 MOD_62_32BIT = 0,
816 MOD_8D,
817 MOD_C4_32BIT,
818 MOD_C5_32BIT,
819 MOD_C6_REG_7,
820 MOD_C7_REG_7,
821 MOD_FF_REG_3,
822 MOD_FF_REG_5,
823 MOD_0F01_REG_0,
824 MOD_0F01_REG_1,
825 MOD_0F01_REG_2,
826 MOD_0F01_REG_3,
827 MOD_0F01_REG_5,
828 MOD_0F01_REG_7,
829 MOD_0F12_PREFIX_0,
830 MOD_0F12_PREFIX_2,
831 MOD_0F13,
832 MOD_0F16_PREFIX_0,
833 MOD_0F16_PREFIX_2,
834 MOD_0F17,
835 MOD_0F18_REG_0,
836 MOD_0F18_REG_1,
837 MOD_0F18_REG_2,
838 MOD_0F18_REG_3,
839 MOD_0F1A_PREFIX_0,
840 MOD_0F1B_PREFIX_0,
841 MOD_0F1B_PREFIX_1,
842 MOD_0F1C_PREFIX_0,
843 MOD_0F1E_PREFIX_1,
844 MOD_0F2B_PREFIX_0,
845 MOD_0F2B_PREFIX_1,
846 MOD_0F2B_PREFIX_2,
847 MOD_0F2B_PREFIX_3,
848 MOD_0F50,
849 MOD_0F71,
850 MOD_0F72,
851 MOD_0F73,
852 MOD_0FAE_REG_0,
853 MOD_0FAE_REG_1,
854 MOD_0FAE_REG_2,
855 MOD_0FAE_REG_3,
856 MOD_0FAE_REG_4,
857 MOD_0FAE_REG_5,
858 MOD_0FAE_REG_6,
859 MOD_0FAE_REG_7,
860 MOD_0FB2,
861 MOD_0FB4,
862 MOD_0FB5,
863 MOD_0FC3,
864 MOD_0FC7_REG_3,
865 MOD_0FC7_REG_4,
866 MOD_0FC7_REG_5,
867 MOD_0FC7_REG_6,
868 MOD_0FC7_REG_7,
869 MOD_0FD7,
870 MOD_0FE7_PREFIX_2,
871 MOD_0FF0_PREFIX_3,
872 MOD_0F382A,
873 MOD_0F38DC_PREFIX_1,
874 MOD_0F38DD_PREFIX_1,
875 MOD_0F38DE_PREFIX_1,
876 MOD_0F38DF_PREFIX_1,
877 MOD_0F38F5,
878 MOD_0F38F6_PREFIX_0,
879 MOD_0F38F8_PREFIX_1,
880 MOD_0F38F8_PREFIX_2,
881 MOD_0F38F8_PREFIX_3,
882 MOD_0F38F9,
883 MOD_0F38FA_PREFIX_1,
884 MOD_0F38FB_PREFIX_1,
885 MOD_0F3A0F_PREFIX_1,
886
887 MOD_VEX_0F12_PREFIX_0,
888 MOD_VEX_0F12_PREFIX_2,
889 MOD_VEX_0F13,
890 MOD_VEX_0F16_PREFIX_0,
891 MOD_VEX_0F16_PREFIX_2,
892 MOD_VEX_0F17,
893 MOD_VEX_0F2B,
894 MOD_VEX_0F41_L_1,
895 MOD_VEX_0F42_L_1,
896 MOD_VEX_0F44_L_0,
897 MOD_VEX_0F45_L_1,
898 MOD_VEX_0F46_L_1,
899 MOD_VEX_0F47_L_1,
900 MOD_VEX_0F4A_L_1,
901 MOD_VEX_0F4B_L_1,
902 MOD_VEX_0F50,
903 MOD_VEX_0F71,
904 MOD_VEX_0F72,
905 MOD_VEX_0F73,
906 MOD_VEX_0F91_L_0,
907 MOD_VEX_0F92_L_0,
908 MOD_VEX_0F93_L_0,
909 MOD_VEX_0F98_L_0,
910 MOD_VEX_0F99_L_0,
911 MOD_VEX_0FAE_REG_2,
912 MOD_VEX_0FAE_REG_3,
913 MOD_VEX_0FD7,
914 MOD_VEX_0FE7,
915 MOD_VEX_0FF0_PREFIX_3,
916 MOD_VEX_0F381A,
917 MOD_VEX_0F382A,
918 MOD_VEX_0F382C,
919 MOD_VEX_0F382D,
920 MOD_VEX_0F382E,
921 MOD_VEX_0F382F,
922 MOD_VEX_0F3849_X86_64_P_0_W_0,
923 MOD_VEX_0F3849_X86_64_P_2_W_0,
924 MOD_VEX_0F3849_X86_64_P_3_W_0,
925 MOD_VEX_0F384B_X86_64_P_1_W_0,
926 MOD_VEX_0F384B_X86_64_P_2_W_0,
927 MOD_VEX_0F384B_X86_64_P_3_W_0,
928 MOD_VEX_0F385A,
929 MOD_VEX_0F385C_X86_64_P_1_W_0,
930 MOD_VEX_0F385E_X86_64_P_0_W_0,
931 MOD_VEX_0F385E_X86_64_P_1_W_0,
932 MOD_VEX_0F385E_X86_64_P_2_W_0,
933 MOD_VEX_0F385E_X86_64_P_3_W_0,
934 MOD_VEX_0F388C,
935 MOD_VEX_0F388E,
936 MOD_VEX_0F3A30_L_0,
937 MOD_VEX_0F3A31_L_0,
938 MOD_VEX_0F3A32_L_0,
939 MOD_VEX_0F3A33_L_0,
940
941 MOD_XOP_09_12,
942
943 MOD_EVEX_0F381A,
944 MOD_EVEX_0F381B,
945 MOD_EVEX_0F3828_P_1,
946 MOD_EVEX_0F382A_P_1_W_1,
947 MOD_EVEX_0F3838_P_1,
948 MOD_EVEX_0F383A_P_1_W_0,
949 MOD_EVEX_0F385A,
950 MOD_EVEX_0F385B,
951 MOD_EVEX_0F387A_W_0,
952 MOD_EVEX_0F387B_W_0,
953 MOD_EVEX_0F387C,
954 MOD_EVEX_0F38C6,
955 MOD_EVEX_0F38C7,
956 };
957
958 enum
959 {
960 RM_C6_REG_7 = 0,
961 RM_C7_REG_7,
962 RM_0F01_REG_0,
963 RM_0F01_REG_1,
964 RM_0F01_REG_2,
965 RM_0F01_REG_3,
966 RM_0F01_REG_5_MOD_3,
967 RM_0F01_REG_7_MOD_3,
968 RM_0F1E_P_1_MOD_3_REG_7,
969 RM_0FAE_REG_6_MOD_3_P_0,
970 RM_0FAE_REG_7_MOD_3,
971 RM_0F3A0F_P_1_MOD_3_REG_0,
972
973 RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
974 };
975
976 enum
977 {
978 PREFIX_90 = 0,
979 PREFIX_0F01_REG_1_RM_4,
980 PREFIX_0F01_REG_1_RM_5,
981 PREFIX_0F01_REG_1_RM_6,
982 PREFIX_0F01_REG_1_RM_7,
983 PREFIX_0F01_REG_3_RM_1,
984 PREFIX_0F01_REG_5_MOD_0,
985 PREFIX_0F01_REG_5_MOD_3_RM_0,
986 PREFIX_0F01_REG_5_MOD_3_RM_1,
987 PREFIX_0F01_REG_5_MOD_3_RM_2,
988 PREFIX_0F01_REG_5_MOD_3_RM_4,
989 PREFIX_0F01_REG_5_MOD_3_RM_5,
990 PREFIX_0F01_REG_5_MOD_3_RM_6,
991 PREFIX_0F01_REG_5_MOD_3_RM_7,
992 PREFIX_0F01_REG_7_MOD_3_RM_2,
993 PREFIX_0F01_REG_7_MOD_3_RM_6,
994 PREFIX_0F01_REG_7_MOD_3_RM_7,
995 PREFIX_0F09,
996 PREFIX_0F10,
997 PREFIX_0F11,
998 PREFIX_0F12,
999 PREFIX_0F16,
1000 PREFIX_0F1A,
1001 PREFIX_0F1B,
1002 PREFIX_0F1C,
1003 PREFIX_0F1E,
1004 PREFIX_0F2A,
1005 PREFIX_0F2B,
1006 PREFIX_0F2C,
1007 PREFIX_0F2D,
1008 PREFIX_0F2E,
1009 PREFIX_0F2F,
1010 PREFIX_0F51,
1011 PREFIX_0F52,
1012 PREFIX_0F53,
1013 PREFIX_0F58,
1014 PREFIX_0F59,
1015 PREFIX_0F5A,
1016 PREFIX_0F5B,
1017 PREFIX_0F5C,
1018 PREFIX_0F5D,
1019 PREFIX_0F5E,
1020 PREFIX_0F5F,
1021 PREFIX_0F60,
1022 PREFIX_0F61,
1023 PREFIX_0F62,
1024 PREFIX_0F6F,
1025 PREFIX_0F70,
1026 PREFIX_0F78,
1027 PREFIX_0F79,
1028 PREFIX_0F7C,
1029 PREFIX_0F7D,
1030 PREFIX_0F7E,
1031 PREFIX_0F7F,
1032 PREFIX_0FAE_REG_0_MOD_3,
1033 PREFIX_0FAE_REG_1_MOD_3,
1034 PREFIX_0FAE_REG_2_MOD_3,
1035 PREFIX_0FAE_REG_3_MOD_3,
1036 PREFIX_0FAE_REG_4_MOD_0,
1037 PREFIX_0FAE_REG_4_MOD_3,
1038 PREFIX_0FAE_REG_5_MOD_3,
1039 PREFIX_0FAE_REG_6_MOD_0,
1040 PREFIX_0FAE_REG_6_MOD_3,
1041 PREFIX_0FAE_REG_7_MOD_0,
1042 PREFIX_0FB8,
1043 PREFIX_0FBC,
1044 PREFIX_0FBD,
1045 PREFIX_0FC2,
1046 PREFIX_0FC7_REG_6_MOD_0,
1047 PREFIX_0FC7_REG_6_MOD_3,
1048 PREFIX_0FC7_REG_7_MOD_3,
1049 PREFIX_0FD0,
1050 PREFIX_0FD6,
1051 PREFIX_0FE6,
1052 PREFIX_0FE7,
1053 PREFIX_0FF0,
1054 PREFIX_0FF7,
1055 PREFIX_0F38D8,
1056 PREFIX_0F38DC,
1057 PREFIX_0F38DD,
1058 PREFIX_0F38DE,
1059 PREFIX_0F38DF,
1060 PREFIX_0F38F0,
1061 PREFIX_0F38F1,
1062 PREFIX_0F38F6,
1063 PREFIX_0F38F8,
1064 PREFIX_0F38FA,
1065 PREFIX_0F38FB,
1066 PREFIX_0F3A0F,
1067 PREFIX_VEX_0F10,
1068 PREFIX_VEX_0F11,
1069 PREFIX_VEX_0F12,
1070 PREFIX_VEX_0F16,
1071 PREFIX_VEX_0F2A,
1072 PREFIX_VEX_0F2C,
1073 PREFIX_VEX_0F2D,
1074 PREFIX_VEX_0F2E,
1075 PREFIX_VEX_0F2F,
1076 PREFIX_VEX_0F41_L_1_M_1_W_0,
1077 PREFIX_VEX_0F41_L_1_M_1_W_1,
1078 PREFIX_VEX_0F42_L_1_M_1_W_0,
1079 PREFIX_VEX_0F42_L_1_M_1_W_1,
1080 PREFIX_VEX_0F44_L_0_M_1_W_0,
1081 PREFIX_VEX_0F44_L_0_M_1_W_1,
1082 PREFIX_VEX_0F45_L_1_M_1_W_0,
1083 PREFIX_VEX_0F45_L_1_M_1_W_1,
1084 PREFIX_VEX_0F46_L_1_M_1_W_0,
1085 PREFIX_VEX_0F46_L_1_M_1_W_1,
1086 PREFIX_VEX_0F47_L_1_M_1_W_0,
1087 PREFIX_VEX_0F47_L_1_M_1_W_1,
1088 PREFIX_VEX_0F4A_L_1_M_1_W_0,
1089 PREFIX_VEX_0F4A_L_1_M_1_W_1,
1090 PREFIX_VEX_0F4B_L_1_M_1_W_0,
1091 PREFIX_VEX_0F4B_L_1_M_1_W_1,
1092 PREFIX_VEX_0F51,
1093 PREFIX_VEX_0F52,
1094 PREFIX_VEX_0F53,
1095 PREFIX_VEX_0F58,
1096 PREFIX_VEX_0F59,
1097 PREFIX_VEX_0F5A,
1098 PREFIX_VEX_0F5B,
1099 PREFIX_VEX_0F5C,
1100 PREFIX_VEX_0F5D,
1101 PREFIX_VEX_0F5E,
1102 PREFIX_VEX_0F5F,
1103 PREFIX_VEX_0F6F,
1104 PREFIX_VEX_0F70,
1105 PREFIX_VEX_0F7C,
1106 PREFIX_VEX_0F7D,
1107 PREFIX_VEX_0F7E,
1108 PREFIX_VEX_0F7F,
1109 PREFIX_VEX_0F90_L_0_W_0,
1110 PREFIX_VEX_0F90_L_0_W_1,
1111 PREFIX_VEX_0F91_L_0_M_0_W_0,
1112 PREFIX_VEX_0F91_L_0_M_0_W_1,
1113 PREFIX_VEX_0F92_L_0_M_1_W_0,
1114 PREFIX_VEX_0F92_L_0_M_1_W_1,
1115 PREFIX_VEX_0F93_L_0_M_1_W_0,
1116 PREFIX_VEX_0F93_L_0_M_1_W_1,
1117 PREFIX_VEX_0F98_L_0_M_1_W_0,
1118 PREFIX_VEX_0F98_L_0_M_1_W_1,
1119 PREFIX_VEX_0F99_L_0_M_1_W_0,
1120 PREFIX_VEX_0F99_L_0_M_1_W_1,
1121 PREFIX_VEX_0FC2,
1122 PREFIX_VEX_0FD0,
1123 PREFIX_VEX_0FE6,
1124 PREFIX_VEX_0FF0,
1125 PREFIX_VEX_0F3849_X86_64,
1126 PREFIX_VEX_0F384B_X86_64,
1127 PREFIX_VEX_0F385C_X86_64,
1128 PREFIX_VEX_0F385E_X86_64,
1129 PREFIX_VEX_0F38F5_L_0,
1130 PREFIX_VEX_0F38F6_L_0,
1131 PREFIX_VEX_0F38F7_L_0,
1132 PREFIX_VEX_0F3AF0_L_0,
1133
1134 PREFIX_EVEX_0F5B,
1135 PREFIX_EVEX_0F6F,
1136 PREFIX_EVEX_0F70,
1137 PREFIX_EVEX_0F78,
1138 PREFIX_EVEX_0F79,
1139 PREFIX_EVEX_0F7A,
1140 PREFIX_EVEX_0F7B,
1141 PREFIX_EVEX_0F7E,
1142 PREFIX_EVEX_0F7F,
1143 PREFIX_EVEX_0FC2,
1144 PREFIX_EVEX_0FE6,
1145 PREFIX_EVEX_0F3810,
1146 PREFIX_EVEX_0F3811,
1147 PREFIX_EVEX_0F3812,
1148 PREFIX_EVEX_0F3813,
1149 PREFIX_EVEX_0F3814,
1150 PREFIX_EVEX_0F3815,
1151 PREFIX_EVEX_0F3820,
1152 PREFIX_EVEX_0F3821,
1153 PREFIX_EVEX_0F3822,
1154 PREFIX_EVEX_0F3823,
1155 PREFIX_EVEX_0F3824,
1156 PREFIX_EVEX_0F3825,
1157 PREFIX_EVEX_0F3826,
1158 PREFIX_EVEX_0F3827,
1159 PREFIX_EVEX_0F3828,
1160 PREFIX_EVEX_0F3829,
1161 PREFIX_EVEX_0F382A,
1162 PREFIX_EVEX_0F3830,
1163 PREFIX_EVEX_0F3831,
1164 PREFIX_EVEX_0F3832,
1165 PREFIX_EVEX_0F3833,
1166 PREFIX_EVEX_0F3834,
1167 PREFIX_EVEX_0F3835,
1168 PREFIX_EVEX_0F3838,
1169 PREFIX_EVEX_0F3839,
1170 PREFIX_EVEX_0F383A,
1171 PREFIX_EVEX_0F3852,
1172 PREFIX_EVEX_0F3853,
1173 PREFIX_EVEX_0F3868,
1174 PREFIX_EVEX_0F3872,
1175 PREFIX_EVEX_0F389A,
1176 PREFIX_EVEX_0F389B,
1177 PREFIX_EVEX_0F38AA,
1178 PREFIX_EVEX_0F38AB,
1179
1180 PREFIX_EVEX_0F3A08,
1181 PREFIX_EVEX_0F3A0A,
1182 PREFIX_EVEX_0F3A26,
1183 PREFIX_EVEX_0F3A27,
1184 PREFIX_EVEX_0F3A56,
1185 PREFIX_EVEX_0F3A57,
1186 PREFIX_EVEX_0F3A66,
1187 PREFIX_EVEX_0F3A67,
1188 PREFIX_EVEX_0F3AC2,
1189
1190 PREFIX_EVEX_MAP5_10,
1191 PREFIX_EVEX_MAP5_11,
1192 PREFIX_EVEX_MAP5_1D,
1193 PREFIX_EVEX_MAP5_2A,
1194 PREFIX_EVEX_MAP5_2C,
1195 PREFIX_EVEX_MAP5_2D,
1196 PREFIX_EVEX_MAP5_2E,
1197 PREFIX_EVEX_MAP5_2F,
1198 PREFIX_EVEX_MAP5_51,
1199 PREFIX_EVEX_MAP5_58,
1200 PREFIX_EVEX_MAP5_59,
1201 PREFIX_EVEX_MAP5_5A,
1202 PREFIX_EVEX_MAP5_5B,
1203 PREFIX_EVEX_MAP5_5C,
1204 PREFIX_EVEX_MAP5_5D,
1205 PREFIX_EVEX_MAP5_5E,
1206 PREFIX_EVEX_MAP5_5F,
1207 PREFIX_EVEX_MAP5_78,
1208 PREFIX_EVEX_MAP5_79,
1209 PREFIX_EVEX_MAP5_7A,
1210 PREFIX_EVEX_MAP5_7B,
1211 PREFIX_EVEX_MAP5_7C,
1212 PREFIX_EVEX_MAP5_7D,
1213
1214 PREFIX_EVEX_MAP6_13,
1215 PREFIX_EVEX_MAP6_56,
1216 PREFIX_EVEX_MAP6_57,
1217 PREFIX_EVEX_MAP6_D6,
1218 PREFIX_EVEX_MAP6_D7,
1219 };
1220
1221 enum
1222 {
1223 X86_64_06 = 0,
1224 X86_64_07,
1225 X86_64_0E,
1226 X86_64_16,
1227 X86_64_17,
1228 X86_64_1E,
1229 X86_64_1F,
1230 X86_64_27,
1231 X86_64_2F,
1232 X86_64_37,
1233 X86_64_3F,
1234 X86_64_60,
1235 X86_64_61,
1236 X86_64_62,
1237 X86_64_63,
1238 X86_64_6D,
1239 X86_64_6F,
1240 X86_64_82,
1241 X86_64_9A,
1242 X86_64_C2,
1243 X86_64_C3,
1244 X86_64_C4,
1245 X86_64_C5,
1246 X86_64_CE,
1247 X86_64_D4,
1248 X86_64_D5,
1249 X86_64_E8,
1250 X86_64_E9,
1251 X86_64_EA,
1252 X86_64_0F01_REG_0,
1253 X86_64_0F01_REG_1,
1254 X86_64_0F01_REG_1_RM_5_PREFIX_2,
1255 X86_64_0F01_REG_1_RM_6_PREFIX_2,
1256 X86_64_0F01_REG_1_RM_7_PREFIX_2,
1257 X86_64_0F01_REG_2,
1258 X86_64_0F01_REG_3,
1259 X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
1260 X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
1261 X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
1262 X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
1263 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
1264 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
1265 X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
1266 X86_64_0F24,
1267 X86_64_0F26,
1268 X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
1269
1270 X86_64_VEX_0F3849,
1271 X86_64_VEX_0F384B,
1272 X86_64_VEX_0F385C,
1273 X86_64_VEX_0F385E
1274 };
1275
1276 enum
1277 {
1278 THREE_BYTE_0F38 = 0,
1279 THREE_BYTE_0F3A
1280 };
1281
1282 enum
1283 {
1284 XOP_08 = 0,
1285 XOP_09,
1286 XOP_0A
1287 };
1288
1289 enum
1290 {
1291 VEX_0F = 0,
1292 VEX_0F38,
1293 VEX_0F3A
1294 };
1295
1296 enum
1297 {
1298 EVEX_0F = 0,
1299 EVEX_0F38,
1300 EVEX_0F3A,
1301 EVEX_MAP5,
1302 EVEX_MAP6,
1303 };
1304
1305 enum
1306 {
1307 VEX_LEN_0F12_P_0_M_0 = 0,
1308 VEX_LEN_0F12_P_0_M_1,
1309 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1310 VEX_LEN_0F13_M_0,
1311 VEX_LEN_0F16_P_0_M_0,
1312 VEX_LEN_0F16_P_0_M_1,
1313 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1314 VEX_LEN_0F17_M_0,
1315 VEX_LEN_0F41,
1316 VEX_LEN_0F42,
1317 VEX_LEN_0F44,
1318 VEX_LEN_0F45,
1319 VEX_LEN_0F46,
1320 VEX_LEN_0F47,
1321 VEX_LEN_0F4A,
1322 VEX_LEN_0F4B,
1323 VEX_LEN_0F6E,
1324 VEX_LEN_0F77,
1325 VEX_LEN_0F7E_P_1,
1326 VEX_LEN_0F7E_P_2,
1327 VEX_LEN_0F90,
1328 VEX_LEN_0F91,
1329 VEX_LEN_0F92,
1330 VEX_LEN_0F93,
1331 VEX_LEN_0F98,
1332 VEX_LEN_0F99,
1333 VEX_LEN_0FAE_R_2_M_0,
1334 VEX_LEN_0FAE_R_3_M_0,
1335 VEX_LEN_0FC4,
1336 VEX_LEN_0FC5,
1337 VEX_LEN_0FD6,
1338 VEX_LEN_0FF7,
1339 VEX_LEN_0F3816,
1340 VEX_LEN_0F3819,
1341 VEX_LEN_0F381A_M_0,
1342 VEX_LEN_0F3836,
1343 VEX_LEN_0F3841,
1344 VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
1345 VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
1346 VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
1347 VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
1348 VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
1349 VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
1350 VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
1351 VEX_LEN_0F385A_M_0,
1352 VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
1353 VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
1354 VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
1355 VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
1356 VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
1357 VEX_LEN_0F38DB,
1358 VEX_LEN_0F38F2,
1359 VEX_LEN_0F38F3,
1360 VEX_LEN_0F38F5,
1361 VEX_LEN_0F38F6,
1362 VEX_LEN_0F38F7,
1363 VEX_LEN_0F3A00,
1364 VEX_LEN_0F3A01,
1365 VEX_LEN_0F3A06,
1366 VEX_LEN_0F3A14,
1367 VEX_LEN_0F3A15,
1368 VEX_LEN_0F3A16,
1369 VEX_LEN_0F3A17,
1370 VEX_LEN_0F3A18,
1371 VEX_LEN_0F3A19,
1372 VEX_LEN_0F3A20,
1373 VEX_LEN_0F3A21,
1374 VEX_LEN_0F3A22,
1375 VEX_LEN_0F3A30,
1376 VEX_LEN_0F3A31,
1377 VEX_LEN_0F3A32,
1378 VEX_LEN_0F3A33,
1379 VEX_LEN_0F3A38,
1380 VEX_LEN_0F3A39,
1381 VEX_LEN_0F3A41,
1382 VEX_LEN_0F3A46,
1383 VEX_LEN_0F3A60,
1384 VEX_LEN_0F3A61,
1385 VEX_LEN_0F3A62,
1386 VEX_LEN_0F3A63,
1387 VEX_LEN_0F3ADF,
1388 VEX_LEN_0F3AF0,
1389 VEX_LEN_0FXOP_08_85,
1390 VEX_LEN_0FXOP_08_86,
1391 VEX_LEN_0FXOP_08_87,
1392 VEX_LEN_0FXOP_08_8E,
1393 VEX_LEN_0FXOP_08_8F,
1394 VEX_LEN_0FXOP_08_95,
1395 VEX_LEN_0FXOP_08_96,
1396 VEX_LEN_0FXOP_08_97,
1397 VEX_LEN_0FXOP_08_9E,
1398 VEX_LEN_0FXOP_08_9F,
1399 VEX_LEN_0FXOP_08_A3,
1400 VEX_LEN_0FXOP_08_A6,
1401 VEX_LEN_0FXOP_08_B6,
1402 VEX_LEN_0FXOP_08_C0,
1403 VEX_LEN_0FXOP_08_C1,
1404 VEX_LEN_0FXOP_08_C2,
1405 VEX_LEN_0FXOP_08_C3,
1406 VEX_LEN_0FXOP_08_CC,
1407 VEX_LEN_0FXOP_08_CD,
1408 VEX_LEN_0FXOP_08_CE,
1409 VEX_LEN_0FXOP_08_CF,
1410 VEX_LEN_0FXOP_08_EC,
1411 VEX_LEN_0FXOP_08_ED,
1412 VEX_LEN_0FXOP_08_EE,
1413 VEX_LEN_0FXOP_08_EF,
1414 VEX_LEN_0FXOP_09_01,
1415 VEX_LEN_0FXOP_09_02,
1416 VEX_LEN_0FXOP_09_12_M_1,
1417 VEX_LEN_0FXOP_09_82_W_0,
1418 VEX_LEN_0FXOP_09_83_W_0,
1419 VEX_LEN_0FXOP_09_90,
1420 VEX_LEN_0FXOP_09_91,
1421 VEX_LEN_0FXOP_09_92,
1422 VEX_LEN_0FXOP_09_93,
1423 VEX_LEN_0FXOP_09_94,
1424 VEX_LEN_0FXOP_09_95,
1425 VEX_LEN_0FXOP_09_96,
1426 VEX_LEN_0FXOP_09_97,
1427 VEX_LEN_0FXOP_09_98,
1428 VEX_LEN_0FXOP_09_99,
1429 VEX_LEN_0FXOP_09_9A,
1430 VEX_LEN_0FXOP_09_9B,
1431 VEX_LEN_0FXOP_09_C1,
1432 VEX_LEN_0FXOP_09_C2,
1433 VEX_LEN_0FXOP_09_C3,
1434 VEX_LEN_0FXOP_09_C6,
1435 VEX_LEN_0FXOP_09_C7,
1436 VEX_LEN_0FXOP_09_CB,
1437 VEX_LEN_0FXOP_09_D1,
1438 VEX_LEN_0FXOP_09_D2,
1439 VEX_LEN_0FXOP_09_D3,
1440 VEX_LEN_0FXOP_09_D6,
1441 VEX_LEN_0FXOP_09_D7,
1442 VEX_LEN_0FXOP_09_DB,
1443 VEX_LEN_0FXOP_09_E1,
1444 VEX_LEN_0FXOP_09_E2,
1445 VEX_LEN_0FXOP_09_E3,
1446 VEX_LEN_0FXOP_0A_12,
1447 };
1448
1449 enum
1450 {
1451 EVEX_LEN_0F3816 = 0,
1452 EVEX_LEN_0F3819,
1453 EVEX_LEN_0F381A_M_0,
1454 EVEX_LEN_0F381B_M_0,
1455 EVEX_LEN_0F3836,
1456 EVEX_LEN_0F385A_M_0,
1457 EVEX_LEN_0F385B_M_0,
1458 EVEX_LEN_0F38C6_M_0,
1459 EVEX_LEN_0F38C7_M_0,
1460 EVEX_LEN_0F3A00,
1461 EVEX_LEN_0F3A01,
1462 EVEX_LEN_0F3A18,
1463 EVEX_LEN_0F3A19,
1464 EVEX_LEN_0F3A1A,
1465 EVEX_LEN_0F3A1B,
1466 EVEX_LEN_0F3A23,
1467 EVEX_LEN_0F3A38,
1468 EVEX_LEN_0F3A39,
1469 EVEX_LEN_0F3A3A,
1470 EVEX_LEN_0F3A3B,
1471 EVEX_LEN_0F3A43
1472 };
1473
1474 enum
1475 {
1476 VEX_W_0F41_L_1_M_1 = 0,
1477 VEX_W_0F42_L_1_M_1,
1478 VEX_W_0F44_L_0_M_1,
1479 VEX_W_0F45_L_1_M_1,
1480 VEX_W_0F46_L_1_M_1,
1481 VEX_W_0F47_L_1_M_1,
1482 VEX_W_0F4A_L_1_M_1,
1483 VEX_W_0F4B_L_1_M_1,
1484 VEX_W_0F90_L_0,
1485 VEX_W_0F91_L_0_M_0,
1486 VEX_W_0F92_L_0_M_1,
1487 VEX_W_0F93_L_0_M_1,
1488 VEX_W_0F98_L_0_M_1,
1489 VEX_W_0F99_L_0_M_1,
1490 VEX_W_0F380C,
1491 VEX_W_0F380D,
1492 VEX_W_0F380E,
1493 VEX_W_0F380F,
1494 VEX_W_0F3813,
1495 VEX_W_0F3816_L_1,
1496 VEX_W_0F3818,
1497 VEX_W_0F3819_L_1,
1498 VEX_W_0F381A_M_0_L_1,
1499 VEX_W_0F382C_M_0,
1500 VEX_W_0F382D_M_0,
1501 VEX_W_0F382E_M_0,
1502 VEX_W_0F382F_M_0,
1503 VEX_W_0F3836,
1504 VEX_W_0F3846,
1505 VEX_W_0F3849_X86_64_P_0,
1506 VEX_W_0F3849_X86_64_P_2,
1507 VEX_W_0F3849_X86_64_P_3,
1508 VEX_W_0F384B_X86_64_P_1,
1509 VEX_W_0F384B_X86_64_P_2,
1510 VEX_W_0F384B_X86_64_P_3,
1511 VEX_W_0F3850,
1512 VEX_W_0F3851,
1513 VEX_W_0F3852,
1514 VEX_W_0F3853,
1515 VEX_W_0F3858,
1516 VEX_W_0F3859,
1517 VEX_W_0F385A_M_0_L_0,
1518 VEX_W_0F385C_X86_64_P_1,
1519 VEX_W_0F385E_X86_64_P_0,
1520 VEX_W_0F385E_X86_64_P_1,
1521 VEX_W_0F385E_X86_64_P_2,
1522 VEX_W_0F385E_X86_64_P_3,
1523 VEX_W_0F3878,
1524 VEX_W_0F3879,
1525 VEX_W_0F38CF,
1526 VEX_W_0F3A00_L_1,
1527 VEX_W_0F3A01_L_1,
1528 VEX_W_0F3A02,
1529 VEX_W_0F3A04,
1530 VEX_W_0F3A05,
1531 VEX_W_0F3A06_L_1,
1532 VEX_W_0F3A18_L_1,
1533 VEX_W_0F3A19_L_1,
1534 VEX_W_0F3A1D,
1535 VEX_W_0F3A38_L_1,
1536 VEX_W_0F3A39_L_1,
1537 VEX_W_0F3A46_L_1,
1538 VEX_W_0F3A4A,
1539 VEX_W_0F3A4B,
1540 VEX_W_0F3A4C,
1541 VEX_W_0F3ACE,
1542 VEX_W_0F3ACF,
1543
1544 VEX_W_0FXOP_08_85_L_0,
1545 VEX_W_0FXOP_08_86_L_0,
1546 VEX_W_0FXOP_08_87_L_0,
1547 VEX_W_0FXOP_08_8E_L_0,
1548 VEX_W_0FXOP_08_8F_L_0,
1549 VEX_W_0FXOP_08_95_L_0,
1550 VEX_W_0FXOP_08_96_L_0,
1551 VEX_W_0FXOP_08_97_L_0,
1552 VEX_W_0FXOP_08_9E_L_0,
1553 VEX_W_0FXOP_08_9F_L_0,
1554 VEX_W_0FXOP_08_A6_L_0,
1555 VEX_W_0FXOP_08_B6_L_0,
1556 VEX_W_0FXOP_08_C0_L_0,
1557 VEX_W_0FXOP_08_C1_L_0,
1558 VEX_W_0FXOP_08_C2_L_0,
1559 VEX_W_0FXOP_08_C3_L_0,
1560 VEX_W_0FXOP_08_CC_L_0,
1561 VEX_W_0FXOP_08_CD_L_0,
1562 VEX_W_0FXOP_08_CE_L_0,
1563 VEX_W_0FXOP_08_CF_L_0,
1564 VEX_W_0FXOP_08_EC_L_0,
1565 VEX_W_0FXOP_08_ED_L_0,
1566 VEX_W_0FXOP_08_EE_L_0,
1567 VEX_W_0FXOP_08_EF_L_0,
1568
1569 VEX_W_0FXOP_09_80,
1570 VEX_W_0FXOP_09_81,
1571 VEX_W_0FXOP_09_82,
1572 VEX_W_0FXOP_09_83,
1573 VEX_W_0FXOP_09_C1_L_0,
1574 VEX_W_0FXOP_09_C2_L_0,
1575 VEX_W_0FXOP_09_C3_L_0,
1576 VEX_W_0FXOP_09_C6_L_0,
1577 VEX_W_0FXOP_09_C7_L_0,
1578 VEX_W_0FXOP_09_CB_L_0,
1579 VEX_W_0FXOP_09_D1_L_0,
1580 VEX_W_0FXOP_09_D2_L_0,
1581 VEX_W_0FXOP_09_D3_L_0,
1582 VEX_W_0FXOP_09_D6_L_0,
1583 VEX_W_0FXOP_09_D7_L_0,
1584 VEX_W_0FXOP_09_DB_L_0,
1585 VEX_W_0FXOP_09_E1_L_0,
1586 VEX_W_0FXOP_09_E2_L_0,
1587 VEX_W_0FXOP_09_E3_L_0,
1588
1589 EVEX_W_0F5B_P_0,
1590 EVEX_W_0F62,
1591 EVEX_W_0F66,
1592 EVEX_W_0F6A,
1593 EVEX_W_0F6B,
1594 EVEX_W_0F6C,
1595 EVEX_W_0F6D,
1596 EVEX_W_0F6F_P_1,
1597 EVEX_W_0F6F_P_2,
1598 EVEX_W_0F6F_P_3,
1599 EVEX_W_0F70_P_2,
1600 EVEX_W_0F72_R_2,
1601 EVEX_W_0F72_R_6,
1602 EVEX_W_0F73_R_2,
1603 EVEX_W_0F73_R_6,
1604 EVEX_W_0F76,
1605 EVEX_W_0F78_P_0,
1606 EVEX_W_0F78_P_2,
1607 EVEX_W_0F79_P_0,
1608 EVEX_W_0F79_P_2,
1609 EVEX_W_0F7A_P_1,
1610 EVEX_W_0F7A_P_2,
1611 EVEX_W_0F7A_P_3,
1612 EVEX_W_0F7B_P_2,
1613 EVEX_W_0F7E_P_1,
1614 EVEX_W_0F7F_P_1,
1615 EVEX_W_0F7F_P_2,
1616 EVEX_W_0F7F_P_3,
1617 EVEX_W_0FD2,
1618 EVEX_W_0FD3,
1619 EVEX_W_0FD4,
1620 EVEX_W_0FD6,
1621 EVEX_W_0FE6_P_1,
1622 EVEX_W_0FE7,
1623 EVEX_W_0FF2,
1624 EVEX_W_0FF3,
1625 EVEX_W_0FF4,
1626 EVEX_W_0FFA,
1627 EVEX_W_0FFB,
1628 EVEX_W_0FFE,
1629
1630 EVEX_W_0F3810_P_1,
1631 EVEX_W_0F3810_P_2,
1632 EVEX_W_0F3811_P_1,
1633 EVEX_W_0F3811_P_2,
1634 EVEX_W_0F3812_P_1,
1635 EVEX_W_0F3812_P_2,
1636 EVEX_W_0F3813_P_1,
1637 EVEX_W_0F3814_P_1,
1638 EVEX_W_0F3815_P_1,
1639 EVEX_W_0F3819_L_n,
1640 EVEX_W_0F381A_M_0_L_n,
1641 EVEX_W_0F381B_M_0_L_2,
1642 EVEX_W_0F381E,
1643 EVEX_W_0F381F,
1644 EVEX_W_0F3820_P_1,
1645 EVEX_W_0F3821_P_1,
1646 EVEX_W_0F3822_P_1,
1647 EVEX_W_0F3823_P_1,
1648 EVEX_W_0F3824_P_1,
1649 EVEX_W_0F3825_P_1,
1650 EVEX_W_0F3825_P_2,
1651 EVEX_W_0F3828_P_2,
1652 EVEX_W_0F3829_P_2,
1653 EVEX_W_0F382A_P_1,
1654 EVEX_W_0F382A_P_2,
1655 EVEX_W_0F382B,
1656 EVEX_W_0F3830_P_1,
1657 EVEX_W_0F3831_P_1,
1658 EVEX_W_0F3832_P_1,
1659 EVEX_W_0F3833_P_1,
1660 EVEX_W_0F3834_P_1,
1661 EVEX_W_0F3835_P_1,
1662 EVEX_W_0F3835_P_2,
1663 EVEX_W_0F3837,
1664 EVEX_W_0F383A_P_1,
1665 EVEX_W_0F3859,
1666 EVEX_W_0F385A_M_0_L_n,
1667 EVEX_W_0F385B_M_0_L_2,
1668 EVEX_W_0F3870,
1669 EVEX_W_0F3872_P_2,
1670 EVEX_W_0F387A,
1671 EVEX_W_0F387B,
1672 EVEX_W_0F3883,
1673
1674 EVEX_W_0F3A18_L_n,
1675 EVEX_W_0F3A19_L_n,
1676 EVEX_W_0F3A1A_L_2,
1677 EVEX_W_0F3A1B_L_2,
1678 EVEX_W_0F3A21,
1679 EVEX_W_0F3A23_L_n,
1680 EVEX_W_0F3A38_L_n,
1681 EVEX_W_0F3A39_L_n,
1682 EVEX_W_0F3A3A_L_2,
1683 EVEX_W_0F3A3B_L_2,
1684 EVEX_W_0F3A42,
1685 EVEX_W_0F3A43_L_n,
1686 EVEX_W_0F3A70,
1687 EVEX_W_0F3A72,
1688
1689 EVEX_W_MAP5_5B_P_0,
1690 EVEX_W_MAP5_7A_P_3,
1691 };
1692
1693 typedef void (*op_rtn) (instr_info *ins, int bytemode, int sizeflag);
1694
1695 struct dis386 {
1696 const char *name;
1697 struct
1698 {
1699 op_rtn rtn;
1700 int bytemode;
1701 } op[MAX_OPERANDS];
1702 unsigned int prefix_requirement;
1703 };
1704
1705 /* Upper case letters in the instruction names here are macros.
1706 'A' => print 'b' if no register operands or suffix_always is true
1707 'B' => print 'b' if suffix_always is true
1708 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1709 size prefix
1710 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1711 suffix_always is true
1712 'E' => print 'e' if 32-bit form of jcxz
1713 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1714 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1715 'H' => print ",pt" or ",pn" branch hint
1716 'I' unused.
1717 'J' unused.
1718 'K' => print 'd' or 'q' if rex prefix is present.
1719 'L' unused.
1720 'M' => print 'r' if intel_mnemonic is false.
1721 'N' => print 'n' if instruction has no wait "prefix"
1722 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1723 'P' => behave as 'T' except with register operand outside of suffix_always
1724 mode
1725 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1726 is true
1727 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1728 'S' => print 'w', 'l' or 'q' if suffix_always is true
1729 'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1730 prefix or if suffix_always is true.
1731 'U' unused.
1732 'V' unused.
1733 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1734 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1735 'Y' unused.
1736 'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1737 '!' => change condition from true to false or from false to true.
1738 '%' => add 1 upper case letter to the macro.
1739 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1740 prefix or suffix_always is true (lcall/ljmp).
1741 '@' => in 64bit mode for Intel64 ISA or if instruction
1742 has no operand sizing prefix, print 'q' if suffix_always is true or
1743 nothing otherwise; behave as 'P' in all other cases
1744
1745 2 upper case letter macros:
1746 "XY" => print 'x' or 'y' if suffix_always is true or no register
1747 operands and no broadcast.
1748 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1749 register operands and no broadcast.
1750 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1751 "XD" => print 'd' if !EVEX or EVEX.W=1, EVEX.W=0 is not a valid encoding
1752 "XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16)
1753 "XS" => print 's' if !EVEX or EVEX.W=0, EVEX.W=1 is not a valid encoding
1754 "XV" => print "{vex3}" pseudo prefix
1755 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1756 being false, or no operand at all in 64bit mode, or if suffix_always
1757 is true.
1758 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1759 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1760 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1761 "DQ" => print 'd' or 'q' depending on the VEX.W bit
1762 "BW" => print 'b' or 'w' depending on the VEX.W bit
1763 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1764 an operand size prefix, or suffix_always is true. print
1765 'q' if rex prefix is present.
1766
1767 Many of the above letters print nothing in Intel mode. See "putop"
1768 for the details.
1769
1770 Braces '{' and '}', and vertical bars '|', indicate alternative
1771 mnemonic strings for AT&T and Intel. */
1772
1773 static const struct dis386 dis386[] = {
1774 /* 00 */
1775 { "addB", { Ebh1, Gb }, 0 },
1776 { "addS", { Evh1, Gv }, 0 },
1777 { "addB", { Gb, EbS }, 0 },
1778 { "addS", { Gv, EvS }, 0 },
1779 { "addB", { AL, Ib }, 0 },
1780 { "addS", { eAX, Iv }, 0 },
1781 { X86_64_TABLE (X86_64_06) },
1782 { X86_64_TABLE (X86_64_07) },
1783 /* 08 */
1784 { "orB", { Ebh1, Gb }, 0 },
1785 { "orS", { Evh1, Gv }, 0 },
1786 { "orB", { Gb, EbS }, 0 },
1787 { "orS", { Gv, EvS }, 0 },
1788 { "orB", { AL, Ib }, 0 },
1789 { "orS", { eAX, Iv }, 0 },
1790 { X86_64_TABLE (X86_64_0E) },
1791 { Bad_Opcode }, /* 0x0f extended opcode escape */
1792 /* 10 */
1793 { "adcB", { Ebh1, Gb }, 0 },
1794 { "adcS", { Evh1, Gv }, 0 },
1795 { "adcB", { Gb, EbS }, 0 },
1796 { "adcS", { Gv, EvS }, 0 },
1797 { "adcB", { AL, Ib }, 0 },
1798 { "adcS", { eAX, Iv }, 0 },
1799 { X86_64_TABLE (X86_64_16) },
1800 { X86_64_TABLE (X86_64_17) },
1801 /* 18 */
1802 { "sbbB", { Ebh1, Gb }, 0 },
1803 { "sbbS", { Evh1, Gv }, 0 },
1804 { "sbbB", { Gb, EbS }, 0 },
1805 { "sbbS", { Gv, EvS }, 0 },
1806 { "sbbB", { AL, Ib }, 0 },
1807 { "sbbS", { eAX, Iv }, 0 },
1808 { X86_64_TABLE (X86_64_1E) },
1809 { X86_64_TABLE (X86_64_1F) },
1810 /* 20 */
1811 { "andB", { Ebh1, Gb }, 0 },
1812 { "andS", { Evh1, Gv }, 0 },
1813 { "andB", { Gb, EbS }, 0 },
1814 { "andS", { Gv, EvS }, 0 },
1815 { "andB", { AL, Ib }, 0 },
1816 { "andS", { eAX, Iv }, 0 },
1817 { Bad_Opcode }, /* SEG ES prefix */
1818 { X86_64_TABLE (X86_64_27) },
1819 /* 28 */
1820 { "subB", { Ebh1, Gb }, 0 },
1821 { "subS", { Evh1, Gv }, 0 },
1822 { "subB", { Gb, EbS }, 0 },
1823 { "subS", { Gv, EvS }, 0 },
1824 { "subB", { AL, Ib }, 0 },
1825 { "subS", { eAX, Iv }, 0 },
1826 { Bad_Opcode }, /* SEG CS prefix */
1827 { X86_64_TABLE (X86_64_2F) },
1828 /* 30 */
1829 { "xorB", { Ebh1, Gb }, 0 },
1830 { "xorS", { Evh1, Gv }, 0 },
1831 { "xorB", { Gb, EbS }, 0 },
1832 { "xorS", { Gv, EvS }, 0 },
1833 { "xorB", { AL, Ib }, 0 },
1834 { "xorS", { eAX, Iv }, 0 },
1835 { Bad_Opcode }, /* SEG SS prefix */
1836 { X86_64_TABLE (X86_64_37) },
1837 /* 38 */
1838 { "cmpB", { Eb, Gb }, 0 },
1839 { "cmpS", { Ev, Gv }, 0 },
1840 { "cmpB", { Gb, EbS }, 0 },
1841 { "cmpS", { Gv, EvS }, 0 },
1842 { "cmpB", { AL, Ib }, 0 },
1843 { "cmpS", { eAX, Iv }, 0 },
1844 { Bad_Opcode }, /* SEG DS prefix */
1845 { X86_64_TABLE (X86_64_3F) },
1846 /* 40 */
1847 { "inc{S|}", { RMeAX }, 0 },
1848 { "inc{S|}", { RMeCX }, 0 },
1849 { "inc{S|}", { RMeDX }, 0 },
1850 { "inc{S|}", { RMeBX }, 0 },
1851 { "inc{S|}", { RMeSP }, 0 },
1852 { "inc{S|}", { RMeBP }, 0 },
1853 { "inc{S|}", { RMeSI }, 0 },
1854 { "inc{S|}", { RMeDI }, 0 },
1855 /* 48 */
1856 { "dec{S|}", { RMeAX }, 0 },
1857 { "dec{S|}", { RMeCX }, 0 },
1858 { "dec{S|}", { RMeDX }, 0 },
1859 { "dec{S|}", { RMeBX }, 0 },
1860 { "dec{S|}", { RMeSP }, 0 },
1861 { "dec{S|}", { RMeBP }, 0 },
1862 { "dec{S|}", { RMeSI }, 0 },
1863 { "dec{S|}", { RMeDI }, 0 },
1864 /* 50 */
1865 { "push{!P|}", { RMrAX }, 0 },
1866 { "push{!P|}", { RMrCX }, 0 },
1867 { "push{!P|}", { RMrDX }, 0 },
1868 { "push{!P|}", { RMrBX }, 0 },
1869 { "push{!P|}", { RMrSP }, 0 },
1870 { "push{!P|}", { RMrBP }, 0 },
1871 { "push{!P|}", { RMrSI }, 0 },
1872 { "push{!P|}", { RMrDI }, 0 },
1873 /* 58 */
1874 { "pop{!P|}", { RMrAX }, 0 },
1875 { "pop{!P|}", { RMrCX }, 0 },
1876 { "pop{!P|}", { RMrDX }, 0 },
1877 { "pop{!P|}", { RMrBX }, 0 },
1878 { "pop{!P|}", { RMrSP }, 0 },
1879 { "pop{!P|}", { RMrBP }, 0 },
1880 { "pop{!P|}", { RMrSI }, 0 },
1881 { "pop{!P|}", { RMrDI }, 0 },
1882 /* 60 */
1883 { X86_64_TABLE (X86_64_60) },
1884 { X86_64_TABLE (X86_64_61) },
1885 { X86_64_TABLE (X86_64_62) },
1886 { X86_64_TABLE (X86_64_63) },
1887 { Bad_Opcode }, /* seg fs */
1888 { Bad_Opcode }, /* seg gs */
1889 { Bad_Opcode }, /* op size prefix */
1890 { Bad_Opcode }, /* adr size prefix */
1891 /* 68 */
1892 { "pushP", { sIv }, 0 },
1893 { "imulS", { Gv, Ev, Iv }, 0 },
1894 { "pushP", { sIbT }, 0 },
1895 { "imulS", { Gv, Ev, sIb }, 0 },
1896 { "ins{b|}", { Ybr, indirDX }, 0 },
1897 { X86_64_TABLE (X86_64_6D) },
1898 { "outs{b|}", { indirDXr, Xb }, 0 },
1899 { X86_64_TABLE (X86_64_6F) },
1900 /* 70 */
1901 { "joH", { Jb, BND, cond_jump_flag }, 0 },
1902 { "jnoH", { Jb, BND, cond_jump_flag }, 0 },
1903 { "jbH", { Jb, BND, cond_jump_flag }, 0 },
1904 { "jaeH", { Jb, BND, cond_jump_flag }, 0 },
1905 { "jeH", { Jb, BND, cond_jump_flag }, 0 },
1906 { "jneH", { Jb, BND, cond_jump_flag }, 0 },
1907 { "jbeH", { Jb, BND, cond_jump_flag }, 0 },
1908 { "jaH", { Jb, BND, cond_jump_flag }, 0 },
1909 /* 78 */
1910 { "jsH", { Jb, BND, cond_jump_flag }, 0 },
1911 { "jnsH", { Jb, BND, cond_jump_flag }, 0 },
1912 { "jpH", { Jb, BND, cond_jump_flag }, 0 },
1913 { "jnpH", { Jb, BND, cond_jump_flag }, 0 },
1914 { "jlH", { Jb, BND, cond_jump_flag }, 0 },
1915 { "jgeH", { Jb, BND, cond_jump_flag }, 0 },
1916 { "jleH", { Jb, BND, cond_jump_flag }, 0 },
1917 { "jgH", { Jb, BND, cond_jump_flag }, 0 },
1918 /* 80 */
1919 { REG_TABLE (REG_80) },
1920 { REG_TABLE (REG_81) },
1921 { X86_64_TABLE (X86_64_82) },
1922 { REG_TABLE (REG_83) },
1923 { "testB", { Eb, Gb }, 0 },
1924 { "testS", { Ev, Gv }, 0 },
1925 { "xchgB", { Ebh2, Gb }, 0 },
1926 { "xchgS", { Evh2, Gv }, 0 },
1927 /* 88 */
1928 { "movB", { Ebh3, Gb }, 0 },
1929 { "movS", { Evh3, Gv }, 0 },
1930 { "movB", { Gb, EbS }, 0 },
1931 { "movS", { Gv, EvS }, 0 },
1932 { "movD", { Sv, Sw }, 0 },
1933 { MOD_TABLE (MOD_8D) },
1934 { "movD", { Sw, Sv }, 0 },
1935 { REG_TABLE (REG_8F) },
1936 /* 90 */
1937 { PREFIX_TABLE (PREFIX_90) },
1938 { "xchgS", { RMeCX, eAX }, 0 },
1939 { "xchgS", { RMeDX, eAX }, 0 },
1940 { "xchgS", { RMeBX, eAX }, 0 },
1941 { "xchgS", { RMeSP, eAX }, 0 },
1942 { "xchgS", { RMeBP, eAX }, 0 },
1943 { "xchgS", { RMeSI, eAX }, 0 },
1944 { "xchgS", { RMeDI, eAX }, 0 },
1945 /* 98 */
1946 { "cW{t|}R", { XX }, 0 },
1947 { "cR{t|}O", { XX }, 0 },
1948 { X86_64_TABLE (X86_64_9A) },
1949 { Bad_Opcode }, /* fwait */
1950 { "pushfP", { XX }, 0 },
1951 { "popfP", { XX }, 0 },
1952 { "sahf", { XX }, 0 },
1953 { "lahf", { XX }, 0 },
1954 /* a0 */
1955 { "mov%LB", { AL, Ob }, 0 },
1956 { "mov%LS", { eAX, Ov }, 0 },
1957 { "mov%LB", { Ob, AL }, 0 },
1958 { "mov%LS", { Ov, eAX }, 0 },
1959 { "movs{b|}", { Ybr, Xb }, 0 },
1960 { "movs{R|}", { Yvr, Xv }, 0 },
1961 { "cmps{b|}", { Xb, Yb }, 0 },
1962 { "cmps{R|}", { Xv, Yv }, 0 },
1963 /* a8 */
1964 { "testB", { AL, Ib }, 0 },
1965 { "testS", { eAX, Iv }, 0 },
1966 { "stosB", { Ybr, AL }, 0 },
1967 { "stosS", { Yvr, eAX }, 0 },
1968 { "lodsB", { ALr, Xb }, 0 },
1969 { "lodsS", { eAXr, Xv }, 0 },
1970 { "scasB", { AL, Yb }, 0 },
1971 { "scasS", { eAX, Yv }, 0 },
1972 /* b0 */
1973 { "movB", { RMAL, Ib }, 0 },
1974 { "movB", { RMCL, Ib }, 0 },
1975 { "movB", { RMDL, Ib }, 0 },
1976 { "movB", { RMBL, Ib }, 0 },
1977 { "movB", { RMAH, Ib }, 0 },
1978 { "movB", { RMCH, Ib }, 0 },
1979 { "movB", { RMDH, Ib }, 0 },
1980 { "movB", { RMBH, Ib }, 0 },
1981 /* b8 */
1982 { "mov%LV", { RMeAX, Iv64 }, 0 },
1983 { "mov%LV", { RMeCX, Iv64 }, 0 },
1984 { "mov%LV", { RMeDX, Iv64 }, 0 },
1985 { "mov%LV", { RMeBX, Iv64 }, 0 },
1986 { "mov%LV", { RMeSP, Iv64 }, 0 },
1987 { "mov%LV", { RMeBP, Iv64 }, 0 },
1988 { "mov%LV", { RMeSI, Iv64 }, 0 },
1989 { "mov%LV", { RMeDI, Iv64 }, 0 },
1990 /* c0 */
1991 { REG_TABLE (REG_C0) },
1992 { REG_TABLE (REG_C1) },
1993 { X86_64_TABLE (X86_64_C2) },
1994 { X86_64_TABLE (X86_64_C3) },
1995 { X86_64_TABLE (X86_64_C4) },
1996 { X86_64_TABLE (X86_64_C5) },
1997 { REG_TABLE (REG_C6) },
1998 { REG_TABLE (REG_C7) },
1999 /* c8 */
2000 { "enterP", { Iw, Ib }, 0 },
2001 { "leaveP", { XX }, 0 },
2002 { "{l|}ret{|f}%LP", { Iw }, 0 },
2003 { "{l|}ret{|f}%LP", { XX }, 0 },
2004 { "int3", { XX }, 0 },
2005 { "int", { Ib }, 0 },
2006 { X86_64_TABLE (X86_64_CE) },
2007 { "iret%LP", { XX }, 0 },
2008 /* d0 */
2009 { REG_TABLE (REG_D0) },
2010 { REG_TABLE (REG_D1) },
2011 { REG_TABLE (REG_D2) },
2012 { REG_TABLE (REG_D3) },
2013 { X86_64_TABLE (X86_64_D4) },
2014 { X86_64_TABLE (X86_64_D5) },
2015 { Bad_Opcode },
2016 { "xlat", { DSBX }, 0 },
2017 /* d8 */
2018 { FLOAT },
2019 { FLOAT },
2020 { FLOAT },
2021 { FLOAT },
2022 { FLOAT },
2023 { FLOAT },
2024 { FLOAT },
2025 { FLOAT },
2026 /* e0 */
2027 { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 },
2028 { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 },
2029 { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 },
2030 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 },
2031 { "inB", { AL, Ib }, 0 },
2032 { "inG", { zAX, Ib }, 0 },
2033 { "outB", { Ib, AL }, 0 },
2034 { "outG", { Ib, zAX }, 0 },
2035 /* e8 */
2036 { X86_64_TABLE (X86_64_E8) },
2037 { X86_64_TABLE (X86_64_E9) },
2038 { X86_64_TABLE (X86_64_EA) },
2039 { "jmp", { Jb, BND }, 0 },
2040 { "inB", { AL, indirDX }, 0 },
2041 { "inG", { zAX, indirDX }, 0 },
2042 { "outB", { indirDX, AL }, 0 },
2043 { "outG", { indirDX, zAX }, 0 },
2044 /* f0 */
2045 { Bad_Opcode }, /* lock prefix */
2046 { "int1", { XX }, 0 },
2047 { Bad_Opcode }, /* repne */
2048 { Bad_Opcode }, /* repz */
2049 { "hlt", { XX }, 0 },
2050 { "cmc", { XX }, 0 },
2051 { REG_TABLE (REG_F6) },
2052 { REG_TABLE (REG_F7) },
2053 /* f8 */
2054 { "clc", { XX }, 0 },
2055 { "stc", { XX }, 0 },
2056 { "cli", { XX }, 0 },
2057 { "sti", { XX }, 0 },
2058 { "cld", { XX }, 0 },
2059 { "std", { XX }, 0 },
2060 { REG_TABLE (REG_FE) },
2061 { REG_TABLE (REG_FF) },
2062 };
2063
2064 static const struct dis386 dis386_twobyte[] = {
2065 /* 00 */
2066 { REG_TABLE (REG_0F00 ) },
2067 { REG_TABLE (REG_0F01 ) },
2068 { "larS", { Gv, Ew }, 0 },
2069 { "lslS", { Gv, Ew }, 0 },
2070 { Bad_Opcode },
2071 { "syscall", { XX }, 0 },
2072 { "clts", { XX }, 0 },
2073 { "sysret%LQ", { XX }, 0 },
2074 /* 08 */
2075 { "invd", { XX }, 0 },
2076 { PREFIX_TABLE (PREFIX_0F09) },
2077 { Bad_Opcode },
2078 { "ud2", { XX }, 0 },
2079 { Bad_Opcode },
2080 { REG_TABLE (REG_0F0D) },
2081 { "femms", { XX }, 0 },
2082 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2083 /* 10 */
2084 { PREFIX_TABLE (PREFIX_0F10) },
2085 { PREFIX_TABLE (PREFIX_0F11) },
2086 { PREFIX_TABLE (PREFIX_0F12) },
2087 { MOD_TABLE (MOD_0F13) },
2088 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2089 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2090 { PREFIX_TABLE (PREFIX_0F16) },
2091 { MOD_TABLE (MOD_0F17) },
2092 /* 18 */
2093 { REG_TABLE (REG_0F18) },
2094 { "nopQ", { Ev }, 0 },
2095 { PREFIX_TABLE (PREFIX_0F1A) },
2096 { PREFIX_TABLE (PREFIX_0F1B) },
2097 { PREFIX_TABLE (PREFIX_0F1C) },
2098 { "nopQ", { Ev }, 0 },
2099 { PREFIX_TABLE (PREFIX_0F1E) },
2100 { "nopQ", { Ev }, 0 },
2101 /* 20 */
2102 { "movZ", { Em, Cm }, 0 },
2103 { "movZ", { Em, Dm }, 0 },
2104 { "movZ", { Cm, Em }, 0 },
2105 { "movZ", { Dm, Em }, 0 },
2106 { X86_64_TABLE (X86_64_0F24) },
2107 { Bad_Opcode },
2108 { X86_64_TABLE (X86_64_0F26) },
2109 { Bad_Opcode },
2110 /* 28 */
2111 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2112 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2113 { PREFIX_TABLE (PREFIX_0F2A) },
2114 { PREFIX_TABLE (PREFIX_0F2B) },
2115 { PREFIX_TABLE (PREFIX_0F2C) },
2116 { PREFIX_TABLE (PREFIX_0F2D) },
2117 { PREFIX_TABLE (PREFIX_0F2E) },
2118 { PREFIX_TABLE (PREFIX_0F2F) },
2119 /* 30 */
2120 { "wrmsr", { XX }, 0 },
2121 { "rdtsc", { XX }, 0 },
2122 { "rdmsr", { XX }, 0 },
2123 { "rdpmc", { XX }, 0 },
2124 { "sysenter", { SEP }, 0 },
2125 { "sysexit%LQ", { SEP }, 0 },
2126 { Bad_Opcode },
2127 { "getsec", { XX }, 0 },
2128 /* 38 */
2129 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2130 { Bad_Opcode },
2131 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2132 { Bad_Opcode },
2133 { Bad_Opcode },
2134 { Bad_Opcode },
2135 { Bad_Opcode },
2136 { Bad_Opcode },
2137 /* 40 */
2138 { "cmovoS", { Gv, Ev }, 0 },
2139 { "cmovnoS", { Gv, Ev }, 0 },
2140 { "cmovbS", { Gv, Ev }, 0 },
2141 { "cmovaeS", { Gv, Ev }, 0 },
2142 { "cmoveS", { Gv, Ev }, 0 },
2143 { "cmovneS", { Gv, Ev }, 0 },
2144 { "cmovbeS", { Gv, Ev }, 0 },
2145 { "cmovaS", { Gv, Ev }, 0 },
2146 /* 48 */
2147 { "cmovsS", { Gv, Ev }, 0 },
2148 { "cmovnsS", { Gv, Ev }, 0 },
2149 { "cmovpS", { Gv, Ev }, 0 },
2150 { "cmovnpS", { Gv, Ev }, 0 },
2151 { "cmovlS", { Gv, Ev }, 0 },
2152 { "cmovgeS", { Gv, Ev }, 0 },
2153 { "cmovleS", { Gv, Ev }, 0 },
2154 { "cmovgS", { Gv, Ev }, 0 },
2155 /* 50 */
2156 { MOD_TABLE (MOD_0F50) },
2157 { PREFIX_TABLE (PREFIX_0F51) },
2158 { PREFIX_TABLE (PREFIX_0F52) },
2159 { PREFIX_TABLE (PREFIX_0F53) },
2160 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2161 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2162 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2163 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2164 /* 58 */
2165 { PREFIX_TABLE (PREFIX_0F58) },
2166 { PREFIX_TABLE (PREFIX_0F59) },
2167 { PREFIX_TABLE (PREFIX_0F5A) },
2168 { PREFIX_TABLE (PREFIX_0F5B) },
2169 { PREFIX_TABLE (PREFIX_0F5C) },
2170 { PREFIX_TABLE (PREFIX_0F5D) },
2171 { PREFIX_TABLE (PREFIX_0F5E) },
2172 { PREFIX_TABLE (PREFIX_0F5F) },
2173 /* 60 */
2174 { PREFIX_TABLE (PREFIX_0F60) },
2175 { PREFIX_TABLE (PREFIX_0F61) },
2176 { PREFIX_TABLE (PREFIX_0F62) },
2177 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2178 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
2179 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
2180 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
2181 { "packuswb", { MX, EM }, PREFIX_OPCODE },
2182 /* 68 */
2183 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
2184 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
2185 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
2186 { "packssdw", { MX, EM }, PREFIX_OPCODE },
2187 { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2188 { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2189 { "movK", { MX, Edq }, PREFIX_OPCODE },
2190 { PREFIX_TABLE (PREFIX_0F6F) },
2191 /* 70 */
2192 { PREFIX_TABLE (PREFIX_0F70) },
2193 { MOD_TABLE (MOD_0F71) },
2194 { MOD_TABLE (MOD_0F72) },
2195 { MOD_TABLE (MOD_0F73) },
2196 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
2197 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
2198 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
2199 { "emms", { XX }, PREFIX_OPCODE },
2200 /* 78 */
2201 { PREFIX_TABLE (PREFIX_0F78) },
2202 { PREFIX_TABLE (PREFIX_0F79) },
2203 { Bad_Opcode },
2204 { Bad_Opcode },
2205 { PREFIX_TABLE (PREFIX_0F7C) },
2206 { PREFIX_TABLE (PREFIX_0F7D) },
2207 { PREFIX_TABLE (PREFIX_0F7E) },
2208 { PREFIX_TABLE (PREFIX_0F7F) },
2209 /* 80 */
2210 { "joH", { Jv, BND, cond_jump_flag }, 0 },
2211 { "jnoH", { Jv, BND, cond_jump_flag }, 0 },
2212 { "jbH", { Jv, BND, cond_jump_flag }, 0 },
2213 { "jaeH", { Jv, BND, cond_jump_flag }, 0 },
2214 { "jeH", { Jv, BND, cond_jump_flag }, 0 },
2215 { "jneH", { Jv, BND, cond_jump_flag }, 0 },
2216 { "jbeH", { Jv, BND, cond_jump_flag }, 0 },
2217 { "jaH", { Jv, BND, cond_jump_flag }, 0 },
2218 /* 88 */
2219 { "jsH", { Jv, BND, cond_jump_flag }, 0 },
2220 { "jnsH", { Jv, BND, cond_jump_flag }, 0 },
2221 { "jpH", { Jv, BND, cond_jump_flag }, 0 },
2222 { "jnpH", { Jv, BND, cond_jump_flag }, 0 },
2223 { "jlH", { Jv, BND, cond_jump_flag }, 0 },
2224 { "jgeH", { Jv, BND, cond_jump_flag }, 0 },
2225 { "jleH", { Jv, BND, cond_jump_flag }, 0 },
2226 { "jgH", { Jv, BND, cond_jump_flag }, 0 },
2227 /* 90 */
2228 { "seto", { Eb }, 0 },
2229 { "setno", { Eb }, 0 },
2230 { "setb", { Eb }, 0 },
2231 { "setae", { Eb }, 0 },
2232 { "sete", { Eb }, 0 },
2233 { "setne", { Eb }, 0 },
2234 { "setbe", { Eb }, 0 },
2235 { "seta", { Eb }, 0 },
2236 /* 98 */
2237 { "sets", { Eb }, 0 },
2238 { "setns", { Eb }, 0 },
2239 { "setp", { Eb }, 0 },
2240 { "setnp", { Eb }, 0 },
2241 { "setl", { Eb }, 0 },
2242 { "setge", { Eb }, 0 },
2243 { "setle", { Eb }, 0 },
2244 { "setg", { Eb }, 0 },
2245 /* a0 */
2246 { "pushP", { fs }, 0 },
2247 { "popP", { fs }, 0 },
2248 { "cpuid", { XX }, 0 },
2249 { "btS", { Ev, Gv }, 0 },
2250 { "shldS", { Ev, Gv, Ib }, 0 },
2251 { "shldS", { Ev, Gv, CL }, 0 },
2252 { REG_TABLE (REG_0FA6) },
2253 { REG_TABLE (REG_0FA7) },
2254 /* a8 */
2255 { "pushP", { gs }, 0 },
2256 { "popP", { gs }, 0 },
2257 { "rsm", { XX }, 0 },
2258 { "btsS", { Evh1, Gv }, 0 },
2259 { "shrdS", { Ev, Gv, Ib }, 0 },
2260 { "shrdS", { Ev, Gv, CL }, 0 },
2261 { REG_TABLE (REG_0FAE) },
2262 { "imulS", { Gv, Ev }, 0 },
2263 /* b0 */
2264 { "cmpxchgB", { Ebh1, Gb }, 0 },
2265 { "cmpxchgS", { Evh1, Gv }, 0 },
2266 { MOD_TABLE (MOD_0FB2) },
2267 { "btrS", { Evh1, Gv }, 0 },
2268 { MOD_TABLE (MOD_0FB4) },
2269 { MOD_TABLE (MOD_0FB5) },
2270 { "movz{bR|x}", { Gv, Eb }, 0 },
2271 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2272 /* b8 */
2273 { PREFIX_TABLE (PREFIX_0FB8) },
2274 { "ud1S", { Gv, Ev }, 0 },
2275 { REG_TABLE (REG_0FBA) },
2276 { "btcS", { Evh1, Gv }, 0 },
2277 { PREFIX_TABLE (PREFIX_0FBC) },
2278 { PREFIX_TABLE (PREFIX_0FBD) },
2279 { "movs{bR|x}", { Gv, Eb }, 0 },
2280 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2281 /* c0 */
2282 { "xaddB", { Ebh1, Gb }, 0 },
2283 { "xaddS", { Evh1, Gv }, 0 },
2284 { PREFIX_TABLE (PREFIX_0FC2) },
2285 { MOD_TABLE (MOD_0FC3) },
2286 { "pinsrw", { MX, Edw, Ib }, PREFIX_OPCODE },
2287 { "pextrw", { Gd, MS, Ib }, PREFIX_OPCODE },
2288 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
2289 { REG_TABLE (REG_0FC7) },
2290 /* c8 */
2291 { "bswap", { RMeAX }, 0 },
2292 { "bswap", { RMeCX }, 0 },
2293 { "bswap", { RMeDX }, 0 },
2294 { "bswap", { RMeBX }, 0 },
2295 { "bswap", { RMeSP }, 0 },
2296 { "bswap", { RMeBP }, 0 },
2297 { "bswap", { RMeSI }, 0 },
2298 { "bswap", { RMeDI }, 0 },
2299 /* d0 */
2300 { PREFIX_TABLE (PREFIX_0FD0) },
2301 { "psrlw", { MX, EM }, PREFIX_OPCODE },
2302 { "psrld", { MX, EM }, PREFIX_OPCODE },
2303 { "psrlq", { MX, EM }, PREFIX_OPCODE },
2304 { "paddq", { MX, EM }, PREFIX_OPCODE },
2305 { "pmullw", { MX, EM }, PREFIX_OPCODE },
2306 { PREFIX_TABLE (PREFIX_0FD6) },
2307 { MOD_TABLE (MOD_0FD7) },
2308 /* d8 */
2309 { "psubusb", { MX, EM }, PREFIX_OPCODE },
2310 { "psubusw", { MX, EM }, PREFIX_OPCODE },
2311 { "pminub", { MX, EM }, PREFIX_OPCODE },
2312 { "pand", { MX, EM }, PREFIX_OPCODE },
2313 { "paddusb", { MX, EM }, PREFIX_OPCODE },
2314 { "paddusw", { MX, EM }, PREFIX_OPCODE },
2315 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
2316 { "pandn", { MX, EM }, PREFIX_OPCODE },
2317 /* e0 */
2318 { "pavgb", { MX, EM }, PREFIX_OPCODE },
2319 { "psraw", { MX, EM }, PREFIX_OPCODE },
2320 { "psrad", { MX, EM }, PREFIX_OPCODE },
2321 { "pavgw", { MX, EM }, PREFIX_OPCODE },
2322 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
2323 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
2324 { PREFIX_TABLE (PREFIX_0FE6) },
2325 { PREFIX_TABLE (PREFIX_0FE7) },
2326 /* e8 */
2327 { "psubsb", { MX, EM }, PREFIX_OPCODE },
2328 { "psubsw", { MX, EM }, PREFIX_OPCODE },
2329 { "pminsw", { MX, EM }, PREFIX_OPCODE },
2330 { "por", { MX, EM }, PREFIX_OPCODE },
2331 { "paddsb", { MX, EM }, PREFIX_OPCODE },
2332 { "paddsw", { MX, EM }, PREFIX_OPCODE },
2333 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
2334 { "pxor", { MX, EM }, PREFIX_OPCODE },
2335 /* f0 */
2336 { PREFIX_TABLE (PREFIX_0FF0) },
2337 { "psllw", { MX, EM }, PREFIX_OPCODE },
2338 { "pslld", { MX, EM }, PREFIX_OPCODE },
2339 { "psllq", { MX, EM }, PREFIX_OPCODE },
2340 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
2341 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
2342 { "psadbw", { MX, EM }, PREFIX_OPCODE },
2343 { PREFIX_TABLE (PREFIX_0FF7) },
2344 /* f8 */
2345 { "psubb", { MX, EM }, PREFIX_OPCODE },
2346 { "psubw", { MX, EM }, PREFIX_OPCODE },
2347 { "psubd", { MX, EM }, PREFIX_OPCODE },
2348 { "psubq", { MX, EM }, PREFIX_OPCODE },
2349 { "paddb", { MX, EM }, PREFIX_OPCODE },
2350 { "paddw", { MX, EM }, PREFIX_OPCODE },
2351 { "paddd", { MX, EM }, PREFIX_OPCODE },
2352 { "ud0S", { Gv, Ev }, 0 },
2353 };
2354
2355 static const bool onebyte_has_modrm[256] = {
2356 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2357 /* ------------------------------- */
2358 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2359 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2360 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2361 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2362 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2363 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2364 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2365 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2366 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2367 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2368 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2369 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2370 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2371 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2372 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2373 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2374 /* ------------------------------- */
2375 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2376 };
2377
2378 static const bool twobyte_has_modrm[256] = {
2379 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2380 /* ------------------------------- */
2381 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2382 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2383 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2384 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2385 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2386 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2387 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2388 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2389 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2390 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2391 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2392 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2393 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2394 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2395 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2396 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2397 /* ------------------------------- */
2398 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2399 };
2400
2401
2402 struct op
2403 {
2404 const char *name;
2405 unsigned int len;
2406 };
2407
2408 /* If we are accessing mod/rm/reg without need_modrm set, then the
2409 values are stale. Hitting this abort likely indicates that you
2410 need to update onebyte_has_modrm or twobyte_has_modrm. */
2411 #define MODRM_CHECK if (!ins->need_modrm) abort ()
2412
2413 static const char *const intel_index16[] = {
2414 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2415 };
2416
2417 static const char *const att_names64[] = {
2418 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2419 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2420 };
2421 static const char *const att_names32[] = {
2422 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2423 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2424 };
2425 static const char *const att_names16[] = {
2426 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2427 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2428 };
2429 static const char *const att_names8[] = {
2430 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2431 };
2432 static const char *const att_names8rex[] = {
2433 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2434 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2435 };
2436 static const char *const att_names_seg[] = {
2437 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2438 };
2439 static const char att_index64[] = "%riz";
2440 static const char att_index32[] = "%eiz";
2441 static const char *const att_index16[] = {
2442 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2443 };
2444
2445 static const char *const att_names_mm[] = {
2446 "%mm0", "%mm1", "%mm2", "%mm3",
2447 "%mm4", "%mm5", "%mm6", "%mm7"
2448 };
2449
2450 static const char *const att_names_bnd[] = {
2451 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2452 };
2453
2454 static const char *const att_names_xmm[] = {
2455 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2456 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2457 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2458 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2459 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2460 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2461 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2462 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2463 };
2464
2465 static const char *const att_names_ymm[] = {
2466 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2467 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2468 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2469 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2470 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2471 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2472 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2473 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2474 };
2475
2476 static const char *const att_names_zmm[] = {
2477 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2478 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2479 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2480 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2481 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2482 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2483 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2484 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2485 };
2486
2487 static const char *const att_names_tmm[] = {
2488 "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2489 "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2490 };
2491
2492 static const char *const att_names_mask[] = {
2493 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2494 };
2495
2496 static const char *const names_rounding[] =
2497 {
2498 "{rn-",
2499 "{rd-",
2500 "{ru-",
2501 "{rz-"
2502 };
2503
2504 static const struct dis386 reg_table[][8] = {
2505 /* REG_80 */
2506 {
2507 { "addA", { Ebh1, Ib }, 0 },
2508 { "orA", { Ebh1, Ib }, 0 },
2509 { "adcA", { Ebh1, Ib }, 0 },
2510 { "sbbA", { Ebh1, Ib }, 0 },
2511 { "andA", { Ebh1, Ib }, 0 },
2512 { "subA", { Ebh1, Ib }, 0 },
2513 { "xorA", { Ebh1, Ib }, 0 },
2514 { "cmpA", { Eb, Ib }, 0 },
2515 },
2516 /* REG_81 */
2517 {
2518 { "addQ", { Evh1, Iv }, 0 },
2519 { "orQ", { Evh1, Iv }, 0 },
2520 { "adcQ", { Evh1, Iv }, 0 },
2521 { "sbbQ", { Evh1, Iv }, 0 },
2522 { "andQ", { Evh1, Iv }, 0 },
2523 { "subQ", { Evh1, Iv }, 0 },
2524 { "xorQ", { Evh1, Iv }, 0 },
2525 { "cmpQ", { Ev, Iv }, 0 },
2526 },
2527 /* REG_83 */
2528 {
2529 { "addQ", { Evh1, sIb }, 0 },
2530 { "orQ", { Evh1, sIb }, 0 },
2531 { "adcQ", { Evh1, sIb }, 0 },
2532 { "sbbQ", { Evh1, sIb }, 0 },
2533 { "andQ", { Evh1, sIb }, 0 },
2534 { "subQ", { Evh1, sIb }, 0 },
2535 { "xorQ", { Evh1, sIb }, 0 },
2536 { "cmpQ", { Ev, sIb }, 0 },
2537 },
2538 /* REG_8F */
2539 {
2540 { "pop{P|}", { stackEv }, 0 },
2541 { XOP_8F_TABLE (XOP_09) },
2542 { Bad_Opcode },
2543 { Bad_Opcode },
2544 { Bad_Opcode },
2545 { XOP_8F_TABLE (XOP_09) },
2546 },
2547 /* REG_C0 */
2548 {
2549 { "rolA", { Eb, Ib }, 0 },
2550 { "rorA", { Eb, Ib }, 0 },
2551 { "rclA", { Eb, Ib }, 0 },
2552 { "rcrA", { Eb, Ib }, 0 },
2553 { "shlA", { Eb, Ib }, 0 },
2554 { "shrA", { Eb, Ib }, 0 },
2555 { "shlA", { Eb, Ib }, 0 },
2556 { "sarA", { Eb, Ib }, 0 },
2557 },
2558 /* REG_C1 */
2559 {
2560 { "rolQ", { Ev, Ib }, 0 },
2561 { "rorQ", { Ev, Ib }, 0 },
2562 { "rclQ", { Ev, Ib }, 0 },
2563 { "rcrQ", { Ev, Ib }, 0 },
2564 { "shlQ", { Ev, Ib }, 0 },
2565 { "shrQ", { Ev, Ib }, 0 },
2566 { "shlQ", { Ev, Ib }, 0 },
2567 { "sarQ", { Ev, Ib }, 0 },
2568 },
2569 /* REG_C6 */
2570 {
2571 { "movA", { Ebh3, Ib }, 0 },
2572 { Bad_Opcode },
2573 { Bad_Opcode },
2574 { Bad_Opcode },
2575 { Bad_Opcode },
2576 { Bad_Opcode },
2577 { Bad_Opcode },
2578 { MOD_TABLE (MOD_C6_REG_7) },
2579 },
2580 /* REG_C7 */
2581 {
2582 { "movQ", { Evh3, Iv }, 0 },
2583 { Bad_Opcode },
2584 { Bad_Opcode },
2585 { Bad_Opcode },
2586 { Bad_Opcode },
2587 { Bad_Opcode },
2588 { Bad_Opcode },
2589 { MOD_TABLE (MOD_C7_REG_7) },
2590 },
2591 /* REG_D0 */
2592 {
2593 { "rolA", { Eb, I1 }, 0 },
2594 { "rorA", { Eb, I1 }, 0 },
2595 { "rclA", { Eb, I1 }, 0 },
2596 { "rcrA", { Eb, I1 }, 0 },
2597 { "shlA", { Eb, I1 }, 0 },
2598 { "shrA", { Eb, I1 }, 0 },
2599 { "shlA", { Eb, I1 }, 0 },
2600 { "sarA", { Eb, I1 }, 0 },
2601 },
2602 /* REG_D1 */
2603 {
2604 { "rolQ", { Ev, I1 }, 0 },
2605 { "rorQ", { Ev, I1 }, 0 },
2606 { "rclQ", { Ev, I1 }, 0 },
2607 { "rcrQ", { Ev, I1 }, 0 },
2608 { "shlQ", { Ev, I1 }, 0 },
2609 { "shrQ", { Ev, I1 }, 0 },
2610 { "shlQ", { Ev, I1 }, 0 },
2611 { "sarQ", { Ev, I1 }, 0 },
2612 },
2613 /* REG_D2 */
2614 {
2615 { "rolA", { Eb, CL }, 0 },
2616 { "rorA", { Eb, CL }, 0 },
2617 { "rclA", { Eb, CL }, 0 },
2618 { "rcrA", { Eb, CL }, 0 },
2619 { "shlA", { Eb, CL }, 0 },
2620 { "shrA", { Eb, CL }, 0 },
2621 { "shlA", { Eb, CL }, 0 },
2622 { "sarA", { Eb, CL }, 0 },
2623 },
2624 /* REG_D3 */
2625 {
2626 { "rolQ", { Ev, CL }, 0 },
2627 { "rorQ", { Ev, CL }, 0 },
2628 { "rclQ", { Ev, CL }, 0 },
2629 { "rcrQ", { Ev, CL }, 0 },
2630 { "shlQ", { Ev, CL }, 0 },
2631 { "shrQ", { Ev, CL }, 0 },
2632 { "shlQ", { Ev, CL }, 0 },
2633 { "sarQ", { Ev, CL }, 0 },
2634 },
2635 /* REG_F6 */
2636 {
2637 { "testA", { Eb, Ib }, 0 },
2638 { "testA", { Eb, Ib }, 0 },
2639 { "notA", { Ebh1 }, 0 },
2640 { "negA", { Ebh1 }, 0 },
2641 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
2642 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
2643 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
2644 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
2645 },
2646 /* REG_F7 */
2647 {
2648 { "testQ", { Ev, Iv }, 0 },
2649 { "testQ", { Ev, Iv }, 0 },
2650 { "notQ", { Evh1 }, 0 },
2651 { "negQ", { Evh1 }, 0 },
2652 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
2653 { "imulQ", { Ev }, 0 },
2654 { "divQ", { Ev }, 0 },
2655 { "idivQ", { Ev }, 0 },
2656 },
2657 /* REG_FE */
2658 {
2659 { "incA", { Ebh1 }, 0 },
2660 { "decA", { Ebh1 }, 0 },
2661 },
2662 /* REG_FF */
2663 {
2664 { "incQ", { Evh1 }, 0 },
2665 { "decQ", { Evh1 }, 0 },
2666 { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2667 { MOD_TABLE (MOD_FF_REG_3) },
2668 { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2669 { MOD_TABLE (MOD_FF_REG_5) },
2670 { "push{P|}", { stackEv }, 0 },
2671 { Bad_Opcode },
2672 },
2673 /* REG_0F00 */
2674 {
2675 { "sldtD", { Sv }, 0 },
2676 { "strD", { Sv }, 0 },
2677 { "lldt", { Ew }, 0 },
2678 { "ltr", { Ew }, 0 },
2679 { "verr", { Ew }, 0 },
2680 { "verw", { Ew }, 0 },
2681 { Bad_Opcode },
2682 { Bad_Opcode },
2683 },
2684 /* REG_0F01 */
2685 {
2686 { MOD_TABLE (MOD_0F01_REG_0) },
2687 { MOD_TABLE (MOD_0F01_REG_1) },
2688 { MOD_TABLE (MOD_0F01_REG_2) },
2689 { MOD_TABLE (MOD_0F01_REG_3) },
2690 { "smswD", { Sv }, 0 },
2691 { MOD_TABLE (MOD_0F01_REG_5) },
2692 { "lmsw", { Ew }, 0 },
2693 { MOD_TABLE (MOD_0F01_REG_7) },
2694 },
2695 /* REG_0F0D */
2696 {
2697 { "prefetch", { Mb }, 0 },
2698 { "prefetchw", { Mb }, 0 },
2699 { "prefetchwt1", { Mb }, 0 },
2700 { "prefetch", { Mb }, 0 },
2701 { "prefetch", { Mb }, 0 },
2702 { "prefetch", { Mb }, 0 },
2703 { "prefetch", { Mb }, 0 },
2704 { "prefetch", { Mb }, 0 },
2705 },
2706 /* REG_0F18 */
2707 {
2708 { MOD_TABLE (MOD_0F18_REG_0) },
2709 { MOD_TABLE (MOD_0F18_REG_1) },
2710 { MOD_TABLE (MOD_0F18_REG_2) },
2711 { MOD_TABLE (MOD_0F18_REG_3) },
2712 { "nopQ", { Ev }, 0 },
2713 { "nopQ", { Ev }, 0 },
2714 { "nopQ", { Ev }, 0 },
2715 { "nopQ", { Ev }, 0 },
2716 },
2717 /* REG_0F1C_P_0_MOD_0 */
2718 {
2719 { "cldemote", { Mb }, 0 },
2720 { "nopQ", { Ev }, 0 },
2721 { "nopQ", { Ev }, 0 },
2722 { "nopQ", { Ev }, 0 },
2723 { "nopQ", { Ev }, 0 },
2724 { "nopQ", { Ev }, 0 },
2725 { "nopQ", { Ev }, 0 },
2726 { "nopQ", { Ev }, 0 },
2727 },
2728 /* REG_0F1E_P_1_MOD_3 */
2729 {
2730 { "nopQ", { Ev }, PREFIX_IGNORED },
2731 { "rdsspK", { Edq }, 0 },
2732 { "nopQ", { Ev }, PREFIX_IGNORED },
2733 { "nopQ", { Ev }, PREFIX_IGNORED },
2734 { "nopQ", { Ev }, PREFIX_IGNORED },
2735 { "nopQ", { Ev }, PREFIX_IGNORED },
2736 { "nopQ", { Ev }, PREFIX_IGNORED },
2737 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2738 },
2739 /* REG_0F38D8_PREFIX_1 */
2740 {
2741 { "aesencwide128kl", { M }, 0 },
2742 { "aesdecwide128kl", { M }, 0 },
2743 { "aesencwide256kl", { M }, 0 },
2744 { "aesdecwide256kl", { M }, 0 },
2745 },
2746 /* REG_0F3A0F_PREFIX_1_MOD_3 */
2747 {
2748 { RM_TABLE (RM_0F3A0F_P_1_MOD_3_REG_0) },
2749 },
2750 /* REG_0F71_MOD_0 */
2751 {
2752 { Bad_Opcode },
2753 { Bad_Opcode },
2754 { "psrlw", { MS, Ib }, PREFIX_OPCODE },
2755 { Bad_Opcode },
2756 { "psraw", { MS, Ib }, PREFIX_OPCODE },
2757 { Bad_Opcode },
2758 { "psllw", { MS, Ib }, PREFIX_OPCODE },
2759 },
2760 /* REG_0F72_MOD_0 */
2761 {
2762 { Bad_Opcode },
2763 { Bad_Opcode },
2764 { "psrld", { MS, Ib }, PREFIX_OPCODE },
2765 { Bad_Opcode },
2766 { "psrad", { MS, Ib }, PREFIX_OPCODE },
2767 { Bad_Opcode },
2768 { "pslld", { MS, Ib }, PREFIX_OPCODE },
2769 },
2770 /* REG_0F73_MOD_0 */
2771 {
2772 { Bad_Opcode },
2773 { Bad_Opcode },
2774 { "psrlq", { MS, Ib }, PREFIX_OPCODE },
2775 { "psrldq", { XS, Ib }, PREFIX_DATA },
2776 { Bad_Opcode },
2777 { Bad_Opcode },
2778 { "psllq", { MS, Ib }, PREFIX_OPCODE },
2779 { "pslldq", { XS, Ib }, PREFIX_DATA },
2780 },
2781 /* REG_0FA6 */
2782 {
2783 { "montmul", { { OP_0f07, 0 } }, 0 },
2784 { "xsha1", { { OP_0f07, 0 } }, 0 },
2785 { "xsha256", { { OP_0f07, 0 } }, 0 },
2786 },
2787 /* REG_0FA7 */
2788 {
2789 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
2790 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
2791 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
2792 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
2793 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
2794 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
2795 },
2796 /* REG_0FAE */
2797 {
2798 { MOD_TABLE (MOD_0FAE_REG_0) },
2799 { MOD_TABLE (MOD_0FAE_REG_1) },
2800 { MOD_TABLE (MOD_0FAE_REG_2) },
2801 { MOD_TABLE (MOD_0FAE_REG_3) },
2802 { MOD_TABLE (MOD_0FAE_REG_4) },
2803 { MOD_TABLE (MOD_0FAE_REG_5) },
2804 { MOD_TABLE (MOD_0FAE_REG_6) },
2805 { MOD_TABLE (MOD_0FAE_REG_7) },
2806 },
2807 /* REG_0FBA */
2808 {
2809 { Bad_Opcode },
2810 { Bad_Opcode },
2811 { Bad_Opcode },
2812 { Bad_Opcode },
2813 { "btQ", { Ev, Ib }, 0 },
2814 { "btsQ", { Evh1, Ib }, 0 },
2815 { "btrQ", { Evh1, Ib }, 0 },
2816 { "btcQ", { Evh1, Ib }, 0 },
2817 },
2818 /* REG_0FC7 */
2819 {
2820 { Bad_Opcode },
2821 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
2822 { Bad_Opcode },
2823 { MOD_TABLE (MOD_0FC7_REG_3) },
2824 { MOD_TABLE (MOD_0FC7_REG_4) },
2825 { MOD_TABLE (MOD_0FC7_REG_5) },
2826 { MOD_TABLE (MOD_0FC7_REG_6) },
2827 { MOD_TABLE (MOD_0FC7_REG_7) },
2828 },
2829 /* REG_VEX_0F71_M_0 */
2830 {
2831 { Bad_Opcode },
2832 { Bad_Opcode },
2833 { "vpsrlw", { Vex, XS, Ib }, PREFIX_DATA },
2834 { Bad_Opcode },
2835 { "vpsraw", { Vex, XS, Ib }, PREFIX_DATA },
2836 { Bad_Opcode },
2837 { "vpsllw", { Vex, XS, Ib }, PREFIX_DATA },
2838 },
2839 /* REG_VEX_0F72_M_0 */
2840 {
2841 { Bad_Opcode },
2842 { Bad_Opcode },
2843 { "vpsrld", { Vex, XS, Ib }, PREFIX_DATA },
2844 { Bad_Opcode },
2845 { "vpsrad", { Vex, XS, Ib }, PREFIX_DATA },
2846 { Bad_Opcode },
2847 { "vpslld", { Vex, XS, Ib }, PREFIX_DATA },
2848 },
2849 /* REG_VEX_0F73_M_0 */
2850 {
2851 { Bad_Opcode },
2852 { Bad_Opcode },
2853 { "vpsrlq", { Vex, XS, Ib }, PREFIX_DATA },
2854 { "vpsrldq", { Vex, XS, Ib }, PREFIX_DATA },
2855 { Bad_Opcode },
2856 { Bad_Opcode },
2857 { "vpsllq", { Vex, XS, Ib }, PREFIX_DATA },
2858 { "vpslldq", { Vex, XS, Ib }, PREFIX_DATA },
2859 },
2860 /* REG_VEX_0FAE */
2861 {
2862 { Bad_Opcode },
2863 { Bad_Opcode },
2864 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
2865 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
2866 },
2867 /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
2868 {
2869 { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
2870 },
2871 /* REG_VEX_0F38F3_L_0 */
2872 {
2873 { Bad_Opcode },
2874 { "blsrS", { VexGdq, Edq }, PREFIX_OPCODE },
2875 { "blsmskS", { VexGdq, Edq }, PREFIX_OPCODE },
2876 { "blsiS", { VexGdq, Edq }, PREFIX_OPCODE },
2877 },
2878 /* REG_XOP_09_01_L_0 */
2879 {
2880 { Bad_Opcode },
2881 { "blcfill", { VexGdq, Edq }, 0 },
2882 { "blsfill", { VexGdq, Edq }, 0 },
2883 { "blcs", { VexGdq, Edq }, 0 },
2884 { "tzmsk", { VexGdq, Edq }, 0 },
2885 { "blcic", { VexGdq, Edq }, 0 },
2886 { "blsic", { VexGdq, Edq }, 0 },
2887 { "t1mskc", { VexGdq, Edq }, 0 },
2888 },
2889 /* REG_XOP_09_02_L_0 */
2890 {
2891 { Bad_Opcode },
2892 { "blcmsk", { VexGdq, Edq }, 0 },
2893 { Bad_Opcode },
2894 { Bad_Opcode },
2895 { Bad_Opcode },
2896 { Bad_Opcode },
2897 { "blci", { VexGdq, Edq }, 0 },
2898 },
2899 /* REG_XOP_09_12_M_1_L_0 */
2900 {
2901 { "llwpcb", { Edq }, 0 },
2902 { "slwpcb", { Edq }, 0 },
2903 },
2904 /* REG_XOP_0A_12_L_0 */
2905 {
2906 { "lwpins", { VexGdq, Ed, Id }, 0 },
2907 { "lwpval", { VexGdq, Ed, Id }, 0 },
2908 },
2909
2910 #include "i386-dis-evex-reg.h"
2911 };
2912
2913 static const struct dis386 prefix_table[][4] = {
2914 /* PREFIX_90 */
2915 {
2916 { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
2917 { "pause", { XX }, 0 },
2918 { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
2919 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
2920 },
2921
2922 /* PREFIX_0F01_REG_1_RM_4 */
2923 {
2924 { Bad_Opcode },
2925 { Bad_Opcode },
2926 { "tdcall", { Skip_MODRM }, 0 },
2927 { Bad_Opcode },
2928 },
2929
2930 /* PREFIX_0F01_REG_1_RM_5 */
2931 {
2932 { Bad_Opcode },
2933 { Bad_Opcode },
2934 { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
2935 { Bad_Opcode },
2936 },
2937
2938 /* PREFIX_0F01_REG_1_RM_6 */
2939 {
2940 { Bad_Opcode },
2941 { Bad_Opcode },
2942 { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
2943 { Bad_Opcode },
2944 },
2945
2946 /* PREFIX_0F01_REG_1_RM_7 */
2947 {
2948 { "encls", { Skip_MODRM }, 0 },
2949 { Bad_Opcode },
2950 { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
2951 { Bad_Opcode },
2952 },
2953
2954 /* PREFIX_0F01_REG_3_RM_1 */
2955 {
2956 { "vmmcall", { Skip_MODRM }, 0 },
2957 { "vmgexit", { Skip_MODRM }, 0 },
2958 { Bad_Opcode },
2959 { "vmgexit", { Skip_MODRM }, 0 },
2960 },
2961
2962 /* PREFIX_0F01_REG_5_MOD_0 */
2963 {
2964 { Bad_Opcode },
2965 { "rstorssp", { Mq }, PREFIX_OPCODE },
2966 },
2967
2968 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
2969 {
2970 { "serialize", { Skip_MODRM }, PREFIX_OPCODE },
2971 { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
2972 { Bad_Opcode },
2973 { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE },
2974 },
2975
2976 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
2977 {
2978 { Bad_Opcode },
2979 { Bad_Opcode },
2980 { Bad_Opcode },
2981 { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE },
2982 },
2983
2984 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
2985 {
2986 { Bad_Opcode },
2987 { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
2988 },
2989
2990 /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
2991 {
2992 { Bad_Opcode },
2993 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) },
2994 },
2995
2996 /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
2997 {
2998 { Bad_Opcode },
2999 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) },
3000 },
3001
3002 /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3003 {
3004 { "rdpkru", { Skip_MODRM }, 0 },
3005 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) },
3006 },
3007
3008 /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3009 {
3010 { "wrpkru", { Skip_MODRM }, 0 },
3011 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) },
3012 },
3013
3014 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3015 {
3016 { "monitorx", { { OP_Monitor, 0 } }, 0 },
3017 { "mcommit", { Skip_MODRM }, 0 },
3018 },
3019
3020 /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3021 {
3022 { "invlpgb", { Skip_MODRM }, 0 },
3023 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) },
3024 { Bad_Opcode },
3025 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) },
3026 },
3027
3028 /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3029 {
3030 { "tlbsync", { Skip_MODRM }, 0 },
3031 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) },
3032 { Bad_Opcode },
3033 { "pvalidate", { Skip_MODRM }, 0 },
3034 },
3035
3036 /* PREFIX_0F09 */
3037 {
3038 { "wbinvd", { XX }, 0 },
3039 { "wbnoinvd", { XX }, 0 },
3040 },
3041
3042 /* PREFIX_0F10 */
3043 {
3044 { "movups", { XM, EXx }, PREFIX_OPCODE },
3045 { "movss", { XM, EXd }, PREFIX_OPCODE },
3046 { "movupd", { XM, EXx }, PREFIX_OPCODE },
3047 { "movsd", { XM, EXq }, PREFIX_OPCODE },
3048 },
3049
3050 /* PREFIX_0F11 */
3051 {
3052 { "movups", { EXxS, XM }, PREFIX_OPCODE },
3053 { "movss", { EXdS, XM }, PREFIX_OPCODE },
3054 { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3055 { "movsd", { EXqS, XM }, PREFIX_OPCODE },
3056 },
3057
3058 /* PREFIX_0F12 */
3059 {
3060 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3061 { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3062 { MOD_TABLE (MOD_0F12_PREFIX_2) },
3063 { "movddup", { XM, EXq }, PREFIX_OPCODE },
3064 },
3065
3066 /* PREFIX_0F16 */
3067 {
3068 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3069 { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3070 { MOD_TABLE (MOD_0F16_PREFIX_2) },
3071 },
3072
3073 /* PREFIX_0F1A */
3074 {
3075 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3076 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3077 { "bndmov", { Gbnd, Ebnd }, 0 },
3078 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3079 },
3080
3081 /* PREFIX_0F1B */
3082 {
3083 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3084 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3085 { "bndmov", { EbndS, Gbnd }, 0 },
3086 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3087 },
3088
3089 /* PREFIX_0F1C */
3090 {
3091 { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3092 { "nopQ", { Ev }, PREFIX_IGNORED },
3093 { "nopQ", { Ev }, 0 },
3094 { "nopQ", { Ev }, PREFIX_IGNORED },
3095 },
3096
3097 /* PREFIX_0F1E */
3098 {
3099 { "nopQ", { Ev }, 0 },
3100 { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3101 { "nopQ", { Ev }, 0 },
3102 { NULL, { XX }, PREFIX_IGNORED },
3103 },
3104
3105 /* PREFIX_0F2A */
3106 {
3107 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3108 { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3109 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3110 { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3111 },
3112
3113 /* PREFIX_0F2B */
3114 {
3115 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3116 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3117 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3118 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3119 },
3120
3121 /* PREFIX_0F2C */
3122 {
3123 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3124 { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3125 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3126 { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3127 },
3128
3129 /* PREFIX_0F2D */
3130 {
3131 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3132 { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3133 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3134 { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3135 },
3136
3137 /* PREFIX_0F2E */
3138 {
3139 { "ucomiss",{ XM, EXd }, 0 },
3140 { Bad_Opcode },
3141 { "ucomisd",{ XM, EXq }, 0 },
3142 },
3143
3144 /* PREFIX_0F2F */
3145 {
3146 { "comiss", { XM, EXd }, 0 },
3147 { Bad_Opcode },
3148 { "comisd", { XM, EXq }, 0 },
3149 },
3150
3151 /* PREFIX_0F51 */
3152 {
3153 { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3154 { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3155 { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3156 { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3157 },
3158
3159 /* PREFIX_0F52 */
3160 {
3161 { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3162 { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3163 },
3164
3165 /* PREFIX_0F53 */
3166 {
3167 { "rcpps", { XM, EXx }, PREFIX_OPCODE },
3168 { "rcpss", { XM, EXd }, PREFIX_OPCODE },
3169 },
3170
3171 /* PREFIX_0F58 */
3172 {
3173 { "addps", { XM, EXx }, PREFIX_OPCODE },
3174 { "addss", { XM, EXd }, PREFIX_OPCODE },
3175 { "addpd", { XM, EXx }, PREFIX_OPCODE },
3176 { "addsd", { XM, EXq }, PREFIX_OPCODE },
3177 },
3178
3179 /* PREFIX_0F59 */
3180 {
3181 { "mulps", { XM, EXx }, PREFIX_OPCODE },
3182 { "mulss", { XM, EXd }, PREFIX_OPCODE },
3183 { "mulpd", { XM, EXx }, PREFIX_OPCODE },
3184 { "mulsd", { XM, EXq }, PREFIX_OPCODE },
3185 },
3186
3187 /* PREFIX_0F5A */
3188 {
3189 { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3190 { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3191 { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3192 { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3193 },
3194
3195 /* PREFIX_0F5B */
3196 {
3197 { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3198 { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3199 { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3200 },
3201
3202 /* PREFIX_0F5C */
3203 {
3204 { "subps", { XM, EXx }, PREFIX_OPCODE },
3205 { "subss", { XM, EXd }, PREFIX_OPCODE },
3206 { "subpd", { XM, EXx }, PREFIX_OPCODE },
3207 { "subsd", { XM, EXq }, PREFIX_OPCODE },
3208 },
3209
3210 /* PREFIX_0F5D */
3211 {
3212 { "minps", { XM, EXx }, PREFIX_OPCODE },
3213 { "minss", { XM, EXd }, PREFIX_OPCODE },
3214 { "minpd", { XM, EXx }, PREFIX_OPCODE },
3215 { "minsd", { XM, EXq }, PREFIX_OPCODE },
3216 },
3217
3218 /* PREFIX_0F5E */
3219 {
3220 { "divps", { XM, EXx }, PREFIX_OPCODE },
3221 { "divss", { XM, EXd }, PREFIX_OPCODE },
3222 { "divpd", { XM, EXx }, PREFIX_OPCODE },
3223 { "divsd", { XM, EXq }, PREFIX_OPCODE },
3224 },
3225
3226 /* PREFIX_0F5F */
3227 {
3228 { "maxps", { XM, EXx }, PREFIX_OPCODE },
3229 { "maxss", { XM, EXd }, PREFIX_OPCODE },
3230 { "maxpd", { XM, EXx }, PREFIX_OPCODE },
3231 { "maxsd", { XM, EXq }, PREFIX_OPCODE },
3232 },
3233
3234 /* PREFIX_0F60 */
3235 {
3236 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3237 { Bad_Opcode },
3238 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3239 },
3240
3241 /* PREFIX_0F61 */
3242 {
3243 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3244 { Bad_Opcode },
3245 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3246 },
3247
3248 /* PREFIX_0F62 */
3249 {
3250 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3251 { Bad_Opcode },
3252 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3253 },
3254
3255 /* PREFIX_0F6F */
3256 {
3257 { "movq", { MX, EM }, PREFIX_OPCODE },
3258 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3259 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3260 },
3261
3262 /* PREFIX_0F70 */
3263 {
3264 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3265 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3266 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3267 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3268 },
3269
3270 /* PREFIX_0F78 */
3271 {
3272 {"vmread", { Em, Gm }, 0 },
3273 { Bad_Opcode },
3274 {"extrq", { XS, Ib, Ib }, 0 },
3275 {"insertq", { XM, XS, Ib, Ib }, 0 },
3276 },
3277
3278 /* PREFIX_0F79 */
3279 {
3280 {"vmwrite", { Gm, Em }, 0 },
3281 { Bad_Opcode },
3282 {"extrq", { XM, XS }, 0 },
3283 {"insertq", { XM, XS }, 0 },
3284 },
3285
3286 /* PREFIX_0F7C */
3287 {
3288 { Bad_Opcode },
3289 { Bad_Opcode },
3290 { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3291 { "haddps", { XM, EXx }, PREFIX_OPCODE },
3292 },
3293
3294 /* PREFIX_0F7D */
3295 {
3296 { Bad_Opcode },
3297 { Bad_Opcode },
3298 { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3299 { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3300 },
3301
3302 /* PREFIX_0F7E */
3303 {
3304 { "movK", { Edq, MX }, PREFIX_OPCODE },
3305 { "movq", { XM, EXq }, PREFIX_OPCODE },
3306 { "movK", { Edq, XM }, PREFIX_OPCODE },
3307 },
3308
3309 /* PREFIX_0F7F */
3310 {
3311 { "movq", { EMS, MX }, PREFIX_OPCODE },
3312 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3313 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3314 },
3315
3316 /* PREFIX_0FAE_REG_0_MOD_3 */
3317 {
3318 { Bad_Opcode },
3319 { "rdfsbase", { Ev }, 0 },
3320 },
3321
3322 /* PREFIX_0FAE_REG_1_MOD_3 */
3323 {
3324 { Bad_Opcode },
3325 { "rdgsbase", { Ev }, 0 },
3326 },
3327
3328 /* PREFIX_0FAE_REG_2_MOD_3 */
3329 {
3330 { Bad_Opcode },
3331 { "wrfsbase", { Ev }, 0 },
3332 },
3333
3334 /* PREFIX_0FAE_REG_3_MOD_3 */
3335 {
3336 { Bad_Opcode },
3337 { "wrgsbase", { Ev }, 0 },
3338 },
3339
3340 /* PREFIX_0FAE_REG_4_MOD_0 */
3341 {
3342 { "xsave", { FXSAVE }, 0 },
3343 { "ptwrite{%LQ|}", { Edq }, 0 },
3344 },
3345
3346 /* PREFIX_0FAE_REG_4_MOD_3 */
3347 {
3348 { Bad_Opcode },
3349 { "ptwrite{%LQ|}", { Edq }, 0 },
3350 },
3351
3352 /* PREFIX_0FAE_REG_5_MOD_3 */
3353 {
3354 { "lfence", { Skip_MODRM }, 0 },
3355 { "incsspK", { Edq }, PREFIX_OPCODE },
3356 },
3357
3358 /* PREFIX_0FAE_REG_6_MOD_0 */
3359 {
3360 { "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
3361 { "clrssbsy", { Mq }, PREFIX_OPCODE },
3362 { "clwb", { Mb }, PREFIX_OPCODE },
3363 },
3364
3365 /* PREFIX_0FAE_REG_6_MOD_3 */
3366 {
3367 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3368 { "umonitor", { Eva }, PREFIX_OPCODE },
3369 { "tpause", { Edq }, PREFIX_OPCODE },
3370 { "umwait", { Edq }, PREFIX_OPCODE },
3371 },
3372
3373 /* PREFIX_0FAE_REG_7_MOD_0 */
3374 {
3375 { "clflush", { Mb }, 0 },
3376 { Bad_Opcode },
3377 { "clflushopt", { Mb }, 0 },
3378 },
3379
3380 /* PREFIX_0FB8 */
3381 {
3382 { Bad_Opcode },
3383 { "popcntS", { Gv, Ev }, 0 },
3384 },
3385
3386 /* PREFIX_0FBC */
3387 {
3388 { "bsfS", { Gv, Ev }, 0 },
3389 { "tzcntS", { Gv, Ev }, 0 },
3390 { "bsfS", { Gv, Ev }, 0 },
3391 },
3392
3393 /* PREFIX_0FBD */
3394 {
3395 { "bsrS", { Gv, Ev }, 0 },
3396 { "lzcntS", { Gv, Ev }, 0 },
3397 { "bsrS", { Gv, Ev }, 0 },
3398 },
3399
3400 /* PREFIX_0FC2 */
3401 {
3402 { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE },
3403 { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE },
3404 { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE },
3405 { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
3406 },
3407
3408 /* PREFIX_0FC7_REG_6_MOD_0 */
3409 {
3410 { "vmptrld",{ Mq }, 0 },
3411 { "vmxon", { Mq }, 0 },
3412 { "vmclear",{ Mq }, 0 },
3413 },
3414
3415 /* PREFIX_0FC7_REG_6_MOD_3 */
3416 {
3417 { "rdrand", { Ev }, 0 },
3418 { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) },
3419 { "rdrand", { Ev }, 0 }
3420 },
3421
3422 /* PREFIX_0FC7_REG_7_MOD_3 */
3423 {
3424 { "rdseed", { Ev }, 0 },
3425 { "rdpid", { Em }, 0 },
3426 { "rdseed", { Ev }, 0 },
3427 },
3428
3429 /* PREFIX_0FD0 */
3430 {
3431 { Bad_Opcode },
3432 { Bad_Opcode },
3433 { "addsubpd", { XM, EXx }, 0 },
3434 { "addsubps", { XM, EXx }, 0 },
3435 },
3436
3437 /* PREFIX_0FD6 */
3438 {
3439 { Bad_Opcode },
3440 { "movq2dq",{ XM, MS }, 0 },
3441 { "movq", { EXqS, XM }, 0 },
3442 { "movdq2q",{ MX, XS }, 0 },
3443 },
3444
3445 /* PREFIX_0FE6 */
3446 {
3447 { Bad_Opcode },
3448 { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3449 { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3450 { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3451 },
3452
3453 /* PREFIX_0FE7 */
3454 {
3455 { "movntq", { Mq, MX }, PREFIX_OPCODE },
3456 { Bad_Opcode },
3457 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3458 },
3459
3460 /* PREFIX_0FF0 */
3461 {
3462 { Bad_Opcode },
3463 { Bad_Opcode },
3464 { Bad_Opcode },
3465 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3466 },
3467
3468 /* PREFIX_0FF7 */
3469 {
3470 { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3471 { Bad_Opcode },
3472 { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3473 },
3474
3475 /* PREFIX_0F38D8 */
3476 {
3477 { Bad_Opcode },
3478 { REG_TABLE (REG_0F38D8_PREFIX_1) },
3479 },
3480
3481 /* PREFIX_0F38DC */
3482 {
3483 { Bad_Opcode },
3484 { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3485 { "aesenc", { XM, EXx }, 0 },
3486 },
3487
3488 /* PREFIX_0F38DD */
3489 {
3490 { Bad_Opcode },
3491 { MOD_TABLE (MOD_0F38DD_PREFIX_1) },
3492 { "aesenclast", { XM, EXx }, 0 },
3493 },
3494
3495 /* PREFIX_0F38DE */
3496 {
3497 { Bad_Opcode },
3498 { MOD_TABLE (MOD_0F38DE_PREFIX_1) },
3499 { "aesdec", { XM, EXx }, 0 },
3500 },
3501
3502 /* PREFIX_0F38DF */
3503 {
3504 { Bad_Opcode },
3505 { MOD_TABLE (MOD_0F38DF_PREFIX_1) },
3506 { "aesdeclast", { XM, EXx }, 0 },
3507 },
3508
3509 /* PREFIX_0F38F0 */
3510 {
3511 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3512 { Bad_Opcode },
3513 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3514 { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3515 },
3516
3517 /* PREFIX_0F38F1 */
3518 {
3519 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3520 { Bad_Opcode },
3521 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3522 { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3523 },
3524
3525 /* PREFIX_0F38F6 */
3526 {
3527 { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
3528 { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
3529 { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
3530 { Bad_Opcode },
3531 },
3532
3533 /* PREFIX_0F38F8 */
3534 {
3535 { Bad_Opcode },
3536 { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
3537 { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
3538 { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
3539 },
3540 /* PREFIX_0F38FA */
3541 {
3542 { Bad_Opcode },
3543 { MOD_TABLE (MOD_0F38FA_PREFIX_1) },
3544 },
3545
3546 /* PREFIX_0F38FB */
3547 {
3548 { Bad_Opcode },
3549 { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
3550 },
3551
3552 /* PREFIX_0F3A0F */
3553 {
3554 { Bad_Opcode },
3555 { MOD_TABLE (MOD_0F3A0F_PREFIX_1)},
3556 },
3557
3558 /* PREFIX_VEX_0F10 */
3559 {
3560 { "vmovupX", { XM, EXEvexXNoBcst }, PREFIX_OPCODE },
3561 { "vmovs%XS", { XMScalar, VexScalarR, EXd }, 0 },
3562 { "vmovupX", { XM, EXEvexXNoBcst }, PREFIX_OPCODE },
3563 { "vmovs%XD", { XMScalar, VexScalarR, EXq }, 0 },
3564 },
3565
3566 /* PREFIX_VEX_0F11 */
3567 {
3568 { "vmovupX", { EXxS, XM }, PREFIX_OPCODE },
3569 { "vmovs%XS", { EXdS, VexScalarR, XMScalar }, 0 },
3570 { "vmovupX", { EXxS, XM }, PREFIX_OPCODE },
3571 { "vmovs%XD", { EXqS, VexScalarR, XMScalar }, 0 },
3572 },
3573
3574 /* PREFIX_VEX_0F12 */
3575 {
3576 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3577 { "vmov%XSldup", { XM, EXEvexXNoBcst }, 0 },
3578 { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
3579 { "vmov%XDdup", { XM, EXymmq }, 0 },
3580 },
3581
3582 /* PREFIX_VEX_0F16 */
3583 {
3584 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3585 { "vmov%XShdup", { XM, EXEvexXNoBcst }, 0 },
3586 { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
3587 },
3588
3589 /* PREFIX_VEX_0F2A */
3590 {
3591 { Bad_Opcode },
3592 { "vcvtsi2ss{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
3593 { Bad_Opcode },
3594 { "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
3595 },
3596
3597 /* PREFIX_VEX_0F2C */
3598 {
3599 { Bad_Opcode },
3600 { "vcvttss2si", { Gdq, EXd, EXxEVexS }, 0 },
3601 { Bad_Opcode },
3602 { "vcvttsd2si", { Gdq, EXq, EXxEVexS }, 0 },
3603 },
3604
3605 /* PREFIX_VEX_0F2D */
3606 {
3607 { Bad_Opcode },
3608 { "vcvtss2si", { Gdq, EXd, EXxEVexR }, 0 },
3609 { Bad_Opcode },
3610 { "vcvtsd2si", { Gdq, EXq, EXxEVexR }, 0 },
3611 },
3612
3613 /* PREFIX_VEX_0F2E */
3614 {
3615 { "vucomisX", { XMScalar, EXd, EXxEVexS }, PREFIX_OPCODE },
3616 { Bad_Opcode },
3617 { "vucomisX", { XMScalar, EXq, EXxEVexS }, PREFIX_OPCODE },
3618 },
3619
3620 /* PREFIX_VEX_0F2F */
3621 {
3622 { "vcomisX", { XMScalar, EXd, EXxEVexS }, PREFIX_OPCODE },
3623 { Bad_Opcode },
3624 { "vcomisX", { XMScalar, EXq, EXxEVexS }, PREFIX_OPCODE },
3625 },
3626
3627 /* PREFIX_VEX_0F41_L_1_M_1_W_0 */
3628 {
3629 { "kandw", { MaskG, MaskVex, MaskE }, 0 },
3630 { Bad_Opcode },
3631 { "kandb", { MaskG, MaskVex, MaskE }, 0 },
3632 },
3633
3634 /* PREFIX_VEX_0F41_L_1_M_1_W_1 */
3635 {
3636 { "kandq", { MaskG, MaskVex, MaskE }, 0 },
3637 { Bad_Opcode },
3638 { "kandd", { MaskG, MaskVex, MaskE }, 0 },
3639 },
3640
3641 /* PREFIX_VEX_0F42_L_1_M_1_W_0 */
3642 {
3643 { "kandnw", { MaskG, MaskVex, MaskE }, 0 },
3644 { Bad_Opcode },
3645 { "kandnb", { MaskG, MaskVex, MaskE }, 0 },
3646 },
3647
3648 /* PREFIX_VEX_0F42_L_1_M_1_W_1 */
3649 {
3650 { "kandnq", { MaskG, MaskVex, MaskE }, 0 },
3651 { Bad_Opcode },
3652 { "kandnd", { MaskG, MaskVex, MaskE }, 0 },
3653 },
3654
3655 /* PREFIX_VEX_0F44_L_0_M_1_W_0 */
3656 {
3657 { "knotw", { MaskG, MaskE }, 0 },
3658 { Bad_Opcode },
3659 { "knotb", { MaskG, MaskE }, 0 },
3660 },
3661
3662 /* PREFIX_VEX_0F44_L_0_M_1_W_1 */
3663 {
3664 { "knotq", { MaskG, MaskE }, 0 },
3665 { Bad_Opcode },
3666 { "knotd", { MaskG, MaskE }, 0 },
3667 },
3668
3669 /* PREFIX_VEX_0F45_L_1_M_1_W_0 */
3670 {
3671 { "korw", { MaskG, MaskVex, MaskE }, 0 },
3672 { Bad_Opcode },
3673 { "korb", { MaskG, MaskVex, MaskE }, 0 },
3674 },
3675
3676 /* PREFIX_VEX_0F45_L_1_M_1_W_1 */
3677 {
3678 { "korq", { MaskG, MaskVex, MaskE }, 0 },
3679 { Bad_Opcode },
3680 { "kord", { MaskG, MaskVex, MaskE }, 0 },
3681 },
3682
3683 /* PREFIX_VEX_0F46_L_1_M_1_W_0 */
3684 {
3685 { "kxnorw", { MaskG, MaskVex, MaskE }, 0 },
3686 { Bad_Opcode },
3687 { "kxnorb", { MaskG, MaskVex, MaskE }, 0 },
3688 },
3689
3690 /* PREFIX_VEX_0F46_L_1_M_1_W_1 */
3691 {
3692 { "kxnorq", { MaskG, MaskVex, MaskE }, 0 },
3693 { Bad_Opcode },
3694 { "kxnord", { MaskG, MaskVex, MaskE }, 0 },
3695 },
3696
3697 /* PREFIX_VEX_0F47_L_1_M_1_W_0 */
3698 {
3699 { "kxorw", { MaskG, MaskVex, MaskE }, 0 },
3700 { Bad_Opcode },
3701 { "kxorb", { MaskG, MaskVex, MaskE }, 0 },
3702 },
3703
3704 /* PREFIX_VEX_0F47_L_1_M_1_W_1 */
3705 {
3706 { "kxorq", { MaskG, MaskVex, MaskE }, 0 },
3707 { Bad_Opcode },
3708 { "kxord", { MaskG, MaskVex, MaskE }, 0 },
3709 },
3710
3711 /* PREFIX_VEX_0F4A_L_1_M_1_W_0 */
3712 {
3713 { "kaddw", { MaskG, MaskVex, MaskE }, 0 },
3714 { Bad_Opcode },
3715 { "kaddb", { MaskG, MaskVex, MaskE }, 0 },
3716 },
3717
3718 /* PREFIX_VEX_0F4A_L_1_M_1_W_1 */
3719 {
3720 { "kaddq", { MaskG, MaskVex, MaskE }, 0 },
3721 { Bad_Opcode },
3722 { "kaddd", { MaskG, MaskVex, MaskE }, 0 },
3723 },
3724
3725 /* PREFIX_VEX_0F4B_L_1_M_1_W_0 */
3726 {
3727 { "kunpckwd", { MaskG, MaskVex, MaskE }, 0 },
3728 { Bad_Opcode },
3729 { "kunpckbw", { MaskG, MaskVex, MaskE }, 0 },
3730 },
3731
3732 /* PREFIX_VEX_0F4B_L_1_M_1_W_1 */
3733 {
3734 { "kunpckdq", { MaskG, MaskVex, MaskE }, 0 },
3735 },
3736
3737 /* PREFIX_VEX_0F51 */
3738 {
3739 { "vsqrtpX", { XM, EXx, EXxEVexR }, PREFIX_OPCODE },
3740 { "vsqrts%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3741 { "vsqrtpX", { XM, EXx, EXxEVexR }, PREFIX_OPCODE },
3742 { "vsqrts%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3743 },
3744
3745 /* PREFIX_VEX_0F52 */
3746 {
3747 { "vrsqrtps", { XM, EXx }, 0 },
3748 { "vrsqrtss", { XMScalar, VexScalar, EXd }, 0 },
3749 },
3750
3751 /* PREFIX_VEX_0F53 */
3752 {
3753 { "vrcpps", { XM, EXx }, 0 },
3754 { "vrcpss", { XMScalar, VexScalar, EXd }, 0 },
3755 },
3756
3757 /* PREFIX_VEX_0F58 */
3758 {
3759 { "vaddpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3760 { "vadds%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3761 { "vaddpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3762 { "vadds%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3763 },
3764
3765 /* PREFIX_VEX_0F59 */
3766 {
3767 { "vmulpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3768 { "vmuls%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3769 { "vmulpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3770 { "vmuls%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3771 },
3772
3773 /* PREFIX_VEX_0F5A */
3774 {
3775 { "vcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
3776 { "vcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3777 { "vcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
3778 { "vcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3779 },
3780
3781 /* PREFIX_VEX_0F5B */
3782 {
3783 { "vcvtdq2ps", { XM, EXx }, 0 },
3784 { "vcvttps2dq", { XM, EXx }, 0 },
3785 { "vcvtps2dq", { XM, EXx }, 0 },
3786 },
3787
3788 /* PREFIX_VEX_0F5C */
3789 {
3790 { "vsubpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3791 { "vsubs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3792 { "vsubpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3793 { "vsubs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3794 },
3795
3796 /* PREFIX_VEX_0F5D */
3797 {
3798 { "vminpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
3799 { "vmins%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3800 { "vminpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
3801 { "vmins%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3802 },
3803
3804 /* PREFIX_VEX_0F5E */
3805 {
3806 { "vdivpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3807 { "vdivs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3808 { "vdivpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3809 { "vdivs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3810 },
3811
3812 /* PREFIX_VEX_0F5F */
3813 {
3814 { "vmaxpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
3815 { "vmaxs%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3816 { "vmaxpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
3817 { "vmaxs%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3818 },
3819
3820 /* PREFIX_VEX_0F6F */
3821 {
3822 { Bad_Opcode },
3823 { "vmovdqu", { XM, EXx }, 0 },
3824 { "vmovdqa", { XM, EXx }, 0 },
3825 },
3826
3827 /* PREFIX_VEX_0F70 */
3828 {
3829 { Bad_Opcode },
3830 { "vpshufhw", { XM, EXx, Ib }, 0 },
3831 { "vpshufd", { XM, EXx, Ib }, 0 },
3832 { "vpshuflw", { XM, EXx, Ib }, 0 },
3833 },
3834
3835 /* PREFIX_VEX_0F7C */
3836 {
3837 { Bad_Opcode },
3838 { Bad_Opcode },
3839 { "vhaddpd", { XM, Vex, EXx }, 0 },
3840 { "vhaddps", { XM, Vex, EXx }, 0 },
3841 },
3842
3843 /* PREFIX_VEX_0F7D */
3844 {
3845 { Bad_Opcode },
3846 { Bad_Opcode },
3847 { "vhsubpd", { XM, Vex, EXx }, 0 },
3848 { "vhsubps", { XM, Vex, EXx }, 0 },
3849 },
3850
3851 /* PREFIX_VEX_0F7E */
3852 {
3853 { Bad_Opcode },
3854 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3855 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3856 },
3857
3858 /* PREFIX_VEX_0F7F */
3859 {
3860 { Bad_Opcode },
3861 { "vmovdqu", { EXxS, XM }, 0 },
3862 { "vmovdqa", { EXxS, XM }, 0 },
3863 },
3864
3865 /* PREFIX_VEX_0F90_L_0_W_0 */
3866 {
3867 { "kmovw", { MaskG, MaskE }, 0 },
3868 { Bad_Opcode },
3869 { "kmovb", { MaskG, MaskBDE }, 0 },
3870 },
3871
3872 /* PREFIX_VEX_0F90_L_0_W_1 */
3873 {
3874 { "kmovq", { MaskG, MaskE }, 0 },
3875 { Bad_Opcode },
3876 { "kmovd", { MaskG, MaskBDE }, 0 },
3877 },
3878
3879 /* PREFIX_VEX_0F91_L_0_M_0_W_0 */
3880 {
3881 { "kmovw", { Ew, MaskG }, 0 },
3882 { Bad_Opcode },
3883 { "kmovb", { Eb, MaskG }, 0 },
3884 },
3885
3886 /* PREFIX_VEX_0F91_L_0_M_0_W_1 */
3887 {
3888 { "kmovq", { Eq, MaskG }, 0 },
3889 { Bad_Opcode },
3890 { "kmovd", { Ed, MaskG }, 0 },
3891 },
3892
3893 /* PREFIX_VEX_0F92_L_0_M_1_W_0 */
3894 {
3895 { "kmovw", { MaskG, Edq }, 0 },
3896 { Bad_Opcode },
3897 { "kmovb", { MaskG, Edq }, 0 },
3898 { "kmovd", { MaskG, Edq }, 0 },
3899 },
3900
3901 /* PREFIX_VEX_0F92_L_0_M_1_W_1 */
3902 {
3903 { Bad_Opcode },
3904 { Bad_Opcode },
3905 { Bad_Opcode },
3906 { "kmovK", { MaskG, Edq }, 0 },
3907 },
3908
3909 /* PREFIX_VEX_0F93_L_0_M_1_W_0 */
3910 {
3911 { "kmovw", { Gdq, MaskE }, 0 },
3912 { Bad_Opcode },
3913 { "kmovb", { Gdq, MaskE }, 0 },
3914 { "kmovd", { Gdq, MaskE }, 0 },
3915 },
3916
3917 /* PREFIX_VEX_0F93_L_0_M_1_W_1 */
3918 {
3919 { Bad_Opcode },
3920 { Bad_Opcode },
3921 { Bad_Opcode },
3922 { "kmovK", { Gdq, MaskE }, 0 },
3923 },
3924
3925 /* PREFIX_VEX_0F98_L_0_M_1_W_0 */
3926 {
3927 { "kortestw", { MaskG, MaskE }, 0 },
3928 { Bad_Opcode },
3929 { "kortestb", { MaskG, MaskE }, 0 },
3930 },
3931
3932 /* PREFIX_VEX_0F98_L_0_M_1_W_1 */
3933 {
3934 { "kortestq", { MaskG, MaskE }, 0 },
3935 { Bad_Opcode },
3936 { "kortestd", { MaskG, MaskE }, 0 },
3937 },
3938
3939 /* PREFIX_VEX_0F99_L_0_M_1_W_0 */
3940 {
3941 { "ktestw", { MaskG, MaskE }, 0 },
3942 { Bad_Opcode },
3943 { "ktestb", { MaskG, MaskE }, 0 },
3944 },
3945
3946 /* PREFIX_VEX_0F99_L_0_M_1_W_1 */
3947 {
3948 { "ktestq", { MaskG, MaskE }, 0 },
3949 { Bad_Opcode },
3950 { "ktestd", { MaskG, MaskE }, 0 },
3951 },
3952
3953 /* PREFIX_VEX_0FC2 */
3954 {
3955 { "vcmpps", { XM, Vex, EXx, CMP }, 0 },
3956 { "vcmpss", { XMScalar, VexScalar, EXd, CMP }, 0 },
3957 { "vcmppd", { XM, Vex, EXx, CMP }, 0 },
3958 { "vcmpsd", { XMScalar, VexScalar, EXq, CMP }, 0 },
3959 },
3960
3961 /* PREFIX_VEX_0FD0 */
3962 {
3963 { Bad_Opcode },
3964 { Bad_Opcode },
3965 { "vaddsubpd", { XM, Vex, EXx }, 0 },
3966 { "vaddsubps", { XM, Vex, EXx }, 0 },
3967 },
3968
3969 /* PREFIX_VEX_0FE6 */
3970 {
3971 { Bad_Opcode },
3972 { "vcvtdq2pd", { XM, EXxmmq }, 0 },
3973 { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
3974 { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
3975 },
3976
3977 /* PREFIX_VEX_0FF0 */
3978 {
3979 { Bad_Opcode },
3980 { Bad_Opcode },
3981 { Bad_Opcode },
3982 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
3983 },
3984
3985 /* PREFIX_VEX_0F3849_X86_64 */
3986 {
3987 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
3988 { Bad_Opcode },
3989 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
3990 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
3991 },
3992
3993 /* PREFIX_VEX_0F384B_X86_64 */
3994 {
3995 { Bad_Opcode },
3996 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
3997 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
3998 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
3999 },
4000
4001 /* PREFIX_VEX_0F385C_X86_64 */
4002 {
4003 { Bad_Opcode },
4004 { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
4005 { Bad_Opcode },
4006 },
4007
4008 /* PREFIX_VEX_0F385E_X86_64 */
4009 {
4010 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
4011 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
4012 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
4013 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
4014 },
4015
4016 /* PREFIX_VEX_0F38F5_L_0 */
4017 {
4018 { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
4019 { "pextS", { Gdq, VexGdq, Edq }, 0 },
4020 { Bad_Opcode },
4021 { "pdepS", { Gdq, VexGdq, Edq }, 0 },
4022 },
4023
4024 /* PREFIX_VEX_0F38F6_L_0 */
4025 {
4026 { Bad_Opcode },
4027 { Bad_Opcode },
4028 { Bad_Opcode },
4029 { "mulxS", { Gdq, VexGdq, Edq }, 0 },
4030 },
4031
4032 /* PREFIX_VEX_0F38F7_L_0 */
4033 {
4034 { "bextrS", { Gdq, Edq, VexGdq }, 0 },
4035 { "sarxS", { Gdq, Edq, VexGdq }, 0 },
4036 { "shlxS", { Gdq, Edq, VexGdq }, 0 },
4037 { "shrxS", { Gdq, Edq, VexGdq }, 0 },
4038 },
4039
4040 /* PREFIX_VEX_0F3AF0_L_0 */
4041 {
4042 { Bad_Opcode },
4043 { Bad_Opcode },
4044 { Bad_Opcode },
4045 { "rorxS", { Gdq, Edq, Ib }, 0 },
4046 },
4047
4048 #include "i386-dis-evex-prefix.h"
4049 };
4050
4051 static const struct dis386 x86_64_table[][2] = {
4052 /* X86_64_06 */
4053 {
4054 { "pushP", { es }, 0 },
4055 },
4056
4057 /* X86_64_07 */
4058 {
4059 { "popP", { es }, 0 },
4060 },
4061
4062 /* X86_64_0E */
4063 {
4064 { "pushP", { cs }, 0 },
4065 },
4066
4067 /* X86_64_16 */
4068 {
4069 { "pushP", { ss }, 0 },
4070 },
4071
4072 /* X86_64_17 */
4073 {
4074 { "popP", { ss }, 0 },
4075 },
4076
4077 /* X86_64_1E */
4078 {
4079 { "pushP", { ds }, 0 },
4080 },
4081
4082 /* X86_64_1F */
4083 {
4084 { "popP", { ds }, 0 },
4085 },
4086
4087 /* X86_64_27 */
4088 {
4089 { "daa", { XX }, 0 },
4090 },
4091
4092 /* X86_64_2F */
4093 {
4094 { "das", { XX }, 0 },
4095 },
4096
4097 /* X86_64_37 */
4098 {
4099 { "aaa", { XX }, 0 },
4100 },
4101
4102 /* X86_64_3F */
4103 {
4104 { "aas", { XX }, 0 },
4105 },
4106
4107 /* X86_64_60 */
4108 {
4109 { "pushaP", { XX }, 0 },
4110 },
4111
4112 /* X86_64_61 */
4113 {
4114 { "popaP", { XX }, 0 },
4115 },
4116
4117 /* X86_64_62 */
4118 {
4119 { MOD_TABLE (MOD_62_32BIT) },
4120 { EVEX_TABLE (EVEX_0F) },
4121 },
4122
4123 /* X86_64_63 */
4124 {
4125 { "arpl", { Ew, Gw }, 0 },
4126 { "movs", { Gv, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4127 },
4128
4129 /* X86_64_6D */
4130 {
4131 { "ins{R|}", { Yzr, indirDX }, 0 },
4132 { "ins{G|}", { Yzr, indirDX }, 0 },
4133 },
4134
4135 /* X86_64_6F */
4136 {
4137 { "outs{R|}", { indirDXr, Xz }, 0 },
4138 { "outs{G|}", { indirDXr, Xz }, 0 },
4139 },
4140
4141 /* X86_64_82 */
4142 {
4143 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
4144 { REG_TABLE (REG_80) },
4145 },
4146
4147 /* X86_64_9A */
4148 {
4149 { "{l|}call{P|}", { Ap }, 0 },
4150 },
4151
4152 /* X86_64_C2 */
4153 {
4154 { "retP", { Iw, BND }, 0 },
4155 { "ret@", { Iw, BND }, 0 },
4156 },
4157
4158 /* X86_64_C3 */
4159 {
4160 { "retP", { BND }, 0 },
4161 { "ret@", { BND }, 0 },
4162 },
4163
4164 /* X86_64_C4 */
4165 {
4166 { MOD_TABLE (MOD_C4_32BIT) },
4167 { VEX_C4_TABLE (VEX_0F) },
4168 },
4169
4170 /* X86_64_C5 */
4171 {
4172 { MOD_TABLE (MOD_C5_32BIT) },
4173 { VEX_C5_TABLE (VEX_0F) },
4174 },
4175
4176 /* X86_64_CE */
4177 {
4178 { "into", { XX }, 0 },
4179 },
4180
4181 /* X86_64_D4 */
4182 {
4183 { "aam", { Ib }, 0 },
4184 },
4185
4186 /* X86_64_D5 */
4187 {
4188 { "aad", { Ib }, 0 },
4189 },
4190
4191 /* X86_64_E8 */
4192 {
4193 { "callP", { Jv, BND }, 0 },
4194 { "call@", { Jv, BND }, 0 }
4195 },
4196
4197 /* X86_64_E9 */
4198 {
4199 { "jmpP", { Jv, BND }, 0 },
4200 { "jmp@", { Jv, BND }, 0 }
4201 },
4202
4203 /* X86_64_EA */
4204 {
4205 { "{l|}jmp{P|}", { Ap }, 0 },
4206 },
4207
4208 /* X86_64_0F01_REG_0 */
4209 {
4210 { "sgdt{Q|Q}", { M }, 0 },
4211 { "sgdt", { M }, 0 },
4212 },
4213
4214 /* X86_64_0F01_REG_1 */
4215 {
4216 { "sidt{Q|Q}", { M }, 0 },
4217 { "sidt", { M }, 0 },
4218 },
4219
4220 /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4221 {
4222 { Bad_Opcode },
4223 { "seamret", { Skip_MODRM }, 0 },
4224 },
4225
4226 /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4227 {
4228 { Bad_Opcode },
4229 { "seamops", { Skip_MODRM }, 0 },
4230 },
4231
4232 /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4233 {
4234 { Bad_Opcode },
4235 { "seamcall", { Skip_MODRM }, 0 },
4236 },
4237
4238 /* X86_64_0F01_REG_2 */
4239 {
4240 { "lgdt{Q|Q}", { M }, 0 },
4241 { "lgdt", { M }, 0 },
4242 },
4243
4244 /* X86_64_0F01_REG_3 */
4245 {
4246 { "lidt{Q|Q}", { M }, 0 },
4247 { "lidt", { M }, 0 },
4248 },
4249
4250 /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4251 {
4252 { Bad_Opcode },
4253 { "uiret", { Skip_MODRM }, 0 },
4254 },
4255
4256 /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4257 {
4258 { Bad_Opcode },
4259 { "testui", { Skip_MODRM }, 0 },
4260 },
4261
4262 /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4263 {
4264 { Bad_Opcode },
4265 { "clui", { Skip_MODRM }, 0 },
4266 },
4267
4268 /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4269 {
4270 { Bad_Opcode },
4271 { "stui", { Skip_MODRM }, 0 },
4272 },
4273
4274 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4275 {
4276 { Bad_Opcode },
4277 { "rmpadjust", { Skip_MODRM }, 0 },
4278 },
4279
4280 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4281 {
4282 { Bad_Opcode },
4283 { "rmpupdate", { Skip_MODRM }, 0 },
4284 },
4285
4286 /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4287 {
4288 { Bad_Opcode },
4289 { "psmash", { Skip_MODRM }, 0 },
4290 },
4291
4292 {
4293 /* X86_64_0F24 */
4294 { "movZ", { Em, Td }, 0 },
4295 },
4296
4297 {
4298 /* X86_64_0F26 */
4299 { "movZ", { Td, Em }, 0 },
4300 },
4301
4302 /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4303 {
4304 { Bad_Opcode },
4305 { "senduipi", { Eq }, 0 },
4306 },
4307
4308 /* X86_64_VEX_0F3849 */
4309 {
4310 { Bad_Opcode },
4311 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
4312 },
4313
4314 /* X86_64_VEX_0F384B */
4315 {
4316 { Bad_Opcode },
4317 { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
4318 },
4319
4320 /* X86_64_VEX_0F385C */
4321 {
4322 { Bad_Opcode },
4323 { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
4324 },
4325
4326 /* X86_64_VEX_0F385E */
4327 {
4328 { Bad_Opcode },
4329 { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
4330 },
4331 };
4332
4333 static const struct dis386 three_byte_table[][256] = {
4334
4335 /* THREE_BYTE_0F38 */
4336 {
4337 /* 00 */
4338 { "pshufb", { MX, EM }, PREFIX_OPCODE },
4339 { "phaddw", { MX, EM }, PREFIX_OPCODE },
4340 { "phaddd", { MX, EM }, PREFIX_OPCODE },
4341 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
4342 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
4343 { "phsubw", { MX, EM }, PREFIX_OPCODE },
4344 { "phsubd", { MX, EM }, PREFIX_OPCODE },
4345 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
4346 /* 08 */
4347 { "psignb", { MX, EM }, PREFIX_OPCODE },
4348 { "psignw", { MX, EM }, PREFIX_OPCODE },
4349 { "psignd", { MX, EM }, PREFIX_OPCODE },
4350 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
4351 { Bad_Opcode },
4352 { Bad_Opcode },
4353 { Bad_Opcode },
4354 { Bad_Opcode },
4355 /* 10 */
4356 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4357 { Bad_Opcode },
4358 { Bad_Opcode },
4359 { Bad_Opcode },
4360 { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4361 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4362 { Bad_Opcode },
4363 { "ptest", { XM, EXx }, PREFIX_DATA },
4364 /* 18 */
4365 { Bad_Opcode },
4366 { Bad_Opcode },
4367 { Bad_Opcode },
4368 { Bad_Opcode },
4369 { "pabsb", { MX, EM }, PREFIX_OPCODE },
4370 { "pabsw", { MX, EM }, PREFIX_OPCODE },
4371 { "pabsd", { MX, EM }, PREFIX_OPCODE },
4372 { Bad_Opcode },
4373 /* 20 */
4374 { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4375 { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4376 { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4377 { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4378 { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4379 { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4380 { Bad_Opcode },
4381 { Bad_Opcode },
4382 /* 28 */
4383 { "pmuldq", { XM, EXx }, PREFIX_DATA },
4384 { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4385 { MOD_TABLE (MOD_0F382A) },
4386 { "packusdw", { XM, EXx }, PREFIX_DATA },
4387 { Bad_Opcode },
4388 { Bad_Opcode },
4389 { Bad_Opcode },
4390 { Bad_Opcode },
4391 /* 30 */
4392 { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4393 { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4394 { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4395 { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4396 { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4397 { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4398 { Bad_Opcode },
4399 { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4400 /* 38 */
4401 { "pminsb", { XM, EXx }, PREFIX_DATA },
4402 { "pminsd", { XM, EXx }, PREFIX_DATA },
4403 { "pminuw", { XM, EXx }, PREFIX_DATA },
4404 { "pminud", { XM, EXx }, PREFIX_DATA },
4405 { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4406 { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4407 { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4408 { "pmaxud", { XM, EXx }, PREFIX_DATA },
4409 /* 40 */
4410 { "pmulld", { XM, EXx }, PREFIX_DATA },
4411 { "phminposuw", { XM, EXx }, PREFIX_DATA },
4412 { Bad_Opcode },
4413 { Bad_Opcode },
4414 { Bad_Opcode },
4415 { Bad_Opcode },
4416 { Bad_Opcode },
4417 { Bad_Opcode },
4418 /* 48 */
4419 { Bad_Opcode },
4420 { Bad_Opcode },
4421 { Bad_Opcode },
4422 { Bad_Opcode },
4423 { Bad_Opcode },
4424 { Bad_Opcode },
4425 { Bad_Opcode },
4426 { Bad_Opcode },
4427 /* 50 */
4428 { Bad_Opcode },
4429 { Bad_Opcode },
4430 { Bad_Opcode },
4431 { Bad_Opcode },
4432 { Bad_Opcode },
4433 { Bad_Opcode },
4434 { Bad_Opcode },
4435 { Bad_Opcode },
4436 /* 58 */
4437 { Bad_Opcode },
4438 { Bad_Opcode },
4439 { Bad_Opcode },
4440 { Bad_Opcode },
4441 { Bad_Opcode },
4442 { Bad_Opcode },
4443 { Bad_Opcode },
4444 { Bad_Opcode },
4445 /* 60 */
4446 { Bad_Opcode },
4447 { Bad_Opcode },
4448 { Bad_Opcode },
4449 { Bad_Opcode },
4450 { Bad_Opcode },
4451 { Bad_Opcode },
4452 { Bad_Opcode },
4453 { Bad_Opcode },
4454 /* 68 */
4455 { Bad_Opcode },
4456 { Bad_Opcode },
4457 { Bad_Opcode },
4458 { Bad_Opcode },
4459 { Bad_Opcode },
4460 { Bad_Opcode },
4461 { Bad_Opcode },
4462 { Bad_Opcode },
4463 /* 70 */
4464 { Bad_Opcode },
4465 { Bad_Opcode },
4466 { Bad_Opcode },
4467 { Bad_Opcode },
4468 { Bad_Opcode },
4469 { Bad_Opcode },
4470 { Bad_Opcode },
4471 { Bad_Opcode },
4472 /* 78 */
4473 { Bad_Opcode },
4474 { Bad_Opcode },
4475 { Bad_Opcode },
4476 { Bad_Opcode },
4477 { Bad_Opcode },
4478 { Bad_Opcode },
4479 { Bad_Opcode },
4480 { Bad_Opcode },
4481 /* 80 */
4482 { "invept", { Gm, Mo }, PREFIX_DATA },
4483 { "invvpid", { Gm, Mo }, PREFIX_DATA },
4484 { "invpcid", { Gm, M }, PREFIX_DATA },
4485 { Bad_Opcode },
4486 { Bad_Opcode },
4487 { Bad_Opcode },
4488 { Bad_Opcode },
4489 { Bad_Opcode },
4490 /* 88 */
4491 { Bad_Opcode },
4492 { Bad_Opcode },
4493 { Bad_Opcode },
4494 { Bad_Opcode },
4495 { Bad_Opcode },
4496 { Bad_Opcode },
4497 { Bad_Opcode },
4498 { Bad_Opcode },
4499 /* 90 */
4500 { Bad_Opcode },
4501 { Bad_Opcode },
4502 { Bad_Opcode },
4503 { Bad_Opcode },
4504 { Bad_Opcode },
4505 { Bad_Opcode },
4506 { Bad_Opcode },
4507 { Bad_Opcode },
4508 /* 98 */
4509 { Bad_Opcode },
4510 { Bad_Opcode },
4511 { Bad_Opcode },
4512 { Bad_Opcode },
4513 { Bad_Opcode },
4514 { Bad_Opcode },
4515 { Bad_Opcode },
4516 { Bad_Opcode },
4517 /* a0 */
4518 { Bad_Opcode },
4519 { Bad_Opcode },
4520 { Bad_Opcode },
4521 { Bad_Opcode },
4522 { Bad_Opcode },
4523 { Bad_Opcode },
4524 { Bad_Opcode },
4525 { Bad_Opcode },
4526 /* a8 */
4527 { Bad_Opcode },
4528 { Bad_Opcode },
4529 { Bad_Opcode },
4530 { Bad_Opcode },
4531 { Bad_Opcode },
4532 { Bad_Opcode },
4533 { Bad_Opcode },
4534 { Bad_Opcode },
4535 /* b0 */
4536 { Bad_Opcode },
4537 { Bad_Opcode },
4538 { Bad_Opcode },
4539 { Bad_Opcode },
4540 { Bad_Opcode },
4541 { Bad_Opcode },
4542 { Bad_Opcode },
4543 { Bad_Opcode },
4544 /* b8 */
4545 { Bad_Opcode },
4546 { Bad_Opcode },
4547 { Bad_Opcode },
4548 { Bad_Opcode },
4549 { Bad_Opcode },
4550 { Bad_Opcode },
4551 { Bad_Opcode },
4552 { Bad_Opcode },
4553 /* c0 */
4554 { Bad_Opcode },
4555 { Bad_Opcode },
4556 { Bad_Opcode },
4557 { Bad_Opcode },
4558 { Bad_Opcode },
4559 { Bad_Opcode },
4560 { Bad_Opcode },
4561 { Bad_Opcode },
4562 /* c8 */
4563 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4564 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4565 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4566 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4567 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4568 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4569 { Bad_Opcode },
4570 { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4571 /* d0 */
4572 { Bad_Opcode },
4573 { Bad_Opcode },
4574 { Bad_Opcode },
4575 { Bad_Opcode },
4576 { Bad_Opcode },
4577 { Bad_Opcode },
4578 { Bad_Opcode },
4579 { Bad_Opcode },
4580 /* d8 */
4581 { PREFIX_TABLE (PREFIX_0F38D8) },
4582 { Bad_Opcode },
4583 { Bad_Opcode },
4584 { "aesimc", { XM, EXx }, PREFIX_DATA },
4585 { PREFIX_TABLE (PREFIX_0F38DC) },
4586 { PREFIX_TABLE (PREFIX_0F38DD) },
4587 { PREFIX_TABLE (PREFIX_0F38DE) },
4588 { PREFIX_TABLE (PREFIX_0F38DF) },
4589 /* e0 */
4590 { Bad_Opcode },
4591 { Bad_Opcode },
4592 { Bad_Opcode },
4593 { Bad_Opcode },
4594 { Bad_Opcode },
4595 { Bad_Opcode },
4596 { Bad_Opcode },
4597 { Bad_Opcode },
4598 /* e8 */
4599 { Bad_Opcode },
4600 { Bad_Opcode },
4601 { Bad_Opcode },
4602 { Bad_Opcode },
4603 { Bad_Opcode },
4604 { Bad_Opcode },
4605 { Bad_Opcode },
4606 { Bad_Opcode },
4607 /* f0 */
4608 { PREFIX_TABLE (PREFIX_0F38F0) },
4609 { PREFIX_TABLE (PREFIX_0F38F1) },
4610 { Bad_Opcode },
4611 { Bad_Opcode },
4612 { Bad_Opcode },
4613 { MOD_TABLE (MOD_0F38F5) },
4614 { PREFIX_TABLE (PREFIX_0F38F6) },
4615 { Bad_Opcode },
4616 /* f8 */
4617 { PREFIX_TABLE (PREFIX_0F38F8) },
4618 { MOD_TABLE (MOD_0F38F9) },
4619 { PREFIX_TABLE (PREFIX_0F38FA) },
4620 { PREFIX_TABLE (PREFIX_0F38FB) },
4621 { Bad_Opcode },
4622 { Bad_Opcode },
4623 { Bad_Opcode },
4624 { Bad_Opcode },
4625 },
4626 /* THREE_BYTE_0F3A */
4627 {
4628 /* 00 */
4629 { Bad_Opcode },
4630 { Bad_Opcode },
4631 { Bad_Opcode },
4632 { Bad_Opcode },
4633 { Bad_Opcode },
4634 { Bad_Opcode },
4635 { Bad_Opcode },
4636 { Bad_Opcode },
4637 /* 08 */
4638 { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4639 { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4640 { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4641 { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4642 { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4643 { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4644 { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4645 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
4646 /* 10 */
4647 { Bad_Opcode },
4648 { Bad_Opcode },
4649 { Bad_Opcode },
4650 { Bad_Opcode },
4651 { "pextrb", { Edb, XM, Ib }, PREFIX_DATA },
4652 { "pextrw", { Edw, XM, Ib }, PREFIX_DATA },
4653 { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4654 { "extractps", { Ed, XM, Ib }, PREFIX_DATA },
4655 /* 18 */
4656 { Bad_Opcode },
4657 { Bad_Opcode },
4658 { Bad_Opcode },
4659 { Bad_Opcode },
4660 { Bad_Opcode },
4661 { Bad_Opcode },
4662 { Bad_Opcode },
4663 { Bad_Opcode },
4664 /* 20 */
4665 { "pinsrb", { XM, Edb, Ib }, PREFIX_DATA },
4666 { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4667 { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4668 { Bad_Opcode },
4669 { Bad_Opcode },
4670 { Bad_Opcode },
4671 { Bad_Opcode },
4672 { Bad_Opcode },
4673 /* 28 */
4674 { Bad_Opcode },
4675 { Bad_Opcode },
4676 { Bad_Opcode },
4677 { Bad_Opcode },
4678 { Bad_Opcode },
4679 { Bad_Opcode },
4680 { Bad_Opcode },
4681 { Bad_Opcode },
4682 /* 30 */
4683 { Bad_Opcode },
4684 { Bad_Opcode },
4685 { Bad_Opcode },
4686 { Bad_Opcode },
4687 { Bad_Opcode },
4688 { Bad_Opcode },
4689 { Bad_Opcode },
4690 { Bad_Opcode },
4691 /* 38 */
4692 { Bad_Opcode },
4693 { Bad_Opcode },
4694 { Bad_Opcode },
4695 { Bad_Opcode },
4696 { Bad_Opcode },
4697 { Bad_Opcode },
4698 { Bad_Opcode },
4699 { Bad_Opcode },
4700 /* 40 */
4701 { "dpps", { XM, EXx, Ib }, PREFIX_DATA },
4702 { "dppd", { XM, EXx, Ib }, PREFIX_DATA },
4703 { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4704 { Bad_Opcode },
4705 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4706 { Bad_Opcode },
4707 { Bad_Opcode },
4708 { Bad_Opcode },
4709 /* 48 */
4710 { Bad_Opcode },
4711 { Bad_Opcode },
4712 { Bad_Opcode },
4713 { Bad_Opcode },
4714 { Bad_Opcode },
4715 { Bad_Opcode },
4716 { Bad_Opcode },
4717 { Bad_Opcode },
4718 /* 50 */
4719 { Bad_Opcode },
4720 { Bad_Opcode },
4721 { Bad_Opcode },
4722 { Bad_Opcode },
4723 { Bad_Opcode },
4724 { Bad_Opcode },
4725 { Bad_Opcode },
4726 { Bad_Opcode },
4727 /* 58 */
4728 { Bad_Opcode },
4729 { Bad_Opcode },
4730 { Bad_Opcode },
4731 { Bad_Opcode },
4732 { Bad_Opcode },
4733 { Bad_Opcode },
4734 { Bad_Opcode },
4735 { Bad_Opcode },
4736 /* 60 */
4737 { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4738 { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4739 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
4740 { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
4741 { Bad_Opcode },
4742 { Bad_Opcode },
4743 { Bad_Opcode },
4744 { Bad_Opcode },
4745 /* 68 */
4746 { Bad_Opcode },
4747 { Bad_Opcode },
4748 { Bad_Opcode },
4749 { Bad_Opcode },
4750 { Bad_Opcode },
4751 { Bad_Opcode },
4752 { Bad_Opcode },
4753 { Bad_Opcode },
4754 /* 70 */
4755 { Bad_Opcode },
4756 { Bad_Opcode },
4757 { Bad_Opcode },
4758 { Bad_Opcode },
4759 { Bad_Opcode },
4760 { Bad_Opcode },
4761 { Bad_Opcode },
4762 { Bad_Opcode },
4763 /* 78 */
4764 { Bad_Opcode },
4765 { Bad_Opcode },
4766 { Bad_Opcode },
4767 { Bad_Opcode },
4768 { Bad_Opcode },
4769 { Bad_Opcode },
4770 { Bad_Opcode },
4771 { Bad_Opcode },
4772 /* 80 */
4773 { Bad_Opcode },
4774 { Bad_Opcode },
4775 { Bad_Opcode },
4776 { Bad_Opcode },
4777 { Bad_Opcode },
4778 { Bad_Opcode },
4779 { Bad_Opcode },
4780 { Bad_Opcode },
4781 /* 88 */
4782 { Bad_Opcode },
4783 { Bad_Opcode },
4784 { Bad_Opcode },
4785 { Bad_Opcode },
4786 { Bad_Opcode },
4787 { Bad_Opcode },
4788 { Bad_Opcode },
4789 { Bad_Opcode },
4790 /* 90 */
4791 { Bad_Opcode },
4792 { Bad_Opcode },
4793 { Bad_Opcode },
4794 { Bad_Opcode },
4795 { Bad_Opcode },
4796 { Bad_Opcode },
4797 { Bad_Opcode },
4798 { Bad_Opcode },
4799 /* 98 */
4800 { Bad_Opcode },
4801 { Bad_Opcode },
4802 { Bad_Opcode },
4803 { Bad_Opcode },
4804 { Bad_Opcode },
4805 { Bad_Opcode },
4806 { Bad_Opcode },
4807 { Bad_Opcode },
4808 /* a0 */
4809 { Bad_Opcode },
4810 { Bad_Opcode },
4811 { Bad_Opcode },
4812 { Bad_Opcode },
4813 { Bad_Opcode },
4814 { Bad_Opcode },
4815 { Bad_Opcode },
4816 { Bad_Opcode },
4817 /* a8 */
4818 { Bad_Opcode },
4819 { Bad_Opcode },
4820 { Bad_Opcode },
4821 { Bad_Opcode },
4822 { Bad_Opcode },
4823 { Bad_Opcode },
4824 { Bad_Opcode },
4825 { Bad_Opcode },
4826 /* b0 */
4827 { Bad_Opcode },
4828 { Bad_Opcode },
4829 { Bad_Opcode },
4830 { Bad_Opcode },
4831 { Bad_Opcode },
4832 { Bad_Opcode },
4833 { Bad_Opcode },
4834 { Bad_Opcode },
4835 /* b8 */
4836 { Bad_Opcode },
4837 { Bad_Opcode },
4838 { Bad_Opcode },
4839 { Bad_Opcode },
4840 { Bad_Opcode },
4841 { Bad_Opcode },
4842 { Bad_Opcode },
4843 { Bad_Opcode },
4844 /* c0 */
4845 { Bad_Opcode },
4846 { Bad_Opcode },
4847 { Bad_Opcode },
4848 { Bad_Opcode },
4849 { Bad_Opcode },
4850 { Bad_Opcode },
4851 { Bad_Opcode },
4852 { Bad_Opcode },
4853 /* c8 */
4854 { Bad_Opcode },
4855 { Bad_Opcode },
4856 { Bad_Opcode },
4857 { Bad_Opcode },
4858 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4859 { Bad_Opcode },
4860 { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4861 { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4862 /* d0 */
4863 { Bad_Opcode },
4864 { Bad_Opcode },
4865 { Bad_Opcode },
4866 { Bad_Opcode },
4867 { Bad_Opcode },
4868 { Bad_Opcode },
4869 { Bad_Opcode },
4870 { Bad_Opcode },
4871 /* d8 */
4872 { Bad_Opcode },
4873 { Bad_Opcode },
4874 { Bad_Opcode },
4875 { Bad_Opcode },
4876 { Bad_Opcode },
4877 { Bad_Opcode },
4878 { Bad_Opcode },
4879 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
4880 /* e0 */
4881 { Bad_Opcode },
4882 { Bad_Opcode },
4883 { Bad_Opcode },
4884 { Bad_Opcode },
4885 { Bad_Opcode },
4886 { Bad_Opcode },
4887 { Bad_Opcode },
4888 { Bad_Opcode },
4889 /* e8 */
4890 { Bad_Opcode },
4891 { Bad_Opcode },
4892 { Bad_Opcode },
4893 { Bad_Opcode },
4894 { Bad_Opcode },
4895 { Bad_Opcode },
4896 { Bad_Opcode },
4897 { Bad_Opcode },
4898 /* f0 */
4899 { PREFIX_TABLE (PREFIX_0F3A0F) },
4900 { Bad_Opcode },
4901 { Bad_Opcode },
4902 { Bad_Opcode },
4903 { Bad_Opcode },
4904 { Bad_Opcode },
4905 { Bad_Opcode },
4906 { Bad_Opcode },
4907 /* f8 */
4908 { Bad_Opcode },
4909 { Bad_Opcode },
4910 { Bad_Opcode },
4911 { Bad_Opcode },
4912 { Bad_Opcode },
4913 { Bad_Opcode },
4914 { Bad_Opcode },
4915 { Bad_Opcode },
4916 },
4917 };
4918
4919 static const struct dis386 xop_table[][256] = {
4920 /* XOP_08 */
4921 {
4922 /* 00 */
4923 { Bad_Opcode },
4924 { Bad_Opcode },
4925 { Bad_Opcode },
4926 { Bad_Opcode },
4927 { Bad_Opcode },
4928 { Bad_Opcode },
4929 { Bad_Opcode },
4930 { Bad_Opcode },
4931 /* 08 */
4932 { Bad_Opcode },
4933 { Bad_Opcode },
4934 { Bad_Opcode },
4935 { Bad_Opcode },
4936 { Bad_Opcode },
4937 { Bad_Opcode },
4938 { Bad_Opcode },
4939 { Bad_Opcode },
4940 /* 10 */
4941 { Bad_Opcode },
4942 { Bad_Opcode },
4943 { Bad_Opcode },
4944 { Bad_Opcode },
4945 { Bad_Opcode },
4946 { Bad_Opcode },
4947 { Bad_Opcode },
4948 { Bad_Opcode },
4949 /* 18 */
4950 { Bad_Opcode },
4951 { Bad_Opcode },
4952 { Bad_Opcode },
4953 { Bad_Opcode },
4954 { Bad_Opcode },
4955 { Bad_Opcode },
4956 { Bad_Opcode },
4957 { Bad_Opcode },
4958 /* 20 */
4959 { Bad_Opcode },
4960 { Bad_Opcode },
4961 { Bad_Opcode },
4962 { Bad_Opcode },
4963 { Bad_Opcode },
4964 { Bad_Opcode },
4965 { Bad_Opcode },
4966 { Bad_Opcode },
4967 /* 28 */
4968 { Bad_Opcode },
4969 { Bad_Opcode },
4970 { Bad_Opcode },
4971 { Bad_Opcode },
4972 { Bad_Opcode },
4973 { Bad_Opcode },
4974 { Bad_Opcode },
4975 { Bad_Opcode },
4976 /* 30 */
4977 { Bad_Opcode },
4978 { Bad_Opcode },
4979 { Bad_Opcode },
4980 { Bad_Opcode },
4981 { Bad_Opcode },
4982 { Bad_Opcode },
4983 { Bad_Opcode },
4984 { Bad_Opcode },
4985 /* 38 */
4986 { Bad_Opcode },
4987 { Bad_Opcode },
4988 { Bad_Opcode },
4989 { Bad_Opcode },
4990 { Bad_Opcode },
4991 { Bad_Opcode },
4992 { Bad_Opcode },
4993 { Bad_Opcode },
4994 /* 40 */
4995 { Bad_Opcode },
4996 { Bad_Opcode },
4997 { Bad_Opcode },
4998 { Bad_Opcode },
4999 { Bad_Opcode },
5000 { Bad_Opcode },
5001 { Bad_Opcode },
5002 { Bad_Opcode },
5003 /* 48 */
5004 { Bad_Opcode },
5005 { Bad_Opcode },
5006 { Bad_Opcode },
5007 { Bad_Opcode },
5008 { Bad_Opcode },
5009 { Bad_Opcode },
5010 { Bad_Opcode },
5011 { Bad_Opcode },
5012 /* 50 */
5013 { Bad_Opcode },
5014 { Bad_Opcode },
5015 { Bad_Opcode },
5016 { Bad_Opcode },
5017 { Bad_Opcode },
5018 { Bad_Opcode },
5019 { Bad_Opcode },
5020 { Bad_Opcode },
5021 /* 58 */
5022 { Bad_Opcode },
5023 { Bad_Opcode },
5024 { Bad_Opcode },
5025 { Bad_Opcode },
5026 { Bad_Opcode },
5027 { Bad_Opcode },
5028 { Bad_Opcode },
5029 { Bad_Opcode },
5030 /* 60 */
5031 { Bad_Opcode },
5032 { Bad_Opcode },
5033 { Bad_Opcode },
5034 { Bad_Opcode },
5035 { Bad_Opcode },
5036 { Bad_Opcode },
5037 { Bad_Opcode },
5038 { Bad_Opcode },
5039 /* 68 */
5040 { Bad_Opcode },
5041 { Bad_Opcode },
5042 { Bad_Opcode },
5043 { Bad_Opcode },
5044 { Bad_Opcode },
5045 { Bad_Opcode },
5046 { Bad_Opcode },
5047 { Bad_Opcode },
5048 /* 70 */
5049 { Bad_Opcode },
5050 { Bad_Opcode },
5051 { Bad_Opcode },
5052 { Bad_Opcode },
5053 { Bad_Opcode },
5054 { Bad_Opcode },
5055 { Bad_Opcode },
5056 { Bad_Opcode },
5057 /* 78 */
5058 { Bad_Opcode },
5059 { Bad_Opcode },
5060 { Bad_Opcode },
5061 { Bad_Opcode },
5062 { Bad_Opcode },
5063 { Bad_Opcode },
5064 { Bad_Opcode },
5065 { Bad_Opcode },
5066 /* 80 */
5067 { Bad_Opcode },
5068 { Bad_Opcode },
5069 { Bad_Opcode },
5070 { Bad_Opcode },
5071 { Bad_Opcode },
5072 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
5073 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
5074 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
5075 /* 88 */
5076 { Bad_Opcode },
5077 { Bad_Opcode },
5078 { Bad_Opcode },
5079 { Bad_Opcode },
5080 { Bad_Opcode },
5081 { Bad_Opcode },
5082 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
5083 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
5084 /* 90 */
5085 { Bad_Opcode },
5086 { Bad_Opcode },
5087 { Bad_Opcode },
5088 { Bad_Opcode },
5089 { Bad_Opcode },
5090 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
5091 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
5092 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
5093 /* 98 */
5094 { Bad_Opcode },
5095 { Bad_Opcode },
5096 { Bad_Opcode },
5097 { Bad_Opcode },
5098 { Bad_Opcode },
5099 { Bad_Opcode },
5100 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
5101 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
5102 /* a0 */
5103 { Bad_Opcode },
5104 { Bad_Opcode },
5105 { "vpcmov", { XM, Vex, EXx, XMVexI4 }, 0 },
5106 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
5107 { Bad_Opcode },
5108 { Bad_Opcode },
5109 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
5110 { Bad_Opcode },
5111 /* a8 */
5112 { Bad_Opcode },
5113 { Bad_Opcode },
5114 { Bad_Opcode },
5115 { Bad_Opcode },
5116 { Bad_Opcode },
5117 { Bad_Opcode },
5118 { Bad_Opcode },
5119 { Bad_Opcode },
5120 /* b0 */
5121 { Bad_Opcode },
5122 { Bad_Opcode },
5123 { Bad_Opcode },
5124 { Bad_Opcode },
5125 { Bad_Opcode },
5126 { Bad_Opcode },
5127 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
5128 { Bad_Opcode },
5129 /* b8 */
5130 { Bad_Opcode },
5131 { Bad_Opcode },
5132 { Bad_Opcode },
5133 { Bad_Opcode },
5134 { Bad_Opcode },
5135 { Bad_Opcode },
5136 { Bad_Opcode },
5137 { Bad_Opcode },
5138 /* c0 */
5139 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
5140 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
5141 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
5142 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
5143 { Bad_Opcode },
5144 { Bad_Opcode },
5145 { Bad_Opcode },
5146 { Bad_Opcode },
5147 /* c8 */
5148 { Bad_Opcode },
5149 { Bad_Opcode },
5150 { Bad_Opcode },
5151 { Bad_Opcode },
5152 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
5153 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
5154 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
5155 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
5156 /* d0 */
5157 { Bad_Opcode },
5158 { Bad_Opcode },
5159 { Bad_Opcode },
5160 { Bad_Opcode },
5161 { Bad_Opcode },
5162 { Bad_Opcode },
5163 { Bad_Opcode },
5164 { Bad_Opcode },
5165 /* d8 */
5166 { Bad_Opcode },
5167 { Bad_Opcode },
5168 { Bad_Opcode },
5169 { Bad_Opcode },
5170 { Bad_Opcode },
5171 { Bad_Opcode },
5172 { Bad_Opcode },
5173 { Bad_Opcode },
5174 /* e0 */
5175 { Bad_Opcode },
5176 { Bad_Opcode },
5177 { Bad_Opcode },
5178 { Bad_Opcode },
5179 { Bad_Opcode },
5180 { Bad_Opcode },
5181 { Bad_Opcode },
5182 { Bad_Opcode },
5183 /* e8 */
5184 { Bad_Opcode },
5185 { Bad_Opcode },
5186 { Bad_Opcode },
5187 { Bad_Opcode },
5188 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
5189 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
5190 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
5191 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
5192 /* f0 */
5193 { Bad_Opcode },
5194 { Bad_Opcode },
5195 { Bad_Opcode },
5196 { Bad_Opcode },
5197 { Bad_Opcode },
5198 { Bad_Opcode },
5199 { Bad_Opcode },
5200 { Bad_Opcode },
5201 /* f8 */
5202 { Bad_Opcode },
5203 { Bad_Opcode },
5204 { Bad_Opcode },
5205 { Bad_Opcode },
5206 { Bad_Opcode },
5207 { Bad_Opcode },
5208 { Bad_Opcode },
5209 { Bad_Opcode },
5210 },
5211 /* XOP_09 */
5212 {
5213 /* 00 */
5214 { Bad_Opcode },
5215 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
5216 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
5217 { Bad_Opcode },
5218 { Bad_Opcode },
5219 { Bad_Opcode },
5220 { Bad_Opcode },
5221 { Bad_Opcode },
5222 /* 08 */
5223 { Bad_Opcode },
5224 { Bad_Opcode },
5225 { Bad_Opcode },
5226 { Bad_Opcode },
5227 { Bad_Opcode },
5228 { Bad_Opcode },
5229 { Bad_Opcode },
5230 { Bad_Opcode },
5231 /* 10 */
5232 { Bad_Opcode },
5233 { Bad_Opcode },
5234 { MOD_TABLE (MOD_XOP_09_12) },
5235 { Bad_Opcode },
5236 { Bad_Opcode },
5237 { Bad_Opcode },
5238 { Bad_Opcode },
5239 { Bad_Opcode },
5240 /* 18 */
5241 { Bad_Opcode },
5242 { Bad_Opcode },
5243 { Bad_Opcode },
5244 { Bad_Opcode },
5245 { Bad_Opcode },
5246 { Bad_Opcode },
5247 { Bad_Opcode },
5248 { Bad_Opcode },
5249 /* 20 */
5250 { Bad_Opcode },
5251 { Bad_Opcode },
5252 { Bad_Opcode },
5253 { Bad_Opcode },
5254 { Bad_Opcode },
5255 { Bad_Opcode },
5256 { Bad_Opcode },
5257 { Bad_Opcode },
5258 /* 28 */
5259 { Bad_Opcode },
5260 { Bad_Opcode },
5261 { Bad_Opcode },
5262 { Bad_Opcode },
5263 { Bad_Opcode },
5264 { Bad_Opcode },
5265 { Bad_Opcode },
5266 { Bad_Opcode },
5267 /* 30 */
5268 { Bad_Opcode },
5269 { Bad_Opcode },
5270 { Bad_Opcode },
5271 { Bad_Opcode },
5272 { Bad_Opcode },
5273 { Bad_Opcode },
5274 { Bad_Opcode },
5275 { Bad_Opcode },
5276 /* 38 */
5277 { Bad_Opcode },
5278 { Bad_Opcode },
5279 { Bad_Opcode },
5280 { Bad_Opcode },
5281 { Bad_Opcode },
5282 { Bad_Opcode },
5283 { Bad_Opcode },
5284 { Bad_Opcode },
5285 /* 40 */
5286 { Bad_Opcode },
5287 { Bad_Opcode },
5288 { Bad_Opcode },
5289 { Bad_Opcode },
5290 { Bad_Opcode },
5291 { Bad_Opcode },
5292 { Bad_Opcode },
5293 { Bad_Opcode },
5294 /* 48 */
5295 { Bad_Opcode },
5296 { Bad_Opcode },
5297 { Bad_Opcode },
5298 { Bad_Opcode },
5299 { Bad_Opcode },
5300 { Bad_Opcode },
5301 { Bad_Opcode },
5302 { Bad_Opcode },
5303 /* 50 */
5304 { Bad_Opcode },
5305 { Bad_Opcode },
5306 { Bad_Opcode },
5307 { Bad_Opcode },
5308 { Bad_Opcode },
5309 { Bad_Opcode },
5310 { Bad_Opcode },
5311 { Bad_Opcode },
5312 /* 58 */
5313 { Bad_Opcode },
5314 { Bad_Opcode },
5315 { Bad_Opcode },
5316 { Bad_Opcode },
5317 { Bad_Opcode },
5318 { Bad_Opcode },
5319 { Bad_Opcode },
5320 { Bad_Opcode },
5321 /* 60 */
5322 { Bad_Opcode },
5323 { Bad_Opcode },
5324 { Bad_Opcode },
5325 { Bad_Opcode },
5326 { Bad_Opcode },
5327 { Bad_Opcode },
5328 { Bad_Opcode },
5329 { Bad_Opcode },
5330 /* 68 */
5331 { Bad_Opcode },
5332 { Bad_Opcode },
5333 { Bad_Opcode },
5334 { Bad_Opcode },
5335 { Bad_Opcode },
5336 { Bad_Opcode },
5337 { Bad_Opcode },
5338 { Bad_Opcode },
5339 /* 70 */
5340 { Bad_Opcode },
5341 { Bad_Opcode },
5342 { Bad_Opcode },
5343 { Bad_Opcode },
5344 { Bad_Opcode },
5345 { Bad_Opcode },
5346 { Bad_Opcode },
5347 { Bad_Opcode },
5348 /* 78 */
5349 { Bad_Opcode },
5350 { Bad_Opcode },
5351 { Bad_Opcode },
5352 { Bad_Opcode },
5353 { Bad_Opcode },
5354 { Bad_Opcode },
5355 { Bad_Opcode },
5356 { Bad_Opcode },
5357 /* 80 */
5358 { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
5359 { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
5360 { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
5361 { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
5362 { Bad_Opcode },
5363 { Bad_Opcode },
5364 { Bad_Opcode },
5365 { Bad_Opcode },
5366 /* 88 */
5367 { Bad_Opcode },
5368 { Bad_Opcode },
5369 { Bad_Opcode },
5370 { Bad_Opcode },
5371 { Bad_Opcode },
5372 { Bad_Opcode },
5373 { Bad_Opcode },
5374 { Bad_Opcode },
5375 /* 90 */
5376 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
5377 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
5378 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
5379 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
5380 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
5381 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
5382 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
5383 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
5384 /* 98 */
5385 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
5386 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
5387 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
5388 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
5389 { Bad_Opcode },
5390 { Bad_Opcode },
5391 { Bad_Opcode },
5392 { Bad_Opcode },
5393 /* a0 */
5394 { Bad_Opcode },
5395 { Bad_Opcode },
5396 { Bad_Opcode },
5397 { Bad_Opcode },
5398 { Bad_Opcode },
5399 { Bad_Opcode },
5400 { Bad_Opcode },
5401 { Bad_Opcode },
5402 /* a8 */
5403 { Bad_Opcode },
5404 { Bad_Opcode },
5405 { Bad_Opcode },
5406 { Bad_Opcode },
5407 { Bad_Opcode },
5408 { Bad_Opcode },
5409 { Bad_Opcode },
5410 { Bad_Opcode },
5411 /* b0 */
5412 { Bad_Opcode },
5413 { Bad_Opcode },
5414 { Bad_Opcode },
5415 { Bad_Opcode },
5416 { Bad_Opcode },
5417 { Bad_Opcode },
5418 { Bad_Opcode },
5419 { Bad_Opcode },
5420 /* b8 */
5421 { Bad_Opcode },
5422 { Bad_Opcode },
5423 { Bad_Opcode },
5424 { Bad_Opcode },
5425 { Bad_Opcode },
5426 { Bad_Opcode },
5427 { Bad_Opcode },
5428 { Bad_Opcode },
5429 /* c0 */
5430 { Bad_Opcode },
5431 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
5432 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
5433 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
5434 { Bad_Opcode },
5435 { Bad_Opcode },
5436 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
5437 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
5438 /* c8 */
5439 { Bad_Opcode },
5440 { Bad_Opcode },
5441 { Bad_Opcode },
5442 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
5443 { Bad_Opcode },
5444 { Bad_Opcode },
5445 { Bad_Opcode },
5446 { Bad_Opcode },
5447 /* d0 */
5448 { Bad_Opcode },
5449 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
5450 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
5451 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
5452 { Bad_Opcode },
5453 { Bad_Opcode },
5454 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
5455 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
5456 /* d8 */
5457 { Bad_Opcode },
5458 { Bad_Opcode },
5459 { Bad_Opcode },
5460 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
5461 { Bad_Opcode },
5462 { Bad_Opcode },
5463 { Bad_Opcode },
5464 { Bad_Opcode },
5465 /* e0 */
5466 { Bad_Opcode },
5467 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
5468 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
5469 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
5470 { Bad_Opcode },
5471 { Bad_Opcode },
5472 { Bad_Opcode },
5473 { Bad_Opcode },
5474 /* e8 */
5475 { Bad_Opcode },
5476 { Bad_Opcode },
5477 { Bad_Opcode },
5478 { Bad_Opcode },
5479 { Bad_Opcode },
5480 { Bad_Opcode },
5481 { Bad_Opcode },
5482 { Bad_Opcode },
5483 /* f0 */
5484 { Bad_Opcode },
5485 { Bad_Opcode },
5486 { Bad_Opcode },
5487 { Bad_Opcode },
5488 { Bad_Opcode },
5489 { Bad_Opcode },
5490 { Bad_Opcode },
5491 { Bad_Opcode },
5492 /* f8 */
5493 { Bad_Opcode },
5494 { Bad_Opcode },
5495 { Bad_Opcode },
5496 { Bad_Opcode },
5497 { Bad_Opcode },
5498 { Bad_Opcode },
5499 { Bad_Opcode },
5500 { Bad_Opcode },
5501 },
5502 /* XOP_0A */
5503 {
5504 /* 00 */
5505 { Bad_Opcode },
5506 { Bad_Opcode },
5507 { Bad_Opcode },
5508 { Bad_Opcode },
5509 { Bad_Opcode },
5510 { Bad_Opcode },
5511 { Bad_Opcode },
5512 { Bad_Opcode },
5513 /* 08 */
5514 { Bad_Opcode },
5515 { Bad_Opcode },
5516 { Bad_Opcode },
5517 { Bad_Opcode },
5518 { Bad_Opcode },
5519 { Bad_Opcode },
5520 { Bad_Opcode },
5521 { Bad_Opcode },
5522 /* 10 */
5523 { "bextrS", { Gdq, Edq, Id }, 0 },
5524 { Bad_Opcode },
5525 { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
5526 { Bad_Opcode },
5527 { Bad_Opcode },
5528 { Bad_Opcode },
5529 { Bad_Opcode },
5530 { Bad_Opcode },
5531 /* 18 */
5532 { Bad_Opcode },
5533 { Bad_Opcode },
5534 { Bad_Opcode },
5535 { Bad_Opcode },
5536 { Bad_Opcode },
5537 { Bad_Opcode },
5538 { Bad_Opcode },
5539 { Bad_Opcode },
5540 /* 20 */
5541 { Bad_Opcode },
5542 { Bad_Opcode },
5543 { Bad_Opcode },
5544 { Bad_Opcode },
5545 { Bad_Opcode },
5546 { Bad_Opcode },
5547 { Bad_Opcode },
5548 { Bad_Opcode },
5549 /* 28 */
5550 { Bad_Opcode },
5551 { Bad_Opcode },
5552 { Bad_Opcode },
5553 { Bad_Opcode },
5554 { Bad_Opcode },
5555 { Bad_Opcode },
5556 { Bad_Opcode },
5557 { Bad_Opcode },
5558 /* 30 */
5559 { Bad_Opcode },
5560 { Bad_Opcode },
5561 { Bad_Opcode },
5562 { Bad_Opcode },
5563 { Bad_Opcode },
5564 { Bad_Opcode },
5565 { Bad_Opcode },
5566 { Bad_Opcode },
5567 /* 38 */
5568 { Bad_Opcode },
5569 { Bad_Opcode },
5570 { Bad_Opcode },
5571 { Bad_Opcode },
5572 { Bad_Opcode },
5573 { Bad_Opcode },
5574 { Bad_Opcode },
5575 { Bad_Opcode },
5576 /* 40 */
5577 { Bad_Opcode },
5578 { Bad_Opcode },
5579 { Bad_Opcode },
5580 { Bad_Opcode },
5581 { Bad_Opcode },
5582 { Bad_Opcode },
5583 { Bad_Opcode },
5584 { Bad_Opcode },
5585 /* 48 */
5586 { Bad_Opcode },
5587 { Bad_Opcode },
5588 { Bad_Opcode },
5589 { Bad_Opcode },
5590 { Bad_Opcode },
5591 { Bad_Opcode },
5592 { Bad_Opcode },
5593 { Bad_Opcode },
5594 /* 50 */
5595 { Bad_Opcode },
5596 { Bad_Opcode },
5597 { Bad_Opcode },
5598 { Bad_Opcode },
5599 { Bad_Opcode },
5600 { Bad_Opcode },
5601 { Bad_Opcode },
5602 { Bad_Opcode },
5603 /* 58 */
5604 { Bad_Opcode },
5605 { Bad_Opcode },
5606 { Bad_Opcode },
5607 { Bad_Opcode },
5608 { Bad_Opcode },
5609 { Bad_Opcode },
5610 { Bad_Opcode },
5611 { Bad_Opcode },
5612 /* 60 */
5613 { Bad_Opcode },
5614 { Bad_Opcode },
5615 { Bad_Opcode },
5616 { Bad_Opcode },
5617 { Bad_Opcode },
5618 { Bad_Opcode },
5619 { Bad_Opcode },
5620 { Bad_Opcode },
5621 /* 68 */
5622 { Bad_Opcode },
5623 { Bad_Opcode },
5624 { Bad_Opcode },
5625 { Bad_Opcode },
5626 { Bad_Opcode },
5627 { Bad_Opcode },
5628 { Bad_Opcode },
5629 { Bad_Opcode },
5630 /* 70 */
5631 { Bad_Opcode },
5632 { Bad_Opcode },
5633 { Bad_Opcode },
5634 { Bad_Opcode },
5635 { Bad_Opcode },
5636 { Bad_Opcode },
5637 { Bad_Opcode },
5638 { Bad_Opcode },
5639 /* 78 */
5640 { Bad_Opcode },
5641 { Bad_Opcode },
5642 { Bad_Opcode },
5643 { Bad_Opcode },
5644 { Bad_Opcode },
5645 { Bad_Opcode },
5646 { Bad_Opcode },
5647 { Bad_Opcode },
5648 /* 80 */
5649 { Bad_Opcode },
5650 { Bad_Opcode },
5651 { Bad_Opcode },
5652 { Bad_Opcode },
5653 { Bad_Opcode },
5654 { Bad_Opcode },
5655 { Bad_Opcode },
5656 { Bad_Opcode },
5657 /* 88 */
5658 { Bad_Opcode },
5659 { Bad_Opcode },
5660 { Bad_Opcode },
5661 { Bad_Opcode },
5662 { Bad_Opcode },
5663 { Bad_Opcode },
5664 { Bad_Opcode },
5665 { Bad_Opcode },
5666 /* 90 */
5667 { Bad_Opcode },
5668 { Bad_Opcode },
5669 { Bad_Opcode },
5670 { Bad_Opcode },
5671 { Bad_Opcode },
5672 { Bad_Opcode },
5673 { Bad_Opcode },
5674 { Bad_Opcode },
5675 /* 98 */
5676 { Bad_Opcode },
5677 { Bad_Opcode },
5678 { Bad_Opcode },
5679 { Bad_Opcode },
5680 { Bad_Opcode },
5681 { Bad_Opcode },
5682 { Bad_Opcode },
5683 { Bad_Opcode },
5684 /* a0 */
5685 { Bad_Opcode },
5686 { Bad_Opcode },
5687 { Bad_Opcode },
5688 { Bad_Opcode },
5689 { Bad_Opcode },
5690 { Bad_Opcode },
5691 { Bad_Opcode },
5692 { Bad_Opcode },
5693 /* a8 */
5694 { Bad_Opcode },
5695 { Bad_Opcode },
5696 { Bad_Opcode },
5697 { Bad_Opcode },
5698 { Bad_Opcode },
5699 { Bad_Opcode },
5700 { Bad_Opcode },
5701 { Bad_Opcode },
5702 /* b0 */
5703 { Bad_Opcode },
5704 { Bad_Opcode },
5705 { Bad_Opcode },
5706 { Bad_Opcode },
5707 { Bad_Opcode },
5708 { Bad_Opcode },
5709 { Bad_Opcode },
5710 { Bad_Opcode },
5711 /* b8 */
5712 { Bad_Opcode },
5713 { Bad_Opcode },
5714 { Bad_Opcode },
5715 { Bad_Opcode },
5716 { Bad_Opcode },
5717 { Bad_Opcode },
5718 { Bad_Opcode },
5719 { Bad_Opcode },
5720 /* c0 */
5721 { Bad_Opcode },
5722 { Bad_Opcode },
5723 { Bad_Opcode },
5724 { Bad_Opcode },
5725 { Bad_Opcode },
5726 { Bad_Opcode },
5727 { Bad_Opcode },
5728 { Bad_Opcode },
5729 /* c8 */
5730 { Bad_Opcode },
5731 { Bad_Opcode },
5732 { Bad_Opcode },
5733 { Bad_Opcode },
5734 { Bad_Opcode },
5735 { Bad_Opcode },
5736 { Bad_Opcode },
5737 { Bad_Opcode },
5738 /* d0 */
5739 { Bad_Opcode },
5740 { Bad_Opcode },
5741 { Bad_Opcode },
5742 { Bad_Opcode },
5743 { Bad_Opcode },
5744 { Bad_Opcode },
5745 { Bad_Opcode },
5746 { Bad_Opcode },
5747 /* d8 */
5748 { Bad_Opcode },
5749 { Bad_Opcode },
5750 { Bad_Opcode },
5751 { Bad_Opcode },
5752 { Bad_Opcode },
5753 { Bad_Opcode },
5754 { Bad_Opcode },
5755 { Bad_Opcode },
5756 /* e0 */
5757 { Bad_Opcode },
5758 { Bad_Opcode },
5759 { Bad_Opcode },
5760 { Bad_Opcode },
5761 { Bad_Opcode },
5762 { Bad_Opcode },
5763 { Bad_Opcode },
5764 { Bad_Opcode },
5765 /* e8 */
5766 { Bad_Opcode },
5767 { Bad_Opcode },
5768 { Bad_Opcode },
5769 { Bad_Opcode },
5770 { Bad_Opcode },
5771 { Bad_Opcode },
5772 { Bad_Opcode },
5773 { Bad_Opcode },
5774 /* f0 */
5775 { Bad_Opcode },
5776 { Bad_Opcode },
5777 { Bad_Opcode },
5778 { Bad_Opcode },
5779 { Bad_Opcode },
5780 { Bad_Opcode },
5781 { Bad_Opcode },
5782 { Bad_Opcode },
5783 /* f8 */
5784 { Bad_Opcode },
5785 { Bad_Opcode },
5786 { Bad_Opcode },
5787 { Bad_Opcode },
5788 { Bad_Opcode },
5789 { Bad_Opcode },
5790 { Bad_Opcode },
5791 { Bad_Opcode },
5792 },
5793 };
5794
5795 static const struct dis386 vex_table[][256] = {
5796 /* VEX_0F */
5797 {
5798 /* 00 */
5799 { Bad_Opcode },
5800 { Bad_Opcode },
5801 { Bad_Opcode },
5802 { Bad_Opcode },
5803 { Bad_Opcode },
5804 { Bad_Opcode },
5805 { Bad_Opcode },
5806 { Bad_Opcode },
5807 /* 08 */
5808 { Bad_Opcode },
5809 { Bad_Opcode },
5810 { Bad_Opcode },
5811 { Bad_Opcode },
5812 { Bad_Opcode },
5813 { Bad_Opcode },
5814 { Bad_Opcode },
5815 { Bad_Opcode },
5816 /* 10 */
5817 { PREFIX_TABLE (PREFIX_VEX_0F10) },
5818 { PREFIX_TABLE (PREFIX_VEX_0F11) },
5819 { PREFIX_TABLE (PREFIX_VEX_0F12) },
5820 { MOD_TABLE (MOD_VEX_0F13) },
5821 { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5822 { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5823 { PREFIX_TABLE (PREFIX_VEX_0F16) },
5824 { MOD_TABLE (MOD_VEX_0F17) },
5825 /* 18 */
5826 { Bad_Opcode },
5827 { Bad_Opcode },
5828 { Bad_Opcode },
5829 { Bad_Opcode },
5830 { Bad_Opcode },
5831 { Bad_Opcode },
5832 { Bad_Opcode },
5833 { Bad_Opcode },
5834 /* 20 */
5835 { Bad_Opcode },
5836 { Bad_Opcode },
5837 { Bad_Opcode },
5838 { Bad_Opcode },
5839 { Bad_Opcode },
5840 { Bad_Opcode },
5841 { Bad_Opcode },
5842 { Bad_Opcode },
5843 /* 28 */
5844 { "vmovapX", { XM, EXx }, PREFIX_OPCODE },
5845 { "vmovapX", { EXxS, XM }, PREFIX_OPCODE },
5846 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
5847 { MOD_TABLE (MOD_VEX_0F2B) },
5848 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
5849 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
5850 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
5851 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
5852 /* 30 */
5853 { Bad_Opcode },
5854 { Bad_Opcode },
5855 { Bad_Opcode },
5856 { Bad_Opcode },
5857 { Bad_Opcode },
5858 { Bad_Opcode },
5859 { Bad_Opcode },
5860 { Bad_Opcode },
5861 /* 38 */
5862 { Bad_Opcode },
5863 { Bad_Opcode },
5864 { Bad_Opcode },
5865 { Bad_Opcode },
5866 { Bad_Opcode },
5867 { Bad_Opcode },
5868 { Bad_Opcode },
5869 { Bad_Opcode },
5870 /* 40 */
5871 { Bad_Opcode },
5872 { VEX_LEN_TABLE (VEX_LEN_0F41) },
5873 { VEX_LEN_TABLE (VEX_LEN_0F42) },
5874 { Bad_Opcode },
5875 { VEX_LEN_TABLE (VEX_LEN_0F44) },
5876 { VEX_LEN_TABLE (VEX_LEN_0F45) },
5877 { VEX_LEN_TABLE (VEX_LEN_0F46) },
5878 { VEX_LEN_TABLE (VEX_LEN_0F47) },
5879 /* 48 */
5880 { Bad_Opcode },
5881 { Bad_Opcode },
5882 { VEX_LEN_TABLE (VEX_LEN_0F4A) },
5883 { VEX_LEN_TABLE (VEX_LEN_0F4B) },
5884 { Bad_Opcode },
5885 { Bad_Opcode },
5886 { Bad_Opcode },
5887 { Bad_Opcode },
5888 /* 50 */
5889 { MOD_TABLE (MOD_VEX_0F50) },
5890 { PREFIX_TABLE (PREFIX_VEX_0F51) },
5891 { PREFIX_TABLE (PREFIX_VEX_0F52) },
5892 { PREFIX_TABLE (PREFIX_VEX_0F53) },
5893 { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5894 { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5895 { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5896 { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5897 /* 58 */
5898 { PREFIX_TABLE (PREFIX_VEX_0F58) },
5899 { PREFIX_TABLE (PREFIX_VEX_0F59) },
5900 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
5901 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
5902 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
5903 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
5904 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
5905 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
5906 /* 60 */
5907 { "vpunpcklbw", { XM, Vex, EXx }, PREFIX_DATA },
5908 { "vpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA },
5909 { "vpunpckldq", { XM, Vex, EXx }, PREFIX_DATA },
5910 { "vpacksswb", { XM, Vex, EXx }, PREFIX_DATA },
5911 { "vpcmpgtb", { XM, Vex, EXx }, PREFIX_DATA },
5912 { "vpcmpgtw", { XM, Vex, EXx }, PREFIX_DATA },
5913 { "vpcmpgtd", { XM, Vex, EXx }, PREFIX_DATA },
5914 { "vpackuswb", { XM, Vex, EXx }, PREFIX_DATA },
5915 /* 68 */
5916 { "vpunpckhbw", { XM, Vex, EXx }, PREFIX_DATA },
5917 { "vpunpckhwd", { XM, Vex, EXx }, PREFIX_DATA },
5918 { "vpunpckhdq", { XM, Vex, EXx }, PREFIX_DATA },
5919 { "vpackssdw", { XM, Vex, EXx }, PREFIX_DATA },
5920 { "vpunpcklqdq", { XM, Vex, EXx }, PREFIX_DATA },
5921 { "vpunpckhqdq", { XM, Vex, EXx }, PREFIX_DATA },
5922 { VEX_LEN_TABLE (VEX_LEN_0F6E) },
5923 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
5924 /* 70 */
5925 { PREFIX_TABLE (PREFIX_VEX_0F70) },
5926 { MOD_TABLE (MOD_VEX_0F71) },
5927 { MOD_TABLE (MOD_VEX_0F72) },
5928 { MOD_TABLE (MOD_VEX_0F73) },
5929 { "vpcmpeqb", { XM, Vex, EXx }, PREFIX_DATA },
5930 { "vpcmpeqw", { XM, Vex, EXx }, PREFIX_DATA },
5931 { "vpcmpeqd", { XM, Vex, EXx }, PREFIX_DATA },
5932 { VEX_LEN_TABLE (VEX_LEN_0F77) },
5933 /* 78 */
5934 { Bad_Opcode },
5935 { Bad_Opcode },
5936 { Bad_Opcode },
5937 { Bad_Opcode },
5938 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
5939 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
5940 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
5941 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
5942 /* 80 */
5943 { Bad_Opcode },
5944 { Bad_Opcode },
5945 { Bad_Opcode },
5946 { Bad_Opcode },
5947 { Bad_Opcode },
5948 { Bad_Opcode },
5949 { Bad_Opcode },
5950 { Bad_Opcode },
5951 /* 88 */
5952 { Bad_Opcode },
5953 { Bad_Opcode },
5954 { Bad_Opcode },
5955 { Bad_Opcode },
5956 { Bad_Opcode },
5957 { Bad_Opcode },
5958 { Bad_Opcode },
5959 { Bad_Opcode },
5960 /* 90 */
5961 { VEX_LEN_TABLE (VEX_LEN_0F90) },
5962 { VEX_LEN_TABLE (VEX_LEN_0F91) },
5963 { VEX_LEN_TABLE (VEX_LEN_0F92) },
5964 { VEX_LEN_TABLE (VEX_LEN_0F93) },
5965 { Bad_Opcode },
5966 { Bad_Opcode },
5967 { Bad_Opcode },
5968 { Bad_Opcode },
5969 /* 98 */
5970 { VEX_LEN_TABLE (VEX_LEN_0F98) },
5971 { VEX_LEN_TABLE (VEX_LEN_0F99) },
5972 { Bad_Opcode },
5973 { Bad_Opcode },
5974 { Bad_Opcode },
5975 { Bad_Opcode },
5976 { Bad_Opcode },
5977 { Bad_Opcode },
5978 /* a0 */
5979 { Bad_Opcode },
5980 { Bad_Opcode },
5981 { Bad_Opcode },
5982 { Bad_Opcode },
5983 { Bad_Opcode },
5984 { Bad_Opcode },
5985 { Bad_Opcode },
5986 { Bad_Opcode },
5987 /* a8 */
5988 { Bad_Opcode },
5989 { Bad_Opcode },
5990 { Bad_Opcode },
5991 { Bad_Opcode },
5992 { Bad_Opcode },
5993 { Bad_Opcode },
5994 { REG_TABLE (REG_VEX_0FAE) },
5995 { Bad_Opcode },
5996 /* b0 */
5997 { Bad_Opcode },
5998 { Bad_Opcode },
5999 { Bad_Opcode },
6000 { Bad_Opcode },
6001 { Bad_Opcode },
6002 { Bad_Opcode },
6003 { Bad_Opcode },
6004 { Bad_Opcode },
6005 /* b8 */
6006 { Bad_Opcode },
6007 { Bad_Opcode },
6008 { Bad_Opcode },
6009 { Bad_Opcode },
6010 { Bad_Opcode },
6011 { Bad_Opcode },
6012 { Bad_Opcode },
6013 { Bad_Opcode },
6014 /* c0 */
6015 { Bad_Opcode },
6016 { Bad_Opcode },
6017 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
6018 { Bad_Opcode },
6019 { VEX_LEN_TABLE (VEX_LEN_0FC4) },
6020 { VEX_LEN_TABLE (VEX_LEN_0FC5) },
6021 { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6022 { Bad_Opcode },
6023 /* c8 */
6024 { Bad_Opcode },
6025 { Bad_Opcode },
6026 { Bad_Opcode },
6027 { Bad_Opcode },
6028 { Bad_Opcode },
6029 { Bad_Opcode },
6030 { Bad_Opcode },
6031 { Bad_Opcode },
6032 /* d0 */
6033 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
6034 { "vpsrlw", { XM, Vex, EXxmm }, PREFIX_DATA },
6035 { "vpsrld", { XM, Vex, EXxmm }, PREFIX_DATA },
6036 { "vpsrlq", { XM, Vex, EXxmm }, PREFIX_DATA },
6037 { "vpaddq", { XM, Vex, EXx }, PREFIX_DATA },
6038 { "vpmullw", { XM, Vex, EXx }, PREFIX_DATA },
6039 { VEX_LEN_TABLE (VEX_LEN_0FD6) },
6040 { MOD_TABLE (MOD_VEX_0FD7) },
6041 /* d8 */
6042 { "vpsubusb", { XM, Vex, EXx }, PREFIX_DATA },
6043 { "vpsubusw", { XM, Vex, EXx }, PREFIX_DATA },
6044 { "vpminub", { XM, Vex, EXx }, PREFIX_DATA },
6045 { "vpand", { XM, Vex, EXx }, PREFIX_DATA },
6046 { "vpaddusb", { XM, Vex, EXx }, PREFIX_DATA },
6047 { "vpaddusw", { XM, Vex, EXx }, PREFIX_DATA },
6048 { "vpmaxub", { XM, Vex, EXx }, PREFIX_DATA },
6049 { "vpandn", { XM, Vex, EXx }, PREFIX_DATA },
6050 /* e0 */
6051 { "vpavgb", { XM, Vex, EXx }, PREFIX_DATA },
6052 { "vpsraw", { XM, Vex, EXxmm }, PREFIX_DATA },
6053 { "vpsrad", { XM, Vex, EXxmm }, PREFIX_DATA },
6054 { "vpavgw", { XM, Vex, EXx }, PREFIX_DATA },
6055 { "vpmulhuw", { XM, Vex, EXx }, PREFIX_DATA },
6056 { "vpmulhw", { XM, Vex, EXx }, PREFIX_DATA },
6057 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
6058 { MOD_TABLE (MOD_VEX_0FE7) },
6059 /* e8 */
6060 { "vpsubsb", { XM, Vex, EXx }, PREFIX_DATA },
6061 { "vpsubsw", { XM, Vex, EXx }, PREFIX_DATA },
6062 { "vpminsw", { XM, Vex, EXx }, PREFIX_DATA },
6063 { "vpor", { XM, Vex, EXx }, PREFIX_DATA },
6064 { "vpaddsb", { XM, Vex, EXx }, PREFIX_DATA },
6065 { "vpaddsw", { XM, Vex, EXx }, PREFIX_DATA },
6066 { "vpmaxsw", { XM, Vex, EXx }, PREFIX_DATA },
6067 { "vpxor", { XM, Vex, EXx }, PREFIX_DATA },
6068 /* f0 */
6069 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
6070 { "vpsllw", { XM, Vex, EXxmm }, PREFIX_DATA },
6071 { "vpslld", { XM, Vex, EXxmm }, PREFIX_DATA },
6072 { "vpsllq", { XM, Vex, EXxmm }, PREFIX_DATA },
6073 { "vpmuludq", { XM, Vex, EXx }, PREFIX_DATA },
6074 { "vpmaddwd", { XM, Vex, EXx }, PREFIX_DATA },
6075 { "vpsadbw", { XM, Vex, EXx }, PREFIX_DATA },
6076 { VEX_LEN_TABLE (VEX_LEN_0FF7) },
6077 /* f8 */
6078 { "vpsubb", { XM, Vex, EXx }, PREFIX_DATA },
6079 { "vpsubw", { XM, Vex, EXx }, PREFIX_DATA },
6080 { "vpsubd", { XM, Vex, EXx }, PREFIX_DATA },
6081 { "vpsubq", { XM, Vex, EXx }, PREFIX_DATA },
6082 { "vpaddb", { XM, Vex, EXx }, PREFIX_DATA },
6083 { "vpaddw", { XM, Vex, EXx }, PREFIX_DATA },
6084 { "vpaddd", { XM, Vex, EXx }, PREFIX_DATA },
6085 { Bad_Opcode },
6086 },
6087 /* VEX_0F38 */
6088 {
6089 /* 00 */
6090 { "vpshufb", { XM, Vex, EXx }, PREFIX_DATA },
6091 { "vphaddw", { XM, Vex, EXx }, PREFIX_DATA },
6092 { "vphaddd", { XM, Vex, EXx }, PREFIX_DATA },
6093 { "vphaddsw", { XM, Vex, EXx }, PREFIX_DATA },
6094 { "vpmaddubsw", { XM, Vex, EXx }, PREFIX_DATA },
6095 { "vphsubw", { XM, Vex, EXx }, PREFIX_DATA },
6096 { "vphsubd", { XM, Vex, EXx }, PREFIX_DATA },
6097 { "vphsubsw", { XM, Vex, EXx }, PREFIX_DATA },
6098 /* 08 */
6099 { "vpsignb", { XM, Vex, EXx }, PREFIX_DATA },
6100 { "vpsignw", { XM, Vex, EXx }, PREFIX_DATA },
6101 { "vpsignd", { XM, Vex, EXx }, PREFIX_DATA },
6102 { "vpmulhrsw", { XM, Vex, EXx }, PREFIX_DATA },
6103 { VEX_W_TABLE (VEX_W_0F380C) },
6104 { VEX_W_TABLE (VEX_W_0F380D) },
6105 { VEX_W_TABLE (VEX_W_0F380E) },
6106 { VEX_W_TABLE (VEX_W_0F380F) },
6107 /* 10 */
6108 { Bad_Opcode },
6109 { Bad_Opcode },
6110 { Bad_Opcode },
6111 { VEX_W_TABLE (VEX_W_0F3813) },
6112 { Bad_Opcode },
6113 { Bad_Opcode },
6114 { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6115 { "vptest", { XM, EXx }, PREFIX_DATA },
6116 /* 18 */
6117 { VEX_W_TABLE (VEX_W_0F3818) },
6118 { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6119 { MOD_TABLE (MOD_VEX_0F381A) },
6120 { Bad_Opcode },
6121 { "vpabsb", { XM, EXx }, PREFIX_DATA },
6122 { "vpabsw", { XM, EXx }, PREFIX_DATA },
6123 { "vpabsd", { XM, EXx }, PREFIX_DATA },
6124 { Bad_Opcode },
6125 /* 20 */
6126 { "vpmovsxbw", { XM, EXxmmq }, PREFIX_DATA },
6127 { "vpmovsxbd", { XM, EXxmmqd }, PREFIX_DATA },
6128 { "vpmovsxbq", { XM, EXxmmdw }, PREFIX_DATA },
6129 { "vpmovsxwd", { XM, EXxmmq }, PREFIX_DATA },
6130 { "vpmovsxwq", { XM, EXxmmqd }, PREFIX_DATA },
6131 { "vpmovsxdq", { XM, EXxmmq }, PREFIX_DATA },
6132 { Bad_Opcode },
6133 { Bad_Opcode },
6134 /* 28 */
6135 { "vpmuldq", { XM, Vex, EXx }, PREFIX_DATA },
6136 { "vpcmpeqq", { XM, Vex, EXx }, PREFIX_DATA },
6137 { MOD_TABLE (MOD_VEX_0F382A) },
6138 { "vpackusdw", { XM, Vex, EXx }, PREFIX_DATA },
6139 { MOD_TABLE (MOD_VEX_0F382C) },
6140 { MOD_TABLE (MOD_VEX_0F382D) },
6141 { MOD_TABLE (MOD_VEX_0F382E) },
6142 { MOD_TABLE (MOD_VEX_0F382F) },
6143 /* 30 */
6144 { "vpmovzxbw", { XM, EXxmmq }, PREFIX_DATA },
6145 { "vpmovzxbd", { XM, EXxmmqd }, PREFIX_DATA },
6146 { "vpmovzxbq", { XM, EXxmmdw }, PREFIX_DATA },
6147 { "vpmovzxwd", { XM, EXxmmq }, PREFIX_DATA },
6148 { "vpmovzxwq", { XM, EXxmmqd }, PREFIX_DATA },
6149 { "vpmovzxdq", { XM, EXxmmq }, PREFIX_DATA },
6150 { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6151 { "vpcmpgtq", { XM, Vex, EXx }, PREFIX_DATA },
6152 /* 38 */
6153 { "vpminsb", { XM, Vex, EXx }, PREFIX_DATA },
6154 { "vpminsd", { XM, Vex, EXx }, PREFIX_DATA },
6155 { "vpminuw", { XM, Vex, EXx }, PREFIX_DATA },
6156 { "vpminud", { XM, Vex, EXx }, PREFIX_DATA },
6157 { "vpmaxsb", { XM, Vex, EXx }, PREFIX_DATA },
6158 { "vpmaxsd", { XM, Vex, EXx }, PREFIX_DATA },
6159 { "vpmaxuw", { XM, Vex, EXx }, PREFIX_DATA },
6160 { "vpmaxud", { XM, Vex, EXx }, PREFIX_DATA },
6161 /* 40 */
6162 { "vpmulld", { XM, Vex, EXx }, PREFIX_DATA },
6163 { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6164 { Bad_Opcode },
6165 { Bad_Opcode },
6166 { Bad_Opcode },
6167 { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6168 { VEX_W_TABLE (VEX_W_0F3846) },
6169 { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6170 /* 48 */
6171 { Bad_Opcode },
6172 { X86_64_TABLE (X86_64_VEX_0F3849) },
6173 { Bad_Opcode },
6174 { X86_64_TABLE (X86_64_VEX_0F384B) },
6175 { Bad_Opcode },
6176 { Bad_Opcode },
6177 { Bad_Opcode },
6178 { Bad_Opcode },
6179 /* 50 */
6180 { VEX_W_TABLE (VEX_W_0F3850) },
6181 { VEX_W_TABLE (VEX_W_0F3851) },
6182 { VEX_W_TABLE (VEX_W_0F3852) },
6183 { VEX_W_TABLE (VEX_W_0F3853) },
6184 { Bad_Opcode },
6185 { Bad_Opcode },
6186 { Bad_Opcode },
6187 { Bad_Opcode },
6188 /* 58 */
6189 { VEX_W_TABLE (VEX_W_0F3858) },
6190 { VEX_W_TABLE (VEX_W_0F3859) },
6191 { MOD_TABLE (MOD_VEX_0F385A) },
6192 { Bad_Opcode },
6193 { X86_64_TABLE (X86_64_VEX_0F385C) },
6194 { Bad_Opcode },
6195 { X86_64_TABLE (X86_64_VEX_0F385E) },
6196 { Bad_Opcode },
6197 /* 60 */
6198 { Bad_Opcode },
6199 { Bad_Opcode },
6200 { Bad_Opcode },
6201 { Bad_Opcode },
6202 { Bad_Opcode },
6203 { Bad_Opcode },
6204 { Bad_Opcode },
6205 { Bad_Opcode },
6206 /* 68 */
6207 { Bad_Opcode },
6208 { Bad_Opcode },
6209 { Bad_Opcode },
6210 { Bad_Opcode },
6211 { Bad_Opcode },
6212 { Bad_Opcode },
6213 { Bad_Opcode },
6214 { Bad_Opcode },
6215 /* 70 */
6216 { Bad_Opcode },
6217 { Bad_Opcode },
6218 { Bad_Opcode },
6219 { Bad_Opcode },
6220 { Bad_Opcode },
6221 { Bad_Opcode },
6222 { Bad_Opcode },
6223 { Bad_Opcode },
6224 /* 78 */
6225 { VEX_W_TABLE (VEX_W_0F3878) },
6226 { VEX_W_TABLE (VEX_W_0F3879) },
6227 { Bad_Opcode },
6228 { Bad_Opcode },
6229 { Bad_Opcode },
6230 { Bad_Opcode },
6231 { Bad_Opcode },
6232 { Bad_Opcode },
6233 /* 80 */
6234 { Bad_Opcode },
6235 { Bad_Opcode },
6236 { Bad_Opcode },
6237 { Bad_Opcode },
6238 { Bad_Opcode },
6239 { Bad_Opcode },
6240 { Bad_Opcode },
6241 { Bad_Opcode },
6242 /* 88 */
6243 { Bad_Opcode },
6244 { Bad_Opcode },
6245 { Bad_Opcode },
6246 { Bad_Opcode },
6247 { MOD_TABLE (MOD_VEX_0F388C) },
6248 { Bad_Opcode },
6249 { MOD_TABLE (MOD_VEX_0F388E) },
6250 { Bad_Opcode },
6251 /* 90 */
6252 { "vpgatherd%DQ", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6253 { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6254 { "vgatherdp%XW", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6255 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6256 { Bad_Opcode },
6257 { Bad_Opcode },
6258 { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6259 { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6260 /* 98 */
6261 { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6262 { "vfmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6263 { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6264 { "vfmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6265 { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6266 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6267 { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6268 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6269 /* a0 */
6270 { Bad_Opcode },
6271 { Bad_Opcode },
6272 { Bad_Opcode },
6273 { Bad_Opcode },
6274 { Bad_Opcode },
6275 { Bad_Opcode },
6276 { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6277 { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6278 /* a8 */
6279 { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6280 { "vfmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6281 { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6282 { "vfmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6283 { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6284 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6285 { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6286 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6287 /* b0 */
6288 { Bad_Opcode },
6289 { Bad_Opcode },
6290 { Bad_Opcode },
6291 { Bad_Opcode },
6292 { Bad_Opcode },
6293 { Bad_Opcode },
6294 { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6295 { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6296 /* b8 */
6297 { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6298 { "vfmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6299 { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6300 { "vfmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6301 { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6302 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6303 { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6304 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6305 /* c0 */
6306 { Bad_Opcode },
6307 { Bad_Opcode },
6308 { Bad_Opcode },
6309 { Bad_Opcode },
6310 { Bad_Opcode },
6311 { Bad_Opcode },
6312 { Bad_Opcode },
6313 { Bad_Opcode },
6314 /* c8 */
6315 { Bad_Opcode },
6316 { Bad_Opcode },
6317 { Bad_Opcode },
6318 { Bad_Opcode },
6319 { Bad_Opcode },
6320 { Bad_Opcode },
6321 { Bad_Opcode },
6322 { VEX_W_TABLE (VEX_W_0F38CF) },
6323 /* d0 */
6324 { Bad_Opcode },
6325 { Bad_Opcode },
6326 { Bad_Opcode },
6327 { Bad_Opcode },
6328 { Bad_Opcode },
6329 { Bad_Opcode },
6330 { Bad_Opcode },
6331 { Bad_Opcode },
6332 /* d8 */
6333 { Bad_Opcode },
6334 { Bad_Opcode },
6335 { Bad_Opcode },
6336 { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6337 { "vaesenc", { XM, Vex, EXx }, PREFIX_DATA },
6338 { "vaesenclast", { XM, Vex, EXx }, PREFIX_DATA },
6339 { "vaesdec", { XM, Vex, EXx }, PREFIX_DATA },
6340 { "vaesdeclast", { XM, Vex, EXx }, PREFIX_DATA },
6341 /* e0 */
6342 { Bad_Opcode },
6343 { Bad_Opcode },
6344 { Bad_Opcode },
6345 { Bad_Opcode },
6346 { Bad_Opcode },
6347 { Bad_Opcode },
6348 { Bad_Opcode },
6349 { Bad_Opcode },
6350 /* e8 */
6351 { Bad_Opcode },
6352 { Bad_Opcode },
6353 { Bad_Opcode },
6354 { Bad_Opcode },
6355 { Bad_Opcode },
6356 { Bad_Opcode },
6357 { Bad_Opcode },
6358 { Bad_Opcode },
6359 /* f0 */
6360 { Bad_Opcode },
6361 { Bad_Opcode },
6362 { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6363 { VEX_LEN_TABLE (VEX_LEN_0F38F3) },
6364 { Bad_Opcode },
6365 { VEX_LEN_TABLE (VEX_LEN_0F38F5) },
6366 { VEX_LEN_TABLE (VEX_LEN_0F38F6) },
6367 { VEX_LEN_TABLE (VEX_LEN_0F38F7) },
6368 /* f8 */
6369 { Bad_Opcode },
6370 { Bad_Opcode },
6371 { Bad_Opcode },
6372 { Bad_Opcode },
6373 { Bad_Opcode },
6374 { Bad_Opcode },
6375 { Bad_Opcode },
6376 { Bad_Opcode },
6377 },
6378 /* VEX_0F3A */
6379 {
6380 /* 00 */
6381 { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6382 { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6383 { VEX_W_TABLE (VEX_W_0F3A02) },
6384 { Bad_Opcode },
6385 { VEX_W_TABLE (VEX_W_0F3A04) },
6386 { VEX_W_TABLE (VEX_W_0F3A05) },
6387 { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6388 { Bad_Opcode },
6389 /* 08 */
6390 { "vroundps", { XM, EXx, Ib }, PREFIX_DATA },
6391 { "vroundpd", { XM, EXx, Ib }, PREFIX_DATA },
6392 { "vroundss", { XMScalar, VexScalar, EXd, Ib }, PREFIX_DATA },
6393 { "vroundsd", { XMScalar, VexScalar, EXq, Ib }, PREFIX_DATA },
6394 { "vblendps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6395 { "vblendpd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6396 { "vpblendw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6397 { "vpalignr", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6398 /* 10 */
6399 { Bad_Opcode },
6400 { Bad_Opcode },
6401 { Bad_Opcode },
6402 { Bad_Opcode },
6403 { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6404 { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6405 { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6406 { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6407 /* 18 */
6408 { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6409 { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6410 { Bad_Opcode },
6411 { Bad_Opcode },
6412 { Bad_Opcode },
6413 { VEX_W_TABLE (VEX_W_0F3A1D) },
6414 { Bad_Opcode },
6415 { Bad_Opcode },
6416 /* 20 */
6417 { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6418 { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6419 { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6420 { Bad_Opcode },
6421 { Bad_Opcode },
6422 { Bad_Opcode },
6423 { Bad_Opcode },
6424 { Bad_Opcode },
6425 /* 28 */
6426 { Bad_Opcode },
6427 { Bad_Opcode },
6428 { Bad_Opcode },
6429 { Bad_Opcode },
6430 { Bad_Opcode },
6431 { Bad_Opcode },
6432 { Bad_Opcode },
6433 { Bad_Opcode },
6434 /* 30 */
6435 { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6436 { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6437 { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6438 { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6439 { Bad_Opcode },
6440 { Bad_Opcode },
6441 { Bad_Opcode },
6442 { Bad_Opcode },
6443 /* 38 */
6444 { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6445 { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6446 { Bad_Opcode },
6447 { Bad_Opcode },
6448 { Bad_Opcode },
6449 { Bad_Opcode },
6450 { Bad_Opcode },
6451 { Bad_Opcode },
6452 /* 40 */
6453 { "vdpps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6454 { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6455 { "vmpsadbw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6456 { Bad_Opcode },
6457 { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6458 { Bad_Opcode },
6459 { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6460 { Bad_Opcode },
6461 /* 48 */
6462 { "vpermil2ps", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6463 { "vpermil2pd", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6464 { VEX_W_TABLE (VEX_W_0F3A4A) },
6465 { VEX_W_TABLE (VEX_W_0F3A4B) },
6466 { VEX_W_TABLE (VEX_W_0F3A4C) },
6467 { Bad_Opcode },
6468 { Bad_Opcode },
6469 { Bad_Opcode },
6470 /* 50 */
6471 { Bad_Opcode },
6472 { Bad_Opcode },
6473 { Bad_Opcode },
6474 { Bad_Opcode },
6475 { Bad_Opcode },
6476 { Bad_Opcode },
6477 { Bad_Opcode },
6478 { Bad_Opcode },
6479 /* 58 */
6480 { Bad_Opcode },
6481 { Bad_Opcode },
6482 { Bad_Opcode },
6483 { Bad_Opcode },
6484 { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6485 { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6486 { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6487 { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6488 /* 60 */
6489 { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6490 { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6491 { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6492 { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6493 { Bad_Opcode },
6494 { Bad_Opcode },
6495 { Bad_Opcode },
6496 { Bad_Opcode },
6497 /* 68 */
6498 { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6499 { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6500 { "vfmaddss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6501 { "vfmaddsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6502 { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6503 { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6504 { "vfmsubss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6505 { "vfmsubsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6506 /* 70 */
6507 { Bad_Opcode },
6508 { Bad_Opcode },
6509 { Bad_Opcode },
6510 { Bad_Opcode },
6511 { Bad_Opcode },
6512 { Bad_Opcode },
6513 { Bad_Opcode },
6514 { Bad_Opcode },
6515 /* 78 */
6516 { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6517 { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6518 { "vfnmaddss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6519 { "vfnmaddsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6520 { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6521 { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6522 { "vfnmsubss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6523 { "vfnmsubsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6524 /* 80 */
6525 { Bad_Opcode },
6526 { Bad_Opcode },
6527 { Bad_Opcode },
6528 { Bad_Opcode },
6529 { Bad_Opcode },
6530 { Bad_Opcode },
6531 { Bad_Opcode },
6532 { Bad_Opcode },
6533 /* 88 */
6534 { Bad_Opcode },
6535 { Bad_Opcode },
6536 { Bad_Opcode },
6537 { Bad_Opcode },
6538 { Bad_Opcode },
6539 { Bad_Opcode },
6540 { Bad_Opcode },
6541 { Bad_Opcode },
6542 /* 90 */
6543 { Bad_Opcode },
6544 { Bad_Opcode },
6545 { Bad_Opcode },
6546 { Bad_Opcode },
6547 { Bad_Opcode },
6548 { Bad_Opcode },
6549 { Bad_Opcode },
6550 { Bad_Opcode },
6551 /* 98 */
6552 { Bad_Opcode },
6553 { Bad_Opcode },
6554 { Bad_Opcode },
6555 { Bad_Opcode },
6556 { Bad_Opcode },
6557 { Bad_Opcode },
6558 { Bad_Opcode },
6559 { Bad_Opcode },
6560 /* a0 */
6561 { Bad_Opcode },
6562 { Bad_Opcode },
6563 { Bad_Opcode },
6564 { Bad_Opcode },
6565 { Bad_Opcode },
6566 { Bad_Opcode },
6567 { Bad_Opcode },
6568 { Bad_Opcode },
6569 /* a8 */
6570 { Bad_Opcode },
6571 { Bad_Opcode },
6572 { Bad_Opcode },
6573 { Bad_Opcode },
6574 { Bad_Opcode },
6575 { Bad_Opcode },
6576 { Bad_Opcode },
6577 { Bad_Opcode },
6578 /* b0 */
6579 { Bad_Opcode },
6580 { Bad_Opcode },
6581 { Bad_Opcode },
6582 { Bad_Opcode },
6583 { Bad_Opcode },
6584 { Bad_Opcode },
6585 { Bad_Opcode },
6586 { Bad_Opcode },
6587 /* b8 */
6588 { Bad_Opcode },
6589 { Bad_Opcode },
6590 { Bad_Opcode },
6591 { Bad_Opcode },
6592 { Bad_Opcode },
6593 { Bad_Opcode },
6594 { Bad_Opcode },
6595 { Bad_Opcode },
6596 /* c0 */
6597 { Bad_Opcode },
6598 { Bad_Opcode },
6599 { Bad_Opcode },
6600 { Bad_Opcode },
6601 { Bad_Opcode },
6602 { Bad_Opcode },
6603 { Bad_Opcode },
6604 { Bad_Opcode },
6605 /* c8 */
6606 { Bad_Opcode },
6607 { Bad_Opcode },
6608 { Bad_Opcode },
6609 { Bad_Opcode },
6610 { Bad_Opcode },
6611 { Bad_Opcode },
6612 { VEX_W_TABLE (VEX_W_0F3ACE) },
6613 { VEX_W_TABLE (VEX_W_0F3ACF) },
6614 /* d0 */
6615 { Bad_Opcode },
6616 { Bad_Opcode },
6617 { Bad_Opcode },
6618 { Bad_Opcode },
6619 { Bad_Opcode },
6620 { Bad_Opcode },
6621 { Bad_Opcode },
6622 { Bad_Opcode },
6623 /* d8 */
6624 { Bad_Opcode },
6625 { Bad_Opcode },
6626 { Bad_Opcode },
6627 { Bad_Opcode },
6628 { Bad_Opcode },
6629 { Bad_Opcode },
6630 { Bad_Opcode },
6631 { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6632 /* e0 */
6633 { Bad_Opcode },
6634 { Bad_Opcode },
6635 { Bad_Opcode },
6636 { Bad_Opcode },
6637 { Bad_Opcode },
6638 { Bad_Opcode },
6639 { Bad_Opcode },
6640 { Bad_Opcode },
6641 /* e8 */
6642 { Bad_Opcode },
6643 { Bad_Opcode },
6644 { Bad_Opcode },
6645 { Bad_Opcode },
6646 { Bad_Opcode },
6647 { Bad_Opcode },
6648 { Bad_Opcode },
6649 { Bad_Opcode },
6650 /* f0 */
6651 { VEX_LEN_TABLE (VEX_LEN_0F3AF0) },
6652 { Bad_Opcode },
6653 { Bad_Opcode },
6654 { Bad_Opcode },
6655 { Bad_Opcode },
6656 { Bad_Opcode },
6657 { Bad_Opcode },
6658 { Bad_Opcode },
6659 /* f8 */
6660 { Bad_Opcode },
6661 { Bad_Opcode },
6662 { Bad_Opcode },
6663 { Bad_Opcode },
6664 { Bad_Opcode },
6665 { Bad_Opcode },
6666 { Bad_Opcode },
6667 { Bad_Opcode },
6668 },
6669 };
6670
6671 #include "i386-dis-evex.h"
6672
6673 static const struct dis386 vex_len_table[][2] = {
6674 /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6675 {
6676 { "vmovlpX", { XM, Vex, EXq }, PREFIX_OPCODE },
6677 },
6678
6679 /* VEX_LEN_0F12_P_0_M_1 */
6680 {
6681 { "vmovhlp%XS", { XM, Vex, EXq }, 0 },
6682 },
6683
6684 /* VEX_LEN_0F13_M_0 */
6685 {
6686 { "vmovlpX", { EXq, XM }, PREFIX_OPCODE },
6687 },
6688
6689 /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6690 {
6691 { "vmovhpX", { XM, Vex, EXq }, PREFIX_OPCODE },
6692 },
6693
6694 /* VEX_LEN_0F16_P_0_M_1 */
6695 {
6696 { "vmovlhp%XS", { XM, Vex, EXq }, 0 },
6697 },
6698
6699 /* VEX_LEN_0F17_M_0 */
6700 {
6701 { "vmovhpX", { EXq, XM }, PREFIX_OPCODE },
6702 },
6703
6704 /* VEX_LEN_0F41 */
6705 {
6706 { Bad_Opcode },
6707 { MOD_TABLE (MOD_VEX_0F41_L_1) },
6708 },
6709
6710 /* VEX_LEN_0F42 */
6711 {
6712 { Bad_Opcode },
6713 { MOD_TABLE (MOD_VEX_0F42_L_1) },
6714 },
6715
6716 /* VEX_LEN_0F44 */
6717 {
6718 { MOD_TABLE (MOD_VEX_0F44_L_0) },
6719 },
6720
6721 /* VEX_LEN_0F45 */
6722 {
6723 { Bad_Opcode },
6724 { MOD_TABLE (MOD_VEX_0F45_L_1) },
6725 },
6726
6727 /* VEX_LEN_0F46 */
6728 {
6729 { Bad_Opcode },
6730 { MOD_TABLE (MOD_VEX_0F46_L_1) },
6731 },
6732
6733 /* VEX_LEN_0F47 */
6734 {
6735 { Bad_Opcode },
6736 { MOD_TABLE (MOD_VEX_0F47_L_1) },
6737 },
6738
6739 /* VEX_LEN_0F4A */
6740 {
6741 { Bad_Opcode },
6742 { MOD_TABLE (MOD_VEX_0F4A_L_1) },
6743 },
6744
6745 /* VEX_LEN_0F4B */
6746 {
6747 { Bad_Opcode },
6748 { MOD_TABLE (MOD_VEX_0F4B_L_1) },
6749 },
6750
6751 /* VEX_LEN_0F6E */
6752 {
6753 { "vmovK", { XMScalar, Edq }, PREFIX_DATA },
6754 },
6755
6756 /* VEX_LEN_0F77 */
6757 {
6758 { "vzeroupper", { XX }, 0 },
6759 { "vzeroall", { XX }, 0 },
6760 },
6761
6762 /* VEX_LEN_0F7E_P_1 */
6763 {
6764 { "vmovq", { XMScalar, EXq }, 0 },
6765 },
6766
6767 /* VEX_LEN_0F7E_P_2 */
6768 {
6769 { "vmovK", { Edq, XMScalar }, 0 },
6770 },
6771
6772 /* VEX_LEN_0F90 */
6773 {
6774 { VEX_W_TABLE (VEX_W_0F90_L_0) },
6775 },
6776
6777 /* VEX_LEN_0F91 */
6778 {
6779 { MOD_TABLE (MOD_VEX_0F91_L_0) },
6780 },
6781
6782 /* VEX_LEN_0F92 */
6783 {
6784 { MOD_TABLE (MOD_VEX_0F92_L_0) },
6785 },
6786
6787 /* VEX_LEN_0F93 */
6788 {
6789 { MOD_TABLE (MOD_VEX_0F93_L_0) },
6790 },
6791
6792 /* VEX_LEN_0F98 */
6793 {
6794 { MOD_TABLE (MOD_VEX_0F98_L_0) },
6795 },
6796
6797 /* VEX_LEN_0F99 */
6798 {
6799 { MOD_TABLE (MOD_VEX_0F99_L_0) },
6800 },
6801
6802 /* VEX_LEN_0FAE_R_2_M_0 */
6803 {
6804 { "vldmxcsr", { Md }, 0 },
6805 },
6806
6807 /* VEX_LEN_0FAE_R_3_M_0 */
6808 {
6809 { "vstmxcsr", { Md }, 0 },
6810 },
6811
6812 /* VEX_LEN_0FC4 */
6813 {
6814 { "vpinsrw", { XM, Vex, Edw, Ib }, PREFIX_DATA },
6815 },
6816
6817 /* VEX_LEN_0FC5 */
6818 {
6819 { "vpextrw", { Gd, XS, Ib }, PREFIX_DATA },
6820 },
6821
6822 /* VEX_LEN_0FD6 */
6823 {
6824 { "vmovq", { EXqS, XMScalar }, PREFIX_DATA },
6825 },
6826
6827 /* VEX_LEN_0FF7 */
6828 {
6829 { "vmaskmovdqu", { XM, XS }, PREFIX_DATA },
6830 },
6831
6832 /* VEX_LEN_0F3816 */
6833 {
6834 { Bad_Opcode },
6835 { VEX_W_TABLE (VEX_W_0F3816_L_1) },
6836 },
6837
6838 /* VEX_LEN_0F3819 */
6839 {
6840 { Bad_Opcode },
6841 { VEX_W_TABLE (VEX_W_0F3819_L_1) },
6842 },
6843
6844 /* VEX_LEN_0F381A_M_0 */
6845 {
6846 { Bad_Opcode },
6847 { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) },
6848 },
6849
6850 /* VEX_LEN_0F3836 */
6851 {
6852 { Bad_Opcode },
6853 { VEX_W_TABLE (VEX_W_0F3836) },
6854 },
6855
6856 /* VEX_LEN_0F3841 */
6857 {
6858 { "vphminposuw", { XM, EXx }, PREFIX_DATA },
6859 },
6860
6861 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
6862 {
6863 { "ldtilecfg", { M }, 0 },
6864 },
6865
6866 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
6867 {
6868 { "tilerelease", { Skip_MODRM }, 0 },
6869 },
6870
6871 /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
6872 {
6873 { "sttilecfg", { M }, 0 },
6874 },
6875
6876 /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
6877 {
6878 { "tilezero", { TMM, Skip_MODRM }, 0 },
6879 },
6880
6881 /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
6882 {
6883 { "tilestored", { MVexSIBMEM, TMM }, 0 },
6884 },
6885 /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
6886 {
6887 { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
6888 },
6889
6890 /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
6891 {
6892 { "tileloadd", { TMM, MVexSIBMEM }, 0 },
6893 },
6894
6895 /* VEX_LEN_0F385A_M_0 */
6896 {
6897 { Bad_Opcode },
6898 { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) },
6899 },
6900
6901 /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
6902 {
6903 { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
6904 },
6905
6906 /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
6907 {
6908 { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
6909 },
6910
6911 /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
6912 {
6913 { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
6914 },
6915
6916 /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
6917 {
6918 { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
6919 },
6920
6921 /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
6922 {
6923 { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
6924 },
6925
6926 /* VEX_LEN_0F38DB */
6927 {
6928 { "vaesimc", { XM, EXx }, PREFIX_DATA },
6929 },
6930
6931 /* VEX_LEN_0F38F2 */
6932 {
6933 { "andnS", { Gdq, VexGdq, Edq }, PREFIX_OPCODE },
6934 },
6935
6936 /* VEX_LEN_0F38F3 */
6937 {
6938 { REG_TABLE(REG_VEX_0F38F3_L_0) },
6939 },
6940
6941 /* VEX_LEN_0F38F5 */
6942 {
6943 { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0) },
6944 },
6945
6946 /* VEX_LEN_0F38F6 */
6947 {
6948 { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0) },
6949 },
6950
6951 /* VEX_LEN_0F38F7 */
6952 {
6953 { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0) },
6954 },
6955
6956 /* VEX_LEN_0F3A00 */
6957 {
6958 { Bad_Opcode },
6959 { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
6960 },
6961
6962 /* VEX_LEN_0F3A01 */
6963 {
6964 { Bad_Opcode },
6965 { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
6966 },
6967
6968 /* VEX_LEN_0F3A06 */
6969 {
6970 { Bad_Opcode },
6971 { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
6972 },
6973
6974 /* VEX_LEN_0F3A14 */
6975 {
6976 { "vpextrb", { Edb, XM, Ib }, PREFIX_DATA },
6977 },
6978
6979 /* VEX_LEN_0F3A15 */
6980 {
6981 { "vpextrw", { Edw, XM, Ib }, PREFIX_DATA },
6982 },
6983
6984 /* VEX_LEN_0F3A16 */
6985 {
6986 { "vpextrK", { Edq, XM, Ib }, PREFIX_DATA },
6987 },
6988
6989 /* VEX_LEN_0F3A17 */
6990 {
6991 { "vextractps", { Ed, XM, Ib }, PREFIX_DATA },
6992 },
6993
6994 /* VEX_LEN_0F3A18 */
6995 {
6996 { Bad_Opcode },
6997 { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
6998 },
6999
7000 /* VEX_LEN_0F3A19 */
7001 {
7002 { Bad_Opcode },
7003 { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7004 },
7005
7006 /* VEX_LEN_0F3A20 */
7007 {
7008 { "vpinsrb", { XM, Vex, Edb, Ib }, PREFIX_DATA },
7009 },
7010
7011 /* VEX_LEN_0F3A21 */
7012 {
7013 { "vinsertps", { XM, Vex, EXd, Ib }, PREFIX_DATA },
7014 },
7015
7016 /* VEX_LEN_0F3A22 */
7017 {
7018 { "vpinsrK", { XM, Vex, Edq, Ib }, PREFIX_DATA },
7019 },
7020
7021 /* VEX_LEN_0F3A30 */
7022 {
7023 { MOD_TABLE (MOD_VEX_0F3A30_L_0) },
7024 },
7025
7026 /* VEX_LEN_0F3A31 */
7027 {
7028 { MOD_TABLE (MOD_VEX_0F3A31_L_0) },
7029 },
7030
7031 /* VEX_LEN_0F3A32 */
7032 {
7033 { MOD_TABLE (MOD_VEX_0F3A32_L_0) },
7034 },
7035
7036 /* VEX_LEN_0F3A33 */
7037 {
7038 { MOD_TABLE (MOD_VEX_0F3A33_L_0) },
7039 },
7040
7041 /* VEX_LEN_0F3A38 */
7042 {
7043 { Bad_Opcode },
7044 { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7045 },
7046
7047 /* VEX_LEN_0F3A39 */
7048 {
7049 { Bad_Opcode },
7050 { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7051 },
7052
7053 /* VEX_LEN_0F3A41 */
7054 {
7055 { "vdppd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7056 },
7057
7058 /* VEX_LEN_0F3A46 */
7059 {
7060 { Bad_Opcode },
7061 { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7062 },
7063
7064 /* VEX_LEN_0F3A60 */
7065 {
7066 { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7067 },
7068
7069 /* VEX_LEN_0F3A61 */
7070 {
7071 { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7072 },
7073
7074 /* VEX_LEN_0F3A62 */
7075 {
7076 { "vpcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
7077 },
7078
7079 /* VEX_LEN_0F3A63 */
7080 {
7081 { "vpcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
7082 },
7083
7084 /* VEX_LEN_0F3ADF */
7085 {
7086 { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7087 },
7088
7089 /* VEX_LEN_0F3AF0 */
7090 {
7091 { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
7092 },
7093
7094 /* VEX_LEN_0FXOP_08_85 */
7095 {
7096 { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
7097 },
7098
7099 /* VEX_LEN_0FXOP_08_86 */
7100 {
7101 { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
7102 },
7103
7104 /* VEX_LEN_0FXOP_08_87 */
7105 {
7106 { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
7107 },
7108
7109 /* VEX_LEN_0FXOP_08_8E */
7110 {
7111 { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
7112 },
7113
7114 /* VEX_LEN_0FXOP_08_8F */
7115 {
7116 { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
7117 },
7118
7119 /* VEX_LEN_0FXOP_08_95 */
7120 {
7121 { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
7122 },
7123
7124 /* VEX_LEN_0FXOP_08_96 */
7125 {
7126 { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
7127 },
7128
7129 /* VEX_LEN_0FXOP_08_97 */
7130 {
7131 { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
7132 },
7133
7134 /* VEX_LEN_0FXOP_08_9E */
7135 {
7136 { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
7137 },
7138
7139 /* VEX_LEN_0FXOP_08_9F */
7140 {
7141 { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
7142 },
7143
7144 /* VEX_LEN_0FXOP_08_A3 */
7145 {
7146 { "vpperm", { XM, Vex, EXx, XMVexI4 }, 0 },
7147 },
7148
7149 /* VEX_LEN_0FXOP_08_A6 */
7150 {
7151 { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
7152 },
7153
7154 /* VEX_LEN_0FXOP_08_B6 */
7155 {
7156 { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
7157 },
7158
7159 /* VEX_LEN_0FXOP_08_C0 */
7160 {
7161 { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
7162 },
7163
7164 /* VEX_LEN_0FXOP_08_C1 */
7165 {
7166 { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
7167 },
7168
7169 /* VEX_LEN_0FXOP_08_C2 */
7170 {
7171 { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
7172 },
7173
7174 /* VEX_LEN_0FXOP_08_C3 */
7175 {
7176 { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
7177 },
7178
7179 /* VEX_LEN_0FXOP_08_CC */
7180 {
7181 { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
7182 },
7183
7184 /* VEX_LEN_0FXOP_08_CD */
7185 {
7186 { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
7187 },
7188
7189 /* VEX_LEN_0FXOP_08_CE */
7190 {
7191 { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
7192 },
7193
7194 /* VEX_LEN_0FXOP_08_CF */
7195 {
7196 { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
7197 },
7198
7199 /* VEX_LEN_0FXOP_08_EC */
7200 {
7201 { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
7202 },
7203
7204 /* VEX_LEN_0FXOP_08_ED */
7205 {
7206 { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
7207 },
7208
7209 /* VEX_LEN_0FXOP_08_EE */
7210 {
7211 { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
7212 },
7213
7214 /* VEX_LEN_0FXOP_08_EF */
7215 {
7216 { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
7217 },
7218
7219 /* VEX_LEN_0FXOP_09_01 */
7220 {
7221 { REG_TABLE (REG_XOP_09_01_L_0) },
7222 },
7223
7224 /* VEX_LEN_0FXOP_09_02 */
7225 {
7226 { REG_TABLE (REG_XOP_09_02_L_0) },
7227 },
7228
7229 /* VEX_LEN_0FXOP_09_12_M_1 */
7230 {
7231 { REG_TABLE (REG_XOP_09_12_M_1_L_0) },
7232 },
7233
7234 /* VEX_LEN_0FXOP_09_82_W_0 */
7235 {
7236 { "vfrczss", { XM, EXd }, 0 },
7237 },
7238
7239 /* VEX_LEN_0FXOP_09_83_W_0 */
7240 {
7241 { "vfrczsd", { XM, EXq }, 0 },
7242 },
7243
7244 /* VEX_LEN_0FXOP_09_90 */
7245 {
7246 { "vprotb", { XM, EXx, VexW }, 0 },
7247 },
7248
7249 /* VEX_LEN_0FXOP_09_91 */
7250 {
7251 { "vprotw", { XM, EXx, VexW }, 0 },
7252 },
7253
7254 /* VEX_LEN_0FXOP_09_92 */
7255 {
7256 { "vprotd", { XM, EXx, VexW }, 0 },
7257 },
7258
7259 /* VEX_LEN_0FXOP_09_93 */
7260 {
7261 { "vprotq", { XM, EXx, VexW }, 0 },
7262 },
7263
7264 /* VEX_LEN_0FXOP_09_94 */
7265 {
7266 { "vpshlb", { XM, EXx, VexW }, 0 },
7267 },
7268
7269 /* VEX_LEN_0FXOP_09_95 */
7270 {
7271 { "vpshlw", { XM, EXx, VexW }, 0 },
7272 },
7273
7274 /* VEX_LEN_0FXOP_09_96 */
7275 {
7276 { "vpshld", { XM, EXx, VexW }, 0 },
7277 },
7278
7279 /* VEX_LEN_0FXOP_09_97 */
7280 {
7281 { "vpshlq", { XM, EXx, VexW }, 0 },
7282 },
7283
7284 /* VEX_LEN_0FXOP_09_98 */
7285 {
7286 { "vpshab", { XM, EXx, VexW }, 0 },
7287 },
7288
7289 /* VEX_LEN_0FXOP_09_99 */
7290 {
7291 { "vpshaw", { XM, EXx, VexW }, 0 },
7292 },
7293
7294 /* VEX_LEN_0FXOP_09_9A */
7295 {
7296 { "vpshad", { XM, EXx, VexW }, 0 },
7297 },
7298
7299 /* VEX_LEN_0FXOP_09_9B */
7300 {
7301 { "vpshaq", { XM, EXx, VexW }, 0 },
7302 },
7303
7304 /* VEX_LEN_0FXOP_09_C1 */
7305 {
7306 { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
7307 },
7308
7309 /* VEX_LEN_0FXOP_09_C2 */
7310 {
7311 { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
7312 },
7313
7314 /* VEX_LEN_0FXOP_09_C3 */
7315 {
7316 { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
7317 },
7318
7319 /* VEX_LEN_0FXOP_09_C6 */
7320 {
7321 { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
7322 },
7323
7324 /* VEX_LEN_0FXOP_09_C7 */
7325 {
7326 { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
7327 },
7328
7329 /* VEX_LEN_0FXOP_09_CB */
7330 {
7331 { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
7332 },
7333
7334 /* VEX_LEN_0FXOP_09_D1 */
7335 {
7336 { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
7337 },
7338
7339 /* VEX_LEN_0FXOP_09_D2 */
7340 {
7341 { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
7342 },
7343
7344 /* VEX_LEN_0FXOP_09_D3 */
7345 {
7346 { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
7347 },
7348
7349 /* VEX_LEN_0FXOP_09_D6 */
7350 {
7351 { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
7352 },
7353
7354 /* VEX_LEN_0FXOP_09_D7 */
7355 {
7356 { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
7357 },
7358
7359 /* VEX_LEN_0FXOP_09_DB */
7360 {
7361 { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
7362 },
7363
7364 /* VEX_LEN_0FXOP_09_E1 */
7365 {
7366 { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
7367 },
7368
7369 /* VEX_LEN_0FXOP_09_E2 */
7370 {
7371 { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
7372 },
7373
7374 /* VEX_LEN_0FXOP_09_E3 */
7375 {
7376 { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
7377 },
7378
7379 /* VEX_LEN_0FXOP_0A_12 */
7380 {
7381 { REG_TABLE (REG_XOP_0A_12_L_0) },
7382 },
7383 };
7384
7385 #include "i386-dis-evex-len.h"
7386
7387 static const struct dis386 vex_w_table[][2] = {
7388 {
7389 /* VEX_W_0F41_L_1_M_1 */
7390 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_0) },
7391 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_1) },
7392 },
7393 {
7394 /* VEX_W_0F42_L_1_M_1 */
7395 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_0) },
7396 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_1) },
7397 },
7398 {
7399 /* VEX_W_0F44_L_0_M_1 */
7400 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_0) },
7401 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_1) },
7402 },
7403 {
7404 /* VEX_W_0F45_L_1_M_1 */
7405 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_0) },
7406 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_1) },
7407 },
7408 {
7409 /* VEX_W_0F46_L_1_M_1 */
7410 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_0) },
7411 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_1) },
7412 },
7413 {
7414 /* VEX_W_0F47_L_1_M_1 */
7415 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_0) },
7416 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_1) },
7417 },
7418 {
7419 /* VEX_W_0F4A_L_1_M_1 */
7420 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_0) },
7421 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_1) },
7422 },
7423 {
7424 /* VEX_W_0F4B_L_1_M_1 */
7425 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_0) },
7426 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_1) },
7427 },
7428 {
7429 /* VEX_W_0F90_L_0 */
7430 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0) },
7431 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1) },
7432 },
7433 {
7434 /* VEX_W_0F91_L_0_M_0 */
7435 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_0) },
7436 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_1) },
7437 },
7438 {
7439 /* VEX_W_0F92_L_0_M_1 */
7440 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_0) },
7441 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_1) },
7442 },
7443 {
7444 /* VEX_W_0F93_L_0_M_1 */
7445 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_0) },
7446 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_1) },
7447 },
7448 {
7449 /* VEX_W_0F98_L_0_M_1 */
7450 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_0) },
7451 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_1) },
7452 },
7453 {
7454 /* VEX_W_0F99_L_0_M_1 */
7455 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_0) },
7456 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_1) },
7457 },
7458 {
7459 /* VEX_W_0F380C */
7460 { "vpermilps", { XM, Vex, EXx }, PREFIX_DATA },
7461 },
7462 {
7463 /* VEX_W_0F380D */
7464 { "vpermilpd", { XM, Vex, EXx }, PREFIX_DATA },
7465 },
7466 {
7467 /* VEX_W_0F380E */
7468 { "vtestps", { XM, EXx }, PREFIX_DATA },
7469 },
7470 {
7471 /* VEX_W_0F380F */
7472 { "vtestpd", { XM, EXx }, PREFIX_DATA },
7473 },
7474 {
7475 /* VEX_W_0F3813 */
7476 { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7477 },
7478 {
7479 /* VEX_W_0F3816_L_1 */
7480 { "vpermps", { XM, Vex, EXx }, PREFIX_DATA },
7481 },
7482 {
7483 /* VEX_W_0F3818 */
7484 { "vbroadcastss", { XM, EXd }, PREFIX_DATA },
7485 },
7486 {
7487 /* VEX_W_0F3819_L_1 */
7488 { "vbroadcastsd", { XM, EXq }, PREFIX_DATA },
7489 },
7490 {
7491 /* VEX_W_0F381A_M_0_L_1 */
7492 { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7493 },
7494 {
7495 /* VEX_W_0F382C_M_0 */
7496 { "vmaskmovps", { XM, Vex, Mx }, PREFIX_DATA },
7497 },
7498 {
7499 /* VEX_W_0F382D_M_0 */
7500 { "vmaskmovpd", { XM, Vex, Mx }, PREFIX_DATA },
7501 },
7502 {
7503 /* VEX_W_0F382E_M_0 */
7504 { "vmaskmovps", { Mx, Vex, XM }, PREFIX_DATA },
7505 },
7506 {
7507 /* VEX_W_0F382F_M_0 */
7508 { "vmaskmovpd", { Mx, Vex, XM }, PREFIX_DATA },
7509 },
7510 {
7511 /* VEX_W_0F3836 */
7512 { "vpermd", { XM, Vex, EXx }, PREFIX_DATA },
7513 },
7514 {
7515 /* VEX_W_0F3846 */
7516 { "vpsravd", { XM, Vex, EXx }, PREFIX_DATA },
7517 },
7518 {
7519 /* VEX_W_0F3849_X86_64_P_0 */
7520 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
7521 },
7522 {
7523 /* VEX_W_0F3849_X86_64_P_2 */
7524 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
7525 },
7526 {
7527 /* VEX_W_0F3849_X86_64_P_3 */
7528 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
7529 },
7530 {
7531 /* VEX_W_0F384B_X86_64_P_1 */
7532 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
7533 },
7534 {
7535 /* VEX_W_0F384B_X86_64_P_2 */
7536 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
7537 },
7538 {
7539 /* VEX_W_0F384B_X86_64_P_3 */
7540 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
7541 },
7542 {
7543 /* VEX_W_0F3850 */
7544 { "%XV vpdpbusd", { XM, Vex, EXx }, 0 },
7545 },
7546 {
7547 /* VEX_W_0F3851 */
7548 { "%XV vpdpbusds", { XM, Vex, EXx }, 0 },
7549 },
7550 {
7551 /* VEX_W_0F3852 */
7552 { "%XV vpdpwssd", { XM, Vex, EXx }, 0 },
7553 },
7554 {
7555 /* VEX_W_0F3853 */
7556 { "%XV vpdpwssds", { XM, Vex, EXx }, 0 },
7557 },
7558 {
7559 /* VEX_W_0F3858 */
7560 { "vpbroadcastd", { XM, EXd }, PREFIX_DATA },
7561 },
7562 {
7563 /* VEX_W_0F3859 */
7564 { "vpbroadcastq", { XM, EXq }, PREFIX_DATA },
7565 },
7566 {
7567 /* VEX_W_0F385A_M_0_L_0 */
7568 { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7569 },
7570 {
7571 /* VEX_W_0F385C_X86_64_P_1 */
7572 { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
7573 },
7574 {
7575 /* VEX_W_0F385E_X86_64_P_0 */
7576 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
7577 },
7578 {
7579 /* VEX_W_0F385E_X86_64_P_1 */
7580 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
7581 },
7582 {
7583 /* VEX_W_0F385E_X86_64_P_2 */
7584 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
7585 },
7586 {
7587 /* VEX_W_0F385E_X86_64_P_3 */
7588 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
7589 },
7590 {
7591 /* VEX_W_0F3878 */
7592 { "vpbroadcastb", { XM, EXb }, PREFIX_DATA },
7593 },
7594 {
7595 /* VEX_W_0F3879 */
7596 { "vpbroadcastw", { XM, EXw }, PREFIX_DATA },
7597 },
7598 {
7599 /* VEX_W_0F38CF */
7600 { "vgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7601 },
7602 {
7603 /* VEX_W_0F3A00_L_1 */
7604 { Bad_Opcode },
7605 { "vpermq", { XM, EXx, Ib }, PREFIX_DATA },
7606 },
7607 {
7608 /* VEX_W_0F3A01_L_1 */
7609 { Bad_Opcode },
7610 { "vpermpd", { XM, EXx, Ib }, PREFIX_DATA },
7611 },
7612 {
7613 /* VEX_W_0F3A02 */
7614 { "vpblendd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7615 },
7616 {
7617 /* VEX_W_0F3A04 */
7618 { "vpermilps", { XM, EXx, Ib }, PREFIX_DATA },
7619 },
7620 {
7621 /* VEX_W_0F3A05 */
7622 { "vpermilpd", { XM, EXx, Ib }, PREFIX_DATA },
7623 },
7624 {
7625 /* VEX_W_0F3A06_L_1 */
7626 { "vperm2f128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7627 },
7628 {
7629 /* VEX_W_0F3A18_L_1 */
7630 { "vinsertf128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7631 },
7632 {
7633 /* VEX_W_0F3A19_L_1 */
7634 { "vextractf128", { EXxmm, XM, Ib }, PREFIX_DATA },
7635 },
7636 {
7637 /* VEX_W_0F3A1D */
7638 { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7639 },
7640 {
7641 /* VEX_W_0F3A38_L_1 */
7642 { "vinserti128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7643 },
7644 {
7645 /* VEX_W_0F3A39_L_1 */
7646 { "vextracti128", { EXxmm, XM, Ib }, PREFIX_DATA },
7647 },
7648 {
7649 /* VEX_W_0F3A46_L_1 */
7650 { "vperm2i128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7651 },
7652 {
7653 /* VEX_W_0F3A4A */
7654 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7655 },
7656 {
7657 /* VEX_W_0F3A4B */
7658 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7659 },
7660 {
7661 /* VEX_W_0F3A4C */
7662 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7663 },
7664 {
7665 /* VEX_W_0F3ACE */
7666 { Bad_Opcode },
7667 { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7668 },
7669 {
7670 /* VEX_W_0F3ACF */
7671 { Bad_Opcode },
7672 { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7673 },
7674 /* VEX_W_0FXOP_08_85_L_0 */
7675 {
7676 { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 },
7677 },
7678 /* VEX_W_0FXOP_08_86_L_0 */
7679 {
7680 { "vpmacsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7681 },
7682 /* VEX_W_0FXOP_08_87_L_0 */
7683 {
7684 { "vpmacssdql", { XM, Vex, EXx, XMVexI4 }, 0 },
7685 },
7686 /* VEX_W_0FXOP_08_8E_L_0 */
7687 {
7688 { "vpmacssdd", { XM, Vex, EXx, XMVexI4 }, 0 },
7689 },
7690 /* VEX_W_0FXOP_08_8F_L_0 */
7691 {
7692 { "vpmacssdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
7693 },
7694 /* VEX_W_0FXOP_08_95_L_0 */
7695 {
7696 { "vpmacsww", { XM, Vex, EXx, XMVexI4 }, 0 },
7697 },
7698 /* VEX_W_0FXOP_08_96_L_0 */
7699 {
7700 { "vpmacswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7701 },
7702 /* VEX_W_0FXOP_08_97_L_0 */
7703 {
7704 { "vpmacsdql", { XM, Vex, EXx, XMVexI4 }, 0 },
7705 },
7706 /* VEX_W_0FXOP_08_9E_L_0 */
7707 {
7708 { "vpmacsdd", { XM, Vex, EXx, XMVexI4 }, 0 },
7709 },
7710 /* VEX_W_0FXOP_08_9F_L_0 */
7711 {
7712 { "vpmacsdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
7713 },
7714 /* VEX_W_0FXOP_08_A6_L_0 */
7715 {
7716 { "vpmadcsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7717 },
7718 /* VEX_W_0FXOP_08_B6_L_0 */
7719 {
7720 { "vpmadcswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7721 },
7722 /* VEX_W_0FXOP_08_C0_L_0 */
7723 {
7724 { "vprotb", { XM, EXx, Ib }, 0 },
7725 },
7726 /* VEX_W_0FXOP_08_C1_L_0 */
7727 {
7728 { "vprotw", { XM, EXx, Ib }, 0 },
7729 },
7730 /* VEX_W_0FXOP_08_C2_L_0 */
7731 {
7732 { "vprotd", { XM, EXx, Ib }, 0 },
7733 },
7734 /* VEX_W_0FXOP_08_C3_L_0 */
7735 {
7736 { "vprotq", { XM, EXx, Ib }, 0 },
7737 },
7738 /* VEX_W_0FXOP_08_CC_L_0 */
7739 {
7740 { "vpcomb", { XM, Vex, EXx, VPCOM }, 0 },
7741 },
7742 /* VEX_W_0FXOP_08_CD_L_0 */
7743 {
7744 { "vpcomw", { XM, Vex, EXx, VPCOM }, 0 },
7745 },
7746 /* VEX_W_0FXOP_08_CE_L_0 */
7747 {
7748 { "vpcomd", { XM, Vex, EXx, VPCOM }, 0 },
7749 },
7750 /* VEX_W_0FXOP_08_CF_L_0 */
7751 {
7752 { "vpcomq", { XM, Vex, EXx, VPCOM }, 0 },
7753 },
7754 /* VEX_W_0FXOP_08_EC_L_0 */
7755 {
7756 { "vpcomub", { XM, Vex, EXx, VPCOM }, 0 },
7757 },
7758 /* VEX_W_0FXOP_08_ED_L_0 */
7759 {
7760 { "vpcomuw", { XM, Vex, EXx, VPCOM }, 0 },
7761 },
7762 /* VEX_W_0FXOP_08_EE_L_0 */
7763 {
7764 { "vpcomud", { XM, Vex, EXx, VPCOM }, 0 },
7765 },
7766 /* VEX_W_0FXOP_08_EF_L_0 */
7767 {
7768 { "vpcomuq", { XM, Vex, EXx, VPCOM }, 0 },
7769 },
7770 /* VEX_W_0FXOP_09_80 */
7771 {
7772 { "vfrczps", { XM, EXx }, 0 },
7773 },
7774 /* VEX_W_0FXOP_09_81 */
7775 {
7776 { "vfrczpd", { XM, EXx }, 0 },
7777 },
7778 /* VEX_W_0FXOP_09_82 */
7779 {
7780 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
7781 },
7782 /* VEX_W_0FXOP_09_83 */
7783 {
7784 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
7785 },
7786 /* VEX_W_0FXOP_09_C1_L_0 */
7787 {
7788 { "vphaddbw", { XM, EXxmm }, 0 },
7789 },
7790 /* VEX_W_0FXOP_09_C2_L_0 */
7791 {
7792 { "vphaddbd", { XM, EXxmm }, 0 },
7793 },
7794 /* VEX_W_0FXOP_09_C3_L_0 */
7795 {
7796 { "vphaddbq", { XM, EXxmm }, 0 },
7797 },
7798 /* VEX_W_0FXOP_09_C6_L_0 */
7799 {
7800 { "vphaddwd", { XM, EXxmm }, 0 },
7801 },
7802 /* VEX_W_0FXOP_09_C7_L_0 */
7803 {
7804 { "vphaddwq", { XM, EXxmm }, 0 },
7805 },
7806 /* VEX_W_0FXOP_09_CB_L_0 */
7807 {
7808 { "vphadddq", { XM, EXxmm }, 0 },
7809 },
7810 /* VEX_W_0FXOP_09_D1_L_0 */
7811 {
7812 { "vphaddubw", { XM, EXxmm }, 0 },
7813 },
7814 /* VEX_W_0FXOP_09_D2_L_0 */
7815 {
7816 { "vphaddubd", { XM, EXxmm }, 0 },
7817 },
7818 /* VEX_W_0FXOP_09_D3_L_0 */
7819 {
7820 { "vphaddubq", { XM, EXxmm }, 0 },
7821 },
7822 /* VEX_W_0FXOP_09_D6_L_0 */
7823 {
7824 { "vphadduwd", { XM, EXxmm }, 0 },
7825 },
7826 /* VEX_W_0FXOP_09_D7_L_0 */
7827 {
7828 { "vphadduwq", { XM, EXxmm }, 0 },
7829 },
7830 /* VEX_W_0FXOP_09_DB_L_0 */
7831 {
7832 { "vphaddudq", { XM, EXxmm }, 0 },
7833 },
7834 /* VEX_W_0FXOP_09_E1_L_0 */
7835 {
7836 { "vphsubbw", { XM, EXxmm }, 0 },
7837 },
7838 /* VEX_W_0FXOP_09_E2_L_0 */
7839 {
7840 { "vphsubwd", { XM, EXxmm }, 0 },
7841 },
7842 /* VEX_W_0FXOP_09_E3_L_0 */
7843 {
7844 { "vphsubdq", { XM, EXxmm }, 0 },
7845 },
7846
7847 #include "i386-dis-evex-w.h"
7848 };
7849
7850 static const struct dis386 mod_table[][2] = {
7851 {
7852 /* MOD_62_32BIT */
7853 { "bound{S|}", { Gv, Ma }, 0 },
7854 { EVEX_TABLE (EVEX_0F) },
7855 },
7856 {
7857 /* MOD_8D */
7858 { "leaS", { Gv, M }, 0 },
7859 },
7860 {
7861 /* MOD_C4_32BIT */
7862 { "lesS", { Gv, Mp }, 0 },
7863 { VEX_C4_TABLE (VEX_0F) },
7864 },
7865 {
7866 /* MOD_C5_32BIT */
7867 { "ldsS", { Gv, Mp }, 0 },
7868 { VEX_C5_TABLE (VEX_0F) },
7869 },
7870 {
7871 /* MOD_C6_REG_7 */
7872 { Bad_Opcode },
7873 { RM_TABLE (RM_C6_REG_7) },
7874 },
7875 {
7876 /* MOD_C7_REG_7 */
7877 { Bad_Opcode },
7878 { RM_TABLE (RM_C7_REG_7) },
7879 },
7880 {
7881 /* MOD_FF_REG_3 */
7882 { "{l|}call^", { indirEp }, 0 },
7883 },
7884 {
7885 /* MOD_FF_REG_5 */
7886 { "{l|}jmp^", { indirEp }, 0 },
7887 },
7888 {
7889 /* MOD_0F01_REG_0 */
7890 { X86_64_TABLE (X86_64_0F01_REG_0) },
7891 { RM_TABLE (RM_0F01_REG_0) },
7892 },
7893 {
7894 /* MOD_0F01_REG_1 */
7895 { X86_64_TABLE (X86_64_0F01_REG_1) },
7896 { RM_TABLE (RM_0F01_REG_1) },
7897 },
7898 {
7899 /* MOD_0F01_REG_2 */
7900 { X86_64_TABLE (X86_64_0F01_REG_2) },
7901 { RM_TABLE (RM_0F01_REG_2) },
7902 },
7903 {
7904 /* MOD_0F01_REG_3 */
7905 { X86_64_TABLE (X86_64_0F01_REG_3) },
7906 { RM_TABLE (RM_0F01_REG_3) },
7907 },
7908 {
7909 /* MOD_0F01_REG_5 */
7910 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
7911 { RM_TABLE (RM_0F01_REG_5_MOD_3) },
7912 },
7913 {
7914 /* MOD_0F01_REG_7 */
7915 { "invlpg", { Mb }, 0 },
7916 { RM_TABLE (RM_0F01_REG_7_MOD_3) },
7917 },
7918 {
7919 /* MOD_0F12_PREFIX_0 */
7920 { "movlpX", { XM, EXq }, 0 },
7921 { "movhlps", { XM, EXq }, 0 },
7922 },
7923 {
7924 /* MOD_0F12_PREFIX_2 */
7925 { "movlpX", { XM, EXq }, 0 },
7926 },
7927 {
7928 /* MOD_0F13 */
7929 { "movlpX", { EXq, XM }, PREFIX_OPCODE },
7930 },
7931 {
7932 /* MOD_0F16_PREFIX_0 */
7933 { "movhpX", { XM, EXq }, 0 },
7934 { "movlhps", { XM, EXq }, 0 },
7935 },
7936 {
7937 /* MOD_0F16_PREFIX_2 */
7938 { "movhpX", { XM, EXq }, 0 },
7939 },
7940 {
7941 /* MOD_0F17 */
7942 { "movhpX", { EXq, XM }, PREFIX_OPCODE },
7943 },
7944 {
7945 /* MOD_0F18_REG_0 */
7946 { "prefetchnta", { Mb }, 0 },
7947 { "nopQ", { Ev }, 0 },
7948 },
7949 {
7950 /* MOD_0F18_REG_1 */
7951 { "prefetcht0", { Mb }, 0 },
7952 { "nopQ", { Ev }, 0 },
7953 },
7954 {
7955 /* MOD_0F18_REG_2 */
7956 { "prefetcht1", { Mb }, 0 },
7957 { "nopQ", { Ev }, 0 },
7958 },
7959 {
7960 /* MOD_0F18_REG_3 */
7961 { "prefetcht2", { Mb }, 0 },
7962 { "nopQ", { Ev }, 0 },
7963 },
7964 {
7965 /* MOD_0F1A_PREFIX_0 */
7966 { "bndldx", { Gbnd, Mv_bnd }, 0 },
7967 { "nopQ", { Ev }, 0 },
7968 },
7969 {
7970 /* MOD_0F1B_PREFIX_0 */
7971 { "bndstx", { Mv_bnd, Gbnd }, 0 },
7972 { "nopQ", { Ev }, 0 },
7973 },
7974 {
7975 /* MOD_0F1B_PREFIX_1 */
7976 { "bndmk", { Gbnd, Mv_bnd }, 0 },
7977 { "nopQ", { Ev }, PREFIX_IGNORED },
7978 },
7979 {
7980 /* MOD_0F1C_PREFIX_0 */
7981 { REG_TABLE (REG_0F1C_P_0_MOD_0) },
7982 { "nopQ", { Ev }, 0 },
7983 },
7984 {
7985 /* MOD_0F1E_PREFIX_1 */
7986 { "nopQ", { Ev }, PREFIX_IGNORED },
7987 { REG_TABLE (REG_0F1E_P_1_MOD_3) },
7988 },
7989 {
7990 /* MOD_0F2B_PREFIX_0 */
7991 {"movntps", { Mx, XM }, PREFIX_OPCODE },
7992 },
7993 {
7994 /* MOD_0F2B_PREFIX_1 */
7995 {"movntss", { Md, XM }, PREFIX_OPCODE },
7996 },
7997 {
7998 /* MOD_0F2B_PREFIX_2 */
7999 {"movntpd", { Mx, XM }, PREFIX_OPCODE },
8000 },
8001 {
8002 /* MOD_0F2B_PREFIX_3 */
8003 {"movntsd", { Mq, XM }, PREFIX_OPCODE },
8004 },
8005 {
8006 /* MOD_0F50 */
8007 { Bad_Opcode },
8008 { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
8009 },
8010 {
8011 /* MOD_0F71 */
8012 { Bad_Opcode },
8013 { REG_TABLE (REG_0F71_MOD_0) },
8014 },
8015 {
8016 /* MOD_0F72 */
8017 { Bad_Opcode },
8018 { REG_TABLE (REG_0F72_MOD_0) },
8019 },
8020 {
8021 /* MOD_0F73 */
8022 { Bad_Opcode },
8023 { REG_TABLE (REG_0F73_MOD_0) },
8024 },
8025 {
8026 /* MOD_0FAE_REG_0 */
8027 { "fxsave", { FXSAVE }, 0 },
8028 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8029 },
8030 {
8031 /* MOD_0FAE_REG_1 */
8032 { "fxrstor", { FXSAVE }, 0 },
8033 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8034 },
8035 {
8036 /* MOD_0FAE_REG_2 */
8037 { "ldmxcsr", { Md }, 0 },
8038 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8039 },
8040 {
8041 /* MOD_0FAE_REG_3 */
8042 { "stmxcsr", { Md }, 0 },
8043 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8044 },
8045 {
8046 /* MOD_0FAE_REG_4 */
8047 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8048 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8049 },
8050 {
8051 /* MOD_0FAE_REG_5 */
8052 { "xrstor", { FXSAVE }, PREFIX_OPCODE },
8053 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8054 },
8055 {
8056 /* MOD_0FAE_REG_6 */
8057 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8058 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8059 },
8060 {
8061 /* MOD_0FAE_REG_7 */
8062 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8063 { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8064 },
8065 {
8066 /* MOD_0FB2 */
8067 { "lssS", { Gv, Mp }, 0 },
8068 },
8069 {
8070 /* MOD_0FB4 */
8071 { "lfsS", { Gv, Mp }, 0 },
8072 },
8073 {
8074 /* MOD_0FB5 */
8075 { "lgsS", { Gv, Mp }, 0 },
8076 },
8077 {
8078 /* MOD_0FC3 */
8079 { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
8080 },
8081 {
8082 /* MOD_0FC7_REG_3 */
8083 { "xrstors", { FXSAVE }, 0 },
8084 },
8085 {
8086 /* MOD_0FC7_REG_4 */
8087 { "xsavec", { FXSAVE }, 0 },
8088 },
8089 {
8090 /* MOD_0FC7_REG_5 */
8091 { "xsaves", { FXSAVE }, 0 },
8092 },
8093 {
8094 /* MOD_0FC7_REG_6 */
8095 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8096 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8097 },
8098 {
8099 /* MOD_0FC7_REG_7 */
8100 { "vmptrst", { Mq }, 0 },
8101 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8102 },
8103 {
8104 /* MOD_0FD7 */
8105 { Bad_Opcode },
8106 { "pmovmskb", { Gdq, MS }, 0 },
8107 },
8108 {
8109 /* MOD_0FE7_PREFIX_2 */
8110 { "movntdq", { Mx, XM }, 0 },
8111 },
8112 {
8113 /* MOD_0FF0_PREFIX_3 */
8114 { "lddqu", { XM, M }, 0 },
8115 },
8116 {
8117 /* MOD_0F382A */
8118 { "movntdqa", { XM, Mx }, PREFIX_DATA },
8119 },
8120 {
8121 /* MOD_0F38DC_PREFIX_1 */
8122 { "aesenc128kl", { XM, M }, 0 },
8123 { "loadiwkey", { XM, EXx }, 0 },
8124 },
8125 {
8126 /* MOD_0F38DD_PREFIX_1 */
8127 { "aesdec128kl", { XM, M }, 0 },
8128 },
8129 {
8130 /* MOD_0F38DE_PREFIX_1 */
8131 { "aesenc256kl", { XM, M }, 0 },
8132 },
8133 {
8134 /* MOD_0F38DF_PREFIX_1 */
8135 { "aesdec256kl", { XM, M }, 0 },
8136 },
8137 {
8138 /* MOD_0F38F5 */
8139 { "wrussK", { M, Gdq }, PREFIX_DATA },
8140 },
8141 {
8142 /* MOD_0F38F6_PREFIX_0 */
8143 { "wrssK", { M, Gdq }, PREFIX_OPCODE },
8144 },
8145 {
8146 /* MOD_0F38F8_PREFIX_1 */
8147 { "enqcmds", { Gva, M }, PREFIX_OPCODE },
8148 },
8149 {
8150 /* MOD_0F38F8_PREFIX_2 */
8151 { "movdir64b", { Gva, M }, PREFIX_OPCODE },
8152 },
8153 {
8154 /* MOD_0F38F8_PREFIX_3 */
8155 { "enqcmd", { Gva, M }, PREFIX_OPCODE },
8156 },
8157 {
8158 /* MOD_0F38F9 */
8159 { "movdiri", { Edq, Gdq }, PREFIX_OPCODE },
8160 },
8161 {
8162 /* MOD_0F38FA_PREFIX_1 */
8163 { Bad_Opcode },
8164 { "encodekey128", { Gd, Ed }, 0 },
8165 },
8166 {
8167 /* MOD_0F38FB_PREFIX_1 */
8168 { Bad_Opcode },
8169 { "encodekey256", { Gd, Ed }, 0 },
8170 },
8171 {
8172 /* MOD_0F3A0F_PREFIX_1 */
8173 { Bad_Opcode },
8174 { REG_TABLE (REG_0F3A0F_PREFIX_1_MOD_3) },
8175 },
8176 {
8177 /* MOD_VEX_0F12_PREFIX_0 */
8178 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
8179 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
8180 },
8181 {
8182 /* MOD_VEX_0F12_PREFIX_2 */
8183 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
8184 },
8185 {
8186 /* MOD_VEX_0F13 */
8187 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
8188 },
8189 {
8190 /* MOD_VEX_0F16_PREFIX_0 */
8191 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
8192 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
8193 },
8194 {
8195 /* MOD_VEX_0F16_PREFIX_2 */
8196 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
8197 },
8198 {
8199 /* MOD_VEX_0F17 */
8200 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
8201 },
8202 {
8203 /* MOD_VEX_0F2B */
8204 { "vmovntpX", { Mx, XM }, PREFIX_OPCODE },
8205 },
8206 {
8207 /* MOD_VEX_0F41_L_1 */
8208 { Bad_Opcode },
8209 { VEX_W_TABLE (VEX_W_0F41_L_1_M_1) },
8210 },
8211 {
8212 /* MOD_VEX_0F42_L_1 */
8213 { Bad_Opcode },
8214 { VEX_W_TABLE (VEX_W_0F42_L_1_M_1) },
8215 },
8216 {
8217 /* MOD_VEX_0F44_L_0 */
8218 { Bad_Opcode },
8219 { VEX_W_TABLE (VEX_W_0F44_L_0_M_1) },
8220 },
8221 {
8222 /* MOD_VEX_0F45_L_1 */
8223 { Bad_Opcode },
8224 { VEX_W_TABLE (VEX_W_0F45_L_1_M_1) },
8225 },
8226 {
8227 /* MOD_VEX_0F46_L_1 */
8228 { Bad_Opcode },
8229 { VEX_W_TABLE (VEX_W_0F46_L_1_M_1) },
8230 },
8231 {
8232 /* MOD_VEX_0F47_L_1 */
8233 { Bad_Opcode },
8234 { VEX_W_TABLE (VEX_W_0F47_L_1_M_1) },
8235 },
8236 {
8237 /* MOD_VEX_0F4A_L_1 */
8238 { Bad_Opcode },
8239 { VEX_W_TABLE (VEX_W_0F4A_L_1_M_1) },
8240 },
8241 {
8242 /* MOD_VEX_0F4B_L_1 */
8243 { Bad_Opcode },
8244 { VEX_W_TABLE (VEX_W_0F4B_L_1_M_1) },
8245 },
8246 {
8247 /* MOD_VEX_0F50 */
8248 { Bad_Opcode },
8249 { "vmovmskpX", { Gdq, XS }, PREFIX_OPCODE },
8250 },
8251 {
8252 /* MOD_VEX_0F71 */
8253 { Bad_Opcode },
8254 { REG_TABLE (REG_VEX_0F71_M_0) },
8255 },
8256 {
8257 /* MOD_VEX_0F72 */
8258 { Bad_Opcode },
8259 { REG_TABLE (REG_VEX_0F72_M_0) },
8260 },
8261 {
8262 /* MOD_VEX_0F73 */
8263 { Bad_Opcode },
8264 { REG_TABLE (REG_VEX_0F73_M_0) },
8265 },
8266 {
8267 /* MOD_VEX_0F91_L_0 */
8268 { VEX_W_TABLE (VEX_W_0F91_L_0_M_0) },
8269 },
8270 {
8271 /* MOD_VEX_0F92_L_0 */
8272 { Bad_Opcode },
8273 { VEX_W_TABLE (VEX_W_0F92_L_0_M_1) },
8274 },
8275 {
8276 /* MOD_VEX_0F93_L_0 */
8277 { Bad_Opcode },
8278 { VEX_W_TABLE (VEX_W_0F93_L_0_M_1) },
8279 },
8280 {
8281 /* MOD_VEX_0F98_L_0 */
8282 { Bad_Opcode },
8283 { VEX_W_TABLE (VEX_W_0F98_L_0_M_1) },
8284 },
8285 {
8286 /* MOD_VEX_0F99_L_0 */
8287 { Bad_Opcode },
8288 { VEX_W_TABLE (VEX_W_0F99_L_0_M_1) },
8289 },
8290 {
8291 /* MOD_VEX_0FAE_REG_2 */
8292 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
8293 },
8294 {
8295 /* MOD_VEX_0FAE_REG_3 */
8296 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
8297 },
8298 {
8299 /* MOD_VEX_0FD7 */
8300 { Bad_Opcode },
8301 { "vpmovmskb", { Gdq, XS }, PREFIX_DATA },
8302 },
8303 {
8304 /* MOD_VEX_0FE7 */
8305 { "vmovntdq", { Mx, XM }, PREFIX_DATA },
8306 },
8307 {
8308 /* MOD_VEX_0FF0_PREFIX_3 */
8309 { "vlddqu", { XM, M }, 0 },
8310 },
8311 {
8312 /* MOD_VEX_0F381A */
8313 { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) },
8314 },
8315 {
8316 /* MOD_VEX_0F382A */
8317 { "vmovntdqa", { XM, Mx }, PREFIX_DATA },
8318 },
8319 {
8320 /* MOD_VEX_0F382C */
8321 { VEX_W_TABLE (VEX_W_0F382C_M_0) },
8322 },
8323 {
8324 /* MOD_VEX_0F382D */
8325 { VEX_W_TABLE (VEX_W_0F382D_M_0) },
8326 },
8327 {
8328 /* MOD_VEX_0F382E */
8329 { VEX_W_TABLE (VEX_W_0F382E_M_0) },
8330 },
8331 {
8332 /* MOD_VEX_0F382F */
8333 { VEX_W_TABLE (VEX_W_0F382F_M_0) },
8334 },
8335 {
8336 /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8337 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
8338 { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
8339 },
8340 {
8341 /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8342 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
8343 },
8344 {
8345 /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8346 { Bad_Opcode },
8347 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
8348 },
8349 {
8350 /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8351 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
8352 },
8353 {
8354 /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8355 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
8356 },
8357 {
8358 /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8359 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
8360 },
8361 {
8362 /* MOD_VEX_0F385A */
8363 { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) },
8364 },
8365 {
8366 /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8367 { Bad_Opcode },
8368 { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
8369 },
8370 {
8371 /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8372 { Bad_Opcode },
8373 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
8374 },
8375 {
8376 /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8377 { Bad_Opcode },
8378 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
8379 },
8380 {
8381 /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8382 { Bad_Opcode },
8383 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
8384 },
8385 {
8386 /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8387 { Bad_Opcode },
8388 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
8389 },
8390 {
8391 /* MOD_VEX_0F388C */
8392 { "vpmaskmov%DQ", { XM, Vex, Mx }, PREFIX_DATA },
8393 },
8394 {
8395 /* MOD_VEX_0F388E */
8396 { "vpmaskmov%DQ", { Mx, Vex, XM }, PREFIX_DATA },
8397 },
8398 {
8399 /* MOD_VEX_0F3A30_L_0 */
8400 { Bad_Opcode },
8401 { "kshiftr%BW", { MaskG, MaskE, Ib }, PREFIX_DATA },
8402 },
8403 {
8404 /* MOD_VEX_0F3A31_L_0 */
8405 { Bad_Opcode },
8406 { "kshiftr%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA },
8407 },
8408 {
8409 /* MOD_VEX_0F3A32_L_0 */
8410 { Bad_Opcode },
8411 { "kshiftl%BW", { MaskG, MaskE, Ib }, PREFIX_DATA },
8412 },
8413 {
8414 /* MOD_VEX_0F3A33_L_0 */
8415 { Bad_Opcode },
8416 { "kshiftl%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA },
8417 },
8418 {
8419 /* MOD_XOP_09_12 */
8420 { Bad_Opcode },
8421 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
8422 },
8423
8424 #include "i386-dis-evex-mod.h"
8425 };
8426
8427 static const struct dis386 rm_table[][8] = {
8428 {
8429 /* RM_C6_REG_7 */
8430 { "xabort", { Skip_MODRM, Ib }, 0 },
8431 },
8432 {
8433 /* RM_C7_REG_7 */
8434 { "xbeginT", { Skip_MODRM, Jdqw }, 0 },
8435 },
8436 {
8437 /* RM_0F01_REG_0 */
8438 { "enclv", { Skip_MODRM }, 0 },
8439 { "vmcall", { Skip_MODRM }, 0 },
8440 { "vmlaunch", { Skip_MODRM }, 0 },
8441 { "vmresume", { Skip_MODRM }, 0 },
8442 { "vmxoff", { Skip_MODRM }, 0 },
8443 { "pconfig", { Skip_MODRM }, 0 },
8444 },
8445 {
8446 /* RM_0F01_REG_1 */
8447 { "monitor", { { OP_Monitor, 0 } }, 0 },
8448 { "mwait", { { OP_Mwait, 0 } }, 0 },
8449 { "clac", { Skip_MODRM }, 0 },
8450 { "stac", { Skip_MODRM }, 0 },
8451 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
8452 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
8453 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
8454 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
8455 },
8456 {
8457 /* RM_0F01_REG_2 */
8458 { "xgetbv", { Skip_MODRM }, 0 },
8459 { "xsetbv", { Skip_MODRM }, 0 },
8460 { Bad_Opcode },
8461 { Bad_Opcode },
8462 { "vmfunc", { Skip_MODRM }, 0 },
8463 { "xend", { Skip_MODRM }, 0 },
8464 { "xtest", { Skip_MODRM }, 0 },
8465 { "enclu", { Skip_MODRM }, 0 },
8466 },
8467 {
8468 /* RM_0F01_REG_3 */
8469 { "vmrun", { Skip_MODRM }, 0 },
8470 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8471 { "vmload", { Skip_MODRM }, 0 },
8472 { "vmsave", { Skip_MODRM }, 0 },
8473 { "stgi", { Skip_MODRM }, 0 },
8474 { "clgi", { Skip_MODRM }, 0 },
8475 { "skinit", { Skip_MODRM }, 0 },
8476 { "invlpga", { Skip_MODRM }, 0 },
8477 },
8478 {
8479 /* RM_0F01_REG_5_MOD_3 */
8480 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8481 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8482 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8483 { Bad_Opcode },
8484 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) },
8485 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) },
8486 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) },
8487 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) },
8488 },
8489 {
8490 /* RM_0F01_REG_7_MOD_3 */
8491 { "swapgs", { Skip_MODRM }, 0 },
8492 { "rdtscp", { Skip_MODRM }, 0 },
8493 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8494 { "mwaitx", { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8495 { "clzero", { Skip_MODRM }, 0 },
8496 { "rdpru", { Skip_MODRM }, 0 },
8497 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) },
8498 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) },
8499 },
8500 {
8501 /* RM_0F1E_P_1_MOD_3_REG_7 */
8502 { "nopQ", { Ev }, PREFIX_IGNORED },
8503 { "nopQ", { Ev }, PREFIX_IGNORED },
8504 { "endbr64", { Skip_MODRM }, 0 },
8505 { "endbr32", { Skip_MODRM }, 0 },
8506 { "nopQ", { Ev }, PREFIX_IGNORED },
8507 { "nopQ", { Ev }, PREFIX_IGNORED },
8508 { "nopQ", { Ev }, PREFIX_IGNORED },
8509 { "nopQ", { Ev }, PREFIX_IGNORED },
8510 },
8511 {
8512 /* RM_0FAE_REG_6_MOD_3 */
8513 { "mfence", { Skip_MODRM }, 0 },
8514 },
8515 {
8516 /* RM_0FAE_REG_7_MOD_3 */
8517 { "sfence", { Skip_MODRM }, 0 },
8518 },
8519 {
8520 /* RM_0F3A0F_P_1_MOD_3_REG_0 */
8521 { "hreset", { Skip_MODRM, Ib }, 0 },
8522 },
8523 {
8524 /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
8525 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
8526 },
8527 };
8528
8529 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8530
8531 /* We use the high bit to indicate different name for the same
8532 prefix. */
8533 #define REP_PREFIX (0xf3 | 0x100)
8534 #define XACQUIRE_PREFIX (0xf2 | 0x200)
8535 #define XRELEASE_PREFIX (0xf3 | 0x400)
8536 #define BND_PREFIX (0xf2 | 0x400)
8537 #define NOTRACK_PREFIX (0x3e | 0x100)
8538
8539 static int
8540 ckprefix (instr_info *ins)
8541 {
8542 int newrex, i, length;
8543 ins->rex = 0;
8544 ins->prefixes = 0;
8545 ins->used_prefixes = 0;
8546 ins->rex_used = 0;
8547 ins->evex_used = 0;
8548 ins->last_lock_prefix = -1;
8549 ins->last_repz_prefix = -1;
8550 ins->last_repnz_prefix = -1;
8551 ins->last_data_prefix = -1;
8552 ins->last_addr_prefix = -1;
8553 ins->last_rex_prefix = -1;
8554 ins->last_seg_prefix = -1;
8555 ins->fwait_prefix = -1;
8556 ins->active_seg_prefix = 0;
8557 for (i = 0; i < (int) ARRAY_SIZE (ins->all_prefixes); i++)
8558 ins->all_prefixes[i] = 0;
8559 i = 0;
8560 length = 0;
8561 /* The maximum instruction length is 15bytes. */
8562 while (length < MAX_CODE_LENGTH - 1)
8563 {
8564 FETCH_DATA (ins->info, ins->codep + 1);
8565 newrex = 0;
8566 switch (*ins->codep)
8567 {
8568 /* REX prefixes family. */
8569 case 0x40:
8570 case 0x41:
8571 case 0x42:
8572 case 0x43:
8573 case 0x44:
8574 case 0x45:
8575 case 0x46:
8576 case 0x47:
8577 case 0x48:
8578 case 0x49:
8579 case 0x4a:
8580 case 0x4b:
8581 case 0x4c:
8582 case 0x4d:
8583 case 0x4e:
8584 case 0x4f:
8585 if (ins->address_mode == mode_64bit)
8586 newrex = *ins->codep;
8587 else
8588 return 1;
8589 ins->last_rex_prefix = i;
8590 break;
8591 case 0xf3:
8592 ins->prefixes |= PREFIX_REPZ;
8593 ins->last_repz_prefix = i;
8594 break;
8595 case 0xf2:
8596 ins->prefixes |= PREFIX_REPNZ;
8597 ins->last_repnz_prefix = i;
8598 break;
8599 case 0xf0:
8600 ins->prefixes |= PREFIX_LOCK;
8601 ins->last_lock_prefix = i;
8602 break;
8603 case 0x2e:
8604 ins->prefixes |= PREFIX_CS;
8605 ins->last_seg_prefix = i;
8606 if (ins->address_mode != mode_64bit)
8607 ins->active_seg_prefix = PREFIX_CS;
8608 break;
8609 case 0x36:
8610 ins->prefixes |= PREFIX_SS;
8611 ins->last_seg_prefix = i;
8612 if (ins->address_mode != mode_64bit)
8613 ins->active_seg_prefix = PREFIX_SS;
8614 break;
8615 case 0x3e:
8616 ins->prefixes |= PREFIX_DS;
8617 ins->last_seg_prefix = i;
8618 if (ins->address_mode != mode_64bit)
8619 ins->active_seg_prefix = PREFIX_DS;
8620 break;
8621 case 0x26:
8622 ins->prefixes |= PREFIX_ES;
8623 ins->last_seg_prefix = i;
8624 if (ins->address_mode != mode_64bit)
8625 ins->active_seg_prefix = PREFIX_ES;
8626 break;
8627 case 0x64:
8628 ins->prefixes |= PREFIX_FS;
8629 ins->last_seg_prefix = i;
8630 ins->active_seg_prefix = PREFIX_FS;
8631 break;
8632 case 0x65:
8633 ins->prefixes |= PREFIX_GS;
8634 ins->last_seg_prefix = i;
8635 ins->active_seg_prefix = PREFIX_GS;
8636 break;
8637 case 0x66:
8638 ins->prefixes |= PREFIX_DATA;
8639 ins->last_data_prefix = i;
8640 break;
8641 case 0x67:
8642 ins->prefixes |= PREFIX_ADDR;
8643 ins->last_addr_prefix = i;
8644 break;
8645 case FWAIT_OPCODE:
8646 /* fwait is really an instruction. If there are prefixes
8647 before the fwait, they belong to the fwait, *not* to the
8648 following instruction. */
8649 ins->fwait_prefix = i;
8650 if (ins->prefixes || ins->rex)
8651 {
8652 ins->prefixes |= PREFIX_FWAIT;
8653 ins->codep++;
8654 /* This ensures that the previous REX prefixes are noticed
8655 as unused prefixes, as in the return case below. */
8656 ins->rex_used = ins->rex;
8657 return 1;
8658 }
8659 ins->prefixes = PREFIX_FWAIT;
8660 break;
8661 default:
8662 return 1;
8663 }
8664 /* Rex is ignored when followed by another prefix. */
8665 if (ins->rex)
8666 {
8667 ins->rex_used = ins->rex;
8668 return 1;
8669 }
8670 if (*ins->codep != FWAIT_OPCODE)
8671 ins->all_prefixes[i++] = *ins->codep;
8672 ins->rex = newrex;
8673 ins->codep++;
8674 length++;
8675 }
8676 return 0;
8677 }
8678
8679 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8680 prefix byte. */
8681
8682 static const char *
8683 prefix_name (instr_info *ins, int pref, int sizeflag)
8684 {
8685 static const char *rexes [16] =
8686 {
8687 "rex", /* 0x40 */
8688 "rex.B", /* 0x41 */
8689 "rex.X", /* 0x42 */
8690 "rex.XB", /* 0x43 */
8691 "rex.R", /* 0x44 */
8692 "rex.RB", /* 0x45 */
8693 "rex.RX", /* 0x46 */
8694 "rex.RXB", /* 0x47 */
8695 "rex.W", /* 0x48 */
8696 "rex.WB", /* 0x49 */
8697 "rex.WX", /* 0x4a */
8698 "rex.WXB", /* 0x4b */
8699 "rex.WR", /* 0x4c */
8700 "rex.WRB", /* 0x4d */
8701 "rex.WRX", /* 0x4e */
8702 "rex.WRXB", /* 0x4f */
8703 };
8704
8705 switch (pref)
8706 {
8707 /* REX prefixes family. */
8708 case 0x40:
8709 case 0x41:
8710 case 0x42:
8711 case 0x43:
8712 case 0x44:
8713 case 0x45:
8714 case 0x46:
8715 case 0x47:
8716 case 0x48:
8717 case 0x49:
8718 case 0x4a:
8719 case 0x4b:
8720 case 0x4c:
8721 case 0x4d:
8722 case 0x4e:
8723 case 0x4f:
8724 return rexes [pref - 0x40];
8725 case 0xf3:
8726 return "repz";
8727 case 0xf2:
8728 return "repnz";
8729 case 0xf0:
8730 return "lock";
8731 case 0x2e:
8732 return "cs";
8733 case 0x36:
8734 return "ss";
8735 case 0x3e:
8736 return "ds";
8737 case 0x26:
8738 return "es";
8739 case 0x64:
8740 return "fs";
8741 case 0x65:
8742 return "gs";
8743 case 0x66:
8744 return (sizeflag & DFLAG) ? "data16" : "data32";
8745 case 0x67:
8746 if (ins->address_mode == mode_64bit)
8747 return (sizeflag & AFLAG) ? "addr32" : "addr64";
8748 else
8749 return (sizeflag & AFLAG) ? "addr16" : "addr32";
8750 case FWAIT_OPCODE:
8751 return "fwait";
8752 case REP_PREFIX:
8753 return "rep";
8754 case XACQUIRE_PREFIX:
8755 return "xacquire";
8756 case XRELEASE_PREFIX:
8757 return "xrelease";
8758 case BND_PREFIX:
8759 return "bnd";
8760 case NOTRACK_PREFIX:
8761 return "notrack";
8762 default:
8763 return NULL;
8764 }
8765 }
8766
8767 /* Here for backwards compatibility. When gdb stops using
8768 print_insn_i386_att and print_insn_i386_intel these functions can
8769 disappear, and print_insn_i386 be merged into print_insn. */
8770 int
8771 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
8772 {
8773 instr_info ins;
8774 ins.info = info;
8775 ins.intel_syntax = 0;
8776
8777 return print_insn (pc, &ins);
8778 }
8779
8780 int
8781 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
8782 {
8783 instr_info ins;
8784 ins.info = info;
8785 ins.intel_syntax = 1;
8786
8787 return print_insn (pc, &ins);
8788 }
8789
8790 int
8791 print_insn_i386 (bfd_vma pc, disassemble_info *info)
8792 {
8793 instr_info ins;
8794 ins.info = info;
8795 ins.intel_syntax = -1;
8796
8797 return print_insn (pc, &ins);
8798 }
8799
8800 void
8801 print_i386_disassembler_options (FILE *stream)
8802 {
8803 fprintf (stream, _("\n\
8804 The following i386/x86-64 specific disassembler options are supported for use\n\
8805 with the -M switch (multiple options should be separated by commas):\n"));
8806
8807 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
8808 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
8809 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
8810 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
8811 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
8812 fprintf (stream, _(" att-mnemonic\n"
8813 " Display instruction in AT&T mnemonic\n"));
8814 fprintf (stream, _(" intel-mnemonic\n"
8815 " Display instruction in Intel mnemonic\n"));
8816 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
8817 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
8818 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
8819 fprintf (stream, _(" data32 Assume 32bit data size\n"));
8820 fprintf (stream, _(" data16 Assume 16bit data size\n"));
8821 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
8822 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
8823 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
8824 }
8825
8826 /* Bad opcode. */
8827 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
8828
8829 /* Get a pointer to struct dis386 with a valid name. */
8830
8831 static const struct dis386 *
8832 get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
8833 {
8834 int vindex, vex_table_index;
8835
8836 if (dp->name != NULL)
8837 return dp;
8838
8839 switch (dp->op[0].bytemode)
8840 {
8841 case USE_REG_TABLE:
8842 dp = &reg_table[dp->op[1].bytemode][ins->modrm.reg];
8843 break;
8844
8845 case USE_MOD_TABLE:
8846 vindex = ins->modrm.mod == 0x3 ? 1 : 0;
8847 dp = &mod_table[dp->op[1].bytemode][vindex];
8848 break;
8849
8850 case USE_RM_TABLE:
8851 dp = &rm_table[dp->op[1].bytemode][ins->modrm.rm];
8852 break;
8853
8854 case USE_PREFIX_TABLE:
8855 if (ins->need_vex)
8856 {
8857 /* The prefix in VEX is implicit. */
8858 switch (ins->vex.prefix)
8859 {
8860 case 0:
8861 vindex = 0;
8862 break;
8863 case REPE_PREFIX_OPCODE:
8864 vindex = 1;
8865 break;
8866 case DATA_PREFIX_OPCODE:
8867 vindex = 2;
8868 break;
8869 case REPNE_PREFIX_OPCODE:
8870 vindex = 3;
8871 break;
8872 default:
8873 abort ();
8874 break;
8875 }
8876 }
8877 else
8878 {
8879 int last_prefix = -1;
8880 int prefix = 0;
8881 vindex = 0;
8882 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
8883 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
8884 last one wins. */
8885 if ((ins->prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
8886 {
8887 if (ins->last_repz_prefix > ins->last_repnz_prefix)
8888 {
8889 vindex = 1;
8890 prefix = PREFIX_REPZ;
8891 last_prefix = ins->last_repz_prefix;
8892 }
8893 else
8894 {
8895 vindex = 3;
8896 prefix = PREFIX_REPNZ;
8897 last_prefix = ins->last_repnz_prefix;
8898 }
8899
8900 /* Check if prefix should be ignored. */
8901 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
8902 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
8903 & prefix) != 0
8904 && !prefix_table[dp->op[1].bytemode][vindex].name)
8905 vindex = 0;
8906 }
8907
8908 if (vindex == 0 && (ins->prefixes & PREFIX_DATA) != 0)
8909 {
8910 vindex = 2;
8911 prefix = PREFIX_DATA;
8912 last_prefix = ins->last_data_prefix;
8913 }
8914
8915 if (vindex != 0)
8916 {
8917 ins->used_prefixes |= prefix;
8918 ins->all_prefixes[last_prefix] = 0;
8919 }
8920 }
8921 dp = &prefix_table[dp->op[1].bytemode][vindex];
8922 break;
8923
8924 case USE_X86_64_TABLE:
8925 vindex = ins->address_mode == mode_64bit ? 1 : 0;
8926 dp = &x86_64_table[dp->op[1].bytemode][vindex];
8927 break;
8928
8929 case USE_3BYTE_TABLE:
8930 FETCH_DATA (ins->info, ins->codep + 2);
8931 vindex = *ins->codep++;
8932 dp = &three_byte_table[dp->op[1].bytemode][vindex];
8933 ins->end_codep = ins->codep;
8934 ins->modrm.mod = (*ins->codep >> 6) & 3;
8935 ins->modrm.reg = (*ins->codep >> 3) & 7;
8936 ins->modrm.rm = *ins->codep & 7;
8937 break;
8938
8939 case USE_VEX_LEN_TABLE:
8940 if (!ins->need_vex)
8941 abort ();
8942
8943 switch (ins->vex.length)
8944 {
8945 case 128:
8946 vindex = 0;
8947 break;
8948 case 512:
8949 /* This allows re-using in particular table entries where only
8950 128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid. */
8951 if (ins->vex.evex)
8952 {
8953 case 256:
8954 vindex = 1;
8955 break;
8956 }
8957 /* Fall through. */
8958 default:
8959 abort ();
8960 break;
8961 }
8962
8963 dp = &vex_len_table[dp->op[1].bytemode][vindex];
8964 break;
8965
8966 case USE_EVEX_LEN_TABLE:
8967 if (!ins->vex.evex)
8968 abort ();
8969
8970 switch (ins->vex.length)
8971 {
8972 case 128:
8973 vindex = 0;
8974 break;
8975 case 256:
8976 vindex = 1;
8977 break;
8978 case 512:
8979 vindex = 2;
8980 break;
8981 default:
8982 abort ();
8983 break;
8984 }
8985
8986 dp = &evex_len_table[dp->op[1].bytemode][vindex];
8987 break;
8988
8989 case USE_XOP_8F_TABLE:
8990 FETCH_DATA (ins->info, ins->codep + 3);
8991 ins->rex = ~(*ins->codep >> 5) & 0x7;
8992
8993 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
8994 switch ((*ins->codep & 0x1f))
8995 {
8996 default:
8997 dp = &bad_opcode;
8998 return dp;
8999 case 0x8:
9000 vex_table_index = XOP_08;
9001 break;
9002 case 0x9:
9003 vex_table_index = XOP_09;
9004 break;
9005 case 0xa:
9006 vex_table_index = XOP_0A;
9007 break;
9008 }
9009 ins->codep++;
9010 ins->vex.w = *ins->codep & 0x80;
9011 if (ins->vex.w && ins->address_mode == mode_64bit)
9012 ins->rex |= REX_W;
9013
9014 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9015 if (ins->address_mode != mode_64bit)
9016 {
9017 /* In 16/32-bit mode REX_B is silently ignored. */
9018 ins->rex &= ~REX_B;
9019 }
9020
9021 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9022 switch ((*ins->codep & 0x3))
9023 {
9024 case 0:
9025 break;
9026 case 1:
9027 ins->vex.prefix = DATA_PREFIX_OPCODE;
9028 break;
9029 case 2:
9030 ins->vex.prefix = REPE_PREFIX_OPCODE;
9031 break;
9032 case 3:
9033 ins->vex.prefix = REPNE_PREFIX_OPCODE;
9034 break;
9035 }
9036 ins->need_vex = true;
9037 ins->codep++;
9038 vindex = *ins->codep++;
9039 dp = &xop_table[vex_table_index][vindex];
9040
9041 ins->end_codep = ins->codep;
9042 FETCH_DATA (ins->info, ins->codep + 1);
9043 ins->modrm.mod = (*ins->codep >> 6) & 3;
9044 ins->modrm.reg = (*ins->codep >> 3) & 7;
9045 ins->modrm.rm = *ins->codep & 7;
9046
9047 /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9048 having to decode the bits for every otherwise valid encoding. */
9049 if (ins->vex.prefix)
9050 return &bad_opcode;
9051 break;
9052
9053 case USE_VEX_C4_TABLE:
9054 /* VEX prefix. */
9055 FETCH_DATA (ins->info, ins->codep + 3);
9056 ins->rex = ~(*ins->codep >> 5) & 0x7;
9057 switch ((*ins->codep & 0x1f))
9058 {
9059 default:
9060 dp = &bad_opcode;
9061 return dp;
9062 case 0x1:
9063 vex_table_index = VEX_0F;
9064 break;
9065 case 0x2:
9066 vex_table_index = VEX_0F38;
9067 break;
9068 case 0x3:
9069 vex_table_index = VEX_0F3A;
9070 break;
9071 }
9072 ins->codep++;
9073 ins->vex.w = *ins->codep & 0x80;
9074 if (ins->address_mode == mode_64bit)
9075 {
9076 if (ins->vex.w)
9077 ins->rex |= REX_W;
9078 }
9079 else
9080 {
9081 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9082 is ignored, other REX bits are 0 and the highest bit in
9083 VEX.vvvv is also ignored (but we mustn't clear it here). */
9084 ins->rex = 0;
9085 }
9086 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9087 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9088 switch ((*ins->codep & 0x3))
9089 {
9090 case 0:
9091 break;
9092 case 1:
9093 ins->vex.prefix = DATA_PREFIX_OPCODE;
9094 break;
9095 case 2:
9096 ins->vex.prefix = REPE_PREFIX_OPCODE;
9097 break;
9098 case 3:
9099 ins->vex.prefix = REPNE_PREFIX_OPCODE;
9100 break;
9101 }
9102 ins->need_vex = true;
9103 ins->codep++;
9104 vindex = *ins->codep++;
9105 dp = &vex_table[vex_table_index][vindex];
9106 ins->end_codep = ins->codep;
9107 /* There is no MODRM byte for VEX0F 77. */
9108 if (vex_table_index != VEX_0F || vindex != 0x77)
9109 {
9110 FETCH_DATA (ins->info, ins->codep + 1);
9111 ins->modrm.mod = (*ins->codep >> 6) & 3;
9112 ins->modrm.reg = (*ins->codep >> 3) & 7;
9113 ins->modrm.rm = *ins->codep & 7;
9114 }
9115 break;
9116
9117 case USE_VEX_C5_TABLE:
9118 /* VEX prefix. */
9119 FETCH_DATA (ins->info, ins->codep + 2);
9120 ins->rex = (*ins->codep & 0x80) ? 0 : REX_R;
9121
9122 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9123 VEX.vvvv is 1. */
9124 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9125 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9126 switch ((*ins->codep & 0x3))
9127 {
9128 case 0:
9129 break;
9130 case 1:
9131 ins->vex.prefix = DATA_PREFIX_OPCODE;
9132 break;
9133 case 2:
9134 ins->vex.prefix = REPE_PREFIX_OPCODE;
9135 break;
9136 case 3:
9137 ins->vex.prefix = REPNE_PREFIX_OPCODE;
9138 break;
9139 }
9140 ins->need_vex = true;
9141 ins->codep++;
9142 vindex = *ins->codep++;
9143 dp = &vex_table[dp->op[1].bytemode][vindex];
9144 ins->end_codep = ins->codep;
9145 /* There is no MODRM byte for VEX 77. */
9146 if (vindex != 0x77)
9147 {
9148 FETCH_DATA (ins->info, ins->codep + 1);
9149 ins->modrm.mod = (*ins->codep >> 6) & 3;
9150 ins->modrm.reg = (*ins->codep >> 3) & 7;
9151 ins->modrm.rm = *ins->codep & 7;
9152 }
9153 break;
9154
9155 case USE_VEX_W_TABLE:
9156 if (!ins->need_vex)
9157 abort ();
9158
9159 dp = &vex_w_table[dp->op[1].bytemode][ins->vex.w];
9160 break;
9161
9162 case USE_EVEX_TABLE:
9163 ins->two_source_ops = false;
9164 /* EVEX prefix. */
9165 ins->vex.evex = true;
9166 FETCH_DATA (ins->info, ins->codep + 4);
9167 /* The first byte after 0x62. */
9168 ins->rex = ~(*ins->codep >> 5) & 0x7;
9169 ins->vex.r = *ins->codep & 0x10;
9170 switch ((*ins->codep & 0xf))
9171 {
9172 default:
9173 return &bad_opcode;
9174 case 0x1:
9175 vex_table_index = EVEX_0F;
9176 break;
9177 case 0x2:
9178 vex_table_index = EVEX_0F38;
9179 break;
9180 case 0x3:
9181 vex_table_index = EVEX_0F3A;
9182 break;
9183 case 0x5:
9184 vex_table_index = EVEX_MAP5;
9185 break;
9186 case 0x6:
9187 vex_table_index = EVEX_MAP6;
9188 break;
9189 }
9190
9191 /* The second byte after 0x62. */
9192 ins->codep++;
9193 ins->vex.w = *ins->codep & 0x80;
9194 if (ins->vex.w && ins->address_mode == mode_64bit)
9195 ins->rex |= REX_W;
9196
9197 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9198
9199 /* The U bit. */
9200 if (!(*ins->codep & 0x4))
9201 return &bad_opcode;
9202
9203 switch ((*ins->codep & 0x3))
9204 {
9205 case 0:
9206 break;
9207 case 1:
9208 ins->vex.prefix = DATA_PREFIX_OPCODE;
9209 break;
9210 case 2:
9211 ins->vex.prefix = REPE_PREFIX_OPCODE;
9212 break;
9213 case 3:
9214 ins->vex.prefix = REPNE_PREFIX_OPCODE;
9215 break;
9216 }
9217
9218 /* The third byte after 0x62. */
9219 ins->codep++;
9220
9221 /* Remember the static rounding bits. */
9222 ins->vex.ll = (*ins->codep >> 5) & 3;
9223 ins->vex.b = *ins->codep & 0x10;
9224
9225 ins->vex.v = *ins->codep & 0x8;
9226 ins->vex.mask_register_specifier = *ins->codep & 0x7;
9227 ins->vex.zeroing = *ins->codep & 0x80;
9228
9229 if (ins->address_mode != mode_64bit)
9230 {
9231 /* In 16/32-bit mode silently ignore following bits. */
9232 ins->rex &= ~REX_B;
9233 ins->vex.r = true;
9234 }
9235
9236 ins->need_vex = true;
9237 ins->codep++;
9238 vindex = *ins->codep++;
9239 dp = &evex_table[vex_table_index][vindex];
9240 ins->end_codep = ins->codep;
9241 FETCH_DATA (ins->info, ins->codep + 1);
9242 ins->modrm.mod = (*ins->codep >> 6) & 3;
9243 ins->modrm.reg = (*ins->codep >> 3) & 7;
9244 ins->modrm.rm = *ins->codep & 7;
9245
9246 /* Set vector length. */
9247 if (ins->modrm.mod == 3 && ins->vex.b)
9248 ins->vex.length = 512;
9249 else
9250 {
9251 switch (ins->vex.ll)
9252 {
9253 case 0x0:
9254 ins->vex.length = 128;
9255 break;
9256 case 0x1:
9257 ins->vex.length = 256;
9258 break;
9259 case 0x2:
9260 ins->vex.length = 512;
9261 break;
9262 default:
9263 return &bad_opcode;
9264 }
9265 }
9266 break;
9267
9268 case 0:
9269 dp = &bad_opcode;
9270 break;
9271
9272 default:
9273 abort ();
9274 }
9275
9276 if (dp->name != NULL)
9277 return dp;
9278 else
9279 return get_valid_dis386 (dp, ins);
9280 }
9281
9282 static void
9283 get_sib (instr_info *ins, int sizeflag)
9284 {
9285 /* If modrm.mod == 3, operand must be register. */
9286 if (ins->need_modrm
9287 && ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
9288 && ins->modrm.mod != 3
9289 && ins->modrm.rm == 4)
9290 {
9291 FETCH_DATA (ins->info, ins->codep + 2);
9292 ins->sib.index = (ins->codep[1] >> 3) & 7;
9293 ins->sib.scale = (ins->codep[1] >> 6) & 3;
9294 ins->sib.base = ins->codep[1] & 7;
9295 ins->has_sib = true;
9296 }
9297 else
9298 ins->has_sib = false;
9299 }
9300
9301 /* Like oappend (below), but S is a string starting with '%'.
9302 In Intel syntax, the '%' is elided. */
9303 static void
9304 oappend_maybe_intel (instr_info *ins, const char *s)
9305 {
9306 oappend (ins, s + ins->intel_syntax);
9307 }
9308
9309 static int
9310 print_insn (bfd_vma pc, instr_info *ins)
9311 {
9312 const struct dis386 *dp;
9313 int i;
9314 char *op_txt[MAX_OPERANDS];
9315 int needcomma;
9316 bool intel_swap_2_3;
9317 int sizeflag, orig_sizeflag;
9318 const char *p;
9319 struct dis_private priv;
9320 int prefix_length;
9321
9322 ins->isa64 = 0;
9323 ins->intel_mnemonic = !SYSV386_COMPAT;
9324 ins->op_is_jump = false;
9325 priv.orig_sizeflag = AFLAG | DFLAG;
9326 if ((ins->info->mach & bfd_mach_i386_i386) != 0)
9327 ins->address_mode = mode_32bit;
9328 else if (ins->info->mach == bfd_mach_i386_i8086)
9329 {
9330 ins->address_mode = mode_16bit;
9331 priv.orig_sizeflag = 0;
9332 }
9333 else
9334 ins->address_mode = mode_64bit;
9335
9336 if (ins->intel_syntax == (char) -1)
9337 ins->intel_syntax = (ins->info->mach & bfd_mach_i386_intel_syntax) != 0;
9338
9339 for (p = ins->info->disassembler_options; p != NULL;)
9340 {
9341 if (startswith (p, "amd64"))
9342 ins->isa64 = amd64;
9343 else if (startswith (p, "intel64"))
9344 ins->isa64 = intel64;
9345 else if (startswith (p, "x86-64"))
9346 {
9347 ins->address_mode = mode_64bit;
9348 priv.orig_sizeflag |= AFLAG | DFLAG;
9349 }
9350 else if (startswith (p, "i386"))
9351 {
9352 ins->address_mode = mode_32bit;
9353 priv.orig_sizeflag |= AFLAG | DFLAG;
9354 }
9355 else if (startswith (p, "i8086"))
9356 {
9357 ins->address_mode = mode_16bit;
9358 priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9359 }
9360 else if (startswith (p, "intel"))
9361 {
9362 ins->intel_syntax = 1;
9363 if (startswith (p + 5, "-mnemonic"))
9364 ins->intel_mnemonic = true;
9365 }
9366 else if (startswith (p, "att"))
9367 {
9368 ins->intel_syntax = 0;
9369 if (startswith (p + 3, "-mnemonic"))
9370 ins->intel_mnemonic = false;
9371 }
9372 else if (startswith (p, "addr"))
9373 {
9374 if (ins->address_mode == mode_64bit)
9375 {
9376 if (p[4] == '3' && p[5] == '2')
9377 priv.orig_sizeflag &= ~AFLAG;
9378 else if (p[4] == '6' && p[5] == '4')
9379 priv.orig_sizeflag |= AFLAG;
9380 }
9381 else
9382 {
9383 if (p[4] == '1' && p[5] == '6')
9384 priv.orig_sizeflag &= ~AFLAG;
9385 else if (p[4] == '3' && p[5] == '2')
9386 priv.orig_sizeflag |= AFLAG;
9387 }
9388 }
9389 else if (startswith (p, "data"))
9390 {
9391 if (p[4] == '1' && p[5] == '6')
9392 priv.orig_sizeflag &= ~DFLAG;
9393 else if (p[4] == '3' && p[5] == '2')
9394 priv.orig_sizeflag |= DFLAG;
9395 }
9396 else if (startswith (p, "suffix"))
9397 priv.orig_sizeflag |= SUFFIX_ALWAYS;
9398
9399 p = strchr (p, ',');
9400 if (p != NULL)
9401 p++;
9402 }
9403
9404 if (ins->address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9405 {
9406 (*ins->info->fprintf_styled_func) (ins->info->stream, dis_style_text,
9407 _("64-bit address is disabled"));
9408 return -1;
9409 }
9410
9411 if (ins->intel_syntax)
9412 {
9413 ins->open_char = '[';
9414 ins->close_char = ']';
9415 ins->separator_char = '+';
9416 ins->scale_char = '*';
9417 }
9418 else
9419 {
9420 ins->open_char = '(';
9421 ins->close_char = ')';
9422 ins->separator_char = ',';
9423 ins->scale_char = ',';
9424 }
9425
9426 /* The output looks better if we put 7 bytes on a line, since that
9427 puts most long word instructions on a single line. */
9428 ins->info->bytes_per_line = 7;
9429
9430 ins->info->private_data = &priv;
9431 priv.max_fetched = priv.the_buffer;
9432 priv.insn_start = pc;
9433
9434 ins->obuf[0] = 0;
9435 for (i = 0; i < MAX_OPERANDS; ++i)
9436 {
9437 ins->op_out[i][0] = 0;
9438 ins->op_index[i] = -1;
9439 }
9440
9441 ins->start_pc = pc;
9442 ins->start_codep = priv.the_buffer;
9443 ins->codep = priv.the_buffer;
9444
9445 if (OPCODES_SIGSETJMP (priv.bailout) != 0)
9446 {
9447 const char *name;
9448
9449 /* Getting here means we tried for data but didn't get it. That
9450 means we have an incomplete instruction of some sort. Just
9451 print the first byte as a prefix or a .byte pseudo-op. */
9452 if (ins->codep > priv.the_buffer)
9453 {
9454 name = prefix_name (ins, priv.the_buffer[0], priv.orig_sizeflag);
9455 if (name != NULL)
9456 (*ins->info->fprintf_styled_func)
9457 (ins->info->stream, dis_style_mnemonic, "%s", name);
9458 else
9459 {
9460 /* Just print the first byte as a .byte instruction. */
9461 (*ins->info->fprintf_styled_func)
9462 (ins->info->stream, dis_style_assembler_directive, ".byte ");
9463 (*ins->info->fprintf_styled_func)
9464 (ins->info->stream, dis_style_immediate, "0x%x",
9465 (unsigned int) priv.the_buffer[0]);
9466 }
9467
9468 return 1;
9469 }
9470
9471 return -1;
9472 }
9473
9474 ins->obufp = ins->obuf;
9475 sizeflag = priv.orig_sizeflag;
9476
9477 if (!ckprefix (ins) || ins->rex_used)
9478 {
9479 /* Too many ins->prefixes or unused REX ins->prefixes. */
9480 for (i = 0;
9481 i < (int) ARRAY_SIZE (ins->all_prefixes) && ins->all_prefixes[i];
9482 i++)
9483 (*ins->info->fprintf_styled_func)
9484 (ins->info->stream, dis_style_mnemonic, "%s%s",
9485 (i == 0 ? "" : " "), prefix_name (ins, ins->all_prefixes[i],
9486 sizeflag));
9487 return i;
9488 }
9489
9490 ins->insn_codep = ins->codep;
9491
9492 FETCH_DATA (ins->info, ins->codep + 1);
9493 ins->two_source_ops = (*ins->codep == 0x62) || (*ins->codep == 0xc8);
9494
9495 if (((ins->prefixes & PREFIX_FWAIT)
9496 && ((*ins->codep < 0xd8) || (*ins->codep > 0xdf))))
9497 {
9498 /* Handle ins->prefixes before fwait. */
9499 for (i = 0; i < ins->fwait_prefix && ins->all_prefixes[i];
9500 i++)
9501 (*ins->info->fprintf_styled_func)
9502 (ins->info->stream, dis_style_mnemonic, "%s ",
9503 prefix_name (ins, ins->all_prefixes[i], sizeflag));
9504 (*ins->info->fprintf_styled_func)
9505 (ins->info->stream, dis_style_mnemonic, "fwait");
9506 return i + 1;
9507 }
9508
9509 if (*ins->codep == 0x0f)
9510 {
9511 unsigned char threebyte;
9512
9513 ins->codep++;
9514 FETCH_DATA (ins->info, ins->codep + 1);
9515 threebyte = *ins->codep;
9516 dp = &dis386_twobyte[threebyte];
9517 ins->need_modrm = twobyte_has_modrm[threebyte];
9518 ins->codep++;
9519 }
9520 else
9521 {
9522 dp = &dis386[*ins->codep];
9523 ins->need_modrm = onebyte_has_modrm[*ins->codep];
9524 ins->codep++;
9525 }
9526
9527 /* Save sizeflag for printing the extra ins->prefixes later before updating
9528 it for mnemonic and operand processing. The prefix names depend
9529 only on the address mode. */
9530 orig_sizeflag = sizeflag;
9531 if (ins->prefixes & PREFIX_ADDR)
9532 sizeflag ^= AFLAG;
9533 if ((ins->prefixes & PREFIX_DATA))
9534 sizeflag ^= DFLAG;
9535
9536 ins->end_codep = ins->codep;
9537 if (ins->need_modrm)
9538 {
9539 FETCH_DATA (ins->info, ins->codep + 1);
9540 ins->modrm.mod = (*ins->codep >> 6) & 3;
9541 ins->modrm.reg = (*ins->codep >> 3) & 7;
9542 ins->modrm.rm = *ins->codep & 7;
9543 }
9544 else
9545 memset (&ins->modrm, 0, sizeof (ins->modrm));
9546
9547 ins->need_vex = false;
9548 memset (&ins->vex, 0, sizeof (ins->vex));
9549
9550 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9551 {
9552 get_sib (ins, sizeflag);
9553 dofloat (ins, sizeflag);
9554 }
9555 else
9556 {
9557 dp = get_valid_dis386 (dp, ins);
9558 if (dp != NULL && putop (ins, dp->name, sizeflag) == 0)
9559 {
9560 get_sib (ins, sizeflag);
9561 for (i = 0; i < MAX_OPERANDS; ++i)
9562 {
9563 ins->obufp = ins->op_out[i];
9564 ins->op_ad = MAX_OPERANDS - 1 - i;
9565 if (dp->op[i].rtn)
9566 (*dp->op[i].rtn) (ins, dp->op[i].bytemode, sizeflag);
9567 /* For EVEX instruction after the last operand masking
9568 should be printed. */
9569 if (i == 0 && ins->vex.evex)
9570 {
9571 /* Don't print {%k0}. */
9572 if (ins->vex.mask_register_specifier)
9573 {
9574 oappend (ins, "{");
9575 oappend_maybe_intel (ins,
9576 att_names_mask
9577 [ins->vex.mask_register_specifier]);
9578 oappend (ins, "}");
9579 }
9580 if (ins->vex.zeroing)
9581 oappend (ins, "{z}");
9582
9583 /* S/G insns require a mask and don't allow
9584 zeroing-masking. */
9585 if ((dp->op[0].bytemode == vex_vsib_d_w_dq_mode
9586 || dp->op[0].bytemode == vex_vsib_q_w_dq_mode)
9587 && (ins->vex.mask_register_specifier == 0
9588 || ins->vex.zeroing))
9589 oappend (ins, "/(bad)");
9590 }
9591 }
9592
9593 /* Check whether rounding control was enabled for an insn not
9594 supporting it. */
9595 if (ins->modrm.mod == 3 && ins->vex.b
9596 && !(ins->evex_used & EVEX_b_used))
9597 {
9598 for (i = 0; i < MAX_OPERANDS; ++i)
9599 {
9600 ins->obufp = ins->op_out[i];
9601 if (*ins->obufp)
9602 continue;
9603 oappend (ins, names_rounding[ins->vex.ll]);
9604 oappend (ins, "bad}");
9605 break;
9606 }
9607 }
9608 }
9609 }
9610
9611 /* Clear instruction information. */
9612 ins->info->insn_info_valid = 0;
9613 ins->info->branch_delay_insns = 0;
9614 ins->info->data_size = 0;
9615 ins->info->insn_type = dis_noninsn;
9616 ins->info->target = 0;
9617 ins->info->target2 = 0;
9618
9619 /* Reset jump operation indicator. */
9620 ins->op_is_jump = false;
9621 {
9622 int jump_detection = 0;
9623
9624 /* Extract flags. */
9625 for (i = 0; i < MAX_OPERANDS; ++i)
9626 {
9627 if ((dp->op[i].rtn == OP_J)
9628 || (dp->op[i].rtn == OP_indirE))
9629 jump_detection |= 1;
9630 else if ((dp->op[i].rtn == BND_Fixup)
9631 || (!dp->op[i].rtn && !dp->op[i].bytemode))
9632 jump_detection |= 2;
9633 else if ((dp->op[i].bytemode == cond_jump_mode)
9634 || (dp->op[i].bytemode == loop_jcxz_mode))
9635 jump_detection |= 4;
9636 }
9637
9638 /* Determine if this is a jump or branch. */
9639 if ((jump_detection & 0x3) == 0x3)
9640 {
9641 ins->op_is_jump = true;
9642 if (jump_detection & 0x4)
9643 ins->info->insn_type = dis_condbranch;
9644 else
9645 ins->info->insn_type = (dp->name && !strncmp (dp->name, "call", 4))
9646 ? dis_jsr : dis_branch;
9647 }
9648 }
9649
9650 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9651 are all 0s in inverted form. */
9652 if (ins->need_vex && ins->vex.register_specifier != 0)
9653 {
9654 (*ins->info->fprintf_styled_func) (ins->info->stream, dis_style_text,
9655 "(bad)");
9656 return ins->end_codep - priv.the_buffer;
9657 }
9658
9659 /* If EVEX.z is set, there must be an actual mask register in use. */
9660 if (ins->vex.zeroing && ins->vex.mask_register_specifier == 0)
9661 {
9662 (*ins->info->fprintf_styled_func) (ins->info->stream, dis_style_text,
9663 "(bad)");
9664 return ins->end_codep - priv.the_buffer;
9665 }
9666
9667 switch (dp->prefix_requirement)
9668 {
9669 case PREFIX_DATA:
9670 /* If only the data prefix is marked as mandatory, its absence renders
9671 the encoding invalid. Most other PREFIX_OPCODE rules still apply. */
9672 if (ins->need_vex ? !ins->vex.prefix : !(ins->prefixes & PREFIX_DATA))
9673 {
9674 (*ins->info->fprintf_styled_func) (ins->info->stream,
9675 dis_style_text, "(bad)");
9676 return ins->end_codep - priv.the_buffer;
9677 }
9678 ins->used_prefixes |= PREFIX_DATA;
9679 /* Fall through. */
9680 case PREFIX_OPCODE:
9681 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
9682 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
9683 used by putop and MMX/SSE operand and may be overridden by the
9684 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
9685 separately. */
9686 if (((ins->need_vex
9687 ? ins->vex.prefix == REPE_PREFIX_OPCODE
9688 || ins->vex.prefix == REPNE_PREFIX_OPCODE
9689 : (ins->prefixes
9690 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9691 && (ins->used_prefixes
9692 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
9693 || (((ins->need_vex
9694 ? ins->vex.prefix == DATA_PREFIX_OPCODE
9695 : ((ins->prefixes
9696 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
9697 == PREFIX_DATA))
9698 && (ins->used_prefixes & PREFIX_DATA) == 0))
9699 || (ins->vex.evex && dp->prefix_requirement != PREFIX_DATA
9700 && !ins->vex.w != !(ins->used_prefixes & PREFIX_DATA)))
9701 {
9702 (*ins->info->fprintf_styled_func) (ins->info->stream,
9703 dis_style_text, "(bad)");
9704 return ins->end_codep - priv.the_buffer;
9705 }
9706 break;
9707
9708 case PREFIX_IGNORED:
9709 /* Zap data size and rep prefixes from used_prefixes and reinstate their
9710 origins in all_prefixes. */
9711 ins->used_prefixes &= ~PREFIX_OPCODE;
9712 if (ins->last_data_prefix >= 0)
9713 ins->all_prefixes[ins->last_data_prefix] = 0x66;
9714 if (ins->last_repz_prefix >= 0)
9715 ins->all_prefixes[ins->last_repz_prefix] = 0xf3;
9716 if (ins->last_repnz_prefix >= 0)
9717 ins->all_prefixes[ins->last_repnz_prefix] = 0xf2;
9718 break;
9719 }
9720
9721 /* Check if the REX prefix is used. */
9722 if ((ins->rex ^ ins->rex_used) == 0
9723 && !ins->need_vex && ins->last_rex_prefix >= 0)
9724 ins->all_prefixes[ins->last_rex_prefix] = 0;
9725
9726 /* Check if the SEG prefix is used. */
9727 if ((ins->prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
9728 | PREFIX_FS | PREFIX_GS)) != 0
9729 && (ins->used_prefixes & ins->active_seg_prefix) != 0)
9730 ins->all_prefixes[ins->last_seg_prefix] = 0;
9731
9732 /* Check if the ADDR prefix is used. */
9733 if ((ins->prefixes & PREFIX_ADDR) != 0
9734 && (ins->used_prefixes & PREFIX_ADDR) != 0)
9735 ins->all_prefixes[ins->last_addr_prefix] = 0;
9736
9737 /* Check if the DATA prefix is used. */
9738 if ((ins->prefixes & PREFIX_DATA) != 0
9739 && (ins->used_prefixes & PREFIX_DATA) != 0
9740 && !ins->need_vex)
9741 ins->all_prefixes[ins->last_data_prefix] = 0;
9742
9743 /* Print the extra ins->prefixes. */
9744 prefix_length = 0;
9745 for (i = 0; i < (int) ARRAY_SIZE (ins->all_prefixes); i++)
9746 if (ins->all_prefixes[i])
9747 {
9748 const char *name;
9749 name = prefix_name (ins, ins->all_prefixes[i], orig_sizeflag);
9750 if (name == NULL)
9751 abort ();
9752 prefix_length += strlen (name) + 1;
9753 (*ins->info->fprintf_styled_func)
9754 (ins->info->stream, dis_style_mnemonic, "%s ", name);
9755 }
9756
9757 /* Check maximum code length. */
9758 if ((ins->codep - ins->start_codep) > MAX_CODE_LENGTH)
9759 {
9760 (*ins->info->fprintf_styled_func)
9761 (ins->info->stream, dis_style_text, "(bad)");
9762 return MAX_CODE_LENGTH;
9763 }
9764
9765 ins->obufp = ins->mnemonicendp;
9766 for (i = strlen (ins->obuf) + prefix_length; i < 6; i++)
9767 oappend (ins, " ");
9768 oappend (ins, " ");
9769 (*ins->info->fprintf_styled_func)
9770 (ins->info->stream, dis_style_mnemonic, "%s", ins->obuf);
9771
9772 /* The enter and bound instructions are printed with operands in the same
9773 order as the intel book; everything else is printed in reverse order. */
9774 intel_swap_2_3 = false;
9775 if (ins->intel_syntax || ins->two_source_ops)
9776 {
9777 for (i = 0; i < MAX_OPERANDS; ++i)
9778 op_txt[i] = ins->op_out[i];
9779
9780 if (ins->intel_syntax && dp && dp->op[2].rtn == OP_Rounding
9781 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
9782 {
9783 op_txt[2] = ins->op_out[3];
9784 op_txt[3] = ins->op_out[2];
9785 intel_swap_2_3 = true;
9786 }
9787
9788 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
9789 {
9790 bool riprel;
9791
9792 ins->op_ad = ins->op_index[i];
9793 ins->op_index[i] = ins->op_index[MAX_OPERANDS - 1 - i];
9794 ins->op_index[MAX_OPERANDS - 1 - i] = ins->op_ad;
9795 riprel = ins->op_riprel[i];
9796 ins->op_riprel[i] = ins->op_riprel[MAX_OPERANDS - 1 - i];
9797 ins->op_riprel[MAX_OPERANDS - 1 - i] = riprel;
9798 }
9799 }
9800 else
9801 {
9802 for (i = 0; i < MAX_OPERANDS; ++i)
9803 op_txt[MAX_OPERANDS - 1 - i] = ins->op_out[i];
9804 }
9805
9806 needcomma = 0;
9807 for (i = 0; i < MAX_OPERANDS; ++i)
9808 if (*op_txt[i])
9809 {
9810 /* In Intel syntax embedded rounding / SAE are not separate operands.
9811 Instead they're attached to the prior register operand. Simply
9812 suppress emission of the comma to achieve that effect. */
9813 switch (i & -(ins->intel_syntax && dp))
9814 {
9815 case 2:
9816 if (dp->op[2].rtn == OP_Rounding && !intel_swap_2_3)
9817 needcomma = 0;
9818 break;
9819 case 3:
9820 if (dp->op[3].rtn == OP_Rounding || intel_swap_2_3)
9821 needcomma = 0;
9822 break;
9823 }
9824 if (needcomma)
9825 (*ins->info->fprintf_styled_func) (ins->info->stream,
9826 dis_style_text, ",");
9827 if (ins->op_index[i] != -1 && !ins->op_riprel[i])
9828 {
9829 bfd_vma target = (bfd_vma) ins->op_address[ins->op_index[i]];
9830
9831 if (ins->op_is_jump)
9832 {
9833 ins->info->insn_info_valid = 1;
9834 ins->info->branch_delay_insns = 0;
9835 ins->info->data_size = 0;
9836 ins->info->target = target;
9837 ins->info->target2 = 0;
9838 }
9839 (*ins->info->print_address_func) (target, ins->info);
9840 }
9841 else
9842 (*ins->info->fprintf_styled_func) (ins->info->stream,
9843 dis_style_text, "%s",
9844 op_txt[i]);
9845 needcomma = 1;
9846 }
9847
9848 for (i = 0; i < MAX_OPERANDS; i++)
9849 if (ins->op_index[i] != -1 && ins->op_riprel[i])
9850 {
9851 (*ins->info->fprintf_styled_func) (ins->info->stream,
9852 dis_style_comment_start,
9853 " # ");
9854 (*ins->info->print_address_func) ((bfd_vma)
9855 (ins->start_pc + (ins->codep - ins->start_codep)
9856 + ins->op_address[ins->op_index[i]]), ins->info);
9857 break;
9858 }
9859 return ins->codep - priv.the_buffer;
9860 }
9861
9862 static const char *float_mem[] = {
9863 /* d8 */
9864 "fadd{s|}",
9865 "fmul{s|}",
9866 "fcom{s|}",
9867 "fcomp{s|}",
9868 "fsub{s|}",
9869 "fsubr{s|}",
9870 "fdiv{s|}",
9871 "fdivr{s|}",
9872 /* d9 */
9873 "fld{s|}",
9874 "(bad)",
9875 "fst{s|}",
9876 "fstp{s|}",
9877 "fldenv{C|C}",
9878 "fldcw",
9879 "fNstenv{C|C}",
9880 "fNstcw",
9881 /* da */
9882 "fiadd{l|}",
9883 "fimul{l|}",
9884 "ficom{l|}",
9885 "ficomp{l|}",
9886 "fisub{l|}",
9887 "fisubr{l|}",
9888 "fidiv{l|}",
9889 "fidivr{l|}",
9890 /* db */
9891 "fild{l|}",
9892 "fisttp{l|}",
9893 "fist{l|}",
9894 "fistp{l|}",
9895 "(bad)",
9896 "fld{t|}",
9897 "(bad)",
9898 "fstp{t|}",
9899 /* dc */
9900 "fadd{l|}",
9901 "fmul{l|}",
9902 "fcom{l|}",
9903 "fcomp{l|}",
9904 "fsub{l|}",
9905 "fsubr{l|}",
9906 "fdiv{l|}",
9907 "fdivr{l|}",
9908 /* dd */
9909 "fld{l|}",
9910 "fisttp{ll|}",
9911 "fst{l||}",
9912 "fstp{l|}",
9913 "frstor{C|C}",
9914 "(bad)",
9915 "fNsave{C|C}",
9916 "fNstsw",
9917 /* de */
9918 "fiadd{s|}",
9919 "fimul{s|}",
9920 "ficom{s|}",
9921 "ficomp{s|}",
9922 "fisub{s|}",
9923 "fisubr{s|}",
9924 "fidiv{s|}",
9925 "fidivr{s|}",
9926 /* df */
9927 "fild{s|}",
9928 "fisttp{s|}",
9929 "fist{s|}",
9930 "fistp{s|}",
9931 "fbld",
9932 "fild{ll|}",
9933 "fbstp",
9934 "fistp{ll|}",
9935 };
9936
9937 static const unsigned char float_mem_mode[] = {
9938 /* d8 */
9939 d_mode,
9940 d_mode,
9941 d_mode,
9942 d_mode,
9943 d_mode,
9944 d_mode,
9945 d_mode,
9946 d_mode,
9947 /* d9 */
9948 d_mode,
9949 0,
9950 d_mode,
9951 d_mode,
9952 0,
9953 w_mode,
9954 0,
9955 w_mode,
9956 /* da */
9957 d_mode,
9958 d_mode,
9959 d_mode,
9960 d_mode,
9961 d_mode,
9962 d_mode,
9963 d_mode,
9964 d_mode,
9965 /* db */
9966 d_mode,
9967 d_mode,
9968 d_mode,
9969 d_mode,
9970 0,
9971 t_mode,
9972 0,
9973 t_mode,
9974 /* dc */
9975 q_mode,
9976 q_mode,
9977 q_mode,
9978 q_mode,
9979 q_mode,
9980 q_mode,
9981 q_mode,
9982 q_mode,
9983 /* dd */
9984 q_mode,
9985 q_mode,
9986 q_mode,
9987 q_mode,
9988 0,
9989 0,
9990 0,
9991 w_mode,
9992 /* de */
9993 w_mode,
9994 w_mode,
9995 w_mode,
9996 w_mode,
9997 w_mode,
9998 w_mode,
9999 w_mode,
10000 w_mode,
10001 /* df */
10002 w_mode,
10003 w_mode,
10004 w_mode,
10005 w_mode,
10006 t_mode,
10007 q_mode,
10008 t_mode,
10009 q_mode
10010 };
10011
10012 #define ST { OP_ST, 0 }
10013 #define STi { OP_STi, 0 }
10014
10015 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10016 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10017 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10018 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10019 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10020 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10021 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10022 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10023 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10024
10025 static const struct dis386 float_reg[][8] = {
10026 /* d8 */
10027 {
10028 { "fadd", { ST, STi }, 0 },
10029 { "fmul", { ST, STi }, 0 },
10030 { "fcom", { STi }, 0 },
10031 { "fcomp", { STi }, 0 },
10032 { "fsub", { ST, STi }, 0 },
10033 { "fsubr", { ST, STi }, 0 },
10034 { "fdiv", { ST, STi }, 0 },
10035 { "fdivr", { ST, STi }, 0 },
10036 },
10037 /* d9 */
10038 {
10039 { "fld", { STi }, 0 },
10040 { "fxch", { STi }, 0 },
10041 { FGRPd9_2 },
10042 { Bad_Opcode },
10043 { FGRPd9_4 },
10044 { FGRPd9_5 },
10045 { FGRPd9_6 },
10046 { FGRPd9_7 },
10047 },
10048 /* da */
10049 {
10050 { "fcmovb", { ST, STi }, 0 },
10051 { "fcmove", { ST, STi }, 0 },
10052 { "fcmovbe",{ ST, STi }, 0 },
10053 { "fcmovu", { ST, STi }, 0 },
10054 { Bad_Opcode },
10055 { FGRPda_5 },
10056 { Bad_Opcode },
10057 { Bad_Opcode },
10058 },
10059 /* db */
10060 {
10061 { "fcmovnb",{ ST, STi }, 0 },
10062 { "fcmovne",{ ST, STi }, 0 },
10063 { "fcmovnbe",{ ST, STi }, 0 },
10064 { "fcmovnu",{ ST, STi }, 0 },
10065 { FGRPdb_4 },
10066 { "fucomi", { ST, STi }, 0 },
10067 { "fcomi", { ST, STi }, 0 },
10068 { Bad_Opcode },
10069 },
10070 /* dc */
10071 {
10072 { "fadd", { STi, ST }, 0 },
10073 { "fmul", { STi, ST }, 0 },
10074 { Bad_Opcode },
10075 { Bad_Opcode },
10076 { "fsub{!M|r}", { STi, ST }, 0 },
10077 { "fsub{M|}", { STi, ST }, 0 },
10078 { "fdiv{!M|r}", { STi, ST }, 0 },
10079 { "fdiv{M|}", { STi, ST }, 0 },
10080 },
10081 /* dd */
10082 {
10083 { "ffree", { STi }, 0 },
10084 { Bad_Opcode },
10085 { "fst", { STi }, 0 },
10086 { "fstp", { STi }, 0 },
10087 { "fucom", { STi }, 0 },
10088 { "fucomp", { STi }, 0 },
10089 { Bad_Opcode },
10090 { Bad_Opcode },
10091 },
10092 /* de */
10093 {
10094 { "faddp", { STi, ST }, 0 },
10095 { "fmulp", { STi, ST }, 0 },
10096 { Bad_Opcode },
10097 { FGRPde_3 },
10098 { "fsub{!M|r}p", { STi, ST }, 0 },
10099 { "fsub{M|}p", { STi, ST }, 0 },
10100 { "fdiv{!M|r}p", { STi, ST }, 0 },
10101 { "fdiv{M|}p", { STi, ST }, 0 },
10102 },
10103 /* df */
10104 {
10105 { "ffreep", { STi }, 0 },
10106 { Bad_Opcode },
10107 { Bad_Opcode },
10108 { Bad_Opcode },
10109 { FGRPdf_4 },
10110 { "fucomip", { ST, STi }, 0 },
10111 { "fcomip", { ST, STi }, 0 },
10112 { Bad_Opcode },
10113 },
10114 };
10115
10116 static const char *const fgrps[][8] = {
10117 /* Bad opcode 0 */
10118 {
10119 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10120 },
10121
10122 /* d9_2 1 */
10123 {
10124 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10125 },
10126
10127 /* d9_4 2 */
10128 {
10129 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10130 },
10131
10132 /* d9_5 3 */
10133 {
10134 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10135 },
10136
10137 /* d9_6 4 */
10138 {
10139 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10140 },
10141
10142 /* d9_7 5 */
10143 {
10144 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10145 },
10146
10147 /* da_5 6 */
10148 {
10149 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10150 },
10151
10152 /* db_4 7 */
10153 {
10154 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10155 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10156 },
10157
10158 /* de_3 8 */
10159 {
10160 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10161 },
10162
10163 /* df_4 9 */
10164 {
10165 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10166 },
10167 };
10168
10169 static void
10170 swap_operand (instr_info *ins)
10171 {
10172 ins->mnemonicendp[0] = '.';
10173 ins->mnemonicendp[1] = 's';
10174 ins->mnemonicendp[2] = '\0';
10175 ins->mnemonicendp += 2;
10176 }
10177
10178 static void
10179 OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10180 int sizeflag ATTRIBUTE_UNUSED)
10181 {
10182 /* Skip mod/rm byte. */
10183 MODRM_CHECK;
10184 ins->codep++;
10185 }
10186
10187 static void
10188 dofloat (instr_info *ins, int sizeflag)
10189 {
10190 const struct dis386 *dp;
10191 unsigned char floatop;
10192
10193 floatop = ins->codep[-1];
10194
10195 if (ins->modrm.mod != 3)
10196 {
10197 int fp_indx = (floatop - 0xd8) * 8 + ins->modrm.reg;
10198
10199 putop (ins, float_mem[fp_indx], sizeflag);
10200 ins->obufp = ins->op_out[0];
10201 ins->op_ad = 2;
10202 OP_E (ins, float_mem_mode[fp_indx], sizeflag);
10203 return;
10204 }
10205 /* Skip mod/rm byte. */
10206 MODRM_CHECK;
10207 ins->codep++;
10208
10209 dp = &float_reg[floatop - 0xd8][ins->modrm.reg];
10210 if (dp->name == NULL)
10211 {
10212 putop (ins, fgrps[dp->op[0].bytemode][ins->modrm.rm], sizeflag);
10213
10214 /* Instruction fnstsw is only one with strange arg. */
10215 if (floatop == 0xdf && ins->codep[-1] == 0xe0)
10216 strcpy (ins->op_out[0], att_names16[0] + ins->intel_syntax);
10217 }
10218 else
10219 {
10220 putop (ins, dp->name, sizeflag);
10221
10222 ins->obufp = ins->op_out[0];
10223 ins->op_ad = 2;
10224 if (dp->op[0].rtn)
10225 (*dp->op[0].rtn) (ins, dp->op[0].bytemode, sizeflag);
10226
10227 ins->obufp = ins->op_out[1];
10228 ins->op_ad = 1;
10229 if (dp->op[1].rtn)
10230 (*dp->op[1].rtn) (ins, dp->op[1].bytemode, sizeflag);
10231 }
10232 }
10233
10234 static void
10235 OP_ST (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10236 int sizeflag ATTRIBUTE_UNUSED)
10237 {
10238 oappend_maybe_intel (ins, "%st");
10239 }
10240
10241 static void
10242 OP_STi (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10243 int sizeflag ATTRIBUTE_UNUSED)
10244 {
10245 sprintf (ins->scratchbuf, "%%st(%d)", ins->modrm.rm);
10246 oappend_maybe_intel (ins, ins->scratchbuf);
10247 }
10248
10249 /* Capital letters in template are macros. */
10250 static int
10251 putop (instr_info *ins, const char *in_template, int sizeflag)
10252 {
10253 const char *p;
10254 int alt = 0;
10255 int cond = 1;
10256 unsigned int l = 0, len = 0;
10257 char last[4];
10258
10259 for (p = in_template; *p; p++)
10260 {
10261 if (len > l)
10262 {
10263 if (l >= sizeof (last) || !ISUPPER (*p))
10264 abort ();
10265 last[l++] = *p;
10266 continue;
10267 }
10268 switch (*p)
10269 {
10270 default:
10271 *ins->obufp++ = *p;
10272 break;
10273 case '%':
10274 len++;
10275 break;
10276 case '!':
10277 cond = 0;
10278 break;
10279 case '{':
10280 if (ins->intel_syntax)
10281 {
10282 while (*++p != '|')
10283 if (*p == '}' || *p == '\0')
10284 abort ();
10285 alt = 1;
10286 }
10287 break;
10288 case '|':
10289 while (*++p != '}')
10290 {
10291 if (*p == '\0')
10292 abort ();
10293 }
10294 break;
10295 case '}':
10296 alt = 0;
10297 break;
10298 case 'A':
10299 if (ins->intel_syntax)
10300 break;
10301 if ((ins->need_modrm && ins->modrm.mod != 3)
10302 || (sizeflag & SUFFIX_ALWAYS))
10303 *ins->obufp++ = 'b';
10304 break;
10305 case 'B':
10306 if (l == 0)
10307 {
10308 case_B:
10309 if (ins->intel_syntax)
10310 break;
10311 if (sizeflag & SUFFIX_ALWAYS)
10312 *ins->obufp++ = 'b';
10313 }
10314 else if (l == 1 && last[0] == 'L')
10315 {
10316 if (ins->address_mode == mode_64bit
10317 && !(ins->prefixes & PREFIX_ADDR))
10318 {
10319 *ins->obufp++ = 'a';
10320 *ins->obufp++ = 'b';
10321 *ins->obufp++ = 's';
10322 }
10323
10324 goto case_B;
10325 }
10326 else
10327 abort ();
10328 break;
10329 case 'C':
10330 if (ins->intel_syntax && !alt)
10331 break;
10332 if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10333 {
10334 if (sizeflag & DFLAG)
10335 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10336 else
10337 *ins->obufp++ = ins->intel_syntax ? 'w' : 's';
10338 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10339 }
10340 break;
10341 case 'D':
10342 if (l == 1)
10343 {
10344 switch (last[0])
10345 {
10346 case 'X':
10347 if (!ins->vex.evex || ins->vex.w)
10348 *ins->obufp++ = 'd';
10349 else
10350 oappend (ins, "{bad}");
10351 break;
10352 default:
10353 abort ();
10354 }
10355 break;
10356 }
10357 if (l)
10358 abort ();
10359 if (ins->intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10360 break;
10361 USED_REX (REX_W);
10362 if (ins->modrm.mod == 3)
10363 {
10364 if (ins->rex & REX_W)
10365 *ins->obufp++ = 'q';
10366 else
10367 {
10368 if (sizeflag & DFLAG)
10369 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10370 else
10371 *ins->obufp++ = 'w';
10372 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10373 }
10374 }
10375 else
10376 *ins->obufp++ = 'w';
10377 break;
10378 case 'E': /* For jcxz/jecxz */
10379 if (ins->address_mode == mode_64bit)
10380 {
10381 if (sizeflag & AFLAG)
10382 *ins->obufp++ = 'r';
10383 else
10384 *ins->obufp++ = 'e';
10385 }
10386 else
10387 if (sizeflag & AFLAG)
10388 *ins->obufp++ = 'e';
10389 ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10390 break;
10391 case 'F':
10392 if (ins->intel_syntax)
10393 break;
10394 if ((ins->prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10395 {
10396 if (sizeflag & AFLAG)
10397 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
10398 else
10399 *ins->obufp++ = ins->address_mode == mode_64bit ? 'l' : 'w';
10400 ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10401 }
10402 break;
10403 case 'G':
10404 if (ins->intel_syntax || (ins->obufp[-1] != 's'
10405 && !(sizeflag & SUFFIX_ALWAYS)))
10406 break;
10407 if ((ins->rex & REX_W) || (sizeflag & DFLAG))
10408 *ins->obufp++ = 'l';
10409 else
10410 *ins->obufp++ = 'w';
10411 if (!(ins->rex & REX_W))
10412 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10413 break;
10414 case 'H':
10415 if (l == 0)
10416 {
10417 if (ins->intel_syntax)
10418 break;
10419 if ((ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10420 || (ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10421 {
10422 ins->used_prefixes |= ins->prefixes & (PREFIX_CS | PREFIX_DS);
10423 *ins->obufp++ = ',';
10424 *ins->obufp++ = 'p';
10425
10426 /* Set active_seg_prefix even if not set in 64-bit mode
10427 because here it is a valid branch hint. */
10428 if (ins->prefixes & PREFIX_DS)
10429 {
10430 ins->active_seg_prefix = PREFIX_DS;
10431 *ins->obufp++ = 't';
10432 }
10433 else
10434 {
10435 ins->active_seg_prefix = PREFIX_CS;
10436 *ins->obufp++ = 'n';
10437 }
10438 }
10439 }
10440 else if (l == 1 && last[0] == 'X')
10441 {
10442 if (!ins->vex.w)
10443 *ins->obufp++ = 'h';
10444 else
10445 oappend (ins, "{bad}");
10446 }
10447 else
10448 abort ();
10449 break;
10450 case 'K':
10451 USED_REX (REX_W);
10452 if (ins->rex & REX_W)
10453 *ins->obufp++ = 'q';
10454 else
10455 *ins->obufp++ = 'd';
10456 break;
10457 case 'L':
10458 abort ();
10459 case 'M':
10460 if (ins->intel_mnemonic != cond)
10461 *ins->obufp++ = 'r';
10462 break;
10463 case 'N':
10464 if ((ins->prefixes & PREFIX_FWAIT) == 0)
10465 *ins->obufp++ = 'n';
10466 else
10467 ins->used_prefixes |= PREFIX_FWAIT;
10468 break;
10469 case 'O':
10470 USED_REX (REX_W);
10471 if (ins->rex & REX_W)
10472 *ins->obufp++ = 'o';
10473 else if (ins->intel_syntax && (sizeflag & DFLAG))
10474 *ins->obufp++ = 'q';
10475 else
10476 *ins->obufp++ = 'd';
10477 if (!(ins->rex & REX_W))
10478 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10479 break;
10480 case '@':
10481 if (ins->address_mode == mode_64bit
10482 && (ins->isa64 == intel64 || (ins->rex & REX_W)
10483 || !(ins->prefixes & PREFIX_DATA)))
10484 {
10485 if (sizeflag & SUFFIX_ALWAYS)
10486 *ins->obufp++ = 'q';
10487 break;
10488 }
10489 /* Fall through. */
10490 case 'P':
10491 if (l == 0)
10492 {
10493 if ((ins->modrm.mod == 3 || !cond)
10494 && !(sizeflag & SUFFIX_ALWAYS))
10495 break;
10496 /* Fall through. */
10497 case 'T':
10498 if ((!(ins->rex & REX_W) && (ins->prefixes & PREFIX_DATA))
10499 || ((sizeflag & SUFFIX_ALWAYS)
10500 && ins->address_mode != mode_64bit))
10501 {
10502 *ins->obufp++ = (sizeflag & DFLAG)
10503 ? ins->intel_syntax ? 'd' : 'l' : 'w';
10504 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10505 }
10506 else if (sizeflag & SUFFIX_ALWAYS)
10507 *ins->obufp++ = 'q';
10508 }
10509 else if (l == 1 && last[0] == 'L')
10510 {
10511 if ((ins->prefixes & PREFIX_DATA)
10512 || (ins->rex & REX_W)
10513 || (sizeflag & SUFFIX_ALWAYS))
10514 {
10515 USED_REX (REX_W);
10516 if (ins->rex & REX_W)
10517 *ins->obufp++ = 'q';
10518 else
10519 {
10520 if (sizeflag & DFLAG)
10521 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10522 else
10523 *ins->obufp++ = 'w';
10524 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10525 }
10526 }
10527 }
10528 else
10529 abort ();
10530 break;
10531 case 'Q':
10532 if (l == 0)
10533 {
10534 if (ins->intel_syntax && !alt)
10535 break;
10536 USED_REX (REX_W);
10537 if ((ins->need_modrm && ins->modrm.mod != 3)
10538 || (sizeflag & SUFFIX_ALWAYS))
10539 {
10540 if (ins->rex & REX_W)
10541 *ins->obufp++ = 'q';
10542 else
10543 {
10544 if (sizeflag & DFLAG)
10545 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10546 else
10547 *ins->obufp++ = 'w';
10548 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10549 }
10550 }
10551 }
10552 else if (l == 1 && last[0] == 'D')
10553 *ins->obufp++ = ins->vex.w ? 'q' : 'd';
10554 else if (l == 1 && last[0] == 'L')
10555 {
10556 if (cond ? ins->modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10557 : ins->address_mode != mode_64bit)
10558 break;
10559 if ((ins->rex & REX_W))
10560 {
10561 USED_REX (REX_W);
10562 *ins->obufp++ = 'q';
10563 }
10564 else if ((ins->address_mode == mode_64bit && cond)
10565 || (sizeflag & SUFFIX_ALWAYS))
10566 *ins->obufp++ = ins->intel_syntax? 'd' : 'l';
10567 }
10568 else
10569 abort ();
10570 break;
10571 case 'R':
10572 USED_REX (REX_W);
10573 if (ins->rex & REX_W)
10574 *ins->obufp++ = 'q';
10575 else if (sizeflag & DFLAG)
10576 {
10577 if (ins->intel_syntax)
10578 *ins->obufp++ = 'd';
10579 else
10580 *ins->obufp++ = 'l';
10581 }
10582 else
10583 *ins->obufp++ = 'w';
10584 if (ins->intel_syntax && !p[1]
10585 && ((ins->rex & REX_W) || (sizeflag & DFLAG)))
10586 *ins->obufp++ = 'e';
10587 if (!(ins->rex & REX_W))
10588 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10589 break;
10590 case 'S':
10591 if (l == 0)
10592 {
10593 case_S:
10594 if (ins->intel_syntax)
10595 break;
10596 if (sizeflag & SUFFIX_ALWAYS)
10597 {
10598 if (ins->rex & REX_W)
10599 *ins->obufp++ = 'q';
10600 else
10601 {
10602 if (sizeflag & DFLAG)
10603 *ins->obufp++ = 'l';
10604 else
10605 *ins->obufp++ = 'w';
10606 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10607 }
10608 }
10609 break;
10610 }
10611 if (l != 1)
10612 abort ();
10613 switch (last[0])
10614 {
10615 case 'L':
10616 if (ins->address_mode == mode_64bit
10617 && !(ins->prefixes & PREFIX_ADDR))
10618 {
10619 *ins->obufp++ = 'a';
10620 *ins->obufp++ = 'b';
10621 *ins->obufp++ = 's';
10622 }
10623
10624 goto case_S;
10625 case 'X':
10626 if (!ins->vex.evex || !ins->vex.w)
10627 *ins->obufp++ = 's';
10628 else
10629 oappend (ins, "{bad}");
10630 break;
10631 default:
10632 abort ();
10633 }
10634 break;
10635 case 'V':
10636 if (l == 0)
10637 abort ();
10638 else if (l == 1
10639 && (last[0] == 'L' || last[0] == 'X'))
10640 {
10641 if (last[0] == 'X')
10642 {
10643 *ins->obufp++ = '{';
10644 *ins->obufp++ = 'v';
10645 *ins->obufp++ = 'e';
10646 *ins->obufp++ = 'x';
10647 *ins->obufp++ = '}';
10648 }
10649 else if (ins->rex & REX_W)
10650 {
10651 *ins->obufp++ = 'a';
10652 *ins->obufp++ = 'b';
10653 *ins->obufp++ = 's';
10654 }
10655 }
10656 else
10657 abort ();
10658 goto case_S;
10659 case 'W':
10660 if (l == 0)
10661 {
10662 /* operand size flag for cwtl, cbtw */
10663 USED_REX (REX_W);
10664 if (ins->rex & REX_W)
10665 {
10666 if (ins->intel_syntax)
10667 *ins->obufp++ = 'd';
10668 else
10669 *ins->obufp++ = 'l';
10670 }
10671 else if (sizeflag & DFLAG)
10672 *ins->obufp++ = 'w';
10673 else
10674 *ins->obufp++ = 'b';
10675 if (!(ins->rex & REX_W))
10676 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10677 }
10678 else if (l == 1)
10679 {
10680 if (!ins->need_vex)
10681 abort ();
10682 if (last[0] == 'X')
10683 *ins->obufp++ = ins->vex.w ? 'd': 's';
10684 else if (last[0] == 'B')
10685 *ins->obufp++ = ins->vex.w ? 'w': 'b';
10686 else
10687 abort ();
10688 }
10689 else
10690 abort ();
10691 break;
10692 case 'X':
10693 if (l != 0)
10694 abort ();
10695 if (ins->need_vex
10696 ? ins->vex.prefix == DATA_PREFIX_OPCODE
10697 : ins->prefixes & PREFIX_DATA)
10698 {
10699 *ins->obufp++ = 'd';
10700 ins->used_prefixes |= PREFIX_DATA;
10701 }
10702 else
10703 *ins->obufp++ = 's';
10704 break;
10705 case 'Y':
10706 if (l == 1 && last[0] == 'X')
10707 {
10708 if (!ins->need_vex)
10709 abort ();
10710 if (ins->intel_syntax
10711 || ((ins->modrm.mod == 3 || ins->vex.b)
10712 && !(sizeflag & SUFFIX_ALWAYS)))
10713 break;
10714 switch (ins->vex.length)
10715 {
10716 case 128:
10717 *ins->obufp++ = 'x';
10718 break;
10719 case 256:
10720 *ins->obufp++ = 'y';
10721 break;
10722 case 512:
10723 if (!ins->vex.evex)
10724 default:
10725 abort ();
10726 }
10727 }
10728 else
10729 abort ();
10730 break;
10731 case 'Z':
10732 if (l == 0)
10733 {
10734 /* These insns ignore ModR/M.mod: Force it to 3 for OP_E(). */
10735 ins->modrm.mod = 3;
10736 if (!ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
10737 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
10738 }
10739 else if (l == 1 && last[0] == 'X')
10740 {
10741 if (!ins->vex.evex)
10742 abort ();
10743 if (ins->intel_syntax
10744 || ((ins->modrm.mod == 3 || ins->vex.b)
10745 && !(sizeflag & SUFFIX_ALWAYS)))
10746 break;
10747 switch (ins->vex.length)
10748 {
10749 case 128:
10750 *ins->obufp++ = 'x';
10751 break;
10752 case 256:
10753 *ins->obufp++ = 'y';
10754 break;
10755 case 512:
10756 *ins->obufp++ = 'z';
10757 break;
10758 default:
10759 abort ();
10760 }
10761 }
10762 else
10763 abort ();
10764 break;
10765 case '^':
10766 if (ins->intel_syntax)
10767 break;
10768 if (ins->isa64 == intel64 && (ins->rex & REX_W))
10769 {
10770 USED_REX (REX_W);
10771 *ins->obufp++ = 'q';
10772 break;
10773 }
10774 if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10775 {
10776 if (sizeflag & DFLAG)
10777 *ins->obufp++ = 'l';
10778 else
10779 *ins->obufp++ = 'w';
10780 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10781 }
10782 break;
10783 }
10784
10785 if (len == l)
10786 len = l = 0;
10787 }
10788 *ins->obufp = 0;
10789 ins->mnemonicendp = ins->obufp;
10790 return 0;
10791 }
10792
10793 static void
10794 oappend (instr_info *ins, const char *s)
10795 {
10796 ins->obufp = stpcpy (ins->obufp, s);
10797 }
10798
10799 static void
10800 append_seg (instr_info *ins)
10801 {
10802 /* Only print the active segment register. */
10803 if (!ins->active_seg_prefix)
10804 return;
10805
10806 ins->used_prefixes |= ins->active_seg_prefix;
10807 switch (ins->active_seg_prefix)
10808 {
10809 case PREFIX_CS:
10810 oappend_maybe_intel (ins, "%cs:");
10811 break;
10812 case PREFIX_DS:
10813 oappend_maybe_intel (ins, "%ds:");
10814 break;
10815 case PREFIX_SS:
10816 oappend_maybe_intel (ins, "%ss:");
10817 break;
10818 case PREFIX_ES:
10819 oappend_maybe_intel (ins, "%es:");
10820 break;
10821 case PREFIX_FS:
10822 oappend_maybe_intel (ins, "%fs:");
10823 break;
10824 case PREFIX_GS:
10825 oappend_maybe_intel (ins, "%gs:");
10826 break;
10827 default:
10828 break;
10829 }
10830 }
10831
10832 static void
10833 OP_indirE (instr_info *ins, int bytemode, int sizeflag)
10834 {
10835 if (!ins->intel_syntax)
10836 oappend (ins, "*");
10837 OP_E (ins, bytemode, sizeflag);
10838 }
10839
10840 static void
10841 print_operand_value (instr_info *ins, char *buf, int hex, bfd_vma disp)
10842 {
10843 if (ins->address_mode == mode_64bit)
10844 {
10845 if (hex)
10846 {
10847 char tmp[30];
10848 int i;
10849 buf[0] = '0';
10850 buf[1] = 'x';
10851 sprintf_vma (tmp, disp);
10852 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
10853 strcpy (buf + 2, tmp + i);
10854 }
10855 else
10856 {
10857 bfd_signed_vma v = disp;
10858 char tmp[30];
10859 int i;
10860 if (v < 0)
10861 {
10862 *(buf++) = '-';
10863 v = -disp;
10864 /* Check for possible overflow on 0x8000000000000000. */
10865 if (v < 0)
10866 {
10867 strcpy (buf, "9223372036854775808");
10868 return;
10869 }
10870 }
10871 if (!v)
10872 {
10873 strcpy (buf, "0");
10874 return;
10875 }
10876
10877 i = 0;
10878 tmp[29] = 0;
10879 while (v)
10880 {
10881 tmp[28 - i] = (v % 10) + '0';
10882 v /= 10;
10883 i++;
10884 }
10885 strcpy (buf, tmp + 29 - i);
10886 }
10887 }
10888 else
10889 {
10890 if (hex)
10891 sprintf (buf, "0x%x", (unsigned int) disp);
10892 else
10893 sprintf (buf, "%d", (int) disp);
10894 }
10895 }
10896
10897 /* Put DISP in BUF as signed hex number. */
10898
10899 static void
10900 print_displacement (instr_info *ins, char *buf, bfd_vma disp)
10901 {
10902 bfd_signed_vma val = disp;
10903 char tmp[30];
10904 int i, j = 0;
10905
10906 if (val < 0)
10907 {
10908 buf[j++] = '-';
10909 val = -disp;
10910
10911 /* Check for possible overflow. */
10912 if (val < 0)
10913 {
10914 switch (ins->address_mode)
10915 {
10916 case mode_64bit:
10917 strcpy (buf + j, "0x8000000000000000");
10918 break;
10919 case mode_32bit:
10920 strcpy (buf + j, "0x80000000");
10921 break;
10922 case mode_16bit:
10923 strcpy (buf + j, "0x8000");
10924 break;
10925 }
10926 return;
10927 }
10928 }
10929
10930 buf[j++] = '0';
10931 buf[j++] = 'x';
10932
10933 sprintf_vma (tmp, (bfd_vma) val);
10934 for (i = 0; tmp[i] == '0'; i++)
10935 continue;
10936 if (tmp[i] == '\0')
10937 i--;
10938 strcpy (buf + j, tmp + i);
10939 }
10940
10941 static void
10942 intel_operand_size (instr_info *ins, int bytemode, int sizeflag)
10943 {
10944 if (ins->vex.b)
10945 {
10946 if (!ins->vex.no_broadcast)
10947 switch (bytemode)
10948 {
10949 case x_mode:
10950 case evex_half_bcst_xmmq_mode:
10951 if (ins->vex.w)
10952 oappend (ins, "QWORD BCST ");
10953 else
10954 oappend (ins, "DWORD BCST ");
10955 break;
10956 case xh_mode:
10957 case evex_half_bcst_xmmqh_mode:
10958 case evex_half_bcst_xmmqdh_mode:
10959 oappend (ins, "WORD BCST ");
10960 break;
10961 default:
10962 ins->vex.no_broadcast = true;
10963 break;
10964 }
10965 return;
10966 }
10967 switch (bytemode)
10968 {
10969 case b_mode:
10970 case b_swap_mode:
10971 case db_mode:
10972 oappend (ins, "BYTE PTR ");
10973 break;
10974 case w_mode:
10975 case w_swap_mode:
10976 case dw_mode:
10977 oappend (ins, "WORD PTR ");
10978 break;
10979 case indir_v_mode:
10980 if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
10981 {
10982 oappend (ins, "QWORD PTR ");
10983 break;
10984 }
10985 /* Fall through. */
10986 case stack_v_mode:
10987 if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
10988 || (ins->rex & REX_W)))
10989 {
10990 oappend (ins, "QWORD PTR ");
10991 break;
10992 }
10993 /* Fall through. */
10994 case v_mode:
10995 case v_swap_mode:
10996 case dq_mode:
10997 USED_REX (REX_W);
10998 if (ins->rex & REX_W)
10999 oappend (ins, "QWORD PTR ");
11000 else if (bytemode == dq_mode)
11001 oappend (ins, "DWORD PTR ");
11002 else
11003 {
11004 if (sizeflag & DFLAG)
11005 oappend (ins, "DWORD PTR ");
11006 else
11007 oappend (ins, "WORD PTR ");
11008 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11009 }
11010 break;
11011 case z_mode:
11012 if ((ins->rex & REX_W) || (sizeflag & DFLAG))
11013 *ins->obufp++ = 'D';
11014 oappend (ins, "WORD PTR ");
11015 if (!(ins->rex & REX_W))
11016 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11017 break;
11018 case a_mode:
11019 if (sizeflag & DFLAG)
11020 oappend (ins, "QWORD PTR ");
11021 else
11022 oappend (ins, "DWORD PTR ");
11023 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11024 break;
11025 case movsxd_mode:
11026 if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11027 oappend (ins, "WORD PTR ");
11028 else
11029 oappend (ins, "DWORD PTR ");
11030 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11031 break;
11032 case d_mode:
11033 case d_swap_mode:
11034 oappend (ins, "DWORD PTR ");
11035 break;
11036 case q_mode:
11037 case q_swap_mode:
11038 oappend (ins, "QWORD PTR ");
11039 break;
11040 case m_mode:
11041 if (ins->address_mode == mode_64bit)
11042 oappend (ins, "QWORD PTR ");
11043 else
11044 oappend (ins, "DWORD PTR ");
11045 break;
11046 case f_mode:
11047 if (sizeflag & DFLAG)
11048 oappend (ins, "FWORD PTR ");
11049 else
11050 oappend (ins, "DWORD PTR ");
11051 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11052 break;
11053 case t_mode:
11054 oappend (ins, "TBYTE PTR ");
11055 break;
11056 case x_mode:
11057 case xh_mode:
11058 case x_swap_mode:
11059 case evex_x_gscat_mode:
11060 case evex_x_nobcst_mode:
11061 case bw_unit_mode:
11062 if (ins->need_vex)
11063 {
11064 switch (ins->vex.length)
11065 {
11066 case 128:
11067 oappend (ins, "XMMWORD PTR ");
11068 break;
11069 case 256:
11070 oappend (ins, "YMMWORD PTR ");
11071 break;
11072 case 512:
11073 oappend (ins, "ZMMWORD PTR ");
11074 break;
11075 default:
11076 abort ();
11077 }
11078 }
11079 else
11080 oappend (ins, "XMMWORD PTR ");
11081 break;
11082 case xmm_mode:
11083 oappend (ins, "XMMWORD PTR ");
11084 break;
11085 case ymm_mode:
11086 oappend (ins, "YMMWORD PTR ");
11087 break;
11088 case xmmq_mode:
11089 case evex_half_bcst_xmmqh_mode:
11090 case evex_half_bcst_xmmq_mode:
11091 if (!ins->need_vex)
11092 abort ();
11093
11094 switch (ins->vex.length)
11095 {
11096 case 128:
11097 oappend (ins, "QWORD PTR ");
11098 break;
11099 case 256:
11100 oappend (ins, "XMMWORD PTR ");
11101 break;
11102 case 512:
11103 oappend (ins, "YMMWORD PTR ");
11104 break;
11105 default:
11106 abort ();
11107 }
11108 break;
11109 case xmmdw_mode:
11110 if (!ins->need_vex)
11111 abort ();
11112
11113 switch (ins->vex.length)
11114 {
11115 case 128:
11116 oappend (ins, "WORD PTR ");
11117 break;
11118 case 256:
11119 oappend (ins, "DWORD PTR ");
11120 break;
11121 case 512:
11122 oappend (ins, "QWORD PTR ");
11123 break;
11124 default:
11125 abort ();
11126 }
11127 break;
11128 case xmmqd_mode:
11129 case evex_half_bcst_xmmqdh_mode:
11130 if (!ins->need_vex)
11131 abort ();
11132
11133 switch (ins->vex.length)
11134 {
11135 case 128:
11136 oappend (ins, "DWORD PTR ");
11137 break;
11138 case 256:
11139 oappend (ins, "QWORD PTR ");
11140 break;
11141 case 512:
11142 oappend (ins, "XMMWORD PTR ");
11143 break;
11144 default:
11145 abort ();
11146 }
11147 break;
11148 case ymmq_mode:
11149 if (!ins->need_vex)
11150 abort ();
11151
11152 switch (ins->vex.length)
11153 {
11154 case 128:
11155 oappend (ins, "QWORD PTR ");
11156 break;
11157 case 256:
11158 oappend (ins, "YMMWORD PTR ");
11159 break;
11160 case 512:
11161 oappend (ins, "ZMMWORD PTR ");
11162 break;
11163 default:
11164 abort ();
11165 }
11166 break;
11167 case o_mode:
11168 oappend (ins, "OWORD PTR ");
11169 break;
11170 case vex_vsib_d_w_dq_mode:
11171 case vex_vsib_q_w_dq_mode:
11172 if (!ins->need_vex)
11173 abort ();
11174 if (ins->vex.w)
11175 oappend (ins, "QWORD PTR ");
11176 else
11177 oappend (ins, "DWORD PTR ");
11178 break;
11179 case mask_bd_mode:
11180 if (!ins->need_vex || ins->vex.length != 128)
11181 abort ();
11182 if (ins->vex.w)
11183 oappend (ins, "DWORD PTR ");
11184 else
11185 oappend (ins, "BYTE PTR ");
11186 break;
11187 case mask_mode:
11188 if (!ins->need_vex)
11189 abort ();
11190 if (ins->vex.w)
11191 oappend (ins, "QWORD PTR ");
11192 else
11193 oappend (ins, "WORD PTR ");
11194 break;
11195 case v_bnd_mode:
11196 case v_bndmk_mode:
11197 default:
11198 break;
11199 }
11200 }
11201
11202 static void
11203 print_register (instr_info *ins, unsigned int reg, unsigned int rexmask,
11204 int bytemode, int sizeflag)
11205 {
11206 const char *const *names;
11207
11208 USED_REX (rexmask);
11209 if (ins->rex & rexmask)
11210 reg += 8;
11211
11212 switch (bytemode)
11213 {
11214 case b_mode:
11215 case b_swap_mode:
11216 if (reg & 4)
11217 USED_REX (0);
11218 if (ins->rex)
11219 names = att_names8rex;
11220 else
11221 names = att_names8;
11222 break;
11223 case w_mode:
11224 names = att_names16;
11225 break;
11226 case d_mode:
11227 case dw_mode:
11228 case db_mode:
11229 names = att_names32;
11230 break;
11231 case q_mode:
11232 names = att_names64;
11233 break;
11234 case m_mode:
11235 case v_bnd_mode:
11236 names = ins->address_mode == mode_64bit ? att_names64 : att_names32;
11237 break;
11238 case bnd_mode:
11239 case bnd_swap_mode:
11240 if (reg > 0x3)
11241 {
11242 oappend (ins, "(bad)");
11243 return;
11244 }
11245 names = att_names_bnd;
11246 break;
11247 case indir_v_mode:
11248 if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11249 {
11250 names = att_names64;
11251 break;
11252 }
11253 /* Fall through. */
11254 case stack_v_mode:
11255 if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11256 || (ins->rex & REX_W)))
11257 {
11258 names = att_names64;
11259 break;
11260 }
11261 bytemode = v_mode;
11262 /* Fall through. */
11263 case v_mode:
11264 case v_swap_mode:
11265 case dq_mode:
11266 USED_REX (REX_W);
11267 if (ins->rex & REX_W)
11268 names = att_names64;
11269 else if (bytemode != v_mode && bytemode != v_swap_mode)
11270 names = att_names32;
11271 else
11272 {
11273 if (sizeflag & DFLAG)
11274 names = att_names32;
11275 else
11276 names = att_names16;
11277 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11278 }
11279 break;
11280 case movsxd_mode:
11281 if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11282 names = att_names16;
11283 else
11284 names = att_names32;
11285 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11286 break;
11287 case va_mode:
11288 names = (ins->address_mode == mode_64bit
11289 ? att_names64 : att_names32);
11290 if (!(ins->prefixes & PREFIX_ADDR))
11291 names = (ins->address_mode == mode_16bit
11292 ? att_names16 : names);
11293 else
11294 {
11295 /* Remove "addr16/addr32". */
11296 ins->all_prefixes[ins->last_addr_prefix] = 0;
11297 names = (ins->address_mode != mode_32bit
11298 ? att_names32 : att_names16);
11299 ins->used_prefixes |= PREFIX_ADDR;
11300 }
11301 break;
11302 case mask_bd_mode:
11303 case mask_mode:
11304 if (reg > 0x7)
11305 {
11306 oappend (ins, "(bad)");
11307 return;
11308 }
11309 names = att_names_mask;
11310 break;
11311 case 0:
11312 return;
11313 default:
11314 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
11315 return;
11316 }
11317 oappend_maybe_intel (ins, names[reg]);
11318 }
11319
11320 static void
11321 OP_E_memory (instr_info *ins, int bytemode, int sizeflag)
11322 {
11323 bfd_vma disp = 0;
11324 int add = (ins->rex & REX_B) ? 8 : 0;
11325 int riprel = 0;
11326 int shift;
11327
11328 if (ins->vex.evex)
11329 {
11330 switch (bytemode)
11331 {
11332 case dw_mode:
11333 case w_mode:
11334 case w_swap_mode:
11335 shift = 1;
11336 break;
11337 case db_mode:
11338 case b_mode:
11339 shift = 0;
11340 break;
11341 case dq_mode:
11342 if (ins->address_mode != mode_64bit)
11343 {
11344 case d_mode:
11345 case d_swap_mode:
11346 shift = 2;
11347 break;
11348 }
11349 /* fall through */
11350 case vex_vsib_d_w_dq_mode:
11351 case vex_vsib_q_w_dq_mode:
11352 case evex_x_gscat_mode:
11353 shift = ins->vex.w ? 3 : 2;
11354 break;
11355 case xh_mode:
11356 case evex_half_bcst_xmmqh_mode:
11357 case evex_half_bcst_xmmqdh_mode:
11358 if (ins->vex.b)
11359 {
11360 shift = ins->vex.w ? 2 : 1;
11361 break;
11362 }
11363 /* Fall through. */
11364 case x_mode:
11365 case evex_half_bcst_xmmq_mode:
11366 if (ins->vex.b)
11367 {
11368 shift = ins->vex.w ? 3 : 2;
11369 break;
11370 }
11371 /* Fall through. */
11372 case xmmqd_mode:
11373 case xmmdw_mode:
11374 case xmmq_mode:
11375 case ymmq_mode:
11376 case evex_x_nobcst_mode:
11377 case x_swap_mode:
11378 switch (ins->vex.length)
11379 {
11380 case 128:
11381 shift = 4;
11382 break;
11383 case 256:
11384 shift = 5;
11385 break;
11386 case 512:
11387 shift = 6;
11388 break;
11389 default:
11390 abort ();
11391 }
11392 /* Make necessary corrections to shift for modes that need it. */
11393 if (bytemode == xmmq_mode
11394 || bytemode == evex_half_bcst_xmmqh_mode
11395 || bytemode == evex_half_bcst_xmmq_mode
11396 || (bytemode == ymmq_mode && ins->vex.length == 128))
11397 shift -= 1;
11398 else if (bytemode == xmmqd_mode
11399 || bytemode == evex_half_bcst_xmmqdh_mode)
11400 shift -= 2;
11401 else if (bytemode == xmmdw_mode)
11402 shift -= 3;
11403 break;
11404 case ymm_mode:
11405 shift = 5;
11406 break;
11407 case xmm_mode:
11408 shift = 4;
11409 break;
11410 case q_mode:
11411 case q_swap_mode:
11412 shift = 3;
11413 break;
11414 case bw_unit_mode:
11415 shift = ins->vex.w ? 1 : 0;
11416 break;
11417 default:
11418 abort ();
11419 }
11420 }
11421 else
11422 shift = 0;
11423
11424 USED_REX (REX_B);
11425 if (ins->intel_syntax)
11426 intel_operand_size (ins, bytemode, sizeflag);
11427 append_seg (ins);
11428
11429 if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
11430 {
11431 /* 32/64 bit address mode */
11432 int havedisp;
11433 int havebase;
11434 int needindex;
11435 int needaddr32;
11436 int base, rbase;
11437 int vindex = 0;
11438 int scale = 0;
11439 int addr32flag = !((sizeflag & AFLAG)
11440 || bytemode == v_bnd_mode
11441 || bytemode == v_bndmk_mode
11442 || bytemode == bnd_mode
11443 || bytemode == bnd_swap_mode);
11444 bool check_gather = false;
11445 const char *const *indexes = NULL;
11446
11447 havebase = 1;
11448 base = ins->modrm.rm;
11449
11450 if (base == 4)
11451 {
11452 vindex = ins->sib.index;
11453 USED_REX (REX_X);
11454 if (ins->rex & REX_X)
11455 vindex += 8;
11456 switch (bytemode)
11457 {
11458 case vex_vsib_d_w_dq_mode:
11459 case vex_vsib_q_w_dq_mode:
11460 if (!ins->need_vex)
11461 abort ();
11462 if (ins->vex.evex)
11463 {
11464 if (!ins->vex.v)
11465 vindex += 16;
11466 check_gather = ins->obufp == ins->op_out[1];
11467 }
11468
11469 switch (ins->vex.length)
11470 {
11471 case 128:
11472 indexes = att_names_xmm;
11473 break;
11474 case 256:
11475 if (!ins->vex.w
11476 || bytemode == vex_vsib_q_w_dq_mode)
11477 indexes = att_names_ymm;
11478 else
11479 indexes = att_names_xmm;
11480 break;
11481 case 512:
11482 if (!ins->vex.w
11483 || bytemode == vex_vsib_q_w_dq_mode)
11484 indexes = att_names_zmm;
11485 else
11486 indexes = att_names_ymm;
11487 break;
11488 default:
11489 abort ();
11490 }
11491 break;
11492 default:
11493 if (vindex != 4)
11494 indexes = ins->address_mode == mode_64bit && !addr32flag
11495 ? att_names64 : att_names32;
11496 break;
11497 }
11498 scale = ins->sib.scale;
11499 base = ins->sib.base;
11500 ins->codep++;
11501 }
11502 else
11503 {
11504 /* Check for mandatory SIB. */
11505 if (bytemode == vex_vsib_d_w_dq_mode
11506 || bytemode == vex_vsib_q_w_dq_mode
11507 || bytemode == vex_sibmem_mode)
11508 {
11509 oappend (ins, "(bad)");
11510 return;
11511 }
11512 }
11513 rbase = base + add;
11514
11515 switch (ins->modrm.mod)
11516 {
11517 case 0:
11518 if (base == 5)
11519 {
11520 havebase = 0;
11521 if (ins->address_mode == mode_64bit && !ins->has_sib)
11522 riprel = 1;
11523 disp = get32s (ins);
11524 if (riprel && bytemode == v_bndmk_mode)
11525 {
11526 oappend (ins, "(bad)");
11527 return;
11528 }
11529 }
11530 break;
11531 case 1:
11532 FETCH_DATA (ins->info, ins->codep + 1);
11533 disp = *ins->codep++;
11534 if ((disp & 0x80) != 0)
11535 disp -= 0x100;
11536 if (ins->vex.evex && shift > 0)
11537 disp <<= shift;
11538 break;
11539 case 2:
11540 disp = get32s (ins);
11541 break;
11542 }
11543
11544 needindex = 0;
11545 needaddr32 = 0;
11546 if (ins->has_sib
11547 && !havebase
11548 && !indexes
11549 && ins->address_mode != mode_16bit)
11550 {
11551 if (ins->address_mode == mode_64bit)
11552 {
11553 if (addr32flag)
11554 {
11555 /* Without base nor index registers, zero-extend the
11556 lower 32-bit displacement to 64 bits. */
11557 disp = (unsigned int) disp;
11558 needindex = 1;
11559 }
11560 needaddr32 = 1;
11561 }
11562 else
11563 {
11564 /* In 32-bit mode, we need index register to tell [offset]
11565 from [eiz*1 + offset]. */
11566 needindex = 1;
11567 }
11568 }
11569
11570 havedisp = (havebase
11571 || needindex
11572 || (ins->has_sib && (indexes || scale != 0)));
11573
11574 if (!ins->intel_syntax)
11575 if (ins->modrm.mod != 0 || base == 5)
11576 {
11577 if (havedisp || riprel)
11578 print_displacement (ins, ins->scratchbuf, disp);
11579 else
11580 print_operand_value (ins, ins->scratchbuf, 1, disp);
11581 oappend (ins, ins->scratchbuf);
11582 if (riprel)
11583 {
11584 set_op (ins, disp, true);
11585 oappend (ins, !addr32flag ? "(%rip)" : "(%eip)");
11586 }
11587 }
11588
11589 if ((havebase || indexes || needindex || needaddr32 || riprel)
11590 && (ins->address_mode != mode_64bit
11591 || ((bytemode != v_bnd_mode)
11592 && (bytemode != v_bndmk_mode)
11593 && (bytemode != bnd_mode)
11594 && (bytemode != bnd_swap_mode))))
11595 ins->used_prefixes |= PREFIX_ADDR;
11596
11597 if (havedisp || (ins->intel_syntax && riprel))
11598 {
11599 *ins->obufp++ = ins->open_char;
11600 if (ins->intel_syntax && riprel)
11601 {
11602 set_op (ins, disp, true);
11603 oappend (ins, !addr32flag ? "rip" : "eip");
11604 }
11605 *ins->obufp = '\0';
11606 if (havebase)
11607 oappend_maybe_intel (ins,
11608 (ins->address_mode == mode_64bit && !addr32flag
11609 ? att_names64 : att_names32)[rbase]);
11610 if (ins->has_sib)
11611 {
11612 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
11613 print index to tell base + index from base. */
11614 if (scale != 0
11615 || needindex
11616 || indexes
11617 || (havebase && base != ESP_REG_NUM))
11618 {
11619 if (!ins->intel_syntax || havebase)
11620 {
11621 *ins->obufp++ = ins->separator_char;
11622 *ins->obufp = '\0';
11623 }
11624 if (indexes)
11625 {
11626 if (ins->address_mode == mode_64bit || vindex < 16)
11627 oappend_maybe_intel (ins, indexes[vindex]);
11628 else
11629 oappend (ins, "(bad)");
11630 }
11631 else
11632 oappend_maybe_intel (ins,
11633 ins->address_mode == mode_64bit
11634 && !addr32flag ? att_index64
11635 : att_index32);
11636
11637 *ins->obufp++ = ins->scale_char;
11638 *ins->obufp = '\0';
11639 sprintf (ins->scratchbuf, "%d", 1 << scale);
11640 oappend (ins, ins->scratchbuf);
11641 }
11642 }
11643 if (ins->intel_syntax
11644 && (disp || ins->modrm.mod != 0 || base == 5))
11645 {
11646 if (!havedisp || (bfd_signed_vma) disp >= 0)
11647 {
11648 *ins->obufp++ = '+';
11649 *ins->obufp = '\0';
11650 }
11651 else if (ins->modrm.mod != 1 && disp != -disp)
11652 {
11653 *ins->obufp++ = '-';
11654 *ins->obufp = '\0';
11655 disp = -disp;
11656 }
11657
11658 if (havedisp)
11659 print_displacement (ins, ins->scratchbuf, disp);
11660 else
11661 print_operand_value (ins, ins->scratchbuf, 1, disp);
11662 oappend (ins, ins->scratchbuf);
11663 }
11664
11665 *ins->obufp++ = ins->close_char;
11666 *ins->obufp = '\0';
11667
11668 if (check_gather)
11669 {
11670 /* Both XMM/YMM/ZMM registers must be distinct. */
11671 int modrm_reg = ins->modrm.reg;
11672
11673 if (ins->rex & REX_R)
11674 modrm_reg += 8;
11675 if (!ins->vex.r)
11676 modrm_reg += 16;
11677 if (vindex == modrm_reg)
11678 oappend (ins, "/(bad)");
11679 }
11680 }
11681 else if (ins->intel_syntax)
11682 {
11683 if (ins->modrm.mod != 0 || base == 5)
11684 {
11685 if (!ins->active_seg_prefix)
11686 {
11687 oappend_maybe_intel (ins, att_names_seg[ds_reg - es_reg]);
11688 oappend (ins, ":");
11689 }
11690 print_operand_value (ins, ins->scratchbuf, 1, disp);
11691 oappend (ins, ins->scratchbuf);
11692 }
11693 }
11694 }
11695 else if (bytemode == v_bnd_mode
11696 || bytemode == v_bndmk_mode
11697 || bytemode == bnd_mode
11698 || bytemode == bnd_swap_mode
11699 || bytemode == vex_vsib_d_w_dq_mode
11700 || bytemode == vex_vsib_q_w_dq_mode)
11701 {
11702 oappend (ins, "(bad)");
11703 return;
11704 }
11705 else
11706 {
11707 /* 16 bit address mode */
11708 ins->used_prefixes |= ins->prefixes & PREFIX_ADDR;
11709 switch (ins->modrm.mod)
11710 {
11711 case 0:
11712 if (ins->modrm.rm == 6)
11713 {
11714 disp = get16 (ins);
11715 if ((disp & 0x8000) != 0)
11716 disp -= 0x10000;
11717 }
11718 break;
11719 case 1:
11720 FETCH_DATA (ins->info, ins->codep + 1);
11721 disp = *ins->codep++;
11722 if ((disp & 0x80) != 0)
11723 disp -= 0x100;
11724 if (ins->vex.evex && shift > 0)
11725 disp <<= shift;
11726 break;
11727 case 2:
11728 disp = get16 (ins);
11729 if ((disp & 0x8000) != 0)
11730 disp -= 0x10000;
11731 break;
11732 }
11733
11734 if (!ins->intel_syntax)
11735 if (ins->modrm.mod != 0 || ins->modrm.rm == 6)
11736 {
11737 print_displacement (ins, ins->scratchbuf, disp);
11738 oappend (ins, ins->scratchbuf);
11739 }
11740
11741 if (ins->modrm.mod != 0 || ins->modrm.rm != 6)
11742 {
11743 *ins->obufp++ = ins->open_char;
11744 *ins->obufp = '\0';
11745 oappend (ins,
11746 (ins->intel_syntax ? intel_index16
11747 : att_index16)[ins->modrm.rm]);
11748 if (ins->intel_syntax
11749 && (disp || ins->modrm.mod != 0 || ins->modrm.rm == 6))
11750 {
11751 if ((bfd_signed_vma) disp >= 0)
11752 {
11753 *ins->obufp++ = '+';
11754 *ins->obufp = '\0';
11755 }
11756 else if (ins->modrm.mod != 1)
11757 {
11758 *ins->obufp++ = '-';
11759 *ins->obufp = '\0';
11760 disp = -disp;
11761 }
11762
11763 print_displacement (ins, ins->scratchbuf, disp);
11764 oappend (ins, ins->scratchbuf);
11765 }
11766
11767 *ins->obufp++ = ins->close_char;
11768 *ins->obufp = '\0';
11769 }
11770 else if (ins->intel_syntax)
11771 {
11772 if (!ins->active_seg_prefix)
11773 {
11774 oappend_maybe_intel (ins, att_names_seg[ds_reg - es_reg]);
11775 oappend (ins, ":");
11776 }
11777 print_operand_value (ins, ins->scratchbuf, 1, disp & 0xffff);
11778 oappend (ins, ins->scratchbuf);
11779 }
11780 }
11781 if (ins->vex.b)
11782 {
11783 ins->evex_used |= EVEX_b_used;
11784
11785 /* Broadcast can only ever be valid for memory sources. */
11786 if (ins->obufp == ins->op_out[0])
11787 ins->vex.no_broadcast = true;
11788
11789 if (!ins->vex.no_broadcast
11790 && (!ins->intel_syntax || !(ins->evex_used & EVEX_len_used)))
11791 {
11792 if (bytemode == xh_mode)
11793 {
11794 if (ins->vex.w)
11795 oappend (ins, "{bad}");
11796 else
11797 {
11798 switch (ins->vex.length)
11799 {
11800 case 128:
11801 oappend (ins, "{1to8}");
11802 break;
11803 case 256:
11804 oappend (ins, "{1to16}");
11805 break;
11806 case 512:
11807 oappend (ins, "{1to32}");
11808 break;
11809 default:
11810 abort ();
11811 }
11812 }
11813 }
11814 else if (bytemode == q_mode
11815 || bytemode == ymmq_mode)
11816 ins->vex.no_broadcast = true;
11817 else if (ins->vex.w
11818 || bytemode == evex_half_bcst_xmmqdh_mode
11819 || bytemode == evex_half_bcst_xmmq_mode)
11820 {
11821 switch (ins->vex.length)
11822 {
11823 case 128:
11824 oappend (ins, "{1to2}");
11825 break;
11826 case 256:
11827 oappend (ins, "{1to4}");
11828 break;
11829 case 512:
11830 oappend (ins, "{1to8}");
11831 break;
11832 default:
11833 abort ();
11834 }
11835 }
11836 else if (bytemode == x_mode
11837 || bytemode == evex_half_bcst_xmmqh_mode)
11838 {
11839 switch (ins->vex.length)
11840 {
11841 case 128:
11842 oappend (ins, "{1to4}");
11843 break;
11844 case 256:
11845 oappend (ins, "{1to8}");
11846 break;
11847 case 512:
11848 oappend (ins, "{1to16}");
11849 break;
11850 default:
11851 abort ();
11852 }
11853 }
11854 else
11855 ins->vex.no_broadcast = true;
11856 }
11857 if (ins->vex.no_broadcast)
11858 oappend (ins, "{bad}");
11859 }
11860 }
11861
11862 static void
11863 OP_E (instr_info *ins, int bytemode, int sizeflag)
11864 {
11865 /* Skip mod/rm byte. */
11866 MODRM_CHECK;
11867 ins->codep++;
11868
11869 if (ins->modrm.mod == 3)
11870 {
11871 if ((sizeflag & SUFFIX_ALWAYS)
11872 && (bytemode == b_swap_mode
11873 || bytemode == bnd_swap_mode
11874 || bytemode == v_swap_mode))
11875 swap_operand (ins);
11876
11877 print_register (ins, ins->modrm.rm, REX_B, bytemode, sizeflag);
11878 }
11879 else
11880 OP_E_memory (ins, bytemode, sizeflag);
11881 }
11882
11883 static void
11884 OP_G (instr_info *ins, int bytemode, int sizeflag)
11885 {
11886 if (ins->vex.evex && !ins->vex.r && ins->address_mode == mode_64bit)
11887 {
11888 oappend (ins, "(bad)");
11889 return;
11890 }
11891
11892 print_register (ins, ins->modrm.reg, REX_R, bytemode, sizeflag);
11893 }
11894
11895 #ifdef BFD64
11896 static bfd_vma
11897 get64 (instr_info *ins)
11898 {
11899 bfd_vma x;
11900 unsigned int a;
11901 unsigned int b;
11902
11903 FETCH_DATA (ins->info, ins->codep + 8);
11904 a = *ins->codep++ & 0xff;
11905 a |= (*ins->codep++ & 0xff) << 8;
11906 a |= (*ins->codep++ & 0xff) << 16;
11907 a |= (*ins->codep++ & 0xffu) << 24;
11908 b = *ins->codep++ & 0xff;
11909 b |= (*ins->codep++ & 0xff) << 8;
11910 b |= (*ins->codep++ & 0xff) << 16;
11911 b |= (*ins->codep++ & 0xffu) << 24;
11912 x = a + ((bfd_vma) b << 32);
11913 return x;
11914 }
11915 #else
11916 static bfd_vma
11917 get64 (instr_info *ins ATTRIBUTE_UNUSED)
11918 {
11919 abort ();
11920 return 0;
11921 }
11922 #endif
11923
11924 static bfd_signed_vma
11925 get32 (instr_info *ins)
11926 {
11927 bfd_vma x = 0;
11928
11929 FETCH_DATA (ins->info, ins->codep + 4);
11930 x = *ins->codep++ & (bfd_vma) 0xff;
11931 x |= (*ins->codep++ & (bfd_vma) 0xff) << 8;
11932 x |= (*ins->codep++ & (bfd_vma) 0xff) << 16;
11933 x |= (*ins->codep++ & (bfd_vma) 0xff) << 24;
11934 return x;
11935 }
11936
11937 static bfd_signed_vma
11938 get32s (instr_info *ins)
11939 {
11940 bfd_vma x = 0;
11941
11942 FETCH_DATA (ins->info, ins->codep + 4);
11943 x = *ins->codep++ & (bfd_vma) 0xff;
11944 x |= (*ins->codep++ & (bfd_vma) 0xff) << 8;
11945 x |= (*ins->codep++ & (bfd_vma) 0xff) << 16;
11946 x |= (*ins->codep++ & (bfd_vma) 0xff) << 24;
11947
11948 x = (x ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
11949
11950 return x;
11951 }
11952
11953 static int
11954 get16 (instr_info *ins)
11955 {
11956 int x = 0;
11957
11958 FETCH_DATA (ins->info, ins->codep + 2);
11959 x = *ins->codep++ & 0xff;
11960 x |= (*ins->codep++ & 0xff) << 8;
11961 return x;
11962 }
11963
11964 static void
11965 set_op (instr_info *ins, bfd_vma op, bool riprel)
11966 {
11967 ins->op_index[ins->op_ad] = ins->op_ad;
11968 if (ins->address_mode == mode_64bit)
11969 ins->op_address[ins->op_ad] = op;
11970 else /* Mask to get a 32-bit address. */
11971 ins->op_address[ins->op_ad] = op & 0xffffffff;
11972 ins->op_riprel[ins->op_ad] = riprel;
11973 }
11974
11975 static void
11976 OP_REG (instr_info *ins, int code, int sizeflag)
11977 {
11978 const char *s;
11979 int add;
11980
11981 switch (code)
11982 {
11983 case es_reg: case ss_reg: case cs_reg:
11984 case ds_reg: case fs_reg: case gs_reg:
11985 oappend_maybe_intel (ins, att_names_seg[code - es_reg]);
11986 return;
11987 }
11988
11989 USED_REX (REX_B);
11990 if (ins->rex & REX_B)
11991 add = 8;
11992 else
11993 add = 0;
11994
11995 switch (code)
11996 {
11997 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
11998 case sp_reg: case bp_reg: case si_reg: case di_reg:
11999 s = att_names16[code - ax_reg + add];
12000 break;
12001 case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12002 USED_REX (0);
12003 /* Fall through. */
12004 case al_reg: case cl_reg: case dl_reg: case bl_reg:
12005 if (ins->rex)
12006 s = att_names8rex[code - al_reg + add];
12007 else
12008 s = att_names8[code - al_reg];
12009 break;
12010 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12011 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12012 if (ins->address_mode == mode_64bit
12013 && ((sizeflag & DFLAG) || (ins->rex & REX_W)))
12014 {
12015 s = att_names64[code - rAX_reg + add];
12016 break;
12017 }
12018 code += eAX_reg - rAX_reg;
12019 /* Fall through. */
12020 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12021 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12022 USED_REX (REX_W);
12023 if (ins->rex & REX_W)
12024 s = att_names64[code - eAX_reg + add];
12025 else
12026 {
12027 if (sizeflag & DFLAG)
12028 s = att_names32[code - eAX_reg + add];
12029 else
12030 s = att_names16[code - eAX_reg + add];
12031 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12032 }
12033 break;
12034 default:
12035 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12036 return;
12037 }
12038 oappend_maybe_intel (ins, s);
12039 }
12040
12041 static void
12042 OP_IMREG (instr_info *ins, int code, int sizeflag)
12043 {
12044 const char *s;
12045
12046 switch (code)
12047 {
12048 case indir_dx_reg:
12049 if (!ins->intel_syntax)
12050 {
12051 oappend (ins, "(%dx)");
12052 return;
12053 }
12054 s = att_names16[dx_reg - ax_reg];
12055 break;
12056 case al_reg: case cl_reg:
12057 s = att_names8[code - al_reg];
12058 break;
12059 case eAX_reg:
12060 USED_REX (REX_W);
12061 if (ins->rex & REX_W)
12062 {
12063 s = *att_names64;
12064 break;
12065 }
12066 /* Fall through. */
12067 case z_mode_ax_reg:
12068 if ((ins->rex & REX_W) || (sizeflag & DFLAG))
12069 s = *att_names32;
12070 else
12071 s = *att_names16;
12072 if (!(ins->rex & REX_W))
12073 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12074 break;
12075 default:
12076 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12077 return;
12078 }
12079 oappend_maybe_intel (ins, s);
12080 }
12081
12082 static void
12083 OP_I (instr_info *ins, int bytemode, int sizeflag)
12084 {
12085 bfd_signed_vma op;
12086 bfd_signed_vma mask = -1;
12087
12088 switch (bytemode)
12089 {
12090 case b_mode:
12091 FETCH_DATA (ins->info, ins->codep + 1);
12092 op = *ins->codep++;
12093 mask = 0xff;
12094 break;
12095 case v_mode:
12096 USED_REX (REX_W);
12097 if (ins->rex & REX_W)
12098 op = get32s (ins);
12099 else
12100 {
12101 if (sizeflag & DFLAG)
12102 {
12103 op = get32 (ins);
12104 mask = 0xffffffff;
12105 }
12106 else
12107 {
12108 op = get16 (ins);
12109 mask = 0xfffff;
12110 }
12111 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12112 }
12113 break;
12114 case d_mode:
12115 mask = 0xffffffff;
12116 op = get32 (ins);
12117 break;
12118 case w_mode:
12119 mask = 0xfffff;
12120 op = get16 (ins);
12121 break;
12122 case const_1_mode:
12123 if (ins->intel_syntax)
12124 oappend (ins, "1");
12125 return;
12126 default:
12127 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12128 return;
12129 }
12130
12131 op &= mask;
12132 ins->scratchbuf[0] = '$';
12133 print_operand_value (ins, ins->scratchbuf + 1, 1, op);
12134 oappend_maybe_intel (ins, ins->scratchbuf);
12135 ins->scratchbuf[0] = '\0';
12136 }
12137
12138 static void
12139 OP_I64 (instr_info *ins, int bytemode, int sizeflag)
12140 {
12141 if (bytemode != v_mode || ins->address_mode != mode_64bit
12142 || !(ins->rex & REX_W))
12143 {
12144 OP_I (ins, bytemode, sizeflag);
12145 return;
12146 }
12147
12148 USED_REX (REX_W);
12149
12150 ins->scratchbuf[0] = '$';
12151 print_operand_value (ins, ins->scratchbuf + 1, 1, get64 (ins));
12152 oappend_maybe_intel (ins, ins->scratchbuf);
12153 ins->scratchbuf[0] = '\0';
12154 }
12155
12156 static void
12157 OP_sI (instr_info *ins, int bytemode, int sizeflag)
12158 {
12159 bfd_signed_vma op;
12160
12161 switch (bytemode)
12162 {
12163 case b_mode:
12164 case b_T_mode:
12165 FETCH_DATA (ins->info, ins->codep + 1);
12166 op = *ins->codep++;
12167 if ((op & 0x80) != 0)
12168 op -= 0x100;
12169 if (bytemode == b_T_mode)
12170 {
12171 if (ins->address_mode != mode_64bit
12172 || !((sizeflag & DFLAG) || (ins->rex & REX_W)))
12173 {
12174 /* The operand-size prefix is overridden by a REX prefix. */
12175 if ((sizeflag & DFLAG) || (ins->rex & REX_W))
12176 op &= 0xffffffff;
12177 else
12178 op &= 0xffff;
12179 }
12180 }
12181 else
12182 {
12183 if (!(ins->rex & REX_W))
12184 {
12185 if (sizeflag & DFLAG)
12186 op &= 0xffffffff;
12187 else
12188 op &= 0xffff;
12189 }
12190 }
12191 break;
12192 case v_mode:
12193 /* The operand-size prefix is overridden by a REX prefix. */
12194 if ((sizeflag & DFLAG) || (ins->rex & REX_W))
12195 op = get32s (ins);
12196 else
12197 op = get16 (ins);
12198 break;
12199 default:
12200 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12201 return;
12202 }
12203
12204 ins->scratchbuf[0] = '$';
12205 print_operand_value (ins, ins->scratchbuf + 1, 1, op);
12206 oappend_maybe_intel (ins, ins->scratchbuf);
12207 }
12208
12209 static void
12210 OP_J (instr_info *ins, int bytemode, int sizeflag)
12211 {
12212 bfd_vma disp;
12213 bfd_vma mask = -1;
12214 bfd_vma segment = 0;
12215
12216 switch (bytemode)
12217 {
12218 case b_mode:
12219 FETCH_DATA (ins->info, ins->codep + 1);
12220 disp = *ins->codep++;
12221 if ((disp & 0x80) != 0)
12222 disp -= 0x100;
12223 break;
12224 case v_mode:
12225 case dqw_mode:
12226 if ((sizeflag & DFLAG)
12227 || (ins->address_mode == mode_64bit
12228 && ((ins->isa64 == intel64 && bytemode != dqw_mode)
12229 || (ins->rex & REX_W))))
12230 disp = get32s (ins);
12231 else
12232 {
12233 disp = get16 (ins);
12234 if ((disp & 0x8000) != 0)
12235 disp -= 0x10000;
12236 /* In 16bit mode, address is wrapped around at 64k within
12237 the same segment. Otherwise, a data16 prefix on a jump
12238 instruction means that the pc is masked to 16 bits after
12239 the displacement is added! */
12240 mask = 0xffff;
12241 if ((ins->prefixes & PREFIX_DATA) == 0)
12242 segment = ((ins->start_pc + (ins->codep - ins->start_codep))
12243 & ~((bfd_vma) 0xffff));
12244 }
12245 if (ins->address_mode != mode_64bit
12246 || (ins->isa64 != intel64 && !(ins->rex & REX_W)))
12247 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12248 break;
12249 default:
12250 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12251 return;
12252 }
12253 disp = ((ins->start_pc + (ins->codep - ins->start_codep) + disp) & mask)
12254 | segment;
12255 set_op (ins, disp, false);
12256 print_operand_value (ins, ins->scratchbuf, 1, disp);
12257 oappend (ins, ins->scratchbuf);
12258 }
12259
12260 static void
12261 OP_SEG (instr_info *ins, int bytemode, int sizeflag)
12262 {
12263 if (bytemode == w_mode)
12264 oappend_maybe_intel (ins, att_names_seg[ins->modrm.reg]);
12265 else
12266 OP_E (ins, ins->modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12267 }
12268
12269 static void
12270 OP_DIR (instr_info *ins, int dummy ATTRIBUTE_UNUSED, int sizeflag)
12271 {
12272 int seg, offset;
12273
12274 if (sizeflag & DFLAG)
12275 {
12276 offset = get32 (ins);
12277 seg = get16 (ins);
12278 }
12279 else
12280 {
12281 offset = get16 (ins);
12282 seg = get16 (ins);
12283 }
12284 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12285 if (ins->intel_syntax)
12286 sprintf (ins->scratchbuf, "0x%x:0x%x", seg, offset);
12287 else
12288 sprintf (ins->scratchbuf, "$0x%x,$0x%x", seg, offset);
12289 oappend (ins, ins->scratchbuf);
12290 }
12291
12292 static void
12293 OP_OFF (instr_info *ins, int bytemode, int sizeflag)
12294 {
12295 bfd_vma off;
12296
12297 if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12298 intel_operand_size (ins, bytemode, sizeflag);
12299 append_seg (ins);
12300
12301 if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
12302 off = get32 (ins);
12303 else
12304 off = get16 (ins);
12305
12306 if (ins->intel_syntax)
12307 {
12308 if (!ins->active_seg_prefix)
12309 {
12310 oappend_maybe_intel (ins, att_names_seg[ds_reg - es_reg]);
12311 oappend (ins, ":");
12312 }
12313 }
12314 print_operand_value (ins, ins->scratchbuf, 1, off);
12315 oappend (ins, ins->scratchbuf);
12316 }
12317
12318 static void
12319 OP_OFF64 (instr_info *ins, int bytemode, int sizeflag)
12320 {
12321 bfd_vma off;
12322
12323 if (ins->address_mode != mode_64bit
12324 || (ins->prefixes & PREFIX_ADDR))
12325 {
12326 OP_OFF (ins, bytemode, sizeflag);
12327 return;
12328 }
12329
12330 if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12331 intel_operand_size (ins, bytemode, sizeflag);
12332 append_seg (ins);
12333
12334 off = get64 (ins);
12335
12336 if (ins->intel_syntax)
12337 {
12338 if (!ins->active_seg_prefix)
12339 {
12340 oappend_maybe_intel (ins, att_names_seg[ds_reg - es_reg]);
12341 oappend (ins, ":");
12342 }
12343 }
12344 print_operand_value (ins, ins->scratchbuf, 1, off);
12345 oappend (ins, ins->scratchbuf);
12346 }
12347
12348 static void
12349 ptr_reg (instr_info *ins, int code, int sizeflag)
12350 {
12351 const char *s;
12352
12353 *ins->obufp++ = ins->open_char;
12354 ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
12355 if (ins->address_mode == mode_64bit)
12356 {
12357 if (!(sizeflag & AFLAG))
12358 s = att_names32[code - eAX_reg];
12359 else
12360 s = att_names64[code - eAX_reg];
12361 }
12362 else if (sizeflag & AFLAG)
12363 s = att_names32[code - eAX_reg];
12364 else
12365 s = att_names16[code - eAX_reg];
12366 oappend_maybe_intel (ins, s);
12367 *ins->obufp++ = ins->close_char;
12368 *ins->obufp = 0;
12369 }
12370
12371 static void
12372 OP_ESreg (instr_info *ins, int code, int sizeflag)
12373 {
12374 if (ins->intel_syntax)
12375 {
12376 switch (ins->codep[-1])
12377 {
12378 case 0x6d: /* insw/insl */
12379 intel_operand_size (ins, z_mode, sizeflag);
12380 break;
12381 case 0xa5: /* movsw/movsl/movsq */
12382 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12383 case 0xab: /* stosw/stosl */
12384 case 0xaf: /* scasw/scasl */
12385 intel_operand_size (ins, v_mode, sizeflag);
12386 break;
12387 default:
12388 intel_operand_size (ins, b_mode, sizeflag);
12389 }
12390 }
12391 oappend_maybe_intel (ins, "%es:");
12392 ptr_reg (ins, code, sizeflag);
12393 }
12394
12395 static void
12396 OP_DSreg (instr_info *ins, int code, int sizeflag)
12397 {
12398 if (ins->intel_syntax)
12399 {
12400 switch (ins->codep[-1])
12401 {
12402 case 0x6f: /* outsw/outsl */
12403 intel_operand_size (ins, z_mode, sizeflag);
12404 break;
12405 case 0xa5: /* movsw/movsl/movsq */
12406 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12407 case 0xad: /* lodsw/lodsl/lodsq */
12408 intel_operand_size (ins, v_mode, sizeflag);
12409 break;
12410 default:
12411 intel_operand_size (ins, b_mode, sizeflag);
12412 }
12413 }
12414 /* Set ins->active_seg_prefix to PREFIX_DS if it is unset so that the
12415 default segment register DS is printed. */
12416 if (!ins->active_seg_prefix)
12417 ins->active_seg_prefix = PREFIX_DS;
12418 append_seg (ins);
12419 ptr_reg (ins, code, sizeflag);
12420 }
12421
12422 static void
12423 OP_C (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12424 int sizeflag ATTRIBUTE_UNUSED)
12425 {
12426 int add;
12427 if (ins->rex & REX_R)
12428 {
12429 USED_REX (REX_R);
12430 add = 8;
12431 }
12432 else if (ins->address_mode != mode_64bit && (ins->prefixes & PREFIX_LOCK))
12433 {
12434 ins->all_prefixes[ins->last_lock_prefix] = 0;
12435 ins->used_prefixes |= PREFIX_LOCK;
12436 add = 8;
12437 }
12438 else
12439 add = 0;
12440 sprintf (ins->scratchbuf, "%%cr%d", ins->modrm.reg + add);
12441 oappend_maybe_intel (ins, ins->scratchbuf);
12442 }
12443
12444 static void
12445 OP_D (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12446 int sizeflag ATTRIBUTE_UNUSED)
12447 {
12448 int add;
12449 USED_REX (REX_R);
12450 if (ins->rex & REX_R)
12451 add = 8;
12452 else
12453 add = 0;
12454 if (ins->intel_syntax)
12455 sprintf (ins->scratchbuf, "dr%d", ins->modrm.reg + add);
12456 else
12457 sprintf (ins->scratchbuf, "%%db%d", ins->modrm.reg + add);
12458 oappend (ins, ins->scratchbuf);
12459 }
12460
12461 static void
12462 OP_T (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12463 int sizeflag ATTRIBUTE_UNUSED)
12464 {
12465 sprintf (ins->scratchbuf, "%%tr%d", ins->modrm.reg);
12466 oappend_maybe_intel (ins, ins->scratchbuf);
12467 }
12468
12469 static void
12470 OP_MMX (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12471 int sizeflag ATTRIBUTE_UNUSED)
12472 {
12473 int reg = ins->modrm.reg;
12474 const char *const *names;
12475
12476 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12477 if (ins->prefixes & PREFIX_DATA)
12478 {
12479 names = att_names_xmm;
12480 USED_REX (REX_R);
12481 if (ins->rex & REX_R)
12482 reg += 8;
12483 }
12484 else
12485 names = att_names_mm;
12486 oappend_maybe_intel (ins, names[reg]);
12487 }
12488
12489 static void
12490 print_vector_reg (instr_info *ins, unsigned int reg, int bytemode)
12491 {
12492 const char *const *names;
12493
12494 if (bytemode == xmmq_mode
12495 || bytemode == evex_half_bcst_xmmqh_mode
12496 || bytemode == evex_half_bcst_xmmq_mode)
12497 {
12498 switch (ins->vex.length)
12499 {
12500 case 128:
12501 case 256:
12502 names = att_names_xmm;
12503 break;
12504 case 512:
12505 names = att_names_ymm;
12506 ins->evex_used |= EVEX_len_used;
12507 break;
12508 default:
12509 abort ();
12510 }
12511 }
12512 else if (bytemode == ymm_mode)
12513 names = att_names_ymm;
12514 else if (bytemode == tmm_mode)
12515 {
12516 if (reg >= 8)
12517 {
12518 oappend (ins, "(bad)");
12519 return;
12520 }
12521 names = att_names_tmm;
12522 }
12523 else if (ins->need_vex
12524 && bytemode != xmm_mode
12525 && bytemode != scalar_mode
12526 && bytemode != xmmdw_mode
12527 && bytemode != xmmqd_mode
12528 && bytemode != evex_half_bcst_xmmqdh_mode
12529 && bytemode != w_swap_mode
12530 && bytemode != b_mode
12531 && bytemode != w_mode
12532 && bytemode != d_mode
12533 && bytemode != q_mode)
12534 {
12535 ins->evex_used |= EVEX_len_used;
12536 switch (ins->vex.length)
12537 {
12538 case 128:
12539 names = att_names_xmm;
12540 break;
12541 case 256:
12542 if (ins->vex.w
12543 || bytemode != vex_vsib_q_w_dq_mode)
12544 names = att_names_ymm;
12545 else
12546 names = att_names_xmm;
12547 break;
12548 case 512:
12549 if (ins->vex.w
12550 || bytemode != vex_vsib_q_w_dq_mode)
12551 names = att_names_zmm;
12552 else
12553 names = att_names_ymm;
12554 break;
12555 default:
12556 abort ();
12557 }
12558 }
12559 else
12560 names = att_names_xmm;
12561 oappend_maybe_intel (ins, names[reg]);
12562 }
12563
12564 static void
12565 OP_XMM (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12566 {
12567 unsigned int reg = ins->modrm.reg;
12568
12569 USED_REX (REX_R);
12570 if (ins->rex & REX_R)
12571 reg += 8;
12572 if (ins->vex.evex)
12573 {
12574 if (!ins->vex.r)
12575 reg += 16;
12576 }
12577
12578 if (bytemode == tmm_mode)
12579 ins->modrm.reg = reg;
12580 else if (bytemode == scalar_mode)
12581 ins->vex.no_broadcast = true;
12582
12583 print_vector_reg (ins, reg, bytemode);
12584 }
12585
12586 static void
12587 OP_EM (instr_info *ins, int bytemode, int sizeflag)
12588 {
12589 int reg;
12590 const char *const *names;
12591
12592 if (ins->modrm.mod != 3)
12593 {
12594 if (ins->intel_syntax
12595 && (bytemode == v_mode || bytemode == v_swap_mode))
12596 {
12597 bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
12598 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12599 }
12600 OP_E (ins, bytemode, sizeflag);
12601 return;
12602 }
12603
12604 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12605 swap_operand (ins);
12606
12607 /* Skip mod/rm byte. */
12608 MODRM_CHECK;
12609 ins->codep++;
12610 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12611 reg = ins->modrm.rm;
12612 if (ins->prefixes & PREFIX_DATA)
12613 {
12614 names = att_names_xmm;
12615 USED_REX (REX_B);
12616 if (ins->rex & REX_B)
12617 reg += 8;
12618 }
12619 else
12620 names = att_names_mm;
12621 oappend_maybe_intel (ins, names[reg]);
12622 }
12623
12624 /* cvt* are the only instructions in sse2 which have
12625 both SSE and MMX operands and also have 0x66 prefix
12626 in their opcode. 0x66 was originally used to differentiate
12627 between SSE and MMX instruction(operands). So we have to handle the
12628 cvt* separately using OP_EMC and OP_MXC */
12629 static void
12630 OP_EMC (instr_info *ins, int bytemode, int sizeflag)
12631 {
12632 if (ins->modrm.mod != 3)
12633 {
12634 if (ins->intel_syntax && bytemode == v_mode)
12635 {
12636 bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
12637 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12638 }
12639 OP_E (ins, bytemode, sizeflag);
12640 return;
12641 }
12642
12643 /* Skip mod/rm byte. */
12644 MODRM_CHECK;
12645 ins->codep++;
12646 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12647 oappend_maybe_intel (ins, att_names_mm[ins->modrm.rm]);
12648 }
12649
12650 static void
12651 OP_MXC (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12652 int sizeflag ATTRIBUTE_UNUSED)
12653 {
12654 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12655 oappend_maybe_intel (ins, att_names_mm[ins->modrm.reg]);
12656 }
12657
12658 static void
12659 OP_EX (instr_info *ins, int bytemode, int sizeflag)
12660 {
12661 int reg;
12662
12663 /* Skip mod/rm byte. */
12664 MODRM_CHECK;
12665 ins->codep++;
12666
12667 if (bytemode == dq_mode)
12668 bytemode = ins->vex.w ? q_mode : d_mode;
12669
12670 if (ins->modrm.mod != 3)
12671 {
12672 OP_E_memory (ins, bytemode, sizeflag);
12673 return;
12674 }
12675
12676 reg = ins->modrm.rm;
12677 USED_REX (REX_B);
12678 if (ins->rex & REX_B)
12679 reg += 8;
12680 if (ins->vex.evex)
12681 {
12682 USED_REX (REX_X);
12683 if ((ins->rex & REX_X))
12684 reg += 16;
12685 }
12686
12687 if ((sizeflag & SUFFIX_ALWAYS)
12688 && (bytemode == x_swap_mode
12689 || bytemode == w_swap_mode
12690 || bytemode == d_swap_mode
12691 || bytemode == q_swap_mode))
12692 swap_operand (ins);
12693
12694 if (bytemode == tmm_mode)
12695 ins->modrm.rm = reg;
12696
12697 print_vector_reg (ins, reg, bytemode);
12698 }
12699
12700 static void
12701 OP_MS (instr_info *ins, int bytemode, int sizeflag)
12702 {
12703 if (ins->modrm.mod == 3)
12704 OP_EM (ins, bytemode, sizeflag);
12705 else
12706 BadOp (ins);
12707 }
12708
12709 static void
12710 OP_XS (instr_info *ins, int bytemode, int sizeflag)
12711 {
12712 if (ins->modrm.mod == 3)
12713 OP_EX (ins, bytemode, sizeflag);
12714 else
12715 BadOp (ins);
12716 }
12717
12718 static void
12719 OP_M (instr_info *ins, int bytemode, int sizeflag)
12720 {
12721 if (ins->modrm.mod == 3)
12722 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12723 BadOp (ins);
12724 else
12725 OP_E (ins, bytemode, sizeflag);
12726 }
12727
12728 static void
12729 OP_0f07 (instr_info *ins, int bytemode, int sizeflag)
12730 {
12731 if (ins->modrm.mod != 3 || ins->modrm.rm != 0)
12732 BadOp (ins);
12733 else
12734 OP_E (ins, bytemode, sizeflag);
12735 }
12736
12737 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
12738 32bit mode and "xchg %rax,%rax" in 64bit mode. */
12739
12740 static void
12741 NOP_Fixup (instr_info *ins, int opnd, int sizeflag)
12742 {
12743 if ((ins->prefixes & PREFIX_DATA) == 0 && (ins->rex & REX_B) == 0)
12744 strcpy (ins->obuf, "nop");
12745 else if (opnd == 0)
12746 OP_REG (ins, eAX_reg, sizeflag);
12747 else
12748 OP_IMREG (ins, eAX_reg, sizeflag);
12749 }
12750
12751 static const char *const Suffix3DNow[] = {
12752 /* 00 */ NULL, NULL, NULL, NULL,
12753 /* 04 */ NULL, NULL, NULL, NULL,
12754 /* 08 */ NULL, NULL, NULL, NULL,
12755 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
12756 /* 10 */ NULL, NULL, NULL, NULL,
12757 /* 14 */ NULL, NULL, NULL, NULL,
12758 /* 18 */ NULL, NULL, NULL, NULL,
12759 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
12760 /* 20 */ NULL, NULL, NULL, NULL,
12761 /* 24 */ NULL, NULL, NULL, NULL,
12762 /* 28 */ NULL, NULL, NULL, NULL,
12763 /* 2C */ NULL, NULL, NULL, NULL,
12764 /* 30 */ NULL, NULL, NULL, NULL,
12765 /* 34 */ NULL, NULL, NULL, NULL,
12766 /* 38 */ NULL, NULL, NULL, NULL,
12767 /* 3C */ NULL, NULL, NULL, NULL,
12768 /* 40 */ NULL, NULL, NULL, NULL,
12769 /* 44 */ NULL, NULL, NULL, NULL,
12770 /* 48 */ NULL, NULL, NULL, NULL,
12771 /* 4C */ NULL, NULL, NULL, NULL,
12772 /* 50 */ NULL, NULL, NULL, NULL,
12773 /* 54 */ NULL, NULL, NULL, NULL,
12774 /* 58 */ NULL, NULL, NULL, NULL,
12775 /* 5C */ NULL, NULL, NULL, NULL,
12776 /* 60 */ NULL, NULL, NULL, NULL,
12777 /* 64 */ NULL, NULL, NULL, NULL,
12778 /* 68 */ NULL, NULL, NULL, NULL,
12779 /* 6C */ NULL, NULL, NULL, NULL,
12780 /* 70 */ NULL, NULL, NULL, NULL,
12781 /* 74 */ NULL, NULL, NULL, NULL,
12782 /* 78 */ NULL, NULL, NULL, NULL,
12783 /* 7C */ NULL, NULL, NULL, NULL,
12784 /* 80 */ NULL, NULL, NULL, NULL,
12785 /* 84 */ NULL, NULL, NULL, NULL,
12786 /* 88 */ NULL, NULL, "pfnacc", NULL,
12787 /* 8C */ NULL, NULL, "pfpnacc", NULL,
12788 /* 90 */ "pfcmpge", NULL, NULL, NULL,
12789 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
12790 /* 98 */ NULL, NULL, "pfsub", NULL,
12791 /* 9C */ NULL, NULL, "pfadd", NULL,
12792 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
12793 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
12794 /* A8 */ NULL, NULL, "pfsubr", NULL,
12795 /* AC */ NULL, NULL, "pfacc", NULL,
12796 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
12797 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
12798 /* B8 */ NULL, NULL, NULL, "pswapd",
12799 /* BC */ NULL, NULL, NULL, "pavgusb",
12800 /* C0 */ NULL, NULL, NULL, NULL,
12801 /* C4 */ NULL, NULL, NULL, NULL,
12802 /* C8 */ NULL, NULL, NULL, NULL,
12803 /* CC */ NULL, NULL, NULL, NULL,
12804 /* D0 */ NULL, NULL, NULL, NULL,
12805 /* D4 */ NULL, NULL, NULL, NULL,
12806 /* D8 */ NULL, NULL, NULL, NULL,
12807 /* DC */ NULL, NULL, NULL, NULL,
12808 /* E0 */ NULL, NULL, NULL, NULL,
12809 /* E4 */ NULL, NULL, NULL, NULL,
12810 /* E8 */ NULL, NULL, NULL, NULL,
12811 /* EC */ NULL, NULL, NULL, NULL,
12812 /* F0 */ NULL, NULL, NULL, NULL,
12813 /* F4 */ NULL, NULL, NULL, NULL,
12814 /* F8 */ NULL, NULL, NULL, NULL,
12815 /* FC */ NULL, NULL, NULL, NULL,
12816 };
12817
12818 static void
12819 OP_3DNowSuffix (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12820 int sizeflag ATTRIBUTE_UNUSED)
12821 {
12822 const char *mnemonic;
12823
12824 FETCH_DATA (ins->info, ins->codep + 1);
12825 /* AMD 3DNow! instructions are specified by an opcode suffix in the
12826 place where an 8-bit immediate would normally go. ie. the last
12827 byte of the instruction. */
12828 ins->obufp = ins->mnemonicendp;
12829 mnemonic = Suffix3DNow[*ins->codep++ & 0xff];
12830 if (mnemonic)
12831 oappend (ins, mnemonic);
12832 else
12833 {
12834 /* Since a variable sized ins->modrm/ins->sib chunk is between the start
12835 of the opcode (0x0f0f) and the opcode suffix, we need to do
12836 all the ins->modrm processing first, and don't know until now that
12837 we have a bad opcode. This necessitates some cleaning up. */
12838 ins->op_out[0][0] = '\0';
12839 ins->op_out[1][0] = '\0';
12840 BadOp (ins);
12841 }
12842 ins->mnemonicendp = ins->obufp;
12843 }
12844
12845 static const struct op simd_cmp_op[] =
12846 {
12847 { STRING_COMMA_LEN ("eq") },
12848 { STRING_COMMA_LEN ("lt") },
12849 { STRING_COMMA_LEN ("le") },
12850 { STRING_COMMA_LEN ("unord") },
12851 { STRING_COMMA_LEN ("neq") },
12852 { STRING_COMMA_LEN ("nlt") },
12853 { STRING_COMMA_LEN ("nle") },
12854 { STRING_COMMA_LEN ("ord") }
12855 };
12856
12857 static const struct op vex_cmp_op[] =
12858 {
12859 { STRING_COMMA_LEN ("eq_uq") },
12860 { STRING_COMMA_LEN ("nge") },
12861 { STRING_COMMA_LEN ("ngt") },
12862 { STRING_COMMA_LEN ("false") },
12863 { STRING_COMMA_LEN ("neq_oq") },
12864 { STRING_COMMA_LEN ("ge") },
12865 { STRING_COMMA_LEN ("gt") },
12866 { STRING_COMMA_LEN ("true") },
12867 { STRING_COMMA_LEN ("eq_os") },
12868 { STRING_COMMA_LEN ("lt_oq") },
12869 { STRING_COMMA_LEN ("le_oq") },
12870 { STRING_COMMA_LEN ("unord_s") },
12871 { STRING_COMMA_LEN ("neq_us") },
12872 { STRING_COMMA_LEN ("nlt_uq") },
12873 { STRING_COMMA_LEN ("nle_uq") },
12874 { STRING_COMMA_LEN ("ord_s") },
12875 { STRING_COMMA_LEN ("eq_us") },
12876 { STRING_COMMA_LEN ("nge_uq") },
12877 { STRING_COMMA_LEN ("ngt_uq") },
12878 { STRING_COMMA_LEN ("false_os") },
12879 { STRING_COMMA_LEN ("neq_os") },
12880 { STRING_COMMA_LEN ("ge_oq") },
12881 { STRING_COMMA_LEN ("gt_oq") },
12882 { STRING_COMMA_LEN ("true_us") },
12883 };
12884
12885 static void
12886 CMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12887 int sizeflag ATTRIBUTE_UNUSED)
12888 {
12889 unsigned int cmp_type;
12890
12891 FETCH_DATA (ins->info, ins->codep + 1);
12892 cmp_type = *ins->codep++ & 0xff;
12893 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
12894 {
12895 char suffix[3];
12896 char *p = ins->mnemonicendp - 2;
12897 suffix[0] = p[0];
12898 suffix[1] = p[1];
12899 suffix[2] = '\0';
12900 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
12901 ins->mnemonicendp += simd_cmp_op[cmp_type].len;
12902 }
12903 else if (ins->need_vex
12904 && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
12905 {
12906 char suffix[3];
12907 char *p = ins->mnemonicendp - 2;
12908 suffix[0] = p[0];
12909 suffix[1] = p[1];
12910 suffix[2] = '\0';
12911 cmp_type -= ARRAY_SIZE (simd_cmp_op);
12912 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
12913 ins->mnemonicendp += vex_cmp_op[cmp_type].len;
12914 }
12915 else
12916 {
12917 /* We have a reserved extension byte. Output it directly. */
12918 ins->scratchbuf[0] = '$';
12919 print_operand_value (ins, ins->scratchbuf + 1, 1, cmp_type);
12920 oappend_maybe_intel (ins, ins->scratchbuf);
12921 ins->scratchbuf[0] = '\0';
12922 }
12923 }
12924
12925 static void
12926 OP_Mwait (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12927 {
12928 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
12929 if (!ins->intel_syntax)
12930 {
12931 strcpy (ins->op_out[0], att_names32[0] + ins->intel_syntax);
12932 strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
12933 if (bytemode == eBX_reg)
12934 strcpy (ins->op_out[2], att_names32[3] + ins->intel_syntax);
12935 ins->two_source_ops = true;
12936 }
12937 /* Skip mod/rm byte. */
12938 MODRM_CHECK;
12939 ins->codep++;
12940 }
12941
12942 static void
12943 OP_Monitor (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12944 int sizeflag ATTRIBUTE_UNUSED)
12945 {
12946 /* monitor %{e,r,}ax,%ecx,%edx" */
12947 if (!ins->intel_syntax)
12948 {
12949 const char *const *names = (ins->address_mode == mode_64bit
12950 ? att_names64 : att_names32);
12951
12952 if (ins->prefixes & PREFIX_ADDR)
12953 {
12954 /* Remove "addr16/addr32". */
12955 ins->all_prefixes[ins->last_addr_prefix] = 0;
12956 names = (ins->address_mode != mode_32bit
12957 ? att_names32 : att_names16);
12958 ins->used_prefixes |= PREFIX_ADDR;
12959 }
12960 else if (ins->address_mode == mode_16bit)
12961 names = att_names16;
12962 strcpy (ins->op_out[0], names[0] + ins->intel_syntax);
12963 strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
12964 strcpy (ins->op_out[2], att_names32[2] + ins->intel_syntax);
12965 ins->two_source_ops = true;
12966 }
12967 /* Skip mod/rm byte. */
12968 MODRM_CHECK;
12969 ins->codep++;
12970 }
12971
12972 static void
12973 BadOp (instr_info *ins)
12974 {
12975 /* Throw away prefixes and 1st. opcode byte. */
12976 ins->codep = ins->insn_codep + 1;
12977 oappend (ins, "(bad)");
12978 }
12979
12980 static void
12981 REP_Fixup (instr_info *ins, int bytemode, int sizeflag)
12982 {
12983 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
12984 lods and stos. */
12985 if (ins->prefixes & PREFIX_REPZ)
12986 ins->all_prefixes[ins->last_repz_prefix] = REP_PREFIX;
12987
12988 switch (bytemode)
12989 {
12990 case al_reg:
12991 case eAX_reg:
12992 case indir_dx_reg:
12993 OP_IMREG (ins, bytemode, sizeflag);
12994 break;
12995 case eDI_reg:
12996 OP_ESreg (ins, bytemode, sizeflag);
12997 break;
12998 case eSI_reg:
12999 OP_DSreg (ins, bytemode, sizeflag);
13000 break;
13001 default:
13002 abort ();
13003 break;
13004 }
13005 }
13006
13007 static void
13008 SEP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13009 int sizeflag ATTRIBUTE_UNUSED)
13010 {
13011 if (ins->isa64 != amd64)
13012 return;
13013
13014 ins->obufp = ins->obuf;
13015 BadOp (ins);
13016 ins->mnemonicendp = ins->obufp;
13017 ++ins->codep;
13018 }
13019
13020 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13021 "bnd". */
13022
13023 static void
13024 BND_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13025 int sizeflag ATTRIBUTE_UNUSED)
13026 {
13027 if (ins->prefixes & PREFIX_REPNZ)
13028 ins->all_prefixes[ins->last_repnz_prefix] = BND_PREFIX;
13029 }
13030
13031 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13032 "notrack". */
13033
13034 static void
13035 NOTRACK_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13036 int sizeflag ATTRIBUTE_UNUSED)
13037 {
13038 /* Since active_seg_prefix is not set in 64-bit mode, check whether
13039 we've seen a PREFIX_DS. */
13040 if ((ins->prefixes & PREFIX_DS) != 0
13041 && (ins->address_mode != mode_64bit || ins->last_data_prefix < 0))
13042 {
13043 /* NOTRACK prefix is only valid on indirect branch instructions.
13044 NB: DATA prefix is unsupported for Intel64. */
13045 ins->active_seg_prefix = 0;
13046 ins->all_prefixes[ins->last_seg_prefix] = NOTRACK_PREFIX;
13047 }
13048 }
13049
13050 /* Similar to OP_E. But the 0xf2/0xf3 ins->prefixes should be displayed as
13051 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13052 */
13053
13054 static void
13055 HLE_Fixup1 (instr_info *ins, int bytemode, int sizeflag)
13056 {
13057 if (ins->modrm.mod != 3
13058 && (ins->prefixes & PREFIX_LOCK) != 0)
13059 {
13060 if (ins->prefixes & PREFIX_REPZ)
13061 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13062 if (ins->prefixes & PREFIX_REPNZ)
13063 ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13064 }
13065
13066 OP_E (ins, bytemode, sizeflag);
13067 }
13068
13069 /* Similar to OP_E. But the 0xf2/0xf3 ins->prefixes should be displayed as
13070 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
13071 */
13072
13073 static void
13074 HLE_Fixup2 (instr_info *ins, int bytemode, int sizeflag)
13075 {
13076 if (ins->modrm.mod != 3)
13077 {
13078 if (ins->prefixes & PREFIX_REPZ)
13079 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13080 if (ins->prefixes & PREFIX_REPNZ)
13081 ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13082 }
13083
13084 OP_E (ins, bytemode, sizeflag);
13085 }
13086
13087 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
13088 "xrelease" for memory operand. No check for LOCK prefix. */
13089
13090 static void
13091 HLE_Fixup3 (instr_info *ins, int bytemode, int sizeflag)
13092 {
13093 if (ins->modrm.mod != 3
13094 && ins->last_repz_prefix > ins->last_repnz_prefix
13095 && (ins->prefixes & PREFIX_REPZ) != 0)
13096 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13097
13098 OP_E (ins, bytemode, sizeflag);
13099 }
13100
13101 static void
13102 CMPXCHG8B_Fixup (instr_info *ins, int bytemode, int sizeflag)
13103 {
13104 USED_REX (REX_W);
13105 if (ins->rex & REX_W)
13106 {
13107 /* Change cmpxchg8b to cmpxchg16b. */
13108 char *p = ins->mnemonicendp - 2;
13109 ins->mnemonicendp = stpcpy (p, "16b");
13110 bytemode = o_mode;
13111 }
13112 else if ((ins->prefixes & PREFIX_LOCK) != 0)
13113 {
13114 if (ins->prefixes & PREFIX_REPZ)
13115 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13116 if (ins->prefixes & PREFIX_REPNZ)
13117 ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13118 }
13119
13120 OP_M (ins, bytemode, sizeflag);
13121 }
13122
13123 static void
13124 XMM_Fixup (instr_info *ins, int reg, int sizeflag ATTRIBUTE_UNUSED)
13125 {
13126 const char *const *names = att_names_xmm;
13127
13128 if (ins->need_vex)
13129 {
13130 switch (ins->vex.length)
13131 {
13132 case 128:
13133 break;
13134 case 256:
13135 names = att_names_ymm;
13136 break;
13137 default:
13138 abort ();
13139 }
13140 }
13141 oappend_maybe_intel (ins, names[reg]);
13142 }
13143
13144 static void
13145 FXSAVE_Fixup (instr_info *ins, int bytemode, int sizeflag)
13146 {
13147 /* Add proper suffix to "fxsave" and "fxrstor". */
13148 USED_REX (REX_W);
13149 if (ins->rex & REX_W)
13150 {
13151 char *p = ins->mnemonicendp;
13152 *p++ = '6';
13153 *p++ = '4';
13154 *p = '\0';
13155 ins->mnemonicendp = p;
13156 }
13157 OP_M (ins, bytemode, sizeflag);
13158 }
13159
13160 /* Display the destination register operand for instructions with
13161 VEX. */
13162
13163 static void
13164 OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13165 {
13166 int reg, modrm_reg, sib_index = -1;
13167 const char *const *names;
13168
13169 if (!ins->need_vex)
13170 abort ();
13171
13172 reg = ins->vex.register_specifier;
13173 ins->vex.register_specifier = 0;
13174 if (ins->address_mode != mode_64bit)
13175 {
13176 if (ins->vex.evex && !ins->vex.v)
13177 {
13178 oappend (ins, "(bad)");
13179 return;
13180 }
13181
13182 reg &= 7;
13183 }
13184 else if (ins->vex.evex && !ins->vex.v)
13185 reg += 16;
13186
13187 switch (bytemode)
13188 {
13189 case scalar_mode:
13190 oappend_maybe_intel (ins, att_names_xmm[reg]);
13191 return;
13192
13193 case vex_vsib_d_w_dq_mode:
13194 case vex_vsib_q_w_dq_mode:
13195 /* This must be the 3rd operand. */
13196 if (ins->obufp != ins->op_out[2])
13197 abort ();
13198 if (ins->vex.length == 128
13199 || (bytemode != vex_vsib_d_w_dq_mode
13200 && !ins->vex.w))
13201 oappend_maybe_intel (ins, att_names_xmm[reg]);
13202 else
13203 oappend_maybe_intel (ins, att_names_ymm[reg]);
13204
13205 /* All 3 XMM/YMM registers must be distinct. */
13206 modrm_reg = ins->modrm.reg;
13207 if (ins->rex & REX_R)
13208 modrm_reg += 8;
13209
13210 if (ins->has_sib && ins->modrm.rm == 4)
13211 {
13212 sib_index = ins->sib.index;
13213 if (ins->rex & REX_X)
13214 sib_index += 8;
13215 }
13216
13217 if (reg == modrm_reg || reg == sib_index)
13218 strcpy (ins->obufp, "/(bad)");
13219 if (modrm_reg == sib_index || modrm_reg == reg)
13220 strcat (ins->op_out[0], "/(bad)");
13221 if (sib_index == modrm_reg || sib_index == reg)
13222 strcat (ins->op_out[1], "/(bad)");
13223
13224 return;
13225
13226 case tmm_mode:
13227 /* All 3 TMM registers must be distinct. */
13228 if (reg >= 8)
13229 oappend (ins, "(bad)");
13230 else
13231 {
13232 /* This must be the 3rd operand. */
13233 if (ins->obufp != ins->op_out[2])
13234 abort ();
13235 oappend_maybe_intel (ins, att_names_tmm[reg]);
13236 if (reg == ins->modrm.reg || reg == ins->modrm.rm)
13237 strcpy (ins->obufp, "/(bad)");
13238 }
13239
13240 if (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg
13241 || ins->modrm.rm == reg)
13242 {
13243 if (ins->modrm.reg <= 8
13244 && (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg))
13245 strcat (ins->op_out[0], "/(bad)");
13246 if (ins->modrm.rm <= 8
13247 && (ins->modrm.rm == ins->modrm.reg || ins->modrm.rm == reg))
13248 strcat (ins->op_out[1], "/(bad)");
13249 }
13250
13251 return;
13252 }
13253
13254 switch (ins->vex.length)
13255 {
13256 case 128:
13257 switch (bytemode)
13258 {
13259 case x_mode:
13260 names = att_names_xmm;
13261 ins->evex_used |= EVEX_len_used;
13262 break;
13263 case dq_mode:
13264 if (ins->rex & REX_W)
13265 names = att_names64;
13266 else
13267 names = att_names32;
13268 break;
13269 case mask_bd_mode:
13270 case mask_mode:
13271 if (reg > 0x7)
13272 {
13273 oappend (ins, "(bad)");
13274 return;
13275 }
13276 names = att_names_mask;
13277 break;
13278 default:
13279 abort ();
13280 return;
13281 }
13282 break;
13283 case 256:
13284 switch (bytemode)
13285 {
13286 case x_mode:
13287 names = att_names_ymm;
13288 ins->evex_used |= EVEX_len_used;
13289 break;
13290 case mask_bd_mode:
13291 case mask_mode:
13292 if (reg > 0x7)
13293 {
13294 oappend (ins, "(bad)");
13295 return;
13296 }
13297 names = att_names_mask;
13298 break;
13299 default:
13300 /* See PR binutils/20893 for a reproducer. */
13301 oappend (ins, "(bad)");
13302 return;
13303 }
13304 break;
13305 case 512:
13306 names = att_names_zmm;
13307 ins->evex_used |= EVEX_len_used;
13308 break;
13309 default:
13310 abort ();
13311 break;
13312 }
13313 oappend_maybe_intel (ins, names[reg]);
13314 }
13315
13316 static void
13317 OP_VexR (instr_info *ins, int bytemode, int sizeflag)
13318 {
13319 if (ins->modrm.mod == 3)
13320 OP_VEX (ins, bytemode, sizeflag);
13321 }
13322
13323 static void
13324 OP_VexW (instr_info *ins, int bytemode, int sizeflag)
13325 {
13326 OP_VEX (ins, bytemode, sizeflag);
13327
13328 if (ins->vex.w)
13329 {
13330 /* Swap 2nd and 3rd operands. */
13331 strcpy (ins->scratchbuf, ins->op_out[2]);
13332 strcpy (ins->op_out[2], ins->op_out[1]);
13333 strcpy (ins->op_out[1], ins->scratchbuf);
13334 }
13335 }
13336
13337 static void
13338 OP_REG_VexI4 (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13339 {
13340 int reg;
13341 const char *const *names = att_names_xmm;
13342
13343 FETCH_DATA (ins->info, ins->codep + 1);
13344 reg = *ins->codep++;
13345
13346 if (bytemode != x_mode && bytemode != scalar_mode)
13347 abort ();
13348
13349 reg >>= 4;
13350 if (ins->address_mode != mode_64bit)
13351 reg &= 7;
13352
13353 if (bytemode == x_mode && ins->vex.length == 256)
13354 names = att_names_ymm;
13355
13356 oappend_maybe_intel (ins, names[reg]);
13357
13358 if (ins->vex.w)
13359 {
13360 /* Swap 3rd and 4th operands. */
13361 strcpy (ins->scratchbuf, ins->op_out[3]);
13362 strcpy (ins->op_out[3], ins->op_out[2]);
13363 strcpy (ins->op_out[2], ins->scratchbuf);
13364 }
13365 }
13366
13367 static void
13368 OP_VexI4 (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13369 int sizeflag ATTRIBUTE_UNUSED)
13370 {
13371 ins->scratchbuf[0] = '$';
13372 print_operand_value (ins, ins->scratchbuf + 1, 1, ins->codep[-1] & 0xf);
13373 oappend_maybe_intel (ins, ins->scratchbuf);
13374 }
13375
13376 static void
13377 VPCMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13378 int sizeflag ATTRIBUTE_UNUSED)
13379 {
13380 unsigned int cmp_type;
13381
13382 if (!ins->vex.evex)
13383 abort ();
13384
13385 FETCH_DATA (ins->info, ins->codep + 1);
13386 cmp_type = *ins->codep++ & 0xff;
13387 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13388 If it's the case, print suffix, otherwise - print the immediate. */
13389 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13390 && cmp_type != 3
13391 && cmp_type != 7)
13392 {
13393 char suffix[3];
13394 char *p = ins->mnemonicendp - 2;
13395
13396 /* vpcmp* can have both one- and two-lettered suffix. */
13397 if (p[0] == 'p')
13398 {
13399 p++;
13400 suffix[0] = p[0];
13401 suffix[1] = '\0';
13402 }
13403 else
13404 {
13405 suffix[0] = p[0];
13406 suffix[1] = p[1];
13407 suffix[2] = '\0';
13408 }
13409
13410 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13411 ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13412 }
13413 else
13414 {
13415 /* We have a reserved extension byte. Output it directly. */
13416 ins->scratchbuf[0] = '$';
13417 print_operand_value (ins, ins->scratchbuf + 1, 1, cmp_type);
13418 oappend_maybe_intel (ins, ins->scratchbuf);
13419 ins->scratchbuf[0] = '\0';
13420 }
13421 }
13422
13423 static const struct op xop_cmp_op[] =
13424 {
13425 { STRING_COMMA_LEN ("lt") },
13426 { STRING_COMMA_LEN ("le") },
13427 { STRING_COMMA_LEN ("gt") },
13428 { STRING_COMMA_LEN ("ge") },
13429 { STRING_COMMA_LEN ("eq") },
13430 { STRING_COMMA_LEN ("neq") },
13431 { STRING_COMMA_LEN ("false") },
13432 { STRING_COMMA_LEN ("true") }
13433 };
13434
13435 static void
13436 VPCOM_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13437 int sizeflag ATTRIBUTE_UNUSED)
13438 {
13439 unsigned int cmp_type;
13440
13441 FETCH_DATA (ins->info, ins->codep + 1);
13442 cmp_type = *ins->codep++ & 0xff;
13443 if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13444 {
13445 char suffix[3];
13446 char *p = ins->mnemonicendp - 2;
13447
13448 /* vpcom* can have both one- and two-lettered suffix. */
13449 if (p[0] == 'm')
13450 {
13451 p++;
13452 suffix[0] = p[0];
13453 suffix[1] = '\0';
13454 }
13455 else
13456 {
13457 suffix[0] = p[0];
13458 suffix[1] = p[1];
13459 suffix[2] = '\0';
13460 }
13461
13462 sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13463 ins->mnemonicendp += xop_cmp_op[cmp_type].len;
13464 }
13465 else
13466 {
13467 /* We have a reserved extension byte. Output it directly. */
13468 ins->scratchbuf[0] = '$';
13469 print_operand_value (ins, ins->scratchbuf + 1, 1, cmp_type);
13470 oappend_maybe_intel (ins, ins->scratchbuf);
13471 ins->scratchbuf[0] = '\0';
13472 }
13473 }
13474
13475 static const struct op pclmul_op[] =
13476 {
13477 { STRING_COMMA_LEN ("lql") },
13478 { STRING_COMMA_LEN ("hql") },
13479 { STRING_COMMA_LEN ("lqh") },
13480 { STRING_COMMA_LEN ("hqh") }
13481 };
13482
13483 static void
13484 PCLMUL_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13485 int sizeflag ATTRIBUTE_UNUSED)
13486 {
13487 unsigned int pclmul_type;
13488
13489 FETCH_DATA (ins->info, ins->codep + 1);
13490 pclmul_type = *ins->codep++ & 0xff;
13491 switch (pclmul_type)
13492 {
13493 case 0x10:
13494 pclmul_type = 2;
13495 break;
13496 case 0x11:
13497 pclmul_type = 3;
13498 break;
13499 default:
13500 break;
13501 }
13502 if (pclmul_type < ARRAY_SIZE (pclmul_op))
13503 {
13504 char suffix[4];
13505 char *p = ins->mnemonicendp - 3;
13506 suffix[0] = p[0];
13507 suffix[1] = p[1];
13508 suffix[2] = p[2];
13509 suffix[3] = '\0';
13510 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13511 ins->mnemonicendp += pclmul_op[pclmul_type].len;
13512 }
13513 else
13514 {
13515 /* We have a reserved extension byte. Output it directly. */
13516 ins->scratchbuf[0] = '$';
13517 print_operand_value (ins, ins->scratchbuf + 1, 1, pclmul_type);
13518 oappend_maybe_intel (ins, ins->scratchbuf);
13519 ins->scratchbuf[0] = '\0';
13520 }
13521 }
13522
13523 static void
13524 MOVSXD_Fixup (instr_info *ins, int bytemode, int sizeflag)
13525 {
13526 /* Add proper suffix to "movsxd". */
13527 char *p = ins->mnemonicendp;
13528
13529 switch (bytemode)
13530 {
13531 case movsxd_mode:
13532 if (!ins->intel_syntax)
13533 {
13534 USED_REX (REX_W);
13535 if (ins->rex & REX_W)
13536 {
13537 *p++ = 'l';
13538 *p++ = 'q';
13539 break;
13540 }
13541 }
13542
13543 *p++ = 'x';
13544 *p++ = 'd';
13545 break;
13546 default:
13547 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
13548 break;
13549 }
13550
13551 ins->mnemonicendp = p;
13552 *p = '\0';
13553 OP_E (ins, bytemode, sizeflag);
13554 }
13555
13556 static void
13557 DistinctDest_Fixup (instr_info *ins, int bytemode, int sizeflag)
13558 {
13559 unsigned int reg = ins->vex.register_specifier;
13560 unsigned int modrm_reg = ins->modrm.reg;
13561 unsigned int modrm_rm = ins->modrm.rm;
13562
13563 /* Calc destination register number. */
13564 if (ins->rex & REX_R)
13565 modrm_reg += 8;
13566 if (!ins->vex.r)
13567 modrm_reg += 16;
13568
13569 /* Calc src1 register number. */
13570 if (ins->address_mode != mode_64bit)
13571 reg &= 7;
13572 else if (ins->vex.evex && !ins->vex.v)
13573 reg += 16;
13574
13575 /* Calc src2 register number. */
13576 if (ins->modrm.mod == 3)
13577 {
13578 if (ins->rex & REX_B)
13579 modrm_rm += 8;
13580 if (ins->rex & REX_X)
13581 modrm_rm += 16;
13582 }
13583
13584 /* Destination and source registers must be distinct, output bad if
13585 dest == src1 or dest == src2. */
13586 if (modrm_reg == reg
13587 || (ins->modrm.mod == 3
13588 && modrm_reg == modrm_rm))
13589 {
13590 oappend (ins, "(bad)");
13591 }
13592 else
13593 OP_XMM (ins, bytemode, sizeflag);
13594 }
13595
13596 static void
13597 OP_Rounding (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13598 {
13599 if (ins->modrm.mod != 3 || !ins->vex.b)
13600 return;
13601
13602 switch (bytemode)
13603 {
13604 case evex_rounding_64_mode:
13605 if (ins->address_mode != mode_64bit || !ins->vex.w)
13606 return;
13607 /* Fall through. */
13608 case evex_rounding_mode:
13609 ins->evex_used |= EVEX_b_used;
13610 oappend (ins, names_rounding[ins->vex.ll]);
13611 break;
13612 case evex_sae_mode:
13613 ins->evex_used |= EVEX_b_used;
13614 oappend (ins, "{");
13615 break;
13616 default:
13617 abort ();
13618 }
13619 oappend (ins, "sae}");
13620 }
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