1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2018 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VCMP_Fixup (int, int);
99 static void VPCMP_Fixup (int, int);
100 static void VPCOM_Fixup (int, int);
101 static void OP_0f07 (int, int);
102 static void OP_Monitor (int, int);
103 static void OP_Mwait (int, int);
104 static void OP_Mwaitx (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void BND_Fixup (int, int);
112 static void NOTRACK_Fixup (int, int);
113 static void HLE_Fixup1 (int, int);
114 static void HLE_Fixup2 (int, int);
115 static void HLE_Fixup3 (int, int);
116 static void CMPXCHG8B_Fixup (int, int);
117 static void XMM_Fixup (int, int);
118 static void CRC32_Fixup (int, int);
119 static void FXSAVE_Fixup (int, int);
120 static void PCMPESTR_Fixup (int, int);
121 static void OP_LWPCB_E (int, int);
122 static void OP_LWP_E (int, int);
123 static void OP_Vex_2src_1 (int, int);
124 static void OP_Vex_2src_2 (int, int);
126 static void MOVBE_Fixup (int, int);
128 static void OP_Mask (int, int);
131 /* Points to first byte not fetched. */
132 bfd_byte
*max_fetched
;
133 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
136 OPCODES_SIGJMP_BUF bailout
;
146 enum address_mode address_mode
;
148 /* Flags for the prefixes for the current instruction. See below. */
151 /* REX prefix the current instruction. See below. */
153 /* Bits of REX we've already used. */
155 /* REX bits in original REX prefix ignored. */
156 static int rex_ignored
;
157 /* Mark parts used in the REX prefix. When we are testing for
158 empty prefix (for 8bit register REX extension), just mask it
159 out. Otherwise test for REX bit is excuse for existence of REX
160 only in case value is nonzero. */
161 #define USED_REX(value) \
166 rex_used |= (value) | REX_OPCODE; \
169 rex_used |= REX_OPCODE; \
172 /* Flags for prefixes which we somehow handled when printing the
173 current instruction. */
174 static int used_prefixes
;
176 /* Flags stored in PREFIXES. */
177 #define PREFIX_REPZ 1
178 #define PREFIX_REPNZ 2
179 #define PREFIX_LOCK 4
181 #define PREFIX_SS 0x10
182 #define PREFIX_DS 0x20
183 #define PREFIX_ES 0x40
184 #define PREFIX_FS 0x80
185 #define PREFIX_GS 0x100
186 #define PREFIX_DATA 0x200
187 #define PREFIX_ADDR 0x400
188 #define PREFIX_FWAIT 0x800
190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
191 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
193 #define FETCH_DATA(info, addr) \
194 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
195 ? 1 : fetch_data ((info), (addr)))
198 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
201 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
202 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
204 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
205 status
= (*info
->read_memory_func
) (start
,
207 addr
- priv
->max_fetched
,
213 /* If we did manage to read at least one byte, then
214 print_insn_i386 will do something sensible. Otherwise, print
215 an error. We do that here because this is where we know
217 if (priv
->max_fetched
== priv
->the_buffer
)
218 (*info
->memory_error_func
) (status
, start
, info
);
219 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
222 priv
->max_fetched
= addr
;
226 /* Possible values for prefix requirement. */
227 #define PREFIX_IGNORED_SHIFT 16
228 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
229 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
234 /* Opcode prefixes. */
235 #define PREFIX_OPCODE (PREFIX_REPZ \
239 /* Prefixes ignored. */
240 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
241 | PREFIX_IGNORED_REPNZ \
242 | PREFIX_IGNORED_DATA)
244 #define XX { NULL, 0 }
245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
247 #define Eb { OP_E, b_mode }
248 #define Ebnd { OP_E, bnd_mode }
249 #define EbS { OP_E, b_swap_mode }
250 #define EbndS { OP_E, bnd_swap_mode }
251 #define Ev { OP_E, v_mode }
252 #define Eva { OP_E, va_mode }
253 #define Ev_bnd { OP_E, v_bnd_mode }
254 #define EvS { OP_E, v_swap_mode }
255 #define Ed { OP_E, d_mode }
256 #define Edq { OP_E, dq_mode }
257 #define Edqw { OP_E, dqw_mode }
258 #define Edqb { OP_E, dqb_mode }
259 #define Edb { OP_E, db_mode }
260 #define Edw { OP_E, dw_mode }
261 #define Edqd { OP_E, dqd_mode }
262 #define Edqa { OP_E, dqa_mode }
263 #define Eq { OP_E, q_mode }
264 #define indirEv { OP_indirE, indir_v_mode }
265 #define indirEp { OP_indirE, f_mode }
266 #define stackEv { OP_E, stack_v_mode }
267 #define Em { OP_E, m_mode }
268 #define Ew { OP_E, w_mode }
269 #define M { OP_M, 0 } /* lea, lgdt, etc. */
270 #define Ma { OP_M, a_mode }
271 #define Mb { OP_M, b_mode }
272 #define Md { OP_M, d_mode }
273 #define Mo { OP_M, o_mode }
274 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
275 #define Mq { OP_M, q_mode }
276 #define Mv_bnd { OP_M, v_bndmk_mode }
277 #define Mx { OP_M, x_mode }
278 #define Mxmm { OP_M, xmm_mode }
279 #define Gb { OP_G, b_mode }
280 #define Gbnd { OP_G, bnd_mode }
281 #define Gv { OP_G, v_mode }
282 #define Gd { OP_G, d_mode }
283 #define Gdq { OP_G, dq_mode }
284 #define Gm { OP_G, m_mode }
285 #define Gva { OP_G, va_mode }
286 #define Gw { OP_G, w_mode }
287 #define Rd { OP_R, d_mode }
288 #define Rdq { OP_R, dq_mode }
289 #define Rm { OP_R, m_mode }
290 #define Ib { OP_I, b_mode }
291 #define sIb { OP_sI, b_mode } /* sign extened byte */
292 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
293 #define Iv { OP_I, v_mode }
294 #define sIv { OP_sI, v_mode }
295 #define Iq { OP_I, q_mode }
296 #define Iv64 { OP_I64, v_mode }
297 #define Iw { OP_I, w_mode }
298 #define I1 { OP_I, const_1_mode }
299 #define Jb { OP_J, b_mode }
300 #define Jv { OP_J, v_mode }
301 #define Cm { OP_C, m_mode }
302 #define Dm { OP_D, m_mode }
303 #define Td { OP_T, d_mode }
304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
306 #define RMeAX { OP_REG, eAX_reg }
307 #define RMeBX { OP_REG, eBX_reg }
308 #define RMeCX { OP_REG, eCX_reg }
309 #define RMeDX { OP_REG, eDX_reg }
310 #define RMeSP { OP_REG, eSP_reg }
311 #define RMeBP { OP_REG, eBP_reg }
312 #define RMeSI { OP_REG, eSI_reg }
313 #define RMeDI { OP_REG, eDI_reg }
314 #define RMrAX { OP_REG, rAX_reg }
315 #define RMrBX { OP_REG, rBX_reg }
316 #define RMrCX { OP_REG, rCX_reg }
317 #define RMrDX { OP_REG, rDX_reg }
318 #define RMrSP { OP_REG, rSP_reg }
319 #define RMrBP { OP_REG, rBP_reg }
320 #define RMrSI { OP_REG, rSI_reg }
321 #define RMrDI { OP_REG, rDI_reg }
322 #define RMAL { OP_REG, al_reg }
323 #define RMCL { OP_REG, cl_reg }
324 #define RMDL { OP_REG, dl_reg }
325 #define RMBL { OP_REG, bl_reg }
326 #define RMAH { OP_REG, ah_reg }
327 #define RMCH { OP_REG, ch_reg }
328 #define RMDH { OP_REG, dh_reg }
329 #define RMBH { OP_REG, bh_reg }
330 #define RMAX { OP_REG, ax_reg }
331 #define RMDX { OP_REG, dx_reg }
333 #define eAX { OP_IMREG, eAX_reg }
334 #define eBX { OP_IMREG, eBX_reg }
335 #define eCX { OP_IMREG, eCX_reg }
336 #define eDX { OP_IMREG, eDX_reg }
337 #define eSP { OP_IMREG, eSP_reg }
338 #define eBP { OP_IMREG, eBP_reg }
339 #define eSI { OP_IMREG, eSI_reg }
340 #define eDI { OP_IMREG, eDI_reg }
341 #define AL { OP_IMREG, al_reg }
342 #define CL { OP_IMREG, cl_reg }
343 #define DL { OP_IMREG, dl_reg }
344 #define BL { OP_IMREG, bl_reg }
345 #define AH { OP_IMREG, ah_reg }
346 #define CH { OP_IMREG, ch_reg }
347 #define DH { OP_IMREG, dh_reg }
348 #define BH { OP_IMREG, bh_reg }
349 #define AX { OP_IMREG, ax_reg }
350 #define DX { OP_IMREG, dx_reg }
351 #define zAX { OP_IMREG, z_mode_ax_reg }
352 #define indirDX { OP_IMREG, indir_dx_reg }
354 #define Sw { OP_SEG, w_mode }
355 #define Sv { OP_SEG, v_mode }
356 #define Ap { OP_DIR, 0 }
357 #define Ob { OP_OFF64, b_mode }
358 #define Ov { OP_OFF64, v_mode }
359 #define Xb { OP_DSreg, eSI_reg }
360 #define Xv { OP_DSreg, eSI_reg }
361 #define Xz { OP_DSreg, eSI_reg }
362 #define Yb { OP_ESreg, eDI_reg }
363 #define Yv { OP_ESreg, eDI_reg }
364 #define DSBX { OP_DSreg, eBX_reg }
366 #define es { OP_REG, es_reg }
367 #define ss { OP_REG, ss_reg }
368 #define cs { OP_REG, cs_reg }
369 #define ds { OP_REG, ds_reg }
370 #define fs { OP_REG, fs_reg }
371 #define gs { OP_REG, gs_reg }
373 #define MX { OP_MMX, 0 }
374 #define XM { OP_XMM, 0 }
375 #define XMScalar { OP_XMM, scalar_mode }
376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
377 #define XMM { OP_XMM, xmm_mode }
378 #define XMxmmq { OP_XMM, xmmq_mode }
379 #define EM { OP_EM, v_mode }
380 #define EMS { OP_EM, v_swap_mode }
381 #define EMd { OP_EM, d_mode }
382 #define EMx { OP_EM, x_mode }
383 #define EXbScalar { OP_EX, b_scalar_mode }
384 #define EXw { OP_EX, w_mode }
385 #define EXwScalar { OP_EX, w_scalar_mode }
386 #define EXd { OP_EX, d_mode }
387 #define EXdScalar { OP_EX, d_scalar_mode }
388 #define EXdS { OP_EX, d_swap_mode }
389 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
390 #define EXq { OP_EX, q_mode }
391 #define EXqScalar { OP_EX, q_scalar_mode }
392 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
393 #define EXqS { OP_EX, q_swap_mode }
394 #define EXx { OP_EX, x_mode }
395 #define EXxS { OP_EX, x_swap_mode }
396 #define EXxmm { OP_EX, xmm_mode }
397 #define EXymm { OP_EX, ymm_mode }
398 #define EXxmmq { OP_EX, xmmq_mode }
399 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
400 #define EXxmm_mb { OP_EX, xmm_mb_mode }
401 #define EXxmm_mw { OP_EX, xmm_mw_mode }
402 #define EXxmm_md { OP_EX, xmm_md_mode }
403 #define EXxmm_mq { OP_EX, xmm_mq_mode }
404 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
405 #define EXxmmdw { OP_EX, xmmdw_mode }
406 #define EXxmmqd { OP_EX, xmmqd_mode }
407 #define EXymmq { OP_EX, ymmq_mode }
408 #define EXVexWdq { OP_EX, vex_w_dq_mode }
409 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
410 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
411 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
412 #define MS { OP_MS, v_mode }
413 #define XS { OP_XS, v_mode }
414 #define EMCq { OP_EMC, q_mode }
415 #define MXC { OP_MXC, 0 }
416 #define OPSUF { OP_3DNowSuffix, 0 }
417 #define CMP { CMP_Fixup, 0 }
418 #define XMM0 { XMM_Fixup, 0 }
419 #define FXSAVE { FXSAVE_Fixup, 0 }
420 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
421 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
423 #define Vex { OP_VEX, vex_mode }
424 #define VexScalar { OP_VEX, vex_scalar_mode }
425 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
426 #define Vex128 { OP_VEX, vex128_mode }
427 #define Vex256 { OP_VEX, vex256_mode }
428 #define VexGdq { OP_VEX, dq_mode }
429 #define EXdVex { OP_EX_Vex, d_mode }
430 #define EXdVexS { OP_EX_Vex, d_swap_mode }
431 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
432 #define EXqVex { OP_EX_Vex, q_mode }
433 #define EXqVexS { OP_EX_Vex, q_swap_mode }
434 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
435 #define EXVexW { OP_EX_VexW, x_mode }
436 #define EXdVexW { OP_EX_VexW, d_mode }
437 #define EXqVexW { OP_EX_VexW, q_mode }
438 #define EXVexImmW { OP_EX_VexImmW, x_mode }
439 #define XMVex { OP_XMM_Vex, 0 }
440 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
441 #define XMVexW { OP_XMM_VexW, 0 }
442 #define XMVexI4 { OP_REG_VexI4, x_mode }
443 #define PCLMUL { PCLMUL_Fixup, 0 }
444 #define VCMP { VCMP_Fixup, 0 }
445 #define VPCMP { VPCMP_Fixup, 0 }
446 #define VPCOM { VPCOM_Fixup, 0 }
448 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
449 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
450 #define EXxEVexS { OP_Rounding, evex_sae_mode }
452 #define XMask { OP_Mask, mask_mode }
453 #define MaskG { OP_G, mask_mode }
454 #define MaskE { OP_E, mask_mode }
455 #define MaskBDE { OP_E, mask_bd_mode }
456 #define MaskR { OP_R, mask_mode }
457 #define MaskVex { OP_VEX, mask_mode }
459 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
460 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
461 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
462 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
464 /* Used handle "rep" prefix for string instructions. */
465 #define Xbr { REP_Fixup, eSI_reg }
466 #define Xvr { REP_Fixup, eSI_reg }
467 #define Ybr { REP_Fixup, eDI_reg }
468 #define Yvr { REP_Fixup, eDI_reg }
469 #define Yzr { REP_Fixup, eDI_reg }
470 #define indirDXr { REP_Fixup, indir_dx_reg }
471 #define ALr { REP_Fixup, al_reg }
472 #define eAXr { REP_Fixup, eAX_reg }
474 /* Used handle HLE prefix for lockable instructions. */
475 #define Ebh1 { HLE_Fixup1, b_mode }
476 #define Evh1 { HLE_Fixup1, v_mode }
477 #define Ebh2 { HLE_Fixup2, b_mode }
478 #define Evh2 { HLE_Fixup2, v_mode }
479 #define Ebh3 { HLE_Fixup3, b_mode }
480 #define Evh3 { HLE_Fixup3, v_mode }
482 #define BND { BND_Fixup, 0 }
483 #define NOTRACK { NOTRACK_Fixup, 0 }
485 #define cond_jump_flag { NULL, cond_jump_mode }
486 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
488 /* bits in sizeflag */
489 #define SUFFIX_ALWAYS 4
497 /* byte operand with operand swapped */
499 /* byte operand, sign extend like 'T' suffix */
501 /* operand size depends on prefixes */
503 /* operand size depends on prefixes with operand swapped */
505 /* operand size depends on address prefix */
509 /* double word operand */
511 /* double word operand with operand swapped */
513 /* quad word operand */
515 /* quad word operand with operand swapped */
517 /* ten-byte operand */
519 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
520 broadcast enabled. */
522 /* Similar to x_mode, but with different EVEX mem shifts. */
524 /* Similar to x_mode, but with disabled broadcast. */
526 /* Similar to x_mode, but with operands swapped and disabled broadcast
529 /* 16-byte XMM operand */
531 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
532 memory operand (depending on vector length). Broadcast isn't
535 /* Same as xmmq_mode, but broadcast is allowed. */
536 evex_half_bcst_xmmq_mode
,
537 /* XMM register or byte memory operand */
539 /* XMM register or word memory operand */
541 /* XMM register or double word memory operand */
543 /* XMM register or quad word memory operand */
545 /* XMM register or double/quad word memory operand, depending on
548 /* 16-byte XMM, word, double word or quad word operand. */
550 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
552 /* 32-byte YMM operand */
554 /* quad word, ymmword or zmmword memory operand. */
556 /* 32-byte YMM or 16-byte word operand */
558 /* d_mode in 32bit, q_mode in 64bit mode. */
560 /* pair of v_mode operands */
565 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
567 /* operand size depends on REX prefixes. */
569 /* registers like dq_mode, memory like w_mode. */
573 /* bounds operand with operand swapped */
575 /* 4- or 6-byte pointer operand */
578 /* v_mode for indirect branch opcodes. */
580 /* v_mode for stack-related opcodes. */
582 /* non-quad operand size depends on prefixes */
584 /* 16-byte operand */
586 /* registers like dq_mode, memory like b_mode. */
588 /* registers like d_mode, memory like b_mode. */
590 /* registers like d_mode, memory like w_mode. */
592 /* registers like dq_mode, memory like d_mode. */
594 /* operand size depends on the W bit as well as address mode. */
596 /* normal vex mode */
598 /* 128bit vex mode */
600 /* 256bit vex mode */
602 /* operand size depends on the VEX.W bit. */
605 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
606 vex_vsib_d_w_dq_mode
,
607 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
609 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
610 vex_vsib_q_w_dq_mode
,
611 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
614 /* scalar, ignore vector length. */
616 /* like b_mode, ignore vector length. */
618 /* like w_mode, ignore vector length. */
620 /* like d_mode, ignore vector length. */
622 /* like d_swap_mode, ignore vector length. */
624 /* like q_mode, ignore vector length. */
626 /* like q_swap_mode, ignore vector length. */
628 /* like vex_mode, ignore vector length. */
630 /* like vex_w_dq_mode, ignore vector length. */
631 vex_scalar_w_dq_mode
,
633 /* Static rounding. */
635 /* Static rounding, 64-bit mode only. */
636 evex_rounding_64_mode
,
637 /* Supress all exceptions. */
640 /* Mask register operand. */
642 /* Mask register operand. */
709 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
711 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
712 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
713 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
714 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
715 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
716 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
717 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
718 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
719 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
720 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
721 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
722 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
723 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
724 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
725 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
851 MOD_VEX_0F12_PREFIX_0
,
853 MOD_VEX_0F16_PREFIX_0
,
856 MOD_VEX_W_0_0F41_P_0_LEN_1
,
857 MOD_VEX_W_1_0F41_P_0_LEN_1
,
858 MOD_VEX_W_0_0F41_P_2_LEN_1
,
859 MOD_VEX_W_1_0F41_P_2_LEN_1
,
860 MOD_VEX_W_0_0F42_P_0_LEN_1
,
861 MOD_VEX_W_1_0F42_P_0_LEN_1
,
862 MOD_VEX_W_0_0F42_P_2_LEN_1
,
863 MOD_VEX_W_1_0F42_P_2_LEN_1
,
864 MOD_VEX_W_0_0F44_P_0_LEN_1
,
865 MOD_VEX_W_1_0F44_P_0_LEN_1
,
866 MOD_VEX_W_0_0F44_P_2_LEN_1
,
867 MOD_VEX_W_1_0F44_P_2_LEN_1
,
868 MOD_VEX_W_0_0F45_P_0_LEN_1
,
869 MOD_VEX_W_1_0F45_P_0_LEN_1
,
870 MOD_VEX_W_0_0F45_P_2_LEN_1
,
871 MOD_VEX_W_1_0F45_P_2_LEN_1
,
872 MOD_VEX_W_0_0F46_P_0_LEN_1
,
873 MOD_VEX_W_1_0F46_P_0_LEN_1
,
874 MOD_VEX_W_0_0F46_P_2_LEN_1
,
875 MOD_VEX_W_1_0F46_P_2_LEN_1
,
876 MOD_VEX_W_0_0F47_P_0_LEN_1
,
877 MOD_VEX_W_1_0F47_P_0_LEN_1
,
878 MOD_VEX_W_0_0F47_P_2_LEN_1
,
879 MOD_VEX_W_1_0F47_P_2_LEN_1
,
880 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
881 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
882 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
883 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
884 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
885 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
886 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
898 MOD_VEX_W_0_0F91_P_0_LEN_0
,
899 MOD_VEX_W_1_0F91_P_0_LEN_0
,
900 MOD_VEX_W_0_0F91_P_2_LEN_0
,
901 MOD_VEX_W_1_0F91_P_2_LEN_0
,
902 MOD_VEX_W_0_0F92_P_0_LEN_0
,
903 MOD_VEX_W_0_0F92_P_2_LEN_0
,
904 MOD_VEX_W_0_0F92_P_3_LEN_0
,
905 MOD_VEX_W_1_0F92_P_3_LEN_0
,
906 MOD_VEX_W_0_0F93_P_0_LEN_0
,
907 MOD_VEX_W_0_0F93_P_2_LEN_0
,
908 MOD_VEX_W_0_0F93_P_3_LEN_0
,
909 MOD_VEX_W_1_0F93_P_3_LEN_0
,
910 MOD_VEX_W_0_0F98_P_0_LEN_0
,
911 MOD_VEX_W_1_0F98_P_0_LEN_0
,
912 MOD_VEX_W_0_0F98_P_2_LEN_0
,
913 MOD_VEX_W_1_0F98_P_2_LEN_0
,
914 MOD_VEX_W_0_0F99_P_0_LEN_0
,
915 MOD_VEX_W_1_0F99_P_0_LEN_0
,
916 MOD_VEX_W_0_0F99_P_2_LEN_0
,
917 MOD_VEX_W_1_0F99_P_2_LEN_0
,
920 MOD_VEX_0FD7_PREFIX_2
,
921 MOD_VEX_0FE7_PREFIX_2
,
922 MOD_VEX_0FF0_PREFIX_3
,
923 MOD_VEX_0F381A_PREFIX_2
,
924 MOD_VEX_0F382A_PREFIX_2
,
925 MOD_VEX_0F382C_PREFIX_2
,
926 MOD_VEX_0F382D_PREFIX_2
,
927 MOD_VEX_0F382E_PREFIX_2
,
928 MOD_VEX_0F382F_PREFIX_2
,
929 MOD_VEX_0F385A_PREFIX_2
,
930 MOD_VEX_0F388C_PREFIX_2
,
931 MOD_VEX_0F388E_PREFIX_2
,
932 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
933 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
934 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
935 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
936 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
937 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
938 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
939 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
941 MOD_EVEX_0F10_PREFIX_1
,
942 MOD_EVEX_0F10_PREFIX_3
,
943 MOD_EVEX_0F11_PREFIX_1
,
944 MOD_EVEX_0F11_PREFIX_3
,
945 MOD_EVEX_0F12_PREFIX_0
,
946 MOD_EVEX_0F16_PREFIX_0
,
947 MOD_EVEX_0F38C6_REG_1
,
948 MOD_EVEX_0F38C6_REG_2
,
949 MOD_EVEX_0F38C6_REG_5
,
950 MOD_EVEX_0F38C6_REG_6
,
951 MOD_EVEX_0F38C7_REG_1
,
952 MOD_EVEX_0F38C7_REG_2
,
953 MOD_EVEX_0F38C7_REG_5
,
954 MOD_EVEX_0F38C7_REG_6
975 PREFIX_MOD_0_0F01_REG_5
,
976 PREFIX_MOD_3_0F01_REG_5_RM_0
,
977 PREFIX_MOD_3_0F01_REG_5_RM_2
,
1023 PREFIX_MOD_0_0FAE_REG_4
,
1024 PREFIX_MOD_3_0FAE_REG_4
,
1025 PREFIX_MOD_0_0FAE_REG_5
,
1026 PREFIX_MOD_3_0FAE_REG_5
,
1027 PREFIX_MOD_0_0FAE_REG_6
,
1028 PREFIX_MOD_1_0FAE_REG_6
,
1035 PREFIX_MOD_0_0FC7_REG_6
,
1036 PREFIX_MOD_3_0FC7_REG_6
,
1037 PREFIX_MOD_3_0FC7_REG_7
,
1167 PREFIX_VEX_0F71_REG_2
,
1168 PREFIX_VEX_0F71_REG_4
,
1169 PREFIX_VEX_0F71_REG_6
,
1170 PREFIX_VEX_0F72_REG_2
,
1171 PREFIX_VEX_0F72_REG_4
,
1172 PREFIX_VEX_0F72_REG_6
,
1173 PREFIX_VEX_0F73_REG_2
,
1174 PREFIX_VEX_0F73_REG_3
,
1175 PREFIX_VEX_0F73_REG_6
,
1176 PREFIX_VEX_0F73_REG_7
,
1349 PREFIX_VEX_0F38F3_REG_1
,
1350 PREFIX_VEX_0F38F3_REG_2
,
1351 PREFIX_VEX_0F38F3_REG_3
,
1470 PREFIX_EVEX_0F71_REG_2
,
1471 PREFIX_EVEX_0F71_REG_4
,
1472 PREFIX_EVEX_0F71_REG_6
,
1473 PREFIX_EVEX_0F72_REG_0
,
1474 PREFIX_EVEX_0F72_REG_1
,
1475 PREFIX_EVEX_0F72_REG_2
,
1476 PREFIX_EVEX_0F72_REG_4
,
1477 PREFIX_EVEX_0F72_REG_6
,
1478 PREFIX_EVEX_0F73_REG_2
,
1479 PREFIX_EVEX_0F73_REG_3
,
1480 PREFIX_EVEX_0F73_REG_6
,
1481 PREFIX_EVEX_0F73_REG_7
,
1677 PREFIX_EVEX_0F38C6_REG_1
,
1678 PREFIX_EVEX_0F38C6_REG_2
,
1679 PREFIX_EVEX_0F38C6_REG_5
,
1680 PREFIX_EVEX_0F38C6_REG_6
,
1681 PREFIX_EVEX_0F38C7_REG_1
,
1682 PREFIX_EVEX_0F38C7_REG_2
,
1683 PREFIX_EVEX_0F38C7_REG_5
,
1684 PREFIX_EVEX_0F38C7_REG_6
,
1786 THREE_BYTE_0F38
= 0,
1813 VEX_LEN_0F12_P_0_M_0
= 0,
1814 VEX_LEN_0F12_P_0_M_1
,
1817 VEX_LEN_0F16_P_0_M_0
,
1818 VEX_LEN_0F16_P_0_M_1
,
1861 VEX_LEN_0FAE_R_2_M_0
,
1862 VEX_LEN_0FAE_R_3_M_0
,
1869 VEX_LEN_0F381A_P_2_M_0
,
1872 VEX_LEN_0F385A_P_2_M_0
,
1875 VEX_LEN_0F38F3_R_1_P_0
,
1876 VEX_LEN_0F38F3_R_2_P_0
,
1877 VEX_LEN_0F38F3_R_3_P_0
,
1920 VEX_LEN_0FXOP_08_CC
,
1921 VEX_LEN_0FXOP_08_CD
,
1922 VEX_LEN_0FXOP_08_CE
,
1923 VEX_LEN_0FXOP_08_CF
,
1924 VEX_LEN_0FXOP_08_EC
,
1925 VEX_LEN_0FXOP_08_ED
,
1926 VEX_LEN_0FXOP_08_EE
,
1927 VEX_LEN_0FXOP_08_EF
,
1928 VEX_LEN_0FXOP_09_80
,
1934 VEX_W_0F41_P_0_LEN_1
= 0,
1935 VEX_W_0F41_P_2_LEN_1
,
1936 VEX_W_0F42_P_0_LEN_1
,
1937 VEX_W_0F42_P_2_LEN_1
,
1938 VEX_W_0F44_P_0_LEN_0
,
1939 VEX_W_0F44_P_2_LEN_0
,
1940 VEX_W_0F45_P_0_LEN_1
,
1941 VEX_W_0F45_P_2_LEN_1
,
1942 VEX_W_0F46_P_0_LEN_1
,
1943 VEX_W_0F46_P_2_LEN_1
,
1944 VEX_W_0F47_P_0_LEN_1
,
1945 VEX_W_0F47_P_2_LEN_1
,
1946 VEX_W_0F4A_P_0_LEN_1
,
1947 VEX_W_0F4A_P_2_LEN_1
,
1948 VEX_W_0F4B_P_0_LEN_1
,
1949 VEX_W_0F4B_P_2_LEN_1
,
1950 VEX_W_0F90_P_0_LEN_0
,
1951 VEX_W_0F90_P_2_LEN_0
,
1952 VEX_W_0F91_P_0_LEN_0
,
1953 VEX_W_0F91_P_2_LEN_0
,
1954 VEX_W_0F92_P_0_LEN_0
,
1955 VEX_W_0F92_P_2_LEN_0
,
1956 VEX_W_0F92_P_3_LEN_0
,
1957 VEX_W_0F93_P_0_LEN_0
,
1958 VEX_W_0F93_P_2_LEN_0
,
1959 VEX_W_0F93_P_3_LEN_0
,
1960 VEX_W_0F98_P_0_LEN_0
,
1961 VEX_W_0F98_P_2_LEN_0
,
1962 VEX_W_0F99_P_0_LEN_0
,
1963 VEX_W_0F99_P_2_LEN_0
,
1973 VEX_W_0F381A_P_2_M_0
,
1974 VEX_W_0F382C_P_2_M_0
,
1975 VEX_W_0F382D_P_2_M_0
,
1976 VEX_W_0F382E_P_2_M_0
,
1977 VEX_W_0F382F_P_2_M_0
,
1982 VEX_W_0F385A_P_2_M_0
,
1997 VEX_W_0F3A30_P_2_LEN_0
,
1998 VEX_W_0F3A31_P_2_LEN_0
,
1999 VEX_W_0F3A32_P_2_LEN_0
,
2000 VEX_W_0F3A33_P_2_LEN_0
,
2013 EVEX_W_0F10_P_1_M_0
,
2014 EVEX_W_0F10_P_1_M_1
,
2016 EVEX_W_0F10_P_3_M_0
,
2017 EVEX_W_0F10_P_3_M_1
,
2019 EVEX_W_0F11_P_1_M_0
,
2020 EVEX_W_0F11_P_1_M_1
,
2022 EVEX_W_0F11_P_3_M_0
,
2023 EVEX_W_0F11_P_3_M_1
,
2024 EVEX_W_0F12_P_0_M_0
,
2025 EVEX_W_0F12_P_0_M_1
,
2035 EVEX_W_0F16_P_0_M_0
,
2036 EVEX_W_0F16_P_0_M_1
,
2107 EVEX_W_0F72_R_2_P_2
,
2108 EVEX_W_0F72_R_6_P_2
,
2109 EVEX_W_0F73_R_2_P_2
,
2110 EVEX_W_0F73_R_6_P_2
,
2218 EVEX_W_0F38C7_R_1_P_2
,
2219 EVEX_W_0F38C7_R_2_P_2
,
2220 EVEX_W_0F38C7_R_5_P_2
,
2221 EVEX_W_0F38C7_R_6_P_2
,
2262 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2271 unsigned int prefix_requirement
;
2274 /* Upper case letters in the instruction names here are macros.
2275 'A' => print 'b' if no register operands or suffix_always is true
2276 'B' => print 'b' if suffix_always is true
2277 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2279 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2280 suffix_always is true
2281 'E' => print 'e' if 32-bit form of jcxz
2282 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2283 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2284 'H' => print ",pt" or ",pn" branch hint
2285 'I' => honor following macro letter even in Intel mode (implemented only
2286 for some of the macro letters)
2288 'K' => print 'd' or 'q' if rex prefix is present.
2289 'L' => print 'l' if suffix_always is true
2290 'M' => print 'r' if intel_mnemonic is false.
2291 'N' => print 'n' if instruction has no wait "prefix"
2292 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2293 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2294 or suffix_always is true. print 'q' if rex prefix is present.
2295 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2297 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2298 'S' => print 'w', 'l' or 'q' if suffix_always is true
2299 'T' => print 'q' in 64bit mode if instruction has no operand size
2300 prefix and behave as 'P' otherwise
2301 'U' => print 'q' in 64bit mode if instruction has no operand size
2302 prefix and behave as 'Q' otherwise
2303 'V' => print 'q' in 64bit mode if instruction has no operand size
2304 prefix and behave as 'S' otherwise
2305 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2306 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2308 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2309 '!' => change condition from true to false or from false to true.
2310 '%' => add 1 upper case letter to the macro.
2311 '^' => print 'w' or 'l' depending on operand size prefix or
2312 suffix_always is true (lcall/ljmp).
2313 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2314 on operand size prefix.
2315 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2316 has no operand size prefix for AMD64 ISA, behave as 'P'
2319 2 upper case letter macros:
2320 "XY" => print 'x' or 'y' if suffix_always is true or no register
2321 operands and no broadcast.
2322 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2323 register operands and no broadcast.
2324 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2325 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2326 or suffix_always is true
2327 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2328 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2329 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2330 "LW" => print 'd', 'q' depending on the VEX.W bit
2331 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2332 an operand size prefix, or suffix_always is true. print
2333 'q' if rex prefix is present.
2335 Many of the above letters print nothing in Intel mode. See "putop"
2338 Braces '{' and '}', and vertical bars '|', indicate alternative
2339 mnemonic strings for AT&T and Intel. */
2341 static const struct dis386 dis386
[] = {
2343 { "addB", { Ebh1
, Gb
}, 0 },
2344 { "addS", { Evh1
, Gv
}, 0 },
2345 { "addB", { Gb
, EbS
}, 0 },
2346 { "addS", { Gv
, EvS
}, 0 },
2347 { "addB", { AL
, Ib
}, 0 },
2348 { "addS", { eAX
, Iv
}, 0 },
2349 { X86_64_TABLE (X86_64_06
) },
2350 { X86_64_TABLE (X86_64_07
) },
2352 { "orB", { Ebh1
, Gb
}, 0 },
2353 { "orS", { Evh1
, Gv
}, 0 },
2354 { "orB", { Gb
, EbS
}, 0 },
2355 { "orS", { Gv
, EvS
}, 0 },
2356 { "orB", { AL
, Ib
}, 0 },
2357 { "orS", { eAX
, Iv
}, 0 },
2358 { X86_64_TABLE (X86_64_0D
) },
2359 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2361 { "adcB", { Ebh1
, Gb
}, 0 },
2362 { "adcS", { Evh1
, Gv
}, 0 },
2363 { "adcB", { Gb
, EbS
}, 0 },
2364 { "adcS", { Gv
, EvS
}, 0 },
2365 { "adcB", { AL
, Ib
}, 0 },
2366 { "adcS", { eAX
, Iv
}, 0 },
2367 { X86_64_TABLE (X86_64_16
) },
2368 { X86_64_TABLE (X86_64_17
) },
2370 { "sbbB", { Ebh1
, Gb
}, 0 },
2371 { "sbbS", { Evh1
, Gv
}, 0 },
2372 { "sbbB", { Gb
, EbS
}, 0 },
2373 { "sbbS", { Gv
, EvS
}, 0 },
2374 { "sbbB", { AL
, Ib
}, 0 },
2375 { "sbbS", { eAX
, Iv
}, 0 },
2376 { X86_64_TABLE (X86_64_1E
) },
2377 { X86_64_TABLE (X86_64_1F
) },
2379 { "andB", { Ebh1
, Gb
}, 0 },
2380 { "andS", { Evh1
, Gv
}, 0 },
2381 { "andB", { Gb
, EbS
}, 0 },
2382 { "andS", { Gv
, EvS
}, 0 },
2383 { "andB", { AL
, Ib
}, 0 },
2384 { "andS", { eAX
, Iv
}, 0 },
2385 { Bad_Opcode
}, /* SEG ES prefix */
2386 { X86_64_TABLE (X86_64_27
) },
2388 { "subB", { Ebh1
, Gb
}, 0 },
2389 { "subS", { Evh1
, Gv
}, 0 },
2390 { "subB", { Gb
, EbS
}, 0 },
2391 { "subS", { Gv
, EvS
}, 0 },
2392 { "subB", { AL
, Ib
}, 0 },
2393 { "subS", { eAX
, Iv
}, 0 },
2394 { Bad_Opcode
}, /* SEG CS prefix */
2395 { X86_64_TABLE (X86_64_2F
) },
2397 { "xorB", { Ebh1
, Gb
}, 0 },
2398 { "xorS", { Evh1
, Gv
}, 0 },
2399 { "xorB", { Gb
, EbS
}, 0 },
2400 { "xorS", { Gv
, EvS
}, 0 },
2401 { "xorB", { AL
, Ib
}, 0 },
2402 { "xorS", { eAX
, Iv
}, 0 },
2403 { Bad_Opcode
}, /* SEG SS prefix */
2404 { X86_64_TABLE (X86_64_37
) },
2406 { "cmpB", { Eb
, Gb
}, 0 },
2407 { "cmpS", { Ev
, Gv
}, 0 },
2408 { "cmpB", { Gb
, EbS
}, 0 },
2409 { "cmpS", { Gv
, EvS
}, 0 },
2410 { "cmpB", { AL
, Ib
}, 0 },
2411 { "cmpS", { eAX
, Iv
}, 0 },
2412 { Bad_Opcode
}, /* SEG DS prefix */
2413 { X86_64_TABLE (X86_64_3F
) },
2415 { "inc{S|}", { RMeAX
}, 0 },
2416 { "inc{S|}", { RMeCX
}, 0 },
2417 { "inc{S|}", { RMeDX
}, 0 },
2418 { "inc{S|}", { RMeBX
}, 0 },
2419 { "inc{S|}", { RMeSP
}, 0 },
2420 { "inc{S|}", { RMeBP
}, 0 },
2421 { "inc{S|}", { RMeSI
}, 0 },
2422 { "inc{S|}", { RMeDI
}, 0 },
2424 { "dec{S|}", { RMeAX
}, 0 },
2425 { "dec{S|}", { RMeCX
}, 0 },
2426 { "dec{S|}", { RMeDX
}, 0 },
2427 { "dec{S|}", { RMeBX
}, 0 },
2428 { "dec{S|}", { RMeSP
}, 0 },
2429 { "dec{S|}", { RMeBP
}, 0 },
2430 { "dec{S|}", { RMeSI
}, 0 },
2431 { "dec{S|}", { RMeDI
}, 0 },
2433 { "pushV", { RMrAX
}, 0 },
2434 { "pushV", { RMrCX
}, 0 },
2435 { "pushV", { RMrDX
}, 0 },
2436 { "pushV", { RMrBX
}, 0 },
2437 { "pushV", { RMrSP
}, 0 },
2438 { "pushV", { RMrBP
}, 0 },
2439 { "pushV", { RMrSI
}, 0 },
2440 { "pushV", { RMrDI
}, 0 },
2442 { "popV", { RMrAX
}, 0 },
2443 { "popV", { RMrCX
}, 0 },
2444 { "popV", { RMrDX
}, 0 },
2445 { "popV", { RMrBX
}, 0 },
2446 { "popV", { RMrSP
}, 0 },
2447 { "popV", { RMrBP
}, 0 },
2448 { "popV", { RMrSI
}, 0 },
2449 { "popV", { RMrDI
}, 0 },
2451 { X86_64_TABLE (X86_64_60
) },
2452 { X86_64_TABLE (X86_64_61
) },
2453 { X86_64_TABLE (X86_64_62
) },
2454 { X86_64_TABLE (X86_64_63
) },
2455 { Bad_Opcode
}, /* seg fs */
2456 { Bad_Opcode
}, /* seg gs */
2457 { Bad_Opcode
}, /* op size prefix */
2458 { Bad_Opcode
}, /* adr size prefix */
2460 { "pushT", { sIv
}, 0 },
2461 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2462 { "pushT", { sIbT
}, 0 },
2463 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2464 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2465 { X86_64_TABLE (X86_64_6D
) },
2466 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2467 { X86_64_TABLE (X86_64_6F
) },
2469 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2470 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2471 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2472 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2473 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2474 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2475 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2476 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2478 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2479 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2480 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2481 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2482 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2483 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2484 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2485 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2487 { REG_TABLE (REG_80
) },
2488 { REG_TABLE (REG_81
) },
2489 { X86_64_TABLE (X86_64_82
) },
2490 { REG_TABLE (REG_83
) },
2491 { "testB", { Eb
, Gb
}, 0 },
2492 { "testS", { Ev
, Gv
}, 0 },
2493 { "xchgB", { Ebh2
, Gb
}, 0 },
2494 { "xchgS", { Evh2
, Gv
}, 0 },
2496 { "movB", { Ebh3
, Gb
}, 0 },
2497 { "movS", { Evh3
, Gv
}, 0 },
2498 { "movB", { Gb
, EbS
}, 0 },
2499 { "movS", { Gv
, EvS
}, 0 },
2500 { "movD", { Sv
, Sw
}, 0 },
2501 { MOD_TABLE (MOD_8D
) },
2502 { "movD", { Sw
, Sv
}, 0 },
2503 { REG_TABLE (REG_8F
) },
2505 { PREFIX_TABLE (PREFIX_90
) },
2506 { "xchgS", { RMeCX
, eAX
}, 0 },
2507 { "xchgS", { RMeDX
, eAX
}, 0 },
2508 { "xchgS", { RMeBX
, eAX
}, 0 },
2509 { "xchgS", { RMeSP
, eAX
}, 0 },
2510 { "xchgS", { RMeBP
, eAX
}, 0 },
2511 { "xchgS", { RMeSI
, eAX
}, 0 },
2512 { "xchgS", { RMeDI
, eAX
}, 0 },
2514 { "cW{t|}R", { XX
}, 0 },
2515 { "cR{t|}O", { XX
}, 0 },
2516 { X86_64_TABLE (X86_64_9A
) },
2517 { Bad_Opcode
}, /* fwait */
2518 { "pushfT", { XX
}, 0 },
2519 { "popfT", { XX
}, 0 },
2520 { "sahf", { XX
}, 0 },
2521 { "lahf", { XX
}, 0 },
2523 { "mov%LB", { AL
, Ob
}, 0 },
2524 { "mov%LS", { eAX
, Ov
}, 0 },
2525 { "mov%LB", { Ob
, AL
}, 0 },
2526 { "mov%LS", { Ov
, eAX
}, 0 },
2527 { "movs{b|}", { Ybr
, Xb
}, 0 },
2528 { "movs{R|}", { Yvr
, Xv
}, 0 },
2529 { "cmps{b|}", { Xb
, Yb
}, 0 },
2530 { "cmps{R|}", { Xv
, Yv
}, 0 },
2532 { "testB", { AL
, Ib
}, 0 },
2533 { "testS", { eAX
, Iv
}, 0 },
2534 { "stosB", { Ybr
, AL
}, 0 },
2535 { "stosS", { Yvr
, eAX
}, 0 },
2536 { "lodsB", { ALr
, Xb
}, 0 },
2537 { "lodsS", { eAXr
, Xv
}, 0 },
2538 { "scasB", { AL
, Yb
}, 0 },
2539 { "scasS", { eAX
, Yv
}, 0 },
2541 { "movB", { RMAL
, Ib
}, 0 },
2542 { "movB", { RMCL
, Ib
}, 0 },
2543 { "movB", { RMDL
, Ib
}, 0 },
2544 { "movB", { RMBL
, Ib
}, 0 },
2545 { "movB", { RMAH
, Ib
}, 0 },
2546 { "movB", { RMCH
, Ib
}, 0 },
2547 { "movB", { RMDH
, Ib
}, 0 },
2548 { "movB", { RMBH
, Ib
}, 0 },
2550 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2551 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2552 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2553 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2554 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2555 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2556 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2557 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2559 { REG_TABLE (REG_C0
) },
2560 { REG_TABLE (REG_C1
) },
2561 { "retT", { Iw
, BND
}, 0 },
2562 { "retT", { BND
}, 0 },
2563 { X86_64_TABLE (X86_64_C4
) },
2564 { X86_64_TABLE (X86_64_C5
) },
2565 { REG_TABLE (REG_C6
) },
2566 { REG_TABLE (REG_C7
) },
2568 { "enterT", { Iw
, Ib
}, 0 },
2569 { "leaveT", { XX
}, 0 },
2570 { "Jret{|f}P", { Iw
}, 0 },
2571 { "Jret{|f}P", { XX
}, 0 },
2572 { "int3", { XX
}, 0 },
2573 { "int", { Ib
}, 0 },
2574 { X86_64_TABLE (X86_64_CE
) },
2575 { "iret%LP", { XX
}, 0 },
2577 { REG_TABLE (REG_D0
) },
2578 { REG_TABLE (REG_D1
) },
2579 { REG_TABLE (REG_D2
) },
2580 { REG_TABLE (REG_D3
) },
2581 { X86_64_TABLE (X86_64_D4
) },
2582 { X86_64_TABLE (X86_64_D5
) },
2584 { "xlat", { DSBX
}, 0 },
2595 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2596 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2597 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2598 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2599 { "inB", { AL
, Ib
}, 0 },
2600 { "inG", { zAX
, Ib
}, 0 },
2601 { "outB", { Ib
, AL
}, 0 },
2602 { "outG", { Ib
, zAX
}, 0 },
2604 { X86_64_TABLE (X86_64_E8
) },
2605 { X86_64_TABLE (X86_64_E9
) },
2606 { X86_64_TABLE (X86_64_EA
) },
2607 { "jmp", { Jb
, BND
}, 0 },
2608 { "inB", { AL
, indirDX
}, 0 },
2609 { "inG", { zAX
, indirDX
}, 0 },
2610 { "outB", { indirDX
, AL
}, 0 },
2611 { "outG", { indirDX
, zAX
}, 0 },
2613 { Bad_Opcode
}, /* lock prefix */
2614 { "icebp", { XX
}, 0 },
2615 { Bad_Opcode
}, /* repne */
2616 { Bad_Opcode
}, /* repz */
2617 { "hlt", { XX
}, 0 },
2618 { "cmc", { XX
}, 0 },
2619 { REG_TABLE (REG_F6
) },
2620 { REG_TABLE (REG_F7
) },
2622 { "clc", { XX
}, 0 },
2623 { "stc", { XX
}, 0 },
2624 { "cli", { XX
}, 0 },
2625 { "sti", { XX
}, 0 },
2626 { "cld", { XX
}, 0 },
2627 { "std", { XX
}, 0 },
2628 { REG_TABLE (REG_FE
) },
2629 { REG_TABLE (REG_FF
) },
2632 static const struct dis386 dis386_twobyte
[] = {
2634 { REG_TABLE (REG_0F00
) },
2635 { REG_TABLE (REG_0F01
) },
2636 { "larS", { Gv
, Ew
}, 0 },
2637 { "lslS", { Gv
, Ew
}, 0 },
2639 { "syscall", { XX
}, 0 },
2640 { "clts", { XX
}, 0 },
2641 { "sysret%LP", { XX
}, 0 },
2643 { "invd", { XX
}, 0 },
2644 { PREFIX_TABLE (PREFIX_0F09
) },
2646 { "ud2", { XX
}, 0 },
2648 { REG_TABLE (REG_0F0D
) },
2649 { "femms", { XX
}, 0 },
2650 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2652 { PREFIX_TABLE (PREFIX_0F10
) },
2653 { PREFIX_TABLE (PREFIX_0F11
) },
2654 { PREFIX_TABLE (PREFIX_0F12
) },
2655 { MOD_TABLE (MOD_0F13
) },
2656 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2657 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2658 { PREFIX_TABLE (PREFIX_0F16
) },
2659 { MOD_TABLE (MOD_0F17
) },
2661 { REG_TABLE (REG_0F18
) },
2662 { "nopQ", { Ev
}, 0 },
2663 { PREFIX_TABLE (PREFIX_0F1A
) },
2664 { PREFIX_TABLE (PREFIX_0F1B
) },
2665 { PREFIX_TABLE (PREFIX_0F1C
) },
2666 { "nopQ", { Ev
}, 0 },
2667 { PREFIX_TABLE (PREFIX_0F1E
) },
2668 { "nopQ", { Ev
}, 0 },
2670 { "movZ", { Rm
, Cm
}, 0 },
2671 { "movZ", { Rm
, Dm
}, 0 },
2672 { "movZ", { Cm
, Rm
}, 0 },
2673 { "movZ", { Dm
, Rm
}, 0 },
2674 { MOD_TABLE (MOD_0F24
) },
2676 { MOD_TABLE (MOD_0F26
) },
2679 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2680 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2681 { PREFIX_TABLE (PREFIX_0F2A
) },
2682 { PREFIX_TABLE (PREFIX_0F2B
) },
2683 { PREFIX_TABLE (PREFIX_0F2C
) },
2684 { PREFIX_TABLE (PREFIX_0F2D
) },
2685 { PREFIX_TABLE (PREFIX_0F2E
) },
2686 { PREFIX_TABLE (PREFIX_0F2F
) },
2688 { "wrmsr", { XX
}, 0 },
2689 { "rdtsc", { XX
}, 0 },
2690 { "rdmsr", { XX
}, 0 },
2691 { "rdpmc", { XX
}, 0 },
2692 { "sysenter", { XX
}, 0 },
2693 { "sysexit", { XX
}, 0 },
2695 { "getsec", { XX
}, 0 },
2697 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2699 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2706 { "cmovoS", { Gv
, Ev
}, 0 },
2707 { "cmovnoS", { Gv
, Ev
}, 0 },
2708 { "cmovbS", { Gv
, Ev
}, 0 },
2709 { "cmovaeS", { Gv
, Ev
}, 0 },
2710 { "cmoveS", { Gv
, Ev
}, 0 },
2711 { "cmovneS", { Gv
, Ev
}, 0 },
2712 { "cmovbeS", { Gv
, Ev
}, 0 },
2713 { "cmovaS", { Gv
, Ev
}, 0 },
2715 { "cmovsS", { Gv
, Ev
}, 0 },
2716 { "cmovnsS", { Gv
, Ev
}, 0 },
2717 { "cmovpS", { Gv
, Ev
}, 0 },
2718 { "cmovnpS", { Gv
, Ev
}, 0 },
2719 { "cmovlS", { Gv
, Ev
}, 0 },
2720 { "cmovgeS", { Gv
, Ev
}, 0 },
2721 { "cmovleS", { Gv
, Ev
}, 0 },
2722 { "cmovgS", { Gv
, Ev
}, 0 },
2724 { MOD_TABLE (MOD_0F51
) },
2725 { PREFIX_TABLE (PREFIX_0F51
) },
2726 { PREFIX_TABLE (PREFIX_0F52
) },
2727 { PREFIX_TABLE (PREFIX_0F53
) },
2728 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2729 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2730 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2731 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2733 { PREFIX_TABLE (PREFIX_0F58
) },
2734 { PREFIX_TABLE (PREFIX_0F59
) },
2735 { PREFIX_TABLE (PREFIX_0F5A
) },
2736 { PREFIX_TABLE (PREFIX_0F5B
) },
2737 { PREFIX_TABLE (PREFIX_0F5C
) },
2738 { PREFIX_TABLE (PREFIX_0F5D
) },
2739 { PREFIX_TABLE (PREFIX_0F5E
) },
2740 { PREFIX_TABLE (PREFIX_0F5F
) },
2742 { PREFIX_TABLE (PREFIX_0F60
) },
2743 { PREFIX_TABLE (PREFIX_0F61
) },
2744 { PREFIX_TABLE (PREFIX_0F62
) },
2745 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2746 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2747 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2748 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2749 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2751 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2752 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2753 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2754 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2755 { PREFIX_TABLE (PREFIX_0F6C
) },
2756 { PREFIX_TABLE (PREFIX_0F6D
) },
2757 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2758 { PREFIX_TABLE (PREFIX_0F6F
) },
2760 { PREFIX_TABLE (PREFIX_0F70
) },
2761 { REG_TABLE (REG_0F71
) },
2762 { REG_TABLE (REG_0F72
) },
2763 { REG_TABLE (REG_0F73
) },
2764 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2765 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2766 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2767 { "emms", { XX
}, PREFIX_OPCODE
},
2769 { PREFIX_TABLE (PREFIX_0F78
) },
2770 { PREFIX_TABLE (PREFIX_0F79
) },
2773 { PREFIX_TABLE (PREFIX_0F7C
) },
2774 { PREFIX_TABLE (PREFIX_0F7D
) },
2775 { PREFIX_TABLE (PREFIX_0F7E
) },
2776 { PREFIX_TABLE (PREFIX_0F7F
) },
2778 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2779 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2780 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2781 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2782 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2783 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2784 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2785 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2787 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2788 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2789 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2790 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2791 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2792 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2793 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2794 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2796 { "seto", { Eb
}, 0 },
2797 { "setno", { Eb
}, 0 },
2798 { "setb", { Eb
}, 0 },
2799 { "setae", { Eb
}, 0 },
2800 { "sete", { Eb
}, 0 },
2801 { "setne", { Eb
}, 0 },
2802 { "setbe", { Eb
}, 0 },
2803 { "seta", { Eb
}, 0 },
2805 { "sets", { Eb
}, 0 },
2806 { "setns", { Eb
}, 0 },
2807 { "setp", { Eb
}, 0 },
2808 { "setnp", { Eb
}, 0 },
2809 { "setl", { Eb
}, 0 },
2810 { "setge", { Eb
}, 0 },
2811 { "setle", { Eb
}, 0 },
2812 { "setg", { Eb
}, 0 },
2814 { "pushT", { fs
}, 0 },
2815 { "popT", { fs
}, 0 },
2816 { "cpuid", { XX
}, 0 },
2817 { "btS", { Ev
, Gv
}, 0 },
2818 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2819 { "shldS", { Ev
, Gv
, CL
}, 0 },
2820 { REG_TABLE (REG_0FA6
) },
2821 { REG_TABLE (REG_0FA7
) },
2823 { "pushT", { gs
}, 0 },
2824 { "popT", { gs
}, 0 },
2825 { "rsm", { XX
}, 0 },
2826 { "btsS", { Evh1
, Gv
}, 0 },
2827 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2828 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2829 { REG_TABLE (REG_0FAE
) },
2830 { "imulS", { Gv
, Ev
}, 0 },
2832 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2833 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2834 { MOD_TABLE (MOD_0FB2
) },
2835 { "btrS", { Evh1
, Gv
}, 0 },
2836 { MOD_TABLE (MOD_0FB4
) },
2837 { MOD_TABLE (MOD_0FB5
) },
2838 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2839 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2841 { PREFIX_TABLE (PREFIX_0FB8
) },
2842 { "ud1S", { Gv
, Ev
}, 0 },
2843 { REG_TABLE (REG_0FBA
) },
2844 { "btcS", { Evh1
, Gv
}, 0 },
2845 { PREFIX_TABLE (PREFIX_0FBC
) },
2846 { PREFIX_TABLE (PREFIX_0FBD
) },
2847 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2848 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2850 { "xaddB", { Ebh1
, Gb
}, 0 },
2851 { "xaddS", { Evh1
, Gv
}, 0 },
2852 { PREFIX_TABLE (PREFIX_0FC2
) },
2853 { MOD_TABLE (MOD_0FC3
) },
2854 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
2855 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
2856 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2857 { REG_TABLE (REG_0FC7
) },
2859 { "bswap", { RMeAX
}, 0 },
2860 { "bswap", { RMeCX
}, 0 },
2861 { "bswap", { RMeDX
}, 0 },
2862 { "bswap", { RMeBX
}, 0 },
2863 { "bswap", { RMeSP
}, 0 },
2864 { "bswap", { RMeBP
}, 0 },
2865 { "bswap", { RMeSI
}, 0 },
2866 { "bswap", { RMeDI
}, 0 },
2868 { PREFIX_TABLE (PREFIX_0FD0
) },
2869 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2870 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2871 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2872 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2873 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2874 { PREFIX_TABLE (PREFIX_0FD6
) },
2875 { MOD_TABLE (MOD_0FD7
) },
2877 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2878 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2879 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2880 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2881 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2882 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2883 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2884 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2886 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2887 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2888 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2889 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2890 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2891 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2892 { PREFIX_TABLE (PREFIX_0FE6
) },
2893 { PREFIX_TABLE (PREFIX_0FE7
) },
2895 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
2896 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
2897 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
2898 { "por", { MX
, EM
}, PREFIX_OPCODE
},
2899 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
2900 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
2901 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
2902 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
2904 { PREFIX_TABLE (PREFIX_0FF0
) },
2905 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
2906 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
2907 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
2908 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
2909 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
2910 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
2911 { PREFIX_TABLE (PREFIX_0FF7
) },
2913 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
2914 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
2915 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
2916 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
2917 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
2918 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
2919 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
2920 { "ud0S", { Gv
, Ev
}, 0 },
2923 static const unsigned char onebyte_has_modrm
[256] = {
2924 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2925 /* ------------------------------- */
2926 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2927 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2928 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2929 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2930 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2931 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2932 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2933 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2934 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2935 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2936 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2937 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2938 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2939 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2940 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2941 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2942 /* ------------------------------- */
2943 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2946 static const unsigned char twobyte_has_modrm
[256] = {
2947 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2948 /* ------------------------------- */
2949 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2950 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2951 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2952 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2953 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2954 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2955 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2956 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2957 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2958 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2959 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2960 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2961 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2962 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2963 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2964 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2965 /* ------------------------------- */
2966 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2969 static char obuf
[100];
2971 static char *mnemonicendp
;
2972 static char scratchbuf
[100];
2973 static unsigned char *start_codep
;
2974 static unsigned char *insn_codep
;
2975 static unsigned char *codep
;
2976 static unsigned char *end_codep
;
2977 static int last_lock_prefix
;
2978 static int last_repz_prefix
;
2979 static int last_repnz_prefix
;
2980 static int last_data_prefix
;
2981 static int last_addr_prefix
;
2982 static int last_rex_prefix
;
2983 static int last_seg_prefix
;
2984 static int fwait_prefix
;
2985 /* The active segment register prefix. */
2986 static int active_seg_prefix
;
2987 #define MAX_CODE_LENGTH 15
2988 /* We can up to 14 prefixes since the maximum instruction length is
2990 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
2991 static disassemble_info
*the_info
;
2999 static unsigned char need_modrm
;
3009 int register_specifier
;
3016 int mask_register_specifier
;
3022 static unsigned char need_vex
;
3023 static unsigned char need_vex_reg
;
3024 static unsigned char vex_w_done
;
3032 /* If we are accessing mod/rm/reg without need_modrm set, then the
3033 values are stale. Hitting this abort likely indicates that you
3034 need to update onebyte_has_modrm or twobyte_has_modrm. */
3035 #define MODRM_CHECK if (!need_modrm) abort ()
3037 static const char **names64
;
3038 static const char **names32
;
3039 static const char **names16
;
3040 static const char **names8
;
3041 static const char **names8rex
;
3042 static const char **names_seg
;
3043 static const char *index64
;
3044 static const char *index32
;
3045 static const char **index16
;
3046 static const char **names_bnd
;
3048 static const char *intel_names64
[] = {
3049 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3050 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3052 static const char *intel_names32
[] = {
3053 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3054 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3056 static const char *intel_names16
[] = {
3057 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3058 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3060 static const char *intel_names8
[] = {
3061 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3063 static const char *intel_names8rex
[] = {
3064 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3065 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3067 static const char *intel_names_seg
[] = {
3068 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3070 static const char *intel_index64
= "riz";
3071 static const char *intel_index32
= "eiz";
3072 static const char *intel_index16
[] = {
3073 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3076 static const char *att_names64
[] = {
3077 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3078 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3080 static const char *att_names32
[] = {
3081 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3082 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3084 static const char *att_names16
[] = {
3085 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3086 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3088 static const char *att_names8
[] = {
3089 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3091 static const char *att_names8rex
[] = {
3092 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3093 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3095 static const char *att_names_seg
[] = {
3096 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3098 static const char *att_index64
= "%riz";
3099 static const char *att_index32
= "%eiz";
3100 static const char *att_index16
[] = {
3101 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3104 static const char **names_mm
;
3105 static const char *intel_names_mm
[] = {
3106 "mm0", "mm1", "mm2", "mm3",
3107 "mm4", "mm5", "mm6", "mm7"
3109 static const char *att_names_mm
[] = {
3110 "%mm0", "%mm1", "%mm2", "%mm3",
3111 "%mm4", "%mm5", "%mm6", "%mm7"
3114 static const char *intel_names_bnd
[] = {
3115 "bnd0", "bnd1", "bnd2", "bnd3"
3118 static const char *att_names_bnd
[] = {
3119 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3122 static const char **names_xmm
;
3123 static const char *intel_names_xmm
[] = {
3124 "xmm0", "xmm1", "xmm2", "xmm3",
3125 "xmm4", "xmm5", "xmm6", "xmm7",
3126 "xmm8", "xmm9", "xmm10", "xmm11",
3127 "xmm12", "xmm13", "xmm14", "xmm15",
3128 "xmm16", "xmm17", "xmm18", "xmm19",
3129 "xmm20", "xmm21", "xmm22", "xmm23",
3130 "xmm24", "xmm25", "xmm26", "xmm27",
3131 "xmm28", "xmm29", "xmm30", "xmm31"
3133 static const char *att_names_xmm
[] = {
3134 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3135 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3136 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3137 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3138 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3139 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3140 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3141 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3144 static const char **names_ymm
;
3145 static const char *intel_names_ymm
[] = {
3146 "ymm0", "ymm1", "ymm2", "ymm3",
3147 "ymm4", "ymm5", "ymm6", "ymm7",
3148 "ymm8", "ymm9", "ymm10", "ymm11",
3149 "ymm12", "ymm13", "ymm14", "ymm15",
3150 "ymm16", "ymm17", "ymm18", "ymm19",
3151 "ymm20", "ymm21", "ymm22", "ymm23",
3152 "ymm24", "ymm25", "ymm26", "ymm27",
3153 "ymm28", "ymm29", "ymm30", "ymm31"
3155 static const char *att_names_ymm
[] = {
3156 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3157 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3158 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3159 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3160 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3161 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3162 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3163 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3166 static const char **names_zmm
;
3167 static const char *intel_names_zmm
[] = {
3168 "zmm0", "zmm1", "zmm2", "zmm3",
3169 "zmm4", "zmm5", "zmm6", "zmm7",
3170 "zmm8", "zmm9", "zmm10", "zmm11",
3171 "zmm12", "zmm13", "zmm14", "zmm15",
3172 "zmm16", "zmm17", "zmm18", "zmm19",
3173 "zmm20", "zmm21", "zmm22", "zmm23",
3174 "zmm24", "zmm25", "zmm26", "zmm27",
3175 "zmm28", "zmm29", "zmm30", "zmm31"
3177 static const char *att_names_zmm
[] = {
3178 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3179 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3180 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3181 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3182 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3183 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3184 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3185 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3188 static const char **names_mask
;
3189 static const char *intel_names_mask
[] = {
3190 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3192 static const char *att_names_mask
[] = {
3193 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3196 static const char *names_rounding
[] =
3204 static const struct dis386 reg_table
[][8] = {
3207 { "addA", { Ebh1
, Ib
}, 0 },
3208 { "orA", { Ebh1
, Ib
}, 0 },
3209 { "adcA", { Ebh1
, Ib
}, 0 },
3210 { "sbbA", { Ebh1
, Ib
}, 0 },
3211 { "andA", { Ebh1
, Ib
}, 0 },
3212 { "subA", { Ebh1
, Ib
}, 0 },
3213 { "xorA", { Ebh1
, Ib
}, 0 },
3214 { "cmpA", { Eb
, Ib
}, 0 },
3218 { "addQ", { Evh1
, Iv
}, 0 },
3219 { "orQ", { Evh1
, Iv
}, 0 },
3220 { "adcQ", { Evh1
, Iv
}, 0 },
3221 { "sbbQ", { Evh1
, Iv
}, 0 },
3222 { "andQ", { Evh1
, Iv
}, 0 },
3223 { "subQ", { Evh1
, Iv
}, 0 },
3224 { "xorQ", { Evh1
, Iv
}, 0 },
3225 { "cmpQ", { Ev
, Iv
}, 0 },
3229 { "addQ", { Evh1
, sIb
}, 0 },
3230 { "orQ", { Evh1
, sIb
}, 0 },
3231 { "adcQ", { Evh1
, sIb
}, 0 },
3232 { "sbbQ", { Evh1
, sIb
}, 0 },
3233 { "andQ", { Evh1
, sIb
}, 0 },
3234 { "subQ", { Evh1
, sIb
}, 0 },
3235 { "xorQ", { Evh1
, sIb
}, 0 },
3236 { "cmpQ", { Ev
, sIb
}, 0 },
3240 { "popU", { stackEv
}, 0 },
3241 { XOP_8F_TABLE (XOP_09
) },
3245 { XOP_8F_TABLE (XOP_09
) },
3249 { "rolA", { Eb
, Ib
}, 0 },
3250 { "rorA", { Eb
, Ib
}, 0 },
3251 { "rclA", { Eb
, Ib
}, 0 },
3252 { "rcrA", { Eb
, Ib
}, 0 },
3253 { "shlA", { Eb
, Ib
}, 0 },
3254 { "shrA", { Eb
, Ib
}, 0 },
3255 { "shlA", { Eb
, Ib
}, 0 },
3256 { "sarA", { Eb
, Ib
}, 0 },
3260 { "rolQ", { Ev
, Ib
}, 0 },
3261 { "rorQ", { Ev
, Ib
}, 0 },
3262 { "rclQ", { Ev
, Ib
}, 0 },
3263 { "rcrQ", { Ev
, Ib
}, 0 },
3264 { "shlQ", { Ev
, Ib
}, 0 },
3265 { "shrQ", { Ev
, Ib
}, 0 },
3266 { "shlQ", { Ev
, Ib
}, 0 },
3267 { "sarQ", { Ev
, Ib
}, 0 },
3271 { "movA", { Ebh3
, Ib
}, 0 },
3278 { MOD_TABLE (MOD_C6_REG_7
) },
3282 { "movQ", { Evh3
, Iv
}, 0 },
3289 { MOD_TABLE (MOD_C7_REG_7
) },
3293 { "rolA", { Eb
, I1
}, 0 },
3294 { "rorA", { Eb
, I1
}, 0 },
3295 { "rclA", { Eb
, I1
}, 0 },
3296 { "rcrA", { Eb
, I1
}, 0 },
3297 { "shlA", { Eb
, I1
}, 0 },
3298 { "shrA", { Eb
, I1
}, 0 },
3299 { "shlA", { Eb
, I1
}, 0 },
3300 { "sarA", { Eb
, I1
}, 0 },
3304 { "rolQ", { Ev
, I1
}, 0 },
3305 { "rorQ", { Ev
, I1
}, 0 },
3306 { "rclQ", { Ev
, I1
}, 0 },
3307 { "rcrQ", { Ev
, I1
}, 0 },
3308 { "shlQ", { Ev
, I1
}, 0 },
3309 { "shrQ", { Ev
, I1
}, 0 },
3310 { "shlQ", { Ev
, I1
}, 0 },
3311 { "sarQ", { Ev
, I1
}, 0 },
3315 { "rolA", { Eb
, CL
}, 0 },
3316 { "rorA", { Eb
, CL
}, 0 },
3317 { "rclA", { Eb
, CL
}, 0 },
3318 { "rcrA", { Eb
, CL
}, 0 },
3319 { "shlA", { Eb
, CL
}, 0 },
3320 { "shrA", { Eb
, CL
}, 0 },
3321 { "shlA", { Eb
, CL
}, 0 },
3322 { "sarA", { Eb
, CL
}, 0 },
3326 { "rolQ", { Ev
, CL
}, 0 },
3327 { "rorQ", { Ev
, CL
}, 0 },
3328 { "rclQ", { Ev
, CL
}, 0 },
3329 { "rcrQ", { Ev
, CL
}, 0 },
3330 { "shlQ", { Ev
, CL
}, 0 },
3331 { "shrQ", { Ev
, CL
}, 0 },
3332 { "shlQ", { Ev
, CL
}, 0 },
3333 { "sarQ", { Ev
, CL
}, 0 },
3337 { "testA", { Eb
, Ib
}, 0 },
3338 { "testA", { Eb
, Ib
}, 0 },
3339 { "notA", { Ebh1
}, 0 },
3340 { "negA", { Ebh1
}, 0 },
3341 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3342 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3343 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3344 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3348 { "testQ", { Ev
, Iv
}, 0 },
3349 { "testQ", { Ev
, Iv
}, 0 },
3350 { "notQ", { Evh1
}, 0 },
3351 { "negQ", { Evh1
}, 0 },
3352 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3353 { "imulQ", { Ev
}, 0 },
3354 { "divQ", { Ev
}, 0 },
3355 { "idivQ", { Ev
}, 0 },
3359 { "incA", { Ebh1
}, 0 },
3360 { "decA", { Ebh1
}, 0 },
3364 { "incQ", { Evh1
}, 0 },
3365 { "decQ", { Evh1
}, 0 },
3366 { "call{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3367 { MOD_TABLE (MOD_FF_REG_3
) },
3368 { "jmp{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3369 { MOD_TABLE (MOD_FF_REG_5
) },
3370 { "pushU", { stackEv
}, 0 },
3375 { "sldtD", { Sv
}, 0 },
3376 { "strD", { Sv
}, 0 },
3377 { "lldt", { Ew
}, 0 },
3378 { "ltr", { Ew
}, 0 },
3379 { "verr", { Ew
}, 0 },
3380 { "verw", { Ew
}, 0 },
3386 { MOD_TABLE (MOD_0F01_REG_0
) },
3387 { MOD_TABLE (MOD_0F01_REG_1
) },
3388 { MOD_TABLE (MOD_0F01_REG_2
) },
3389 { MOD_TABLE (MOD_0F01_REG_3
) },
3390 { "smswD", { Sv
}, 0 },
3391 { MOD_TABLE (MOD_0F01_REG_5
) },
3392 { "lmsw", { Ew
}, 0 },
3393 { MOD_TABLE (MOD_0F01_REG_7
) },
3397 { "prefetch", { Mb
}, 0 },
3398 { "prefetchw", { Mb
}, 0 },
3399 { "prefetchwt1", { Mb
}, 0 },
3400 { "prefetch", { Mb
}, 0 },
3401 { "prefetch", { Mb
}, 0 },
3402 { "prefetch", { Mb
}, 0 },
3403 { "prefetch", { Mb
}, 0 },
3404 { "prefetch", { Mb
}, 0 },
3408 { MOD_TABLE (MOD_0F18_REG_0
) },
3409 { MOD_TABLE (MOD_0F18_REG_1
) },
3410 { MOD_TABLE (MOD_0F18_REG_2
) },
3411 { MOD_TABLE (MOD_0F18_REG_3
) },
3412 { MOD_TABLE (MOD_0F18_REG_4
) },
3413 { MOD_TABLE (MOD_0F18_REG_5
) },
3414 { MOD_TABLE (MOD_0F18_REG_6
) },
3415 { MOD_TABLE (MOD_0F18_REG_7
) },
3417 /* REG_0F1C_MOD_0 */
3419 { "cldemote", { Mb
}, 0 },
3420 { "nopQ", { Ev
}, 0 },
3421 { "nopQ", { Ev
}, 0 },
3422 { "nopQ", { Ev
}, 0 },
3423 { "nopQ", { Ev
}, 0 },
3424 { "nopQ", { Ev
}, 0 },
3425 { "nopQ", { Ev
}, 0 },
3426 { "nopQ", { Ev
}, 0 },
3428 /* REG_0F1E_MOD_3 */
3430 { "nopQ", { Ev
}, 0 },
3431 { "rdsspK", { Rdq
}, PREFIX_OPCODE
},
3432 { "nopQ", { Ev
}, 0 },
3433 { "nopQ", { Ev
}, 0 },
3434 { "nopQ", { Ev
}, 0 },
3435 { "nopQ", { Ev
}, 0 },
3436 { "nopQ", { Ev
}, 0 },
3437 { RM_TABLE (RM_0F1E_MOD_3_REG_7
) },
3443 { MOD_TABLE (MOD_0F71_REG_2
) },
3445 { MOD_TABLE (MOD_0F71_REG_4
) },
3447 { MOD_TABLE (MOD_0F71_REG_6
) },
3453 { MOD_TABLE (MOD_0F72_REG_2
) },
3455 { MOD_TABLE (MOD_0F72_REG_4
) },
3457 { MOD_TABLE (MOD_0F72_REG_6
) },
3463 { MOD_TABLE (MOD_0F73_REG_2
) },
3464 { MOD_TABLE (MOD_0F73_REG_3
) },
3467 { MOD_TABLE (MOD_0F73_REG_6
) },
3468 { MOD_TABLE (MOD_0F73_REG_7
) },
3472 { "montmul", { { OP_0f07
, 0 } }, 0 },
3473 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3474 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3478 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3479 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3480 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3481 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3482 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3483 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3487 { MOD_TABLE (MOD_0FAE_REG_0
) },
3488 { MOD_TABLE (MOD_0FAE_REG_1
) },
3489 { MOD_TABLE (MOD_0FAE_REG_2
) },
3490 { MOD_TABLE (MOD_0FAE_REG_3
) },
3491 { MOD_TABLE (MOD_0FAE_REG_4
) },
3492 { MOD_TABLE (MOD_0FAE_REG_5
) },
3493 { MOD_TABLE (MOD_0FAE_REG_6
) },
3494 { MOD_TABLE (MOD_0FAE_REG_7
) },
3502 { "btQ", { Ev
, Ib
}, 0 },
3503 { "btsQ", { Evh1
, Ib
}, 0 },
3504 { "btrQ", { Evh1
, Ib
}, 0 },
3505 { "btcQ", { Evh1
, Ib
}, 0 },
3510 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3512 { MOD_TABLE (MOD_0FC7_REG_3
) },
3513 { MOD_TABLE (MOD_0FC7_REG_4
) },
3514 { MOD_TABLE (MOD_0FC7_REG_5
) },
3515 { MOD_TABLE (MOD_0FC7_REG_6
) },
3516 { MOD_TABLE (MOD_0FC7_REG_7
) },
3522 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3524 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3526 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3532 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3534 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3536 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3542 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3543 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3546 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3547 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3553 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3554 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3556 /* REG_VEX_0F38F3 */
3559 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3560 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3561 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3565 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3566 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3570 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3571 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3573 /* REG_XOP_TBM_01 */
3576 { "blcfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3577 { "blsfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3578 { "blcs", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3579 { "tzmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3580 { "blcic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3581 { "blsic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3582 { "t1mskc", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3584 /* REG_XOP_TBM_02 */
3587 { "blcmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3592 { "blci", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3594 #define NEED_REG_TABLE
3595 #include "i386-dis-evex.h"
3596 #undef NEED_REG_TABLE
3599 static const struct dis386 prefix_table
[][4] = {
3602 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3603 { "pause", { XX
}, 0 },
3604 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3605 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3608 /* PREFIX_MOD_0_0F01_REG_5 */
3611 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3614 /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3617 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3620 /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3623 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3628 { "wbinvd", { XX
}, 0 },
3629 { "wbnoinvd", { XX
}, 0 },
3634 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3635 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3636 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3637 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3642 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3643 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3644 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3645 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3650 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3651 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3652 { "movlpd", { XM
, EXq
}, PREFIX_OPCODE
},
3653 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3658 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3659 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3660 { "movhpd", { XM
, EXq
}, PREFIX_OPCODE
},
3665 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3666 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3667 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3668 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3673 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3674 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3675 { "bndmov", { EbndS
, Gbnd
}, 0 },
3676 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3681 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3682 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3683 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3684 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3689 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3690 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3691 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3692 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3697 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3698 { "cvtsi2ss%LQ", { XM
, Ev
}, PREFIX_OPCODE
},
3699 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3700 { "cvtsi2sd%LQ", { XM
, Ev
}, 0 },
3705 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3706 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3707 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3708 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3713 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3714 { "cvttss2si", { Gv
, EXd
}, PREFIX_OPCODE
},
3715 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3716 { "cvttsd2si", { Gv
, EXq
}, PREFIX_OPCODE
},
3721 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3722 { "cvtss2si", { Gv
, EXd
}, PREFIX_OPCODE
},
3723 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3724 { "cvtsd2si", { Gv
, EXq
}, PREFIX_OPCODE
},
3729 { "ucomiss",{ XM
, EXd
}, 0 },
3731 { "ucomisd",{ XM
, EXq
}, 0 },
3736 { "comiss", { XM
, EXd
}, 0 },
3738 { "comisd", { XM
, EXq
}, 0 },
3743 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3744 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3745 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3746 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3751 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3752 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3757 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3758 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3763 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3764 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3765 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3766 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3771 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3772 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3773 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3774 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3779 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3780 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3781 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3782 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3787 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3788 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3789 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3794 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3795 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3796 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3797 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3802 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3803 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3804 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3805 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3810 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3811 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3812 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3813 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3818 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3819 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3820 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3821 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3826 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3828 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3833 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3835 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3840 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3842 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3849 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3856 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3861 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3862 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3863 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3868 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3869 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3870 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3871 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3874 /* PREFIX_0F73_REG_3 */
3878 { "psrldq", { XS
, Ib
}, 0 },
3881 /* PREFIX_0F73_REG_7 */
3885 { "pslldq", { XS
, Ib
}, 0 },
3890 {"vmread", { Em
, Gm
}, 0 },
3892 {"extrq", { XS
, Ib
, Ib
}, 0 },
3893 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3898 {"vmwrite", { Gm
, Em
}, 0 },
3900 {"extrq", { XM
, XS
}, 0 },
3901 {"insertq", { XM
, XS
}, 0 },
3908 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3909 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3916 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3917 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3922 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3923 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3924 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3929 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3930 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3931 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3934 /* PREFIX_0FAE_REG_0 */
3937 { "rdfsbase", { Ev
}, 0 },
3940 /* PREFIX_0FAE_REG_1 */
3943 { "rdgsbase", { Ev
}, 0 },
3946 /* PREFIX_0FAE_REG_2 */
3949 { "wrfsbase", { Ev
}, 0 },
3952 /* PREFIX_0FAE_REG_3 */
3955 { "wrgsbase", { Ev
}, 0 },
3958 /* PREFIX_MOD_0_0FAE_REG_4 */
3960 { "xsave", { FXSAVE
}, 0 },
3961 { "ptwrite%LQ", { Edq
}, 0 },
3964 /* PREFIX_MOD_3_0FAE_REG_4 */
3967 { "ptwrite%LQ", { Edq
}, 0 },
3970 /* PREFIX_MOD_0_0FAE_REG_5 */
3972 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
3975 /* PREFIX_MOD_3_0FAE_REG_5 */
3977 { "lfence", { Skip_MODRM
}, 0 },
3978 { "incsspK", { Rdq
}, PREFIX_OPCODE
},
3981 /* PREFIX_MOD_0_0FAE_REG_6 */
3983 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
3984 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
3985 { "clwb", { Mb
}, PREFIX_OPCODE
},
3988 /* PREFIX_MOD_1_0FAE_REG_6 */
3990 { RM_TABLE (RM_0FAE_REG_6
) },
3991 { "umonitor", { Eva
}, PREFIX_OPCODE
},
3992 { "tpause", { Edq
}, PREFIX_OPCODE
},
3993 { "umwait", { Edq
}, PREFIX_OPCODE
},
3996 /* PREFIX_0FAE_REG_7 */
3998 { "clflush", { Mb
}, 0 },
4000 { "clflushopt", { Mb
}, 0 },
4006 { "popcntS", { Gv
, Ev
}, 0 },
4011 { "bsfS", { Gv
, Ev
}, 0 },
4012 { "tzcntS", { Gv
, Ev
}, 0 },
4013 { "bsfS", { Gv
, Ev
}, 0 },
4018 { "bsrS", { Gv
, Ev
}, 0 },
4019 { "lzcntS", { Gv
, Ev
}, 0 },
4020 { "bsrS", { Gv
, Ev
}, 0 },
4025 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4026 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4027 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4028 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4031 /* PREFIX_MOD_0_0FC3 */
4033 { "movntiS", { Ev
, Gv
}, PREFIX_OPCODE
},
4036 /* PREFIX_MOD_0_0FC7_REG_6 */
4038 { "vmptrld",{ Mq
}, 0 },
4039 { "vmxon", { Mq
}, 0 },
4040 { "vmclear",{ Mq
}, 0 },
4043 /* PREFIX_MOD_3_0FC7_REG_6 */
4045 { "rdrand", { Ev
}, 0 },
4047 { "rdrand", { Ev
}, 0 }
4050 /* PREFIX_MOD_3_0FC7_REG_7 */
4052 { "rdseed", { Ev
}, 0 },
4053 { "rdpid", { Em
}, 0 },
4054 { "rdseed", { Ev
}, 0 },
4061 { "addsubpd", { XM
, EXx
}, 0 },
4062 { "addsubps", { XM
, EXx
}, 0 },
4068 { "movq2dq",{ XM
, MS
}, 0 },
4069 { "movq", { EXqS
, XM
}, 0 },
4070 { "movdq2q",{ MX
, XS
}, 0 },
4076 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4077 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4078 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4083 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4085 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4093 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4098 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4100 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4107 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4114 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4121 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4128 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4135 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4142 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4149 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4156 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4163 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4170 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4177 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4184 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4191 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4198 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4205 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4212 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4219 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4226 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4233 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4240 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4247 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4254 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4261 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4268 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4275 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4282 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4289 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4296 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4303 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4310 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4317 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4324 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4331 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4338 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4343 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4348 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4353 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4358 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4363 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4368 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4375 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_OPCODE
},
4382 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4389 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4396 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4403 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4410 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4415 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4417 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4418 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4423 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4425 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4426 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4433 { MOD_TABLE (MOD_0F38F5_PREFIX_2
) },
4438 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
4439 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4440 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4448 { MOD_TABLE (MOD_0F38F8_PREFIX_2
) },
4453 { MOD_TABLE (MOD_0F38F9_PREFIX_0
) },
4460 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4467 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4474 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4481 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4488 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4495 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4502 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4509 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4516 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4523 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4530 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4537 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4544 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4551 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4558 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4565 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4572 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4579 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4586 { "pcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4593 { "pcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4600 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4607 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4612 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4619 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4626 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4633 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4636 /* PREFIX_VEX_0F10 */
4638 { "vmovups", { XM
, EXx
}, 0 },
4639 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
}, 0 },
4640 { "vmovupd", { XM
, EXx
}, 0 },
4641 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
}, 0 },
4644 /* PREFIX_VEX_0F11 */
4646 { "vmovups", { EXxS
, XM
}, 0 },
4647 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
4648 { "vmovupd", { EXxS
, XM
}, 0 },
4649 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
4652 /* PREFIX_VEX_0F12 */
4654 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4655 { "vmovsldup", { XM
, EXx
}, 0 },
4656 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4657 { "vmovddup", { XM
, EXymmq
}, 0 },
4660 /* PREFIX_VEX_0F16 */
4662 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4663 { "vmovshdup", { XM
, EXx
}, 0 },
4664 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4667 /* PREFIX_VEX_0F2A */
4670 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1
) },
4672 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3
) },
4675 /* PREFIX_VEX_0F2C */
4678 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1
) },
4680 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3
) },
4683 /* PREFIX_VEX_0F2D */
4686 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1
) },
4688 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3
) },
4691 /* PREFIX_VEX_0F2E */
4693 { "vucomiss", { XMScalar
, EXdScalar
}, 0 },
4695 { "vucomisd", { XMScalar
, EXqScalar
}, 0 },
4698 /* PREFIX_VEX_0F2F */
4700 { "vcomiss", { XMScalar
, EXdScalar
}, 0 },
4702 { "vcomisd", { XMScalar
, EXqScalar
}, 0 },
4705 /* PREFIX_VEX_0F41 */
4707 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4709 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4712 /* PREFIX_VEX_0F42 */
4714 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4716 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4719 /* PREFIX_VEX_0F44 */
4721 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4723 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4726 /* PREFIX_VEX_0F45 */
4728 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4730 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4733 /* PREFIX_VEX_0F46 */
4735 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4737 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4740 /* PREFIX_VEX_0F47 */
4742 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4744 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4747 /* PREFIX_VEX_0F4A */
4749 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4751 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4754 /* PREFIX_VEX_0F4B */
4756 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4758 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4761 /* PREFIX_VEX_0F51 */
4763 { "vsqrtps", { XM
, EXx
}, 0 },
4764 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4765 { "vsqrtpd", { XM
, EXx
}, 0 },
4766 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4769 /* PREFIX_VEX_0F52 */
4771 { "vrsqrtps", { XM
, EXx
}, 0 },
4772 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4775 /* PREFIX_VEX_0F53 */
4777 { "vrcpps", { XM
, EXx
}, 0 },
4778 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4781 /* PREFIX_VEX_0F58 */
4783 { "vaddps", { XM
, Vex
, EXx
}, 0 },
4784 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4785 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
4786 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4789 /* PREFIX_VEX_0F59 */
4791 { "vmulps", { XM
, Vex
, EXx
}, 0 },
4792 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4793 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
4794 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4797 /* PREFIX_VEX_0F5A */
4799 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
4800 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4801 { "vcvtpd2ps%XY",{ XMM
, EXx
}, 0 },
4802 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4805 /* PREFIX_VEX_0F5B */
4807 { "vcvtdq2ps", { XM
, EXx
}, 0 },
4808 { "vcvttps2dq", { XM
, EXx
}, 0 },
4809 { "vcvtps2dq", { XM
, EXx
}, 0 },
4812 /* PREFIX_VEX_0F5C */
4814 { "vsubps", { XM
, Vex
, EXx
}, 0 },
4815 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4816 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
4817 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4820 /* PREFIX_VEX_0F5D */
4822 { "vminps", { XM
, Vex
, EXx
}, 0 },
4823 { "vminss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4824 { "vminpd", { XM
, Vex
, EXx
}, 0 },
4825 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4828 /* PREFIX_VEX_0F5E */
4830 { "vdivps", { XM
, Vex
, EXx
}, 0 },
4831 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4832 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
4833 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4836 /* PREFIX_VEX_0F5F */
4838 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
4839 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4840 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
4841 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4844 /* PREFIX_VEX_0F60 */
4848 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
4851 /* PREFIX_VEX_0F61 */
4855 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
4858 /* PREFIX_VEX_0F62 */
4862 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
4865 /* PREFIX_VEX_0F63 */
4869 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
4872 /* PREFIX_VEX_0F64 */
4876 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
4879 /* PREFIX_VEX_0F65 */
4883 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
4886 /* PREFIX_VEX_0F66 */
4890 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
4893 /* PREFIX_VEX_0F67 */
4897 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
4900 /* PREFIX_VEX_0F68 */
4904 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
4907 /* PREFIX_VEX_0F69 */
4911 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
4914 /* PREFIX_VEX_0F6A */
4918 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
4921 /* PREFIX_VEX_0F6B */
4925 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
4928 /* PREFIX_VEX_0F6C */
4932 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
4935 /* PREFIX_VEX_0F6D */
4939 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
4942 /* PREFIX_VEX_0F6E */
4946 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4949 /* PREFIX_VEX_0F6F */
4952 { "vmovdqu", { XM
, EXx
}, 0 },
4953 { "vmovdqa", { XM
, EXx
}, 0 },
4956 /* PREFIX_VEX_0F70 */
4959 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
4960 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
4961 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
4964 /* PREFIX_VEX_0F71_REG_2 */
4968 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
4971 /* PREFIX_VEX_0F71_REG_4 */
4975 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
4978 /* PREFIX_VEX_0F71_REG_6 */
4982 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
4985 /* PREFIX_VEX_0F72_REG_2 */
4989 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
4992 /* PREFIX_VEX_0F72_REG_4 */
4996 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
4999 /* PREFIX_VEX_0F72_REG_6 */
5003 { "vpslld", { Vex
, XS
, Ib
}, 0 },
5006 /* PREFIX_VEX_0F73_REG_2 */
5010 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
5013 /* PREFIX_VEX_0F73_REG_3 */
5017 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
5020 /* PREFIX_VEX_0F73_REG_6 */
5024 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
5027 /* PREFIX_VEX_0F73_REG_7 */
5031 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
5034 /* PREFIX_VEX_0F74 */
5038 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
5041 /* PREFIX_VEX_0F75 */
5045 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
5048 /* PREFIX_VEX_0F76 */
5052 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
5055 /* PREFIX_VEX_0F77 */
5057 { VEX_LEN_TABLE (VEX_LEN_0F77_P_0
) },
5060 /* PREFIX_VEX_0F7C */
5064 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
5065 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
5068 /* PREFIX_VEX_0F7D */
5072 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
5073 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
5076 /* PREFIX_VEX_0F7E */
5079 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5080 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5083 /* PREFIX_VEX_0F7F */
5086 { "vmovdqu", { EXxS
, XM
}, 0 },
5087 { "vmovdqa", { EXxS
, XM
}, 0 },
5090 /* PREFIX_VEX_0F90 */
5092 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5094 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5097 /* PREFIX_VEX_0F91 */
5099 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5101 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5104 /* PREFIX_VEX_0F92 */
5106 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5108 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5109 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5112 /* PREFIX_VEX_0F93 */
5114 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5116 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5117 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5120 /* PREFIX_VEX_0F98 */
5122 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5124 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5127 /* PREFIX_VEX_0F99 */
5129 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5131 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5134 /* PREFIX_VEX_0FC2 */
5136 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
5137 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
}, 0 },
5138 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
5139 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
}, 0 },
5142 /* PREFIX_VEX_0FC4 */
5146 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5149 /* PREFIX_VEX_0FC5 */
5153 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5156 /* PREFIX_VEX_0FD0 */
5160 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
5161 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
5164 /* PREFIX_VEX_0FD1 */
5168 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
5171 /* PREFIX_VEX_0FD2 */
5175 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
5178 /* PREFIX_VEX_0FD3 */
5182 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
5185 /* PREFIX_VEX_0FD4 */
5189 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
5192 /* PREFIX_VEX_0FD5 */
5196 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
5199 /* PREFIX_VEX_0FD6 */
5203 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5206 /* PREFIX_VEX_0FD7 */
5210 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5213 /* PREFIX_VEX_0FD8 */
5217 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
5220 /* PREFIX_VEX_0FD9 */
5224 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
5227 /* PREFIX_VEX_0FDA */
5231 { "vpminub", { XM
, Vex
, EXx
}, 0 },
5234 /* PREFIX_VEX_0FDB */
5238 { "vpand", { XM
, Vex
, EXx
}, 0 },
5241 /* PREFIX_VEX_0FDC */
5245 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
5248 /* PREFIX_VEX_0FDD */
5252 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
5255 /* PREFIX_VEX_0FDE */
5259 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
5262 /* PREFIX_VEX_0FDF */
5266 { "vpandn", { XM
, Vex
, EXx
}, 0 },
5269 /* PREFIX_VEX_0FE0 */
5273 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
5276 /* PREFIX_VEX_0FE1 */
5280 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
5283 /* PREFIX_VEX_0FE2 */
5287 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
5290 /* PREFIX_VEX_0FE3 */
5294 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
5297 /* PREFIX_VEX_0FE4 */
5301 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
5304 /* PREFIX_VEX_0FE5 */
5308 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
5311 /* PREFIX_VEX_0FE6 */
5314 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
5315 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
5316 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
5319 /* PREFIX_VEX_0FE7 */
5323 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5326 /* PREFIX_VEX_0FE8 */
5330 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
5333 /* PREFIX_VEX_0FE9 */
5337 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
5340 /* PREFIX_VEX_0FEA */
5344 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
5347 /* PREFIX_VEX_0FEB */
5351 { "vpor", { XM
, Vex
, EXx
}, 0 },
5354 /* PREFIX_VEX_0FEC */
5358 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
5361 /* PREFIX_VEX_0FED */
5365 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
5368 /* PREFIX_VEX_0FEE */
5372 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
5375 /* PREFIX_VEX_0FEF */
5379 { "vpxor", { XM
, Vex
, EXx
}, 0 },
5382 /* PREFIX_VEX_0FF0 */
5387 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5390 /* PREFIX_VEX_0FF1 */
5394 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
5397 /* PREFIX_VEX_0FF2 */
5401 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
5404 /* PREFIX_VEX_0FF3 */
5408 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
5411 /* PREFIX_VEX_0FF4 */
5415 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
5418 /* PREFIX_VEX_0FF5 */
5422 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
5425 /* PREFIX_VEX_0FF6 */
5429 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
5432 /* PREFIX_VEX_0FF7 */
5436 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5439 /* PREFIX_VEX_0FF8 */
5443 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
5446 /* PREFIX_VEX_0FF9 */
5450 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
5453 /* PREFIX_VEX_0FFA */
5457 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
5460 /* PREFIX_VEX_0FFB */
5464 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
5467 /* PREFIX_VEX_0FFC */
5471 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
5474 /* PREFIX_VEX_0FFD */
5478 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
5481 /* PREFIX_VEX_0FFE */
5485 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
5488 /* PREFIX_VEX_0F3800 */
5492 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
5495 /* PREFIX_VEX_0F3801 */
5499 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
5502 /* PREFIX_VEX_0F3802 */
5506 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
5509 /* PREFIX_VEX_0F3803 */
5513 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
5516 /* PREFIX_VEX_0F3804 */
5520 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
5523 /* PREFIX_VEX_0F3805 */
5527 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
5530 /* PREFIX_VEX_0F3806 */
5534 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
5537 /* PREFIX_VEX_0F3807 */
5541 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
5544 /* PREFIX_VEX_0F3808 */
5548 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
5551 /* PREFIX_VEX_0F3809 */
5555 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
5558 /* PREFIX_VEX_0F380A */
5562 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
5565 /* PREFIX_VEX_0F380B */
5569 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
5572 /* PREFIX_VEX_0F380C */
5576 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5579 /* PREFIX_VEX_0F380D */
5583 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5586 /* PREFIX_VEX_0F380E */
5590 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5593 /* PREFIX_VEX_0F380F */
5597 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5600 /* PREFIX_VEX_0F3813 */
5604 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
5607 /* PREFIX_VEX_0F3816 */
5611 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5614 /* PREFIX_VEX_0F3817 */
5618 { "vptest", { XM
, EXx
}, 0 },
5621 /* PREFIX_VEX_0F3818 */
5625 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5628 /* PREFIX_VEX_0F3819 */
5632 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5635 /* PREFIX_VEX_0F381A */
5639 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5642 /* PREFIX_VEX_0F381C */
5646 { "vpabsb", { XM
, EXx
}, 0 },
5649 /* PREFIX_VEX_0F381D */
5653 { "vpabsw", { XM
, EXx
}, 0 },
5656 /* PREFIX_VEX_0F381E */
5660 { "vpabsd", { XM
, EXx
}, 0 },
5663 /* PREFIX_VEX_0F3820 */
5667 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
5670 /* PREFIX_VEX_0F3821 */
5674 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
5677 /* PREFIX_VEX_0F3822 */
5681 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
5684 /* PREFIX_VEX_0F3823 */
5688 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
5691 /* PREFIX_VEX_0F3824 */
5695 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
5698 /* PREFIX_VEX_0F3825 */
5702 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
5705 /* PREFIX_VEX_0F3828 */
5709 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
5712 /* PREFIX_VEX_0F3829 */
5716 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
5719 /* PREFIX_VEX_0F382A */
5723 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5726 /* PREFIX_VEX_0F382B */
5730 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
5733 /* PREFIX_VEX_0F382C */
5737 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5740 /* PREFIX_VEX_0F382D */
5744 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5747 /* PREFIX_VEX_0F382E */
5751 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5754 /* PREFIX_VEX_0F382F */
5758 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5761 /* PREFIX_VEX_0F3830 */
5765 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
5768 /* PREFIX_VEX_0F3831 */
5772 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
5775 /* PREFIX_VEX_0F3832 */
5779 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
5782 /* PREFIX_VEX_0F3833 */
5786 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
5789 /* PREFIX_VEX_0F3834 */
5793 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
5796 /* PREFIX_VEX_0F3835 */
5800 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
5803 /* PREFIX_VEX_0F3836 */
5807 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5810 /* PREFIX_VEX_0F3837 */
5814 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
5817 /* PREFIX_VEX_0F3838 */
5821 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
5824 /* PREFIX_VEX_0F3839 */
5828 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
5831 /* PREFIX_VEX_0F383A */
5835 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
5838 /* PREFIX_VEX_0F383B */
5842 { "vpminud", { XM
, Vex
, EXx
}, 0 },
5845 /* PREFIX_VEX_0F383C */
5849 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
5852 /* PREFIX_VEX_0F383D */
5856 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
5859 /* PREFIX_VEX_0F383E */
5863 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
5866 /* PREFIX_VEX_0F383F */
5870 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
5873 /* PREFIX_VEX_0F3840 */
5877 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
5880 /* PREFIX_VEX_0F3841 */
5884 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5887 /* PREFIX_VEX_0F3845 */
5891 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
5894 /* PREFIX_VEX_0F3846 */
5898 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5901 /* PREFIX_VEX_0F3847 */
5905 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
5908 /* PREFIX_VEX_0F3858 */
5912 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5915 /* PREFIX_VEX_0F3859 */
5919 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5922 /* PREFIX_VEX_0F385A */
5926 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5929 /* PREFIX_VEX_0F3878 */
5933 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5936 /* PREFIX_VEX_0F3879 */
5940 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5943 /* PREFIX_VEX_0F388C */
5947 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5950 /* PREFIX_VEX_0F388E */
5954 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
5957 /* PREFIX_VEX_0F3890 */
5961 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5964 /* PREFIX_VEX_0F3891 */
5968 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
5971 /* PREFIX_VEX_0F3892 */
5975 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5978 /* PREFIX_VEX_0F3893 */
5982 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
5985 /* PREFIX_VEX_0F3896 */
5989 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, 0 },
5992 /* PREFIX_VEX_0F3897 */
5996 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, 0 },
5999 /* PREFIX_VEX_0F3898 */
6003 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6006 /* PREFIX_VEX_0F3899 */
6010 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6013 /* PREFIX_VEX_0F389A */
6017 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6020 /* PREFIX_VEX_0F389B */
6024 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6027 /* PREFIX_VEX_0F389C */
6031 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6034 /* PREFIX_VEX_0F389D */
6038 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6041 /* PREFIX_VEX_0F389E */
6045 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6048 /* PREFIX_VEX_0F389F */
6052 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6055 /* PREFIX_VEX_0F38A6 */
6059 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6063 /* PREFIX_VEX_0F38A7 */
6067 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6070 /* PREFIX_VEX_0F38A8 */
6074 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6077 /* PREFIX_VEX_0F38A9 */
6081 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6084 /* PREFIX_VEX_0F38AA */
6088 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6091 /* PREFIX_VEX_0F38AB */
6095 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6098 /* PREFIX_VEX_0F38AC */
6102 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6105 /* PREFIX_VEX_0F38AD */
6109 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6112 /* PREFIX_VEX_0F38AE */
6116 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6119 /* PREFIX_VEX_0F38AF */
6123 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6126 /* PREFIX_VEX_0F38B6 */
6130 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6133 /* PREFIX_VEX_0F38B7 */
6137 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6140 /* PREFIX_VEX_0F38B8 */
6144 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6147 /* PREFIX_VEX_0F38B9 */
6151 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6154 /* PREFIX_VEX_0F38BA */
6158 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6161 /* PREFIX_VEX_0F38BB */
6165 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6168 /* PREFIX_VEX_0F38BC */
6172 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6175 /* PREFIX_VEX_0F38BD */
6179 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6182 /* PREFIX_VEX_0F38BE */
6186 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6189 /* PREFIX_VEX_0F38BF */
6193 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6196 /* PREFIX_VEX_0F38CF */
6200 { VEX_W_TABLE (VEX_W_0F38CF_P_2
) },
6203 /* PREFIX_VEX_0F38DB */
6207 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6210 /* PREFIX_VEX_0F38DC */
6214 { "vaesenc", { XM
, Vex
, EXx
}, 0 },
6217 /* PREFIX_VEX_0F38DD */
6221 { "vaesenclast", { XM
, Vex
, EXx
}, 0 },
6224 /* PREFIX_VEX_0F38DE */
6228 { "vaesdec", { XM
, Vex
, EXx
}, 0 },
6231 /* PREFIX_VEX_0F38DF */
6235 { "vaesdeclast", { XM
, Vex
, EXx
}, 0 },
6238 /* PREFIX_VEX_0F38F2 */
6240 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6243 /* PREFIX_VEX_0F38F3_REG_1 */
6245 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6248 /* PREFIX_VEX_0F38F3_REG_2 */
6250 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6253 /* PREFIX_VEX_0F38F3_REG_3 */
6255 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6258 /* PREFIX_VEX_0F38F5 */
6260 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6261 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6263 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6266 /* PREFIX_VEX_0F38F6 */
6271 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6274 /* PREFIX_VEX_0F38F7 */
6276 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6277 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6278 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6279 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6282 /* PREFIX_VEX_0F3A00 */
6286 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6289 /* PREFIX_VEX_0F3A01 */
6293 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6296 /* PREFIX_VEX_0F3A02 */
6300 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6303 /* PREFIX_VEX_0F3A04 */
6307 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6310 /* PREFIX_VEX_0F3A05 */
6314 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6317 /* PREFIX_VEX_0F3A06 */
6321 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6324 /* PREFIX_VEX_0F3A08 */
6328 { "vroundps", { XM
, EXx
, Ib
}, 0 },
6331 /* PREFIX_VEX_0F3A09 */
6335 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
6338 /* PREFIX_VEX_0F3A0A */
6342 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
}, 0 },
6345 /* PREFIX_VEX_0F3A0B */
6349 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
}, 0 },
6352 /* PREFIX_VEX_0F3A0C */
6356 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
6359 /* PREFIX_VEX_0F3A0D */
6363 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
6366 /* PREFIX_VEX_0F3A0E */
6370 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
6373 /* PREFIX_VEX_0F3A0F */
6377 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
6380 /* PREFIX_VEX_0F3A14 */
6384 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6387 /* PREFIX_VEX_0F3A15 */
6391 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6394 /* PREFIX_VEX_0F3A16 */
6398 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6401 /* PREFIX_VEX_0F3A17 */
6405 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6408 /* PREFIX_VEX_0F3A18 */
6412 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6415 /* PREFIX_VEX_0F3A19 */
6419 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6422 /* PREFIX_VEX_0F3A1D */
6426 { "vcvtps2ph", { EXxmmq
, XM
, Ib
}, 0 },
6429 /* PREFIX_VEX_0F3A20 */
6433 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6436 /* PREFIX_VEX_0F3A21 */
6440 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6443 /* PREFIX_VEX_0F3A22 */
6447 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6450 /* PREFIX_VEX_0F3A30 */
6454 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6457 /* PREFIX_VEX_0F3A31 */
6461 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6464 /* PREFIX_VEX_0F3A32 */
6468 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6471 /* PREFIX_VEX_0F3A33 */
6475 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6478 /* PREFIX_VEX_0F3A38 */
6482 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6485 /* PREFIX_VEX_0F3A39 */
6489 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6492 /* PREFIX_VEX_0F3A40 */
6496 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
6499 /* PREFIX_VEX_0F3A41 */
6503 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6506 /* PREFIX_VEX_0F3A42 */
6510 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
6513 /* PREFIX_VEX_0F3A44 */
6517 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, 0 },
6520 /* PREFIX_VEX_0F3A46 */
6524 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6527 /* PREFIX_VEX_0F3A48 */
6531 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6534 /* PREFIX_VEX_0F3A49 */
6538 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6541 /* PREFIX_VEX_0F3A4A */
6545 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6548 /* PREFIX_VEX_0F3A4B */
6552 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6555 /* PREFIX_VEX_0F3A4C */
6559 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6562 /* PREFIX_VEX_0F3A5C */
6566 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6569 /* PREFIX_VEX_0F3A5D */
6573 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6576 /* PREFIX_VEX_0F3A5E */
6580 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6583 /* PREFIX_VEX_0F3A5F */
6587 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6590 /* PREFIX_VEX_0F3A60 */
6594 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6598 /* PREFIX_VEX_0F3A61 */
6602 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6605 /* PREFIX_VEX_0F3A62 */
6609 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6612 /* PREFIX_VEX_0F3A63 */
6616 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6619 /* PREFIX_VEX_0F3A68 */
6623 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6626 /* PREFIX_VEX_0F3A69 */
6630 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6633 /* PREFIX_VEX_0F3A6A */
6637 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6640 /* PREFIX_VEX_0F3A6B */
6644 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6647 /* PREFIX_VEX_0F3A6C */
6651 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6654 /* PREFIX_VEX_0F3A6D */
6658 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6661 /* PREFIX_VEX_0F3A6E */
6665 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6668 /* PREFIX_VEX_0F3A6F */
6672 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6675 /* PREFIX_VEX_0F3A78 */
6679 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6682 /* PREFIX_VEX_0F3A79 */
6686 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6689 /* PREFIX_VEX_0F3A7A */
6693 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6696 /* PREFIX_VEX_0F3A7B */
6700 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6703 /* PREFIX_VEX_0F3A7C */
6707 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6711 /* PREFIX_VEX_0F3A7D */
6715 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6718 /* PREFIX_VEX_0F3A7E */
6722 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6725 /* PREFIX_VEX_0F3A7F */
6729 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6732 /* PREFIX_VEX_0F3ACE */
6736 { VEX_W_TABLE (VEX_W_0F3ACE_P_2
) },
6739 /* PREFIX_VEX_0F3ACF */
6743 { VEX_W_TABLE (VEX_W_0F3ACF_P_2
) },
6746 /* PREFIX_VEX_0F3ADF */
6750 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6753 /* PREFIX_VEX_0F3AF0 */
6758 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6761 #define NEED_PREFIX_TABLE
6762 #include "i386-dis-evex.h"
6763 #undef NEED_PREFIX_TABLE
6766 static const struct dis386 x86_64_table
[][2] = {
6769 { "pushP", { es
}, 0 },
6774 { "popP", { es
}, 0 },
6779 { "pushP", { cs
}, 0 },
6784 { "pushP", { ss
}, 0 },
6789 { "popP", { ss
}, 0 },
6794 { "pushP", { ds
}, 0 },
6799 { "popP", { ds
}, 0 },
6804 { "daa", { XX
}, 0 },
6809 { "das", { XX
}, 0 },
6814 { "aaa", { XX
}, 0 },
6819 { "aas", { XX
}, 0 },
6824 { "pushaP", { XX
}, 0 },
6829 { "popaP", { XX
}, 0 },
6834 { MOD_TABLE (MOD_62_32BIT
) },
6835 { EVEX_TABLE (EVEX_0F
) },
6840 { "arpl", { Ew
, Gw
}, 0 },
6841 { "movs{lq|xd}", { Gv
, Ed
}, 0 },
6846 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6847 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6852 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6853 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6858 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
6859 { REG_TABLE (REG_80
) },
6864 { "Jcall{T|}", { Ap
}, 0 },
6869 { MOD_TABLE (MOD_C4_32BIT
) },
6870 { VEX_C4_TABLE (VEX_0F
) },
6875 { MOD_TABLE (MOD_C5_32BIT
) },
6876 { VEX_C5_TABLE (VEX_0F
) },
6881 { "into", { XX
}, 0 },
6886 { "aam", { Ib
}, 0 },
6891 { "aad", { Ib
}, 0 },
6896 { "callP", { Jv
, BND
}, 0 },
6897 { "call@", { Jv
, BND
}, 0 }
6902 { "jmpP", { Jv
, BND
}, 0 },
6903 { "jmp@", { Jv
, BND
}, 0 }
6908 { "Jjmp{T|}", { Ap
}, 0 },
6911 /* X86_64_0F01_REG_0 */
6913 { "sgdt{Q|IQ}", { M
}, 0 },
6914 { "sgdt", { M
}, 0 },
6917 /* X86_64_0F01_REG_1 */
6919 { "sidt{Q|IQ}", { M
}, 0 },
6920 { "sidt", { M
}, 0 },
6923 /* X86_64_0F01_REG_2 */
6925 { "lgdt{Q|Q}", { M
}, 0 },
6926 { "lgdt", { M
}, 0 },
6929 /* X86_64_0F01_REG_3 */
6931 { "lidt{Q|Q}", { M
}, 0 },
6932 { "lidt", { M
}, 0 },
6936 static const struct dis386 three_byte_table
[][256] = {
6938 /* THREE_BYTE_0F38 */
6941 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
6942 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
6943 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
6944 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
6945 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
6946 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
6947 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
6948 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
6950 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
6951 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
6952 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
6953 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
6959 { PREFIX_TABLE (PREFIX_0F3810
) },
6963 { PREFIX_TABLE (PREFIX_0F3814
) },
6964 { PREFIX_TABLE (PREFIX_0F3815
) },
6966 { PREFIX_TABLE (PREFIX_0F3817
) },
6972 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
6973 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
6974 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
6977 { PREFIX_TABLE (PREFIX_0F3820
) },
6978 { PREFIX_TABLE (PREFIX_0F3821
) },
6979 { PREFIX_TABLE (PREFIX_0F3822
) },
6980 { PREFIX_TABLE (PREFIX_0F3823
) },
6981 { PREFIX_TABLE (PREFIX_0F3824
) },
6982 { PREFIX_TABLE (PREFIX_0F3825
) },
6986 { PREFIX_TABLE (PREFIX_0F3828
) },
6987 { PREFIX_TABLE (PREFIX_0F3829
) },
6988 { PREFIX_TABLE (PREFIX_0F382A
) },
6989 { PREFIX_TABLE (PREFIX_0F382B
) },
6995 { PREFIX_TABLE (PREFIX_0F3830
) },
6996 { PREFIX_TABLE (PREFIX_0F3831
) },
6997 { PREFIX_TABLE (PREFIX_0F3832
) },
6998 { PREFIX_TABLE (PREFIX_0F3833
) },
6999 { PREFIX_TABLE (PREFIX_0F3834
) },
7000 { PREFIX_TABLE (PREFIX_0F3835
) },
7002 { PREFIX_TABLE (PREFIX_0F3837
) },
7004 { PREFIX_TABLE (PREFIX_0F3838
) },
7005 { PREFIX_TABLE (PREFIX_0F3839
) },
7006 { PREFIX_TABLE (PREFIX_0F383A
) },
7007 { PREFIX_TABLE (PREFIX_0F383B
) },
7008 { PREFIX_TABLE (PREFIX_0F383C
) },
7009 { PREFIX_TABLE (PREFIX_0F383D
) },
7010 { PREFIX_TABLE (PREFIX_0F383E
) },
7011 { PREFIX_TABLE (PREFIX_0F383F
) },
7013 { PREFIX_TABLE (PREFIX_0F3840
) },
7014 { PREFIX_TABLE (PREFIX_0F3841
) },
7085 { PREFIX_TABLE (PREFIX_0F3880
) },
7086 { PREFIX_TABLE (PREFIX_0F3881
) },
7087 { PREFIX_TABLE (PREFIX_0F3882
) },
7166 { PREFIX_TABLE (PREFIX_0F38C8
) },
7167 { PREFIX_TABLE (PREFIX_0F38C9
) },
7168 { PREFIX_TABLE (PREFIX_0F38CA
) },
7169 { PREFIX_TABLE (PREFIX_0F38CB
) },
7170 { PREFIX_TABLE (PREFIX_0F38CC
) },
7171 { PREFIX_TABLE (PREFIX_0F38CD
) },
7173 { PREFIX_TABLE (PREFIX_0F38CF
) },
7187 { PREFIX_TABLE (PREFIX_0F38DB
) },
7188 { PREFIX_TABLE (PREFIX_0F38DC
) },
7189 { PREFIX_TABLE (PREFIX_0F38DD
) },
7190 { PREFIX_TABLE (PREFIX_0F38DE
) },
7191 { PREFIX_TABLE (PREFIX_0F38DF
) },
7211 { PREFIX_TABLE (PREFIX_0F38F0
) },
7212 { PREFIX_TABLE (PREFIX_0F38F1
) },
7216 { PREFIX_TABLE (PREFIX_0F38F5
) },
7217 { PREFIX_TABLE (PREFIX_0F38F6
) },
7220 { PREFIX_TABLE (PREFIX_0F38F8
) },
7221 { PREFIX_TABLE (PREFIX_0F38F9
) },
7229 /* THREE_BYTE_0F3A */
7241 { PREFIX_TABLE (PREFIX_0F3A08
) },
7242 { PREFIX_TABLE (PREFIX_0F3A09
) },
7243 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7244 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7245 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7246 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7247 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7248 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7254 { PREFIX_TABLE (PREFIX_0F3A14
) },
7255 { PREFIX_TABLE (PREFIX_0F3A15
) },
7256 { PREFIX_TABLE (PREFIX_0F3A16
) },
7257 { PREFIX_TABLE (PREFIX_0F3A17
) },
7268 { PREFIX_TABLE (PREFIX_0F3A20
) },
7269 { PREFIX_TABLE (PREFIX_0F3A21
) },
7270 { PREFIX_TABLE (PREFIX_0F3A22
) },
7304 { PREFIX_TABLE (PREFIX_0F3A40
) },
7305 { PREFIX_TABLE (PREFIX_0F3A41
) },
7306 { PREFIX_TABLE (PREFIX_0F3A42
) },
7308 { PREFIX_TABLE (PREFIX_0F3A44
) },
7340 { PREFIX_TABLE (PREFIX_0F3A60
) },
7341 { PREFIX_TABLE (PREFIX_0F3A61
) },
7342 { PREFIX_TABLE (PREFIX_0F3A62
) },
7343 { PREFIX_TABLE (PREFIX_0F3A63
) },
7461 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7463 { PREFIX_TABLE (PREFIX_0F3ACE
) },
7464 { PREFIX_TABLE (PREFIX_0F3ACF
) },
7482 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7522 static const struct dis386 xop_table
[][256] = {
7675 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7676 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7677 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7685 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7686 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7693 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7694 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7695 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7703 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7704 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7708 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7709 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7712 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7730 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7742 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
7743 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
7744 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
7745 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
7755 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7756 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7757 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7758 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7791 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7792 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7793 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7794 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
7818 { REG_TABLE (REG_XOP_TBM_01
) },
7819 { REG_TABLE (REG_XOP_TBM_02
) },
7837 { REG_TABLE (REG_XOP_LWPCB
) },
7961 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
7962 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
7963 { "vfrczss", { XM
, EXd
}, 0 },
7964 { "vfrczsd", { XM
, EXq
}, 0 },
7979 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7980 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7981 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7982 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7983 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7984 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7985 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7986 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7988 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7989 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7990 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7991 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8034 { "vphaddbw", { XM
, EXxmm
}, 0 },
8035 { "vphaddbd", { XM
, EXxmm
}, 0 },
8036 { "vphaddbq", { XM
, EXxmm
}, 0 },
8039 { "vphaddwd", { XM
, EXxmm
}, 0 },
8040 { "vphaddwq", { XM
, EXxmm
}, 0 },
8045 { "vphadddq", { XM
, EXxmm
}, 0 },
8052 { "vphaddubw", { XM
, EXxmm
}, 0 },
8053 { "vphaddubd", { XM
, EXxmm
}, 0 },
8054 { "vphaddubq", { XM
, EXxmm
}, 0 },
8057 { "vphadduwd", { XM
, EXxmm
}, 0 },
8058 { "vphadduwq", { XM
, EXxmm
}, 0 },
8063 { "vphaddudq", { XM
, EXxmm
}, 0 },
8070 { "vphsubbw", { XM
, EXxmm
}, 0 },
8071 { "vphsubwd", { XM
, EXxmm
}, 0 },
8072 { "vphsubdq", { XM
, EXxmm
}, 0 },
8126 { "bextr", { Gv
, Ev
, Iq
}, 0 },
8128 { REG_TABLE (REG_XOP_LWP
) },
8398 static const struct dis386 vex_table
[][256] = {
8420 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8421 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8422 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8423 { MOD_TABLE (MOD_VEX_0F13
) },
8424 { "vunpcklpX", { XM
, Vex
, EXx
}, 0 },
8425 { "vunpckhpX", { XM
, Vex
, EXx
}, 0 },
8426 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8427 { MOD_TABLE (MOD_VEX_0F17
) },
8447 { "vmovapX", { XM
, EXx
}, 0 },
8448 { "vmovapX", { EXxS
, XM
}, 0 },
8449 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8450 { MOD_TABLE (MOD_VEX_0F2B
) },
8451 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8452 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8453 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8454 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8475 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8476 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8478 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8479 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8480 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8481 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8485 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8486 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8492 { MOD_TABLE (MOD_VEX_0F50
) },
8493 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8494 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8495 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8496 { "vandpX", { XM
, Vex
, EXx
}, 0 },
8497 { "vandnpX", { XM
, Vex
, EXx
}, 0 },
8498 { "vorpX", { XM
, Vex
, EXx
}, 0 },
8499 { "vxorpX", { XM
, Vex
, EXx
}, 0 },
8501 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8502 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8503 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8504 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8505 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8506 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8507 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8508 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8510 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8511 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8512 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8513 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8514 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8515 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8516 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8517 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8519 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8520 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8521 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8522 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8523 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8524 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8525 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8526 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8528 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8529 { REG_TABLE (REG_VEX_0F71
) },
8530 { REG_TABLE (REG_VEX_0F72
) },
8531 { REG_TABLE (REG_VEX_0F73
) },
8532 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8533 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8534 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8535 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8541 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8542 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8543 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8544 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8564 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8565 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8566 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8567 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8573 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8574 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8597 { REG_TABLE (REG_VEX_0FAE
) },
8620 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8622 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8623 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8624 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, 0 },
8636 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8637 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8638 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8639 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8640 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8641 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8642 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8643 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8645 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8646 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8647 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8648 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8649 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8650 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8651 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8652 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8654 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8655 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8656 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8657 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8658 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8659 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8660 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8661 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8663 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8664 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8665 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8666 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8667 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8668 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8669 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8670 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8672 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8673 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8674 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8675 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8676 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8677 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8678 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8679 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8681 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8682 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8683 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8684 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8685 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8686 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8687 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8693 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8694 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8695 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8696 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8697 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8698 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8699 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8700 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8702 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8703 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8704 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8705 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8706 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8707 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8708 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8709 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8714 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8717 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8718 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8720 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8721 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8722 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8724 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8725 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8726 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8729 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8730 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8731 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8732 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8733 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8734 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8738 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8739 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8740 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8741 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8742 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8743 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8744 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8745 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8747 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8748 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8749 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8750 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8751 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8752 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8753 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8754 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8756 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8758 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8759 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8760 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8762 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8763 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8765 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8766 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8770 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8771 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8792 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8793 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8794 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
8828 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
8829 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
8850 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
8852 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
8855 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
8856 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
8857 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
8858 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
8861 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
8862 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
8864 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
8865 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
8866 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
8867 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
8868 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
8869 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
8870 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
8871 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
8879 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
8880 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
8882 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
8883 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
8884 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
8885 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
8886 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
8887 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
8888 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
8889 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
8897 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
8898 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
8900 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
8901 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
8902 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
8903 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
8904 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
8905 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
8906 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
8907 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
8925 { PREFIX_TABLE (PREFIX_VEX_0F38CF
) },
8939 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
8940 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
8941 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
8942 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
8943 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
8965 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
8966 { REG_TABLE (REG_VEX_0F38F3
) },
8968 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
8969 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
8970 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
8984 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
8985 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
8986 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
8988 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
8989 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
8990 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
8993 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
8994 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
8995 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
8996 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
8997 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
8998 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
8999 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9000 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9006 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9007 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9008 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9009 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9011 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9012 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9016 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9020 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9021 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9022 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9038 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9039 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9040 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9041 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9047 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9048 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9056 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9057 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9058 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9060 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9062 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9065 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9066 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9067 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9068 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9069 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9087 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9088 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9089 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9090 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9092 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9093 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9094 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9095 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9101 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9102 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9103 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9104 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9105 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9106 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9107 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9108 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9119 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9120 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9121 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9122 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9123 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9124 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9125 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9126 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9215 { PREFIX_TABLE(PREFIX_VEX_0F3ACE
) },
9216 { PREFIX_TABLE(PREFIX_VEX_0F3ACF
) },
9234 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9254 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9274 #define NEED_OPCODE_TABLE
9275 #include "i386-dis-evex.h"
9276 #undef NEED_OPCODE_TABLE
9277 static const struct dis386 vex_len_table
[][2] = {
9278 /* VEX_LEN_0F12_P_0_M_0 */
9280 { "vmovlps", { XM
, Vex128
, EXq
}, 0 },
9283 /* VEX_LEN_0F12_P_0_M_1 */
9285 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
9288 /* VEX_LEN_0F12_P_2 */
9290 { "vmovlpd", { XM
, Vex128
, EXq
}, 0 },
9293 /* VEX_LEN_0F13_M_0 */
9295 { "vmovlpX", { EXq
, XM
}, 0 },
9298 /* VEX_LEN_0F16_P_0_M_0 */
9300 { "vmovhps", { XM
, Vex128
, EXq
}, 0 },
9303 /* VEX_LEN_0F16_P_0_M_1 */
9305 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
9308 /* VEX_LEN_0F16_P_2 */
9310 { "vmovhpd", { XM
, Vex128
, EXq
}, 0 },
9313 /* VEX_LEN_0F17_M_0 */
9315 { "vmovhpX", { EXq
, XM
}, 0 },
9318 /* VEX_LEN_0F2A_P_1 */
9320 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9321 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9324 /* VEX_LEN_0F2A_P_3 */
9326 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9327 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9330 /* VEX_LEN_0F2C_P_1 */
9332 { "vcvttss2si", { Gv
, EXdScalar
}, 0 },
9333 { "vcvttss2si", { Gv
, EXdScalar
}, 0 },
9336 /* VEX_LEN_0F2C_P_3 */
9338 { "vcvttsd2si", { Gv
, EXqScalar
}, 0 },
9339 { "vcvttsd2si", { Gv
, EXqScalar
}, 0 },
9342 /* VEX_LEN_0F2D_P_1 */
9344 { "vcvtss2si", { Gv
, EXdScalar
}, 0 },
9345 { "vcvtss2si", { Gv
, EXdScalar
}, 0 },
9348 /* VEX_LEN_0F2D_P_3 */
9350 { "vcvtsd2si", { Gv
, EXqScalar
}, 0 },
9351 { "vcvtsd2si", { Gv
, EXqScalar
}, 0 },
9354 /* VEX_LEN_0F41_P_0 */
9357 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9359 /* VEX_LEN_0F41_P_2 */
9362 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9364 /* VEX_LEN_0F42_P_0 */
9367 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9369 /* VEX_LEN_0F42_P_2 */
9372 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9374 /* VEX_LEN_0F44_P_0 */
9376 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9378 /* VEX_LEN_0F44_P_2 */
9380 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9382 /* VEX_LEN_0F45_P_0 */
9385 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9387 /* VEX_LEN_0F45_P_2 */
9390 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9392 /* VEX_LEN_0F46_P_0 */
9395 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9397 /* VEX_LEN_0F46_P_2 */
9400 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9402 /* VEX_LEN_0F47_P_0 */
9405 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9407 /* VEX_LEN_0F47_P_2 */
9410 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9412 /* VEX_LEN_0F4A_P_0 */
9415 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9417 /* VEX_LEN_0F4A_P_2 */
9420 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9422 /* VEX_LEN_0F4B_P_0 */
9425 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9427 /* VEX_LEN_0F4B_P_2 */
9430 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9433 /* VEX_LEN_0F6E_P_2 */
9435 { "vmovK", { XMScalar
, Edq
}, 0 },
9438 /* VEX_LEN_0F77_P_1 */
9440 { "vzeroupper", { XX
}, 0 },
9441 { "vzeroall", { XX
}, 0 },
9444 /* VEX_LEN_0F7E_P_1 */
9446 { "vmovq", { XMScalar
, EXqScalar
}, 0 },
9449 /* VEX_LEN_0F7E_P_2 */
9451 { "vmovK", { Edq
, XMScalar
}, 0 },
9454 /* VEX_LEN_0F90_P_0 */
9456 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9459 /* VEX_LEN_0F90_P_2 */
9461 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9464 /* VEX_LEN_0F91_P_0 */
9466 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9469 /* VEX_LEN_0F91_P_2 */
9471 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9474 /* VEX_LEN_0F92_P_0 */
9476 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9479 /* VEX_LEN_0F92_P_2 */
9481 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9484 /* VEX_LEN_0F92_P_3 */
9486 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0
) },
9489 /* VEX_LEN_0F93_P_0 */
9491 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9494 /* VEX_LEN_0F93_P_2 */
9496 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9499 /* VEX_LEN_0F93_P_3 */
9501 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0
) },
9504 /* VEX_LEN_0F98_P_0 */
9506 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9509 /* VEX_LEN_0F98_P_2 */
9511 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9514 /* VEX_LEN_0F99_P_0 */
9516 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9519 /* VEX_LEN_0F99_P_2 */
9521 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9524 /* VEX_LEN_0FAE_R_2_M_0 */
9526 { "vldmxcsr", { Md
}, 0 },
9529 /* VEX_LEN_0FAE_R_3_M_0 */
9531 { "vstmxcsr", { Md
}, 0 },
9534 /* VEX_LEN_0FC4_P_2 */
9536 { VEX_W_TABLE (VEX_W_0FC4_P_2
) },
9539 /* VEX_LEN_0FC5_P_2 */
9541 { VEX_W_TABLE (VEX_W_0FC5_P_2
) },
9544 /* VEX_LEN_0FD6_P_2 */
9546 { "vmovq", { EXqScalarS
, XMScalar
}, 0 },
9549 /* VEX_LEN_0FF7_P_2 */
9551 { "vmaskmovdqu", { XM
, XS
}, 0 },
9554 /* VEX_LEN_0F3816_P_2 */
9557 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9560 /* VEX_LEN_0F3819_P_2 */
9563 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9566 /* VEX_LEN_0F381A_P_2_M_0 */
9569 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9572 /* VEX_LEN_0F3836_P_2 */
9575 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9578 /* VEX_LEN_0F3841_P_2 */
9580 { "vphminposuw", { XM
, EXx
}, 0 },
9583 /* VEX_LEN_0F385A_P_2_M_0 */
9586 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9589 /* VEX_LEN_0F38DB_P_2 */
9591 { "vaesimc", { XM
, EXx
}, 0 },
9594 /* VEX_LEN_0F38F2_P_0 */
9596 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
9599 /* VEX_LEN_0F38F3_R_1_P_0 */
9601 { "blsrS", { VexGdq
, Edq
}, 0 },
9604 /* VEX_LEN_0F38F3_R_2_P_0 */
9606 { "blsmskS", { VexGdq
, Edq
}, 0 },
9609 /* VEX_LEN_0F38F3_R_3_P_0 */
9611 { "blsiS", { VexGdq
, Edq
}, 0 },
9614 /* VEX_LEN_0F38F5_P_0 */
9616 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
9619 /* VEX_LEN_0F38F5_P_1 */
9621 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
9624 /* VEX_LEN_0F38F5_P_3 */
9626 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
9629 /* VEX_LEN_0F38F6_P_3 */
9631 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
9634 /* VEX_LEN_0F38F7_P_0 */
9636 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
9639 /* VEX_LEN_0F38F7_P_1 */
9641 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
9644 /* VEX_LEN_0F38F7_P_2 */
9646 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
9649 /* VEX_LEN_0F38F7_P_3 */
9651 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
9654 /* VEX_LEN_0F3A00_P_2 */
9657 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
9660 /* VEX_LEN_0F3A01_P_2 */
9663 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
9666 /* VEX_LEN_0F3A06_P_2 */
9669 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
9672 /* VEX_LEN_0F3A14_P_2 */
9674 { VEX_W_TABLE (VEX_W_0F3A14_P_2
) },
9677 /* VEX_LEN_0F3A15_P_2 */
9679 { VEX_W_TABLE (VEX_W_0F3A15_P_2
) },
9682 /* VEX_LEN_0F3A16_P_2 */
9684 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
9687 /* VEX_LEN_0F3A17_P_2 */
9689 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
9692 /* VEX_LEN_0F3A18_P_2 */
9695 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
9698 /* VEX_LEN_0F3A19_P_2 */
9701 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
9704 /* VEX_LEN_0F3A20_P_2 */
9706 { VEX_W_TABLE (VEX_W_0F3A20_P_2
) },
9709 /* VEX_LEN_0F3A21_P_2 */
9711 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
9714 /* VEX_LEN_0F3A22_P_2 */
9716 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
9719 /* VEX_LEN_0F3A30_P_2 */
9721 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
9724 /* VEX_LEN_0F3A31_P_2 */
9726 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
9729 /* VEX_LEN_0F3A32_P_2 */
9731 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
9734 /* VEX_LEN_0F3A33_P_2 */
9736 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
9739 /* VEX_LEN_0F3A38_P_2 */
9742 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
9745 /* VEX_LEN_0F3A39_P_2 */
9748 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
9751 /* VEX_LEN_0F3A41_P_2 */
9753 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
9756 /* VEX_LEN_0F3A46_P_2 */
9759 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
9762 /* VEX_LEN_0F3A60_P_2 */
9764 { "vpcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9767 /* VEX_LEN_0F3A61_P_2 */
9769 { "vpcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9772 /* VEX_LEN_0F3A62_P_2 */
9774 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
9777 /* VEX_LEN_0F3A63_P_2 */
9779 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
9782 /* VEX_LEN_0F3A6A_P_2 */
9784 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9787 /* VEX_LEN_0F3A6B_P_2 */
9789 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9792 /* VEX_LEN_0F3A6E_P_2 */
9794 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9797 /* VEX_LEN_0F3A6F_P_2 */
9799 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9802 /* VEX_LEN_0F3A7A_P_2 */
9804 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9807 /* VEX_LEN_0F3A7B_P_2 */
9809 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9812 /* VEX_LEN_0F3A7E_P_2 */
9814 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9817 /* VEX_LEN_0F3A7F_P_2 */
9819 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9822 /* VEX_LEN_0F3ADF_P_2 */
9824 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
9827 /* VEX_LEN_0F3AF0_P_3 */
9829 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
9832 /* VEX_LEN_0FXOP_08_CC */
9834 { "vpcomb", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9837 /* VEX_LEN_0FXOP_08_CD */
9839 { "vpcomw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9842 /* VEX_LEN_0FXOP_08_CE */
9844 { "vpcomd", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9847 /* VEX_LEN_0FXOP_08_CF */
9849 { "vpcomq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9852 /* VEX_LEN_0FXOP_08_EC */
9854 { "vpcomub", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9857 /* VEX_LEN_0FXOP_08_ED */
9859 { "vpcomuw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9862 /* VEX_LEN_0FXOP_08_EE */
9864 { "vpcomud", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9867 /* VEX_LEN_0FXOP_08_EF */
9869 { "vpcomuq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9872 /* VEX_LEN_0FXOP_09_80 */
9874 { "vfrczps", { XM
, EXxmm
}, 0 },
9875 { "vfrczps", { XM
, EXymmq
}, 0 },
9878 /* VEX_LEN_0FXOP_09_81 */
9880 { "vfrczpd", { XM
, EXxmm
}, 0 },
9881 { "vfrczpd", { XM
, EXymmq
}, 0 },
9885 static const struct dis386 vex_w_table
[][2] = {
9887 /* VEX_W_0F41_P_0_LEN_1 */
9888 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
9889 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
9892 /* VEX_W_0F41_P_2_LEN_1 */
9893 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
9894 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
9897 /* VEX_W_0F42_P_0_LEN_1 */
9898 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
9899 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
9902 /* VEX_W_0F42_P_2_LEN_1 */
9903 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
9904 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
9907 /* VEX_W_0F44_P_0_LEN_0 */
9908 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
9909 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
9912 /* VEX_W_0F44_P_2_LEN_0 */
9913 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
9914 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
9917 /* VEX_W_0F45_P_0_LEN_1 */
9918 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
9919 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
9922 /* VEX_W_0F45_P_2_LEN_1 */
9923 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
9924 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
9927 /* VEX_W_0F46_P_0_LEN_1 */
9928 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
9929 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
9932 /* VEX_W_0F46_P_2_LEN_1 */
9933 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
9934 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
9937 /* VEX_W_0F47_P_0_LEN_1 */
9938 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
9939 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
9942 /* VEX_W_0F47_P_2_LEN_1 */
9943 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
9944 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
9947 /* VEX_W_0F4A_P_0_LEN_1 */
9948 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
9949 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
9952 /* VEX_W_0F4A_P_2_LEN_1 */
9953 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
9954 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
9957 /* VEX_W_0F4B_P_0_LEN_1 */
9958 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
9959 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
9962 /* VEX_W_0F4B_P_2_LEN_1 */
9963 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
9966 /* VEX_W_0F90_P_0_LEN_0 */
9967 { "kmovw", { MaskG
, MaskE
}, 0 },
9968 { "kmovq", { MaskG
, MaskE
}, 0 },
9971 /* VEX_W_0F90_P_2_LEN_0 */
9972 { "kmovb", { MaskG
, MaskBDE
}, 0 },
9973 { "kmovd", { MaskG
, MaskBDE
}, 0 },
9976 /* VEX_W_0F91_P_0_LEN_0 */
9977 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
9978 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
9981 /* VEX_W_0F91_P_2_LEN_0 */
9982 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
9983 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
9986 /* VEX_W_0F92_P_0_LEN_0 */
9987 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
9990 /* VEX_W_0F92_P_2_LEN_0 */
9991 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
9994 /* VEX_W_0F92_P_3_LEN_0 */
9995 { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0
) },
9996 { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0
) },
9999 /* VEX_W_0F93_P_0_LEN_0 */
10000 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
10003 /* VEX_W_0F93_P_2_LEN_0 */
10004 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
10007 /* VEX_W_0F93_P_3_LEN_0 */
10008 { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0
) },
10009 { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0
) },
10012 /* VEX_W_0F98_P_0_LEN_0 */
10013 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
10014 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
10017 /* VEX_W_0F98_P_2_LEN_0 */
10018 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
10019 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
10022 /* VEX_W_0F99_P_0_LEN_0 */
10023 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
10024 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
10027 /* VEX_W_0F99_P_2_LEN_0 */
10028 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
10029 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
10032 /* VEX_W_0FC4_P_2 */
10033 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
10036 /* VEX_W_0FC5_P_2 */
10037 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
10040 /* VEX_W_0F380C_P_2 */
10041 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
10044 /* VEX_W_0F380D_P_2 */
10045 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
10048 /* VEX_W_0F380E_P_2 */
10049 { "vtestps", { XM
, EXx
}, 0 },
10052 /* VEX_W_0F380F_P_2 */
10053 { "vtestpd", { XM
, EXx
}, 0 },
10056 /* VEX_W_0F3816_P_2 */
10057 { "vpermps", { XM
, Vex
, EXx
}, 0 },
10060 /* VEX_W_0F3818_P_2 */
10061 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
10064 /* VEX_W_0F3819_P_2 */
10065 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
10068 /* VEX_W_0F381A_P_2_M_0 */
10069 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
10072 /* VEX_W_0F382C_P_2_M_0 */
10073 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
10076 /* VEX_W_0F382D_P_2_M_0 */
10077 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
10080 /* VEX_W_0F382E_P_2_M_0 */
10081 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
10084 /* VEX_W_0F382F_P_2_M_0 */
10085 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
10088 /* VEX_W_0F3836_P_2 */
10089 { "vpermd", { XM
, Vex
, EXx
}, 0 },
10092 /* VEX_W_0F3846_P_2 */
10093 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
10096 /* VEX_W_0F3858_P_2 */
10097 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
10100 /* VEX_W_0F3859_P_2 */
10101 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
10104 /* VEX_W_0F385A_P_2_M_0 */
10105 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
10108 /* VEX_W_0F3878_P_2 */
10109 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
10112 /* VEX_W_0F3879_P_2 */
10113 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
10116 /* VEX_W_0F38CF_P_2 */
10117 { "vgf2p8mulb", { XM
, Vex
, EXx
}, 0 },
10120 /* VEX_W_0F3A00_P_2 */
10122 { "vpermq", { XM
, EXx
, Ib
}, 0 },
10125 /* VEX_W_0F3A01_P_2 */
10127 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
10130 /* VEX_W_0F3A02_P_2 */
10131 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
10134 /* VEX_W_0F3A04_P_2 */
10135 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
10138 /* VEX_W_0F3A05_P_2 */
10139 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
10142 /* VEX_W_0F3A06_P_2 */
10143 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10146 /* VEX_W_0F3A14_P_2 */
10147 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
10150 /* VEX_W_0F3A15_P_2 */
10151 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
10154 /* VEX_W_0F3A18_P_2 */
10155 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10158 /* VEX_W_0F3A19_P_2 */
10159 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
10162 /* VEX_W_0F3A20_P_2 */
10163 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
10166 /* VEX_W_0F3A30_P_2_LEN_0 */
10167 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
10168 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
10171 /* VEX_W_0F3A31_P_2_LEN_0 */
10172 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
10173 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
10176 /* VEX_W_0F3A32_P_2_LEN_0 */
10177 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
10178 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
10181 /* VEX_W_0F3A33_P_2_LEN_0 */
10182 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
10183 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
10186 /* VEX_W_0F3A38_P_2 */
10187 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10190 /* VEX_W_0F3A39_P_2 */
10191 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
10194 /* VEX_W_0F3A46_P_2 */
10195 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10198 /* VEX_W_0F3A48_P_2 */
10199 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10200 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10203 /* VEX_W_0F3A49_P_2 */
10204 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10205 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10208 /* VEX_W_0F3A4A_P_2 */
10209 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10212 /* VEX_W_0F3A4B_P_2 */
10213 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10216 /* VEX_W_0F3A4C_P_2 */
10217 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10220 /* VEX_W_0F3ACE_P_2 */
10222 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10225 /* VEX_W_0F3ACF_P_2 */
10227 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10229 #define NEED_VEX_W_TABLE
10230 #include "i386-dis-evex.h"
10231 #undef NEED_VEX_W_TABLE
10234 static const struct dis386 mod_table
[][2] = {
10237 { "leaS", { Gv
, M
}, 0 },
10242 { RM_TABLE (RM_C6_REG_7
) },
10247 { RM_TABLE (RM_C7_REG_7
) },
10251 { "Jcall^", { indirEp
}, 0 },
10255 { "Jjmp^", { indirEp
}, 0 },
10258 /* MOD_0F01_REG_0 */
10259 { X86_64_TABLE (X86_64_0F01_REG_0
) },
10260 { RM_TABLE (RM_0F01_REG_0
) },
10263 /* MOD_0F01_REG_1 */
10264 { X86_64_TABLE (X86_64_0F01_REG_1
) },
10265 { RM_TABLE (RM_0F01_REG_1
) },
10268 /* MOD_0F01_REG_2 */
10269 { X86_64_TABLE (X86_64_0F01_REG_2
) },
10270 { RM_TABLE (RM_0F01_REG_2
) },
10273 /* MOD_0F01_REG_3 */
10274 { X86_64_TABLE (X86_64_0F01_REG_3
) },
10275 { RM_TABLE (RM_0F01_REG_3
) },
10278 /* MOD_0F01_REG_5 */
10279 { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5
) },
10280 { RM_TABLE (RM_0F01_REG_5
) },
10283 /* MOD_0F01_REG_7 */
10284 { "invlpg", { Mb
}, 0 },
10285 { RM_TABLE (RM_0F01_REG_7
) },
10288 /* MOD_0F12_PREFIX_0 */
10289 { "movlps", { XM
, EXq
}, PREFIX_OPCODE
},
10290 { "movhlps", { XM
, EXq
}, PREFIX_OPCODE
},
10294 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
10297 /* MOD_0F16_PREFIX_0 */
10298 { "movhps", { XM
, EXq
}, 0 },
10299 { "movlhps", { XM
, EXq
}, 0 },
10303 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
10306 /* MOD_0F18_REG_0 */
10307 { "prefetchnta", { Mb
}, 0 },
10310 /* MOD_0F18_REG_1 */
10311 { "prefetcht0", { Mb
}, 0 },
10314 /* MOD_0F18_REG_2 */
10315 { "prefetcht1", { Mb
}, 0 },
10318 /* MOD_0F18_REG_3 */
10319 { "prefetcht2", { Mb
}, 0 },
10322 /* MOD_0F18_REG_4 */
10323 { "nop/reserved", { Mb
}, 0 },
10326 /* MOD_0F18_REG_5 */
10327 { "nop/reserved", { Mb
}, 0 },
10330 /* MOD_0F18_REG_6 */
10331 { "nop/reserved", { Mb
}, 0 },
10334 /* MOD_0F18_REG_7 */
10335 { "nop/reserved", { Mb
}, 0 },
10338 /* MOD_0F1A_PREFIX_0 */
10339 { "bndldx", { Gbnd
, Mv_bnd
}, 0 },
10340 { "nopQ", { Ev
}, 0 },
10343 /* MOD_0F1B_PREFIX_0 */
10344 { "bndstx", { Mv_bnd
, Gbnd
}, 0 },
10345 { "nopQ", { Ev
}, 0 },
10348 /* MOD_0F1B_PREFIX_1 */
10349 { "bndmk", { Gbnd
, Mv_bnd
}, 0 },
10350 { "nopQ", { Ev
}, 0 },
10353 /* MOD_0F1C_PREFIX_0 */
10354 { REG_TABLE (REG_0F1C_MOD_0
) },
10355 { "nopQ", { Ev
}, 0 },
10358 /* MOD_0F1E_PREFIX_1 */
10359 { "nopQ", { Ev
}, 0 },
10360 { REG_TABLE (REG_0F1E_MOD_3
) },
10365 { "movL", { Rd
, Td
}, 0 },
10370 { "movL", { Td
, Rd
}, 0 },
10373 /* MOD_0F2B_PREFIX_0 */
10374 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
10377 /* MOD_0F2B_PREFIX_1 */
10378 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
10381 /* MOD_0F2B_PREFIX_2 */
10382 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
10385 /* MOD_0F2B_PREFIX_3 */
10386 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
10391 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
10394 /* MOD_0F71_REG_2 */
10396 { "psrlw", { MS
, Ib
}, 0 },
10399 /* MOD_0F71_REG_4 */
10401 { "psraw", { MS
, Ib
}, 0 },
10404 /* MOD_0F71_REG_6 */
10406 { "psllw", { MS
, Ib
}, 0 },
10409 /* MOD_0F72_REG_2 */
10411 { "psrld", { MS
, Ib
}, 0 },
10414 /* MOD_0F72_REG_4 */
10416 { "psrad", { MS
, Ib
}, 0 },
10419 /* MOD_0F72_REG_6 */
10421 { "pslld", { MS
, Ib
}, 0 },
10424 /* MOD_0F73_REG_2 */
10426 { "psrlq", { MS
, Ib
}, 0 },
10429 /* MOD_0F73_REG_3 */
10431 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
10434 /* MOD_0F73_REG_6 */
10436 { "psllq", { MS
, Ib
}, 0 },
10439 /* MOD_0F73_REG_7 */
10441 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
10444 /* MOD_0FAE_REG_0 */
10445 { "fxsave", { FXSAVE
}, 0 },
10446 { PREFIX_TABLE (PREFIX_0FAE_REG_0
) },
10449 /* MOD_0FAE_REG_1 */
10450 { "fxrstor", { FXSAVE
}, 0 },
10451 { PREFIX_TABLE (PREFIX_0FAE_REG_1
) },
10454 /* MOD_0FAE_REG_2 */
10455 { "ldmxcsr", { Md
}, 0 },
10456 { PREFIX_TABLE (PREFIX_0FAE_REG_2
) },
10459 /* MOD_0FAE_REG_3 */
10460 { "stmxcsr", { Md
}, 0 },
10461 { PREFIX_TABLE (PREFIX_0FAE_REG_3
) },
10464 /* MOD_0FAE_REG_4 */
10465 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4
) },
10466 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4
) },
10469 /* MOD_0FAE_REG_5 */
10470 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5
) },
10471 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5
) },
10474 /* MOD_0FAE_REG_6 */
10475 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6
) },
10476 { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6
) },
10479 /* MOD_0FAE_REG_7 */
10480 { PREFIX_TABLE (PREFIX_0FAE_REG_7
) },
10481 { RM_TABLE (RM_0FAE_REG_7
) },
10485 { "lssS", { Gv
, Mp
}, 0 },
10489 { "lfsS", { Gv
, Mp
}, 0 },
10493 { "lgsS", { Gv
, Mp
}, 0 },
10497 { PREFIX_TABLE (PREFIX_MOD_0_0FC3
) },
10500 /* MOD_0FC7_REG_3 */
10501 { "xrstors", { FXSAVE
}, 0 },
10504 /* MOD_0FC7_REG_4 */
10505 { "xsavec", { FXSAVE
}, 0 },
10508 /* MOD_0FC7_REG_5 */
10509 { "xsaves", { FXSAVE
}, 0 },
10512 /* MOD_0FC7_REG_6 */
10513 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6
) },
10514 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6
) }
10517 /* MOD_0FC7_REG_7 */
10518 { "vmptrst", { Mq
}, 0 },
10519 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7
) }
10524 { "pmovmskb", { Gdq
, MS
}, 0 },
10527 /* MOD_0FE7_PREFIX_2 */
10528 { "movntdq", { Mx
, XM
}, 0 },
10531 /* MOD_0FF0_PREFIX_3 */
10532 { "lddqu", { XM
, M
}, 0 },
10535 /* MOD_0F382A_PREFIX_2 */
10536 { "movntdqa", { XM
, Mx
}, 0 },
10539 /* MOD_0F38F5_PREFIX_2 */
10540 { "wrussK", { M
, Gdq
}, PREFIX_OPCODE
},
10543 /* MOD_0F38F6_PREFIX_0 */
10544 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
10547 /* MOD_0F38F8_PREFIX_2 */
10548 { "movdir64b", { Gva
, M
}, PREFIX_OPCODE
},
10551 /* MOD_0F38F9_PREFIX_0 */
10552 { "movdiri", { Em
, Gv
}, PREFIX_OPCODE
},
10556 { "bound{S|}", { Gv
, Ma
}, 0 },
10557 { EVEX_TABLE (EVEX_0F
) },
10561 { "lesS", { Gv
, Mp
}, 0 },
10562 { VEX_C4_TABLE (VEX_0F
) },
10566 { "ldsS", { Gv
, Mp
}, 0 },
10567 { VEX_C5_TABLE (VEX_0F
) },
10570 /* MOD_VEX_0F12_PREFIX_0 */
10571 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
10572 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
10576 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
10579 /* MOD_VEX_0F16_PREFIX_0 */
10580 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
10581 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
10585 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
10589 { "vmovntpX", { Mx
, XM
}, 0 },
10592 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10594 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
10597 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10599 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
10602 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10604 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
10607 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10609 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
10612 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10614 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
10617 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10619 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
10622 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10624 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
10627 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10629 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
10632 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10634 { "knotw", { MaskG
, MaskR
}, 0 },
10637 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10639 { "knotq", { MaskG
, MaskR
}, 0 },
10642 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10644 { "knotb", { MaskG
, MaskR
}, 0 },
10647 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10649 { "knotd", { MaskG
, MaskR
}, 0 },
10652 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10654 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
10657 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10659 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
10662 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10664 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
10667 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10669 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
10672 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10674 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10677 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10679 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10682 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10684 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10687 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10689 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
10692 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10694 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10697 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10699 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10702 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10704 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10707 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10709 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
10712 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10714 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
10717 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10719 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
10722 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10724 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
10727 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10729 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
10732 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10734 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
10737 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10739 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
10742 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10744 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
10749 { "vmovmskpX", { Gdq
, XS
}, 0 },
10752 /* MOD_VEX_0F71_REG_2 */
10754 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
10757 /* MOD_VEX_0F71_REG_4 */
10759 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
10762 /* MOD_VEX_0F71_REG_6 */
10764 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
10767 /* MOD_VEX_0F72_REG_2 */
10769 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
10772 /* MOD_VEX_0F72_REG_4 */
10774 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
10777 /* MOD_VEX_0F72_REG_6 */
10779 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
10782 /* MOD_VEX_0F73_REG_2 */
10784 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
10787 /* MOD_VEX_0F73_REG_3 */
10789 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
10792 /* MOD_VEX_0F73_REG_6 */
10794 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
10797 /* MOD_VEX_0F73_REG_7 */
10799 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
10802 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10803 { "kmovw", { Ew
, MaskG
}, 0 },
10807 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10808 { "kmovq", { Eq
, MaskG
}, 0 },
10812 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10813 { "kmovb", { Eb
, MaskG
}, 0 },
10817 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10818 { "kmovd", { Ed
, MaskG
}, 0 },
10822 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10824 { "kmovw", { MaskG
, Rdq
}, 0 },
10827 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10829 { "kmovb", { MaskG
, Rdq
}, 0 },
10832 /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
10834 { "kmovd", { MaskG
, Rdq
}, 0 },
10837 /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
10839 { "kmovq", { MaskG
, Rdq
}, 0 },
10842 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10844 { "kmovw", { Gdq
, MaskR
}, 0 },
10847 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10849 { "kmovb", { Gdq
, MaskR
}, 0 },
10852 /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
10854 { "kmovd", { Gdq
, MaskR
}, 0 },
10857 /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
10859 { "kmovq", { Gdq
, MaskR
}, 0 },
10862 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10864 { "kortestw", { MaskG
, MaskR
}, 0 },
10867 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10869 { "kortestq", { MaskG
, MaskR
}, 0 },
10872 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10874 { "kortestb", { MaskG
, MaskR
}, 0 },
10877 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10879 { "kortestd", { MaskG
, MaskR
}, 0 },
10882 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10884 { "ktestw", { MaskG
, MaskR
}, 0 },
10887 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10889 { "ktestq", { MaskG
, MaskR
}, 0 },
10892 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10894 { "ktestb", { MaskG
, MaskR
}, 0 },
10897 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10899 { "ktestd", { MaskG
, MaskR
}, 0 },
10902 /* MOD_VEX_0FAE_REG_2 */
10903 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
10906 /* MOD_VEX_0FAE_REG_3 */
10907 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
10910 /* MOD_VEX_0FD7_PREFIX_2 */
10912 { "vpmovmskb", { Gdq
, XS
}, 0 },
10915 /* MOD_VEX_0FE7_PREFIX_2 */
10916 { "vmovntdq", { Mx
, XM
}, 0 },
10919 /* MOD_VEX_0FF0_PREFIX_3 */
10920 { "vlddqu", { XM
, M
}, 0 },
10923 /* MOD_VEX_0F381A_PREFIX_2 */
10924 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
10927 /* MOD_VEX_0F382A_PREFIX_2 */
10928 { "vmovntdqa", { XM
, Mx
}, 0 },
10931 /* MOD_VEX_0F382C_PREFIX_2 */
10932 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
10935 /* MOD_VEX_0F382D_PREFIX_2 */
10936 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
10939 /* MOD_VEX_0F382E_PREFIX_2 */
10940 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
10943 /* MOD_VEX_0F382F_PREFIX_2 */
10944 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
10947 /* MOD_VEX_0F385A_PREFIX_2 */
10948 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
10951 /* MOD_VEX_0F388C_PREFIX_2 */
10952 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
10955 /* MOD_VEX_0F388E_PREFIX_2 */
10956 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
10959 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10961 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
10964 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10966 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
10969 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10971 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
10974 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10976 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
10979 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10981 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
10984 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10986 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
10989 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10991 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
10994 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10996 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
10998 #define NEED_MOD_TABLE
10999 #include "i386-dis-evex.h"
11000 #undef NEED_MOD_TABLE
11003 static const struct dis386 rm_table
[][8] = {
11006 { "xabort", { Skip_MODRM
, Ib
}, 0 },
11010 { "xbeginT", { Skip_MODRM
, Jv
}, 0 },
11013 /* RM_0F01_REG_0 */
11015 { "vmcall", { Skip_MODRM
}, 0 },
11016 { "vmlaunch", { Skip_MODRM
}, 0 },
11017 { "vmresume", { Skip_MODRM
}, 0 },
11018 { "vmxoff", { Skip_MODRM
}, 0 },
11019 { "pconfig", { Skip_MODRM
}, 0 },
11022 /* RM_0F01_REG_1 */
11023 { "monitor", { { OP_Monitor
, 0 } }, 0 },
11024 { "mwait", { { OP_Mwait
, 0 } }, 0 },
11025 { "clac", { Skip_MODRM
}, 0 },
11026 { "stac", { Skip_MODRM
}, 0 },
11030 { "encls", { Skip_MODRM
}, 0 },
11033 /* RM_0F01_REG_2 */
11034 { "xgetbv", { Skip_MODRM
}, 0 },
11035 { "xsetbv", { Skip_MODRM
}, 0 },
11038 { "vmfunc", { Skip_MODRM
}, 0 },
11039 { "xend", { Skip_MODRM
}, 0 },
11040 { "xtest", { Skip_MODRM
}, 0 },
11041 { "enclu", { Skip_MODRM
}, 0 },
11044 /* RM_0F01_REG_3 */
11045 { "vmrun", { Skip_MODRM
}, 0 },
11046 { "vmmcall", { Skip_MODRM
}, 0 },
11047 { "vmload", { Skip_MODRM
}, 0 },
11048 { "vmsave", { Skip_MODRM
}, 0 },
11049 { "stgi", { Skip_MODRM
}, 0 },
11050 { "clgi", { Skip_MODRM
}, 0 },
11051 { "skinit", { Skip_MODRM
}, 0 },
11052 { "invlpga", { Skip_MODRM
}, 0 },
11055 /* RM_0F01_REG_5 */
11056 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0
) },
11058 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2
) },
11062 { "rdpkru", { Skip_MODRM
}, 0 },
11063 { "wrpkru", { Skip_MODRM
}, 0 },
11066 /* RM_0F01_REG_7 */
11067 { "swapgs", { Skip_MODRM
}, 0 },
11068 { "rdtscp", { Skip_MODRM
}, 0 },
11069 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
11070 { "mwaitx", { { OP_Mwaitx
, 0 } }, 0 },
11071 { "clzero", { Skip_MODRM
}, 0 },
11074 /* RM_0F1E_MOD_3_REG_7 */
11075 { "nopQ", { Ev
}, 0 },
11076 { "nopQ", { Ev
}, 0 },
11077 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
11078 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
11079 { "nopQ", { Ev
}, 0 },
11080 { "nopQ", { Ev
}, 0 },
11081 { "nopQ", { Ev
}, 0 },
11082 { "nopQ", { Ev
}, 0 },
11085 /* RM_0FAE_REG_6 */
11086 { "mfence", { Skip_MODRM
}, 0 },
11089 /* RM_0FAE_REG_7 */
11090 { "sfence", { Skip_MODRM
}, 0 },
11095 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11097 /* We use the high bit to indicate different name for the same
11099 #define REP_PREFIX (0xf3 | 0x100)
11100 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11101 #define XRELEASE_PREFIX (0xf3 | 0x400)
11102 #define BND_PREFIX (0xf2 | 0x400)
11103 #define NOTRACK_PREFIX (0x3e | 0x100)
11108 int newrex
, i
, length
;
11114 last_lock_prefix
= -1;
11115 last_repz_prefix
= -1;
11116 last_repnz_prefix
= -1;
11117 last_data_prefix
= -1;
11118 last_addr_prefix
= -1;
11119 last_rex_prefix
= -1;
11120 last_seg_prefix
= -1;
11122 active_seg_prefix
= 0;
11123 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11124 all_prefixes
[i
] = 0;
11127 /* The maximum instruction length is 15bytes. */
11128 while (length
< MAX_CODE_LENGTH
- 1)
11130 FETCH_DATA (the_info
, codep
+ 1);
11134 /* REX prefixes family. */
11151 if (address_mode
== mode_64bit
)
11155 last_rex_prefix
= i
;
11158 prefixes
|= PREFIX_REPZ
;
11159 last_repz_prefix
= i
;
11162 prefixes
|= PREFIX_REPNZ
;
11163 last_repnz_prefix
= i
;
11166 prefixes
|= PREFIX_LOCK
;
11167 last_lock_prefix
= i
;
11170 prefixes
|= PREFIX_CS
;
11171 last_seg_prefix
= i
;
11172 active_seg_prefix
= PREFIX_CS
;
11175 prefixes
|= PREFIX_SS
;
11176 last_seg_prefix
= i
;
11177 active_seg_prefix
= PREFIX_SS
;
11180 prefixes
|= PREFIX_DS
;
11181 last_seg_prefix
= i
;
11182 active_seg_prefix
= PREFIX_DS
;
11185 prefixes
|= PREFIX_ES
;
11186 last_seg_prefix
= i
;
11187 active_seg_prefix
= PREFIX_ES
;
11190 prefixes
|= PREFIX_FS
;
11191 last_seg_prefix
= i
;
11192 active_seg_prefix
= PREFIX_FS
;
11195 prefixes
|= PREFIX_GS
;
11196 last_seg_prefix
= i
;
11197 active_seg_prefix
= PREFIX_GS
;
11200 prefixes
|= PREFIX_DATA
;
11201 last_data_prefix
= i
;
11204 prefixes
|= PREFIX_ADDR
;
11205 last_addr_prefix
= i
;
11208 /* fwait is really an instruction. If there are prefixes
11209 before the fwait, they belong to the fwait, *not* to the
11210 following instruction. */
11212 if (prefixes
|| rex
)
11214 prefixes
|= PREFIX_FWAIT
;
11216 /* This ensures that the previous REX prefixes are noticed
11217 as unused prefixes, as in the return case below. */
11221 prefixes
= PREFIX_FWAIT
;
11226 /* Rex is ignored when followed by another prefix. */
11232 if (*codep
!= FWAIT_OPCODE
)
11233 all_prefixes
[i
++] = *codep
;
11241 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11244 static const char *
11245 prefix_name (int pref
, int sizeflag
)
11247 static const char *rexes
[16] =
11250 "rex.B", /* 0x41 */
11251 "rex.X", /* 0x42 */
11252 "rex.XB", /* 0x43 */
11253 "rex.R", /* 0x44 */
11254 "rex.RB", /* 0x45 */
11255 "rex.RX", /* 0x46 */
11256 "rex.RXB", /* 0x47 */
11257 "rex.W", /* 0x48 */
11258 "rex.WB", /* 0x49 */
11259 "rex.WX", /* 0x4a */
11260 "rex.WXB", /* 0x4b */
11261 "rex.WR", /* 0x4c */
11262 "rex.WRB", /* 0x4d */
11263 "rex.WRX", /* 0x4e */
11264 "rex.WRXB", /* 0x4f */
11269 /* REX prefixes family. */
11286 return rexes
[pref
- 0x40];
11306 return (sizeflag
& DFLAG
) ? "data16" : "data32";
11308 if (address_mode
== mode_64bit
)
11309 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
11311 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
11316 case XACQUIRE_PREFIX
:
11318 case XRELEASE_PREFIX
:
11322 case NOTRACK_PREFIX
:
11329 static char op_out
[MAX_OPERANDS
][100];
11330 static int op_ad
, op_index
[MAX_OPERANDS
];
11331 static int two_source_ops
;
11332 static bfd_vma op_address
[MAX_OPERANDS
];
11333 static bfd_vma op_riprel
[MAX_OPERANDS
];
11334 static bfd_vma start_pc
;
11337 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11338 * (see topic "Redundant prefixes" in the "Differences from 8086"
11339 * section of the "Virtual 8086 Mode" chapter.)
11340 * 'pc' should be the address of this instruction, it will
11341 * be used to print the target address if this is a relative jump or call
11342 * The function returns the length of this instruction in bytes.
11345 static char intel_syntax
;
11346 static char intel_mnemonic
= !SYSV386_COMPAT
;
11347 static char open_char
;
11348 static char close_char
;
11349 static char separator_char
;
11350 static char scale_char
;
11358 static enum x86_64_isa isa64
;
11360 /* Here for backwards compatibility. When gdb stops using
11361 print_insn_i386_att and print_insn_i386_intel these functions can
11362 disappear, and print_insn_i386 be merged into print_insn. */
11364 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
11368 return print_insn (pc
, info
);
11372 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
11376 return print_insn (pc
, info
);
11380 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
11384 return print_insn (pc
, info
);
11388 print_i386_disassembler_options (FILE *stream
)
11390 fprintf (stream
, _("\n\
11391 The following i386/x86-64 specific disassembler options are supported for use\n\
11392 with the -M switch (multiple options should be separated by commas):\n"));
11394 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
11395 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
11396 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
11397 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
11398 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
11399 fprintf (stream
, _(" att-mnemonic\n"
11400 " Display instruction in AT&T mnemonic\n"));
11401 fprintf (stream
, _(" intel-mnemonic\n"
11402 " Display instruction in Intel mnemonic\n"));
11403 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
11404 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
11405 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
11406 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
11407 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
11408 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11409 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
11410 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
11414 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
11416 /* Get a pointer to struct dis386 with a valid name. */
11418 static const struct dis386
*
11419 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
11421 int vindex
, vex_table_index
;
11423 if (dp
->name
!= NULL
)
11426 switch (dp
->op
[0].bytemode
)
11428 case USE_REG_TABLE
:
11429 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
11432 case USE_MOD_TABLE
:
11433 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
11434 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
11438 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
11441 case USE_PREFIX_TABLE
:
11444 /* The prefix in VEX is implicit. */
11445 switch (vex
.prefix
)
11450 case REPE_PREFIX_OPCODE
:
11453 case DATA_PREFIX_OPCODE
:
11456 case REPNE_PREFIX_OPCODE
:
11466 int last_prefix
= -1;
11469 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11470 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11472 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
11474 if (last_repz_prefix
> last_repnz_prefix
)
11477 prefix
= PREFIX_REPZ
;
11478 last_prefix
= last_repz_prefix
;
11483 prefix
= PREFIX_REPNZ
;
11484 last_prefix
= last_repnz_prefix
;
11487 /* Check if prefix should be ignored. */
11488 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
11489 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
11494 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
11497 prefix
= PREFIX_DATA
;
11498 last_prefix
= last_data_prefix
;
11503 used_prefixes
|= prefix
;
11504 all_prefixes
[last_prefix
] = 0;
11507 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
11510 case USE_X86_64_TABLE
:
11511 vindex
= address_mode
== mode_64bit
? 1 : 0;
11512 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
11515 case USE_3BYTE_TABLE
:
11516 FETCH_DATA (info
, codep
+ 2);
11518 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
11520 modrm
.mod
= (*codep
>> 6) & 3;
11521 modrm
.reg
= (*codep
>> 3) & 7;
11522 modrm
.rm
= *codep
& 7;
11525 case USE_VEX_LEN_TABLE
:
11529 switch (vex
.length
)
11542 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
11545 case USE_XOP_8F_TABLE
:
11546 FETCH_DATA (info
, codep
+ 3);
11547 /* All bits in the REX prefix are ignored. */
11549 rex
= ~(*codep
>> 5) & 0x7;
11551 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11552 switch ((*codep
& 0x1f))
11558 vex_table_index
= XOP_08
;
11561 vex_table_index
= XOP_09
;
11564 vex_table_index
= XOP_0A
;
11568 vex
.w
= *codep
& 0x80;
11569 if (vex
.w
&& address_mode
== mode_64bit
)
11572 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11573 if (address_mode
!= mode_64bit
)
11575 /* In 16/32-bit mode REX_B is silently ignored. */
11579 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11580 switch ((*codep
& 0x3))
11585 vex
.prefix
= DATA_PREFIX_OPCODE
;
11588 vex
.prefix
= REPE_PREFIX_OPCODE
;
11591 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11598 dp
= &xop_table
[vex_table_index
][vindex
];
11601 FETCH_DATA (info
, codep
+ 1);
11602 modrm
.mod
= (*codep
>> 6) & 3;
11603 modrm
.reg
= (*codep
>> 3) & 7;
11604 modrm
.rm
= *codep
& 7;
11607 case USE_VEX_C4_TABLE
:
11609 FETCH_DATA (info
, codep
+ 3);
11610 /* All bits in the REX prefix are ignored. */
11612 rex
= ~(*codep
>> 5) & 0x7;
11613 switch ((*codep
& 0x1f))
11619 vex_table_index
= VEX_0F
;
11622 vex_table_index
= VEX_0F38
;
11625 vex_table_index
= VEX_0F3A
;
11629 vex
.w
= *codep
& 0x80;
11630 if (address_mode
== mode_64bit
)
11637 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11638 is ignored, other REX bits are 0 and the highest bit in
11639 VEX.vvvv is also ignored (but we mustn't clear it here). */
11642 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11643 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11644 switch ((*codep
& 0x3))
11649 vex
.prefix
= DATA_PREFIX_OPCODE
;
11652 vex
.prefix
= REPE_PREFIX_OPCODE
;
11655 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11662 dp
= &vex_table
[vex_table_index
][vindex
];
11664 /* There is no MODRM byte for VEX0F 77. */
11665 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
11667 FETCH_DATA (info
, codep
+ 1);
11668 modrm
.mod
= (*codep
>> 6) & 3;
11669 modrm
.reg
= (*codep
>> 3) & 7;
11670 modrm
.rm
= *codep
& 7;
11674 case USE_VEX_C5_TABLE
:
11676 FETCH_DATA (info
, codep
+ 2);
11677 /* All bits in the REX prefix are ignored. */
11679 rex
= (*codep
& 0x80) ? 0 : REX_R
;
11681 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11683 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11684 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11685 switch ((*codep
& 0x3))
11690 vex
.prefix
= DATA_PREFIX_OPCODE
;
11693 vex
.prefix
= REPE_PREFIX_OPCODE
;
11696 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11703 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
11705 /* There is no MODRM byte for VEX 77. */
11706 if (vindex
!= 0x77)
11708 FETCH_DATA (info
, codep
+ 1);
11709 modrm
.mod
= (*codep
>> 6) & 3;
11710 modrm
.reg
= (*codep
>> 3) & 7;
11711 modrm
.rm
= *codep
& 7;
11715 case USE_VEX_W_TABLE
:
11719 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
11722 case USE_EVEX_TABLE
:
11723 two_source_ops
= 0;
11726 FETCH_DATA (info
, codep
+ 4);
11727 /* All bits in the REX prefix are ignored. */
11729 /* The first byte after 0x62. */
11730 rex
= ~(*codep
>> 5) & 0x7;
11731 vex
.r
= *codep
& 0x10;
11732 switch ((*codep
& 0xf))
11735 return &bad_opcode
;
11737 vex_table_index
= EVEX_0F
;
11740 vex_table_index
= EVEX_0F38
;
11743 vex_table_index
= EVEX_0F3A
;
11747 /* The second byte after 0x62. */
11749 vex
.w
= *codep
& 0x80;
11750 if (vex
.w
&& address_mode
== mode_64bit
)
11753 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11756 if (!(*codep
& 0x4))
11757 return &bad_opcode
;
11759 switch ((*codep
& 0x3))
11764 vex
.prefix
= DATA_PREFIX_OPCODE
;
11767 vex
.prefix
= REPE_PREFIX_OPCODE
;
11770 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11774 /* The third byte after 0x62. */
11777 /* Remember the static rounding bits. */
11778 vex
.ll
= (*codep
>> 5) & 3;
11779 vex
.b
= (*codep
& 0x10) != 0;
11781 vex
.v
= *codep
& 0x8;
11782 vex
.mask_register_specifier
= *codep
& 0x7;
11783 vex
.zeroing
= *codep
& 0x80;
11785 if (address_mode
!= mode_64bit
)
11787 /* In 16/32-bit mode silently ignore following bits. */
11797 dp
= &evex_table
[vex_table_index
][vindex
];
11799 FETCH_DATA (info
, codep
+ 1);
11800 modrm
.mod
= (*codep
>> 6) & 3;
11801 modrm
.reg
= (*codep
>> 3) & 7;
11802 modrm
.rm
= *codep
& 7;
11804 /* Set vector length. */
11805 if (modrm
.mod
== 3 && vex
.b
)
11821 return &bad_opcode
;
11834 if (dp
->name
!= NULL
)
11837 return get_valid_dis386 (dp
, info
);
11841 get_sib (disassemble_info
*info
, int sizeflag
)
11843 /* If modrm.mod == 3, operand must be register. */
11845 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11849 FETCH_DATA (info
, codep
+ 2);
11850 sib
.index
= (codep
[1] >> 3) & 7;
11851 sib
.scale
= (codep
[1] >> 6) & 3;
11852 sib
.base
= codep
[1] & 7;
11857 print_insn (bfd_vma pc
, disassemble_info
*info
)
11859 const struct dis386
*dp
;
11861 char *op_txt
[MAX_OPERANDS
];
11863 int sizeflag
, orig_sizeflag
;
11865 struct dis_private priv
;
11868 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11869 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
11870 address_mode
= mode_32bit
;
11871 else if (info
->mach
== bfd_mach_i386_i8086
)
11873 address_mode
= mode_16bit
;
11874 priv
.orig_sizeflag
= 0;
11877 address_mode
= mode_64bit
;
11879 if (intel_syntax
== (char) -1)
11880 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
11882 for (p
= info
->disassembler_options
; p
!= NULL
; )
11884 if (CONST_STRNEQ (p
, "amd64"))
11886 else if (CONST_STRNEQ (p
, "intel64"))
11888 else if (CONST_STRNEQ (p
, "x86-64"))
11890 address_mode
= mode_64bit
;
11891 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11893 else if (CONST_STRNEQ (p
, "i386"))
11895 address_mode
= mode_32bit
;
11896 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11898 else if (CONST_STRNEQ (p
, "i8086"))
11900 address_mode
= mode_16bit
;
11901 priv
.orig_sizeflag
= 0;
11903 else if (CONST_STRNEQ (p
, "intel"))
11906 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
11907 intel_mnemonic
= 1;
11909 else if (CONST_STRNEQ (p
, "att"))
11912 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
11913 intel_mnemonic
= 0;
11915 else if (CONST_STRNEQ (p
, "addr"))
11917 if (address_mode
== mode_64bit
)
11919 if (p
[4] == '3' && p
[5] == '2')
11920 priv
.orig_sizeflag
&= ~AFLAG
;
11921 else if (p
[4] == '6' && p
[5] == '4')
11922 priv
.orig_sizeflag
|= AFLAG
;
11926 if (p
[4] == '1' && p
[5] == '6')
11927 priv
.orig_sizeflag
&= ~AFLAG
;
11928 else if (p
[4] == '3' && p
[5] == '2')
11929 priv
.orig_sizeflag
|= AFLAG
;
11932 else if (CONST_STRNEQ (p
, "data"))
11934 if (p
[4] == '1' && p
[5] == '6')
11935 priv
.orig_sizeflag
&= ~DFLAG
;
11936 else if (p
[4] == '3' && p
[5] == '2')
11937 priv
.orig_sizeflag
|= DFLAG
;
11939 else if (CONST_STRNEQ (p
, "suffix"))
11940 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
11942 p
= strchr (p
, ',');
11947 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
11949 (*info
->fprintf_func
) (info
->stream
,
11950 _("64-bit address is disabled"));
11956 names64
= intel_names64
;
11957 names32
= intel_names32
;
11958 names16
= intel_names16
;
11959 names8
= intel_names8
;
11960 names8rex
= intel_names8rex
;
11961 names_seg
= intel_names_seg
;
11962 names_mm
= intel_names_mm
;
11963 names_bnd
= intel_names_bnd
;
11964 names_xmm
= intel_names_xmm
;
11965 names_ymm
= intel_names_ymm
;
11966 names_zmm
= intel_names_zmm
;
11967 index64
= intel_index64
;
11968 index32
= intel_index32
;
11969 names_mask
= intel_names_mask
;
11970 index16
= intel_index16
;
11973 separator_char
= '+';
11978 names64
= att_names64
;
11979 names32
= att_names32
;
11980 names16
= att_names16
;
11981 names8
= att_names8
;
11982 names8rex
= att_names8rex
;
11983 names_seg
= att_names_seg
;
11984 names_mm
= att_names_mm
;
11985 names_bnd
= att_names_bnd
;
11986 names_xmm
= att_names_xmm
;
11987 names_ymm
= att_names_ymm
;
11988 names_zmm
= att_names_zmm
;
11989 index64
= att_index64
;
11990 index32
= att_index32
;
11991 names_mask
= att_names_mask
;
11992 index16
= att_index16
;
11995 separator_char
= ',';
11999 /* The output looks better if we put 7 bytes on a line, since that
12000 puts most long word instructions on a single line. Use 8 bytes
12002 if ((info
->mach
& bfd_mach_l1om
) != 0)
12003 info
->bytes_per_line
= 8;
12005 info
->bytes_per_line
= 7;
12007 info
->private_data
= &priv
;
12008 priv
.max_fetched
= priv
.the_buffer
;
12009 priv
.insn_start
= pc
;
12012 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12020 start_codep
= priv
.the_buffer
;
12021 codep
= priv
.the_buffer
;
12023 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
12027 /* Getting here means we tried for data but didn't get it. That
12028 means we have an incomplete instruction of some sort. Just
12029 print the first byte as a prefix or a .byte pseudo-op. */
12030 if (codep
> priv
.the_buffer
)
12032 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
12034 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
12037 /* Just print the first byte as a .byte instruction. */
12038 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
12039 (unsigned int) priv
.the_buffer
[0]);
12049 sizeflag
= priv
.orig_sizeflag
;
12051 if (!ckprefix () || rex_used
)
12053 /* Too many prefixes or unused REX prefixes. */
12055 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
12057 (*info
->fprintf_func
) (info
->stream
, "%s%s",
12059 prefix_name (all_prefixes
[i
], sizeflag
));
12063 insn_codep
= codep
;
12065 FETCH_DATA (info
, codep
+ 1);
12066 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
12068 if (((prefixes
& PREFIX_FWAIT
)
12069 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
12071 /* Handle prefixes before fwait. */
12072 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
12074 (*info
->fprintf_func
) (info
->stream
, "%s ",
12075 prefix_name (all_prefixes
[i
], sizeflag
));
12076 (*info
->fprintf_func
) (info
->stream
, "fwait");
12080 if (*codep
== 0x0f)
12082 unsigned char threebyte
;
12085 FETCH_DATA (info
, codep
+ 1);
12086 threebyte
= *codep
;
12087 dp
= &dis386_twobyte
[threebyte
];
12088 need_modrm
= twobyte_has_modrm
[*codep
];
12093 dp
= &dis386
[*codep
];
12094 need_modrm
= onebyte_has_modrm
[*codep
];
12098 /* Save sizeflag for printing the extra prefixes later before updating
12099 it for mnemonic and operand processing. The prefix names depend
12100 only on the address mode. */
12101 orig_sizeflag
= sizeflag
;
12102 if (prefixes
& PREFIX_ADDR
)
12104 if ((prefixes
& PREFIX_DATA
))
12110 FETCH_DATA (info
, codep
+ 1);
12111 modrm
.mod
= (*codep
>> 6) & 3;
12112 modrm
.reg
= (*codep
>> 3) & 7;
12113 modrm
.rm
= *codep
& 7;
12119 memset (&vex
, 0, sizeof (vex
));
12121 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
12123 get_sib (info
, sizeflag
);
12124 dofloat (sizeflag
);
12128 dp
= get_valid_dis386 (dp
, info
);
12129 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
12131 get_sib (info
, sizeflag
);
12132 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12135 op_ad
= MAX_OPERANDS
- 1 - i
;
12137 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
12138 /* For EVEX instruction after the last operand masking
12139 should be printed. */
12140 if (i
== 0 && vex
.evex
)
12142 /* Don't print {%k0}. */
12143 if (vex
.mask_register_specifier
)
12146 oappend (names_mask
[vex
.mask_register_specifier
]);
12156 /* Check if the REX prefix is used. */
12157 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
12158 all_prefixes
[last_rex_prefix
] = 0;
12160 /* Check if the SEG prefix is used. */
12161 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
12162 | PREFIX_FS
| PREFIX_GS
)) != 0
12163 && (used_prefixes
& active_seg_prefix
) != 0)
12164 all_prefixes
[last_seg_prefix
] = 0;
12166 /* Check if the ADDR prefix is used. */
12167 if ((prefixes
& PREFIX_ADDR
) != 0
12168 && (used_prefixes
& PREFIX_ADDR
) != 0)
12169 all_prefixes
[last_addr_prefix
] = 0;
12171 /* Check if the DATA prefix is used. */
12172 if ((prefixes
& PREFIX_DATA
) != 0
12173 && (used_prefixes
& PREFIX_DATA
) != 0)
12174 all_prefixes
[last_data_prefix
] = 0;
12176 /* Print the extra prefixes. */
12178 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12179 if (all_prefixes
[i
])
12182 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
12185 prefix_length
+= strlen (name
) + 1;
12186 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
12189 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12190 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
12191 used by putop and MMX/SSE operand and may be overriden by the
12192 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12194 if (dp
->prefix_requirement
== PREFIX_OPCODE
12195 && dp
!= &bad_opcode
12197 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
12199 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
12201 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
12203 && (used_prefixes
& PREFIX_DATA
) == 0))))
12205 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12206 return end_codep
- priv
.the_buffer
;
12209 /* Check maximum code length. */
12210 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
12212 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12213 return MAX_CODE_LENGTH
;
12216 obufp
= mnemonicendp
;
12217 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
12220 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
12222 /* The enter and bound instructions are printed with operands in the same
12223 order as the intel book; everything else is printed in reverse order. */
12224 if (intel_syntax
|| two_source_ops
)
12228 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12229 op_txt
[i
] = op_out
[i
];
12231 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
12232 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
12234 op_txt
[2] = op_out
[3];
12235 op_txt
[3] = op_out
[2];
12238 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
12240 op_ad
= op_index
[i
];
12241 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
12242 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
12243 riprel
= op_riprel
[i
];
12244 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
12245 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
12250 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12251 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
12255 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12259 (*info
->fprintf_func
) (info
->stream
, ",");
12260 if (op_index
[i
] != -1 && !op_riprel
[i
])
12261 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
12263 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
12267 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12268 if (op_index
[i
] != -1 && op_riprel
[i
])
12270 (*info
->fprintf_func
) (info
->stream
, " # ");
12271 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
12272 + op_address
[op_index
[i
]]), info
);
12275 return codep
- priv
.the_buffer
;
12278 static const char *float_mem
[] = {
12353 static const unsigned char float_mem_mode
[] = {
12428 #define ST { OP_ST, 0 }
12429 #define STi { OP_STi, 0 }
12431 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12432 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12433 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12434 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12435 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12436 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12437 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12438 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12439 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12441 static const struct dis386 float_reg
[][8] = {
12444 { "fadd", { ST
, STi
}, 0 },
12445 { "fmul", { ST
, STi
}, 0 },
12446 { "fcom", { STi
}, 0 },
12447 { "fcomp", { STi
}, 0 },
12448 { "fsub", { ST
, STi
}, 0 },
12449 { "fsubr", { ST
, STi
}, 0 },
12450 { "fdiv", { ST
, STi
}, 0 },
12451 { "fdivr", { ST
, STi
}, 0 },
12455 { "fld", { STi
}, 0 },
12456 { "fxch", { STi
}, 0 },
12466 { "fcmovb", { ST
, STi
}, 0 },
12467 { "fcmove", { ST
, STi
}, 0 },
12468 { "fcmovbe",{ ST
, STi
}, 0 },
12469 { "fcmovu", { ST
, STi
}, 0 },
12477 { "fcmovnb",{ ST
, STi
}, 0 },
12478 { "fcmovne",{ ST
, STi
}, 0 },
12479 { "fcmovnbe",{ ST
, STi
}, 0 },
12480 { "fcmovnu",{ ST
, STi
}, 0 },
12482 { "fucomi", { ST
, STi
}, 0 },
12483 { "fcomi", { ST
, STi
}, 0 },
12488 { "fadd", { STi
, ST
}, 0 },
12489 { "fmul", { STi
, ST
}, 0 },
12492 { "fsub{!M|r}", { STi
, ST
}, 0 },
12493 { "fsub{M|}", { STi
, ST
}, 0 },
12494 { "fdiv{!M|r}", { STi
, ST
}, 0 },
12495 { "fdiv{M|}", { STi
, ST
}, 0 },
12499 { "ffree", { STi
}, 0 },
12501 { "fst", { STi
}, 0 },
12502 { "fstp", { STi
}, 0 },
12503 { "fucom", { STi
}, 0 },
12504 { "fucomp", { STi
}, 0 },
12510 { "faddp", { STi
, ST
}, 0 },
12511 { "fmulp", { STi
, ST
}, 0 },
12514 { "fsub{!M|r}p", { STi
, ST
}, 0 },
12515 { "fsub{M|}p", { STi
, ST
}, 0 },
12516 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
12517 { "fdiv{M|}p", { STi
, ST
}, 0 },
12521 { "ffreep", { STi
}, 0 },
12526 { "fucomip", { ST
, STi
}, 0 },
12527 { "fcomip", { ST
, STi
}, 0 },
12532 static char *fgrps
[][8] = {
12535 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12540 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12545 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12550 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12555 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12560 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12565 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12570 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12571 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12576 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12581 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12586 swap_operand (void)
12588 mnemonicendp
[0] = '.';
12589 mnemonicendp
[1] = 's';
12594 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
12595 int sizeflag ATTRIBUTE_UNUSED
)
12597 /* Skip mod/rm byte. */
12603 dofloat (int sizeflag
)
12605 const struct dis386
*dp
;
12606 unsigned char floatop
;
12608 floatop
= codep
[-1];
12610 if (modrm
.mod
!= 3)
12612 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
12614 putop (float_mem
[fp_indx
], sizeflag
);
12617 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
12620 /* Skip mod/rm byte. */
12624 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
12625 if (dp
->name
== NULL
)
12627 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
12629 /* Instruction fnstsw is only one with strange arg. */
12630 if (floatop
== 0xdf && codep
[-1] == 0xe0)
12631 strcpy (op_out
[0], names16
[0]);
12635 putop (dp
->name
, sizeflag
);
12640 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
12645 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
12649 /* Like oappend (below), but S is a string starting with '%'.
12650 In Intel syntax, the '%' is elided. */
12652 oappend_maybe_intel (const char *s
)
12654 oappend (s
+ intel_syntax
);
12658 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12660 oappend_maybe_intel ("%st");
12664 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12666 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
12667 oappend_maybe_intel (scratchbuf
);
12670 /* Capital letters in template are macros. */
12672 putop (const char *in_template
, int sizeflag
)
12677 unsigned int l
= 0, len
= 1;
12680 #define SAVE_LAST(c) \
12681 if (l < len && l < sizeof (last)) \
12686 for (p
= in_template
; *p
; p
++)
12702 while (*++p
!= '|')
12703 if (*p
== '}' || *p
== '\0')
12706 /* Fall through. */
12711 while (*++p
!= '}')
12722 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12726 if (l
== 0 && len
== 1)
12731 if (sizeflag
& SUFFIX_ALWAYS
)
12744 if (address_mode
== mode_64bit
12745 && !(prefixes
& PREFIX_ADDR
))
12756 if (intel_syntax
&& !alt
)
12758 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
12760 if (sizeflag
& DFLAG
)
12761 *obufp
++ = intel_syntax
? 'd' : 'l';
12763 *obufp
++ = intel_syntax
? 'w' : 's';
12764 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12768 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12771 if (modrm
.mod
== 3)
12777 if (sizeflag
& DFLAG
)
12778 *obufp
++ = intel_syntax
? 'd' : 'l';
12781 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12787 case 'E': /* For jcxz/jecxz */
12788 if (address_mode
== mode_64bit
)
12790 if (sizeflag
& AFLAG
)
12796 if (sizeflag
& AFLAG
)
12798 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12803 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
12805 if (sizeflag
& AFLAG
)
12806 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
12808 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
12809 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12813 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
12815 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12819 if (!(rex
& REX_W
))
12820 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12825 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
12826 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
12828 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
12831 if (prefixes
& PREFIX_DS
)
12850 if (l
!= 0 || len
!= 1)
12852 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
12857 if (!need_vex
|| !vex
.evex
)
12860 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
12862 switch (vex
.length
)
12880 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
12885 /* Fall through. */
12888 if (l
!= 0 || len
!= 1)
12896 if (sizeflag
& SUFFIX_ALWAYS
)
12900 if (intel_mnemonic
!= cond
)
12904 if ((prefixes
& PREFIX_FWAIT
) == 0)
12907 used_prefixes
|= PREFIX_FWAIT
;
12913 else if (intel_syntax
&& (sizeflag
& DFLAG
))
12917 if (!(rex
& REX_W
))
12918 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12922 && address_mode
== mode_64bit
12923 && isa64
== intel64
)
12928 /* Fall through. */
12931 && address_mode
== mode_64bit
12932 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12937 /* Fall through. */
12940 if (l
== 0 && len
== 1)
12945 if ((rex
& REX_W
) == 0
12946 && (prefixes
& PREFIX_DATA
))
12948 if ((sizeflag
& DFLAG
) == 0)
12950 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12954 if ((prefixes
& PREFIX_DATA
)
12956 || (sizeflag
& SUFFIX_ALWAYS
))
12963 if (sizeflag
& DFLAG
)
12967 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12973 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
12979 if ((prefixes
& PREFIX_DATA
)
12981 || (sizeflag
& SUFFIX_ALWAYS
))
12988 if (sizeflag
& DFLAG
)
12989 *obufp
++ = intel_syntax
? 'd' : 'l';
12992 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13000 if (address_mode
== mode_64bit
13001 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13003 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13007 /* Fall through. */
13010 if (l
== 0 && len
== 1)
13013 if (intel_syntax
&& !alt
)
13016 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13022 if (sizeflag
& DFLAG
)
13023 *obufp
++ = intel_syntax
? 'd' : 'l';
13026 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13032 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13038 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
13053 else if (sizeflag
& DFLAG
)
13062 if (intel_syntax
&& !p
[1]
13063 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
13065 if (!(rex
& REX_W
))
13066 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13069 if (l
== 0 && len
== 1)
13073 if (address_mode
== mode_64bit
13074 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13076 if (sizeflag
& SUFFIX_ALWAYS
)
13098 /* Fall through. */
13101 if (l
== 0 && len
== 1)
13106 if (sizeflag
& SUFFIX_ALWAYS
)
13112 if (sizeflag
& DFLAG
)
13116 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13130 if (address_mode
== mode_64bit
13131 && !(prefixes
& PREFIX_ADDR
))
13142 if (l
!= 0 || len
!= 1)
13147 if (need_vex
&& vex
.prefix
)
13149 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
13156 if (prefixes
& PREFIX_DATA
)
13160 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13164 if (l
== 0 && len
== 1)
13168 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
13176 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
13178 switch (vex
.length
)
13194 if (l
== 0 && len
== 1)
13196 /* operand size flag for cwtl, cbtw */
13205 else if (sizeflag
& DFLAG
)
13209 if (!(rex
& REX_W
))
13210 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13217 && last
[0] != 'L'))
13224 if (last
[0] == 'X')
13225 *obufp
++ = vex
.w
? 'd': 's';
13227 *obufp
++ = vex
.w
? 'q': 'd';
13233 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13235 if (sizeflag
& DFLAG
)
13239 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13245 if (address_mode
== mode_64bit
13246 && (isa64
== intel64
13247 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
13249 else if ((prefixes
& PREFIX_DATA
))
13251 if (!(sizeflag
& DFLAG
))
13253 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13260 mnemonicendp
= obufp
;
13265 oappend (const char *s
)
13267 obufp
= stpcpy (obufp
, s
);
13273 /* Only print the active segment register. */
13274 if (!active_seg_prefix
)
13277 used_prefixes
|= active_seg_prefix
;
13278 switch (active_seg_prefix
)
13281 oappend_maybe_intel ("%cs:");
13284 oappend_maybe_intel ("%ds:");
13287 oappend_maybe_intel ("%ss:");
13290 oappend_maybe_intel ("%es:");
13293 oappend_maybe_intel ("%fs:");
13296 oappend_maybe_intel ("%gs:");
13304 OP_indirE (int bytemode
, int sizeflag
)
13308 OP_E (bytemode
, sizeflag
);
13312 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
13314 if (address_mode
== mode_64bit
)
13322 sprintf_vma (tmp
, disp
);
13323 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
13324 strcpy (buf
+ 2, tmp
+ i
);
13328 bfd_signed_vma v
= disp
;
13335 /* Check for possible overflow on 0x8000000000000000. */
13338 strcpy (buf
, "9223372036854775808");
13352 tmp
[28 - i
] = (v
% 10) + '0';
13356 strcpy (buf
, tmp
+ 29 - i
);
13362 sprintf (buf
, "0x%x", (unsigned int) disp
);
13364 sprintf (buf
, "%d", (int) disp
);
13368 /* Put DISP in BUF as signed hex number. */
13371 print_displacement (char *buf
, bfd_vma disp
)
13373 bfd_signed_vma val
= disp
;
13382 /* Check for possible overflow. */
13385 switch (address_mode
)
13388 strcpy (buf
+ j
, "0x8000000000000000");
13391 strcpy (buf
+ j
, "0x80000000");
13394 strcpy (buf
+ j
, "0x8000");
13404 sprintf_vma (tmp
, (bfd_vma
) val
);
13405 for (i
= 0; tmp
[i
] == '0'; i
++)
13407 if (tmp
[i
] == '\0')
13409 strcpy (buf
+ j
, tmp
+ i
);
13413 intel_operand_size (int bytemode
, int sizeflag
)
13417 && (bytemode
== x_mode
13418 || bytemode
== evex_half_bcst_xmmq_mode
))
13421 oappend ("QWORD PTR ");
13423 oappend ("DWORD PTR ");
13432 oappend ("BYTE PTR ");
13437 oappend ("WORD PTR ");
13440 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13442 oappend ("QWORD PTR ");
13445 /* Fall through. */
13447 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13449 oappend ("QWORD PTR ");
13452 /* Fall through. */
13458 oappend ("QWORD PTR ");
13461 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
13462 oappend ("DWORD PTR ");
13464 oappend ("WORD PTR ");
13465 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13469 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13471 oappend ("WORD PTR ");
13472 if (!(rex
& REX_W
))
13473 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13476 if (sizeflag
& DFLAG
)
13477 oappend ("QWORD PTR ");
13479 oappend ("DWORD PTR ");
13480 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13483 case d_scalar_mode
:
13484 case d_scalar_swap_mode
:
13487 oappend ("DWORD PTR ");
13490 case q_scalar_mode
:
13491 case q_scalar_swap_mode
:
13493 oappend ("QWORD PTR ");
13497 if (address_mode
== mode_64bit
)
13498 oappend ("QWORD PTR ");
13500 oappend ("DWORD PTR ");
13503 if (sizeflag
& DFLAG
)
13504 oappend ("FWORD PTR ");
13506 oappend ("DWORD PTR ");
13507 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13510 oappend ("TBYTE PTR ");
13514 case evex_x_gscat_mode
:
13515 case evex_x_nobcst_mode
:
13516 case b_scalar_mode
:
13517 case w_scalar_mode
:
13520 switch (vex
.length
)
13523 oappend ("XMMWORD PTR ");
13526 oappend ("YMMWORD PTR ");
13529 oappend ("ZMMWORD PTR ");
13536 oappend ("XMMWORD PTR ");
13539 oappend ("XMMWORD PTR ");
13542 oappend ("YMMWORD PTR ");
13545 case evex_half_bcst_xmmq_mode
:
13549 switch (vex
.length
)
13552 oappend ("QWORD PTR ");
13555 oappend ("XMMWORD PTR ");
13558 oappend ("YMMWORD PTR ");
13568 switch (vex
.length
)
13573 oappend ("BYTE PTR ");
13583 switch (vex
.length
)
13588 oappend ("WORD PTR ");
13598 switch (vex
.length
)
13603 oappend ("DWORD PTR ");
13613 switch (vex
.length
)
13618 oappend ("QWORD PTR ");
13628 switch (vex
.length
)
13631 oappend ("WORD PTR ");
13634 oappend ("DWORD PTR ");
13637 oappend ("QWORD PTR ");
13647 switch (vex
.length
)
13650 oappend ("DWORD PTR ");
13653 oappend ("QWORD PTR ");
13656 oappend ("XMMWORD PTR ");
13666 switch (vex
.length
)
13669 oappend ("QWORD PTR ");
13672 oappend ("YMMWORD PTR ");
13675 oappend ("ZMMWORD PTR ");
13685 switch (vex
.length
)
13689 oappend ("XMMWORD PTR ");
13696 oappend ("OWORD PTR ");
13699 case vex_w_dq_mode
:
13700 case vex_scalar_w_dq_mode
:
13705 oappend ("QWORD PTR ");
13707 oappend ("DWORD PTR ");
13709 case vex_vsib_d_w_dq_mode
:
13710 case vex_vsib_q_w_dq_mode
:
13717 oappend ("QWORD PTR ");
13719 oappend ("DWORD PTR ");
13723 switch (vex
.length
)
13726 oappend ("XMMWORD PTR ");
13729 oappend ("YMMWORD PTR ");
13732 oappend ("ZMMWORD PTR ");
13739 case vex_vsib_q_w_d_mode
:
13740 case vex_vsib_d_w_d_mode
:
13741 if (!need_vex
|| !vex
.evex
)
13744 switch (vex
.length
)
13747 oappend ("QWORD PTR ");
13750 oappend ("XMMWORD PTR ");
13753 oappend ("YMMWORD PTR ");
13761 if (!need_vex
|| vex
.length
!= 128)
13764 oappend ("DWORD PTR ");
13766 oappend ("BYTE PTR ");
13772 oappend ("QWORD PTR ");
13774 oappend ("WORD PTR ");
13784 OP_E_register (int bytemode
, int sizeflag
)
13786 int reg
= modrm
.rm
;
13787 const char **names
;
13793 if ((sizeflag
& SUFFIX_ALWAYS
)
13794 && (bytemode
== b_swap_mode
13795 || bytemode
== bnd_swap_mode
13796 || bytemode
== v_swap_mode
))
13822 names
= address_mode
== mode_64bit
? names64
: names32
;
13825 case bnd_swap_mode
:
13834 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13839 /* Fall through. */
13841 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13847 /* Fall through. */
13860 if ((sizeflag
& DFLAG
)
13861 || (bytemode
!= v_mode
13862 && bytemode
!= v_swap_mode
))
13866 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13870 names
= (address_mode
== mode_64bit
13871 ? names64
: names32
);
13872 if (!(prefixes
& PREFIX_ADDR
))
13873 names
= (address_mode
== mode_16bit
13874 ? names16
: names
);
13877 /* Remove "addr16/addr32". */
13878 all_prefixes
[last_addr_prefix
] = 0;
13879 names
= (address_mode
!= mode_32bit
13880 ? names32
: names16
);
13881 used_prefixes
|= PREFIX_ADDR
;
13891 names
= names_mask
;
13896 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13899 oappend (names
[reg
]);
13903 OP_E_memory (int bytemode
, int sizeflag
)
13906 int add
= (rex
& REX_B
) ? 8 : 0;
13912 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
13914 && bytemode
!= x_mode
13915 && bytemode
!= xmmq_mode
13916 && bytemode
!= evex_half_bcst_xmmq_mode
)
13931 case vex_vsib_d_w_dq_mode
:
13932 case vex_vsib_d_w_d_mode
:
13933 case vex_vsib_q_w_dq_mode
:
13934 case vex_vsib_q_w_d_mode
:
13935 case evex_x_gscat_mode
:
13937 shift
= vex
.w
? 3 : 2;
13940 case evex_half_bcst_xmmq_mode
:
13944 shift
= vex
.w
? 3 : 2;
13947 /* Fall through. */
13951 case evex_x_nobcst_mode
:
13953 switch (vex
.length
)
13976 case q_scalar_mode
:
13978 case q_scalar_swap_mode
:
13984 case d_scalar_mode
:
13986 case d_scalar_swap_mode
:
13989 case w_scalar_mode
:
13993 case b_scalar_mode
:
13998 shift
= address_mode
== mode_64bit
? 3 : 2;
14003 /* Make necessary corrections to shift for modes that need it.
14004 For these modes we currently have shift 4, 5 or 6 depending on
14005 vex.length (it corresponds to xmmword, ymmword or zmmword
14006 operand). We might want to make it 3, 4 or 5 (e.g. for
14007 xmmq_mode). In case of broadcast enabled the corrections
14008 aren't needed, as element size is always 32 or 64 bits. */
14010 && (bytemode
== xmmq_mode
14011 || bytemode
== evex_half_bcst_xmmq_mode
))
14013 else if (bytemode
== xmmqd_mode
)
14015 else if (bytemode
== xmmdw_mode
)
14017 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
14025 intel_operand_size (bytemode
, sizeflag
);
14028 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14030 /* 32/64 bit address mode */
14040 int addr32flag
= !((sizeflag
& AFLAG
)
14041 || bytemode
== v_bnd_mode
14042 || bytemode
== v_bndmk_mode
14043 || bytemode
== bnd_mode
14044 || bytemode
== bnd_swap_mode
);
14045 const char **indexes64
= names64
;
14046 const char **indexes32
= names32
;
14056 vindex
= sib
.index
;
14062 case vex_vsib_d_w_dq_mode
:
14063 case vex_vsib_d_w_d_mode
:
14064 case vex_vsib_q_w_dq_mode
:
14065 case vex_vsib_q_w_d_mode
:
14075 switch (vex
.length
)
14078 indexes64
= indexes32
= names_xmm
;
14082 || bytemode
== vex_vsib_q_w_dq_mode
14083 || bytemode
== vex_vsib_q_w_d_mode
)
14084 indexes64
= indexes32
= names_ymm
;
14086 indexes64
= indexes32
= names_xmm
;
14090 || bytemode
== vex_vsib_q_w_dq_mode
14091 || bytemode
== vex_vsib_q_w_d_mode
)
14092 indexes64
= indexes32
= names_zmm
;
14094 indexes64
= indexes32
= names_ymm
;
14101 haveindex
= vindex
!= 4;
14108 rbase
= base
+ add
;
14116 if (address_mode
== mode_64bit
&& !havesib
)
14119 if (riprel
&& bytemode
== v_bndmk_mode
)
14127 FETCH_DATA (the_info
, codep
+ 1);
14129 if ((disp
& 0x80) != 0)
14131 if (vex
.evex
&& shift
> 0)
14144 && address_mode
!= mode_16bit
)
14146 if (address_mode
== mode_64bit
)
14148 /* Display eiz instead of addr32. */
14149 needindex
= addr32flag
;
14154 /* In 32-bit mode, we need index register to tell [offset]
14155 from [eiz*1 + offset]. */
14160 havedisp
= (havebase
14162 || (havesib
&& (haveindex
|| scale
!= 0)));
14165 if (modrm
.mod
!= 0 || base
== 5)
14167 if (havedisp
|| riprel
)
14168 print_displacement (scratchbuf
, disp
);
14170 print_operand_value (scratchbuf
, 1, disp
);
14171 oappend (scratchbuf
);
14175 oappend (!addr32flag
? "(%rip)" : "(%eip)");
14179 if ((havebase
|| haveindex
|| needaddr32
|| riprel
)
14180 && (bytemode
!= v_bnd_mode
)
14181 && (bytemode
!= v_bndmk_mode
)
14182 && (bytemode
!= bnd_mode
)
14183 && (bytemode
!= bnd_swap_mode
))
14184 used_prefixes
|= PREFIX_ADDR
;
14186 if (havedisp
|| (intel_syntax
&& riprel
))
14188 *obufp
++ = open_char
;
14189 if (intel_syntax
&& riprel
)
14192 oappend (!addr32flag
? "rip" : "eip");
14196 oappend (address_mode
== mode_64bit
&& !addr32flag
14197 ? names64
[rbase
] : names32
[rbase
]);
14200 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14201 print index to tell base + index from base. */
14205 || (havebase
&& base
!= ESP_REG_NUM
))
14207 if (!intel_syntax
|| havebase
)
14209 *obufp
++ = separator_char
;
14213 oappend (address_mode
== mode_64bit
&& !addr32flag
14214 ? indexes64
[vindex
] : indexes32
[vindex
]);
14216 oappend (address_mode
== mode_64bit
&& !addr32flag
14217 ? index64
: index32
);
14219 *obufp
++ = scale_char
;
14221 sprintf (scratchbuf
, "%d", 1 << scale
);
14222 oappend (scratchbuf
);
14226 && (disp
|| modrm
.mod
!= 0 || base
== 5))
14228 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
14233 else if (modrm
.mod
!= 1 && disp
!= -disp
)
14237 disp
= - (bfd_signed_vma
) disp
;
14241 print_displacement (scratchbuf
, disp
);
14243 print_operand_value (scratchbuf
, 1, disp
);
14244 oappend (scratchbuf
);
14247 *obufp
++ = close_char
;
14250 else if (intel_syntax
)
14252 if (modrm
.mod
!= 0 || base
== 5)
14254 if (!active_seg_prefix
)
14256 oappend (names_seg
[ds_reg
- es_reg
]);
14259 print_operand_value (scratchbuf
, 1, disp
);
14260 oappend (scratchbuf
);
14266 /* 16 bit address mode */
14267 used_prefixes
|= prefixes
& PREFIX_ADDR
;
14274 if ((disp
& 0x8000) != 0)
14279 FETCH_DATA (the_info
, codep
+ 1);
14281 if ((disp
& 0x80) != 0)
14283 if (vex
.evex
&& shift
> 0)
14288 if ((disp
& 0x8000) != 0)
14294 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
14296 print_displacement (scratchbuf
, disp
);
14297 oappend (scratchbuf
);
14300 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
14302 *obufp
++ = open_char
;
14304 oappend (index16
[modrm
.rm
]);
14306 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
14308 if ((bfd_signed_vma
) disp
>= 0)
14313 else if (modrm
.mod
!= 1)
14317 disp
= - (bfd_signed_vma
) disp
;
14320 print_displacement (scratchbuf
, disp
);
14321 oappend (scratchbuf
);
14324 *obufp
++ = close_char
;
14327 else if (intel_syntax
)
14329 if (!active_seg_prefix
)
14331 oappend (names_seg
[ds_reg
- es_reg
]);
14334 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
14335 oappend (scratchbuf
);
14338 if (vex
.evex
&& vex
.b
14339 && (bytemode
== x_mode
14340 || bytemode
== xmmq_mode
14341 || bytemode
== evex_half_bcst_xmmq_mode
))
14344 || bytemode
== xmmq_mode
14345 || bytemode
== evex_half_bcst_xmmq_mode
)
14347 switch (vex
.length
)
14350 oappend ("{1to2}");
14353 oappend ("{1to4}");
14356 oappend ("{1to8}");
14364 switch (vex
.length
)
14367 oappend ("{1to4}");
14370 oappend ("{1to8}");
14373 oappend ("{1to16}");
14383 OP_E (int bytemode
, int sizeflag
)
14385 /* Skip mod/rm byte. */
14389 if (modrm
.mod
== 3)
14390 OP_E_register (bytemode
, sizeflag
);
14392 OP_E_memory (bytemode
, sizeflag
);
14396 OP_G (int bytemode
, int sizeflag
)
14399 const char **names
;
14408 oappend (names8rex
[modrm
.reg
+ add
]);
14410 oappend (names8
[modrm
.reg
+ add
]);
14413 oappend (names16
[modrm
.reg
+ add
]);
14418 oappend (names32
[modrm
.reg
+ add
]);
14421 oappend (names64
[modrm
.reg
+ add
]);
14424 if (modrm
.reg
> 0x3)
14429 oappend (names_bnd
[modrm
.reg
]);
14438 oappend (names64
[modrm
.reg
+ add
]);
14441 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
14442 oappend (names32
[modrm
.reg
+ add
]);
14444 oappend (names16
[modrm
.reg
+ add
]);
14445 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14449 names
= (address_mode
== mode_64bit
14450 ? names64
: names32
);
14451 if (!(prefixes
& PREFIX_ADDR
))
14453 if (address_mode
== mode_16bit
)
14458 /* Remove "addr16/addr32". */
14459 all_prefixes
[last_addr_prefix
] = 0;
14460 names
= (address_mode
!= mode_32bit
14461 ? names32
: names16
);
14462 used_prefixes
|= PREFIX_ADDR
;
14464 oappend (names
[modrm
.reg
+ add
]);
14467 if (address_mode
== mode_64bit
)
14468 oappend (names64
[modrm
.reg
+ add
]);
14470 oappend (names32
[modrm
.reg
+ add
]);
14474 if ((modrm
.reg
+ add
) > 0x7)
14479 oappend (names_mask
[modrm
.reg
+ add
]);
14482 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14495 FETCH_DATA (the_info
, codep
+ 8);
14496 a
= *codep
++ & 0xff;
14497 a
|= (*codep
++ & 0xff) << 8;
14498 a
|= (*codep
++ & 0xff) << 16;
14499 a
|= (*codep
++ & 0xffu
) << 24;
14500 b
= *codep
++ & 0xff;
14501 b
|= (*codep
++ & 0xff) << 8;
14502 b
|= (*codep
++ & 0xff) << 16;
14503 b
|= (*codep
++ & 0xffu
) << 24;
14504 x
= a
+ ((bfd_vma
) b
<< 32);
14512 static bfd_signed_vma
14515 bfd_signed_vma x
= 0;
14517 FETCH_DATA (the_info
, codep
+ 4);
14518 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14519 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14520 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14521 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14525 static bfd_signed_vma
14528 bfd_signed_vma x
= 0;
14530 FETCH_DATA (the_info
, codep
+ 4);
14531 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14532 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14533 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14534 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14536 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
14546 FETCH_DATA (the_info
, codep
+ 2);
14547 x
= *codep
++ & 0xff;
14548 x
|= (*codep
++ & 0xff) << 8;
14553 set_op (bfd_vma op
, int riprel
)
14555 op_index
[op_ad
] = op_ad
;
14556 if (address_mode
== mode_64bit
)
14558 op_address
[op_ad
] = op
;
14559 op_riprel
[op_ad
] = riprel
;
14563 /* Mask to get a 32-bit address. */
14564 op_address
[op_ad
] = op
& 0xffffffff;
14565 op_riprel
[op_ad
] = riprel
& 0xffffffff;
14570 OP_REG (int code
, int sizeflag
)
14577 case es_reg
: case ss_reg
: case cs_reg
:
14578 case ds_reg
: case fs_reg
: case gs_reg
:
14579 oappend (names_seg
[code
- es_reg
]);
14591 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14592 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14593 s
= names16
[code
- ax_reg
+ add
];
14595 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14596 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14599 s
= names8rex
[code
- al_reg
+ add
];
14601 s
= names8
[code
- al_reg
];
14603 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
14604 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
14605 if (address_mode
== mode_64bit
14606 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14608 s
= names64
[code
- rAX_reg
+ add
];
14611 code
+= eAX_reg
- rAX_reg
;
14612 /* Fall through. */
14613 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14614 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14617 s
= names64
[code
- eAX_reg
+ add
];
14620 if (sizeflag
& DFLAG
)
14621 s
= names32
[code
- eAX_reg
+ add
];
14623 s
= names16
[code
- eAX_reg
+ add
];
14624 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14628 s
= INTERNAL_DISASSEMBLER_ERROR
;
14635 OP_IMREG (int code
, int sizeflag
)
14647 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14648 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14649 s
= names16
[code
- ax_reg
];
14651 case es_reg
: case ss_reg
: case cs_reg
:
14652 case ds_reg
: case fs_reg
: case gs_reg
:
14653 s
= names_seg
[code
- es_reg
];
14655 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14656 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14659 s
= names8rex
[code
- al_reg
];
14661 s
= names8
[code
- al_reg
];
14663 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14664 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14667 s
= names64
[code
- eAX_reg
];
14670 if (sizeflag
& DFLAG
)
14671 s
= names32
[code
- eAX_reg
];
14673 s
= names16
[code
- eAX_reg
];
14674 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14677 case z_mode_ax_reg
:
14678 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14682 if (!(rex
& REX_W
))
14683 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14686 s
= INTERNAL_DISASSEMBLER_ERROR
;
14693 OP_I (int bytemode
, int sizeflag
)
14696 bfd_signed_vma mask
= -1;
14701 FETCH_DATA (the_info
, codep
+ 1);
14706 if (address_mode
== mode_64bit
)
14711 /* Fall through. */
14718 if (sizeflag
& DFLAG
)
14728 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14740 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14745 scratchbuf
[0] = '$';
14746 print_operand_value (scratchbuf
+ 1, 1, op
);
14747 oappend_maybe_intel (scratchbuf
);
14748 scratchbuf
[0] = '\0';
14752 OP_I64 (int bytemode
, int sizeflag
)
14755 bfd_signed_vma mask
= -1;
14757 if (address_mode
!= mode_64bit
)
14759 OP_I (bytemode
, sizeflag
);
14766 FETCH_DATA (the_info
, codep
+ 1);
14776 if (sizeflag
& DFLAG
)
14786 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14794 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14799 scratchbuf
[0] = '$';
14800 print_operand_value (scratchbuf
+ 1, 1, op
);
14801 oappend_maybe_intel (scratchbuf
);
14802 scratchbuf
[0] = '\0';
14806 OP_sI (int bytemode
, int sizeflag
)
14814 FETCH_DATA (the_info
, codep
+ 1);
14816 if ((op
& 0x80) != 0)
14818 if (bytemode
== b_T_mode
)
14820 if (address_mode
!= mode_64bit
14821 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14823 /* The operand-size prefix is overridden by a REX prefix. */
14824 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14832 if (!(rex
& REX_W
))
14834 if (sizeflag
& DFLAG
)
14842 /* The operand-size prefix is overridden by a REX prefix. */
14843 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14849 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14853 scratchbuf
[0] = '$';
14854 print_operand_value (scratchbuf
+ 1, 1, op
);
14855 oappend_maybe_intel (scratchbuf
);
14859 OP_J (int bytemode
, int sizeflag
)
14863 bfd_vma segment
= 0;
14868 FETCH_DATA (the_info
, codep
+ 1);
14870 if ((disp
& 0x80) != 0)
14874 if (isa64
== amd64
)
14876 if ((sizeflag
& DFLAG
)
14877 || (address_mode
== mode_64bit
14878 && (isa64
!= amd64
|| (rex
& REX_W
))))
14883 if ((disp
& 0x8000) != 0)
14885 /* In 16bit mode, address is wrapped around at 64k within
14886 the same segment. Otherwise, a data16 prefix on a jump
14887 instruction means that the pc is masked to 16 bits after
14888 the displacement is added! */
14890 if ((prefixes
& PREFIX_DATA
) == 0)
14891 segment
= ((start_pc
+ (codep
- start_codep
))
14892 & ~((bfd_vma
) 0xffff));
14894 if (address_mode
!= mode_64bit
14895 || (isa64
== amd64
&& !(rex
& REX_W
)))
14896 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14899 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14902 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
14904 print_operand_value (scratchbuf
, 1, disp
);
14905 oappend (scratchbuf
);
14909 OP_SEG (int bytemode
, int sizeflag
)
14911 if (bytemode
== w_mode
)
14912 oappend (names_seg
[modrm
.reg
]);
14914 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
14918 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
14922 if (sizeflag
& DFLAG
)
14932 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14934 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
14936 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
14937 oappend (scratchbuf
);
14941 OP_OFF (int bytemode
, int sizeflag
)
14945 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14946 intel_operand_size (bytemode
, sizeflag
);
14949 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14956 if (!active_seg_prefix
)
14958 oappend (names_seg
[ds_reg
- es_reg
]);
14962 print_operand_value (scratchbuf
, 1, off
);
14963 oappend (scratchbuf
);
14967 OP_OFF64 (int bytemode
, int sizeflag
)
14971 if (address_mode
!= mode_64bit
14972 || (prefixes
& PREFIX_ADDR
))
14974 OP_OFF (bytemode
, sizeflag
);
14978 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14979 intel_operand_size (bytemode
, sizeflag
);
14986 if (!active_seg_prefix
)
14988 oappend (names_seg
[ds_reg
- es_reg
]);
14992 print_operand_value (scratchbuf
, 1, off
);
14993 oappend (scratchbuf
);
14997 ptr_reg (int code
, int sizeflag
)
15001 *obufp
++ = open_char
;
15002 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
15003 if (address_mode
== mode_64bit
)
15005 if (!(sizeflag
& AFLAG
))
15006 s
= names32
[code
- eAX_reg
];
15008 s
= names64
[code
- eAX_reg
];
15010 else if (sizeflag
& AFLAG
)
15011 s
= names32
[code
- eAX_reg
];
15013 s
= names16
[code
- eAX_reg
];
15015 *obufp
++ = close_char
;
15020 OP_ESreg (int code
, int sizeflag
)
15026 case 0x6d: /* insw/insl */
15027 intel_operand_size (z_mode
, sizeflag
);
15029 case 0xa5: /* movsw/movsl/movsq */
15030 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15031 case 0xab: /* stosw/stosl */
15032 case 0xaf: /* scasw/scasl */
15033 intel_operand_size (v_mode
, sizeflag
);
15036 intel_operand_size (b_mode
, sizeflag
);
15039 oappend_maybe_intel ("%es:");
15040 ptr_reg (code
, sizeflag
);
15044 OP_DSreg (int code
, int sizeflag
)
15050 case 0x6f: /* outsw/outsl */
15051 intel_operand_size (z_mode
, sizeflag
);
15053 case 0xa5: /* movsw/movsl/movsq */
15054 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15055 case 0xad: /* lodsw/lodsl/lodsq */
15056 intel_operand_size (v_mode
, sizeflag
);
15059 intel_operand_size (b_mode
, sizeflag
);
15062 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15063 default segment register DS is printed. */
15064 if (!active_seg_prefix
)
15065 active_seg_prefix
= PREFIX_DS
;
15067 ptr_reg (code
, sizeflag
);
15071 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15079 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
15081 all_prefixes
[last_lock_prefix
] = 0;
15082 used_prefixes
|= PREFIX_LOCK
;
15087 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
15088 oappend_maybe_intel (scratchbuf
);
15092 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15101 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
15103 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
15104 oappend (scratchbuf
);
15108 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15110 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
15111 oappend_maybe_intel (scratchbuf
);
15115 OP_R (int bytemode
, int sizeflag
)
15117 /* Skip mod/rm byte. */
15120 OP_E_register (bytemode
, sizeflag
);
15124 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15126 int reg
= modrm
.reg
;
15127 const char **names
;
15129 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15130 if (prefixes
& PREFIX_DATA
)
15139 oappend (names
[reg
]);
15143 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15145 int reg
= modrm
.reg
;
15146 const char **names
;
15158 && bytemode
!= xmm_mode
15159 && bytemode
!= xmmq_mode
15160 && bytemode
!= evex_half_bcst_xmmq_mode
15161 && bytemode
!= ymm_mode
15162 && bytemode
!= scalar_mode
)
15164 switch (vex
.length
)
15171 || (bytemode
!= vex_vsib_q_w_dq_mode
15172 && bytemode
!= vex_vsib_q_w_d_mode
))
15184 else if (bytemode
== xmmq_mode
15185 || bytemode
== evex_half_bcst_xmmq_mode
)
15187 switch (vex
.length
)
15200 else if (bytemode
== ymm_mode
)
15204 oappend (names
[reg
]);
15208 OP_EM (int bytemode
, int sizeflag
)
15211 const char **names
;
15213 if (modrm
.mod
!= 3)
15216 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
15218 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15219 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15221 OP_E (bytemode
, sizeflag
);
15225 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
15228 /* Skip mod/rm byte. */
15231 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15233 if (prefixes
& PREFIX_DATA
)
15242 oappend (names
[reg
]);
15245 /* cvt* are the only instructions in sse2 which have
15246 both SSE and MMX operands and also have 0x66 prefix
15247 in their opcode. 0x66 was originally used to differentiate
15248 between SSE and MMX instruction(operands). So we have to handle the
15249 cvt* separately using OP_EMC and OP_MXC */
15251 OP_EMC (int bytemode
, int sizeflag
)
15253 if (modrm
.mod
!= 3)
15255 if (intel_syntax
&& bytemode
== v_mode
)
15257 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15258 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15260 OP_E (bytemode
, sizeflag
);
15264 /* Skip mod/rm byte. */
15267 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15268 oappend (names_mm
[modrm
.rm
]);
15272 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15274 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15275 oappend (names_mm
[modrm
.reg
]);
15279 OP_EX (int bytemode
, int sizeflag
)
15282 const char **names
;
15284 /* Skip mod/rm byte. */
15288 if (modrm
.mod
!= 3)
15290 OP_E_memory (bytemode
, sizeflag
);
15305 if ((sizeflag
& SUFFIX_ALWAYS
)
15306 && (bytemode
== x_swap_mode
15307 || bytemode
== d_swap_mode
15308 || bytemode
== d_scalar_swap_mode
15309 || bytemode
== q_swap_mode
15310 || bytemode
== q_scalar_swap_mode
))
15314 && bytemode
!= xmm_mode
15315 && bytemode
!= xmmdw_mode
15316 && bytemode
!= xmmqd_mode
15317 && bytemode
!= xmm_mb_mode
15318 && bytemode
!= xmm_mw_mode
15319 && bytemode
!= xmm_md_mode
15320 && bytemode
!= xmm_mq_mode
15321 && bytemode
!= xmm_mdq_mode
15322 && bytemode
!= xmmq_mode
15323 && bytemode
!= evex_half_bcst_xmmq_mode
15324 && bytemode
!= ymm_mode
15325 && bytemode
!= d_scalar_mode
15326 && bytemode
!= d_scalar_swap_mode
15327 && bytemode
!= q_scalar_mode
15328 && bytemode
!= q_scalar_swap_mode
15329 && bytemode
!= vex_scalar_w_dq_mode
)
15331 switch (vex
.length
)
15346 else if (bytemode
== xmmq_mode
15347 || bytemode
== evex_half_bcst_xmmq_mode
)
15349 switch (vex
.length
)
15362 else if (bytemode
== ymm_mode
)
15366 oappend (names
[reg
]);
15370 OP_MS (int bytemode
, int sizeflag
)
15372 if (modrm
.mod
== 3)
15373 OP_EM (bytemode
, sizeflag
);
15379 OP_XS (int bytemode
, int sizeflag
)
15381 if (modrm
.mod
== 3)
15382 OP_EX (bytemode
, sizeflag
);
15388 OP_M (int bytemode
, int sizeflag
)
15390 if (modrm
.mod
== 3)
15391 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15394 OP_E (bytemode
, sizeflag
);
15398 OP_0f07 (int bytemode
, int sizeflag
)
15400 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
15403 OP_E (bytemode
, sizeflag
);
15406 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15407 32bit mode and "xchg %rax,%rax" in 64bit mode. */
15410 NOP_Fixup1 (int bytemode
, int sizeflag
)
15412 if ((prefixes
& PREFIX_DATA
) != 0
15415 && address_mode
== mode_64bit
))
15416 OP_REG (bytemode
, sizeflag
);
15418 strcpy (obuf
, "nop");
15422 NOP_Fixup2 (int bytemode
, int sizeflag
)
15424 if ((prefixes
& PREFIX_DATA
) != 0
15427 && address_mode
== mode_64bit
))
15428 OP_IMREG (bytemode
, sizeflag
);
15431 static const char *const Suffix3DNow
[] = {
15432 /* 00 */ NULL
, NULL
, NULL
, NULL
,
15433 /* 04 */ NULL
, NULL
, NULL
, NULL
,
15434 /* 08 */ NULL
, NULL
, NULL
, NULL
,
15435 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
15436 /* 10 */ NULL
, NULL
, NULL
, NULL
,
15437 /* 14 */ NULL
, NULL
, NULL
, NULL
,
15438 /* 18 */ NULL
, NULL
, NULL
, NULL
,
15439 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
15440 /* 20 */ NULL
, NULL
, NULL
, NULL
,
15441 /* 24 */ NULL
, NULL
, NULL
, NULL
,
15442 /* 28 */ NULL
, NULL
, NULL
, NULL
,
15443 /* 2C */ NULL
, NULL
, NULL
, NULL
,
15444 /* 30 */ NULL
, NULL
, NULL
, NULL
,
15445 /* 34 */ NULL
, NULL
, NULL
, NULL
,
15446 /* 38 */ NULL
, NULL
, NULL
, NULL
,
15447 /* 3C */ NULL
, NULL
, NULL
, NULL
,
15448 /* 40 */ NULL
, NULL
, NULL
, NULL
,
15449 /* 44 */ NULL
, NULL
, NULL
, NULL
,
15450 /* 48 */ NULL
, NULL
, NULL
, NULL
,
15451 /* 4C */ NULL
, NULL
, NULL
, NULL
,
15452 /* 50 */ NULL
, NULL
, NULL
, NULL
,
15453 /* 54 */ NULL
, NULL
, NULL
, NULL
,
15454 /* 58 */ NULL
, NULL
, NULL
, NULL
,
15455 /* 5C */ NULL
, NULL
, NULL
, NULL
,
15456 /* 60 */ NULL
, NULL
, NULL
, NULL
,
15457 /* 64 */ NULL
, NULL
, NULL
, NULL
,
15458 /* 68 */ NULL
, NULL
, NULL
, NULL
,
15459 /* 6C */ NULL
, NULL
, NULL
, NULL
,
15460 /* 70 */ NULL
, NULL
, NULL
, NULL
,
15461 /* 74 */ NULL
, NULL
, NULL
, NULL
,
15462 /* 78 */ NULL
, NULL
, NULL
, NULL
,
15463 /* 7C */ NULL
, NULL
, NULL
, NULL
,
15464 /* 80 */ NULL
, NULL
, NULL
, NULL
,
15465 /* 84 */ NULL
, NULL
, NULL
, NULL
,
15466 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
15467 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
15468 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
15469 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
15470 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
15471 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
15472 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
15473 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
15474 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
15475 /* AC */ NULL
, NULL
, "pfacc", NULL
,
15476 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
15477 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
15478 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
15479 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
15480 /* C0 */ NULL
, NULL
, NULL
, NULL
,
15481 /* C4 */ NULL
, NULL
, NULL
, NULL
,
15482 /* C8 */ NULL
, NULL
, NULL
, NULL
,
15483 /* CC */ NULL
, NULL
, NULL
, NULL
,
15484 /* D0 */ NULL
, NULL
, NULL
, NULL
,
15485 /* D4 */ NULL
, NULL
, NULL
, NULL
,
15486 /* D8 */ NULL
, NULL
, NULL
, NULL
,
15487 /* DC */ NULL
, NULL
, NULL
, NULL
,
15488 /* E0 */ NULL
, NULL
, NULL
, NULL
,
15489 /* E4 */ NULL
, NULL
, NULL
, NULL
,
15490 /* E8 */ NULL
, NULL
, NULL
, NULL
,
15491 /* EC */ NULL
, NULL
, NULL
, NULL
,
15492 /* F0 */ NULL
, NULL
, NULL
, NULL
,
15493 /* F4 */ NULL
, NULL
, NULL
, NULL
,
15494 /* F8 */ NULL
, NULL
, NULL
, NULL
,
15495 /* FC */ NULL
, NULL
, NULL
, NULL
,
15499 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15501 const char *mnemonic
;
15503 FETCH_DATA (the_info
, codep
+ 1);
15504 /* AMD 3DNow! instructions are specified by an opcode suffix in the
15505 place where an 8-bit immediate would normally go. ie. the last
15506 byte of the instruction. */
15507 obufp
= mnemonicendp
;
15508 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
15510 oappend (mnemonic
);
15513 /* Since a variable sized modrm/sib chunk is between the start
15514 of the opcode (0x0f0f) and the opcode suffix, we need to do
15515 all the modrm processing first, and don't know until now that
15516 we have a bad opcode. This necessitates some cleaning up. */
15517 op_out
[0][0] = '\0';
15518 op_out
[1][0] = '\0';
15521 mnemonicendp
= obufp
;
15524 static struct op simd_cmp_op
[] =
15526 { STRING_COMMA_LEN ("eq") },
15527 { STRING_COMMA_LEN ("lt") },
15528 { STRING_COMMA_LEN ("le") },
15529 { STRING_COMMA_LEN ("unord") },
15530 { STRING_COMMA_LEN ("neq") },
15531 { STRING_COMMA_LEN ("nlt") },
15532 { STRING_COMMA_LEN ("nle") },
15533 { STRING_COMMA_LEN ("ord") }
15537 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15539 unsigned int cmp_type
;
15541 FETCH_DATA (the_info
, codep
+ 1);
15542 cmp_type
= *codep
++ & 0xff;
15543 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
15546 char *p
= mnemonicendp
- 2;
15550 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
15551 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
15555 /* We have a reserved extension byte. Output it directly. */
15556 scratchbuf
[0] = '$';
15557 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
15558 oappend_maybe_intel (scratchbuf
);
15559 scratchbuf
[0] = '\0';
15564 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED
,
15565 int sizeflag ATTRIBUTE_UNUSED
)
15567 /* mwaitx %eax,%ecx,%ebx */
15570 const char **names
= (address_mode
== mode_64bit
15571 ? names64
: names32
);
15572 strcpy (op_out
[0], names
[0]);
15573 strcpy (op_out
[1], names
[1]);
15574 strcpy (op_out
[2], names
[3]);
15575 two_source_ops
= 1;
15577 /* Skip mod/rm byte. */
15583 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
15584 int sizeflag ATTRIBUTE_UNUSED
)
15586 /* mwait %eax,%ecx */
15589 const char **names
= (address_mode
== mode_64bit
15590 ? names64
: names32
);
15591 strcpy (op_out
[0], names
[0]);
15592 strcpy (op_out
[1], names
[1]);
15593 two_source_ops
= 1;
15595 /* Skip mod/rm byte. */
15601 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
15602 int sizeflag ATTRIBUTE_UNUSED
)
15604 /* monitor %eax,%ecx,%edx" */
15607 const char **op1_names
;
15608 const char **names
= (address_mode
== mode_64bit
15609 ? names64
: names32
);
15611 if (!(prefixes
& PREFIX_ADDR
))
15612 op1_names
= (address_mode
== mode_16bit
15613 ? names16
: names
);
15616 /* Remove "addr16/addr32". */
15617 all_prefixes
[last_addr_prefix
] = 0;
15618 op1_names
= (address_mode
!= mode_32bit
15619 ? names32
: names16
);
15620 used_prefixes
|= PREFIX_ADDR
;
15622 strcpy (op_out
[0], op1_names
[0]);
15623 strcpy (op_out
[1], names
[1]);
15624 strcpy (op_out
[2], names
[2]);
15625 two_source_ops
= 1;
15627 /* Skip mod/rm byte. */
15635 /* Throw away prefixes and 1st. opcode byte. */
15636 codep
= insn_codep
+ 1;
15641 REP_Fixup (int bytemode
, int sizeflag
)
15643 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15645 if (prefixes
& PREFIX_REPZ
)
15646 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
15653 OP_IMREG (bytemode
, sizeflag
);
15656 OP_ESreg (bytemode
, sizeflag
);
15659 OP_DSreg (bytemode
, sizeflag
);
15667 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15671 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15673 if (prefixes
& PREFIX_REPNZ
)
15674 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
15677 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15681 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
15682 int sizeflag ATTRIBUTE_UNUSED
)
15684 if (active_seg_prefix
== PREFIX_DS
15685 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
15687 /* NOTRACK prefix is only valid on indirect branch instructions.
15688 NB: DATA prefix is unsupported for Intel64. */
15689 active_seg_prefix
= 0;
15690 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
15694 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15695 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15699 HLE_Fixup1 (int bytemode
, int sizeflag
)
15702 && (prefixes
& PREFIX_LOCK
) != 0)
15704 if (prefixes
& PREFIX_REPZ
)
15705 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15706 if (prefixes
& PREFIX_REPNZ
)
15707 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15710 OP_E (bytemode
, sizeflag
);
15713 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15714 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
15718 HLE_Fixup2 (int bytemode
, int sizeflag
)
15720 if (modrm
.mod
!= 3)
15722 if (prefixes
& PREFIX_REPZ
)
15723 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15724 if (prefixes
& PREFIX_REPNZ
)
15725 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15728 OP_E (bytemode
, sizeflag
);
15731 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
15732 "xrelease" for memory operand. No check for LOCK prefix. */
15735 HLE_Fixup3 (int bytemode
, int sizeflag
)
15738 && last_repz_prefix
> last_repnz_prefix
15739 && (prefixes
& PREFIX_REPZ
) != 0)
15740 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15742 OP_E (bytemode
, sizeflag
);
15746 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
15751 /* Change cmpxchg8b to cmpxchg16b. */
15752 char *p
= mnemonicendp
- 2;
15753 mnemonicendp
= stpcpy (p
, "16b");
15756 else if ((prefixes
& PREFIX_LOCK
) != 0)
15758 if (prefixes
& PREFIX_REPZ
)
15759 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15760 if (prefixes
& PREFIX_REPNZ
)
15761 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15764 OP_M (bytemode
, sizeflag
);
15768 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
15770 const char **names
;
15774 switch (vex
.length
)
15788 oappend (names
[reg
]);
15792 CRC32_Fixup (int bytemode
, int sizeflag
)
15794 /* Add proper suffix to "crc32". */
15795 char *p
= mnemonicendp
;
15814 if (sizeflag
& DFLAG
)
15818 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15822 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15829 if (modrm
.mod
== 3)
15833 /* Skip mod/rm byte. */
15838 add
= (rex
& REX_B
) ? 8 : 0;
15839 if (bytemode
== b_mode
)
15843 oappend (names8rex
[modrm
.rm
+ add
]);
15845 oappend (names8
[modrm
.rm
+ add
]);
15851 oappend (names64
[modrm
.rm
+ add
]);
15852 else if ((prefixes
& PREFIX_DATA
))
15853 oappend (names16
[modrm
.rm
+ add
]);
15855 oappend (names32
[modrm
.rm
+ add
]);
15859 OP_E (bytemode
, sizeflag
);
15863 FXSAVE_Fixup (int bytemode
, int sizeflag
)
15865 /* Add proper suffix to "fxsave" and "fxrstor". */
15869 char *p
= mnemonicendp
;
15875 OP_M (bytemode
, sizeflag
);
15879 PCMPESTR_Fixup (int bytemode
, int sizeflag
)
15881 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
15884 char *p
= mnemonicendp
;
15889 else if (sizeflag
& SUFFIX_ALWAYS
)
15896 OP_EX (bytemode
, sizeflag
);
15899 /* Display the destination register operand for instructions with
15903 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15906 const char **names
;
15914 reg
= vex
.register_specifier
;
15915 if (address_mode
!= mode_64bit
)
15917 else if (vex
.evex
&& !vex
.v
)
15920 if (bytemode
== vex_scalar_mode
)
15922 oappend (names_xmm
[reg
]);
15926 switch (vex
.length
)
15933 case vex_vsib_q_w_dq_mode
:
15934 case vex_vsib_q_w_d_mode
:
15950 names
= names_mask
;
15964 case vex_vsib_q_w_dq_mode
:
15965 case vex_vsib_q_w_d_mode
:
15966 names
= vex
.w
? names_ymm
: names_xmm
;
15975 names
= names_mask
;
15978 /* See PR binutils/20893 for a reproducer. */
15990 oappend (names
[reg
]);
15993 /* Get the VEX immediate byte without moving codep. */
15995 static unsigned char
15996 get_vex_imm8 (int sizeflag
, int opnum
)
15998 int bytes_before_imm
= 0;
16000 if (modrm
.mod
!= 3)
16002 /* There are SIB/displacement bytes. */
16003 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
16005 /* 32/64 bit address mode */
16006 int base
= modrm
.rm
;
16008 /* Check SIB byte. */
16011 FETCH_DATA (the_info
, codep
+ 1);
16013 /* When decoding the third source, don't increase
16014 bytes_before_imm as this has already been incremented
16015 by one in OP_E_memory while decoding the second
16018 bytes_before_imm
++;
16021 /* Don't increase bytes_before_imm when decoding the third source,
16022 it has already been incremented by OP_E_memory while decoding
16023 the second source operand. */
16029 /* When modrm.rm == 5 or modrm.rm == 4 and base in
16030 SIB == 5, there is a 4 byte displacement. */
16032 /* No displacement. */
16034 /* Fall through. */
16036 /* 4 byte displacement. */
16037 bytes_before_imm
+= 4;
16040 /* 1 byte displacement. */
16041 bytes_before_imm
++;
16048 /* 16 bit address mode */
16049 /* Don't increase bytes_before_imm when decoding the third source,
16050 it has already been incremented by OP_E_memory while decoding
16051 the second source operand. */
16057 /* When modrm.rm == 6, there is a 2 byte displacement. */
16059 /* No displacement. */
16061 /* Fall through. */
16063 /* 2 byte displacement. */
16064 bytes_before_imm
+= 2;
16067 /* 1 byte displacement: when decoding the third source,
16068 don't increase bytes_before_imm as this has already
16069 been incremented by one in OP_E_memory while decoding
16070 the second source operand. */
16072 bytes_before_imm
++;
16080 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
16081 return codep
[bytes_before_imm
];
16085 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
16087 const char **names
;
16089 if (reg
== -1 && modrm
.mod
!= 3)
16091 OP_E_memory (bytemode
, sizeflag
);
16103 if (address_mode
!= mode_64bit
)
16107 switch (vex
.length
)
16118 oappend (names
[reg
]);
16122 OP_EX_VexImmW (int bytemode
, int sizeflag
)
16125 static unsigned char vex_imm8
;
16127 if (vex_w_done
== 0)
16131 /* Skip mod/rm byte. */
16135 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
16138 reg
= vex_imm8
>> 4;
16140 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16142 else if (vex_w_done
== 1)
16147 reg
= vex_imm8
>> 4;
16149 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16153 /* Output the imm8 directly. */
16154 scratchbuf
[0] = '$';
16155 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
16156 oappend_maybe_intel (scratchbuf
);
16157 scratchbuf
[0] = '\0';
16163 OP_Vex_2src (int bytemode
, int sizeflag
)
16165 if (modrm
.mod
== 3)
16167 int reg
= modrm
.rm
;
16171 oappend (names_xmm
[reg
]);
16176 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16178 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16179 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16181 OP_E (bytemode
, sizeflag
);
16186 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
16188 if (modrm
.mod
== 3)
16190 /* Skip mod/rm byte. */
16197 unsigned int reg
= vex
.register_specifier
;
16199 if (address_mode
!= mode_64bit
)
16201 oappend (names_xmm
[reg
]);
16204 OP_Vex_2src (bytemode
, sizeflag
);
16208 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
16211 OP_Vex_2src (bytemode
, sizeflag
);
16214 unsigned int reg
= vex
.register_specifier
;
16216 if (address_mode
!= mode_64bit
)
16218 oappend (names_xmm
[reg
]);
16223 OP_EX_VexW (int bytemode
, int sizeflag
)
16229 /* Skip mod/rm byte. */
16234 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
16239 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
16242 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16250 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16253 const char **names
;
16255 FETCH_DATA (the_info
, codep
+ 1);
16258 if (bytemode
!= x_mode
)
16262 if (address_mode
!= mode_64bit
)
16265 switch (vex
.length
)
16276 oappend (names
[reg
]);
16280 OP_XMM_VexW (int bytemode
, int sizeflag
)
16282 /* Turn off the REX.W bit since it is used for swapping operands
16285 OP_XMM (bytemode
, sizeflag
);
16289 OP_EX_Vex (int bytemode
, int sizeflag
)
16291 if (modrm
.mod
!= 3)
16293 if (vex
.register_specifier
!= 0)
16297 OP_EX (bytemode
, sizeflag
);
16301 OP_XMM_Vex (int bytemode
, int sizeflag
)
16303 if (modrm
.mod
!= 3)
16305 if (vex
.register_specifier
!= 0)
16309 OP_XMM (bytemode
, sizeflag
);
16312 static struct op vex_cmp_op
[] =
16314 { STRING_COMMA_LEN ("eq") },
16315 { STRING_COMMA_LEN ("lt") },
16316 { STRING_COMMA_LEN ("le") },
16317 { STRING_COMMA_LEN ("unord") },
16318 { STRING_COMMA_LEN ("neq") },
16319 { STRING_COMMA_LEN ("nlt") },
16320 { STRING_COMMA_LEN ("nle") },
16321 { STRING_COMMA_LEN ("ord") },
16322 { STRING_COMMA_LEN ("eq_uq") },
16323 { STRING_COMMA_LEN ("nge") },
16324 { STRING_COMMA_LEN ("ngt") },
16325 { STRING_COMMA_LEN ("false") },
16326 { STRING_COMMA_LEN ("neq_oq") },
16327 { STRING_COMMA_LEN ("ge") },
16328 { STRING_COMMA_LEN ("gt") },
16329 { STRING_COMMA_LEN ("true") },
16330 { STRING_COMMA_LEN ("eq_os") },
16331 { STRING_COMMA_LEN ("lt_oq") },
16332 { STRING_COMMA_LEN ("le_oq") },
16333 { STRING_COMMA_LEN ("unord_s") },
16334 { STRING_COMMA_LEN ("neq_us") },
16335 { STRING_COMMA_LEN ("nlt_uq") },
16336 { STRING_COMMA_LEN ("nle_uq") },
16337 { STRING_COMMA_LEN ("ord_s") },
16338 { STRING_COMMA_LEN ("eq_us") },
16339 { STRING_COMMA_LEN ("nge_uq") },
16340 { STRING_COMMA_LEN ("ngt_uq") },
16341 { STRING_COMMA_LEN ("false_os") },
16342 { STRING_COMMA_LEN ("neq_os") },
16343 { STRING_COMMA_LEN ("ge_oq") },
16344 { STRING_COMMA_LEN ("gt_oq") },
16345 { STRING_COMMA_LEN ("true_us") },
16349 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16351 unsigned int cmp_type
;
16353 FETCH_DATA (the_info
, codep
+ 1);
16354 cmp_type
= *codep
++ & 0xff;
16355 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
16358 char *p
= mnemonicendp
- 2;
16362 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
16363 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
16367 /* We have a reserved extension byte. Output it directly. */
16368 scratchbuf
[0] = '$';
16369 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16370 oappend_maybe_intel (scratchbuf
);
16371 scratchbuf
[0] = '\0';
16376 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16377 int sizeflag ATTRIBUTE_UNUSED
)
16379 unsigned int cmp_type
;
16384 FETCH_DATA (the_info
, codep
+ 1);
16385 cmp_type
= *codep
++ & 0xff;
16386 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16387 If it's the case, print suffix, otherwise - print the immediate. */
16388 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
16393 char *p
= mnemonicendp
- 2;
16395 /* vpcmp* can have both one- and two-lettered suffix. */
16409 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16410 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16414 /* We have a reserved extension byte. Output it directly. */
16415 scratchbuf
[0] = '$';
16416 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16417 oappend_maybe_intel (scratchbuf
);
16418 scratchbuf
[0] = '\0';
16422 static const struct op xop_cmp_op
[] =
16424 { STRING_COMMA_LEN ("lt") },
16425 { STRING_COMMA_LEN ("le") },
16426 { STRING_COMMA_LEN ("gt") },
16427 { STRING_COMMA_LEN ("ge") },
16428 { STRING_COMMA_LEN ("eq") },
16429 { STRING_COMMA_LEN ("neq") },
16430 { STRING_COMMA_LEN ("false") },
16431 { STRING_COMMA_LEN ("true") }
16435 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16436 int sizeflag ATTRIBUTE_UNUSED
)
16438 unsigned int cmp_type
;
16440 FETCH_DATA (the_info
, codep
+ 1);
16441 cmp_type
= *codep
++ & 0xff;
16442 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
16445 char *p
= mnemonicendp
- 2;
16447 /* vpcom* can have both one- and two-lettered suffix. */
16461 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
16462 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
16466 /* We have a reserved extension byte. Output it directly. */
16467 scratchbuf
[0] = '$';
16468 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16469 oappend_maybe_intel (scratchbuf
);
16470 scratchbuf
[0] = '\0';
16474 static const struct op pclmul_op
[] =
16476 { STRING_COMMA_LEN ("lql") },
16477 { STRING_COMMA_LEN ("hql") },
16478 { STRING_COMMA_LEN ("lqh") },
16479 { STRING_COMMA_LEN ("hqh") }
16483 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16484 int sizeflag ATTRIBUTE_UNUSED
)
16486 unsigned int pclmul_type
;
16488 FETCH_DATA (the_info
, codep
+ 1);
16489 pclmul_type
= *codep
++ & 0xff;
16490 switch (pclmul_type
)
16501 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
16504 char *p
= mnemonicendp
- 3;
16509 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
16510 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
16514 /* We have a reserved extension byte. Output it directly. */
16515 scratchbuf
[0] = '$';
16516 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
16517 oappend_maybe_intel (scratchbuf
);
16518 scratchbuf
[0] = '\0';
16523 MOVBE_Fixup (int bytemode
, int sizeflag
)
16525 /* Add proper suffix to "movbe". */
16526 char *p
= mnemonicendp
;
16535 if (sizeflag
& SUFFIX_ALWAYS
)
16541 if (sizeflag
& DFLAG
)
16545 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16550 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16557 OP_M (bytemode
, sizeflag
);
16561 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16564 const char **names
;
16566 /* Skip mod/rm byte. */
16580 oappend (names
[reg
]);
16584 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16586 const char **names
;
16587 unsigned int reg
= vex
.register_specifier
;
16594 if (address_mode
!= mode_64bit
)
16596 oappend (names
[reg
]);
16600 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16603 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
16607 if ((rex
& REX_R
) != 0 || !vex
.r
)
16613 oappend (names_mask
[modrm
.reg
]);
16617 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16620 || (bytemode
!= evex_rounding_mode
16621 && bytemode
!= evex_rounding_64_mode
16622 && bytemode
!= evex_sae_mode
))
16624 if (modrm
.mod
== 3 && vex
.b
)
16627 case evex_rounding_64_mode
:
16628 if (address_mode
!= mode_64bit
)
16633 /* Fall through. */
16634 case evex_rounding_mode
:
16635 oappend (names_rounding
[vex
.ll
]);
16637 case evex_sae_mode
: